From d29f7b983736a516068823674e6733c84b3fa95c Mon Sep 17 00:00:00 2001
From: Alexandre Dumont aka Adlx <adumont@users.noreply.github.com>
Date: Mon, 29 Jun 2020 00:42:06 +0200
Subject: [PATCH] Tipo missing * in Global Clock example

---
 docs/source/verilog.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/source/verilog.rst b/docs/source/verilog.rst
index f43f71f..474514e 100644
--- a/docs/source/verilog.rst
+++ b/docs/source/verilog.rst
@@ -211,7 +211,7 @@ To use ``(* gclk *)``, define a register with that attribute, as in:
 
 .. code-block:: systemverilog
 
-    (* gclk ) reg formal_timestep;
+    (* gclk *) reg formal_timestep;
 
 You can then reference this ``formal_timestep`` in the clocking section
 of an always block, as in,