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Change stage 3 assertion

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Gus Smith 2026-01-21 08:20:24 -08:00
parent 5e6e984a67
commit 501a054731
1 changed files with 4 additions and 8 deletions
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12
tests/staged_sim_and_verif/Req_Ack.sv
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@ -67,14 +67,10 @@ module DUT (
phase3a_cover_ack: cover(ack);
end
// Assert the third ack arrives within a bounded window after beginning
// phase 3, and furthermore after that point no further acks arrive.
property p_acks_seen_hits_3_and_stays;
@(posedge clk) ##[0:8] $rose(acks_seen == 3) ##1 (acks_seen == 3)[*0:$];
endproperty
phase3b_acks_seen_hits_3_and_stays: assert property (p_acks_seen_hits_3_and_stays);
// In phase 3b, assert that once we've seen 3 acks, we stay at 3 acks.
phase3b_acks_remains_3: assert property (
@(posedge clk) $rose(acks_seen == 3) |-> (acks_seen == 3)[*1:$]
);
`endif