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Rename "abc_bmc3" engine to "abc bmc3"
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parent
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commit
4f97a20acd
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@ -7,7 +7,7 @@ depth 10
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smtbmc -s yices
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smtbmc -s yices
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smtbmc -s boolector
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smtbmc -s boolector
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smtbmc -s z3 --nomem
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smtbmc -s z3 --nomem
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abc_bmc3
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abc bmc3
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[script]
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[script]
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read_verilog -formal -norestrict -assume-asserts picorv32.v
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read_verilog -formal -norestrict -assume-asserts picorv32.v
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@ -78,7 +78,9 @@ def run_smtbmc(job, engine_idx, engine):
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job.engine_tasks.append(task)
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job.engine_tasks.append(task)
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def run_abc_bmc3(job, engine_idx, engine):
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def run_abc(job, engine_idx, engine):
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assert engine == ["abc", "bmc3"]
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task = SbyTask(job, "engine_%d" % engine_idx, job.model("aig"),
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task = SbyTask(job, "engine_%d" % engine_idx, job.model("aig"),
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("cd %s; yosys-abc -c 'read_aiger model/design_aiger.aig; fold; strash; bmc3 -F %d -v; " +
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("cd %s; yosys-abc -c 'read_aiger model/design_aiger.aig; fold; strash; bmc3 -F %d -v; " +
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"undc -c; write_cex -a engine_%d/trace.aiw'") % (job.workdir, job.opt_depth, engine_idx),
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"undc -c; write_cex -a engine_%d/trace.aiw'") % (job.workdir, job.opt_depth, engine_idx),
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@ -159,8 +161,8 @@ def run(job):
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if engine[0] == "smtbmc":
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if engine[0] == "smtbmc":
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run_smtbmc(job, engine_idx, engine)
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run_smtbmc(job, engine_idx, engine)
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elif engine[0] == "abc_bmc3":
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elif engine[0] == "abc":
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run_abc_bmc3(job, engine_idx, engine)
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run_abc(job, engine_idx, engine)
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else:
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else:
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assert False
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assert False
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