diff --git a/tests/staged_sim_and_verif/skip_staged_flow.sby b/tests/staged_sim_and_verif/skip_staged_flow.sby
index 03f7001..9fef0fc 100644
--- a/tests/staged_sim_and_verif/skip_staged_flow.sby
+++ b/tests/staged_sim_and_verif/skip_staged_flow.sby
@@ -23,6 +23,7 @@ fv: smtbmc
 stage_1_init:
 verific -formal Req_Ack.sv
 hierarchy -top DUT
+prep
 
 stage_1_fv:
 read_rtlil design_prep.il