Use the test Makefile for all examples

* Rename and move sbysrc/demo[123].sby to docs/examples/demos
    * Make them use multiple tasks for multiple engines
* Scan docs/examples for sby files for make test
* `make ci` is now `NOSKIP` by default
* Skip scripts using `verific` w/o yosys verific support
    * This does not fail even with NOSKIP set

docs/examples/demos/memory.sby

@@ -0,0 +1,53 @@
+[options]
+depth 10
+mode bmc
+
+[engines]
+smtbmc yices
+
+[script]
+read_verilog -formal demo.v
+prep -top top
+
+[file demo.v]
+module top (
+  input clk,
+  input [7:0] addr,
+  input [7:0] wdata,
+  output [7:0] rdata
+);
+  rand const reg [7:0] test_addr;
+  reg [7:0] test_data;
+  reg test_valid = 0;
+
+  always @(posedge clk) begin
+    if (addr == test_addr) begin
+      if (test_valid)
+        assert(test_data == rdata);
+      test_data <= wdata;
+      test_valid <= 1;
+    end
+  end
+
+  memory uut (
+    .clk  (clk  ),
+    .addr (addr ),
+    .wdata(wdata),
+    .rdata(rdata)
+  );
+endmodule
+
+
+module memory (
+  input clk,
+  input [7:0] addr,
+  input [7:0] wdata,
+  output [7:0] rdata
+);
+  reg [7:0] mem [0:255];
+
+  always @(posedge clk)
+    mem[addr] <= wdata;
+
+  assign rdata = mem[addr];
+endmodule