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Add [script] documentation, add some paragraphs on "verific" command

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf 2018-04-18 19:32:58 +02:00
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docs/source/verific.rst
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@ -2,15 +2,15 @@
SystemVerilog, VHDL, SVA
========================
TBD
Run ``verific -sv <files>`` in the ``[script]`` section of you ``.sby`` file
to read a SystemVerilog source file, and ``verific -vhdl <files>`` to read a
VHDL source file.
``verific -sv <files>``
After all source files have been read, run ``verific -import <topmodule>``
to import the design elaborated at the specified top module.
``verific -vhdl <files>``
``verific -import <top>``
TBD
Run ``yosys -h verific`` in a terminal window and enter for more information
on the ``verific`` script command.
Supported SVA Property Syntax
-----------------------------