mirrors/sby
3
0
Fork 0
mirror of https://github.com/YosysHQ/sby.git synced 2025-04-06 14:24:08 +00:00
Code Activity

Fixed bug in examples/quickstart/demo.sv

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-07-26 14:19:04 +02:00
parent 07d124084c
commit 2fef25f93d
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
docs/examples/quickstart/demo.sv
View file

@ -5,7 +5,7 @@ module demo (
reg [5:0] counter = 0; reg [5:0] counter = 0;
always @(posedge clk) begin always @(posedge clk) begin
if (counter == 50) if (counter == 15)
counter <= 0; counter <= 0;
else else
counter <= counter + 1; counter <= counter + 1;