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Extend primegen example

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-03-07 23:10:53 +01:00
parent ec38b0b841
commit 2c13fbefe6
4 changed files with 32 additions and 3 deletions
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3
docs/examples/demos/.gitignore vendored Normal file
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@ -0,0 +1,3 @@
/fib_cover
/fib_prove
/fib_live

4
docs/examples/puzzles/.gitignore vendored
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@ -1,2 +1,4 @@
/wolf_goat_cabbage /wolf_goat_cabbage
/primegen /primegen_primegen
/primegen_primes_pass
/primegen_primes_fail

12
docs/examples/puzzles/primegen.sby
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@ -1,13 +1,21 @@
[tasks]
primegen
primes_fail
primes_pass
[options] [options]
mode cover mode cover
depth 1 depth 1
primes_fail: expect fail
[engines] [engines]
smtbmc --dumpsmt2 --stbv z3 smtbmc --dumpsmt2 --progress --stbv z3
[script] [script]
read_verilog -formal primegen.v read_verilog -formal primegen.v
prep -top primegen primes_fail: chparam -set offset 7 primes
primegen: prep -top primegen
~primegen: prep -top primes
[files] [files]
primegen.v primegen.v

16
docs/examples/puzzles/primegen.v
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@ -9,3 +9,19 @@ module primegen;
cover(1); cover(1);
end end
endmodule endmodule
module primes;
parameter [8:0] offset = 500;
wire [8:0] prime1 = $anyconst;
wire [9:0] prime2 = prime1 + offset;
wire [4:0] factor = $allconst;
always @* begin
if (1 < factor && factor < prime1)
assume((prime1 % factor) != 0);
if (1 < factor && factor < prime2)
assume((prime2 % factor) != 0);
assume(1 < prime1);
cover(1);
end
endmodule