From f62d5b01ea73a81dbe988a00267b2331dfe30243 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 15 Jan 2025 20:33:54 -0800 Subject: [PATCH] add link to https://forum.libre-chip.org/t/idea-for-maybe-allowing-much-wider-fetch-rename-etc-widths-in-a-cpu/33 --- src/first_arch/index.md | 1 + 1 file changed, 1 insertion(+) diff --git a/src/first_arch/index.md b/src/first_arch/index.md index 3501a70..9ca3f99 100644 --- a/src/first_arch/index.md +++ b/src/first_arch/index.md @@ -11,6 +11,7 @@ Possible follow-on work, order TBD: * Expand CPU to support more operations (e.g. floating-point, vector ops., paging) * Add FPGA-style programmable decoder and μOp Cache, with trap-to-software fallback for uncommon/complex ops, which allows running more ISAs such as RISC-V, older x86-32/64, more PowerISA support, and then if we can figure out the legal situation, ARM and modern x86-64. The idea is QEMU (or similar) will be compiled with a special compiler that generates both the fallback software and the bitstream for the decoder, the compiled output will be covered by QEMU's license which has some patent clauses, which hopefully helps with the legal situation. Jacob Lifshay came up with this idea [back in 2022](https://web.archive.org/web/20220612082603/https://bugs.libre-soc.org/show_bug.cgi?id=841) * Formal proof that the CPU doesn't have any spectre-style bugs even though it still is OoO superscalar with speculative execution. Jacob Lifshay came up with this idea [back in 2020](https://web.archive.org/web/20201021124234/https://bugs.libre-soc.org/show_bug.cgi?id=209) +* [Idea for much wider fetch/decode/rename width based on parallel-prefix-sum and taking more than 1 cycle per batch of renamed instructions](https://forum.libre-chip.org/t/idea-for-maybe-allowing-much-wider-fetch-rename-etc-widths-in-a-cpu/33) ## Register Renaming & Internal Registers