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link to register renaming page
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Jacob Lifshay 2024-09-13 13:42:23 -07:00
parent 3bd126fb1f
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src/first_arch/register_renaming.md
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@ -23,4 +23,4 @@ Because each Unit doesn't necessarily have enough output registers to hold all I
All Units' Output Registers are actually stored distributed in duplicated register files positioned at the beginning of every Unit's pipeline, this allows for faster reads from Units' Output Registers, as well as allowing register files to be more optimal for FPGAs since FPGAs tend to only support at most 2-port register files.
![](distributed_registers.dia.svg)
![](distributed_registers.dia.svg)