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Jacob Lifshay 2025-11-30 19:06:05 -08:00
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src/grants/cpu_with_programmable_decoder.md
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@ -8,11 +8,7 @@ Website/Wiki: <https://libre-chip.org/>
Modern computers are built on several different mutually-incompatible popular ISAs such as x86_64, PowerISA, AArch64, and RISC-V. Many of the most popular ISAs have no high-speed libre/open-source implementations, which makes them much harder to trust since you can't inspect their source-code to look for bugs or secret backdoors. Additionally, there are basically no existing modern CPUs which can run more than one of those ISAs without requiring software emulation, which is slow and can often be buggy.
To solve those issues, we are building a libre-licensed CPU with speculative out-of-order superscalar execution that will support a programmable decoder (loosely inspired by FPGAs) followed by a µOp cache so the CPU can be programmed to decode and run at full speed just about any ISA you select, by handling the most common instructions entirely in hardware, with software fallback for decoding some of the less common instructions which can still easily be executed in hardware (storing the decoded instructions in the µOp cache), and full software emulation for the remaining instructions. Additionally you can easily switch between selected ISAs by reprogramming the decoder, allowing you to e.g. run an x86_64 program alongside a RISC-V program in the same OS and quickly context-switch between them.
We are planning on building a custom compiler so the user can select an ISA and that compiler can compile the source code of QEMU to automatically generate the required bitstream for the FPGA, as well as generating the software required for decoding and/or emulating the remaining parts of the chosen ISA.
Our CPU is a continuation of the CPU from <https://nlnet.nl/project/Libre-Chip-proof/>, which we will also be extending to support more features such as memory paging, floating-point instructions, and better compatibility with the PowerISA specification.
To solve those issues, we are building a libre-licensed CPU with speculative out-of-order superscalar execution that will support a programmable decoder (loosely inspired by FPGAs) followed by a µOp cache so the CPU can be programmed to decode and run at full speed just about any ISA you select, by handling the most common instructions entirely in hardware, with software fallback for decoding some of the less common instructions which can still easily be executed in hardware (storing the decoded instructions in the µOp cache), and full software emulation for the remaining instructions.
## Relevant Previous Involvement
@ -61,6 +57,13 @@ We expect to solve 3 technical challenges:
A WIP high-level design of our CPU: <https://libre-chip.org/first_arch/index.html>
Text that was intended to be part of the Abstract, but didn't fit within the 1200 character length constraint:
Additionally you can easily switch between selected ISAs by reprogramming the decoder, allowing you to e.g. run an x86_64 program alongside a RISC-V program in the same OS and quickly context-switch between them.
We are planning on building a custom compiler so the user can select an ISA and that compiler can compile the source code of QEMU to automatically generate the required bitstream for the FPGA, as well as generating the software required for decoding and/or emulating the remaining parts of the chosen ISA.
Our CPU is a continuation of the CPU from <https://nlnet.nl/project/Libre-Chip-proof/>, which we will also be extending to support more features such as memory paging, floating-point instructions, and better compatibility with the PowerISA specification.
## Ecosystem
We are likely to work with QEMU upstream, as well as LLVM and Clang. We are already working with the FIRRTL specification GitHub repo to resolve problems we encounter, as well as with LLVM Circt, and with the Rust Language.