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add Cesar as requested in https://forum.libre-chip.org/t/starting-working-on-a-nlnet-grant-proposal/29/4
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Jacob Lifshay 2024-11-30 16:23:03 -08:00
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src/grants/nlnet-first.md
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@ -16,6 +16,11 @@ We are working towards building a high-performance superscalar CPU with speculat
* Jacob Lifshay -- Worked on designing PowerISA CPUs with Libre-SOC for 5yr, built a simple OoO Superscalar CPU simulator <https://salsa.debian.org/Kazan-team/power-cpu-sim>, built a RV32I CPU with VGA output in a few weeks that runs a 2.5D maze game <https://github.com/programmerjake/rv32>. Also is the main author of the [Fayalite](https://git.libre-chip.org/libre-chip/fayalite) HDL library
* Cesar Strauss - Contributed to the Libre-SOC project, mostly on digital
design and formal verification. Presented the talk "An introduction to
Formal Verification of Digital Circuits" on FOSDEM 2024
(<https://archive.fosdem.org/2024/schedule/event/fosdem-2024-2215-an-introduction-to-formal-verification-of-digital-circuits/>).
* Others... TODO
# Requested support