wording fixes

src/grants/nlnet-first.md

@@ -6,9 +6,9 @@ Website/Wiki: <https://libre-chip.org/>
 
 # Abstract
 
-Modern CPUs suffer from a [constant stream of new speculative-execution security flaws](https://en.wikipedia.org/wiki/Transient_execution_CPU_vulnerability#Timeline) ([Spectre](https://meltdownattack.com/)-style bugs), additionally software has to constantly add more convoluted and slow mitigations to properly enforce security boundaries, such as a WebAssembly VM needing to add code to prevent leaking data from outside the VM to whatever programs are running inside the VM, or a web browser needing to stop JavaScript code from seeing memory that it should not have access to.
+Modern CPUs suffer from a [constant stream of new speculative-execution security flaws](https://en.wikipedia.org/wiki/Transient_execution_CPU_vulnerability#Timeline) ([Spectre](https://meltdownattack.com/)-style bugs). Because of that, software has to constantly add more convoluted and slow mitigations to properly enforce security boundaries, such as a WebAssembly VM needing to add code to prevent leaking data from outside the VM to whatever programs are running inside the VM, or a web browser needing to stop JavaScript code from seeing memory that it should not have access to.
 
-To address this major category of CPU flaws, Jacob Lifshay invented a way to formally prove that a CPU with speculative execution doesn't suffer from any speculative-execution data leaks -- this should work for nearly any kind of CPU design.
+To address this major category of CPU flaws, Jacob Lifshay formulated a way to formally prove that a CPU with speculative execution doesn't suffer from any speculative-execution data leaks -- this should work for nearly any kind of CPU design.
 
 We are working towards building a high-performance superscalar CPU with speculative execution and working on proving that it doesn't suffer from any speculative-execution data leaks, thereby demonstrating that this major category of CPU flaws can be fixed once and for all without crippling CPU performance.
 
@@ -87,13 +87,13 @@ We expect to solve 2 technical challenges:
 * To create a working OoO Superscalar CPU with Speculative Execution, trying to design it such that it doesn't have any Spectre-style vulnerabilities (mostly by doing a better job of tracking any state whatsoever that has speculative modifications). The CPU probably will not yet support some of the features required for high performance (e.g. a complex cache hierarchy) and/or supporting running an operating system and/or floating-point. The plan is to add those features later if they are not completed as part of this grant.
 * To make substantial progress on creating a formal proof that the CPU doesn't have any Spectre-style vulnerabilities. This is complex enough and has enough potential problems we may run into that we may not finish by the end of this grant, and may need additional grants afterward to finish, hence why the goal is making substantial progress instead of having the proof 100% complete and working.
 
-To address this general category of CPU flaws, I (Jacob Lifshay) invented a way to formally prove that a CPU with speculative execution doesn't suffer from any speculative-execution data leaks:
+To address this general category of CPU flaws, Jacob Lifshay formulated a way to formally prove that a CPU with speculative execution doesn't suffer from any speculative-execution data leaks:
 
 1. Assume that to leak data, you must be able to observe some change in the digital signals going from/to the CPU core that depends on the results (defined to include any side-effects that change any state, such as cache state changes or branch predictor changes) of some transient instructions (instructions that were speculatively executed and then canceled).
 2. Take the concrete cycle-accurate CPU design, and construct a theoretical equivalent that has the additional feature of looking into the future to determine which instructions will be canceled and preemptively forces their results to be zeros (or any other value that doesn't depend on transient instructions' data; since we're doing math here, we don't have to limit ourselves to physically possible designs that respect time flow). The reasoning is that if all transient instructions' results are always zeros, they can't possibly be leaking any useful data, therefore the theoretical equivalent CPU design doesn't have any speculative-execution data leaks.
 3. Formally prove that all digital signals from/to the concrete CPU core always exactly match the timing and data in all respects of the theoretical equivalent CPU design. This proves that the concrete CPU core can't have any speculative-execution data leaks.
 
-It is expected that automated formal proof software (stuff like SMT solvers such as Z3) will probably be too slow to be usable for the formal correctness proof, therefore the plan is to use Fayalite to generate a translation of the CPU design to Coq or some other similar language for writing formal proofs. [Fayalite](https://git.libre-chip.org/libre-chip/fayalite) is a HDL library written in Rust that we have been developing since around April 2024 that targets the [FIRRTL](https://github.com/chipsalliance/firrtl-spec) intermediate language (used by the [Chisel](https://www.chisel-lang.org/) ecosystem for generating Verilog; firtool, the FIRRTL to Verilog translator, is part of [LLVM Circt](https://circt.llvm.org/), so is well maintained).
+It is expected that automated formal proof software (like SMT solvers such as Z3) will probably be too slow to be usable for the formal correctness proof, therefore the plan is to use Fayalite to generate a translation of the CPU design to Coq or some other similar language for writing formal proofs. [Fayalite](https://git.libre-chip.org/libre-chip/fayalite) is a HDL library written in Rust that we have been developing since around April 2024 that targets the [FIRRTL](https://github.com/chipsalliance/firrtl-spec) intermediate language (used by the [Chisel](https://www.chisel-lang.org/) ecosystem for generating Verilog; firtool, the FIRRTL to Verilog translator, is part of [LLVM Circt](https://circt.llvm.org/), so is well maintained).
 
 A WIP high-level design of our CPU: <https://libre-chip.org/first_arch/index.html>