Jacob Lifshay d4d9706798 reimplement fayalite::formal and add support to the simulator ... Add support to the simulator for running hdl asserts/assumes and being able to write to the formal global clock/reset and all any/all_const/seq that are used. This allows you to use the exact same HDL code for running a simulation and for running a formal proof.		2026-06-05 00:56:24 -07:00
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fayalite	reimplement fayalite::formal and add support to the simulator	2026-06-05 00:56:24 -07:00
fayalite-proc-macros	clean up deps and move missed deps to workspace	2024-09-25 01:22:35 -07:00
fayalite-proc-macros-impl	redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue	2026-05-03 23:23:17 -07:00
fayalite-visit-gen	format code after switching to edition 2024	2025-08-24 16:35:21 -07:00