Simulation { state: State { insns: Insns { state_layout: StateLayout { ty: TypeLayout { small_slots: StatePartLayout { len: 0, debug_data: [], .. }, big_slots: StatePartLayout { len: 4, debug_data: [ SlotDebugData { name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::i", ty: Bool, }, SlotDebugData { name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::w", ty: Bool, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: Bool, }, ], .. }, sim_only_slots: StatePartLayout { len: 0, debug_data: [], layout_data: [], .. }, }, memories: StatePartLayout { len: 0, debug_data: [], layout_data: [], .. }, }, insns: [ // at: module-XXXXXXXXXX.rs:1:1 0: Const { dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "", ty: Bool }, value: 0x0, }, 1: Const { dest: StatePartIndex(2), // (0x1) SlotDebugData { name: "", ty: Bool }, value: 0x1, }, // at: module-XXXXXXXXXX.rs:4:1 2: Copy { dest: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::w", ty: Bool }, src: StatePartIndex(2), // (0x1) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:5:1 3: BranchIfZero { target: 5, value: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::i", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:6:1 4: Copy { dest: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::w", ty: Bool }, src: StatePartIndex(3), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 5: Return, ], .. }, pc: 5, memory_write_log: [], memories: StatePart { value: [], }, small_slots: StatePart { value: [], }, big_slots: StatePart { value: [ 1, 0, 1, 0, ], }, sim_only_slots: StatePart { value: [], }, }, io: Instance { name: ::conditional_assignment_last, instantiated: Module { name: conditional_assignment_last, .. }, }, main_module: SimulationModuleState { base_targets: [ Instance { name: ::conditional_assignment_last, instantiated: Module { name: conditional_assignment_last, .. }, }.i, ], uninitialized_ios: {}, io_targets: { Instance { name: ::conditional_assignment_last, instantiated: Module { name: conditional_assignment_last, .. }, }.i, }, did_initial_settle: true, }, extern_modules: [], trace_decls: TraceModule { name: "conditional_assignment_last", children: [ TraceModuleIO { name: "i", child: TraceBool { location: TraceScalarId(0), name: "i", flow: Source, }, ty: Bool, flow: Source, }, TraceWire { name: "w", child: TraceBool { location: TraceScalarId(1), name: "w", flow: Duplex, }, ty: Bool, }, ], }, traces: [ SimTrace { id: TraceScalarId(0), kind: BigBool { index: StatePartIndex(0), }, state: 0x1, last_state: 0x0, }, SimTrace { id: TraceScalarId(1), kind: BigBool { index: StatePartIndex(1), }, state: 0x0, last_state: 0x1, }, ], trace_memories: {}, trace_writers: [ Running( VcdWriter { finished_init: true, timescale: 1 ps, .. }, ), ], clocks_triggered: [], event_queue: EventQueue(EventQueueData { instant: 2 μs, events: {}, }), waiting_sensitivity_sets_by_address: {}, waiting_sensitivity_sets_by_compiled_value: {}, .. }