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HaeckseAlex cesar postmaster programmerjake

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HaeckseAlex

cesar

postmaster

programmerjake

add #[hdl(cmp_eq)] to implement HdlPartialEq automatically

#19 by programmerjake was merged 2025-02-17 04:56:49 +00:00

master

support unknown trait bounds in type parameters

#18 by programmerjake was merged 2025-02-14 02:52:18 +00:00

master

add #[hdl] let destructuring

#17 by programmerjake was merged 2025-02-11 07:07:26 +00:00

master

sim: fix "label address not set" bug when the last Assignment is conditional

#16 by programmerjake was merged 2025-01-16 03:12:04 +00:00

master

tests/sim: add test_array_rw

#15 by programmerjake was merged 2025-01-13 06:02:20 +00:00

master

properly handle duplicate names in vcd

#14 by programmerjake was merged 2025-01-10 07:11:44 +00:00

master

fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s

#13 by programmerjake was merged 2024-12-29 09:06:59 +00:00

master

implementing handling #[cfg] and #[cfg_attr] in proc macro inputs

#12 by programmerjake was merged 2024-12-29 07:50:06 +00:00

master

Queue formal proof based on one-entry FIFO equivalence

5

#11 by cesar was merged 2024-12-29 21:05:26 +00:00

master

1 change request

make sim::Compiler not print things to stdout unless you ask for it

#10 by programmerjake was merged 2024-12-19 05:28:51 +00:00

master

sim: fix sim.write to struct

#9 by programmerjake was merged 2024-12-19 05:04:18 +00:00

master

sim: add SimValue and reading/writing more than just a scalar

#8 by programmerjake was merged 2024-12-18 10:03:36 +00:00

master

Add module exercising formal verification of memories

#7 by cesar was merged 2024-12-08 21:25:32 +00:00

master

Fix SInt::for_value not accounting for sign bit for positive values

#5 by programmerjake was merged 2024-11-27 00:38:37 +00:00

master

add a simulator

2

#3 by programmerjake was merged 2024-12-16 04:06:48 +00:00

master

Add test module exercising formal verification.

2

#2 by cesar was merged 2024-11-20 21:40:35 +00:00

master