diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs index d082187..dd5fc2e 100644 --- a/crates/fayalite/src/firrtl.rs +++ b/crates/fayalite/src/firrtl.rs @@ -2258,7 +2258,6 @@ impl<'a> Exporter<'a> { ModuleBody::Extern(ExternModuleBody { verilog_name, parameters, - simulation: _, }) => { let verilog_name = Ident(verilog_name); writeln!(body, "{indent}defname = {verilog_name}").unwrap(); diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs index 236f240..5d10b29 100644 --- a/crates/fayalite/src/int.rs +++ b/crates/fayalite/src/int.rs @@ -621,12 +621,6 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed { let bitslice = &BitSlice::::from_slice(&bytes)[..width]; bits.clone_from_bitslice(bitslice); } - fn bits_equal_bigint_wrapping(v: &BigInt, bits: &BitSlice) -> bool { - bits.iter() - .by_vals() - .enumerate() - .all(|(bit_index, bit): (usize, bool)| v.bit(bit_index as u64) == bit) - } fn bits_to_bigint(bits: &BitSlice) -> BigInt { let sign_byte = if Self::Signed::VALUE && bits.last().as_deref().copied().unwrap_or(false) { 0xFF diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs index 1fcb529..446746a 100644 --- a/crates/fayalite/src/module.rs +++ b/crates/fayalite/src/module.rs @@ -21,7 +21,6 @@ use crate::{ memory::{Mem, MemBuilder, MemBuilderTarget, PortName}, reg::Reg, reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset}, - sim::{ExternModuleSimGenerator, ExternModuleSimulation}, source_location::SourceLocation, ty::{CanonicalType, Type}, util::ScopedRef, @@ -34,7 +33,6 @@ use std::{ collections::VecDeque, convert::Infallible, fmt, - future::IntoFuture, hash::{Hash, Hasher}, iter::FusedIterator, marker::PhantomData, @@ -1083,7 +1081,6 @@ pub struct ExternModuleBody< > { pub verilog_name: Interned, pub parameters: P, - pub simulation: Option, } impl From>> for ExternModuleBody { @@ -1091,13 +1088,11 @@ impl From>> for ExternModuleBody { let ExternModuleBody { verilog_name, parameters, - simulation, } = value; let parameters = Intern::intern_owned(parameters); Self { verilog_name, parameters, - simulation, } } } @@ -1288,12 +1283,10 @@ impl fmt::Debug for DebugModuleBody { ModuleBody::Extern(ExternModuleBody { verilog_name, parameters, - simulation, }) => { debug_struct .field("verilog_name", verilog_name) - .field("parameters", parameters) - .field("simulation", simulation); + .field("parameters", parameters); } } debug_struct.finish_non_exhaustive() @@ -1768,7 +1761,6 @@ impl AssertValidityState { ModuleBody::Extern(ExternModuleBody { verilog_name: _, parameters: _, - simulation: _, }) => {} ModuleBody::Normal(NormalModuleBody { body }) => { let body = self.make_block_index(body); @@ -2116,7 +2108,6 @@ impl ModuleBuilder { ModuleKind::Extern => ModuleBody::Extern(ExternModuleBody { verilog_name: name.0, parameters: vec![], - simulation: None, }), ModuleKind::Normal => ModuleBody::Normal(NormalModuleBody { body: BuilderModuleBody { @@ -2183,7 +2174,6 @@ impl ModuleBuilder { .builder_extern_body() .verilog_name = name.intern(); } - #[track_caller] pub fn parameter(&self, name: impl AsRef, value: ExternModuleParameterValue) { let name = name.as_ref(); self.impl_ @@ -2196,7 +2186,6 @@ impl ModuleBuilder { value, }); } - #[track_caller] pub fn parameter_int(&self, name: impl AsRef, value: impl Into) { let name = name.as_ref(); let value = value.into(); @@ -2210,7 +2199,6 @@ impl ModuleBuilder { value: ExternModuleParameterValue::Integer(value), }); } - #[track_caller] pub fn parameter_str(&self, name: impl AsRef, value: impl AsRef) { let name = name.as_ref(); let value = value.as_ref(); @@ -2224,7 +2212,6 @@ impl ModuleBuilder { value: ExternModuleParameterValue::String(value.intern()), }); } - #[track_caller] pub fn parameter_raw_verilog(&self, name: impl AsRef, raw_verilog: impl AsRef) { let name = name.as_ref(); let raw_verilog = raw_verilog.as_ref(); @@ -2238,26 +2225,6 @@ impl ModuleBuilder { value: ExternModuleParameterValue::RawVerilog(raw_verilog.intern()), }); } - #[track_caller] - pub fn extern_module_simulation(&self, generator: G) { - let mut impl_ = self.impl_.borrow_mut(); - let simulation = &mut impl_.body.builder_extern_body().simulation; - if simulation.is_some() { - panic!("already added an extern module simulation"); - } - *simulation = Some(ExternModuleSimulation::new(generator)); - } - #[track_caller] - pub fn extern_module_simulation_fn< - Args: fmt::Debug + Clone + Hash + Eq + Send + Sync + 'static, - Fut: IntoFuture + 'static, - >( - &self, - args: Args, - f: fn(Args, crate::sim::ExternModuleSimulationState) -> Fut, - ) { - self.extern_module_simulation(crate::sim::SimGeneratorFn { args, f }); - } } #[track_caller] diff --git a/crates/fayalite/src/module/transform/visit.rs b/crates/fayalite/src/module/transform/visit.rs index 526a62c..662a578 100644 --- a/crates/fayalite/src/module/transform/visit.rs +++ b/crates/fayalite/src/module/transform/visit.rs @@ -31,7 +31,6 @@ use crate::{ phantom_const::PhantomConst, reg::Reg, reset::{AsyncReset, Reset, ResetType, SyncReset}, - sim::ExternModuleSimulation, source_location::SourceLocation, ty::{CanonicalType, Type}, wire::Wire, diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index 275b106..96f6dd9 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -15,15 +15,12 @@ use crate::{ ExprEnum, Flow, ToLiteralBits, }, int::{BoolOrIntType, IntType, SIntValue, UIntValue}, - intern::{ - Intern, Interned, InternedCompare, Memoize, PtrEqWithTypeId, SupportsPtrEqWithTypeId, - }, + intern::{Intern, Interned, Memoize}, memory::PortKind, module::{ - transform::deduce_resets::deduce_resets, AnnotatedModuleIO, Block, ExternModuleBody, Id, - InstantiatedModule, ModuleBody, NameId, NormalModuleBody, ScopedNameId, Stmt, StmtConnect, - StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire, - TargetInInstantiatedModule, + transform::deduce_resets::deduce_resets, AnnotatedModuleIO, Block, Id, InstantiatedModule, + ModuleBody, NameId, NormalModuleBody, ScopedNameId, Stmt, StmtConnect, StmtDeclaration, + StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire, TargetInInstantiatedModule, }, prelude::*, reset::{ResetType, ResetTypeDispatch}, @@ -54,20 +51,7 @@ use petgraph::{ }, }; use std::{ - any::Any, - borrow::Cow, - cell::RefCell, - collections::BTreeSet, - fmt, - future::{Future, IntoFuture}, - hash::Hash, - marker::PhantomData, - mem, - ops::IndexMut, - pin::Pin, - rc::Rc, - sync::Arc, - task::Poll, + borrow::Cow, collections::BTreeSet, fmt, marker::PhantomData, mem, ops::IndexMut, sync::Arc, }; mod interpreter; @@ -1633,20 +1617,12 @@ impl fmt::Debug for DebugOpaque { } } -#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)] -struct CompiledExternModule { - module_io_targets: Interned<[Target]>, - module_io: Interned<[CompiledValue]>, - simulation: ExternModuleSimulation, -} - #[derive(Debug)] pub struct Compiler { insns: Insns, original_base_module: Interned>, base_module: Interned>, modules: HashMap, - extern_modules: Vec, compiled_values: HashMap>, compiled_exprs: HashMap, CompiledExpr>, compiled_exprs_to_values: HashMap, CompiledValue>, @@ -1675,7 +1651,6 @@ impl Compiler { original_base_module, base_module, modules: HashMap::new(), - extern_modules: Vec::new(), compiled_values: HashMap::new(), compiled_exprs: HashMap::new(), compiled_exprs_to_values: HashMap::new(), @@ -4701,27 +4676,8 @@ impl Compiler { ModuleBody::Normal(NormalModuleBody { body }) => { self.compile_block(module, body, Interned::default(), &mut trace_decls); } - ModuleBody::Extern(ExternModuleBody { - verilog_name: _, - parameters: _, - simulation, - }) => { - let Some(simulation) = simulation else { - panic!( - "can't simulate extern module without extern_module_simulation: {}", - module.leaf_module().source_location() - ); - }; - self.extern_modules.push(CompiledExternModule { - module_io_targets: module - .leaf_module() - .module_io() - .iter() - .map(|v| Target::from(v.module_io)) - .collect(), - module_io, - simulation, - }); + ModuleBody::Extern(_extern_module_body) => { + todo!("simulating extern module: {:?}", module); } } let hashbrown::hash_map::Entry::Vacant(entry) = self.modules.entry(*module) else { @@ -5002,7 +4958,6 @@ impl Compiler { Compiled { insns: Insns::from(self.insns).intern_sized(), base_module, - extern_modules: Intern::intern_owned(self.extern_modules), io: Instance::new_unchecked( ScopedNameId( NameId("".intern(), Id::new()), @@ -5035,7 +4990,6 @@ struct CompiledModule { pub struct Compiled { insns: Interned>, base_module: CompiledModule, - extern_modules: Interned<[CompiledExternModule]>, io: Instance, traces: SimTraces]>>, trace_memories: Interned<[(StatePartIndex, TraceMem)]>, @@ -5050,7 +5004,6 @@ impl Compiled { let Self { insns, base_module, - extern_modules, io, traces, trace_memories, @@ -5059,7 +5012,6 @@ impl Compiled { Compiled { insns, base_module, - extern_modules, io: Instance::from_canonical(io.canonical()), traces, trace_memories, @@ -5070,7 +5022,6 @@ impl Compiled { let Compiled { insns, base_module, - extern_modules, io, traces, trace_memories, @@ -5079,7 +5030,6 @@ impl Compiled { Self { insns, base_module, - extern_modules, io: Instance::from_canonical(io.canonical()), traces, trace_memories, @@ -5904,21 +5854,12 @@ impl SimTraceKind { } } -#[derive(Clone, PartialEq, Eq, Hash)] +#[derive(Clone, PartialEq, Eq, Hash, Debug)] pub struct SimValue { ty: T, bits: BitVec, } -impl fmt::Debug for SimValue { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_struct("SimValue") - .field("ty", &self.ty) - .field("bits", &BitSliceWriteWithBase(&self.bits)) - .finish() - } -} - impl SimValue { #[track_caller] fn to_expr_impl(ty: CanonicalType, bits: &BitSlice) -> Expr { @@ -6533,85 +6474,62 @@ macro_rules! impl_to_sim_value_for_int_value { impl_to_sim_value_for_int_value!(UIntValue, UInt, UIntType); impl_to_sim_value_for_int_value!(SIntValue, SInt, SIntType); -#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)] -enum MaybeNeedsSettle { - NeedsSettle(S), - NoSettleNeeded(N), -} - -impl MaybeNeedsSettle { - fn map(self, f: impl FnOnce(T) -> U) -> MaybeNeedsSettle { - match self { - MaybeNeedsSettle::NeedsSettle(v) => MaybeNeedsSettle::NeedsSettle(f(v)), - MaybeNeedsSettle::NoSettleNeeded(v) => MaybeNeedsSettle::NoSettleNeeded(f(v)), - } - } -} - -// workaround implementing FnOnce not being stable -trait MaybeNeedsSettleFn { - type Output; - - fn call(self, arg: A) -> Self::Output; -} - -impl O, A, O> MaybeNeedsSettleFn for T { - type Output = O; - - fn call(self, arg: A) -> Self::Output { - self(arg) - } -} - -impl MaybeNeedsSettle { - fn apply_no_settle(self, arg: T) -> MaybeNeedsSettle - where - N: MaybeNeedsSettleFn, - { - match self { - MaybeNeedsSettle::NeedsSettle(v) => MaybeNeedsSettle::NeedsSettle(v), - MaybeNeedsSettle::NoSettleNeeded(v) => MaybeNeedsSettle::NoSettleNeeded(v.call(arg)), - } - } -} - -struct SimulationModuleState { - base_targets: Vec, - uninitialized_ios: HashMap>, +struct SimulationImpl { + state: interpreter::State, + io: Expr, + uninitialized_inputs: HashMap>, io_targets: HashMap>, - did_initial_settle: bool, + made_initial_step: bool, + needs_settle: bool, + trace_decls: TraceModule, + traces: SimTraces]>>, + trace_memories: HashMap, TraceMem>, + trace_writers: Vec>, + instant: SimInstant, + clocks_triggered: Interned<[StatePartIndex]>, + breakpoints: Option, } -impl fmt::Debug for SimulationModuleState { +impl fmt::Debug for SimulationImpl { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { - base_targets, - uninitialized_ios, - io_targets, - did_initial_settle, - } = self; - f.debug_struct("SimulationModuleState") - .field("base_targets", base_targets) - .field("uninitialized_ios", &SortedSetDebug(uninitialized_ios)) - .field("io_targets", &SortedSetDebug(io_targets)) - .field("did_initial_settle", did_initial_settle) - .finish() + self.debug_fmt(None, f) } } -impl SimulationModuleState { - fn new(base_targets: impl IntoIterator)>) -> Self { - let mut retval = Self { - base_targets: Vec::new(), - uninitialized_ios: HashMap::new(), - io_targets: HashMap::new(), - did_initial_settle: false, - }; - for (base_target, value) in base_targets { - retval.base_targets.push(base_target); - retval.parse_io(base_target, value); - } - retval +impl SimulationImpl { + fn debug_fmt(&self, io: Option<&dyn fmt::Debug>, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + state, + io: self_io, + uninitialized_inputs, + io_targets, + made_initial_step, + needs_settle, + trace_decls, + traces, + trace_memories, + trace_writers, + instant, + clocks_triggered, + breakpoints: _, + } = self; + f.debug_struct("Simulation") + .field("state", state) + .field("io", io.unwrap_or(self_io)) + .field( + "uninitialized_inputs", + &SortedSetDebug(uninitialized_inputs), + ) + .field("io_targets", &SortedMapDebug(io_targets)) + .field("made_initial_step", made_initial_step) + .field("needs_settle", needs_settle) + .field("trace_decls", trace_decls) + .field("traces", traces) + .field("trace_memories", trace_memories) + .field("trace_writers", trace_writers) + .field("instant", instant) + .field("clocks_triggered", clocks_triggered) + .finish_non_exhaustive() } /// returns `true` if `target` or any sub-targets are uninitialized inputs fn parse_io(&mut self, target: Target, value: CompiledValue) -> bool { @@ -6620,7 +6538,7 @@ impl SimulationModuleState { CompiledTypeLayoutBody::Scalar => match target.flow() { Flow::Source => false, Flow::Sink => { - self.uninitialized_ios.insert(target, vec![]); + self.uninitialized_inputs.insert(target, vec![]); true } Flow::Duplex => unreachable!(), @@ -6639,7 +6557,7 @@ impl SimulationModuleState { if sub_targets.is_empty() { false } else { - self.uninitialized_ios.insert(target, sub_targets); + self.uninitialized_inputs.insert(target, sub_targets); true } } @@ -6657,505 +6575,20 @@ impl SimulationModuleState { if sub_targets.is_empty() { false } else { - self.uninitialized_ios.insert(target, sub_targets); + self.uninitialized_inputs.insert(target, sub_targets); true } } } } - fn mark_target_as_initialized(&mut self, mut target: Target) { - fn remove_target_and_children( - uninitialized_ios: &mut HashMap>, - target: Target, - ) { - let Some(children) = uninitialized_ios.remove(&target) else { - return; - }; - for child in children { - remove_target_and_children(uninitialized_ios, child); - } - } - remove_target_and_children(&mut self.uninitialized_ios, target); - while let Some(target_child) = target.child() { - let parent = target_child.parent(); - for child in self - .uninitialized_ios - .get(&*parent) - .map(|v| &**v) - .unwrap_or(&[]) - { - if self.uninitialized_ios.contains_key(child) { - return; - } - } - target = *parent; - self.uninitialized_ios.remove(&target); - } - } - #[track_caller] - fn get_io( - &self, - mut target: Target, - which_module: WhichModule, - ) -> CompiledValue { - if let Some(&retval) = self.io_targets.get(&target) { - return retval; - } - loop { - target = match target { - Target::Base(_) => break, - Target::Child(child) => { - match *child.path_element() { - TargetPathElement::BundleField(_) | TargetPathElement::ArrayElement(_) => {} - TargetPathElement::DynArrayElement(_) => panic!( - "simulator read/write expression must not have dynamic array indexes" - ), - } - *child.parent() - } - }; - } - match which_module { - WhichModule::Main => panic!( - "simulator read/write expression must be \ - an array element/field of `Simulation::io()`" - ), - WhichModule::Extern { .. } => panic!( - "simulator read/write expression must be \ - one of this module's inputs/outputs or an \ - array element/field of one of this module's inputs/outputs" - ), - } - } - #[track_caller] - fn read_helper( - &self, - io: Expr, - which_module: WhichModule, - ) -> MaybeNeedsSettle> { - let Some(target) = io.target() else { - match which_module { - WhichModule::Main => panic!( - "can't read from an expression that's not a field/element of `Simulation::io()`" - ), - WhichModule::Extern { .. } => panic!( - "can't read from an expression that's not based on one of this module's inputs/outputs" - ), - } - }; - let compiled_value = self.get_io(*target, which_module); - match target.flow() { - Flow::Source => { - if !self.uninitialized_ios.is_empty() { - match which_module { - WhichModule::Main => { - panic!("can't read from an output before initializing all inputs"); - } - WhichModule::Extern { .. } => { - panic!("can't read from an input before initializing all outputs"); - } - } - } - MaybeNeedsSettle::NeedsSettle(compiled_value) - } - Flow::Sink => { - if self.uninitialized_ios.contains_key(&*target) { - match which_module { - WhichModule::Main => panic!("can't read from an uninitialized input"), - WhichModule::Extern { .. } => { - panic!("can't read from an uninitialized output"); - } - } - } - MaybeNeedsSettle::NoSettleNeeded(compiled_value) - } - Flow::Duplex => unreachable!(), - } - } - #[track_caller] - fn write_helper( - &mut self, - io: Expr, - which_module: WhichModule, - ) -> CompiledValue { - let Some(target) = io.target() else { - match which_module { - WhichModule::Main => panic!( - "can't write to an expression that's not a field/element of `Simulation::io()`" - ), - WhichModule::Extern { .. } => panic!( - "can't write to an expression that's not based on one of this module's outputs" - ), - } - }; - let compiled_value = self.get_io(*target, which_module); - match target.flow() { - Flow::Source => match which_module { - WhichModule::Main => panic!("can't write to an output"), - WhichModule::Extern { .. } => panic!("can't write to an input"), - }, - Flow::Sink => {} - Flow::Duplex => unreachable!(), - } - if !self.did_initial_settle { - self.mark_target_as_initialized(*target); - } - compiled_value - } -} - -#[derive(Copy, Clone, Debug)] -enum WaitTarget { - Settle, - Instant(SimInstant), - Change { key: ChangeKey, value: ChangeValue }, -} - -#[derive(Clone)] -struct EarliestWaitTargets { - settle: bool, - instant: Option, - changes: HashMap, SimValue>, -} - -impl fmt::Debug for EarliestWaitTargets { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_set().entries(self.iter()).finish() - } -} - -impl Default for EarliestWaitTargets { - fn default() -> Self { - Self { - settle: false, - instant: None, - changes: HashMap::new(), - } - } -} - -impl EarliestWaitTargets { - fn settle() -> Self { - Self { - settle: true, - instant: None, - changes: HashMap::new(), - } - } - fn instant(instant: SimInstant) -> Self { - Self { - settle: false, - instant: Some(instant), - changes: HashMap::new(), - } - } - fn len(&self) -> usize { - self.settle as usize + self.instant.is_some() as usize + self.changes.len() - } - fn is_empty(&self) -> bool { - self.len() == 0 - } - fn clear(&mut self) { - let Self { - settle, - instant, - changes, - } = self; - *settle = false; - *instant = None; - changes.clear(); - } - fn insert( - &mut self, - value: impl std::borrow::Borrow, ChangeValue>>, - ) where - ChangeValue: std::borrow::Borrow>, - { - let value = value.borrow(); - match value { - WaitTarget::Settle => self.settle = true, - WaitTarget::Instant(instant) => { - if self.instant.is_none_or(|v| v > *instant) { - self.instant = Some(*instant); - } - } - WaitTarget::Change { key, value } => { - self.changes - .entry(*key) - .or_insert_with(|| value.borrow().clone()); - } - } - } - fn convert_earlier_instants_to_settle(&mut self, instant: SimInstant) { - if self.instant.is_some_and(|v| v <= instant) { - self.settle = true; - self.instant = None; - } - } - fn iter<'a>( - &'a self, - ) -> impl Clone - + Iterator, &'a SimValue>> - + 'a { - self.settle - .then_some(WaitTarget::Settle) - .into_iter() - .chain(self.instant.map(|instant| WaitTarget::Instant(instant))) - .chain( - self.changes - .iter() - .map(|(&key, value)| WaitTarget::Change { key, value }), - ) - } -} - -impl>> - Extend, ChangeValue>> for EarliestWaitTargets -{ - fn extend, ChangeValue>>>( - &mut self, - iter: T, - ) { - iter.into_iter().for_each(|v| self.insert(v)) - } -} - -impl<'a, ChangeValue: std::borrow::Borrow>> - Extend<&'a WaitTarget, ChangeValue>> for EarliestWaitTargets -{ - fn extend, ChangeValue>>>( - &mut self, - iter: T, - ) { - iter.into_iter().for_each(|v| self.insert(v)) - } -} - -impl FromIterator for EarliestWaitTargets -where - Self: Extend, -{ - fn from_iter>(iter: T) -> Self { - let mut retval = Self::default(); - retval.extend(iter); - retval - } -} - -struct SimulationExternModuleState { - module_state: SimulationModuleState, - sim: ExternModuleSimulation, - running_generator: Option + 'static>>>, - wait_targets: EarliestWaitTargets, -} - -impl fmt::Debug for SimulationExternModuleState { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { - module_state, - sim, - running_generator, - wait_targets, - } = self; - f.debug_struct("SimulationExternModuleState") - .field("module_state", module_state) - .field("sim", sim) - .field( - "running_generator", - &running_generator.as_ref().map(|_| DebugAsDisplay("...")), - ) - .field("wait_targets", wait_targets) - .finish() - } -} - -#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)] -enum WhichModule { - Main, - Extern { module_index: usize }, -} - -struct ReadBitFn { - compiled_value: CompiledValue, -} - -impl MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadBitFn { - type Output = bool; - - fn call(self, state: &mut interpreter::State) -> Self::Output { - match self.compiled_value.range.len() { - TypeLen::A_SMALL_SLOT => { - state.small_slots[self.compiled_value.range.small_slots.start] != 0 - } - TypeLen::A_BIG_SLOT => !state.big_slots[self.compiled_value.range.big_slots.start] - .clone() - .is_zero(), - _ => unreachable!(), - } - } -} - -struct ReadBoolOrIntFn { - compiled_value: CompiledValue, - io: Expr, -} - -impl MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadBoolOrIntFn { - type Output = I::Value; - - fn call(self, state: &mut interpreter::State) -> Self::Output { - let Self { compiled_value, io } = self; - match compiled_value.range.len() { - TypeLen::A_SMALL_SLOT => Expr::ty(io) - .value_from_int_wrapping(state.small_slots[compiled_value.range.small_slots.start]), - TypeLen::A_BIG_SLOT => Expr::ty(io).value_from_int_wrapping( - state.big_slots[compiled_value.range.big_slots.start].clone(), - ), - _ => unreachable!(), - } - } -} - -struct ReadFn { - compiled_value: CompiledValue, - io: Expr, - bits: BitVec, -} - -impl MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadFn { - type Output = SimValue; - - fn call(self, state: &mut interpreter::State) -> Self::Output { - let Self { - compiled_value, - io, - bits, - } = self; - SimulationImpl::read_no_settle_helper(state, io, compiled_value, bits) - } -} - -struct GeneratorWaker; - -impl std::task::Wake for GeneratorWaker { - fn wake(self: Arc) { - panic!("can't await other kinds of futures in function passed to ExternalModuleSimulation"); - } -} - -#[derive(Default)] -struct ReadyToRunSet { - state_ready_to_run: bool, - extern_modules_ready_to_run: Vec, -} - -impl ReadyToRunSet { - fn clear(&mut self) { - let Self { - state_ready_to_run, - extern_modules_ready_to_run, - } = self; - *state_ready_to_run = false; - extern_modules_ready_to_run.clear(); - } -} - -struct SimulationImpl { - state: interpreter::State, - io: Expr, - main_module: SimulationModuleState, - extern_modules: Box<[SimulationExternModuleState]>, - state_ready_to_run: bool, - trace_decls: TraceModule, - traces: SimTraces]>>, - trace_memories: HashMap, TraceMem>, - trace_writers: Vec>, - instant: SimInstant, - clocks_triggered: Interned<[StatePartIndex]>, - breakpoints: Option, - generator_waker: std::task::Waker, -} - -impl fmt::Debug for SimulationImpl { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - self.debug_fmt(None, f) - } -} - -impl SimulationImpl { - fn debug_fmt(&self, io: Option<&dyn fmt::Debug>, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { - state, - io: self_io, - main_module, - extern_modules, - state_ready_to_run, - trace_decls, - traces, - trace_memories, - trace_writers, - instant, - clocks_triggered, - breakpoints: _, - generator_waker: _, - } = self; - f.debug_struct("Simulation") - .field("state", state) - .field("io", io.unwrap_or(self_io)) - .field("main_module", main_module) - .field("extern_modules", extern_modules) - .field("state_ready_to_run", state_ready_to_run) - .field("trace_decls", trace_decls) - .field("traces", traces) - .field("trace_memories", trace_memories) - .field("trace_writers", trace_writers) - .field("instant", instant) - .field("clocks_triggered", clocks_triggered) - .finish_non_exhaustive() - } fn new(compiled: Compiled) -> Self { - let io_target = Target::from(compiled.io); - let extern_modules = Box::from_iter(compiled.extern_modules.iter().map( - |&CompiledExternModule { - module_io_targets, - module_io, - simulation, - }| { - SimulationExternModuleState { - module_state: SimulationModuleState::new( - module_io_targets - .iter() - .copied() - .zip(module_io.iter().copied()), - ), - sim: simulation, - running_generator: None, - wait_targets: EarliestWaitTargets::settle(), - } - }, - )); - Self { + let mut retval = Self { state: State::new(compiled.insns), io: compiled.io.to_expr(), - main_module: SimulationModuleState::new( - compiled - .io - .ty() - .fields() - .into_iter() - .zip(compiled.base_module.module_io) - .map(|(BundleField { name, .. }, value)| { - ( - io_target.join( - TargetPathElement::from(TargetPathBundleField { name }) - .intern_sized(), - ), - value, - ) - }), - ), - extern_modules, - state_ready_to_run: true, + uninitialized_inputs: HashMap::new(), + io_targets: HashMap::new(), + made_initial_step: false, + needs_settle: true, trace_decls: compiled.base_module.trace_decls, traces: SimTraces(Box::from_iter(compiled.traces.0.iter().map( |&SimTrace { @@ -7173,8 +6606,22 @@ impl SimulationImpl { instant: SimInstant::START, clocks_triggered: compiled.clocks_triggered, breakpoints: None, - generator_waker: Arc::new(GeneratorWaker).into(), + }; + let io_target = Target::from(compiled.io); + for (BundleField { name, .. }, value) in compiled + .io + .ty() + .fields() + .into_iter() + .zip(compiled.base_module.module_io) + { + retval.parse_io( + io_target + .join(TargetPathElement::from(TargetPathBundleField { name }).intern_sized()), + value, + ); } + retval } fn write_traces( &mut self, @@ -7312,120 +6759,9 @@ impl SimulationImpl { } } #[track_caller] - fn advance_time(this_ref: &Rc>, duration: SimDuration) { - let run_target = this_ref.borrow().instant + duration; - Self::run_until(this_ref, run_target); - } - /// clears `targets` - #[must_use] - fn yield_wait<'a>( - this: Rc>, - module_index: usize, - targets: &'a mut EarliestWaitTargets, - ) -> impl Future + 'a { - struct MyGenerator<'a> { - sim: Rc>, - yielded_at_all: bool, - module_index: usize, - targets: &'a mut EarliestWaitTargets, - } - impl Future for MyGenerator<'_> { - type Output = (); - - fn poll( - mut self: Pin<&mut Self>, - cx: &mut std::task::Context<'_>, - ) -> Poll { - let this = &mut *self; - let mut sim = this.sim.borrow_mut(); - let sim = &mut *sim; - assert!(cx.waker().will_wake(&sim.generator_waker), "can't use ExternModuleSimulationState's methods outside of ExternModuleSimulation"); - this.targets.convert_earlier_instants_to_settle(sim.instant); - if this.targets.is_empty() { - this.targets.settle = true; - } - if this.targets.settle { - if this.yielded_at_all { - this.targets.clear(); - return Poll::Ready(()); - } - } - sim.extern_modules[this.module_index] - .wait_targets - .extend(this.targets.iter()); - this.targets.clear(); - this.yielded_at_all = true; - Poll::Pending - } - } - MyGenerator { - sim: this, - yielded_at_all: false, - module_index, - targets, - } - } - async fn yield_advance_time_or_settle( - this: Rc>, - module_index: usize, - duration: Option, - ) { - let mut targets = duration.map_or(EarliestWaitTargets::settle(), |duration| { - EarliestWaitTargets::instant(this.borrow().instant + duration) - }); - Self::yield_wait(this, module_index, &mut targets).await; - } - fn is_extern_module_ready_to_run(&mut self, module_index: usize) -> Option { - let module = &self.extern_modules[module_index]; - let mut retval = None; - for wait_target in module.wait_targets.iter() { - retval = match (wait_target, retval) { - (WaitTarget::Settle, _) => Some(self.instant), - (WaitTarget::Instant(instant), _) if instant <= self.instant => Some(self.instant), - (WaitTarget::Instant(instant), None) => Some(instant), - (WaitTarget::Instant(instant), Some(retval)) => Some(instant.min(retval)), - (WaitTarget::Change { key, value }, retval) => { - if Self::value_changed(&mut self.state, key, &value.bits) { - Some(self.instant) - } else { - retval - } - } - }; - if retval == Some(self.instant) { - break; - } - } - retval - } - fn get_ready_to_run_set(&mut self, ready_to_run_set: &mut ReadyToRunSet) -> Option { - ready_to_run_set.clear(); - let mut retval = None; - if self.state_ready_to_run { - ready_to_run_set.state_ready_to_run = true; - retval = Some(self.instant); - } - for module_index in 0..self.extern_modules.len() { - let Some(instant) = self.is_extern_module_ready_to_run(module_index) else { - continue; - }; - if let Some(retval) = &mut retval { - match instant.cmp(retval) { - std::cmp::Ordering::Less => ready_to_run_set.clear(), - std::cmp::Ordering::Equal => {} - std::cmp::Ordering::Greater => continue, - } - } else { - retval = Some(instant); - } - ready_to_run_set - .extern_modules_ready_to_run - .push(module_index); - } - retval - } - fn set_instant_no_sim(&mut self, instant: SimInstant) { - self.instant = instant; + fn advance_time(&mut self, duration: SimDuration) { + self.settle(); + self.instant += duration; self.for_each_trace_writer_storing_error(|this, mut trace_writer_state| { match &mut trace_writer_state { TraceWriterState::Decls(_) | TraceWriterState::Init(_) => unreachable!(), @@ -7437,145 +6773,54 @@ impl SimulationImpl { Ok(trace_writer_state) }); } - #[must_use] #[track_caller] - fn run_state_settle_cycle(&mut self) -> bool { - self.state_ready_to_run = false; - self.state.setup_call(0); - if self.breakpoints.is_some() { - loop { - match self - .state - .run(self.breakpoints.as_mut().expect("just checked")) - { - RunResult::Break(break_action) => { - println!( - "hit breakpoint at:\n{:?}", - self.state.debug_insn_at(self.state.pc), - ); - match break_action { - BreakAction::DumpStateAndContinue => { - println!("{self:#?}"); - } - BreakAction::Continue => {} - } - } - RunResult::Return(()) => break, - } - } - } else { - let RunResult::Return(()) = self.state.run(()); - } - if self - .clocks_triggered - .iter() - .any(|i| self.state.small_slots[*i] != 0) - { - self.state_ready_to_run = true; - true - } else { - false - } - } - #[track_caller] - fn run_extern_modules_cycle( - this_ref: &Rc>, - generator_waker: &std::task::Waker, - extern_modules_ready_to_run: &[usize], - ) { - let mut this = this_ref.borrow_mut(); - for module_index in extern_modules_ready_to_run.iter().copied() { - let extern_module = &mut this.extern_modules[module_index]; - extern_module.wait_targets.clear(); - let mut generator = if !extern_module.module_state.did_initial_settle { - let sim = extern_module.sim; - drop(this); - Box::into_pin(sim.run(ExternModuleSimulationState { - sim_impl: this_ref.clone(), - module_index, - wait_for_changes_wait_targets: EarliestWaitTargets::default(), - })) - } else if let Some(generator) = extern_module.running_generator.take() { - drop(this); - generator - } else { - continue; - }; - let generator = match generator - .as_mut() - .poll(&mut std::task::Context::from_waker(generator_waker)) - { - Poll::Ready(()) => None, - Poll::Pending => Some(generator), - }; - this = this_ref.borrow_mut(); - this.extern_modules[module_index] - .module_state - .did_initial_settle = true; - if !this.extern_modules[module_index] - .module_state - .uninitialized_ios - .is_empty() - { - panic!( - "extern module didn't initialize all outputs before \ - waiting, settling, or reading any inputs: {}", - this.extern_modules[module_index].sim.source_location - ); - } - this.extern_modules[module_index].running_generator = generator; - } - } - /// clears `targets` - #[track_caller] - fn run_until(this_ref: &Rc>, run_target: SimInstant) { - let mut this = this_ref.borrow_mut(); - let mut ready_to_run_set = ReadyToRunSet::default(); - let generator_waker = this.generator_waker.clone(); + fn settle(&mut self) { assert!( - this.main_module.uninitialized_ios.is_empty(), + self.uninitialized_inputs.is_empty(), "didn't initialize all inputs", ); - let run_target = run_target.max(this.instant); - let mut settle_cycle = 0; - let mut run_extern_modules = true; - loop { - assert!(settle_cycle < 100000, "settle(): took too many steps"); - settle_cycle += 1; - let next_wait_target = match this.get_ready_to_run_set(&mut ready_to_run_set) { - Some(next_wait_target) if next_wait_target <= run_target => next_wait_target, - _ => break, - }; - if next_wait_target > this.instant { - settle_cycle = 0; - this.set_instant_no_sim(next_wait_target); + for _ in 0..100000 { + if !self.needs_settle { + return; } - if run_extern_modules { - drop(this); - Self::run_extern_modules_cycle( - this_ref, - &generator_waker, - &ready_to_run_set.extern_modules_ready_to_run, - ); - this = this_ref.borrow_mut(); - } - if ready_to_run_set.state_ready_to_run { - if this.run_state_settle_cycle() { - // wait for clocks to settle before running extern modules again - run_extern_modules = false; - } else { - run_extern_modules = true; + self.state.setup_call(0); + if self.breakpoints.is_some() { + loop { + match self + .state + .run(self.breakpoints.as_mut().expect("just checked")) + { + RunResult::Break(break_action) => { + println!( + "hit breakpoint at:\n{:?}", + self.state.debug_insn_at(self.state.pc), + ); + match break_action { + BreakAction::DumpStateAndContinue => { + println!("{self:#?}"); + } + BreakAction::Continue => {} + } + } + RunResult::Return(()) => break, + } } - } - if this.main_module.did_initial_settle { - this.read_traces::(); } else { - this.read_traces::(); + let RunResult::Return(()) = self.state.run(()); } - this.state.memory_write_log.sort_unstable(); - this.state.memory_write_log.dedup(); - this.main_module.did_initial_settle = true; - this.for_each_trace_writer_storing_error(|this, trace_writer_state| { + if self.made_initial_step { + self.read_traces::(); + } else { + self.read_traces::(); + } + self.state.memory_write_log.sort_unstable(); + self.state.memory_write_log.dedup(); + self.made_initial_step = true; + self.needs_settle = self + .clocks_triggered + .iter() + .any(|i| self.state.small_slots[*i] != 0); + self.for_each_trace_writer_storing_error(|this, trace_writer_state| { Ok(match trace_writer_state { TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running( this.init_trace_writer(trace_writer_decls.write_decls( @@ -7593,48 +6838,114 @@ impl SimulationImpl { TraceWriterState::Errored(e) => TraceWriterState::Errored(e), }) }); - this.state.memory_write_log.clear(); - } - if run_target > this.instant { - this.set_instant_no_sim(run_target); + self.state.memory_write_log.clear(); } + panic!("settle(): took too many steps"); } #[track_caller] - fn settle(this_ref: &Rc>) { - let run_target = this_ref.borrow().instant; - Self::run_until(this_ref, run_target); - } - fn get_module(&self, which_module: WhichModule) -> &SimulationModuleState { - match which_module { - WhichModule::Main => &self.main_module, - WhichModule::Extern { module_index } => &self.extern_modules[module_index].module_state, + fn get_io(&self, target: Target) -> CompiledValue { + if let Some(&retval) = self.io_targets.get(&target) { + return retval; } + if Some(&target) == self.io.target().as_deref() + || Some(target.base()) != self.io.target().map(|v| v.base()) + { + panic!("simulator read/write expression must be an array element/field of `Simulation::io()`"); + }; + panic!("simulator read/write expression must not have dynamic array indexes"); } - fn get_module_mut(&mut self, which_module: WhichModule) -> &mut SimulationModuleState { - match which_module { - WhichModule::Main => &mut self.main_module, - WhichModule::Extern { module_index } => { - &mut self.extern_modules[module_index].module_state + fn mark_target_as_initialized(&mut self, mut target: Target) { + fn remove_target_and_children( + uninitialized_inputs: &mut HashMap>, + target: Target, + ) { + let Some(children) = uninitialized_inputs.remove(&target) else { + return; + }; + for child in children { + remove_target_and_children(uninitialized_inputs, child); } } + remove_target_and_children(&mut self.uninitialized_inputs, target); + while let Some(target_child) = target.child() { + let parent = target_child.parent(); + for child in self + .uninitialized_inputs + .get(&*parent) + .map(|v| &**v) + .unwrap_or(&[]) + { + if self.uninitialized_inputs.contains_key(child) { + return; + } + } + target = *parent; + self.uninitialized_inputs.remove(&target); + } } #[track_caller] - fn read_bit( - &mut self, - io: Expr, - which_module: WhichModule, - ) -> MaybeNeedsSettle { - self.get_module(which_module) - .read_helper(Expr::canonical(io), which_module) - .map(|compiled_value| ReadBitFn { compiled_value }) - .apply_no_settle(&mut self.state) + fn read_helper(&mut self, io: Expr) -> CompiledValue { + let Some(target) = io.target() else { + panic!("can't read from expression that's not a field/element of `Simulation::io()`"); + }; + let compiled_value = self.get_io(*target); + if self.made_initial_step { + self.settle(); + } else { + match target.flow() { + Flow::Source => { + if !self.uninitialized_inputs.is_empty() { + panic!( + "can't read from an output before the simulation has made any steps" + ); + } + self.settle(); + } + Flow::Sink => { + if self.uninitialized_inputs.contains_key(&*target) { + panic!("can't read from an uninitialized input"); + } + } + Flow::Duplex => unreachable!(), + } + } + compiled_value } #[track_caller] - fn write_bit(&mut self, io: Expr, value: bool, which_module: WhichModule) { - let compiled_value = self - .get_module_mut(which_module) - .write_helper(io, which_module); - self.state_ready_to_run = true; + fn write_helper(&mut self, io: Expr) -> CompiledValue { + let Some(target) = io.target() else { + panic!("can't write to an expression that's not a field/element of `Simulation::io()`"); + }; + let compiled_value = self.get_io(*target); + match target.flow() { + Flow::Source => { + panic!("can't write to an output"); + } + Flow::Sink => {} + Flow::Duplex => unreachable!(), + } + if !self.made_initial_step { + self.mark_target_as_initialized(*target); + } + self.needs_settle = true; + compiled_value + } + #[track_caller] + fn read_bit(&mut self, io: Expr) -> bool { + let compiled_value = self.read_helper(Expr::canonical(io)); + match compiled_value.range.len() { + TypeLen::A_SMALL_SLOT => { + self.state.small_slots[compiled_value.range.small_slots.start] != 0 + } + TypeLen::A_BIG_SLOT => !self.state.big_slots[compiled_value.range.big_slots.start] + .clone() + .is_zero(), + _ => unreachable!(), + } + } + #[track_caller] + fn write_bit(&mut self, io: Expr, value: bool) { + let compiled_value = self.write_helper(io); match compiled_value.range.len() { TypeLen::A_SMALL_SLOT => { self.state.small_slots[compiled_value.range.small_slots.start] = value as _; @@ -7646,27 +6957,21 @@ impl SimulationImpl { } } #[track_caller] - fn read_bool_or_int( - &mut self, - io: Expr, - which_module: WhichModule, - ) -> MaybeNeedsSettle, I::Value> { - self.get_module(which_module) - .read_helper(Expr::canonical(io), which_module) - .map(|compiled_value| ReadBoolOrIntFn { compiled_value, io }) - .apply_no_settle(&mut self.state) + fn read_bool_or_int(&mut self, io: Expr) -> I::Value { + let compiled_value = self.read_helper(Expr::canonical(io)); + match compiled_value.range.len() { + TypeLen::A_SMALL_SLOT => Expr::ty(io).value_from_int_wrapping( + self.state.small_slots[compiled_value.range.small_slots.start], + ), + TypeLen::A_BIG_SLOT => Expr::ty(io).value_from_int_wrapping( + self.state.big_slots[compiled_value.range.big_slots.start].clone(), + ), + _ => unreachable!(), + } } #[track_caller] - fn write_bool_or_int( - &mut self, - io: Expr, - value: I::Value, - which_module: WhichModule, - ) { - let compiled_value = self - .get_module_mut(which_module) - .write_helper(Expr::canonical(io), which_module); - self.state_ready_to_run = true; + fn write_bool_or_int(&mut self, io: Expr, value: I::Value) { + let compiled_value = self.write_helper(Expr::canonical(io)); let value: BigInt = value.into(); match compiled_value.range.len() { TypeLen::A_SMALL_SLOT => { @@ -7683,13 +6988,12 @@ impl SimulationImpl { } } #[track_caller] - fn read_write_sim_value_helper( - state: &mut interpreter::State, + fn read_write_sim_value_helper( + &mut self, compiled_value: CompiledValue, - start_bit_index: usize, - bits: &mut Bits, - read_write_big_scalar: impl Fn(bool, std::ops::Range, &mut Bits, &mut BigInt) + Copy, - read_write_small_scalar: impl Fn(bool, std::ops::Range, &mut Bits, &mut SmallUInt) + Copy, + bits: &mut BitSlice, + read_write_big_scalar: impl Fn(bool, &mut BitSlice, &mut BigInt) + Copy, + read_write_small_scalar: impl Fn(bool, &mut BitSlice, &mut SmallUInt) + Copy, ) { match compiled_value.layout.body { CompiledTypeLayoutBody::Scalar => { @@ -7706,20 +7010,16 @@ impl SimulationImpl { CanonicalType::Clock(_) => false, CanonicalType::PhantomConst(_) => unreachable!(), }; - let bit_indexes = - start_bit_index..start_bit_index + compiled_value.layout.ty.bit_width(); match compiled_value.range.len() { TypeLen::A_SMALL_SLOT => read_write_small_scalar( signed, - bit_indexes, bits, - &mut state.small_slots[compiled_value.range.small_slots.start], + &mut self.state.small_slots[compiled_value.range.small_slots.start], ), TypeLen::A_BIG_SLOT => read_write_big_scalar( signed, - bit_indexes, bits, - &mut state.big_slots[compiled_value.range.big_slots.start], + &mut self.state.big_slots[compiled_value.range.big_slots.start], ), _ => unreachable!(), } @@ -7728,8 +7028,7 @@ impl SimulationImpl { let ty = ::from_canonical(compiled_value.layout.ty); let element_bit_width = ty.element().bit_width(); for element_index in 0..ty.len() { - Self::read_write_sim_value_helper( - state, + self.read_write_sim_value_helper( CompiledValue { layout: *element, range: compiled_value @@ -7737,8 +7036,7 @@ impl SimulationImpl { .index_array(element.layout.len(), element_index), write: None, }, - start_bit_index + element_index * element_bit_width, - bits, + &mut bits[element_index * element_bit_width..][..element_bit_width], read_write_big_scalar, read_write_small_scalar, ); @@ -7747,15 +7045,14 @@ impl SimulationImpl { CompiledTypeLayoutBody::Bundle { fields } => { let ty = Bundle::from_canonical(compiled_value.layout.ty); for ( - (_field, offset), + (field, offset), CompiledBundleField { offset: layout_offset, ty: field_layout, }, ) in ty.fields().iter().zip(ty.field_offsets()).zip(fields) { - Self::read_write_sim_value_helper( - state, + self.read_write_sim_value_helper( CompiledValue { layout: field_layout, range: compiled_value.range.slice(TypeIndexRange::new( @@ -7764,8 +7061,7 @@ impl SimulationImpl { )), write: None, }, - start_bit_index + offset, - bits, + &mut bits[offset..][..field.ty.bit_width()], read_write_big_scalar, read_write_small_scalar, ); @@ -7774,27 +7070,17 @@ impl SimulationImpl { } } #[track_caller] - fn read_no_settle_helper( - state: &mut interpreter::State, - io: Expr, - compiled_value: CompiledValue, - mut bits: BitVec, - ) -> SimValue { - bits.clear(); - bits.resize(compiled_value.layout.ty.bit_width(), false); - SimulationImpl::read_write_sim_value_helper( - state, + fn read(&mut self, io: Expr) -> SimValue { + let compiled_value = self.read_helper(io); + let mut bits = BitVec::repeat(false, compiled_value.layout.ty.bit_width()); + self.read_write_sim_value_helper( compiled_value, - 0, &mut bits, - |_signed, bit_range, bits, value| { - ::copy_bits_from_bigint_wrapping(value, &mut bits[bit_range]); - }, - |_signed, bit_range, bits, value| { + |_signed, bits, value| ::copy_bits_from_bigint_wrapping(value, bits), + |_signed, bits, value| { let bytes = value.to_le_bytes(); let bitslice = BitSlice::::from_slice(&bytes); - let bitslice = &bitslice[..bit_range.len()]; - bits[bit_range].clone_from_bitslice(bitslice); + bits.clone_from_bitslice(&bitslice[..bits.len()]); }, ); SimValue { @@ -7802,120 +7088,30 @@ impl SimulationImpl { bits, } } - /// doesn't modify `bits` - fn value_changed( - state: &mut interpreter::State, - compiled_value: CompiledValue, - mut bits: &BitSlice, - ) -> bool { - assert_eq!(bits.len(), compiled_value.layout.ty.bit_width()); - let any_change = std::cell::Cell::new(false); - SimulationImpl::read_write_sim_value_helper( - state, - compiled_value, - 0, - &mut bits, - |_signed, bit_range, bits, value| { - if !::bits_equal_bigint_wrapping(value, &bits[bit_range]) { - any_change.set(true); - } - }, - |_signed, bit_range, bits, value| { - let bytes = value.to_le_bytes(); - let bitslice = BitSlice::::from_slice(&bytes); - let bitslice = &bitslice[..bit_range.len()]; - if bits[bit_range] != *bitslice { - any_change.set(true); - } - }, - ); - any_change.get() - } #[track_caller] - fn read( - &mut self, - io: Expr, - which_module: WhichModule, - ) -> ( - CompiledValue, - MaybeNeedsSettle>, - ) { - let compiled_value = self.get_module(which_module).read_helper(io, which_module); - let value = compiled_value - .map(|compiled_value| ReadFn { - compiled_value, - io, - bits: BitVec::new(), - }) - .apply_no_settle(&mut self.state); - let (MaybeNeedsSettle::NeedsSettle(compiled_value) - | MaybeNeedsSettle::NoSettleNeeded(compiled_value)) = compiled_value; - (compiled_value, value) - } - #[track_caller] - fn write( - &mut self, - io: Expr, - value: &SimValue, - which_module: WhichModule, - ) { - let compiled_value = self - .get_module_mut(which_module) - .write_helper(io, which_module); - self.state_ready_to_run = true; + fn write(&mut self, io: Expr, value: SimValue) { + let compiled_value = self.write_helper(io); assert_eq!(Expr::ty(io), value.ty()); - Self::read_write_sim_value_helper( - &mut self.state, + self.read_write_sim_value_helper( compiled_value, - 0, - &mut value.bits(), - |signed, bit_range, bits, value| { + &mut value.into_bits(), + |signed, bits, value| { if signed { - *value = SInt::bits_to_bigint(&bits[bit_range]); + *value = SInt::bits_to_bigint(bits); } else { - *value = UInt::bits_to_bigint(&bits[bit_range]); + *value = UInt::bits_to_bigint(bits); } }, - |signed, bit_range, bits, value| { + |signed, bits, value| { let mut small_value = [0; mem::size_of::()]; - if signed && bits[bit_range.clone()].last().as_deref().copied() == Some(true) { + if signed && bits.last().as_deref().copied() == Some(true) { small_value.fill(u8::MAX); } - small_value.view_bits_mut::()[0..bit_range.len()] - .clone_from_bitslice(&bits[bit_range]); + small_value.view_bits_mut::()[0..bits.len()].clone_from_bitslice(bits); *value = SmallUInt::from_le_bytes(small_value); }, ); } - #[track_caller] - fn settle_if_needed(this_ref: &Rc>, v: MaybeNeedsSettle) -> O - where - for<'a> F: MaybeNeedsSettleFn<&'a mut interpreter::State, Output = O>, - { - match v { - MaybeNeedsSettle::NeedsSettle(v) => { - Self::settle(this_ref); - v.call(&mut this_ref.borrow_mut().state) - } - MaybeNeedsSettle::NoSettleNeeded(v) => v, - } - } - async fn yield_settle_if_needed( - this_ref: &Rc>, - module_index: usize, - v: MaybeNeedsSettle, - ) -> O - where - for<'a> F: MaybeNeedsSettleFn<&'a mut interpreter::State, Output = O>, - { - match v { - MaybeNeedsSettle::NeedsSettle(v) => { - Self::yield_advance_time_or_settle(this_ref.clone(), module_index, None).await; - v.call(&mut this_ref.borrow_mut().state) - } - MaybeNeedsSettle::NoSettleNeeded(v) => v, - } - } fn close_all_trace_writers(&mut self) -> std::io::Result<()> { let trace_writers = mem::take(&mut self.trace_writers); let mut retval = Ok(()); @@ -7985,17 +7181,17 @@ impl SimulationImpl { self.trace_writers = trace_writers; retval } - fn close(this: Rc>) -> std::io::Result<()> { - if this.borrow().main_module.did_initial_settle { - Self::settle(&this); + fn close(mut self) -> std::io::Result<()> { + if self.made_initial_step { + self.settle(); } - this.borrow_mut().close_all_trace_writers() + self.close_all_trace_writers() } - fn flush_traces(this_ref: &Rc>) -> std::io::Result<()> { - if this_ref.borrow().main_module.did_initial_settle { - Self::settle(this_ref); + fn flush_traces(&mut self) -> std::io::Result<()> { + if self.made_initial_step { + self.settle(); } - this_ref.borrow_mut().for_each_trace_writer_getting_error( + self.for_each_trace_writer_getting_error( |this, trace_writer: TraceWriterState| match trace_writer { TraceWriterState::Decls(v) => { let mut v = v.write_decls( @@ -8029,7 +7225,7 @@ impl Drop for SimulationImpl { } pub struct Simulation { - sim_impl: Rc>, + sim_impl: SimulationImpl, io: Expr, } @@ -8076,117 +7272,24 @@ impl fmt::Debug for SortedMapDebug<'_, K, V> { impl fmt::Debug for Simulation { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { let Self { sim_impl, io } = self; - sim_impl.borrow().debug_fmt(Some(io), f) + sim_impl.debug_fmt(Some(io), f) } } -macro_rules! impl_simulation_methods { - ( - async_await = ($($async:tt, $await:tt)?), - track_caller = ($(#[$track_caller:tt])?), - which_module = |$self:ident| $which_module:expr, - ) => { - $(#[$track_caller])? - pub $($async)? fn read_bool_or_int(&mut $self, io: Expr) -> I::Value { - let retval = $self - .sim_impl - .borrow_mut() - .read_bool_or_int(io, $which_module); - $self.settle_if_needed(retval)$(.$await)? - } - $(#[$track_caller])? - pub $($async)? fn write_bool_or_int( - &mut $self, - io: Expr, - value: impl ToExpr, - ) { - let value = value.to_expr(); - assert_eq!(Expr::ty(io), Expr::ty(value), "type mismatch"); - let value = value - .to_literal_bits() - .expect("the value that is being written to an input must be a literal"); - $self.sim_impl.borrow_mut().write_bool_or_int( - io, - I::bits_to_value(Cow::Borrowed(&value)), - $which_module, - ); - } - $(#[$track_caller])? - pub $($async)? fn write_clock(&mut $self, io: Expr, value: bool) { - $self.sim_impl - .borrow_mut() - .write_bit(Expr::canonical(io), value, $which_module); - } - $(#[$track_caller])? - pub $($async)? fn read_clock(&mut $self, io: Expr) -> bool { - let retval = $self - .sim_impl - .borrow_mut() - .read_bit(Expr::canonical(io), $which_module); - $self.settle_if_needed(retval)$(.$await)? - } - $(#[$track_caller])? - pub $($async)? fn write_bool(&mut $self, io: Expr, value: bool) { - $self.sim_impl - .borrow_mut() - .write_bit(Expr::canonical(io), value, $which_module); - } - $(#[$track_caller])? - pub $($async)? fn read_bool(&mut $self, io: Expr) -> bool { - let retval = $self - .sim_impl - .borrow_mut() - .read_bit(Expr::canonical(io), $which_module); - $self.settle_if_needed(retval)$(.$await)? - } - $(#[$track_caller])? - pub $($async)? fn write_reset(&mut $self, io: Expr, value: bool) { - $self.sim_impl - .borrow_mut() - .write_bit(Expr::canonical(io), value, $which_module); - } - $(#[$track_caller])? - pub $($async)? fn read_reset(&mut $self, io: Expr) -> bool { - let retval = $self - .sim_impl - .borrow_mut() - .read_bit(Expr::canonical(io), $which_module); - $self.settle_if_needed(retval)$(.$await)? - } - $(#[$track_caller])? - pub $($async)? fn read(&mut $self, io: Expr) -> SimValue { - let retval = $self - .sim_impl - .borrow_mut() - .read(Expr::canonical(io), $which_module).1; - SimValue::from_canonical($self.settle_if_needed(retval)$(.$await)?) - } - $(#[$track_caller])? - pub $($async)? fn write>(&mut $self, io: Expr, value: V) { - $self.sim_impl.borrow_mut().write( - Expr::canonical(io), - &value.into_sim_value(Expr::ty(io)).into_canonical(), - $which_module, - ); - } - }; -} - impl Simulation { pub fn new(module: Interned>) -> Self { Self::from_compiled(Compiled::new(module)) } pub fn add_trace_writer(&mut self, writer: W) { self.sim_impl - .borrow_mut() .trace_writers .push(TraceWriterState::Decls(DynTraceWriterDecls::new(writer))); } pub fn flush_traces(&mut self) -> std::io::Result<()> { - SimulationImpl::flush_traces(&self.sim_impl) + self.sim_impl.flush_traces() } pub fn close(self) -> std::io::Result<()> { - SimulationImpl::close(self.sim_impl) + self.sim_impl.close() } pub fn canonical(self) -> Simulation { let Self { sim_impl, io } = self; @@ -8209,225 +7312,77 @@ impl Simulation { let sim_impl = SimulationImpl::new(compiled.canonical()); Self { io: Expr::from_bundle(sim_impl.io), - sim_impl: Rc::new(RefCell::new(sim_impl)), + sim_impl, } } #[track_caller] pub fn settle(&mut self) { - SimulationImpl::settle(&self.sim_impl); + self.sim_impl.settle(); } #[track_caller] pub fn advance_time(&mut self, duration: SimDuration) { - SimulationImpl::advance_time(&self.sim_impl, duration); + self.sim_impl.advance_time(duration); } #[track_caller] - fn settle_if_needed(&mut self, v: MaybeNeedsSettle) -> O - where - for<'a> F: MaybeNeedsSettleFn<&'a mut interpreter::State, Output = O>, - { - SimulationImpl::settle_if_needed(&self.sim_impl, v) + pub fn read_bool_or_int(&mut self, io: Expr) -> I::Value { + self.sim_impl.read_bool_or_int(io) + } + #[track_caller] + pub fn write_bool_or_int( + &mut self, + io: Expr, + value: impl ToExpr, + ) { + let value = value.to_expr(); + assert_eq!(Expr::ty(io), Expr::ty(value), "type mismatch"); + let value = value + .to_literal_bits() + .expect("the value that is being written to an input must be a literal"); + self.sim_impl + .write_bool_or_int(io, I::bits_to_value(Cow::Borrowed(&value))); + } + #[track_caller] + pub fn write_clock(&mut self, io: Expr, value: bool) { + self.sim_impl.write_bit(Expr::canonical(io), value); + } + #[track_caller] + pub fn read_clock(&mut self, io: Expr) -> bool { + self.sim_impl.read_bit(Expr::canonical(io)) + } + #[track_caller] + pub fn write_bool(&mut self, io: Expr, value: bool) { + self.sim_impl.write_bit(Expr::canonical(io), value); + } + #[track_caller] + pub fn read_bool(&mut self, io: Expr) -> bool { + self.sim_impl.read_bit(Expr::canonical(io)) + } + #[track_caller] + pub fn write_reset(&mut self, io: Expr, value: bool) { + self.sim_impl.write_bit(Expr::canonical(io), value); + } + #[track_caller] + pub fn read_reset(&mut self, io: Expr) -> bool { + self.sim_impl.read_bit(Expr::canonical(io)) + } + #[track_caller] + pub fn read(&mut self, io: Expr) -> SimValue { + SimValue::from_canonical(self.sim_impl.read(Expr::canonical(io))) + } + #[track_caller] + pub fn write>(&mut self, io: Expr, value: V) { + self.sim_impl.write( + Expr::canonical(io), + value.into_sim_value(Expr::ty(io)).into_canonical(), + ); } - impl_simulation_methods!( - async_await = (), - track_caller = (#[track_caller]), - which_module = |self| WhichModule::Main, - ); #[doc(hidden)] /// This is explicitly unstable and may be changed/removed at any time pub fn set_breakpoints_unstable(&mut self, pcs: HashSet, trace: bool) { - self.sim_impl.borrow_mut().breakpoints = Some(BreakpointsSet { + self.sim_impl.breakpoints = Some(BreakpointsSet { last_was_break: false, set: pcs, trace, }); } } - -pub struct ExternModuleSimulationState { - sim_impl: Rc>, - module_index: usize, - wait_for_changes_wait_targets: EarliestWaitTargets, -} - -impl fmt::Debug for ExternModuleSimulationState { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { - sim_impl: _, - module_index, - wait_for_changes_wait_targets: _, - } = self; - f.debug_struct("ExternModuleSimulationState") - .field("sim_impl", &DebugAsDisplay("...")) - .field("module_index", module_index) - .finish_non_exhaustive() - } -} - -impl ExternModuleSimulationState { - pub async fn settle(&mut self) { - SimulationImpl::yield_advance_time_or_settle(self.sim_impl.clone(), self.module_index, None) - .await - } - pub async fn advance_time(&mut self, duration: SimDuration) { - SimulationImpl::yield_advance_time_or_settle( - self.sim_impl.clone(), - self.module_index, - Some(duration), - ) - .await - } - pub async fn wait_for_changes>( - &mut self, - iter: I, - timeout: Option, - ) { - self.wait_for_changes_wait_targets.clear(); - let which_module = WhichModule::Extern { - module_index: self.module_index, - }; - for io in iter { - let io = Expr::canonical(io.to_expr()); - let (key, value) = self.sim_impl.borrow_mut().read(io, which_module); - let value = self.settle_if_needed(value).await; - self.wait_for_changes_wait_targets - .insert(WaitTarget::Change { key, value }); - } - if let Some(timeout) = timeout { - self.wait_for_changes_wait_targets.instant = - Some(self.sim_impl.borrow().instant + timeout); - } - SimulationImpl::yield_wait( - self.sim_impl.clone(), - self.module_index, - &mut self.wait_for_changes_wait_targets, - ) - .await; - } - pub async fn wait_for_clock_edge(&mut self, clk: impl ToExpr) { - let clk = clk.to_expr(); - while self.read_clock(clk).await { - self.wait_for_changes([clk], None).await; - } - while !self.read_clock(clk).await { - self.wait_for_changes([clk], None).await; - } - } - async fn settle_if_needed(&mut self, v: MaybeNeedsSettle) -> O - where - for<'a> F: MaybeNeedsSettleFn<&'a mut interpreter::State, Output = O>, - { - SimulationImpl::yield_settle_if_needed(&self.sim_impl, self.module_index, v).await - } - impl_simulation_methods!( - async_await = (async, await), - track_caller = (), - which_module = |self| WhichModule::Extern { module_index: self.module_index }, - ); -} - -pub trait ExternModuleSimGenerator: Clone + Eq + Hash + Any + Send + Sync + fmt::Debug { - fn run<'a>(&'a self, sim: ExternModuleSimulationState) -> impl IntoFuture + 'a; -} - -pub struct SimGeneratorFn { - pub args: Args, - pub f: fn(Args, ExternModuleSimulationState) -> Fut, -} - -impl fmt::Debug for SimGeneratorFn { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { args, f: _ } = self; - f.debug_struct("SimGeneratorFn") - .field("args", args) - .field("f", &DebugAsDisplay("...")) - .finish() - } -} - -impl Hash for SimGeneratorFn { - fn hash(&self, state: &mut H) { - let Self { args, f } = self; - args.hash(state); - f.hash(state); - } -} - -impl Eq for SimGeneratorFn {} - -impl PartialEq for SimGeneratorFn { - fn eq(&self, other: &Self) -> bool { - let Self { args, f } = self; - *args == other.args && *f == other.f - } -} - -impl Clone for SimGeneratorFn { - fn clone(&self) -> Self { - Self { - args: self.args.clone(), - f: self.f, - } - } -} - -impl Copy for SimGeneratorFn {} - -impl< - T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static, - Fut: IntoFuture + 'static, - > ExternModuleSimGenerator for SimGeneratorFn -{ - fn run<'a>(&'a self, sim: ExternModuleSimulationState) -> impl IntoFuture + 'a { - (self.f)(self.args.clone(), sim) - } -} - -trait DynExternModuleSimGenerator: Any + Send + Sync + SupportsPtrEqWithTypeId + fmt::Debug { - fn dyn_run<'a>(&'a self, sim: ExternModuleSimulationState) - -> Box + 'a>; -} - -impl DynExternModuleSimGenerator for T { - fn dyn_run<'a>( - &'a self, - sim: ExternModuleSimulationState, - ) -> Box + 'a> { - Box::new(self.run(sim).into_future()) - } -} - -impl InternedCompare for dyn DynExternModuleSimGenerator { - type InternedCompareKey = PtrEqWithTypeId; - - fn interned_compare_key_ref(this: &Self) -> Self::InternedCompareKey { - this.get_ptr_eq_with_type_id() - } -} - -#[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)] -pub struct ExternModuleSimulation { - generator: Interned, - source_location: SourceLocation, -} - -impl ExternModuleSimulation { - pub fn new_with_loc( - source_location: SourceLocation, - generator: G, - ) -> Self { - Self { - generator: Interned::cast_unchecked( - generator.intern(), - |v| -> &dyn DynExternModuleSimGenerator { v }, - ), - source_location, - } - } - #[track_caller] - pub fn new(generator: G) -> Self { - Self::new_with_loc(SourceLocation::caller(), generator) - } - fn run(&self, sim: ExternModuleSimulationState) -> Box + 'static> { - Interned::into_inner(self.generator).dyn_run(sim) - } -} diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index 450be54..8c8a10f 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -3,7 +3,6 @@ use fayalite::{ int::UIntValue, - module::{instance_with_loc, reg_builder_with_loc}, prelude::*, reset::ResetType, sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation, ToSimValue}, @@ -1444,172 +1443,3 @@ fn test_conditional_assignment_last() { panic!(); } } - -#[hdl_module(outline_generated, extern)] -pub fn extern_module() { - #[hdl] - let i: Bool = m.input(); - #[hdl] - let o: Bool = m.output(); - m.extern_module_simulation_fn((i, o), |(i, o), mut sim| async move { - sim.write(o, true).await; - sim.advance_time(SimDuration::from_nanos(500)).await; - let mut invert = false; - loop { - sim.advance_time(SimDuration::from_micros(1)).await; - let v = sim.read_bool(i).await; - sim.write(o, v ^ invert).await; - invert = !invert; - } - }); -} - -#[test] -fn test_extern_module() { - let _n = SourceLocation::normalize_files_for_tests(); - let mut sim = Simulation::new(extern_module()); - let mut writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - sim.write(sim.io().i, false); - sim.advance_time(SimDuration::from_micros(10)); - sim.write(sim.io().i, true); - sim.advance_time(SimDuration::from_micros(10)); - sim.flush_traces().unwrap(); - let vcd = String::from_utf8(writer.take()).unwrap(); - println!("####### VCD:\n{vcd}\n#######"); - if vcd != include_str!("sim/expected/extern_module.vcd") { - panic!(); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/extern_module.txt") { - panic!(); - } -} - -#[hdl_module(outline_generated, extern)] -pub fn extern_module2() { - #[hdl] - let en: Bool = m.input(); - #[hdl] - let clk: Clock = m.input(); - #[hdl] - let o: UInt<8> = m.output(); - m.extern_module_simulation_fn((en, clk, o), |(en, clk, o), mut sim| async move { - for b in "Hello, World!\n".bytes().cycle() { - sim.write(o, b).await; - loop { - sim.wait_for_clock_edge(clk).await; - if sim.read_bool(en).await { - break; - } - } - } - }); -} - -#[test] -fn test_extern_module2() { - let _n = SourceLocation::normalize_files_for_tests(); - let mut sim = Simulation::new(extern_module2()); - let mut writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - for i in 0..30 { - sim.write(sim.io().en, i % 10 < 5); - sim.write(sim.io().clk, false); - sim.advance_time(SimDuration::from_micros(1)); - sim.write(sim.io().clk, true); - sim.advance_time(SimDuration::from_micros(1)); - } - sim.flush_traces().unwrap(); - let vcd = String::from_utf8(writer.take()).unwrap(); - println!("####### VCD:\n{vcd}\n#######"); - if vcd != include_str!("sim/expected/extern_module2.vcd") { - panic!(); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/extern_module2.txt") { - panic!(); - } -} - -// use an extern module to simulate a register to test that the -// simulator can handle chains of alternating circuits and extern modules. -#[hdl_module(outline_generated, extern)] -pub fn sw_reg() { - #[hdl] - let clk: Clock = m.input(); - #[hdl] - let o: Bool = m.output(); - m.extern_module_simulation_fn((clk, o), |(clk, o), mut sim| async move { - let mut state = false; - loop { - sim.write(o, state).await; - sim.wait_for_clock_edge(clk).await; - state = !state; - } - }); -} - -#[hdl_module(outline_generated)] -pub fn ripple_counter() { - #[hdl] - let clk: Clock = m.input(); - #[hdl] - let o: UInt<6> = m.output(); - - #[hdl] - let bits: Array = wire(); - - connect_any(o, bits.cast_to_bits()); - - let mut clk_in = clk; - for (i, bit) in bits.into_iter().enumerate() { - if i % 2 == 0 { - let bit_reg = reg_builder_with_loc(&format!("bit_reg_{i}"), SourceLocation::caller()) - .clock_domain( - #[hdl] - ClockDomain { - clk: clk_in, - rst: false.to_sync_reset(), - }, - ) - .no_reset(Bool) - .build(); - connect(bit, bit_reg); - connect(bit_reg, !bit_reg); - } else { - let bit_reg = - instance_with_loc(&format!("bit_reg_{i}"), sw_reg(), SourceLocation::caller()); - connect(bit_reg.clk, clk_in); - connect(bit, bit_reg.o); - } - clk_in = bit.to_clock(); - } -} - -#[test] -fn test_ripple_counter() { - let _n = SourceLocation::normalize_files_for_tests(); - let mut sim = Simulation::new(ripple_counter()); - let mut writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - for _ in 0..0x80 { - sim.write(sim.io().clk, false); - sim.advance_time(SimDuration::from_micros(1)); - sim.write(sim.io().clk, true); - sim.advance_time(SimDuration::from_micros(1)); - } - sim.flush_traces().unwrap(); - let vcd = String::from_utf8(writer.take()).unwrap(); - println!("####### VCD:\n{vcd}\n#######"); - if vcd != include_str!("sim/expected/ripple_counter.vcd") { - panic!(); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/ripple_counter.txt") { - panic!(); - } -} diff --git a/crates/fayalite/tests/sim/expected/array_rw.txt b/crates/fayalite/tests/sim/expected/array_rw.txt index 34643f2..f016e72 100644 --- a/crates/fayalite/tests/sim/expected/array_rw.txt +++ b/crates/fayalite/tests/sim/expected/array_rw.txt @@ -488,338 +488,1501 @@ Simulation { .. }, }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in: CompiledValue { + layout: CompiledTypeLayout { + ty: Array, 16>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 16, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[7]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[8]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[9]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[10]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[11]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[12]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[13]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[14]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[15]", + ty: UInt<8>, + }, + ], + .. + }, }, - }.array_in, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. + body: Array { + element: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, }, - }.array_out, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.read_index, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.read_data, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.write_index, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.write_data, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.write_en, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[0], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[10], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[11], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[12], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[13], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[14], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[15], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[1], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[2], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[3], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[4], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[5], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[6], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[7], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[8], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[9], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[0], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[10], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[11], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[12], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[13], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[14], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[15], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[1], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[2], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[3], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[4], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[5], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[6], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[7], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[8], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[9], - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.read_data, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.read_index, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.write_data, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.write_en, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.write_index, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 16 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[0]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[10]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 10, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[11]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 11, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[12]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 12, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[13]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 13, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[14]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 14, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[15]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 15, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[1]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[2]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[3]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[4]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[5]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 5, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[6]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 6, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[7]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 7, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[8]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 8, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[9]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 9, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out: CompiledValue { + layout: CompiledTypeLayout { + ty: Array, 16>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 16, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[7]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[8]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[9]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[10]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[11]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[12]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[13]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[14]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[15]", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Array { + element: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 16, len: 16 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[0]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 16, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[10]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 26, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[11]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 27, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[12]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 28, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[13]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 29, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[14]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 30, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[15]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 31, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[1]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 17, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[2]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 18, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[3]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 19, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[4]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 20, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[5]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 21, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[6]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 22, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[7]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 23, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[8]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 24, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[9]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 25, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.read_data: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::read_data", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 33, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.read_index: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::read_index", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 32, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.write_data: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::write_data", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 35, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.write_en: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::write_en", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 36, len: 1 }, + }, + write: None, + }, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.write_index: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(array_rw: array_rw).array_rw::write_index", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 34, len: 1 }, + }, + write: None, }, - did_initial_settle: true, }, - extern_modules: [], - state_ready_to_run: false, + made_initial_step: true, + needs_settle: false, trace_decls: TraceModule { name: "array_rw", children: [ diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt index c4242c4..186e5a5 100644 --- a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt +++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt @@ -92,30 +92,45 @@ Simulation { .. }, }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::conditional_assignment_last, - instantiated: Module { - name: conditional_assignment_last, - .. + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::conditional_assignment_last, + instantiated: Module { + name: conditional_assignment_last, + .. + }, + }.i: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::i", + ty: Bool, + }, + ], + .. + }, }, - }.i, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::conditional_assignment_last, - instantiated: Module { - name: conditional_assignment_last, - .. - }, - }.i, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, }, - did_initial_settle: true, }, - extern_modules: [], - state_ready_to_run: false, + made_initial_step: true, + needs_settle: false, trace_decls: TraceModule { name: "conditional_assignment_last", children: [ diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt index d357741..e44c50d 100644 --- a/crates/fayalite/tests/sim/expected/connect_const.txt +++ b/crates/fayalite/tests/sim/expected/connect_const.txt @@ -68,30 +68,45 @@ Simulation { .. }, }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::connect_const, - instantiated: Module { - name: connect_const, - .. + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::connect_const, + instantiated: Module { + name: connect_const, + .. + }, + }.o: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(connect_const: connect_const).connect_const::o", + ty: UInt<8>, + }, + ], + .. + }, }, - }.o, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::connect_const, - instantiated: Module { - name: connect_const, - .. - }, - }.o, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, }, - did_initial_settle: true, }, - extern_modules: [], - state_ready_to_run: false, + made_initial_step: true, + needs_settle: false, trace_decls: TraceModule { name: "connect_const", children: [ diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt index b3eb3ea..d1ab998 100644 --- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt +++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt @@ -97,44 +97,79 @@ Simulation { .. }, }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::connect_const_reset, - instantiated: Module { - name: connect_const_reset, - .. + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::connect_const_reset, + instantiated: Module { + name: connect_const_reset, + .. + }, + }.bit_out: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", + ty: Bool, + }, + ], + .. + }, }, - }.reset_out, - Instance { - name: ::connect_const_reset, - instantiated: Module { - name: connect_const_reset, - .. - }, - }.bit_out, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::connect_const_reset, - instantiated: Module { - name: connect_const_reset, - .. - }, - }.bit_out, - Instance { - name: ::connect_const_reset, - instantiated: Module { - name: connect_const_reset, - .. - }, - }.reset_out, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::connect_const_reset, + instantiated: Module { + name: connect_const_reset, + .. + }, + }.reset_out: CompiledValue { + layout: CompiledTypeLayout { + ty: AsyncReset, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", + ty: AsyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, }, - did_initial_settle: true, }, - extern_modules: [], - state_ready_to_run: false, + made_initial_step: true, + needs_settle: false, trace_decls: TraceModule { name: "connect_const_reset", children: [ diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt index 558d943..2e005a0 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.txt +++ b/crates/fayalite/tests/sim/expected/counter_async.txt @@ -203,58 +203,213 @@ Simulation { .. }, }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, }, - }.cd, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::cd.rst", + ty: AsyncReset, + }, + ], + .. + }, }, - }.count, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: AsyncReset, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: AsyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], }, - }.cd, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd.clk, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd.rst, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.count, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 2 }, + }, + write: None, + }, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd.rst: CompiledValue { + layout: CompiledTypeLayout { + ty: AsyncReset, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: AsyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.count: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::count", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, }, - did_initial_settle: true, }, - extern_modules: [], - state_ready_to_run: false, + made_initial_step: true, + needs_settle: false, trace_decls: TraceModule { name: "counter", children: [ diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt index d31db25..78fc200 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/counter_sync.txt @@ -184,58 +184,213 @@ Simulation { .. }, }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, }, - }.cd, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::cd.rst", + ty: SyncReset, + }, + ], + .. + }, }, - }.count, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SyncReset, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], }, - }.cd, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd.clk, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd.rst, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.count, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 2 }, + }, + write: None, + }, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd.rst: CompiledValue { + layout: CompiledTypeLayout { + ty: SyncReset, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.count: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::count", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, }, - did_initial_settle: true, }, - extern_modules: [], - state_ready_to_run: false, + made_initial_step: true, + needs_settle: false, trace_decls: TraceModule { name: "counter", children: [ diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.txt b/crates/fayalite/tests/sim/expected/duplicate_names.txt index 5c6c18a..8a59861 100644 --- a/crates/fayalite/tests/sim/expected/duplicate_names.txt +++ b/crates/fayalite/tests/sim/expected/duplicate_names.txt @@ -88,14 +88,10 @@ Simulation { .. }, }, - main_module: SimulationModuleState { - base_targets: [], - uninitialized_ios: {}, - io_targets: {}, - did_initial_settle: true, - }, - extern_modules: [], - state_ready_to_run: false, + uninitialized_inputs: {}, + io_targets: {}, + made_initial_step: true, + needs_settle: false, trace_decls: TraceModule { name: "duplicate_names", children: [ diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt index 089ea31..ebfae3e 100644 --- a/crates/fayalite/tests/sim/expected/enums.txt +++ b/crates/fayalite/tests/sim/expected/enums.txt @@ -1215,128 +1215,389 @@ Simulation { .. }, }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.b_out: CompiledValue { + layout: CompiledTypeLayout { + ty: Enum { + HdlNone, + HdlSome(Bundle {0: UInt<1>, 1: Bool}), }, - }.cd, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(enums: enums).enums::b_out", + ty: Enum { + HdlNone, + HdlSome(Bundle {0: UInt<1>, 1: Bool}), + }, + }, + ], + .. + }, }, - }.en, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.which_in, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.data_in, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.which_out, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.data_out, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.b_out, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.b_out, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.cd, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.cd.clk, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.cd.rst, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.data_in, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.data_out, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.en, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.which_in, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.which_out, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 7, len: 1 }, + }, + write: None, + }, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.cd: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(enums: enums).enums::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(enums: enums).enums::cd.rst", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SyncReset, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 2 }, + }, + write: None, + }, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.cd.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.cd.rst: CompiledValue { + layout: CompiledTypeLayout { + ty: SyncReset, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.data_in: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(enums: enums).enums::data_in", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 1 }, + }, + write: None, + }, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.data_out: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(enums: enums).enums::data_out", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 6, len: 1 }, + }, + write: None, + }, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.en: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(enums: enums).enums::en", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, + }, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.which_in: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(enums: enums).enums::which_in", + ty: UInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 1 }, + }, + write: None, + }, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.which_out: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(enums: enums).enums::which_out", + ty: UInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 5, len: 1 }, + }, + write: None, }, - did_initial_settle: true, }, - extern_modules: [], - state_ready_to_run: false, + made_initial_step: true, + needs_settle: false, trace_decls: TraceModule { name: "enums", children: [ diff --git a/crates/fayalite/tests/sim/expected/extern_module.txt b/crates/fayalite/tests/sim/expected/extern_module.txt deleted file mode 100644 index 6cce70b..0000000 --- a/crates/fayalite/tests/sim/expected/extern_module.txt +++ /dev/null @@ -1,220 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(extern_module: extern_module).extern_module::i", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(extern_module: extern_module).extern_module::o", - ty: Bool, - }, - ], - .. - }, - }, - memories: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:1:1 - 0: Return, - ], - .. - }, - pc: 0, - memory_write_log: [], - memories: StatePart { - value: [], - }, - small_slots: StatePart { - value: [], - }, - big_slots: StatePart { - value: [ - 1, - 1, - ], - }, - }, - io: Instance { - name: ::extern_module, - instantiated: Module { - name: extern_module, - .. - }, - }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::extern_module, - instantiated: Module { - name: extern_module, - .. - }, - }.i, - Instance { - name: ::extern_module, - instantiated: Module { - name: extern_module, - .. - }, - }.o, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::extern_module, - instantiated: Module { - name: extern_module, - .. - }, - }.i, - Instance { - name: ::extern_module, - instantiated: Module { - name: extern_module, - .. - }, - }.o, - }, - did_initial_settle: true, - }, - extern_modules: [ - SimulationExternModuleState { - module_state: SimulationModuleState { - base_targets: [ - ModuleIO { - name: extern_module::i, - is_input: true, - ty: Bool, - .. - }, - ModuleIO { - name: extern_module::o, - is_input: false, - ty: Bool, - .. - }, - ], - uninitialized_ios: {}, - io_targets: { - ModuleIO { - name: extern_module::i, - is_input: true, - ty: Bool, - .. - }, - ModuleIO { - name: extern_module::o, - is_input: false, - ty: Bool, - .. - }, - }, - did_initial_settle: true, - }, - sim: ExternModuleSimulation { - generator: SimGeneratorFn { - args: ( - ModuleIO { - name: extern_module::i, - is_input: true, - ty: Bool, - .. - }, - ModuleIO { - name: extern_module::o, - is_input: false, - ty: Bool, - .. - }, - ), - f: ..., - }, - source_location: SourceLocation( - module-XXXXXXXXXX.rs:4:1, - ), - }, - running_generator: Some( - ..., - ), - wait_targets: { - Instant( - 20.500000000000 μs, - ), - }, - }, - ], - state_ready_to_run: false, - trace_decls: TraceModule { - name: "extern_module", - children: [ - TraceModuleIO { - name: "i", - child: TraceBool { - location: TraceScalarId(0), - name: "i", - flow: Source, - }, - ty: Bool, - flow: Source, - }, - TraceModuleIO { - name: "o", - child: TraceBool { - location: TraceScalarId(1), - name: "o", - flow: Sink, - }, - ty: Bool, - flow: Sink, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigBool { - index: StatePartIndex(0), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigBool { - index: StatePartIndex(1), - }, - state: 0x1, - last_state: 0x1, - }, - ], - trace_memories: {}, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - instant: 20 μs, - clocks_triggered: [], - .. -} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/extern_module.vcd b/crates/fayalite/tests/sim/expected/extern_module.vcd deleted file mode 100644 index e026a50..0000000 --- a/crates/fayalite/tests/sim/expected/extern_module.vcd +++ /dev/null @@ -1,51 +0,0 @@ -$timescale 1 ps $end -$scope module extern_module $end -$var wire 1 ! i $end -$var wire 1 " o $end -$upscope $end -$enddefinitions $end -$dumpvars -0! -1" -$end -#500000 -#1500000 -0" -#2500000 -1" -#3500000 -0" -#4500000 -1" -#5500000 -0" -#6500000 -1" -#7500000 -0" -#8500000 -1" -#9500000 -0" -#10000000 -1! -#10500000 -#11500000 -1" -#12500000 -0" -#13500000 -1" -#14500000 -0" -#15500000 -1" -#16500000 -0" -#17500000 -1" -#18500000 -0" -#19500000 -1" -#20000000 diff --git a/crates/fayalite/tests/sim/expected/extern_module2.txt b/crates/fayalite/tests/sim/expected/extern_module2.txt deleted file mode 100644 index 96710fb..0000000 --- a/crates/fayalite/tests/sim/expected/extern_module2.txt +++ /dev/null @@ -1,308 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 3, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::o", - ty: UInt<8>, - }, - ], - .. - }, - }, - memories: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:1:1 - 0: Return, - ], - .. - }, - pc: 0, - memory_write_log: [], - memories: StatePart { - value: [], - }, - small_slots: StatePart { - value: [], - }, - big_slots: StatePart { - value: [ - 0, - 1, - 101, - ], - }, - }, - io: Instance { - name: ::extern_module2, - instantiated: Module { - name: extern_module2, - .. - }, - }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::extern_module2, - instantiated: Module { - name: extern_module2, - .. - }, - }.en, - Instance { - name: ::extern_module2, - instantiated: Module { - name: extern_module2, - .. - }, - }.clk, - Instance { - name: ::extern_module2, - instantiated: Module { - name: extern_module2, - .. - }, - }.o, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::extern_module2, - instantiated: Module { - name: extern_module2, - .. - }, - }.clk, - Instance { - name: ::extern_module2, - instantiated: Module { - name: extern_module2, - .. - }, - }.en, - Instance { - name: ::extern_module2, - instantiated: Module { - name: extern_module2, - .. - }, - }.o, - }, - did_initial_settle: true, - }, - extern_modules: [ - SimulationExternModuleState { - module_state: SimulationModuleState { - base_targets: [ - ModuleIO { - name: extern_module2::en, - is_input: true, - ty: Bool, - .. - }, - ModuleIO { - name: extern_module2::clk, - is_input: true, - ty: Clock, - .. - }, - ModuleIO { - name: extern_module2::o, - is_input: false, - ty: UInt<8>, - .. - }, - ], - uninitialized_ios: {}, - io_targets: { - ModuleIO { - name: extern_module2::clk, - is_input: true, - ty: Clock, - .. - }, - ModuleIO { - name: extern_module2::en, - is_input: true, - ty: Bool, - .. - }, - ModuleIO { - name: extern_module2::o, - is_input: false, - ty: UInt<8>, - .. - }, - }, - did_initial_settle: true, - }, - sim: ExternModuleSimulation { - generator: SimGeneratorFn { - args: ( - ModuleIO { - name: extern_module2::en, - is_input: true, - ty: Bool, - .. - }, - ModuleIO { - name: extern_module2::clk, - is_input: true, - ty: Clock, - .. - }, - ModuleIO { - name: extern_module2::o, - is_input: false, - ty: UInt<8>, - .. - }, - ), - f: ..., - }, - source_location: SourceLocation( - module-XXXXXXXXXX.rs:5:1, - ), - }, - running_generator: Some( - ..., - ), - wait_targets: { - Change { - key: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - value: SimValue { - ty: Clock, - bits: 0x1, - }, - }, - }, - }, - ], - state_ready_to_run: false, - trace_decls: TraceModule { - name: "extern_module2", - children: [ - TraceModuleIO { - name: "en", - child: TraceBool { - location: TraceScalarId(0), - name: "en", - flow: Source, - }, - ty: Bool, - flow: Source, - }, - TraceModuleIO { - name: "clk", - child: TraceClock { - location: TraceScalarId(1), - name: "clk", - flow: Source, - }, - ty: Clock, - flow: Source, - }, - TraceModuleIO { - name: "o", - child: TraceUInt { - location: TraceScalarId(2), - name: "o", - ty: UInt<8>, - flow: Sink, - }, - ty: UInt<8>, - flow: Sink, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigBool { - index: StatePartIndex(0), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigClock { - index: StatePartIndex(1), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigUInt { - index: StatePartIndex(2), - ty: UInt<8>, - }, - state: 0x65, - last_state: 0x65, - }, - ], - trace_memories: {}, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - instant: 60 μs, - clocks_triggered: [], - .. -} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/extern_module2.vcd b/crates/fayalite/tests/sim/expected/extern_module2.vcd deleted file mode 100644 index 464f4bd..0000000 --- a/crates/fayalite/tests/sim/expected/extern_module2.vcd +++ /dev/null @@ -1,150 +0,0 @@ -$timescale 1 ps $end -$scope module extern_module2 $end -$var wire 1 ! en $end -$var wire 1 " clk $end -$var wire 8 # o $end -$upscope $end -$enddefinitions $end -$dumpvars -1! -0" -b1001000 # -$end -#1000000 -1" -b1100101 # -#2000000 -0" -#3000000 -1" -b1101100 # -#4000000 -0" -#5000000 -1" -#6000000 -0" -#7000000 -1" -b1101111 # -#8000000 -0" -#9000000 -1" -b101100 # -#10000000 -0! -0" -#11000000 -1" -#12000000 -0" -#13000000 -1" -#14000000 -0" -#15000000 -1" -#16000000 -0" -#17000000 -1" -#18000000 -0" -#19000000 -1" -#20000000 -1! -0" -#21000000 -1" -b100000 # -#22000000 -0" -#23000000 -1" -b1010111 # -#24000000 -0" -#25000000 -1" -b1101111 # -#26000000 -0" -#27000000 -1" -b1110010 # -#28000000 -0" -#29000000 -1" -b1101100 # -#30000000 -0! -0" -#31000000 -1" -#32000000 -0" -#33000000 -1" -#34000000 -0" -#35000000 -1" -#36000000 -0" -#37000000 -1" -#38000000 -0" -#39000000 -1" -#40000000 -1! -0" -#41000000 -1" -b1100100 # -#42000000 -0" -#43000000 -1" -b100001 # -#44000000 -0" -#45000000 -1" -b1010 # -#46000000 -0" -#47000000 -1" -b1001000 # -#48000000 -0" -#49000000 -1" -b1100101 # -#50000000 -0! -0" -#51000000 -1" -#52000000 -0" -#53000000 -1" -#54000000 -0" -#55000000 -1" -#56000000 -0" -#57000000 -1" -#58000000 -0" -#59000000 -1" -#60000000 diff --git a/crates/fayalite/tests/sim/expected/memories.txt b/crates/fayalite/tests/sim/expected/memories.txt index cd778d4..afccd8a 100644 --- a/crates/fayalite/tests/sim/expected/memories.txt +++ b/crates/fayalite/tests/sim/expected/memories.txt @@ -570,149 +570,1309 @@ Simulation { .. }, }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, }, - }.r, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 5, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::r.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::r.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::r.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::r.data.0", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::r.data.1", + ty: SInt<8>, + }, + ], + .. + }, }, - }.w, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(2), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(3), + }, + ty: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".0", + ty: UInt<8>, + }, + SlotDebugData { + name: ".1", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + }, + ], }, - }.r, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.r.addr, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.r.clk, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.r.data, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.r.data.0, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.r.data.1, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.r.en, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.addr, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.clk, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.data, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.data.0, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.data.1, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.en, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.mask, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.mask.0, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.mask.1, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 5 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.addr: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.data: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".0", + ty: UInt<8>, + }, + SlotDebugData { + name: ".1", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 2 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.data.0: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.data.1: CompiledValue { + layout: CompiledTypeLayout { + ty: SInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.en: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + /* offset = 22 */ + mask: Bundle { + /* offset = 0 */ + 0: Bool, + /* offset = 1 */ + 1: Bool, + }, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 7, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.data.0", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.data.1", + ty: SInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.mask.0", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories: memories).memories::w.mask.1", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(2), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(3), + }, + ty: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".0", + ty: UInt<8>, + }, + SlotDebugData { + name: ".1", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(5), + }, + ty: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + 0: Bool, + /* offset = 1 */ + 1: Bool, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".0", + ty: Bool, + }, + SlotDebugData { + name: ".1", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 5, len: 7 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.addr: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 5, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 7, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.data: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + 0: UInt<8>, + /* offset = 8 */ + 1: SInt<8>, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".0", + ty: UInt<8>, + }, + SlotDebugData { + name: ".1", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 8, len: 2 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.data.0: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 8, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.data.1: CompiledValue { + layout: CompiledTypeLayout { + ty: SInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 9, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.en: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 6, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.mask: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + 0: Bool, + /* offset = 1 */ + 1: Bool, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: ".0", + ty: Bool, + }, + SlotDebugData { + name: ".1", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 10, len: 2 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.mask.0: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 10, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.mask.1: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 11, len: 1 }, + }, + write: None, }, - did_initial_settle: true, }, - extern_modules: [], - state_ready_to_run: false, + made_initial_step: true, + needs_settle: false, trace_decls: TraceModule { name: "memories", children: [ diff --git a/crates/fayalite/tests/sim/expected/memories2.txt b/crates/fayalite/tests/sim/expected/memories2.txt index 2359749..5d90815 100644 --- a/crates/fayalite/tests/sim/expected/memories2.txt +++ b/crates/fayalite/tests/sim/expected/memories2.txt @@ -598,79 +598,514 @@ Simulation { .. }, }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + rdata: UInt<2>, + /* offset = 7 */ + wmode: Bool, + /* offset = 8 */ + wdata: UInt<2>, + /* offset = 10 */ + wmask: Bool, }, - }.rw, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 7, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.addr", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask", + ty: Bool, + }, + ], + .. + }, }, - }.rw, - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<3>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(2), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(3), + }, + ty: CompiledTypeLayout { + ty: UInt<2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(4), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(5), + }, + ty: CompiledTypeLayout { + ty: UInt<2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(6), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], }, - }.rw.addr, - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. - }, - }.rw.clk, - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. - }, - }.rw.en, - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. - }, - }.rw.rdata, - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. - }, - }.rw.wdata, - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. - }, - }.rw.wmask, - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. - }, - }.rw.wmode, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 7 }, + }, + write: None, + }, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.addr: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<3>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.en: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.rdata: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.wdata: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 5, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.wmask: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 6, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.wmode: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 1 }, + }, + write: None, }, - did_initial_settle: true, }, - extern_modules: [], - state_ready_to_run: false, + made_initial_step: true, + needs_settle: false, trace_decls: TraceModule { name: "memories2", children: [ diff --git a/crates/fayalite/tests/sim/expected/memories3.txt b/crates/fayalite/tests/sim/expected/memories3.txt index ad12aa4..7860bc5 100644 --- a/crates/fayalite/tests/sim/expected/memories3.txt +++ b/crates/fayalite/tests/sim/expected/memories3.txt @@ -1486,275 +1486,1882 @@ Simulation { .. }, }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + data: Array, 8>, }, - }.r, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 11, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.addr", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[7]", + ty: UInt<8>, + }, + ], + .. + }, }, - }.w, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<3>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(2), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(3), + }, + ty: CompiledTypeLayout { + ty: Array, 8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 8, + debug_data: [ + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[7]", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Array { + element: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + }, + }, + ], }, - }.r, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.addr, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.clk, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[0], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[1], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[2], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[3], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[4], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[5], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[6], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[7], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.en, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.addr, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.clk, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[0], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[1], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[2], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[3], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[4], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[5], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[6], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[7], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.en, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[0], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[1], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[2], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[3], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[4], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[5], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[6], - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[7], + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 11 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.addr: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<3>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data: CompiledValue { + layout: CompiledTypeLayout { + ty: Array, 8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 8, + debug_data: [ + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[7]", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Array { + element: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 8 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[0]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[1]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[2]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 5, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[3]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 6, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[4]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 7, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[5]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 8, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[6]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 9, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[7]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 10, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.en: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + /* offset = 5 */ + data: Array, 8>, + /* offset = 69 */ + mask: Array, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 19, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.addr", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[7]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[0]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[1]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[2]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[3]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[4]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[5]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[6]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[7]", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<3>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(2), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(3), + }, + ty: CompiledTypeLayout { + ty: Array, 8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 8, + debug_data: [ + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[7]", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Array { + element: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(11), + }, + ty: CompiledTypeLayout { + ty: Array, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 8, + debug_data: [ + SlotDebugData { + name: "[0]", + ty: Bool, + }, + SlotDebugData { + name: "[1]", + ty: Bool, + }, + SlotDebugData { + name: "[2]", + ty: Bool, + }, + SlotDebugData { + name: "[3]", + ty: Bool, + }, + SlotDebugData { + name: "[4]", + ty: Bool, + }, + SlotDebugData { + name: "[5]", + ty: Bool, + }, + SlotDebugData { + name: "[6]", + ty: Bool, + }, + SlotDebugData { + name: "[7]", + ty: Bool, + }, + ], + .. + }, + }, + body: Array { + element: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 11, len: 19 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.addr: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<3>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 11, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 13, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data: CompiledValue { + layout: CompiledTypeLayout { + ty: Array, 8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 8, + debug_data: [ + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[7]", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Array { + element: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 14, len: 8 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[0]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 14, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[1]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 15, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[2]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 16, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[3]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 17, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[4]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 18, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[5]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 19, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[6]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 20, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[7]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 21, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.en: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 12, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask: CompiledValue { + layout: CompiledTypeLayout { + ty: Array, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 8, + debug_data: [ + SlotDebugData { + name: "[0]", + ty: Bool, + }, + SlotDebugData { + name: "[1]", + ty: Bool, + }, + SlotDebugData { + name: "[2]", + ty: Bool, + }, + SlotDebugData { + name: "[3]", + ty: Bool, + }, + SlotDebugData { + name: "[4]", + ty: Bool, + }, + SlotDebugData { + name: "[5]", + ty: Bool, + }, + SlotDebugData { + name: "[6]", + ty: Bool, + }, + SlotDebugData { + name: "[7]", + ty: Bool, + }, + ], + .. + }, + }, + body: Array { + element: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 22, len: 8 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[0]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 22, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[1]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 23, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[2]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 24, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[3]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 25, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[4]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 26, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[5]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 27, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[6]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 28, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[7]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 29, len: 1 }, + }, + write: None, }, - did_initial_settle: true, }, - extern_modules: [], - state_ready_to_run: false, + made_initial_step: true, + needs_settle: false, trace_decls: TraceModule { name: "memories3", children: [ diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt index 3656247..5c2b7eb 100644 --- a/crates/fayalite/tests/sim/expected/mod1.txt +++ b/crates/fayalite/tests/sim/expected/mod1.txt @@ -216,58 +216,313 @@ Simulation { .. }, }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. + }, + }.o: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + #[hdl(flip)] /* offset = 0 */ + i: UInt<4>, + /* offset = 4 */ + o: SInt<2>, + #[hdl(flip)] /* offset = 6 */ + i2: SInt<2>, + /* offset = 8 */ + o2: UInt<4>, }, - }.o, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 4, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::o.i", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::o.o", + ty: SInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::o.i2", + ty: SInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::o.o2", + ty: UInt<4>, + }, + ], + .. + }, }, - }.o, - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SInt<2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(2), + }, + ty: CompiledTypeLayout { + ty: SInt<2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(3), + }, + ty: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], }, - }.o.i, - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. - }, - }.o.i2, - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. - }, - }.o.o, - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. - }, - }.o.o2, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 4 }, + }, + write: None, + }, + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. + }, + }.o.i: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. + }, + }.o.i2: CompiledValue { + layout: CompiledTypeLayout { + ty: SInt<2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, + }, + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. + }, + }.o.o: CompiledValue { + layout: CompiledTypeLayout { + ty: SInt<2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. + }, + }.o.o2: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 1 }, + }, + write: None, }, - did_initial_settle: true, }, - extern_modules: [], - state_ready_to_run: false, + made_initial_step: true, + needs_settle: false, trace_decls: TraceModule { name: "mod1", children: [ diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.txt b/crates/fayalite/tests/sim/expected/ripple_counter.txt deleted file mode 100644 index e290ace..0000000 --- a/crates/fayalite/tests/sim/expected/ripple_counter.txt +++ /dev/null @@ -1,1492 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 9, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - big_slots: StatePartLayout { - len: 58, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::o", - ty: UInt<6>, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<1>, - }, - SlotDebugData { - name: "", - ty: UInt<1>, - }, - SlotDebugData { - name: "", - ty: UInt<2>, - }, - SlotDebugData { - name: "", - ty: UInt<2>, - }, - SlotDebugData { - name: "", - ty: UInt<1>, - }, - SlotDebugData { - name: "", - ty: UInt<3>, - }, - SlotDebugData { - name: "", - ty: UInt<3>, - }, - SlotDebugData { - name: "", - ty: UInt<1>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: UInt<1>, - }, - SlotDebugData { - name: "", - ty: UInt<5>, - }, - SlotDebugData { - name: "", - ty: UInt<5>, - }, - SlotDebugData { - name: "", - ty: UInt<1>, - }, - SlotDebugData { - name: "", - ty: UInt<6>, - }, - SlotDebugData { - name: "", - ty: UInt<6>, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", - ty: Bool, - }, - SlotDebugData { - name: ".clk", - ty: Clock, - }, - SlotDebugData { - name: ".rst", - ty: SyncReset, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: SyncReset, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::o", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", - ty: Bool, - }, - SlotDebugData { - name: ".clk", - ty: Clock, - }, - SlotDebugData { - name: ".rst", - ty: SyncReset, - }, - SlotDebugData { - name: "", - ty: Clock, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::o", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", - ty: Bool, - }, - SlotDebugData { - name: ".clk", - ty: Clock, - }, - SlotDebugData { - name: ".rst", - ty: SyncReset, - }, - SlotDebugData { - name: "", - ty: Clock, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.o", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::o", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - memories: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:9:1 - 0: Copy { - dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.o", ty: Bool }, - src: StatePartIndex(56), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::o", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:11:1 - 1: Copy { - dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]", ty: Bool }, - src: StatePartIndex(54), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.o", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 2: NotU { - dest: StatePartIndex(52), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool }, - width: 1, - }, - // at: module-XXXXXXXXXX.rs:8:1 - 3: Copy { - dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool }, - src: StatePartIndex(52), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:7:1 - 4: Copy { - dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool }, - src: StatePartIndex(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 5: Copy { - dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Clock }, - src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:10:1 - 6: Copy { - dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock }, - src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Clock }, - }, - // at: module-XXXXXXXXXX.rs:9:1 - 7: Copy { - dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", ty: Clock }, - src: StatePartIndex(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock }, - }, - 8: Copy { - dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool }, - src: StatePartIndex(45), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::o", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:11:1 - 9: Copy { - dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool }, - src: StatePartIndex(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 10: Copy { - dest: StatePartIndex(51), // (0x0) SlotDebugData { name: "", ty: Clock }, - src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool }, - }, - 11: NotU { - dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool }, - width: 1, - }, - // at: module-XXXXXXXXXX.rs:8:1 - 12: Copy { - dest: StatePartIndex(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool }, - src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:7:1 - 13: Copy { - dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool }, - src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 14: Copy { - dest: StatePartIndex(46), // (0x0) SlotDebugData { name: "", ty: Clock }, - src: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:10:1 - 15: Copy { - dest: StatePartIndex(42), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk", ty: Clock }, - src: StatePartIndex(46), // (0x0) SlotDebugData { name: "", ty: Clock }, - }, - // at: module-XXXXXXXXXX.rs:9:1 - 16: Copy { - dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", ty: Clock }, - src: StatePartIndex(42), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk", ty: Clock }, - }, - 17: Copy { - dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool }, - src: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::o", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:11:1 - 18: Copy { - dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool }, - src: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 19: Copy { - dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Clock }, - src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool }, - }, - 20: NotU { - dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool }, - width: 1, - }, - // at: module-XXXXXXXXXX.rs:8:1 - 21: Copy { - dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool }, - src: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:7:1 - 22: Copy { - dest: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool }, - src: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 23: Copy { - dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Clock }, - src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:10:1 - 24: Copy { - dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock }, - src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Clock }, - }, - // at: module-XXXXXXXXXX.rs:9:1 - 25: Copy { - dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", ty: Clock }, - src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 26: Const { - dest: StatePartIndex(28), // (0x0) SlotDebugData { name: "", ty: Bool }, - value: 0x0, - }, - 27: Copy { - dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, - src: StatePartIndex(28), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - 28: Copy { - dest: StatePartIndex(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock }, - src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::clk", ty: Clock }, - }, - 29: Copy { - dest: StatePartIndex(27), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset }, - src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 30: IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock }, - }, - 31: AndSmall { - dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 32: Copy { - dest: StatePartIndex(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, - src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Clock }, - }, - 33: Copy { - dest: StatePartIndex(39), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset }, - src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 34: IsNonZeroDestIsSmall { - dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, - }, - 35: AndSmall { - dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 36: Copy { - dest: StatePartIndex(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, - src: StatePartIndex(51), // (0x0) SlotDebugData { name: "", ty: Clock }, - }, - 37: Copy { - dest: StatePartIndex(50), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset }, - src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 38: IsNonZeroDestIsSmall { - dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, - }, - 39: AndSmall { - dest: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 40: Copy { - dest: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]", ty: Bool }, - }, - 41: Shl { - dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, - lhs: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - rhs: 5, - }, - 42: Copy { - dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool }, - }, - 43: Shl { - dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, - lhs: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - rhs: 4, - }, - 44: Copy { - dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool }, - }, - 45: Shl { - dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, - lhs: StatePartIndex(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - rhs: 3, - }, - 46: Copy { - dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool }, - }, - 47: Shl { - dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, - lhs: StatePartIndex(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - rhs: 2, - }, - 48: Copy { - dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool }, - }, - 49: Shl { - dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - rhs: 1, - }, - 50: Copy { - dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool }, - }, - 51: Or { - dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - lhs: StatePartIndex(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, - rhs: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - }, - 52: Or { - dest: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, - lhs: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, - rhs: StatePartIndex(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, - }, - 53: Or { - dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, - lhs: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, - rhs: StatePartIndex(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, - }, - 54: Or { - dest: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, - lhs: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, - rhs: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, - }, - 55: Or { - dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, - lhs: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, - rhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, - }, - // at: module-XXXXXXXXXX.rs:5:1 - 56: Copy { - dest: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::o", ty: UInt<6> }, - src: StatePartIndex(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 57: BranchIfSmallZero { - target: 59, - value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 58: Copy { - dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool }, - src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool }, - }, - 59: BranchIfSmallZero { - target: 61, - value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 60: Copy { - dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool }, - src: StatePartIndex(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool }, - }, - 61: BranchIfSmallZero { - target: 63, - value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 62: Copy { - dest: StatePartIndex(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool }, - src: StatePartIndex(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool }, - }, - 63: XorSmallImmediate { - dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 64: XorSmallImmediate { - dest: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 65: XorSmallImmediate { - dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 66: Return, - ], - .. - }, - pc: 66, - memory_write_log: [], - memories: StatePart { - value: [], - }, - small_slots: StatePart { - value: [ - 0, - 0, - 1, - 1, - 0, - 0, - 1, - 0, - 0, - ], - }, - big_slots: StatePart { - value: [ - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 0, - ], - }, - }, - io: Instance { - name: ::ripple_counter, - instantiated: Module { - name: ripple_counter, - .. - }, - }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::ripple_counter, - instantiated: Module { - name: ripple_counter, - .. - }, - }.clk, - Instance { - name: ::ripple_counter, - instantiated: Module { - name: ripple_counter, - .. - }, - }.o, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::ripple_counter, - instantiated: Module { - name: ripple_counter, - .. - }, - }.clk, - Instance { - name: ::ripple_counter, - instantiated: Module { - name: ripple_counter, - .. - }, - }.o, - }, - did_initial_settle: true, - }, - extern_modules: [ - SimulationExternModuleState { - module_state: SimulationModuleState { - base_targets: [ - ModuleIO { - name: sw_reg::clk, - is_input: true, - ty: Clock, - .. - }, - ModuleIO { - name: sw_reg::o, - is_input: false, - ty: Bool, - .. - }, - ], - uninitialized_ios: {}, - io_targets: { - ModuleIO { - name: sw_reg::clk, - is_input: true, - ty: Clock, - .. - }, - ModuleIO { - name: sw_reg::o, - is_input: false, - ty: Bool, - .. - }, - }, - did_initial_settle: true, - }, - sim: ExternModuleSimulation { - generator: SimGeneratorFn { - args: ( - ModuleIO { - name: sw_reg::clk, - is_input: true, - ty: Clock, - .. - }, - ModuleIO { - name: sw_reg::o, - is_input: false, - ty: Bool, - .. - }, - ), - f: ..., - }, - source_location: SourceLocation( - module-XXXXXXXXXX-2.rs:4:1, - ), - }, - running_generator: Some( - ..., - ), - wait_targets: { - Change { - key: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 3, len: 0 }, - big_slots: StatePartIndexRange { start: 33, len: 1 }, - }, - write: None, - }, - value: SimValue { - ty: Clock, - bits: 0x0, - }, - }, - }, - }, - SimulationExternModuleState { - module_state: SimulationModuleState { - base_targets: [ - ModuleIO { - name: sw_reg::clk, - is_input: true, - ty: Clock, - .. - }, - ModuleIO { - name: sw_reg::o, - is_input: false, - ty: Bool, - .. - }, - ], - uninitialized_ios: {}, - io_targets: { - ModuleIO { - name: sw_reg::clk, - is_input: true, - ty: Clock, - .. - }, - ModuleIO { - name: sw_reg::o, - is_input: false, - ty: Bool, - .. - }, - }, - did_initial_settle: true, - }, - sim: ExternModuleSimulation { - generator: SimGeneratorFn { - args: ( - ModuleIO { - name: sw_reg::clk, - is_input: true, - ty: Clock, - .. - }, - ModuleIO { - name: sw_reg::o, - is_input: false, - ty: Bool, - .. - }, - ), - f: ..., - }, - source_location: SourceLocation( - module-XXXXXXXXXX-2.rs:4:1, - ), - }, - running_generator: Some( - ..., - ), - wait_targets: { - Change { - key: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 6, len: 0 }, - big_slots: StatePartIndexRange { start: 44, len: 1 }, - }, - write: None, - }, - value: SimValue { - ty: Clock, - bits: 0x0, - }, - }, - }, - }, - SimulationExternModuleState { - module_state: SimulationModuleState { - base_targets: [ - ModuleIO { - name: sw_reg::clk, - is_input: true, - ty: Clock, - .. - }, - ModuleIO { - name: sw_reg::o, - is_input: false, - ty: Bool, - .. - }, - ], - uninitialized_ios: {}, - io_targets: { - ModuleIO { - name: sw_reg::clk, - is_input: true, - ty: Clock, - .. - }, - ModuleIO { - name: sw_reg::o, - is_input: false, - ty: Bool, - .. - }, - }, - did_initial_settle: true, - }, - sim: ExternModuleSimulation { - generator: SimGeneratorFn { - args: ( - ModuleIO { - name: sw_reg::clk, - is_input: true, - ty: Clock, - .. - }, - ModuleIO { - name: sw_reg::o, - is_input: false, - ty: Bool, - .. - }, - ), - f: ..., - }, - source_location: SourceLocation( - module-XXXXXXXXXX-2.rs:4:1, - ), - }, - running_generator: Some( - ..., - ), - wait_targets: { - Change { - key: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 9, len: 0 }, - big_slots: StatePartIndexRange { start: 55, len: 1 }, - }, - write: None, - }, - value: SimValue { - ty: Clock, - bits: 0x0, - }, - }, - }, - }, - ], - state_ready_to_run: false, - trace_decls: TraceModule { - name: "ripple_counter", - children: [ - TraceModuleIO { - name: "clk", - child: TraceClock { - location: TraceScalarId(0), - name: "clk", - flow: Source, - }, - ty: Clock, - flow: Source, - }, - TraceModuleIO { - name: "o", - child: TraceUInt { - location: TraceScalarId(1), - name: "o", - ty: UInt<6>, - flow: Sink, - }, - ty: UInt<6>, - flow: Sink, - }, - TraceWire { - name: "bits", - child: TraceArray { - name: "bits", - elements: [ - TraceBool { - location: TraceScalarId(2), - name: "[0]", - flow: Duplex, - }, - TraceBool { - location: TraceScalarId(3), - name: "[1]", - flow: Duplex, - }, - TraceBool { - location: TraceScalarId(4), - name: "[2]", - flow: Duplex, - }, - TraceBool { - location: TraceScalarId(5), - name: "[3]", - flow: Duplex, - }, - TraceBool { - location: TraceScalarId(6), - name: "[4]", - flow: Duplex, - }, - TraceBool { - location: TraceScalarId(7), - name: "[5]", - flow: Duplex, - }, - ], - ty: Array, - flow: Duplex, - }, - ty: Array, - }, - TraceReg { - name: "bit_reg_0", - child: TraceBool { - location: TraceScalarId(8), - name: "bit_reg_0", - flow: Duplex, - }, - ty: Bool, - }, - TraceInstance { - name: "bit_reg_1", - instance_io: TraceBundle { - name: "bit_reg_1", - fields: [ - TraceClock { - location: TraceScalarId(11), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(12), - name: "o", - flow: Source, - }, - ], - ty: Bundle { - #[hdl(flip)] /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - o: Bool, - }, - flow: Source, - }, - module: TraceModule { - name: "sw_reg", - children: [ - TraceModuleIO { - name: "clk", - child: TraceClock { - location: TraceScalarId(9), - name: "clk", - flow: Source, - }, - ty: Clock, - flow: Source, - }, - TraceModuleIO { - name: "o", - child: TraceBool { - location: TraceScalarId(10), - name: "o", - flow: Sink, - }, - ty: Bool, - flow: Sink, - }, - ], - }, - ty: Bundle { - #[hdl(flip)] /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - o: Bool, - }, - }, - TraceReg { - name: "bit_reg_2", - child: TraceBool { - location: TraceScalarId(13), - name: "bit_reg_2", - flow: Duplex, - }, - ty: Bool, - }, - TraceInstance { - name: "bit_reg_3", - instance_io: TraceBundle { - name: "bit_reg_3", - fields: [ - TraceClock { - location: TraceScalarId(16), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(17), - name: "o", - flow: Source, - }, - ], - ty: Bundle { - #[hdl(flip)] /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - o: Bool, - }, - flow: Source, - }, - module: TraceModule { - name: "sw_reg", - children: [ - TraceModuleIO { - name: "clk", - child: TraceClock { - location: TraceScalarId(14), - name: "clk", - flow: Source, - }, - ty: Clock, - flow: Source, - }, - TraceModuleIO { - name: "o", - child: TraceBool { - location: TraceScalarId(15), - name: "o", - flow: Sink, - }, - ty: Bool, - flow: Sink, - }, - ], - }, - ty: Bundle { - #[hdl(flip)] /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - o: Bool, - }, - }, - TraceReg { - name: "bit_reg_4", - child: TraceBool { - location: TraceScalarId(18), - name: "bit_reg_4", - flow: Duplex, - }, - ty: Bool, - }, - TraceInstance { - name: "bit_reg_5", - instance_io: TraceBundle { - name: "bit_reg_5", - fields: [ - TraceClock { - location: TraceScalarId(21), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(22), - name: "o", - flow: Source, - }, - ], - ty: Bundle { - #[hdl(flip)] /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - o: Bool, - }, - flow: Source, - }, - module: TraceModule { - name: "sw_reg", - children: [ - TraceModuleIO { - name: "clk", - child: TraceClock { - location: TraceScalarId(19), - name: "clk", - flow: Source, - }, - ty: Clock, - flow: Source, - }, - TraceModuleIO { - name: "o", - child: TraceBool { - location: TraceScalarId(20), - name: "o", - flow: Sink, - }, - ty: Bool, - flow: Sink, - }, - ], - }, - ty: Bundle { - #[hdl(flip)] /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - o: Bool, - }, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigClock { - index: StatePartIndex(0), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigUInt { - index: StatePartIndex(1), - ty: UInt<6>, - }, - state: 0x00, - last_state: 0x00, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigBool { - index: StatePartIndex(2), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(3), - kind: BigBool { - index: StatePartIndex(3), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(4), - kind: BigBool { - index: StatePartIndex(4), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(5), - kind: BigBool { - index: StatePartIndex(5), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(6), - kind: BigBool { - index: StatePartIndex(6), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(7), - kind: BigBool { - index: StatePartIndex(7), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(8), - kind: BigBool { - index: StatePartIndex(24), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(9), - kind: BigClock { - index: StatePartIndex(33), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(10), - kind: BigBool { - index: StatePartIndex(34), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(11), - kind: BigClock { - index: StatePartIndex(31), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(12), - kind: BigBool { - index: StatePartIndex(32), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(13), - kind: BigBool { - index: StatePartIndex(36), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(14), - kind: BigClock { - index: StatePartIndex(44), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(15), - kind: BigBool { - index: StatePartIndex(45), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(16), - kind: BigClock { - index: StatePartIndex(42), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(17), - kind: BigBool { - index: StatePartIndex(43), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(18), - kind: BigBool { - index: StatePartIndex(47), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(19), - kind: BigClock { - index: StatePartIndex(55), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(20), - kind: BigBool { - index: StatePartIndex(56), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(21), - kind: BigClock { - index: StatePartIndex(53), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(22), - kind: BigBool { - index: StatePartIndex(54), - }, - state: 0x0, - last_state: 0x0, - }, - ], - trace_memories: {}, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - instant: 256 μs, - clocks_triggered: [ - StatePartIndex(1), - StatePartIndex(4), - StatePartIndex(7), - ], - .. -} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.vcd b/crates/fayalite/tests/sim/expected/ripple_counter.vcd deleted file mode 100644 index 6f14a8e..0000000 --- a/crates/fayalite/tests/sim/expected/ripple_counter.vcd +++ /dev/null @@ -1,1753 +0,0 @@ -$timescale 1 ps $end -$scope module ripple_counter $end -$var wire 1 ! clk $end -$var wire 6 " o $end -$scope struct bits $end -$var wire 1 # \[0] $end -$var wire 1 $ \[1] $end -$var wire 1 % \[2] $end -$var wire 1 & \[3] $end -$var wire 1 ' \[4] $end -$var wire 1 ( \[5] $end -$upscope $end -$var reg 1 ) bit_reg_0 $end -$scope struct bit_reg_1 $end -$var wire 1 , clk $end -$var wire 1 - o $end -$upscope $end -$scope module sw_reg $end -$var wire 1 * clk $end -$var wire 1 + o $end -$upscope $end -$var reg 1 . bit_reg_2 $end -$scope struct bit_reg_3 $end -$var wire 1 1 clk $end -$var wire 1 2 o $end -$upscope $end -$scope module sw_reg_2 $end -$var wire 1 / clk $end -$var wire 1 0 o $end -$upscope $end -$var reg 1 3 bit_reg_4 $end -$scope struct bit_reg_5 $end -$var wire 1 6 clk $end -$var wire 1 7 o $end -$upscope $end -$scope module sw_reg_3 $end -$var wire 1 4 clk $end -$var wire 1 5 o $end -$upscope $end -$upscope $end -$enddefinitions $end -$dumpvars -0! -b0 " -0# -0$ -0% -0& -0' -0( -0) -0* -0+ -0, -0- -0. -0/ -00 -01 -02 -03 -04 -05 -06 -07 -$end -#1000000 -1! -1) -b1 " -1# -1* -1, -1+ -b11 " -1$ -1- -1. -b111 " -1% -1/ -11 -10 -b1111 " -1& -12 -13 -b11111 " -1' -14 -16 -15 -b111111 " -1( -17 -#2000000 -0! -#3000000 -1! -0) -b111110 " -0# -0* -0, -#4000000 -0! -#5000000 -1! -1) -b111111 " -1# -1* -1, -0+ -b111101 " -0$ -0- -#6000000 -0! -#7000000 -1! -0) -b111100 " -0# -0* -0, -#8000000 -0! -#9000000 -1! -1) -b111101 " -1# -1* -1, -1+ -b111111 " -1$ -1- -0. -b111011 " -0% -0/ -01 -#10000000 -0! -#11000000 -1! -0) -b111010 " -0# -0* -0, -#12000000 -0! -#13000000 -1! -1) -b111011 " -1# -1* -1, -0+ -b111001 " -0$ -0- -#14000000 -0! -#15000000 -1! -0) -b111000 " -0# -0* -0, -#16000000 -0! -#17000000 -1! -1) -b111001 " -1# -1* -1, -1+ -b111011 " -1$ -1- -1. -b111111 " -1% -1/ -11 -00 -b110111 " -0& -02 -#18000000 -0! -#19000000 -1! -0) -b110110 " -0# -0* -0, -#20000000 -0! -#21000000 -1! -1) -b110111 " -1# -1* -1, -0+ -b110101 " -0$ -0- -#22000000 -0! -#23000000 -1! -0) -b110100 " -0# -0* -0, -#24000000 -0! -#25000000 -1! -1) -b110101 " -1# -1* -1, -1+ -b110111 " -1$ -1- -0. -b110011 " -0% -0/ -01 -#26000000 -0! -#27000000 -1! -0) -b110010 " -0# -0* -0, -#28000000 -0! -#29000000 -1! -1) -b110011 " -1# -1* -1, -0+ -b110001 " -0$ -0- -#30000000 -0! -#31000000 -1! -0) -b110000 " -0# -0* -0, -#32000000 -0! -#33000000 -1! -1) -b110001 " -1# -1* -1, -1+ -b110011 " -1$ -1- -1. -b110111 " -1% -1/ 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901cf70..73f6263 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.txt +++ b/crates/fayalite/tests/sim/expected/shift_register.txt @@ -265,72 +265,247 @@ Simulation { .. }, }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }.cd: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, }, - }.cd, - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", + ty: SyncReset, + }, + ], + .. + }, }, - }.d, - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SyncReset, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], }, - }.q, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }.cd, - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }.cd.clk, - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }.cd.rst, - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }.d, - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }.q, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 2 }, + }, + write: None, + }, + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }.cd.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }.cd.rst: CompiledValue { + layout: CompiledTypeLayout { + ty: SyncReset, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }.d: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::d", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, + }, + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }.q: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::q", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 1 }, + }, + write: None, }, - did_initial_settle: true, }, - extern_modules: [], - state_ready_to_run: false, + made_initial_step: true, + needs_settle: false, trace_decls: TraceModule { name: "shift_register", children: [ diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json index ff2050a..b284372 100644 --- a/crates/fayalite/visit_types.json +++ b/crates/fayalite/visit_types.json @@ -160,8 +160,7 @@ "data": { "$kind": "Struct", "verilog_name": "Visible", - "parameters": "Visible", - "simulation": "Visible" + "parameters": "Visible" } }, "ExternModuleParameter": { @@ -1270,11 +1269,6 @@ "$kind": "Opaque" }, "generics": "" - }, - "ExternModuleSimulation": { - "data": { - "$kind": "Opaque" - } } } } \ No newline at end of file