diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml index 7a69a7e..001168f 100644 --- a/.forgejo/workflows/test.yml +++ b/.forgejo/workflows/test.yml @@ -16,7 +16,6 @@ jobs: - uses: https://git.libre-chip.org/mirrors/rust-cache@v2 with: save-if: ${{ github.ref == 'refs/heads/master' }} - - run: rustup override set 1.93.0 - run: cargo test - run: cargo build --tests --features=unstable-doc - run: cargo test --doc --features=unstable-doc diff --git a/Cargo.lock b/Cargo.lock index 9177305..be5f3bc 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -319,12 +319,10 @@ dependencies = [ "jobslot", "num-bigint", "num-traits", - "once_cell", "ordered-float", "petgraph", "serde", "serde_json", - "sha2", "tempfile", "trybuild", "vec_map", @@ -523,9 +521,9 @@ dependencies = [ [[package]] name = "once_cell" -version = "1.21.3" +version = "1.19.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "42f5e15c9953c5e4ccceeb2e7382a716482c34515315f7b03532b8b4e8393d2d" +checksum = "3fdb12b2476b595f9358c5161aa467c2438859caa136dec86c26fdd2efe17b92" [[package]] name = "ordered-float" diff --git a/Cargo.toml b/Cargo.toml index 504d90f..2380ea7 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -11,7 +11,7 @@ edition = "2024" repository = "https://git.libre-chip.org/libre-chip/fayalite" keywords = ["hdl", "hardware", "semiconductors", "firrtl", "fpga"] categories = ["simulation", "development-tools", "compilers"] -rust-version = "1.93.0" +rust-version = "1.89.0" [workspace.dependencies] fayalite-proc-macros = { version = "=0.3.0", path = "crates/fayalite-proc-macros" } @@ -30,7 +30,6 @@ indexmap = { version = "2.5.0", features = ["serde"] } jobslot = "0.2.23" num-bigint = "0.4.6" num-traits = "0.2.16" -once_cell = "1.21.3" ordered-float = { version = "5.1.0", features = ["serde"] } petgraph = "0.8.1" prettyplease = "0.2.20" diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs index ae0f8f4..90838f0 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs @@ -888,7 +888,6 @@ impl ToTokens for ParsedEnum { #(#sim_value_from_opaque_match_arms)* } } - #[allow(irrefutable_let_patterns)] fn sim_value_clone_from_opaque( &self, value: &mut ::SimValue, diff --git a/crates/fayalite/Cargo.toml b/crates/fayalite/Cargo.toml index 1743add..fdf1c87 100644 --- a/crates/fayalite/Cargo.toml +++ b/crates/fayalite/Cargo.toml @@ -26,12 +26,10 @@ hashbrown.workspace = true jobslot.workspace = true num-bigint.workspace = true num-traits.workspace = true -once_cell.workspace = true ordered-float.workspace = true petgraph.workspace = true serde_json.workspace = true serde.workspace = true -sha2.workspace = true tempfile.workspace = true vec_map.workspace = true which.workspace = true diff --git a/crates/fayalite/src/array.rs b/crates/fayalite/src/array.rs index 6ca6809..4e2b223 100644 --- a/crates/fayalite/src/array.rs +++ b/crates/fayalite/src/array.rs @@ -109,42 +109,14 @@ impl Default for ArrayType { } } -struct MakeType(Interned); - -impl From> for Interned { - fn from(value: MakeType) -> Self { - value.0 - } -} - -impl Default for MakeType { - fn default() -> Self { - Self(T::TYPE.intern_sized()) - } -} - -struct MakeMaskType(Interned); - -impl From> for Interned { - fn from(value: MakeMaskType) -> Self { - value.0 - } -} - -impl Default for MakeMaskType { - fn default() -> Self { - Self(T::MASK_TYPE.intern_sized()) - } -} - impl StaticType for ArrayType { const TYPE: Self = Self { - element: LazyInterned::new_const::>(), + element: LazyInterned::new_lazy(&|| T::TYPE.intern_sized()), len: Len::SIZE, type_properties: Self::TYPE_PROPERTIES, }; const MASK_TYPE: Self::MaskType = ArrayType:: { - element: LazyInterned::new_const::>(), + element: LazyInterned::new_lazy(&|| T::MASK_TYPE.intern_sized()), len: Len::SIZE, type_properties: Self::MASK_TYPE_PROPERTIES, }; diff --git a/crates/fayalite/src/expr/ops.rs b/crates/fayalite/src/expr/ops.rs index f4cfebd..b8ef4f7 100644 --- a/crates/fayalite/src/expr/ops.rs +++ b/crates/fayalite/src/expr/ops.rs @@ -579,8 +579,6 @@ macro_rules! make_impls { (#[kind(i64)] $($rest:tt)*) => {make_impls! { #[type([][] (i64))] $($rest)* }}; (#[kind(i128)] $($rest:tt)*) => {make_impls! { #[type([][] (i128))] $($rest)* }}; } - -#[cfg(test)] pub(crate) use make_impls; #[cfg(test)] diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs index c461306..2d1f6d2 100644 --- a/crates/fayalite/src/int.rs +++ b/crates/fayalite/src/int.rs @@ -10,7 +10,7 @@ use crate::{ value_category::ValueCategoryValue, }, hdl, - intern::{Intern, Interned, Memoize, OnceInterned}, + intern::{Intern, Interned, Memoize}, sim::value::{SimValue, ToSimValueWithType}, source_location::SourceLocation, ty::{ @@ -65,21 +65,14 @@ pub type DynSize = ConstUsize; trait KnownSizeBaseSealed {} -impl KnownSizeBaseSealed for ConstUsize {} +impl KnownSizeBaseSealed for [(); N] {} #[expect(private_bounds)] -pub trait KnownSizeBase: KnownSizeBaseSealed + GetInternedIntCaches {} +pub trait KnownSizeBase: KnownSizeBaseSealed {} macro_rules! impl_known_size_base { ($($size:literal),* $(,)?) => { - $(impl KnownSizeBase for ConstUsize<$size> {})* - $(impl GetInternedIntCaches for ConstUsize<$size> { - #[inline(always)] - fn get_interned_int_caches() -> &'static InternedIntCaches { - static CACHES: InternedIntCaches> = InternedIntCaches::new(); - &CACHES - } - })* + $(impl KnownSizeBase for [(); $size] {})* }; } @@ -120,34 +113,12 @@ impl_known_size_base! { 0x200, } -trait GetInternedIntCaches { - fn get_interned_int_caches() -> &'static InternedIntCaches - where - Self: KnownSize; -} - -struct InternedIntCaches { - uint: OnceInterned>, - sint: OnceInterned>, -} - -impl InternedIntCaches { - const fn new() -> Self { - Self { - uint: OnceInterned::new(), - sint: OnceInterned::new(), - } - } -} - -#[expect(private_bounds)] pub trait KnownSize: GenericConstUsize + sealed::SizeTypeSealed + sealed::SizeSealed + Default + FillInDefaultedGenerics - + GetInternedIntCaches { const SIZE: Self; type ArrayMatch: AsRef<[Expr]> @@ -177,7 +148,7 @@ pub trait KnownSize: impl KnownSize for ConstUsize where - ConstUsize: KnownSizeBase, + [(); N]: KnownSizeBase, { const SIZE: Self = Self; type ArrayMatch = [Expr; N]; @@ -250,10 +221,6 @@ pub trait Size: fn from_usize(v: usize) -> Self::SizeType { Self::try_from_usize(v).expect("wrong size") } - #[doc(hidden)] - fn interned_uint(size_type: Self::SizeType) -> Interned>; - #[doc(hidden)] - fn interned_sint(size_type: Self::SizeType) -> Interned>; } impl sealed::SizeTypeSealed for usize {} @@ -262,8 +229,6 @@ impl SizeType for usize { type Size = DynSize; } -const MAX_CACHED_INT_WIDTH: usize = 1 << 10; - impl Size for DynSize { type ArrayMatch = Box<[Expr]>; type ArraySimValue = Box<[SimValue]>; @@ -277,36 +242,6 @@ impl Size for DynSize { fn try_from_usize(v: usize) -> Option { Some(v) } - - #[doc(hidden)] - fn interned_uint(size_type: Self::SizeType) -> Interned> { - static CACHED: [OnceInterned; MAX_CACHED_INT_WIDTH] = - [const { OnceInterned::new() }; _]; - #[cold] - fn intern_cold(width: usize) -> Interned { - Intern::intern_sized(UInt::new(width)) - } - if let Some(cached) = CACHED.get(size_type) { - cached.get_or_init(|| intern_cold(size_type)) - } else { - intern_cold(size_type) - } - } - - #[doc(hidden)] - fn interned_sint(size_type: Self::SizeType) -> Interned> { - static CACHED: [OnceInterned; MAX_CACHED_INT_WIDTH] = - [const { OnceInterned::new() }; _]; - #[cold] - fn intern_cold(width: usize) -> Interned { - Intern::intern_sized(SInt::new(width)) - } - if let Some(cached) = CACHED.get(size_type) { - cached.get_or_init(|| intern_cold(size_type)) - } else { - intern_cold(size_type) - } - } } impl sealed::SizeSealed for ConstUsize {} @@ -332,20 +267,6 @@ impl Size for T { fn try_from_usize(v: usize) -> Option { if v == T::VALUE { Some(T::SIZE) } else { None } } - - #[doc(hidden)] - fn interned_uint(_size_type: Self::SizeType) -> Interned> { - T::get_interned_int_caches() - .uint - .get_or_init(|| UIntType::new_static().intern_sized()) - } - - #[doc(hidden)] - fn interned_sint(_size_type: Self::SizeType) -> Interned> { - T::get_interned_int_caches() - .sint - .get_or_init(|| SIntType::new_static().intern_sized()) - } } #[derive(Clone, PartialEq, Eq, Debug)] @@ -665,7 +586,7 @@ macro_rules! impl_valueless_op_forward { } macro_rules! impl_int { - ($pretty_name:ident, $name:ident, $generic_name:ident, $value:ident, $SIGNED:literal, $interned_int:ident) => { + ($pretty_name:ident, $name:ident, $generic_name:ident, $value:ident, $SIGNED:literal) => { #[derive(Copy, Clone, PartialEq, Eq, Hash)] #[repr(transparent)] pub struct $name { @@ -1082,7 +1003,7 @@ macro_rules! impl_int { type Output = $name; fn index(&self, width: Width) -> &Self::Output { - Interned::into_inner(Width::Size::$interned_int(width)) + Interned::into_inner(Intern::intern_sized($name::new(width))) } } @@ -1263,22 +1184,8 @@ macro_rules! impl_int { }; } -impl_int!( - UInt, - UIntType, - UIntWithoutGenerics, - UIntValue, - false, - interned_uint -); -impl_int!( - SInt, - SIntType, - SIntWithoutGenerics, - SIntValue, - true, - interned_sint -); +impl_int!(UInt, UIntType, UIntWithoutGenerics, UIntValue, false); +impl_int!(SInt, SIntType, SIntWithoutGenerics, SIntValue, true); impl UInt { /// gets the smallest `UInt` that fits `v` losslessly diff --git a/crates/fayalite/src/intern.rs b/crates/fayalite/src/intern.rs index b78aa59..b68140b 100644 --- a/crates/fayalite/src/intern.rs +++ b/crates/fayalite/src/intern.rs @@ -4,191 +4,68 @@ use crate::{intern::type_map::TypeIdMap, util::DefaultBuildHasher}; use bitvec::{ptr::BitPtr, slice::BitSlice, vec::BitVec}; use hashbrown::HashTable; -use once_cell::race::OnceRef; use serde::{Deserialize, Serialize}; use std::{ any::{Any, TypeId}, borrow::{Borrow, Cow}, - cell::RefCell, cmp::Ordering, ffi::{OsStr, OsString}, fmt, hash::{BuildHasher, Hash, Hasher}, iter::FusedIterator, + marker::PhantomData, ops::Deref, path::{Path, PathBuf}, - sync::RwLock, + sync::{Mutex, RwLock}, }; -mod interner; mod type_map; -/// invariant: T must be zero-sized, `type_id` is unique for every possible T value. -struct LazyInternedLazyInner { - type_id: TypeId, - value: T, +pub trait LazyInternedTrait: Send + Sync + Any { + fn get(&self) -> Interned; } -impl Hash for LazyInternedLazyInner { - fn hash(&self, state: &mut H) { - let Self { type_id, value: _ } = self; - type_id.hash(state); +impl Interned + Send + Sync + Any> + LazyInternedTrait for F +{ + fn get(&self) -> Interned { + self() } } -impl PartialEq for LazyInternedLazyInner { - fn eq(&self, other: &Self) -> bool { - let Self { type_id, value: _ } = self; - *type_id == other.type_id - } -} +#[repr(transparent)] +pub struct LazyInternedFn(pub &'static dyn LazyInternedTrait); -impl Eq for LazyInternedLazyInner {} +impl Copy for LazyInternedFn {} -impl fmt::Debug for LazyInternedLazyInner { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_struct("LazyInternedLazyInner") - .finish_non_exhaustive() - } -} - -impl LazyInternedLazyInner { - const fn new(value: T) -> Self - where - T: Sized, - { - const { assert!(size_of::() == 0) }; - Self { - type_id: TypeId::of::(), - value, - } - } -} - -pub struct LazyInternedLazy( - &'static LazyInternedLazyInner Interned + Send + Sync>, -); - -impl LazyInternedLazy { - pub const fn new_const>>() -> Self { - Self(&const { LazyInternedLazyInner::new(|| V::default().into()) }) - } - pub const fn new_const_default() -> Self - where - Interned: Default, - { - Self::new_const::>() - } - pub fn interned(self) -> Interned { - struct Map(hashbrown::HashTable<(TypeId, &'static (dyn Any + Send + Sync))>); - impl Map { - const EMPTY: Self = Self(hashbrown::HashTable::new()); - fn get( - &self, - lazy_interned_lazy: LazyInternedLazy, - hash: u64, - ) -> Option<&'static Interned> { - let &(_, v) = self.0.find(hash, |v| v.0 == lazy_interned_lazy.0.type_id)?; - let Some(retval) = v.downcast_ref::>() else { - unreachable!(); - }; - Some(retval) - } - fn get_or_insert( - &mut self, - lazy_interned_lazy: LazyInternedLazy, - hash: u64, - v: &'static Interned, - ) -> &'static Interned { - let entry = self - .0 - .entry( - hash, - |&(k, _)| k == lazy_interned_lazy.0.type_id, - |&(k, _)| type_map::TypeIdBuildHasher.hash_one(k), - ) - .or_insert_with(|| (lazy_interned_lazy.0.type_id, v)); - let &(_, v) = entry.get(); - let Some(retval) = v.downcast_ref::>() else { - unreachable!(); - }; - retval - } - } - static GLOBAL_CACHE: RwLock = RwLock::new(Map::EMPTY); - #[cold] - fn insert_in_thread_local_cache( - cache: &RefCell, - this: LazyInternedLazy, - hash: u64, - ) -> Interned { - let read_lock = GLOBAL_CACHE.read().unwrap(); - let v = read_lock.get(this, hash); - drop(read_lock); - let v = v.unwrap_or_else(|| { - let v = Box::leak(Box::new((this.0.value)())); - GLOBAL_CACHE.write().unwrap().get_or_insert(this, hash, v) - }); - *cache.borrow_mut().get_or_insert(this, hash, v) - } - thread_local! { - static THREAD_LOCAL_CACHE: RefCell = const { RefCell::new(Map::EMPTY) }; - } - let hash = type_map::TypeIdBuildHasher.hash_one(self.0.type_id); - THREAD_LOCAL_CACHE.with(|cache| { - let borrow = cache.borrow(); - if let Some(v) = borrow.get(self, hash) { - *v - } else { - drop(borrow); - insert_in_thread_local_cache(cache, self, hash) - } - }) - } -} - -impl Copy for LazyInternedLazy {} - -impl Clone for LazyInternedLazy { +impl Clone for LazyInternedFn { fn clone(&self) -> Self { *self } } -impl Hash for LazyInternedLazy { +impl Hash for LazyInternedFn { fn hash(&self, state: &mut H) { - self.0.hash(state); + self.0.get_ptr_eq_with_type_id().hash(state); } } -impl Eq for LazyInternedLazy {} +impl Eq for LazyInternedFn {} -impl PartialEq for LazyInternedLazy { +impl PartialEq for LazyInternedFn { fn eq(&self, other: &Self) -> bool { - self.0 == other.0 + self.0.get_ptr_eq_with_type_id() == other.0.get_ptr_eq_with_type_id() } } pub enum LazyInterned { Interned(Interned), - Lazy(LazyInternedLazy), + Lazy(LazyInternedFn), } impl LazyInterned { - pub const fn new_const>>() -> Self { - Self::Lazy(LazyInternedLazy::new_const::()) - } - pub const fn new_const_default() -> Self - where - Interned: Default, - { - Self::new_const::>() - } - pub fn interned(self) -> Interned { - match self { - Self::Interned(retval) => retval, - Self::Lazy(retval) => retval.interned(), - } + pub const fn new_lazy(v: &'static dyn LazyInternedTrait) -> Self { + Self::Lazy(LazyInternedFn(v)) } } @@ -200,7 +77,7 @@ impl Clone for LazyInterned { impl Copy for LazyInterned {} -impl Deref for LazyInterned { +impl Deref for LazyInterned { type Target = T; fn deref(&self) -> &Self::Target { @@ -208,9 +85,9 @@ impl Deref for LazyInterned { } } -impl Eq for LazyInterned where Interned: Eq {} +impl Eq for LazyInterned where Interned: Eq {} -impl PartialEq for LazyInterned +impl PartialEq for LazyInterned where Interned: PartialEq, { @@ -219,7 +96,7 @@ where } } -impl Ord for LazyInterned +impl Ord for LazyInterned where Interned: Ord, { @@ -228,7 +105,7 @@ where } } -impl PartialOrd for LazyInterned +impl PartialOrd for LazyInterned where Interned: PartialOrd, { @@ -237,7 +114,7 @@ where } } -impl Hash for LazyInterned +impl Hash for LazyInterned where Interned: Hash, { @@ -246,6 +123,77 @@ where } } +impl LazyInterned { + pub fn interned(self) -> Interned + where + T: Intern, + { + struct MemoizeInterned(PhantomData); + + impl Hash for MemoizeInterned { + fn hash(&self, _state: &mut H) {} + } + + impl PartialEq for MemoizeInterned { + fn eq(&self, _other: &Self) -> bool { + true + } + } + + impl Eq for MemoizeInterned {} + + impl Clone for MemoizeInterned { + fn clone(&self) -> Self { + *self + } + } + + impl Copy for MemoizeInterned {} + + impl MemoizeGeneric for MemoizeInterned { + type InputRef<'a> = LazyInternedFn; + + type InputOwned = LazyInternedFn; + + type InputCow<'a> = LazyInternedFn; + + type Output = Interned; + + fn input_eq(a: Self::InputRef<'_>, b: Self::InputRef<'_>) -> bool { + a == b + } + + fn input_borrow(input: &Self::InputOwned) -> Self::InputRef<'_> { + *input + } + + fn input_cow_into_owned(input: Self::InputCow<'_>) -> Self::InputOwned { + input + } + + fn input_cow_borrow<'a>(input: &'a Self::InputCow<'_>) -> Self::InputRef<'a> { + *input + } + + fn input_cow_from_owned<'a>(input: Self::InputOwned) -> Self::InputCow<'a> { + input + } + + fn input_cow_from_ref(input: Self::InputRef<'_>) -> Self::InputCow<'_> { + input + } + + fn inner(self, input: Self::InputRef<'_>) -> Self::Output { + input.0.get() + } + } + match self { + Self::Interned(retval) => retval, + Self::Lazy(retval) => MemoizeInterned(PhantomData).get(retval), + } + } +} + pub trait InternedCompare { type InternedCompareKey: Ord + Hash; fn interned_compare_key_ref(this: &Self) -> Self::InternedCompareKey; @@ -645,6 +593,71 @@ impl From> for Cow<'_, } } +struct InternerState { + table: HashTable<&'static T>, + hasher: DefaultBuildHasher, +} + +pub struct Interner { + state: Mutex>, +} + +impl Interner { + fn get() -> &'static Interner { + static TYPE_ID_MAP: TypeIdMap = TypeIdMap::new(); + TYPE_ID_MAP.get_or_insert_default() + } +} + +impl Default for Interner { + fn default() -> Self { + Self { + state: Mutex::new(InternerState { + table: HashTable::new(), + hasher: Default::default(), + }), + } + } +} + +impl Interner { + fn intern) -> &'static T>( + &self, + alloc: F, + value: Cow<'_, T>, + ) -> Interned { + let mut state = self.state.lock().unwrap(); + let InternerState { table, hasher } = &mut *state; + let inner = *table + .entry( + hasher.hash_one(&*value), + |k| **k == *value, + |k| hasher.hash_one(&**k), + ) + .or_insert_with(|| alloc(value)) + .get(); + Interned { inner } + } +} + +impl Interner { + fn intern_sized(&self, value: Cow<'_, T>) -> Interned { + self.intern(|value| Box::leak(Box::new(value.into_owned())), value) + } +} + +impl Interner<[T]> { + fn intern_slice(&self, value: Cow<'_, [T]>) -> Interned<[T]> { + self.intern(|value| value.into_owned().leak(), value) + } +} + +impl Interner { + fn intern_bit_slice(&self, value: Cow<'_, BitSlice>) -> Interned { + self.intern(|value| value.into_owned().leak(), value) + } +} + pub struct Interned { inner: &'static T, } @@ -964,7 +977,7 @@ impl Intern for T { where Self: ToOwned, { - interner::Interner::get().intern_sized(this) + Interner::get().intern_sized(this) } } @@ -984,7 +997,7 @@ impl Intern for [T] { where Self: ToOwned, { - interner::Interner::get().intern_slice(this) + Interner::get().intern_slice(this) } } @@ -1004,7 +1017,7 @@ impl Intern for BitSlice { where Self: ToOwned, { - interner::Interner::get().intern_bit_slice(this) + Interner::get().intern_bit_slice(this) } } @@ -1022,17 +1035,10 @@ pub trait MemoizeGeneric: 'static + Send + Sync + Hash + Eq + Copy { fn inner(self, input: Self::InputRef<'_>) -> Self::Output; fn get_cow(self, input: Self::InputCow<'_>) -> Self::Output { static TYPE_ID_MAP: TypeIdMap = TypeIdMap::new(); - thread_local! { - static TYPE_ID_MAP_CACHE: TypeIdMap = const { TypeIdMap::new() }; - } let map: &RwLock<( DefaultBuildHasher, HashTable<(Self, Self::InputOwned, Self::Output)>, - )> = TYPE_ID_MAP_CACHE.with(|cache| { - cache.get_or_insert_with(|| { - TYPE_ID_MAP.get_or_insert_with(|| Box::leak(Default::default())) - }) - }); + )> = TYPE_ID_MAP.get_or_insert_default(); fn hash_eq_key<'a, 'b, T: MemoizeGeneric>( this: &'a T, input: T::InputRef<'b>, @@ -1134,35 +1140,3 @@ pub trait Memoize: 'static + Send + Sync + Hash + Eq + Copy { self.get_cow(Cow::Borrowed(input)) } } - -/// like `once_cell::race::OnceBox` but for `Interned` instead of `Box` -pub struct OnceInterned(OnceRef<'static, T>); - -impl fmt::Debug for OnceInterned { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_tuple("OnceInterned").field(&self.get()).finish() - } -} - -impl Default for OnceInterned { - fn default() -> Self { - Self::new() - } -} - -impl OnceInterned { - pub const fn new() -> Self { - Self(OnceRef::new()) - } - pub fn set(&self, v: Interned) -> Result<(), ()> { - self.0.set(v.inner) - } - pub fn get(&self) -> Option> { - self.0.get().map(|inner| Interned { inner }) - } - pub fn get_or_init Interned>(&self, f: F) -> Interned { - Interned { - inner: self.0.get_or_init(|| f().inner), - } - } -} diff --git a/crates/fayalite/src/intern/interner.rs b/crates/fayalite/src/intern/interner.rs deleted file mode 100644 index 4e35636..0000000 --- a/crates/fayalite/src/intern/interner.rs +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: LGPL-3.0-or-later -// See Notices.txt for copyright information - -use crate::{ - intern::{Interned, type_map::TypeIdMap}, - util::DefaultBuildHasher, -}; -use bitvec::slice::BitSlice; -use hashbrown::HashTable; -use std::{ - borrow::Cow, - hash::{BuildHasher, Hash}, - sync::RwLock, -}; - -struct InternerShard { - table: HashTable<&'static T>, -} - -const LOG2_SHARD_COUNT: u32 = 6; - -fn shard_index_from_hash(hash: u64) -> usize { - // number of bits used for hashbrown's Tag - const HASH_BROWN_TAG_BITS: u32 = 7; - // try to extract bits of the hash that hashbrown isn't using, - // while accounting for some hash functions only returning `usize` bits. - const SHARD_INDEX_START: u32 = usize::BITS - .saturating_sub(HASH_BROWN_TAG_BITS) - .saturating_sub(LOG2_SHARD_COUNT); - let mut shard_index = hash >> SHARD_INDEX_START; - shard_index %= 1 << LOG2_SHARD_COUNT; - shard_index as usize -} - -pub(crate) struct Interner { - shards: [RwLock>; 1 << LOG2_SHARD_COUNT], - hasher: DefaultBuildHasher, -} - -impl Interner { - pub(crate) fn get() -> &'static Interner { - static TYPE_ID_MAP: TypeIdMap = TypeIdMap::new(); - thread_local! { - static TYPE_ID_MAP_CACHE: TypeIdMap = const { TypeIdMap::new() }; - } - TYPE_ID_MAP_CACHE.with(|cache| { - cache.get_or_insert_with(|| { - TYPE_ID_MAP.get_or_insert_with(|| Box::leak(Default::default())) - }) - }) - } -} - -impl Default for Interner { - fn default() -> Self { - Self { - shards: [const { - RwLock::new(InternerShard { - table: HashTable::new(), - }) - }; _], - hasher: Default::default(), - } - } -} - -impl Interner { - fn intern) -> &'static T>( - &self, - alloc: F, - value: Cow<'_, T>, - ) -> Interned { - let hash = self.hasher.hash_one(&*value); - let shard_index = shard_index_from_hash(hash); - let shard = &self.shards[shard_index]; - let shard_read = shard.read().unwrap(); - let Some(&inner) = shard_read.table.find(hash, |k| **k == *value) else { - drop(shard_read); - return self.intern_cold(alloc, value, hash, shard); - }; - Interned { inner } - } - #[cold] - fn intern_cold) -> &'static T>( - &self, - alloc: F, - value: Cow<'_, T>, - hash: u64, - shard: &RwLock>, - ) -> Interned { - let mut shard = shard.write().unwrap(); - let inner = *shard - .table - .entry(hash, |k| **k == *value, |k| self.hasher.hash_one(&**k)) - .or_insert_with(|| alloc(value)) - .get(); - Interned { inner } - } -} - -impl Interner { - pub(crate) fn intern_sized(&self, value: Cow<'_, T>) -> Interned { - self.intern(|value| Box::leak(Box::new(value.into_owned())), value) - } -} - -impl Interner<[T]> { - pub(crate) fn intern_slice(&self, value: Cow<'_, [T]>) -> Interned<[T]> { - self.intern(|value| value.into_owned().leak(), value) - } -} - -impl Interner { - pub(crate) fn intern_bit_slice(&self, value: Cow<'_, BitSlice>) -> Interned { - self.intern(|value| value.into_owned().leak(), value) - } -} diff --git a/crates/fayalite/src/intern/type_map.rs b/crates/fayalite/src/intern/type_map.rs index e31a5bf..945116b 100644 --- a/crates/fayalite/src/intern/type_map.rs +++ b/crates/fayalite/src/intern/type_map.rs @@ -6,7 +6,7 @@ use std::{ sync::RwLock, }; -pub(crate) struct TypeIdHasher(u64); +struct TypeIdHasher(u64); // assumes TypeId has at least 64 bits that is a good hash impl Hasher for TypeIdHasher { @@ -63,7 +63,7 @@ impl Hasher for TypeIdHasher { } } -pub(crate) struct TypeIdBuildHasher; +struct TypeIdBuildHasher; impl BuildHasher for TypeIdBuildHasher { type Hasher = TypeIdHasher; @@ -87,23 +87,20 @@ impl TypeIdMap { fn insert_slow( &self, type_id: TypeId, - make: impl FnOnce() -> &'static (dyn Any + Sync + Send), + make: fn() -> Box, ) -> &'static (dyn Any + Sync + Send) { - let value = make(); + let value = Box::leak(make()); let mut write_guard = self.0.write().unwrap(); *write_guard.entry(type_id).or_insert(value) } - pub(crate) fn get_or_insert_with( - &self, - make: impl FnOnce() -> &'static T, - ) -> &'static T { + pub(crate) fn get_or_insert_default(&self) -> &T { let type_id = TypeId::of::(); let read_guard = self.0.read().unwrap(); let retval = read_guard.get(&type_id).map(|v| *v); drop(read_guard); let retval = match retval { Some(retval) => retval, - None => self.insert_slow(type_id, move || make()), + None => self.insert_slow(type_id, move || Box::new(T::default())), }; retval.downcast_ref().expect("known to have correct TypeId") } diff --git a/crates/fayalite/src/phantom_const.rs b/crates/fayalite/src/phantom_const.rs index fb7be6f..32e9d6b 100644 --- a/crates/fayalite/src/phantom_const.rs +++ b/crates/fayalite/src/phantom_const.rs @@ -4,7 +4,7 @@ use crate::{ expr::{Expr, HdlPartialEqImpl, HdlPartialOrdImpl, ToExpr, ValueType}, int::Bool, - intern::{Intern, Interned, InternedCompare, LazyInterned, Memoize}, + intern::{Intern, Interned, InternedCompare, LazyInterned, LazyInternedTrait, Memoize}, sim::value::{SimValue, ToSimValue, ToSimValueWithType}, source_location::SourceLocation, ty::{ @@ -240,17 +240,11 @@ impl PhantomConst { { Self::new_interned(value.intern_deref()) } - pub const fn new_const>>() -> Self { + pub const fn new_lazy(v: &'static dyn LazyInternedTrait) -> Self { Self { - value: LazyInterned::new_const::(), + value: LazyInterned::new_lazy(v), } } - pub const fn new_const_default() -> Self - where - Interned: Default, - { - Self::new_const::>() - } pub fn get(self) -> Interned { self.value.interned() } @@ -340,7 +334,9 @@ impl StaticType for PhantomConst where Interned: Default, { - const TYPE: Self = Self::new_const_default(); + const TYPE: Self = PhantomConst { + value: LazyInterned::new_lazy(&Interned::::default), + }; const MASK_TYPE: Self::MaskType = (); const TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES; const MASK_TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES; diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index 002161e..a59a4c7 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -40,7 +40,7 @@ use crate::{ OpaqueSimValue, OpaqueSimValueSize, OpaqueSimValueSizeRange, OpaqueSimValueSlice, OpaqueSimValueWriter, }, - util::{BitSliceWriteWithBase, DebugAsDisplay, HashMap, HashSet, copy_le_bytes_to_bitslice}, + util::{BitSliceWriteWithBase, DebugAsDisplay, HashMap, HashSet}, }; use bitvec::{bits, order::Lsb0, slice::BitSlice, vec::BitVec, view::BitView}; use num_bigint::BigInt; @@ -2198,11 +2198,14 @@ impl SimulationImpl { SimTraceKind::BigUInt { index, ty: _ } | SimTraceKind::BigSInt { index, ty: _ } => { let state = state.unwrap_bits_mut(); let bigint = &self.state.big_slots[index]; - copy_le_bytes_to_bitslice( - state, - &bigint.to_signed_bytes_le(), - bigint.is_negative(), + let mut bytes = bigint.to_signed_bytes_le(); + bytes.resize( + state.len().div_ceil(8), + if bigint.is_negative() { 0xFF } else { 0 }, ); + let bitslice = BitSlice::::from_slice(&bytes); + let bitslice = &bitslice[..state.len()]; + state.clone_from_bitslice(bitslice); } SimTraceKind::BigBool { index } | SimTraceKind::BigAsyncReset { index } diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs index d970eb0..6ba37b3 100644 --- a/crates/fayalite/src/sim/vcd.rs +++ b/crates/fayalite/src/sim/vcd.rs @@ -21,30 +21,14 @@ use crate::{ }; use bitvec::{order::Lsb0, slice::BitSlice}; use hashbrown::hash_map::Entry; -use sha2::{Digest, Sha256}; use std::{ - collections::BTreeMap, fmt::{self, Write as _}, io, mem, }; -#[derive(Default, Clone)] -struct PathHash(Sha256); - -impl PathHash { - fn joined(mut self, segment: impl AsRef<[u8]>) -> Self { - let segment = segment.as_ref(); - self.0.update(u32::to_le_bytes( - segment.len().try_into().expect("path segment is too big"), - )); - self.0.update(segment); - self - } -} - +#[derive(Default)] struct Scope { last_inserted: HashMap, usize>, - path_hash: PathHash, } #[derive(Copy, Clone)] @@ -77,13 +61,6 @@ impl fmt::Display for VerilogIdentifier { } impl Scope { - fn new(path_hash: PathHash) -> Self { - Self { - last_inserted: Default::default(), - path_hash, - } - } - fn new_identifier(&mut self, unescaped_name: Interned) -> VerilogIdentifier { let next_disambiguator = match self.last_inserted.entry(unescaped_name) { Entry::Vacant(entry) => { @@ -194,10 +171,12 @@ fn write_vcd_scope( scope: &mut Scope, f: impl FnOnce(&mut W, &mut Scope) -> io::Result, ) -> io::Result { - let path_hash = scope.path_hash.clone().joined(scope_name); - let scope_name = scope.new_identifier(scope_name); - writeln!(writer, "$scope {scope_type} {scope_name} $end")?; - let retval = f(writer, &mut Scope::new(path_hash))?; + writeln!( + writer, + "$scope {scope_type} {} $end", + scope.new_identifier(scope_name), + )?; + let retval = f(writer, &mut Scope::default())?; writeln!(writer, "$upscope $end")?; Ok(retval) } @@ -312,75 +291,19 @@ impl WriteTrace for TraceScalar { } } -#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)] -#[repr(transparent)] -struct VcdId(u64); - -impl VcdId { - const CHAR_RANGE: std::ops::RangeInclusive = b'!'..=b'~'; - const BASE: u8 = *Self::CHAR_RANGE.end() - *Self::CHAR_RANGE.start() + 1; - const LOW_HALF_CHARS: u32 = 5; - const LOW_HALF_MODULUS: u64 = (Self::BASE as u64).pow(Self::LOW_HALF_CHARS); - - const fn from_str(s: &str) -> Option { - if s.is_empty() { - return None; +fn write_vcd_id(writer: &mut W, mut id: usize) -> io::Result<()> { + let min_char = b'!'; + let max_char = b'~'; + let base = (max_char - min_char + 1) as usize; + loop { + let digit = (id % base) as u8 + min_char; + id /= base; + writer.write_all(&[digit])?; + if id == 0 { + break; } - let mut retval = 0u64; - let mut bytes = s.as_bytes(); - while let [ref rest @ .., digit] = *bytes { - bytes = rest; - let Some(digit) = digit.checked_sub(*Self::CHAR_RANGE.start()) else { - return None; - }; - if digit >= Self::BASE { - return None; - } - let Some(v) = retval.checked_mul(Self::BASE as _) else { - return None; - }; - let Some(v) = v.checked_add(digit as _) else { - return None; - }; - retval = v; - } - Some(Self(retval)) } - #[must_use] - const fn write(self, out: &mut [u8]) -> usize { - let mut id = self.0; - let mut len = 0; - loop { - let digit = (id % Self::BASE as u64) as u8 + *Self::CHAR_RANGE.start(); - id /= Self::BASE as u64; - if len < out.len() { - out[len] = digit; - } - len += 1; - if id == 0 { - break; - } - } - len - } - const MAX_ID_LEN: usize = Self(u64::MAX).write(&mut []); -} - -/// check that VcdId properly round-trips -const _: () = { - let s = "RoundTrip"; - let Some(id) = VcdId::from_str(s) else { - unreachable!(); - }; - let mut buf = [0u8; VcdId::MAX_ID_LEN]; - let len = id.write(&mut buf); - assert!(crate::util::const_bytes_cmp(buf.split_at(len).0, s.as_bytes()).is_eq()); -}; - -fn write_vcd_id(writer: &mut W, id: VcdId) -> io::Result<()> { - let mut buf = [0u8; VcdId::MAX_ID_LEN]; - let len = id.write(&mut buf); - writer.write_all(&buf[..len]) + Ok(()) } struct Escaped(T); @@ -423,16 +346,13 @@ impl fmt::Display for Escaped { fn write_vcd_var( properties: &mut VcdWriterProperties, - scope: &mut Scope, memory_element_part_body: MemoryElementPartBody, writer: &mut W, var_type: &str, size: usize, location: TraceLocation, - name: Interned, + name: VerilogIdentifier, ) -> io::Result<()> { - let path_hash = scope.path_hash.clone().joined(name); - let name = scope.new_identifier(name); let id = match location { TraceLocation::Scalar(id) => id.as_usize(), TraceLocation::Memory(TraceMemoryLocation { @@ -464,9 +384,6 @@ fn write_vcd_var( first_id + *element_index } }; - let id = properties - .scalar_id_to_vcd_id_map - .builder_get_or_insert(id, &path_hash); write!(writer, "$var {var_type} {size} ")?; write_vcd_id(writer, id)?; writeln!(writer, " {name} $end") @@ -497,13 +414,12 @@ impl WriteTrace for TraceUInt { } write_vcd_var( properties, - scope, MemoryElementPartBody::Scalar, writer, var_type, ty.width(), location, - name, + scope.new_identifier(name), ) } } @@ -578,13 +494,12 @@ impl WriteTrace for TraceEnumDiscriminant { } = self; write_vcd_var( properties, - scope, MemoryElementPartBody::EnumDiscriminant { ty }, writer, "string", 1, location, - name, + scope.new_identifier(name), ) } } @@ -654,13 +569,12 @@ impl WriteTrace for TracePhantomConst { } = self; write_vcd_var( properties, - scope, MemoryElementPartBody::Scalar, writer, "string", 1, location, - name, + scope.new_identifier(name), ) } } @@ -682,13 +596,12 @@ impl WriteTrace for TraceSimOnly { } = self; write_vcd_var( properties, - scope, MemoryElementPartBody::Scalar, writer, "string", 1, location, - name, + scope.new_identifier(name), ) } } @@ -1010,9 +923,6 @@ impl TraceWriterDecls for VcdWriterDecls { writeln!(writer, "$timescale {} $end", vcd_timescale(timescale))?; let mut properties = VcdWriterProperties { next_scalar_id: trace_scalar_id_count, - scalar_id_to_vcd_id_map: ScalarIdToVcdIdMapOrBuilder::Builder( - ScalarIdToVcdIdMapBuilder::default(), - ), memory_properties: (0..trace_memory_id_count) .map(|_| MemoryProperties { element_parts: Vec::with_capacity(8), @@ -1025,16 +935,9 @@ impl TraceWriterDecls for VcdWriterDecls { &mut writer, ArgModule { properties: &mut properties, - scope: &mut Scope::new(PathHash::default()), + scope: &mut Scope::default(), }, )?; - let ScalarIdToVcdIdMapOrBuilder::Builder(scalar_id_to_vcd_id_map_builder) = - properties.scalar_id_to_vcd_id_map - else { - unreachable!(); - }; - properties.scalar_id_to_vcd_id_map = - ScalarIdToVcdIdMapOrBuilder::Built(scalar_id_to_vcd_id_map_builder.build()); writeln!(writer, "$enddefinitions $end")?; writeln!(writer, "$dumpvars")?; Ok(VcdWriter { @@ -1064,88 +967,8 @@ struct MemoryProperties { element_index: usize, } -struct ScalarIdToVcdIdMap { - scalar_id_to_vcd_id_map: Box<[VcdId]>, -} - -#[derive(Default)] -struct ScalarIdToVcdIdMapBuilder { - scalar_id_to_vcd_id_map: BTreeMap, - lower_half_to_next_upper_half_map: HashMap, -} - -impl ScalarIdToVcdIdMapBuilder { - /// `VcdId`s are based off of `path_hash` (and not `scalar_id`) since the hash doesn't change - /// when unrelated variables are added/removed, making the generated VCD more friendly for git diff. - fn get_or_insert(&mut self, scalar_id: usize, path_hash: &PathHash) -> VcdId { - *self - .scalar_id_to_vcd_id_map - .entry(scalar_id) - .or_insert_with(|| { - let hash = u128::from_le_bytes( - *path_hash - .0 - .clone() - .finalize() - .first_chunk() - .expect("known to be bigger than u128"), - ); - let lower_half = (hash % VcdId::LOW_HALF_MODULUS as u128) as u64; - let next_upper_half = self - .lower_half_to_next_upper_half_map - .entry(lower_half) - .or_insert(0); - let upper_half = *next_upper_half; - *next_upper_half += 1; - let Some(id) = upper_half - .checked_mul(VcdId::LOW_HALF_MODULUS) - .and_then(|v| v.checked_add(lower_half)) - else { - panic!("too many VcdIds"); - }; - VcdId(id) - }) - } - fn build(self) -> ScalarIdToVcdIdMap { - ScalarIdToVcdIdMap { - scalar_id_to_vcd_id_map: self - .scalar_id_to_vcd_id_map - .into_iter() - .enumerate() - .map(|(index, (scalar_id, vcd_id))| { - if index != scalar_id { - panic!("missing scalar id {index}"); - } - vcd_id - }) - .collect(), - } - } -} - -enum ScalarIdToVcdIdMapOrBuilder { - Builder(ScalarIdToVcdIdMapBuilder), - Built(ScalarIdToVcdIdMap), -} - -impl ScalarIdToVcdIdMapOrBuilder { - fn built_scalar_id_to_vcd_id(&self, scalar_id: usize) -> VcdId { - let Self::Built(v) = self else { - panic!("ScalarIdToVcdIdMap isn't built yet"); - }; - v.scalar_id_to_vcd_id_map[scalar_id] - } - fn builder_get_or_insert(&mut self, scalar_id: usize, path_hash: &PathHash) -> VcdId { - let Self::Builder(v) = self else { - panic!("ScalarIdToVcdIdMap is already built"); - }; - v.get_or_insert(scalar_id, path_hash) - } -} - struct VcdWriterProperties { next_scalar_id: usize, - scalar_id_to_vcd_id_map: ScalarIdToVcdIdMapOrBuilder, memory_properties: Box<[MemoryProperties]>, } @@ -1165,7 +988,7 @@ impl VcdWriter { fn write_string_value_change( writer: &mut impl io::Write, value: impl fmt::Display, - id: VcdId, + id: usize, ) -> io::Result<()> { write!(writer, "s{} ", Escaped(value))?; write_vcd_id(writer, id)?; @@ -1175,7 +998,7 @@ fn write_string_value_change( fn write_bits_value_change( writer: &mut impl io::Write, value: &BitSlice, - id: VcdId, + id: usize, ) -> io::Result<()> { match value.len() { 0 => writer.write_all(b"s0 ")?, @@ -1205,7 +1028,7 @@ fn write_enum_discriminant_value_change( writer: &mut impl io::Write, variant_index: usize, ty: Enum, - id: VcdId, + id: usize, ) -> io::Result<()> { write_string_value_change( writer, @@ -1240,9 +1063,7 @@ impl TraceWriter for VcdWriter { MemoryElementPartBody::Scalar => write_bits_value_change( &mut self.writer, &element_data[start..start + len], - self.properties - .scalar_id_to_vcd_id_map - .built_scalar_id_to_vcd_id(first_id + element_index), + first_id + element_index, )?, MemoryElementPartBody::EnumDiscriminant { ty } => { let mut variant_index = 0; @@ -1252,9 +1073,7 @@ impl TraceWriter for VcdWriter { &mut self.writer, variant_index, *ty, - self.properties - .scalar_id_to_vcd_id_map - .built_scalar_id_to_vcd_id(first_id + element_index), + first_id + element_index, )? } } @@ -1263,23 +1082,11 @@ impl TraceWriter for VcdWriter { } fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> { - write_bits_value_change( - &mut self.writer, - value, - self.properties - .scalar_id_to_vcd_id_map - .built_scalar_id_to_vcd_id(id.as_usize()), - ) + write_bits_value_change(&mut self.writer, value, id.as_usize()) } fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> { - write_bits_value_change( - &mut self.writer, - value, - self.properties - .scalar_id_to_vcd_id_map - .built_scalar_id_to_vcd_id(id.as_usize()), - ) + write_bits_value_change(&mut self.writer, value, id.as_usize()) } fn finish_init(&mut self) -> Result<(), Self::Error> { @@ -1311,14 +1118,7 @@ impl TraceWriter for VcdWriter { variant_index: usize, ty: Enum, ) -> Result<(), Self::Error> { - write_enum_discriminant_value_change( - &mut self.writer, - variant_index, - ty, - self.properties - .scalar_id_to_vcd_id_map - .built_scalar_id_to_vcd_id(id.as_usize()), - ) + write_enum_discriminant_value_change(&mut self.writer, variant_index, ty, id.as_usize()) } fn set_signal_phantom_const( @@ -1328,13 +1128,7 @@ impl TraceWriter for VcdWriter { ) -> Result<(), Self::Error> { // avoid multi-line strings because GTKWave can't display them properly: // https://github.com/gtkwave/gtkwave/issues/460 - write_string_value_change( - &mut self.writer, - format_args!("{ty:?}"), - self.properties - .scalar_id_to_vcd_id_map - .built_scalar_id_to_vcd_id(id.as_usize()), - ) + write_string_value_change(&mut self.writer, format_args!("{ty:?}"), id.as_usize()) } fn set_signal_sim_only_value( @@ -1342,13 +1136,7 @@ impl TraceWriter for VcdWriter { id: TraceScalarId, value: &DynSimOnlyValue, ) -> Result<(), Self::Error> { - write_string_value_change( - &mut self.writer, - format_args!("{value:?}"), - self.properties - .scalar_id_to_vcd_id_map - .built_scalar_id_to_vcd_id(id.as_usize()), - ) + write_string_value_change(&mut self.writer, format_args!("{value:?}"), id.as_usize()) } } @@ -1373,7 +1161,7 @@ mod tests { #[test] fn test_scope() { - let mut scope = Scope::new(PathHash::default()); + let mut scope = Scope::default(); assert_eq!(&*scope.new_identifier("foo".intern()).unescaped_name, "foo"); assert_eq!( &*scope.new_identifier("foo_0".intern()).unescaped_name, diff --git a/crates/fayalite/src/util.rs b/crates/fayalite/src/util.rs index f1457de..9796488 100644 --- a/crates/fayalite/src/util.rs +++ b/crates/fayalite/src/util.rs @@ -41,7 +41,7 @@ pub use misc::{ os_str_strip_suffix, serialize_to_json_ascii, serialize_to_json_ascii_pretty, serialize_to_json_ascii_pretty_with_indent, slice_range, try_slice_range, }; -pub(crate) use misc::{InternedStrCompareAsStr, chain, copy_le_bytes_to_bitslice}; +pub(crate) use misc::{InternedStrCompareAsStr, chain}; pub mod job_server; pub mod prefix_sum; diff --git a/crates/fayalite/src/util/misc.rs b/crates/fayalite/src/util/misc.rs index 8879a8d..165ab3a 100644 --- a/crates/fayalite/src/util/misc.rs +++ b/crates/fayalite/src/util/misc.rs @@ -612,43 +612,3 @@ impl std::borrow::Borrow for InternedStrCompareAsStr { &self.0 } } - -pub(crate) fn copy_le_bytes_to_bitslice( - dest: &mut BitSlice, - bytes: &[u8], - msb_fill: bool, -) { - let (chunks, remainder) = bytes.as_chunks(); - let mut filled_to = 0; - for (i, chunk) in chunks.iter().enumerate() { - if let Some(start_bit_index) = i.checked_mul(usize::BITS as usize) - && start_bit_index < dest.len() - { - let end_bit_index = start_bit_index - .saturating_add(usize::BITS as usize) - .min(dest.len()); - let bit_len = end_bit_index - start_bit_index; - let chunk = usize::from_le_bytes(*chunk); - dest[start_bit_index..end_bit_index].copy_from_bitslice(&chunk.view_bits()[..bit_len]); - filled_to = end_bit_index; - } else { - break; - } - } - if !remainder.is_empty() { - if let Some(start_bit_index) = chunks.len().checked_mul(usize::BITS as usize) - && start_bit_index < dest.len() - { - let end_bit_index = start_bit_index - .saturating_add(usize::BITS as usize) - .min(dest.len()); - let bit_len = end_bit_index - start_bit_index; - let mut chunk = [if msb_fill { !0 } else { 0 }; _]; - chunk[..remainder.len()].copy_from_slice(remainder); - let chunk = usize::from_le_bytes(chunk); - dest[start_bit_index..end_bit_index].copy_from_bitslice(&chunk.view_bits()[..bit_len]); - filled_to = end_bit_index; - } - } - dest[filled_to..].fill(msb_fill); -} diff --git a/crates/fayalite/src/vendor/lattice.rs b/crates/fayalite/src/vendor/lattice.rs new file mode 100644 index 0000000..1c2d5c2 --- /dev/null +++ b/crates/fayalite/src/vendor/lattice.rs @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information + +use crate::{ + annotations::make_annotation_enum, + build::{GlobalParams, ToArgs, WriteArgs}, + intern::Interned, + prelude::{DynPlatform, Platform}, +}; +use clap::ValueEnum; +use ordered_float::NotNan; +use serde::{Deserialize, Serialize}; +use std::fmt; + +// copy of xilinx.rs with same header diff --git a/crates/fayalite/src/vendor/lattice/orangecrab.rs b/crates/fayalite/src/vendor/lattice/orangecrab.rs new file mode 100644 index 0000000..552eb4a --- /dev/null +++ b/crates/fayalite/src/vendor/lattice/orangecrab.rs @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information + +use crate::{ + intern::{Intern, Interned}, + module::{instance_with_loc, reg_builder_with_loc, wire_with_loc}, + platform::{ + DynPlatform, Peripheral, PeripheralRef, Peripherals, PeripheralsBuilderFactory, + PeripheralsBuilderFinished, Platform, PlatformAspectSet, + peripherals::{ClockInput, Led, RgbLed, Uart}, + }, + prelude::*, + vendor::xilinx::{ + Device, XdcCreateClockAnnotation, XdcIOStandardAnnotation, XdcLocationAnnotation, + primitives, + }, +}; +use ordered_float::NotNan; +use std::sync::OnceLock; + +macro_rules! arty_a7_platform { + ( + $vis:vis enum $ArtyA7Platform:ident { + $(#[name = $name:literal, device = $device:ident] + $Variant:ident,)* + } + ) => { + #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)] + #[non_exhaustive] + $vis enum $ArtyA7Platform { + $($Variant,)* + } + + impl $ArtyA7Platform { + $vis const VARIANTS: &'static [Self] = &[$(Self::$Variant,)*]; + $vis fn device(self) -> Device { + match self { + $(Self::$Variant => Device::$device,)* + } + } + $vis const fn as_str(self) -> &'static str { + match self { + $(Self::$Variant => $name,)* + } + } + fn get_aspects(self) -> &'static PlatformAspectSet { + match self { + $(Self::$Variant => { + static ASPECTS_SET: OnceLock = OnceLock::new(); + ASPECTS_SET.get_or_init(|| self.make_aspects()) + })* + } + } + } + }; +} + +arty_a7_platform! { + pub enum ArtyA7Platform { + #[name = "arty-a7-35t", device = Xc7a35ticsg324_1l] + ArtyA7_35T, + #[name = "arty-a7-100t", device = Xc7a100ticsg324_1l] + ArtyA7_100T, + } +} + +#[derive(Debug)] +pub struct ArtyA7Peripherals { + clk100_div_pow2: [Peripheral; 4], + rst: Peripheral, + rst_sync: Peripheral, + ld0: Peripheral, + ld1: Peripheral, + ld2: Peripheral, + ld3: Peripheral, + ld4: Peripheral, + ld5: Peripheral, + ld6: Peripheral, + ld7: Peripheral, + uart: Peripheral, + // TODO: add rest of peripherals when we need them +} + +impl Peripherals for ArtyA7Peripherals { + fn append_peripherals<'a>(&'a self, peripherals: &mut Vec>) { + let Self { + clk100_div_pow2, + rst, + rst_sync, + ld0, + ld1, + ld2, + ld3, + ld4, + ld5, + ld6, + ld7, + uart, + } = self; + clk100_div_pow2.append_peripherals(peripherals); + rst.append_peripherals(peripherals); + rst_sync.append_peripherals(peripherals); + ld0.append_peripherals(peripherals); + ld1.append_peripherals(peripherals); + ld2.append_peripherals(peripherals); + ld3.append_peripherals(peripherals); + ld4.append_peripherals(peripherals); + ld5.append_peripherals(peripherals); + ld6.append_peripherals(peripherals); + ld7.append_peripherals(peripherals); + uart.append_peripherals(peripherals); + } +} + +impl ArtyA7Platform { + fn make_aspects(self) -> PlatformAspectSet { + let mut retval = PlatformAspectSet::new(); + retval.insert_new(self.device()); + retval + } +} + +#[hdl_module(extern)] +fn reset_sync() { + #[hdl] + let clk: Clock = m.input(); + #[hdl] + let inp: Bool = m.input(); + #[hdl] + let out: SyncReset = m.output(); + m.annotate_module(BlackBoxInlineAnnotation { + path: "fayalite_arty_a7_reset_sync.v".intern(), + text: r#"module __fayalite_arty_a7_reset_sync(input clk, input inp, output out); + wire reset_0_out; + (* ASYNC_REG = "TRUE" *) + FDPE #( + .INIT(1'b1) + ) reset_0 ( + .Q(reset_0_out), + .C(clk), + .CE(1'b1), + .PRE(inp), + .D(1'b0) + ); + (* ASYNC_REG = "TRUE" *) + FDPE #( + .INIT(1'b1) + ) reset_1 ( + .Q(out), + .C(clk), + .CE(1'b1), + .PRE(inp), + .D(reset_0_out) + ); +endmodule +"# + .intern(), + }); + m.verilog_name("__fayalite_arty_a7_reset_sync"); +} + +impl Platform for ArtyA7Platform { + type Peripherals = ArtyA7Peripherals; + + fn name(&self) -> Interned { + self.as_str().intern() + } + + fn new_peripherals<'builder>( + &self, + builder_factory: PeripheralsBuilderFactory<'builder>, + ) -> (Self::Peripherals, PeripheralsBuilderFinished<'builder>) { + let mut builder = builder_factory.builder(); + + let clk100_div_pow2 = std::array::from_fn(|log2_divisor| { + let divisor = 1u64 << log2_divisor; + let name = if divisor != 1 { + format!("clk100_div_{divisor}") + } else { + "clk100".into() + }; + builder.input_peripheral(name, ClockInput::new(100e6 / divisor as f64)) + }); + builder.add_conflicts(Vec::from_iter(clk100_div_pow2.iter().map(|v| v.id()))); + ( + ArtyA7Peripherals { + clk100_div_pow2, + rst: builder.input_peripheral("rst", Reset), + rst_sync: builder.input_peripheral("rst_sync", SyncReset), + ld0: builder.output_peripheral("ld0", RgbLed), + ld1: builder.output_peripheral("ld1", RgbLed), + ld2: builder.output_peripheral("ld2", RgbLed), + ld3: builder.output_peripheral("ld3", RgbLed), + ld4: builder.output_peripheral("ld4", Led), + ld5: builder.output_peripheral("ld5", Led), + ld6: builder.output_peripheral("ld6", Led), + ld7: builder.output_peripheral("ld7", Led), + uart: builder.output_peripheral("uart", Uart), + }, + builder.finish(), + ) + } + + fn source_location(&self) -> SourceLocation { + SourceLocation::builtin() + } + + fn add_peripherals_in_wrapper_module(&self, m: &ModuleBuilder, peripherals: Self::Peripherals) { + let ArtyA7Peripherals { + clk100_div_pow2, + rst, + rst_sync, + ld0, + ld1, + ld2, + ld3, + ld4, + ld5, + ld6, + ld7, + uart, + } = peripherals; + let make_buffered_input = |name: &str, location: &str, io_standard: &str, invert: bool| { + let pin = m.input_with_loc(name, SourceLocation::builtin(), Bool); + annotate( + pin, + XdcLocationAnnotation { + location: location.intern(), + }, + ); + annotate( + pin, + XdcIOStandardAnnotation { + value: io_standard.intern(), + }, + ); + let buf = instance_with_loc( + &format!("{name}_buf"), + primitives::IBUF(), + SourceLocation::builtin(), + ); + connect(buf.I, pin); + if invert { !buf.O } else { buf.O } + }; + let make_buffered_output = |name: &str, location: &str, io_standard: &str| { + let pin = m.output_with_loc(name, SourceLocation::builtin(), Bool); + annotate( + pin, + XdcLocationAnnotation { + location: location.intern(), + }, + ); + annotate( + pin, + XdcIOStandardAnnotation { + value: io_standard.intern(), + }, + ); + let buf = instance_with_loc( + &format!("{name}_buf"), + primitives::OBUFT(), + SourceLocation::builtin(), + ); + connect(pin, buf.O); + connect(buf.T, false); + buf.I + }; + let mut frequency = clk100_div_pow2[0].ty().frequency(); + let mut log2_divisor = 0; + let mut clk = None; + for (cur_log2_divisor, p) in clk100_div_pow2.into_iter().enumerate() { + let Some(p) = p.into_used() else { + continue; + }; + debug_assert!( + clk.is_none(), + "conflict-handling logic should ensure at most one clock is used", + ); + frequency = p.ty().frequency(); + clk = Some(p); + log2_divisor = cur_log2_divisor; + } + let clk100_buf = make_buffered_input("clk100", "E3", "LVCMOS33", false); + let startup = instance_with_loc( + "startup", + primitives::STARTUPE2_default_inputs(), + SourceLocation::builtin(), + ); + let clk_global_buf = instance_with_loc( + "clk_global_buf", + primitives::BUFGCE(), + SourceLocation::builtin(), + ); + connect(clk_global_buf.CE, startup.EOS); + let mut clk_global_buf_in = clk100_buf.to_clock(); + for prev_log2_divisor in 0..log2_divisor { + let prev_divisor = 1u64 << prev_log2_divisor; + let clk_in = wire_with_loc( + &format!("clk_div_{prev_divisor}"), + SourceLocation::builtin(), + Clock, + ); + connect(clk_in, clk_global_buf_in); + annotate( + clk_in, + XdcCreateClockAnnotation { + period: NotNan::new(1e9 / (100e6 / prev_divisor as f64)) + .expect("known to be valid"), + }, + ); + annotate(clk_in, DontTouchAnnotation); + let cd = wire_with_loc( + &format!("clk_div_{prev_divisor}_in"), + SourceLocation::builtin(), + ClockDomain[AsyncReset], + ); + connect(cd.clk, clk_in); + connect(cd.rst, (!startup.EOS).to_async_reset()); + let divider = reg_builder_with_loc("divider", SourceLocation::builtin()) + .clock_domain(cd) + .reset(false) + .build(); + connect(divider, !divider); + clk_global_buf_in = divider.to_clock(); + } + connect(clk_global_buf.I, clk_global_buf_in); + let clk_out = wire_with_loc("clk_out", SourceLocation::builtin(), Clock); + connect(clk_out, clk_global_buf.O); + annotate( + clk_out, + XdcCreateClockAnnotation { + period: NotNan::new(1e9 / frequency).expect("known to be valid"), + }, + ); + annotate(clk_out, DontTouchAnnotation); + if let Some(clk) = clk { + connect(clk.instance_io_field().clk, clk_out); + } + let rst_value = { + let rst_buf = make_buffered_input("rst", "C2", "LVCMOS33", true); + let rst_sync = instance_with_loc("rst_sync", reset_sync(), SourceLocation::builtin()); + connect(rst_sync.clk, clk_out); + connect(rst_sync.inp, rst_buf | !startup.EOS); + rst_sync.out + }; + if let Some(rst) = rst.into_used() { + connect(rst.instance_io_field(), rst_value.to_reset()); + } + if let Some(rst_sync) = rst_sync.into_used() { + connect(rst_sync.instance_io_field(), rst_value); + } + let rgb_leds = [ + (ld0, ("G6", "F6", "E1")), + (ld1, ("G3", "J4", "G4")), + (ld2, ("J3", "J2", "H4")), + (ld3, ("K1", "H6", "K2")), + ]; + for (rgb_led, (r_loc, g_loc, b_loc)) in rgb_leds { + let r = make_buffered_output(&format!("{}_r", rgb_led.name()), r_loc, "LVCMOS33"); + let g = make_buffered_output(&format!("{}_g", rgb_led.name()), g_loc, "LVCMOS33"); + let b = make_buffered_output(&format!("{}_b", rgb_led.name()), b_loc, "LVCMOS33"); + if let Some(rgb_led) = rgb_led.into_used() { + connect(r, rgb_led.instance_io_field().r); + connect(g, rgb_led.instance_io_field().g); + connect(b, rgb_led.instance_io_field().b); + } else { + connect(r, false); + connect(g, false); + connect(b, false); + } + } + let leds = [(ld4, "H5"), (ld5, "J5"), (ld6, "T9"), (ld7, "T10")]; + for (led, loc) in leds { + let o = make_buffered_output(&led.name(), loc, "LVCMOS33"); + if let Some(led) = led.into_used() { + connect(o, led.instance_io_field().on); + } else { + connect(o, false); + } + } + let uart_tx = make_buffered_output("uart_tx", "D10", "LVCMOS33"); + let uart_rx = make_buffered_input("uart_rx", "A9", "LVCMOS33", false); + if let Some(uart) = uart.into_used() { + connect(uart_tx, uart.instance_io_field().tx); + connect(uart.instance_io_field().rx, uart_rx); + } else { + connect(uart_tx, true); // idle + } + } + + fn aspects(&self) -> PlatformAspectSet { + self.get_aspects().clone() + } +} + +pub(crate) fn built_in_job_kinds() -> impl IntoIterator { + [] +} + +pub(crate) fn built_in_platforms() -> impl IntoIterator { + ArtyA7Platform::VARIANTS + .iter() + .map(|&v| DynPlatform::new(v)) +} diff --git a/crates/fayalite/src/vendor/lattice/primitives.rs b/crates/fayalite/src/vendor/lattice/primitives.rs new file mode 100644 index 0000000..018eab3 --- /dev/null +++ b/crates/fayalite/src/vendor/lattice/primitives.rs @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information + +#![allow(non_snake_case)] + +use crate::prelude::*; + +//#[hdl_module(extern)] +//pub fn PLACEHOLDER() { +//do this first diff --git a/crates/fayalite/src/vendor/lattice/yosys_nextpnr_trellis.rs b/crates/fayalite/src/vendor/lattice/yosys_nextpnr_trellis.rs new file mode 100644 index 0000000..94ab863 --- /dev/null +++ b/crates/fayalite/src/vendor/lattice/yosys_nextpnr_trellis.rs @@ -0,0 +1,1043 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information + +use crate::{ + annotations::{Annotation, TargetedAnnotation}, + build::{ + BaseJob, CommandParams, DynJobKind, GetJobPositionDependencies, GlobalParams, + JobAndDependencies, JobArgsAndDependencies, JobDependencies, JobItem, JobItemName, JobKind, + JobKindAndDependencies, ToArgs, WriteArgs, + external::{ + ExternalCommand, ExternalCommandJob, ExternalCommandJobKind, ExternalProgramTrait, + }, + verilog::{UnadjustedVerilog, VerilogDialect, VerilogJob, VerilogJobKind}, + }, + bundle::{Bundle, BundleType}, + expr::target::{Target, TargetBase}, + firrtl::{ScalarizedModuleABI, ScalarizedModuleABIAnnotations, ScalarizedModuleABIPort}, + intern::{Intern, InternSlice, Interned}, + module::{ + NameId, ScopedNameId, TargetName, + transform::visit::{Visit, Visitor}, + }, + prelude::*, + source_location::SourceLocation, + util::{HashSet, job_server::AcquiredJob}, + vendor::lattice::{ + Device, XdcCreateClockAnnotation, XdcIOStandardAnnotation, XdcLocationAnnotation, + LatticeAnnotation, LatticeArgs, + }, +}; +use eyre::Context; +use serde::{Deserialize, Serialize}; +use std::{ + convert::Infallible, + ffi::{OsStr, OsString}, + fmt::{self, Write}, + ops::ControlFlow, + path::{Path, PathBuf}, +}; + +#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash, Default)] +pub struct YosysNextpnrTrellisWriteYsFileJobKind; + +#[derive(Clone, PartialEq, Eq, Hash, Debug, clap::Args)] +pub struct YosysNextpnrTrellisWriteYsFileArgs {} + +impl ToArgs for YosysNextpnrTrellisWriteYsFileArgs { + fn to_args(&self, _args: &mut (impl WriteArgs + ?Sized)) { + let Self {} = self; + } +} + +#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)] +pub struct YosysNextpnrTrellisWriteYsFile { + main_verilog_file: Interned, + ys_file: Interned, + json_file: Interned, + json_file_name: Interned, +} + +impl YosysNextpnrTrellisWriteYsFile { + pub fn main_verilog_file(&self) -> Interned { + self.main_verilog_file + } + pub fn ys_file(&self) -> Interned { + self.ys_file + } + pub fn json_file(&self) -> Interned { + self.json_file + } + pub fn json_file_name(&self) -> Interned { + self.json_file_name + } + fn write_ys( + &self, + output: &mut OsString, + additional_files: &[Interned], + main_module_name_id: NameId, + ) -> eyre::Result<()> { + let Self { + main_verilog_file, + ys_file: _, + json_file: _, + json_file_name, + } = self; + for verilog_file in VerilogJob::all_verilog_files(*main_verilog_file, additional_files)? { + output.push("read_verilog -sv \""); + output.push(verilog_file); + output.push("\"\n"); + } + let circuit_name = crate::firrtl::get_circuit_name(main_module_name_id); + writeln!( + output, + "synth_lattice -flatten -abc9 -nobram -arch xc7 -top {circuit_name}" + ) + .expect("writing to OsString can't fail"); + output.push("write_json \""); + output.push(json_file_name); + output.push("\"\n"); + Ok(()) + } +} + +impl JobKind for YosysNextpnrTrellisWriteYsFileJobKind { + type Args = YosysNextpnrTrellisWriteYsFileArgs; + type Job = YosysNextpnrTrellisWriteYsFile; + type Dependencies = JobKindAndDependencies; + + fn dependencies(self) -> Self::Dependencies { + Default::default() + } + + fn args_to_jobs( + mut args: JobArgsAndDependencies, + params: &JobParams, + global_params: &GlobalParams, + ) -> eyre::Result> { + args.dependencies + .dependencies + .args + .args + .additional_args + .verilog_dialect + .get_or_insert(VerilogDialect::Yosys); + args.args_to_jobs_simple(params, global_params, |_kind, args, dependencies| { + let YosysNextpnrTrellisWriteYsFileArgs {} = args; + let base_job = dependencies.get_job::(); + let verilog_job = dependencies.get_job::(); + let json_file = base_job.file_with_ext("json"); + Ok(YosysNextpnrTrellisWriteYsFile { + main_verilog_file: verilog_job.main_verilog_file(), + ys_file: base_job.file_with_ext("ys"), + json_file, + json_file_name: json_file + .interned_file_name() + .expect("known to have file name"), + }) + }) + } + + fn inputs(self, _job: &Self::Job) -> Interned<[JobItemName]> { + [JobItemName::DynamicPaths { + source_job_name: VerilogJobKind.name(), + }] + .intern_slice() + } + + fn outputs(self, job: &Self::Job) -> Interned<[JobItemName]> { + [JobItemName::Path { path: job.ys_file }].intern_slice() + } + + fn name(self) -> Interned { + "yosys-nextpnr-trellis-write-ys-file".intern() + } + + fn external_command_params(self, _job: &Self::Job) -> Option { + None + } + + fn run( + self, + job: &Self::Job, + inputs: &[JobItem], + params: &JobParams, + _global_params: &GlobalParams, + _acquired_job: &mut AcquiredJob, + ) -> eyre::Result> { + assert!(inputs.iter().map(JobItem::name).eq(self.inputs(job))); + let [additional_files] = inputs else { + unreachable!(); + }; + let additional_files = VerilogJob::unwrap_additional_files(additional_files); + let mut contents = OsString::new(); + job.write_ys( + &mut contents, + additional_files, + params.main_module().name_id(), + )?; + let path = job.ys_file; + std::fs::write(path, contents.as_encoded_bytes()) + .wrap_err_with(|| format!("writing {path:?} failed"))?; + Ok(vec![JobItem::Path { path }]) + } + + fn subcommand_hidden(self) -> bool { + true + } +} + +#[derive(Clone, PartialEq, Eq, Hash, Debug, clap::Args)] +pub struct YosysNextpnrTrellisSynthArgs {} + +impl ToArgs for YosysNextpnrTrellisSynthArgs { + fn to_args(&self, _args: &mut (impl WriteArgs + ?Sized)) { + let Self {} = self; + } +} + +#[derive(Clone, PartialEq, Eq, Hash, Deserialize, Serialize)] +pub struct YosysNextpnrTrellisSynth { + #[serde(flatten)] + write_ys_file: YosysNextpnrTrellisWriteYsFile, + ys_file_name: Interned, +} + +impl fmt::Debug for YosysNextpnrTrellisSynth { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + write_ys_file: + YosysNextpnrTrellisWriteYsFile { + main_verilog_file, + ys_file, + json_file, + json_file_name, + }, + ys_file_name, + } = self; + f.debug_struct("YosysNextpnrTrellisSynth") + .field("main_verilog_file", main_verilog_file) + .field("ys_file", ys_file) + .field("ys_file_name", ys_file_name) + .field("json_file", json_file) + .field("json_file_name", json_file_name) + .finish() + } +} + +impl YosysNextpnrTrellisSynth { + pub fn main_verilog_file(&self) -> Interned { + self.write_ys_file.main_verilog_file() + } + pub fn ys_file(&self) -> Interned { + self.write_ys_file.ys_file() + } + pub fn ys_file_name(&self) -> Interned { + self.ys_file_name + } + pub fn json_file(&self) -> Interned { + self.write_ys_file.json_file() + } + pub fn json_file_name(&self) -> Interned { + self.write_ys_file.json_file_name() + } +} + +#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)] +pub struct Yosys; + +impl ExternalProgramTrait for Yosys { + fn default_program_name() -> Interned { + "yosys".intern() + } +} + +impl ExternalCommand for YosysNextpnrTrellisSynth { + type AdditionalArgs = YosysNextpnrTrellisSynthArgs; + type AdditionalJobData = Self; + type BaseJobPosition = GetJobPositionDependencies< + GetJobPositionDependencies< + GetJobPositionDependencies<::BaseJobPosition>, + >, + >; + type Dependencies = JobKindAndDependencies; + type ExternalProgram = Yosys; + + fn dependencies() -> Self::Dependencies { + Default::default() + } + + fn args_to_jobs( + args: JobArgsAndDependencies>, + params: &JobParams, + global_params: &GlobalParams, + ) -> eyre::Result<( + Self::AdditionalJobData, + ::JobsAndKinds, + )> { + args.args_to_jobs_external_simple(params, global_params, |args, dependencies| { + let YosysNextpnrTrellisSynthArgs {} = args.additional_args; + Ok(Self { + write_ys_file: dependencies.job.job.clone(), + ys_file_name: dependencies + .job + .job + .ys_file() + .interned_file_name() + .expect("known to have file name"), + }) + }) + } + + fn inputs(job: &ExternalCommandJob) -> Interned<[JobItemName]> { + [ + JobItemName::Path { + path: job.additional_job_data().ys_file(), + }, + JobItemName::Path { + path: job.additional_job_data().main_verilog_file(), + }, + JobItemName::DynamicPaths { + source_job_name: VerilogJobKind.name(), + }, + ] + .intern_slice() + } + + fn output_paths(job: &ExternalCommandJob) -> Interned<[Interned]> { + [job.additional_job_data().json_file()].intern_slice() + } + + fn command_line_args(job: &ExternalCommandJob, args: &mut W) { + args.write_arg("-s"); + args.write_interned_arg(job.additional_job_data().ys_file_name()); + } + + fn current_dir(job: &ExternalCommandJob) -> Option> { + Some(job.output_dir()) + } + + fn job_kind_name() -> Interned { + "yosys-nextpnr-trellis-synth".intern() + } + + fn subcommand_hidden() -> bool { + true + } +} + +#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash, Default)] +pub struct YosysNextpnrTrellisWriteXdcFileJobKind; + +#[derive(Clone, PartialEq, Eq, Hash, Debug, clap::Args)] +pub struct YosysNextpnrTrellisWriteXdcFileArgs {} + +impl ToArgs for YosysNextpnrTrellisWriteXdcFileArgs { + fn to_args(&self, _args: &mut (impl WriteArgs + ?Sized)) { + let Self {} = self; + } +} + +#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)] +pub struct YosysNextpnrTrellisWriteXdcFile { + firrtl_export_options: crate::firrtl::ExportOptions, + output_dir: Interned, + xdc_file: Interned, +} + +struct WriteXdcContentsError(eyre::Report); + +impl From for WriteXdcContentsError { + fn from(v: eyre::Report) -> Self { + Self(v) + } +} + +impl From for WriteXdcContentsError { + fn from(_v: fmt::Error) -> Self { + unreachable!("String write can't fail") + } +} + +fn tcl_escape(s: impl AsRef) -> String { + let s = s.as_ref(); + if !s.contains(|ch: char| !ch.is_alphanumeric() && ch != '_') { + return s.into(); + } + let mut retval = String::with_capacity(s.len().saturating_add(2)); + retval.push('"'); + for ch in s.chars() { + if let '$' | '\\' | '[' = ch { + retval.push('\\'); + } + retval.push(ch); + } + retval.push('"'); + retval +} + +#[derive(Copy, Clone, Debug)] +enum AnnotationTarget { + None, + Module(Module), + Mem(Mem), + Target(Interned), +} + +impl AnnotationTarget { + fn source_location(self) -> SourceLocation { + match self { + AnnotationTarget::None => unreachable!(), + AnnotationTarget::Module(module) => module.source_location(), + AnnotationTarget::Mem(mem) => mem.source_location(), + AnnotationTarget::Target(target) => target.base().source_location(), + } + } +} + +struct XdcFileWriter { + output: W, + module_depth: usize, + annotation_target: AnnotationTarget, + dont_touch_targets: HashSet>, + required_dont_touch_targets: HashSet>, +} + +impl XdcFileWriter { + fn run(output: W, top_module: Module) -> Result<(), WriteXdcContentsError> { + let mut this = Self { + output, + module_depth: 0, + annotation_target: AnnotationTarget::None, + dont_touch_targets: HashSet::default(), + required_dont_touch_targets: HashSet::default(), + }; + top_module.visit(&mut this)?; + let Self { + output: _, + module_depth: _, + annotation_target: _, + dont_touch_targets, + required_dont_touch_targets, + } = this; + for &target in required_dont_touch_targets.difference(&dont_touch_targets) { + return Err(eyre::eyre!( + "a DontTouchAnnotation is required since the target is also annotated with a LatticeAnnotation:\ntarget: {target:?}\nat: {}", + target.base().source_location(), + ).into()); + } + Ok(()) + } + fn default_visit_with>( + &mut self, + module_depth: usize, + annotation_target: AnnotationTarget, + v: &T, + ) -> Result<(), WriteXdcContentsError> { + let Self { + output: _, + module_depth: old_module_depth, + annotation_target: old_annotation_target, + dont_touch_targets: _, + required_dont_touch_targets: _, + } = *self; + self.module_depth = module_depth; + self.annotation_target = annotation_target; + let retval = v.default_visit(self); + self.module_depth = old_module_depth; + self.annotation_target = old_annotation_target; + retval + } +} + +impl Visitor for XdcFileWriter { + type Error = WriteXdcContentsError; + + fn visit_targeted_annotation(&mut self, v: &TargetedAnnotation) -> Result<(), Self::Error> { + self.default_visit_with(self.module_depth, AnnotationTarget::Target(v.target()), v) + } + + fn visit_module(&mut self, v: &Module) -> Result<(), Self::Error> { + self.default_visit_with( + self.module_depth + 1, + AnnotationTarget::Module(v.canonical()), + v, + ) + } + + fn visit_mem( + &mut self, + v: &Mem, + ) -> Result<(), Self::Error> + where + Element: Visit, + { + self.default_visit_with( + self.module_depth + 1, + AnnotationTarget::Mem(v.canonical()), + v, + ) + } + + fn visit_dont_touch_annotation(&mut self, _v: &DontTouchAnnotation) -> Result<(), Self::Error> { + if let AnnotationTarget::Target(target) = self.annotation_target { + self.dont_touch_targets.insert(target); + } + Ok(()) + } + + fn visit_lattice_annotation(&mut self, v: &LatticeAnnotation) -> Result<(), Self::Error> { + fn todo( + msg: &str, + annotation: &LatticeAnnotation, + source_location: SourceLocation, + ) -> Result { + Err(WriteXdcContentsError(eyre::eyre!( + "{msg}\nannotation: {annotation:?}\nat: {source_location}" + ))) + } + if self.module_depth != 1 { + match todo( + "annotations are not yet supported outside of the top module since the logic to figure out the correct name isn't implemented", + v, + self.annotation_target.source_location(), + )? {} + } + match self.annotation_target { + AnnotationTarget::None => unreachable!(), + AnnotationTarget::Module(module) => match v { + LatticeAnnotation::XdcIOStandard(_) + | LatticeAnnotation::XdcLocation(_) + | LatticeAnnotation::XdcCreateClock(_) => { + return Err(WriteXdcContentsError(eyre::eyre!( + "annotation not allowed on a module: {v:?}\nat: {}", + module.source_location(), + ))); + } + }, + AnnotationTarget::Mem(mem) => match todo( + "lattice annotations are not yet supported on memories since the logic to figure out the correct name isn't implemented", + v, + mem.source_location(), + )? {}, + AnnotationTarget::Target(target) => { + let base = target.base(); + match *base { + TargetBase::ModuleIO(_) => { + // already handled by write_xdc_contents handling the main module's ScalarizedModuleABI + Ok(()) + } + TargetBase::MemPort(mem_port) => { + match todo( + "lattice annotations are not yet supported on memory ports since the logic to figure out the correct name isn't implemented", + v, + mem_port.source_location(), + )? {} + } + TargetBase::Reg(_) + | TargetBase::RegSync(_) + | TargetBase::RegAsync(_) + | TargetBase::Wire(_) => { + match *target { + Target::Base(_) => {} + Target::Child(_) => match todo( + "lattice annotations are not yet supported on parts of registers/wires since the logic to figure out the correct name isn't implemented", + v, + base.source_location(), + )? {}, + } + match base.canonical_ty() { + CanonicalType::UInt(_) + | CanonicalType::SInt(_) + | CanonicalType::Bool(_) + | CanonicalType::AsyncReset(_) + | CanonicalType::SyncReset(_) + | CanonicalType::Reset(_) + | CanonicalType::Clock(_) => {} + CanonicalType::Enum(_) + | CanonicalType::Array(_) + | CanonicalType::Bundle(_) + | CanonicalType::PhantomConst(_) + | CanonicalType::DynSimOnly(_) => match todo( + "lattice annotations are not yet supported on types other than integers, Bool, resets, or Clock since the logic to figure out the correct name isn't implemented", + v, + base.source_location(), + )? {}, + } + self.required_dont_touch_targets.insert(target); + match v { + LatticeAnnotation::XdcIOStandard(_) + | LatticeAnnotation::XdcLocation(_) => { + return Err(WriteXdcContentsError(eyre::eyre!( + "annotation must be on a ModuleIO: {v:?}\nat: {}", + base.source_location(), + ))); + } + LatticeAnnotation::XdcCreateClock(XdcCreateClockAnnotation { + period, + }) => { + let TargetName(ScopedNameId(_, NameId(name, _)), _) = + base.target_name(); + writeln!( + self.output, + "create_clock -period {period} [get_nets {}]", + tcl_escape(name), + )?; + Ok(()) + } + } + } + TargetBase::Instance(instance) => match todo( + "lattice annotations are not yet supported on instances' IO since the logic to figure out the correct name isn't implemented", + v, + instance.source_location(), + )? {}, + } + } + } + } +} + +impl YosysNextpnrTrellisWriteXdcFile { + fn write_xdc_contents_for_port_and_annotations( + &self, + output: &mut impl fmt::Write, + port: &ScalarizedModuleABIPort, + annotations: ScalarizedModuleABIAnnotations<'_>, + ) -> Result<(), WriteXdcContentsError> { + for annotation in annotations { + match annotation.annotation() { + Annotation::DontTouch(_) + | Annotation::SVAttribute(_) + | Annotation::BlackBoxInline(_) + | Annotation::BlackBoxPath(_) + | Annotation::DocString(_) + | Annotation::CustomFirrtl(_) => {} + Annotation::Lattice(LatticeAnnotation::XdcLocation(XdcLocationAnnotation { + location, + })) => writeln!( + output, + "set_property LOC {} [get_ports {}]", + tcl_escape(location), + tcl_escape(port.scalarized_name()), + )?, + Annotation::Lattice(LatticeAnnotation::XdcIOStandard(XdcIOStandardAnnotation { + value, + })) => writeln!( + output, + "set_property IOSTANDARD {} [get_ports {}]", + tcl_escape(value), + tcl_escape(port.scalarized_name()), + )?, + Annotation::Lattice(LatticeAnnotation::XdcCreateClock( + XdcCreateClockAnnotation { period }, + )) => writeln!( + output, + "create_clock -period {period} [get_ports {}]", + tcl_escape(port.scalarized_name()), + )?, + } + } + Ok(()) + } + fn write_xdc_contents( + &self, + output: &mut String, + top_module: &Module, + ) -> eyre::Result<()> { + let scalarized_module_abi = + ScalarizedModuleABI::new(top_module, self.firrtl_export_options) + .map_err(eyre::Report::from)?; + match scalarized_module_abi.for_each_port_and_annotations(|port, annotations| { + match self.write_xdc_contents_for_port_and_annotations(output, port, annotations) { + Ok(()) => ControlFlow::Continue(()), + Err(e) => ControlFlow::Break(e), + } + }) { + ControlFlow::Continue(()) => {} + ControlFlow::Break(e) => return Err(e.0), + } + XdcFileWriter::run(output, *top_module).map_err(|e| e.0) + } +} + +impl JobKind for YosysNextpnrTrellisWriteXdcFileJobKind { + type Args = YosysNextpnrTrellisWriteXdcFileArgs; + type Job = YosysNextpnrTrellisWriteXdcFile; + type Dependencies = JobKindAndDependencies>; + + fn dependencies(self) -> Self::Dependencies { + Default::default() + } + + fn args_to_jobs( + args: JobArgsAndDependencies, + params: &JobParams, + global_params: &GlobalParams, + ) -> eyre::Result> { + let firrtl_export_options = args + .dependencies + .dependencies + .dependencies + .dependencies + .dependencies + .args + .args + .export_options; + args.args_to_jobs_simple(params, global_params, |_kind, args, dependencies| { + let YosysNextpnrTrellisWriteXdcFileArgs {} = args; + let base_job = dependencies.get_job::(); + Ok(YosysNextpnrTrellisWriteXdcFile { + firrtl_export_options, + output_dir: base_job.output_dir(), + xdc_file: base_job.file_with_ext("xdc"), + }) + }) + } + + fn inputs(self, job: &Self::Job) -> Interned<[JobItemName]> { + [JobItemName::Path { + path: job.output_dir, + }] + .intern_slice() + } + + fn outputs(self, job: &Self::Job) -> Interned<[JobItemName]> { + [JobItemName::Path { path: job.xdc_file }].intern_slice() + } + + fn name(self) -> Interned { + "yosys-nextpnr-trellis-write-xdc-file".intern() + } + + fn external_command_params(self, _job: &Self::Job) -> Option { + None + } + + fn run( + self, + job: &Self::Job, + inputs: &[JobItem], + params: &JobParams, + _global_params: &GlobalParams, + _acquired_job: &mut AcquiredJob, + ) -> eyre::Result> { + assert!(inputs.iter().map(JobItem::name).eq(self.inputs(job))); + let mut xdc = String::new(); + job.write_xdc_contents(&mut xdc, params.main_module())?; + std::fs::write(job.xdc_file, xdc)?; + Ok(vec![JobItem::Path { path: job.xdc_file }]) + } + + fn subcommand_hidden(self) -> bool { + true + } +} + +#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)] +pub struct NextpnrLattice; + +impl ExternalProgramTrait for NextpnrLattice { + fn default_program_name() -> Interned { + "nextpnr-lattice".intern() + } +} + +#[derive(Clone, PartialEq, Eq, Hash, Debug, clap::Args)] +pub struct YosysNextpnrTrellisRunNextpnrArgs { + #[command(flatten)] + pub common: LatticeArgs, + #[arg(long, env = "CHIPDB_DIR", value_hint = clap::ValueHint::DirPath)] + pub nextpnr_lattice_chipdb_dir: PathBuf, + #[arg(long, default_value_t = 0)] + pub nextpnr_lattice_seed: i32, +} + +impl ToArgs for YosysNextpnrTrellisRunNextpnrArgs { + fn to_args(&self, args: &mut (impl WriteArgs + ?Sized)) { + let Self { + common, + nextpnr_lattice_chipdb_dir, + nextpnr_lattice_seed, + } = self; + common.to_args(args); + args.write_long_option_eq("nextpnr-lattice-chipdb-dir", nextpnr_lattice_chipdb_dir); + args.write_display_arg(format_args!("--nextpnr-lattice-seed={nextpnr_lattice_seed}")); + } +} + +#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)] +pub struct YosysNextpnrTrellisRunNextpnr { + nextpnr_lattice_chipdb_dir: Interned, + device: Device, + nextpnr_lattice_seed: i32, + xdc_file: Interned, + xdc_file_name: Interned, + json_file: Interned, + json_file_name: Interned, + routed_json_file: Interned, + routed_json_file_name: Interned, + fasm_file: Interned, + fasm_file_name: Interned, +} + +impl YosysNextpnrTrellisRunNextpnr { + fn chipdb_file(&self) -> Interned { + let mut retval = self + .nextpnr_lattice_chipdb_dir + .join(self.device.trellis_device()); + retval.set_extension("bin"); + retval.intern_deref() + } +} + +impl ExternalCommand for YosysNextpnrTrellisRunNextpnr { + type AdditionalArgs = YosysNextpnrTrellisRunNextpnrArgs; + type AdditionalJobData = Self; + type BaseJobPosition = GetJobPositionDependencies< + GetJobPositionDependencies<::BaseJobPosition>, + >; + type Dependencies = JobKindAndDependencies; + type ExternalProgram = NextpnrLattice; + + fn dependencies() -> Self::Dependencies { + Default::default() + } + + fn args_to_jobs( + args: JobArgsAndDependencies>, + params: &JobParams, + global_params: &GlobalParams, + ) -> eyre::Result<( + Self::AdditionalJobData, + ::JobsAndKinds, + )> { + args.args_to_jobs_external_simple(params, global_params, |args, dependencies| { + let YosysNextpnrTrellisRunNextpnrArgs { + common, + nextpnr_lattice_chipdb_dir, + nextpnr_lattice_seed, + } = args.additional_args; + let base_job = dependencies.get_job::(); + let write_xdc_file = dependencies.get_job::(); + let synth = dependencies.get_job::, _>(); + let routed_json_file = base_job.file_with_ext("routed.json"); + let fasm_file = base_job.file_with_ext("fasm"); + Ok(Self { + nextpnr_lattice_chipdb_dir: nextpnr_lattice_chipdb_dir.intern_deref(), + device: common.require_device(base_job.platform(), global_params)?, + nextpnr_lattice_seed, + xdc_file: write_xdc_file.xdc_file, + xdc_file_name: write_xdc_file + .xdc_file + .interned_file_name() + .expect("known to have file name"), + json_file: synth.additional_job_data().json_file(), + json_file_name: synth.additional_job_data().json_file_name(), + routed_json_file, + routed_json_file_name: routed_json_file + .interned_file_name() + .expect("known to have file name"), + fasm_file, + fasm_file_name: fasm_file + .interned_file_name() + .expect("known to have file name"), + }) + }) + } + + fn inputs(job: &ExternalCommandJob) -> Interned<[JobItemName]> { + [ + JobItemName::Path { + path: job.additional_job_data().json_file, + }, + JobItemName::Path { + path: job.additional_job_data().xdc_file, + }, + ] + .intern_slice() + } + + fn output_paths(job: &ExternalCommandJob) -> Interned<[Interned]> { + [ + job.additional_job_data().routed_json_file, + job.additional_job_data().fasm_file, + ] + .intern_slice() + } + + fn command_line_args(job: &ExternalCommandJob, args: &mut W) { + let job_data @ YosysNextpnrTrellisRunNextpnr { + nextpnr_lattice_seed, + xdc_file_name, + json_file_name, + routed_json_file_name, + fasm_file_name, + .. + } = job.additional_job_data(); + args.write_long_option_eq("chipdb", job_data.chipdb_file()); + args.write_long_option_eq("xdc", xdc_file_name); + args.write_long_option_eq("json", json_file_name); + args.write_long_option_eq("write", routed_json_file_name); + args.write_long_option_eq("fasm", fasm_file_name); + args.write_display_arg(format_args!("--seed={nextpnr_lattice_seed}")); + } + + fn current_dir(job: &ExternalCommandJob) -> Option> { + Some(job.output_dir()) + } + + fn job_kind_name() -> Interned { + "yosys-nextpnr-trellis-run-nextpnr".intern() + } + + fn subcommand_hidden() -> bool { + true + } +} + +#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)] +pub struct Xcfasm; + +impl ExternalProgramTrait for Xcfasm { + fn default_program_name() -> Interned { + "xcfasm".intern() + } +} + +#[derive(Clone, PartialEq, Eq, Hash, Debug, clap::Args)] +pub struct YosysNextpnrTrellisArgs { + #[arg(long, env = "DB_DIR", value_hint = clap::ValueHint::DirPath)] + pub prjtrellis_db_dir: PathBuf, +} + +impl ToArgs for YosysNextpnrTrellisArgs { + fn to_args(&self, args: &mut (impl WriteArgs + ?Sized)) { + let Self { prjtrellis_db_dir } = self; + args.write_long_option_eq("prjtrellis-db-dir", prjtrellis_db_dir); + } +} + +#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)] +pub struct YosysNextpnrTrellis { + prjtrellis_db_dir: Interned, + device: Device, + fasm_file: Interned, + fasm_file_name: Interned, + frames_file: Interned, + frames_file_name: Interned, + bit_file: Interned, + bit_file_name: Interned, +} + +impl YosysNextpnrTrellis { + fn db_root(&self) -> Interned { + self.prjtrellis_db_dir + .join(self.device.trellis_family()) + .intern_deref() + } + fn part_file(&self) -> Interned { + let mut retval = self.prjtrellis_db_dir.join(self.device.trellis_family()); + retval.push(self.device.trellis_part()); + retval.push("part.yaml"); + retval.intern_deref() + } +} + +impl ExternalCommand for YosysNextpnrTrellis { + type AdditionalArgs = YosysNextpnrTrellisArgs; + type AdditionalJobData = Self; + type BaseJobPosition = GetJobPositionDependencies< + ::BaseJobPosition, + >; + type Dependencies = JobKindAndDependencies>; + type ExternalProgram = Xcfasm; + + fn dependencies() -> Self::Dependencies { + Default::default() + } + + fn args_to_jobs( + args: JobArgsAndDependencies>, + params: &JobParams, + global_params: &GlobalParams, + ) -> eyre::Result<( + Self::AdditionalJobData, + ::JobsAndKinds, + )> { + args.args_to_jobs_external_simple(params, global_params, |args, dependencies| { + let YosysNextpnrTrellisArgs { prjtrellis_db_dir } = args.additional_args; + let base_job = dependencies.get_job::(); + let frames_file = base_job.file_with_ext("frames"); + let bit_file = base_job.file_with_ext("bit"); + Ok(Self { + prjtrellis_db_dir: prjtrellis_db_dir.intern_deref(), + device: dependencies.job.job.additional_job_data().device, + fasm_file: dependencies.job.job.additional_job_data().fasm_file, + fasm_file_name: dependencies.job.job.additional_job_data().fasm_file_name, + frames_file, + frames_file_name: frames_file + .interned_file_name() + .expect("known to have file name"), + bit_file, + bit_file_name: bit_file + .interned_file_name() + .expect("known to have file name"), + }) + }) + } + + fn inputs(job: &ExternalCommandJob) -> Interned<[JobItemName]> { + [JobItemName::Path { + path: job.additional_job_data().fasm_file, + }] + .intern_slice() + } + + fn output_paths(job: &ExternalCommandJob) -> Interned<[Interned]> { + [ + job.additional_job_data().frames_file, + job.additional_job_data().bit_file, + ] + .intern_slice() + } + + fn command_line_args(job: &ExternalCommandJob, args: &mut W) { + let job_data @ YosysNextpnrTrellis { + device, + fasm_file_name, + frames_file_name, + bit_file_name, + .. + } = job.additional_job_data(); + args.write_arg("--sparse"); + args.write_long_option_eq("db-root", job_data.db_root()); + args.write_long_option_eq("part", device.trellis_part()); + args.write_long_option_eq("part_file", job_data.part_file()); + args.write_long_option_eq("fn_in", fasm_file_name); + args.write_long_option_eq("frm_out", frames_file_name); + args.write_long_option_eq("bit_out", bit_file_name); + } + + fn current_dir(job: &ExternalCommandJob) -> Option> { + Some(job.output_dir()) + } + + fn job_kind_name() -> Interned { + "yosys-nextpnr-trellis".intern() + } +} + +pub(crate) fn built_in_job_kinds() -> impl IntoIterator { + [ + DynJobKind::new(YosysNextpnrTrellisWriteYsFileJobKind), + DynJobKind::new(ExternalCommandJobKind::::new()), + DynJobKind::new(YosysNextpnrTrellisWriteXdcFileJobKind), + DynJobKind::new(ExternalCommandJobKind::::new()), + DynJobKind::new(ExternalCommandJobKind::::new()), + ] +} + +pub(crate) fn built_in_platforms() -> impl IntoIterator { + [] +} diff --git a/crates/fayalite/tests/hdl_types.rs b/crates/fayalite/tests/hdl_types.rs index cb3510e..5030282 100644 --- a/crates/fayalite/tests/hdl_types.rs +++ b/crates/fayalite/tests/hdl_types.rs @@ -244,13 +244,3 @@ pub struct MyTypeWithPrivateMembersWithArg { pub(crate) b: MyPubCrateTypeWithArg, pub c: T, } - -#[hdl(outline_generated)] -pub enum EnumWithOnlyOneVariant { - A, -} - -#[hdl(outline_generated)] -pub enum EnumWithOnlyOneVariant2 { - A(T), -} diff --git a/crates/fayalite/tests/sim/expected/array_rw.vcd b/crates/fayalite/tests/sim/expected/array_rw.vcd index fefce5f..8ede394 100644 --- a/crates/fayalite/tests/sim/expected/array_rw.vcd +++ b/crates/fayalite/tests/sim/expected/array_rw.vcd @@ -1,283 +1,283 @@ $timescale 1 ps $end $scope module array_rw $end $scope struct array_in $end -$var wire 8 Yvfu^ \[0] $end -$var wire 8 |Cs`W \[1] $end -$var wire 8 M!nsb \[2] $end -$var wire 8 59L{w \[3] $end -$var wire 8 o2+|F \[4] $end -$var wire 8 ikzV5 \[5] $end -$var wire 8 [E$Z* \[6] $end -$var wire 8 ?"~01 \[7] $end -$var wire 8 /kghT \[8] $end -$var wire 8 +}(9) \[9] $end -$var wire 8 iMP}= \[10] $end -$var wire 8 2M0tL \[11] $end -$var wire 8 :AjkA \[12] $end -$var wire 8 VM_:8 \[13] $end -$var wire 8 UveL2 \[14] $end -$var wire 8 A)9Z6 \[15] $end +$var wire 8 ! \[0] $end +$var wire 8 " \[1] $end +$var wire 8 # \[2] $end +$var wire 8 $ \[3] $end +$var wire 8 % \[4] $end +$var wire 8 & \[5] $end +$var wire 8 ' \[6] $end +$var wire 8 ( \[7] $end +$var wire 8 ) \[8] $end +$var wire 8 * \[9] $end +$var wire 8 + \[10] $end +$var wire 8 , \[11] $end +$var wire 8 - \[12] $end +$var wire 8 . \[13] $end +$var wire 8 / \[14] $end +$var wire 8 0 \[15] $end $upscope $end $scope struct array_out $end -$var wire 8 2zdj1 \[0] $end -$var wire 8 =;m_[ \[1] $end -$var wire 8 @9Hd \[2] $end -$var wire 8 C:="| \[3] $end -$var wire 8 IDk7# \[4] $end -$var wire 8 i]E1i \[5] $end -$var wire 8 tK,M] \[6] $end -$var wire 8 tGp!\ \[7] $end -$var wire 8 ."qjK \[8] $end -$var wire 8 AUO:R \[9] $end -$var wire 8 'kx`n \[10] $end -$var wire 8 U&(K\ \[11] $end -$var wire 8 q0H<( \[14] $end -$var wire 8 ARhXJ \[15] $end +$var wire 8 1 \[0] $end +$var wire 8 2 \[1] $end +$var wire 8 3 \[2] $end +$var wire 8 4 \[3] $end +$var wire 8 5 \[4] $end +$var wire 8 6 \[5] $end +$var wire 8 7 \[6] $end +$var wire 8 8 \[7] $end +$var wire 8 9 \[8] $end +$var wire 8 : \[9] $end +$var wire 8 ; \[10] $end +$var wire 8 < \[11] $end +$var wire 8 = \[12] $end +$var wire 8 > \[13] $end +$var wire 8 ? \[14] $end +$var wire 8 @ \[15] $end $upscope $end -$var wire 8 -n:7@ read_index $end -$var wire 8 >h<=Z read_data $end -$var wire 8 [xld3 write_index $end -$var wire 8 J+DYh write_data $end -$var wire 1 z,@WW write_en $end +$var wire 8 A read_index $end +$var wire 8 B read_data $end +$var wire 8 C write_index $end +$var wire 8 D write_data $end +$var wire 1 E write_en $end $scope struct array_wire $end -$var wire 8 B{KJS \[0] $end -$var wire 8 V'K*& \[1] $end -$var wire 8 4zI$O \[2] $end -$var wire 8 %TTk[ \[3] $end -$var wire 8 IgSeY \[4] $end -$var wire 8 &&1T" \[5] $end -$var wire 8 5)-l\ \[6] $end -$var wire 8 0RsLb \[7] $end -$var wire 8 T>:}D \[8] $end -$var wire 8 DPpZ* \[9] $end -$var wire 8 %E(nf \[10] $end -$var wire 8 2'pba \[11] $end -$var wire 8 e/c1: \[12] $end -$var wire 8 ;w.C7 \[13] $end -$var wire 8 fwdfu \[14] $end -$var wire 8 *R\vx \[15] $end +$var wire 8 F \[0] $end +$var wire 8 G \[1] $end +$var wire 8 H \[2] $end +$var wire 8 I \[3] $end +$var wire 8 J \[4] $end +$var wire 8 K \[5] $end +$var wire 8 L \[6] $end +$var wire 8 M \[7] $end +$var wire 8 N \[8] $end +$var wire 8 O \[9] $end +$var wire 8 P \[10] $end +$var wire 8 Q \[11] $end +$var wire 8 R \[12] $end +$var wire 8 S \[13] $end +$var wire 8 T \[14] $end +$var wire 8 U \[15] $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -b11111111 Yvfu^ -b1111111 |Cs`W -b111111 M!nsb -b11111 59L{w -b1111 o2+|F -b111 ikzV5 -b11 [E$Z* -b1 ?"~01 -b0 /kghT -b10000000 +}(9) -b11000000 iMP}= -b11100000 2M0tL -b11110000 :AjkA -b11111000 VM_:8 -b11111100 UveL2 -b11111110 A)9Z6 -b11111111 2zdj1 -b1111111 =;m_[ -b111111 @9Hd -b11111 C:="| -b1111 IDk7# -b111 i]E1i -b11 tK,M] -b1 tGp!\ -b0 ."qjK -b10000000 AUO:R -b11000000 'kx`n -b11100000 U&(K\ -b11110000 q0H<( -b11111110 ARhXJ -b0 -n:7@ -b11111111 >h<=Z -b0 [xld3 -b0 J+DYh -0z,@WW -b11111111 B{KJS -b1111111 V'K*& -b111111 4zI$O -b11111 %TTk[ -b1111 IgSeY -b111 &&1T" -b11 5)-l\ -b1 0RsLb -b0 T>:}D -b10000000 DPpZ* -b11000000 %E(nf -b11100000 2'pba -b11110000 e/c1: -b11111000 ;w.C7 -b11111100 fwdfu -b11111110 *R\vx +b11111111 ! +b1111111 " +b111111 # +b11111 $ +b1111 % +b111 & +b11 ' +b1 ( +b0 ) +b10000000 * +b11000000 + +b11100000 , +b11110000 - +b11111000 . +b11111100 / +b11111110 0 +b11111111 1 +b1111111 2 +b111111 3 +b11111 4 +b1111 5 +b111 6 +b11 7 +b1 8 +b0 9 +b10000000 : +b11000000 ; +b11100000 < +b11110000 = +b11111000 > +b11111100 ? +b11111110 @ +b0 A +b11111111 B +b0 C +b0 D +0E +b11111111 F +b1111111 G +b111111 H +b11111 I +b1111 J +b111 K +b11 L +b1 M +b0 N +b10000000 O +b11000000 P +b11100000 Q +b11110000 R +b11111000 S +b11111100 T +b11111110 U $end #1000000 -b1 -n:7@ -b1111111 >h<=Z +b1 A +b1111111 B #2000000 -b10 -n:7@ -b111111 >h<=Z +b10 A +b111111 B #3000000 -b11 -n:7@ -b11111 >h<=Z +b11 A +b11111 B #4000000 -b100 -n:7@ -b1111 >h<=Z +b100 A +b1111 B #5000000 -b101 -n:7@ -b111 >h<=Z +b101 A +b111 B #6000000 -b110 -n:7@ -b11 >h<=Z +b110 A +b11 B #7000000 -b111 -n:7@ -b1 >h<=Z +b111 A +b1 B #8000000 -b1000 -n:7@ -b0 >h<=Z +b1000 A +b0 B #9000000 -b1001 -n:7@ -b10000000 >h<=Z +b1001 A +b10000000 B #10000000 -b1010 -n:7@ -b11000000 >h<=Z +b1010 A +b11000000 B #11000000 -b1011 -n:7@ -b11100000 >h<=Z +b1011 A +b11100000 B #12000000 -b1100 -n:7@ -b11110000 >h<=Z +b1100 A +b11110000 B #13000000 -b1101 -n:7@ -b11111000 >h<=Z +b1101 A +b11111000 B #14000000 -b1110 -n:7@ -b11111100 >h<=Z +b1110 A +b11111100 B #15000000 -b1111 -n:7@ -b11111110 >h<=Z +b1111 A +b11111110 B #16000000 -b10000 -n:7@ -b0 >h<=Z +b10000 A +b0 B #17000000 -b0 2zdj1 -b0 -n:7@ -1z,@WW -b0 B{KJS +b0 1 +b0 A +1E +b0 F #18000000 -b11111111 2zdj1 -b1 =;m_[ -b11111111 >h<=Z -b1 [xld3 -b1 J+DYh -b11111111 B{KJS -b1 V'K*& +b11111111 1 +b1 2 +b11111111 B +b1 C +b1 D +b11111111 F +b1 G #19000000 -b1111111 =;m_[ -b100 @9Hd -b10 [xld3 -b100 J+DYh -b1111111 V'K*& -b100 4zI$O +b1111111 2 +b100 3 +b10 C +b100 D +b1111111 G +b100 H #20000000 -b111111 @9Hd -b1001 C:="| -b11 [xld3 -b1001 J+DYh -b111111 4zI$O -b1001 %TTk[ +b111111 3 +b1001 4 +b11 C +b1001 D +b111111 H +b1001 I #21000000 -b11111 C:="| -b10000 IDk7# -b100 [xld3 -b10000 J+DYh -b11111 %TTk[ -b10000 IgSeY +b11111 4 +b10000 5 +b100 C +b10000 D +b11111 I +b10000 J #22000000 -b1111 IDk7# -b11001 i]E1i -b101 [xld3 -b11001 J+DYh -b1111 IgSeY -b11001 &&1T" +b1111 5 +b11001 6 +b101 C +b11001 D +b1111 J +b11001 K #23000000 -b111 i]E1i -b100100 tK,M] -b110 [xld3 -b100100 J+DYh -b111 &&1T" -b100100 5)-l\ +b111 6 +b100100 7 +b110 C +b100100 D +b111 K +b100100 L #24000000 -b11 tK,M] -b110001 tGp!\ -b111 [xld3 -b110001 J+DYh -b11 5)-l\ -b110001 0RsLb +b11 7 +b110001 8 +b111 C +b110001 D +b11 L +b110001 M #25000000 -b1 tGp!\ -b1000000 ."qjK -b1000 [xld3 -b1000000 J+DYh -b1 0RsLb -b1000000 T>:}D +b1 8 +b1000000 9 +b1000 C +b1000000 D +b1 M +b1000000 N #26000000 -b0 ."qjK -b1010001 AUO:R -b1001 [xld3 -b1010001 J+DYh -b0 T>:}D -b1010001 DPpZ* +b0 9 +b1010001 : +b1001 C +b1010001 D +b0 N +b1010001 O #27000000 -b10000000 AUO:R -b1100100 'kx`n -b1010 [xld3 -b1100100 J+DYh -b10000000 DPpZ* -b1100100 %E(nf +b10000000 : +b1100100 ; +b1010 C +b1100100 D +b10000000 O +b1100100 P #28000000 -b11000000 'kx`n -b1111001 U&(K\ -b1011 [xld3 -b1111001 J+DYh -b11000000 %E(nf -b1111001 2'pba +b11000000 ; +b1111001 < +b1011 C +b1111001 D +b11000000 P +b1111001 Q #29000000 -b11100000 U&(K\ -b10010000 q +b1101 C +b10101001 D +b11110000 R +b10101001 S #31000000 -b11111000 zvj)] -b11000100 >0H<( -b1110 [xld3 -b11000100 J+DYh -b11111000 ;w.C7 -b11000100 fwdfu +b11111000 > +b11000100 ? +b1110 C +b11000100 D +b11111000 S +b11000100 T #32000000 -b11111100 >0H<( -b11100001 ARhXJ -b1111 [xld3 -b11100001 J+DYh -b11111100 fwdfu -b11100001 *R\vx +b11111100 ? +b11100001 @ +b1111 C +b11100001 D +b11111100 T +b11100001 U #33000000 -b11111110 ARhXJ -b10000 [xld3 -b0 J+DYh -b11111110 *R\vx +b11111110 @ +b10000 C +b0 D +b11111110 U #34000000 diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd b/crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd index 96a9fba..dd9a85a 100644 --- a/crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd +++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd @@ -1,14 +1,14 @@ $timescale 1 ps $end $scope module conditional_assignment_last $end -$var wire 1 xt~(W i $end -$var wire 1 6:7im w $end +$var wire 1 ! i $end +$var wire 1 " w $end $upscope $end $enddefinitions $end $dumpvars -0xt~(W -16:7im +0! +1" $end #1000000 -1xt~(W -06:7im +1! +0" #2000000 diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.vcd b/crates/fayalite/tests/sim/expected/connect_const_reset.vcd index f6e228a..50b427c 100644 --- a/crates/fayalite/tests/sim/expected/connect_const_reset.vcd +++ b/crates/fayalite/tests/sim/expected/connect_const_reset.vcd @@ -1,11 +1,11 @@ $timescale 1 ps $end $scope module connect_const_reset $end -$var wire 1 8ke|= reset_out $end -$var wire 1 {"c@= bit_out $end +$var wire 1 ! reset_out $end +$var wire 1 " bit_out $end $upscope $end $enddefinitions $end $dumpvars -18ke|= -1{"c@= +1! +1" $end #1000000 diff --git a/crates/fayalite/tests/sim/expected/counter_async.vcd b/crates/fayalite/tests/sim/expected/counter_async.vcd index d40f10f..dab690f 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.vcd +++ b/crates/fayalite/tests/sim/expected/counter_async.vcd @@ -1,217 +1,217 @@ $timescale 1 ps $end $scope module counter $end $scope struct cd $end -$var wire 1 `[J;" clk $end -$var wire 1 4pZx7 rst $end +$var wire 1 ! clk $end +$var wire 1 " rst $end $upscope $end -$var wire 4 rPs;{ count $end -$var reg 4 6_+(g count_reg $end +$var wire 4 # count $end +$var reg 4 $ count_reg $end $upscope $end $enddefinitions $end $dumpvars -0`[J;" -04pZx7 -b0 rPs;{ -b0 6_+(g +0! +0" +b0 # +b0 $ $end #500000 -14pZx7 -b11 rPs;{ -b11 6_+(g +1" +b11 # +b11 $ #1000000 -1`[J;" +1! #1500000 -04pZx7 +0" #2000000 -0`[J;" +0! #3000000 -1`[J;" -b100 rPs;{ -b100 6_+(g +1! +b100 # +b100 $ #4000000 -0`[J;" +0! #5000000 -1`[J;" -b101 rPs;{ -b101 6_+(g +1! +b101 # +b101 $ #6000000 -0`[J;" +0! #7000000 -1`[J;" -b110 rPs;{ -b110 6_+(g +1! +b110 # +b110 $ #8000000 -0`[J;" +0! #9000000 -1`[J;" -b111 rPs;{ -b111 6_+(g +1! +b111 # +b111 $ #10000000 -0`[J;" +0! #11000000 -1`[J;" -b1000 rPs;{ -b1000 6_+(g +1! +b1000 # +b1000 $ #12000000 -0`[J;" +0! #13000000 -1`[J;" -b1001 rPs;{ -b1001 6_+(g +1! +b1001 # +b1001 $ #14000000 -0`[J;" +0! #15000000 -1`[J;" -b1010 rPs;{ -b1010 6_+(g +1! +b1010 # +b1010 $ #16000000 -0`[J;" +0! #17000000 -1`[J;" -b1011 rPs;{ -b1011 6_+(g +1! +b1011 # +b1011 $ #18000000 -0`[J;" +0! #19000000 -1`[J;" -b1100 rPs;{ -b1100 6_+(g +1! +b1100 # +b1100 $ #20000000 -0`[J;" +0! #21000000 -1`[J;" -b1101 rPs;{ -b1101 6_+(g +1! +b1101 # +b1101 $ #22000000 -0`[J;" +0! #23000000 -1`[J;" -b1110 rPs;{ -b1110 6_+(g +1! +b1110 # +b1110 $ #24000000 -0`[J;" +0! #25000000 -1`[J;" -b1111 rPs;{ -b1111 6_+(g +1! +b1111 # +b1111 $ #26000000 -0`[J;" +0! #27000000 -1`[J;" -b0 rPs;{ -b0 6_+(g +1! +b0 # +b0 $ #28000000 -0`[J;" +0! #29000000 -1`[J;" -b1 rPs;{ -b1 6_+(g +1! +b1 # +b1 $ #30000000 -0`[J;" +0! #31000000 -1`[J;" -b10 rPs;{ -b10 6_+(g +1! +b10 # +b10 $ #32000000 -0`[J;" +0! #33000000 -1`[J;" -b11 rPs;{ -b11 6_+(g +1! +b11 # +b11 $ #34000000 -0`[J;" +0! #35000000 -1`[J;" -b100 rPs;{ -b100 6_+(g +1! +b100 # +b100 $ #36000000 -0`[J;" +0! #37000000 -1`[J;" -b101 rPs;{ -b101 6_+(g +1! +b101 # +b101 $ #38000000 -0`[J;" +0! #39000000 -1`[J;" -b110 rPs;{ -b110 6_+(g +1! +b110 # +b110 $ #40000000 -0`[J;" +0! #41000000 -1`[J;" -b111 rPs;{ -b111 6_+(g +1! +b111 # +b111 $ #42000000 -0`[J;" +0! #43000000 -1`[J;" -b1000 rPs;{ -b1000 6_+(g +1! +b1000 # +b1000 $ #44000000 -0`[J;" +0! #45000000 -1`[J;" -b1001 rPs;{ -b1001 6_+(g +1! +b1001 # +b1001 $ #46000000 -0`[J;" +0! #47000000 -1`[J;" -b1010 rPs;{ -b1010 6_+(g +1! +b1010 # +b1010 $ #48000000 -0`[J;" +0! #49000000 -1`[J;" -b1011 rPs;{ -b1011 6_+(g +1! +b1011 # +b1011 $ #50000000 -0`[J;" +0! #51000000 -1`[J;" -b1100 rPs;{ -b1100 6_+(g +1! +b1100 # +b1100 $ #52000000 -0`[J;" +0! #53000000 -1`[J;" -b1101 rPs;{ -b1101 6_+(g +1! +b1101 # +b1101 $ #54000000 -0`[J;" +0! #55000000 -1`[J;" -b1110 rPs;{ -b1110 6_+(g +1! +b1110 # +b1110 $ #56000000 -0`[J;" +0! #57000000 -1`[J;" -b1111 rPs;{ -b1111 6_+(g +1! +b1111 # +b1111 $ #58000000 -0`[J;" +0! #59000000 -1`[J;" -b0 rPs;{ -b0 6_+(g +1! +b0 # +b0 $ #60000000 -0`[J;" +0! #61000000 -1`[J;" -b1 rPs;{ -b1 6_+(g +1! +b1 # +b1 $ #62000000 -0`[J;" +0! #63000000 -1`[J;" -b10 rPs;{ -b10 6_+(g +1! +b10 # +b10 $ #64000000 -0`[J;" +0! #65000000 -1`[J;" -b11 rPs;{ -b11 6_+(g +1! +b11 # +b11 $ #66000000 diff --git a/crates/fayalite/tests/sim/expected/counter_sync.vcd b/crates/fayalite/tests/sim/expected/counter_sync.vcd index f6a8177..9504a30 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.vcd +++ b/crates/fayalite/tests/sim/expected/counter_sync.vcd @@ -1,214 +1,214 @@ $timescale 1 ps $end $scope module counter $end $scope struct cd $end -$var wire 1 `[J;" clk $end -$var wire 1 4pZx7 rst $end +$var wire 1 ! clk $end +$var wire 1 " rst $end $upscope $end -$var wire 4 rPs;{ count $end -$var reg 4 6_+(g count_reg $end +$var wire 4 # count $end +$var reg 4 $ count_reg $end $upscope $end $enddefinitions $end $dumpvars -0`[J;" -14pZx7 -b0 rPs;{ -b0 6_+(g +0! +1" +b0 # +b0 $ $end #1000000 -1`[J;" -b11 rPs;{ -b11 6_+(g -04pZx7 +1! +b11 # +b11 $ +0" #2000000 -0`[J;" +0! #3000000 -1`[J;" -b100 rPs;{ -b100 6_+(g +1! +b100 # +b100 $ #4000000 -0`[J;" +0! #5000000 -1`[J;" -b101 rPs;{ -b101 6_+(g +1! +b101 # +b101 $ #6000000 -0`[J;" +0! #7000000 -1`[J;" -b110 rPs;{ -b110 6_+(g +1! +b110 # +b110 $ #8000000 -0`[J;" +0! #9000000 -1`[J;" -b111 rPs;{ -b111 6_+(g +1! +b111 # +b111 $ #10000000 -0`[J;" +0! #11000000 -1`[J;" -b1000 rPs;{ -b1000 6_+(g +1! +b1000 # +b1000 $ #12000000 -0`[J;" +0! #13000000 -1`[J;" -b1001 rPs;{ -b1001 6_+(g +1! +b1001 # +b1001 $ #14000000 -0`[J;" +0! #15000000 -1`[J;" -b1010 rPs;{ -b1010 6_+(g +1! +b1010 # +b1010 $ #16000000 -0`[J;" +0! #17000000 -1`[J;" -b1011 rPs;{ -b1011 6_+(g +1! +b1011 # +b1011 $ #18000000 -0`[J;" +0! #19000000 -1`[J;" -b1100 rPs;{ -b1100 6_+(g +1! +b1100 # +b1100 $ #20000000 -0`[J;" +0! #21000000 -1`[J;" -b1101 rPs;{ -b1101 6_+(g +1! +b1101 # +b1101 $ #22000000 -0`[J;" +0! #23000000 -1`[J;" -b1110 rPs;{ -b1110 6_+(g +1! +b1110 # +b1110 $ #24000000 -0`[J;" +0! #25000000 -1`[J;" -b1111 rPs;{ -b1111 6_+(g +1! +b1111 # +b1111 $ #26000000 -0`[J;" +0! #27000000 -1`[J;" -b0 rPs;{ -b0 6_+(g +1! +b0 # +b0 $ #28000000 -0`[J;" +0! #29000000 -1`[J;" -b1 rPs;{ -b1 6_+(g +1! +b1 # +b1 $ #30000000 -0`[J;" +0! #31000000 -1`[J;" -b10 rPs;{ -b10 6_+(g +1! +b10 # +b10 $ #32000000 -0`[J;" +0! #33000000 -1`[J;" -b11 rPs;{ -b11 6_+(g +1! +b11 # +b11 $ #34000000 -0`[J;" +0! #35000000 -1`[J;" -b100 rPs;{ -b100 6_+(g +1! +b100 # +b100 $ #36000000 -0`[J;" +0! #37000000 -1`[J;" -b101 rPs;{ -b101 6_+(g +1! +b101 # +b101 $ #38000000 -0`[J;" +0! #39000000 -1`[J;" -b110 rPs;{ -b110 6_+(g +1! +b110 # +b110 $ #40000000 -0`[J;" +0! #41000000 -1`[J;" -b111 rPs;{ -b111 6_+(g +1! +b111 # +b111 $ #42000000 -0`[J;" +0! #43000000 -1`[J;" -b1000 rPs;{ -b1000 6_+(g +1! +b1000 # +b1000 $ #44000000 -0`[J;" +0! #45000000 -1`[J;" -b1001 rPs;{ -b1001 6_+(g +1! +b1001 # +b1001 $ #46000000 -0`[J;" +0! #47000000 -1`[J;" -b1010 rPs;{ -b1010 6_+(g +1! +b1010 # +b1010 $ #48000000 -0`[J;" +0! #49000000 -1`[J;" -b1011 rPs;{ -b1011 6_+(g +1! +b1011 # +b1011 $ #50000000 -0`[J;" +0! #51000000 -1`[J;" -b1100 rPs;{ -b1100 6_+(g +1! +b1100 # +b1100 $ #52000000 -0`[J;" +0! #53000000 -1`[J;" -b1101 rPs;{ -b1101 6_+(g +1! +b1101 # +b1101 $ #54000000 -0`[J;" +0! #55000000 -1`[J;" -b1110 rPs;{ -b1110 6_+(g +1! +b1110 # +b1110 $ #56000000 -0`[J;" +0! #57000000 -1`[J;" -b1111 rPs;{ -b1111 6_+(g +1! +b1111 # +b1111 $ #58000000 -0`[J;" +0! #59000000 -1`[J;" -b0 rPs;{ -b0 6_+(g +1! +b0 # +b0 $ #60000000 -0`[J;" +0! #61000000 -1`[J;" -b1 rPs;{ -b1 6_+(g +1! +b1 # +b1 $ #62000000 -0`[J;" +0! #63000000 -1`[J;" -b10 rPs;{ -b10 6_+(g +1! +b10 # +b10 $ #64000000 -0`[J;" +0! #65000000 -1`[J;" -b11 rPs;{ -b11 6_+(g +1! +b11 # +b11 $ #66000000 diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.vcd b/crates/fayalite/tests/sim/expected/duplicate_names.vcd index 238c074..1e9f6c6 100644 --- a/crates/fayalite/tests/sim/expected/duplicate_names.vcd +++ b/crates/fayalite/tests/sim/expected/duplicate_names.vcd @@ -1,11 +1,11 @@ $timescale 1 ps $end $scope module duplicate_names $end -$var wire 8 7[_7. w $end -$var wire 8 7[_7." w_2 $end +$var wire 8 ! w $end +$var wire 8 " w_2 $end $upscope $end $enddefinitions $end $dumpvars -b101 7[_7. -b110 7[_7." +b101 ! +b110 " $end #1000000 diff --git a/crates/fayalite/tests/sim/expected/enums.vcd b/crates/fayalite/tests/sim/expected/enums.vcd index 03682b1..aff867b 100644 --- a/crates/fayalite/tests/sim/expected/enums.vcd +++ b/crates/fayalite/tests/sim/expected/enums.vcd @@ -1,126 +1,126 @@ $timescale 1 ps $end $scope module enums $end $scope struct cd $end -$var wire 1 0n\U< clk $end -$var wire 1 a?A!) rst $end +$var wire 1 ! clk $end +$var wire 1 " rst $end $upscope $end -$var wire 1 #ZQY# en $end -$var wire 2 8?II+ which_in $end -$var wire 4 OO,N+ data_in $end -$var wire 2 yr2gr which_out $end -$var wire 4 q_O;Y data_out $end +$var wire 1 # en $end +$var wire 2 $ which_in $end +$var wire 4 % data_in $end +$var wire 2 & which_out $end +$var wire 4 ' data_out $end $scope struct b_out $end -$var string 1 7L1gf \$tag $end +$var string 1 ( \$tag $end $scope struct HdlSome $end -$var wire 1 EO?Ju \0 $end -$var wire 1 cGtNN \1 $end +$var wire 1 ) \0 $end +$var wire 1 * \1 $end $upscope $end $upscope $end $scope struct b2_out $end -$var string 1 dqd@B \$tag $end +$var string 1 + \$tag $end $scope struct HdlSome $end -$var wire 1 (FG:I \0 $end -$var wire 1 dzy-= \1 $end +$var wire 1 , \0 $end +$var wire 1 - \1 $end $upscope $end $upscope $end $scope struct the_reg $end -$var string 1 J#9uO \$tag $end +$var string 1 . \$tag $end $scope struct B $end -$var reg 1 ca2Gh \0 $end -$var reg 1 f)r)? \1 $end +$var reg 1 / \0 $end +$var reg 1 0 \1 $end $upscope $end $scope struct C $end $scope struct a $end -$var reg 1 ;BepJ \[0] $end -$var reg 1 J~2;e \[1] $end +$var reg 1 1 \[0] $end +$var reg 1 2 \[1] $end $upscope $end -$var reg 2 w\b)K b $end +$var reg 2 3 b $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -00n\U< -1a?A!) -0#ZQY# -b0 8?II+ -b0 OO,N+ -b0 yr2gr -b0 q_O;Y -sHdlNone\x20(0) 7L1gf -0EO?Ju -0cGtNN -sHdlNone\x20(0) dqd@B -0(FG:I -0dzy-= -sA\x20(0) J#9uO -0ca2Gh -0f)r)? -0;BepJ -0J~2;e -b0 w\b)K +0! +1" +0# +b0 $ +b0 % +b0 & +b0 ' +sHdlNone\x20(0) ( +0) +0* +sHdlNone\x20(0) + +0, +0- +sA\x20(0) . +0/ +00 +01 +02 +b0 3 $end #1000000 -10n\U< +1! #1100000 -0a?A!) +0" #2000000 -00n\U< +0! #3000000 -10n\U< +1! #4000000 -1#ZQY# -b1 8?II+ -00n\U< +1# +b1 $ +0! #5000000 -10n\U< -b1 yr2gr -sHdlSome\x20(1) 7L1gf -sHdlSome\x20(1) dqd@B -sB\x20(1) J#9uO +1! +b1 & +sHdlSome\x20(1) ( +sHdlSome\x20(1) + +sB\x20(1) . #6000000 -0#ZQY# -b0 8?II+ -00n\U< +0# +b0 $ +0! #7000000 -10n\U< +1! #8000000 -1#ZQY# -b1 8?II+ -b1111 OO,N+ -00n\U< +1# +b1 $ +b1111 % +0! #9000000 -10n\U< -b11 q_O;Y -1EO?Ju -1cGtNN -1(FG:I -1dzy-= -1ca2Gh -1f)r)? -1;BepJ -1J~2;e +1! +b11 ' +1) +1* +1, +1- +1/ +10 +11 +12 #10000000 -00n\U< +0! #11000000 -10n\U< +1! #12000000 -b10 8?II+ -00n\U< +b10 $ +0! #13000000 -10n\U< -b10 yr2gr -b1111 q_O;Y -sHdlNone\x20(0) 7L1gf -0EO?Ju -0cGtNN -sHdlNone\x20(0) dqd@B -0(FG:I -0dzy-= -sC\x20(2) J#9uO -b11 w\b)K +1! +b10 & +b1111 ' +sHdlNone\x20(0) ( +0) +0* +sHdlNone\x20(0) + +0, +0- +sC\x20(2) . +b11 3 #14000000 -00n\U< +0! #15000000 -10n\U< +1! #16000000 diff --git a/crates/fayalite/tests/sim/expected/extern_module.vcd b/crates/fayalite/tests/sim/expected/extern_module.vcd index 21ec5b9..5d6a0bc 100644 --- a/crates/fayalite/tests/sim/expected/extern_module.vcd +++ b/crates/fayalite/tests/sim/expected/extern_module.vcd @@ -1,52 +1,52 @@ $timescale 1 ps $end $scope module extern_module $end -$var wire 1 `MLd_ i $end -$var wire 1 ^;OnJ o $end +$var wire 1 ! i $end +$var wire 1 " o $end $upscope $end $enddefinitions $end $dumpvars -0`MLd_ -0^;OnJ +0! +0" $end -1^;OnJ +1" #500000 #1500000 -0^;OnJ +0" #2500000 -1^;OnJ +1" #3500000 -0^;OnJ +0" #4500000 -1^;OnJ +1" #5500000 -0^;OnJ +0" #6500000 -1^;OnJ +1" #7500000 -0^;OnJ +0" #8500000 -1^;OnJ +1" #9500000 -0^;OnJ +0" #10000000 -1`MLd_ +1! #10500000 #11500000 -1^;OnJ +1" #12500000 -0^;OnJ +0" #13500000 -1^;OnJ +1" #14500000 -0^;OnJ +0" #15500000 -1^;OnJ +1" #16500000 -0^;OnJ +0" #17500000 -1^;OnJ +1" #18500000 -0^;OnJ +0" #19500000 -1^;OnJ +1" #20000000 diff --git a/crates/fayalite/tests/sim/expected/extern_module2.vcd b/crates/fayalite/tests/sim/expected/extern_module2.vcd index bf0885a..4204567 100644 --- a/crates/fayalite/tests/sim/expected/extern_module2.vcd +++ b/crates/fayalite/tests/sim/expected/extern_module2.vcd @@ -1,151 +1,151 @@ $timescale 1 ps $end $scope module extern_module2 $end -$var wire 1 oHT(x en $end -$var wire 1 nHT-: clk $end -$var wire 8 0:wF& o $end +$var wire 1 ! en $end +$var wire 1 " clk $end +$var wire 8 # o $end $upscope $end $enddefinitions $end $dumpvars -1oHT(x -0nHT-: -b0 0:wF& +1! +0" +b0 # $end -b1001000 0:wF& +b1001000 # #1000000 -1nHT-: -b1100101 0:wF& +1" +b1100101 # #2000000 -0nHT-: +0" #3000000 -1nHT-: -b1101100 0:wF& +1" +b1101100 # #4000000 -0nHT-: +0" #5000000 -1nHT-: +1" #6000000 -0nHT-: +0" #7000000 -1nHT-: -b1101111 0:wF& +1" +b1101111 # #8000000 -0nHT-: +0" #9000000 -1nHT-: -b101100 0:wF& +1" +b101100 # #10000000 -0oHT(x -0nHT-: +0! +0" #11000000 -1nHT-: +1" #12000000 -0nHT-: +0" #13000000 -1nHT-: +1" #14000000 -0nHT-: +0" #15000000 -1nHT-: +1" #16000000 -0nHT-: +0" #17000000 -1nHT-: +1" #18000000 -0nHT-: +0" #19000000 -1nHT-: +1" #20000000 -1oHT(x -0nHT-: +1! +0" #21000000 -1nHT-: -b100000 0:wF& +1" +b100000 # #22000000 -0nHT-: +0" #23000000 -1nHT-: -b1010111 0:wF& +1" +b1010111 # #24000000 -0nHT-: +0" #25000000 -1nHT-: -b1101111 0:wF& +1" +b1101111 # #26000000 -0nHT-: +0" #27000000 -1nHT-: -b1110010 0:wF& +1" +b1110010 # #28000000 -0nHT-: +0" #29000000 -1nHT-: -b1101100 0:wF& +1" +b1101100 # #30000000 -0oHT(x -0nHT-: +0! +0" #31000000 -1nHT-: +1" #32000000 -0nHT-: +0" #33000000 -1nHT-: +1" #34000000 -0nHT-: +0" #35000000 -1nHT-: +1" #36000000 -0nHT-: +0" #37000000 -1nHT-: +1" #38000000 -0nHT-: +0" #39000000 -1nHT-: +1" #40000000 -1oHT(x -0nHT-: +1! +0" #41000000 -1nHT-: -b1100100 0:wF& +1" +b1100100 # #42000000 -0nHT-: +0" #43000000 -1nHT-: -b100001 0:wF& +1" +b100001 # #44000000 -0nHT-: +0" #45000000 -1nHT-: -b1010 0:wF& +1" +b1010 # #46000000 -0nHT-: +0" #47000000 -1nHT-: -b1001000 0:wF& +1" +b1001000 # #48000000 -0nHT-: +0" #49000000 -1nHT-: -b1100101 0:wF& +1" +b1100101 # #50000000 -0oHT(x -0nHT-: +0! +0" #51000000 -1nHT-: +1" #52000000 -0nHT-: +0" #53000000 -1nHT-: +1" #54000000 -0nHT-: +0" #55000000 -1nHT-: +1" #56000000 -0nHT-: +0" #57000000 -1nHT-: +1" #58000000 -0nHT-: +0" #59000000 -1nHT-: +1" #60000000 diff --git a/crates/fayalite/tests/sim/expected/many_memories.vcd b/crates/fayalite/tests/sim/expected/many_memories.vcd index db41ca3..77d1447 100644 --- a/crates/fayalite/tests/sim/expected/many_memories.vcd +++ b/crates/fayalite/tests/sim/expected/many_memories.vcd @@ -2,2595 +2,2595 @@ $timescale 1 ps $end $scope module many_memories $end $scope struct r $end $scope struct \[0] $end -$var wire 4 d|7Sd addr $end -$var wire 1 bl7[X en $end -$var wire 1 17/]f clk $end -$var wire 1 0*lF; data $end +$var wire 4 ! addr $end +$var wire 1 " en $end +$var wire 1 # clk $end +$var wire 1 $ data $end $upscope $end $scope struct \[1] $end -$var wire 4 0?lo9 addr $end -$var wire 1 iP},z en $end -$var wire 1 5Gki< clk $end -$var wire 1 5MnH3 data $end +$var wire 4 % addr $end +$var wire 1 & en $end +$var wire 1 ' clk $end +$var wire 1 ( data $end $upscope $end $scope struct \[2] $end -$var wire 4 AvJcz addr $end -$var wire 1 mSys{ en $end -$var wire 1 jJ+ac clk $end -$var wire 1 4C05W data $end +$var wire 4 ) addr $end +$var wire 1 * en $end +$var wire 1 + clk $end +$var wire 1 , data $end $upscope $end $scope struct \[3] $end -$var wire 4 sC0ee addr $end -$var wire 1 tG`f% en $end -$var wire 1 V1=.M clk $end -$var wire 1 6!E3h data $end +$var wire 4 - addr $end +$var wire 1 . en $end +$var wire 1 / clk $end +$var wire 1 0 data $end $upscope $end $scope struct \[4] $end -$var wire 4 j,j"< addr $end -$var wire 1 >[_ax en $end -$var wire 1 (v:Ix clk $end -$var wire 1 J[r\_ data $end +$var wire 4 1 addr $end +$var wire 1 2 en $end +$var wire 1 3 clk $end +$var wire 1 4 data $end $upscope $end $scope struct \[5] $end -$var wire 4 OXs&> addr $end -$var wire 1 lu%y\ en $end -$var wire 1 l=z|A clk $end -$var wire 1 +UTFi data $end +$var wire 4 5 addr $end +$var wire 1 6 en $end +$var wire 1 7 clk $end +$var wire 1 8 data $end $upscope $end $scope struct \[6] $end -$var wire 4 iC]Q& addr $end -$var wire 1 h:kXG en $end -$var wire 1 hP6aI clk $end -$var wire 1 72ujb data $end +$var wire 4 9 addr $end +$var wire 1 : en $end +$var wire 1 ; clk $end +$var wire 1 < data $end $upscope $end $scope struct \[7] $end -$var wire 4 "I):@ addr $end -$var wire 1 rw'Lc en $end -$var wire 1 Vvn/E clk $end -$var wire 1 .[P*8 data $end +$var wire 4 = addr $end +$var wire 1 > en $end +$var wire 1 ? clk $end +$var wire 1 @ data $end $upscope $end $upscope $end $scope struct w $end $scope struct \[0] $end -$var wire 4 W9?X. addr $end -$var wire 1 4Dh3Z en $end -$var wire 1 $\W(J clk $end -$var wire 1 cH{Ze data $end -$var wire 1 _OA4l mask $end +$var wire 4 A addr $end +$var wire 1 B en $end +$var wire 1 C clk $end +$var wire 1 D data $end +$var wire 1 E mask $end $upscope $end $scope struct \[1] $end -$var wire 4 6,|K% addr $end -$var wire 1 #'qYA en $end -$var wire 1 QI!iU clk $end -$var wire 1 |di=b data $end -$var wire 1 BCB!} mask $end +$var wire 4 F addr $end +$var wire 1 G en $end +$var wire 1 H clk $end +$var wire 1 I data $end +$var wire 1 J mask $end $upscope $end $scope struct \[2] $end -$var wire 4 $i,h9 addr $end -$var wire 1 =4Sky en $end -$var wire 1 EC,z> clk $end -$var wire 1 y;\Pv data $end -$var wire 1 1XcmV mask $end +$var wire 4 K addr $end +$var wire 1 L en $end +$var wire 1 M clk $end +$var wire 1 N data $end +$var wire 1 O mask $end $upscope $end $scope struct \[3] $end -$var wire 4 IC,mz addr $end -$var wire 1 LM^hS en $end -$var wire 1 mm5\_ clk $end -$var wire 1 KYJ1[ data $end -$var wire 1 ;wrI1 mask $end +$var wire 4 P addr $end +$var wire 1 Q en $end +$var wire 1 R clk $end +$var wire 1 S data $end +$var wire 1 T mask $end $upscope $end $scope struct \[4] $end -$var wire 4 ^%H-d addr $end -$var wire 1 {{"vF en $end -$var wire 1 sfo}Z clk $end -$var wire 1 VxyrG data $end -$var wire 1 rjp*# mask $end +$var wire 4 U addr $end +$var wire 1 V en $end +$var wire 1 W clk $end +$var wire 1 X data $end +$var wire 1 Y mask $end $upscope $end $scope struct \[5] $end -$var wire 4 %xhho addr $end -$var wire 1 ]0GiL en $end -$var wire 1 )|%6{ clk $end -$var wire 1 ,3Sf| data $end -$var wire 1 oJrGc mask $end +$var wire 4 Z addr $end +$var wire 1 [ en $end +$var wire 1 \ clk $end +$var wire 1 ] data $end +$var wire 1 ^ mask $end $upscope $end $scope struct \[6] $end -$var wire 4 TdJW4 addr $end -$var wire 1 LjMuL en $end -$var wire 1 t'l~] clk $end -$var wire 1 <}D%K data $end -$var wire 1 @0}S5 mask $end +$var wire 4 _ addr $end +$var wire 1 ` en $end +$var wire 1 a clk $end +$var wire 1 b data $end +$var wire 1 c mask $end $upscope $end $scope struct \[7] $end -$var wire 4 @T;Mg addr $end -$var wire 1 lGp}g en $end -$var wire 1 [|v\H$ addr $end -$var wire 1 1dk]f en $end -$var wire 1 B(P|B clk $end -$var wire 1 {)s\9 data $end +$var wire 4 i addr $end +$var wire 1 j en $end +$var wire 1 k clk $end +$var wire 1 l data $end $upscope $end $scope struct w1 $end -$var wire 4 |Xtj6 addr $end -$var wire 1 kEHuz en $end -$var wire 1 .7gMQ clk $end -$var wire 1 GC4id data $end -$var wire 1 po>X< mask $end +$var wire 4 m addr $end +$var wire 1 n en $end +$var wire 1 o clk $end +$var wire 1 p data $end +$var wire 1 q mask $end $upscope $end $upscope $end $scope struct mem_1 $end $scope struct contents $end $scope struct \[0] $end -$var reg 1 lk3NH mem_1 $end +$var reg 1 c" mem_1 $end $upscope $end $scope struct \[1] $end -$var reg 1 V]u6p mem_1 $end +$var reg 1 d" mem_1 $end $upscope $end $scope struct \[2] $end -$var reg 1 U=Gh> mem_1 $end +$var reg 1 e" mem_1 $end $upscope $end $scope struct \[3] $end -$var reg 1 1Fg?Y mem_1 $end +$var reg 1 f" mem_1 $end $upscope $end $scope struct \[4] $end -$var reg 1 x[-fM mem_1 $end +$var reg 1 g" mem_1 $end $upscope $end $scope struct \[5] $end -$var reg 1 $1^H, mem_1 $end +$var reg 1 h" mem_1 $end $upscope $end $scope struct \[6] $end -$var reg 1 0M$4D mem_1 $end +$var reg 1 i" mem_1 $end $upscope $end $scope struct \[7] $end -$var reg 1 CN_fu mem_1 $end +$var reg 1 j" mem_1 $end $upscope $end $scope struct \[8] $end -$var reg 1 K/ql@ mem_1 $end +$var reg 1 k" mem_1 $end $upscope $end $scope struct \[9] $end -$var reg 1 '%]Ik mem_1 $end +$var reg 1 l" mem_1 $end $upscope $end $scope struct \[10] $end -$var reg 1 M[~-; mem_1 $end +$var reg 1 m" mem_1 $end $upscope $end $scope struct \[11] $end -$var reg 1 ae(_Y mem_1 $end +$var reg 1 n" mem_1 $end $upscope $end $scope struct \[12] $end -$var reg 1 @~%Yu mem_1 $end +$var reg 1 o" mem_1 $end $upscope $end $scope struct \[13] $end -$var reg 1 bly?K mem_1 $end +$var reg 1 p" mem_1 $end $upscope $end $scope struct \[14] $end -$var reg 1 ;l0g- mem_1 $end +$var reg 1 q" mem_1 $end $upscope $end $scope struct \[15] $end -$var reg 1 Pc5L mem_1 $end +$var reg 1 r" mem_1 $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 4 ,SVcw addr $end -$var wire 1 crI6R en $end -$var wire 1 7}oLq clk $end -$var wire 1 pv)Ph data $end +$var wire 4 r addr $end +$var wire 1 s en $end +$var wire 1 t clk $end +$var wire 1 u data $end $upscope $end $scope struct w1 $end -$var wire 4 E%~x' addr $end -$var wire 1 K9WYT en $end -$var wire 1 a~%H' clk $end -$var wire 1 |=vD0 data $end -$var wire 1 ]K`^ mask $end +$var wire 4 v addr $end +$var wire 1 w en $end +$var wire 1 x clk $end +$var wire 1 y data $end +$var wire 1 z mask $end $upscope $end $upscope $end $scope struct mem_2 $end $scope struct contents $end $scope struct \[0] $end -$var reg 1 S33J- mem_2 $end +$var reg 1 s" mem_2 $end $upscope $end $scope struct \[1] $end -$var reg 1 6|@8V mem_2 $end +$var reg 1 t" mem_2 $end $upscope $end $scope struct \[2] $end -$var reg 1 >&bO) mem_2 $end +$var reg 1 u" mem_2 $end $upscope $end $scope struct \[3] $end -$var reg 1 I6cQ4 mem_2 $end +$var reg 1 v" mem_2 $end $upscope $end $scope struct \[4] $end -$var reg 1 6<\}Q mem_2 $end +$var reg 1 w" mem_2 $end $upscope $end $scope struct \[5] $end -$var reg 1 f:Ue2 mem_2 $end +$var reg 1 x" mem_2 $end $upscope $end $scope struct \[6] $end -$var reg 1 5Me%A mem_2 $end +$var reg 1 y" mem_2 $end $upscope $end $scope struct \[7] $end -$var reg 1 o?yX1 mem_2 $end +$var reg 1 z" mem_2 $end $upscope $end $scope struct \[8] $end -$var reg 1 _usg8 mem_2 $end +$var reg 1 {" mem_2 $end $upscope $end $scope struct \[9] $end -$var reg 1 VrGM\ mem_2 $end +$var reg 1 |" mem_2 $end $upscope $end $scope struct \[10] $end -$var reg 1 "CN$B mem_2 $end +$var reg 1 }" mem_2 $end $upscope $end $scope struct \[11] $end -$var reg 1 &Kn]3 mem_2 $end +$var reg 1 ~" mem_2 $end $upscope $end $scope struct \[12] $end -$var reg 1 pidX) mem_2 $end +$var reg 1 !# mem_2 $end $upscope $end $scope struct \[13] $end -$var reg 1 JXxH( mem_2 $end +$var reg 1 "# mem_2 $end $upscope $end $scope struct \[14] $end -$var reg 1 alU~# mem_2 $end +$var reg 1 ## mem_2 $end $upscope $end $scope struct \[15] $end -$var reg 1 o4-M= mem_2 $end +$var reg 1 $# mem_2 $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 4 8K@uI addr $end -$var wire 1 BL~4g en $end -$var wire 1 B{,;o mem_3 $end +$var reg 1 -# mem_3 $end $upscope $end $scope struct \[9] $end -$var reg 1 @|$h( mem_3 $end +$var reg 1 .# mem_3 $end $upscope $end $scope struct \[10] $end -$var reg 1 sey{< mem_3 $end +$var reg 1 /# mem_3 $end $upscope $end $scope struct \[11] $end -$var reg 1 RbWU} mem_3 $end +$var reg 1 0# mem_3 $end $upscope $end $scope struct \[12] $end -$var reg 1 S09. mem_3 $end +$var reg 1 4# mem_3 $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 4 QLM%y addr $end -$var wire 1 7k:)O en $end -$var wire 1 }oa[9 clk $end -$var wire 1 GfxP1 data $end +$var wire 4 &" addr $end +$var wire 1 '" en $end +$var wire 1 (" clk $end +$var wire 1 )" data $end $upscope $end $scope struct w1 $end -$var wire 4 z$\>X addr $end -$var wire 1 J%@q: en $end -$var wire 1 xI.Te clk $end -$var wire 1 ),_Fe data $end -$var wire 1 %MYTb mask $end +$var wire 4 *" addr $end +$var wire 1 +" en $end +$var wire 1 ," clk $end +$var wire 1 -" data $end +$var wire 1 ." mask $end $upscope $end $upscope $end $scope struct mem_4 $end $scope struct contents $end $scope struct \[0] $end -$var reg 1 qH-C: mem_4 $end +$var reg 1 5# mem_4 $end $upscope $end $scope struct \[1] $end -$var reg 1 7085? mem_4 $end +$var reg 1 6# mem_4 $end $upscope $end $scope struct \[2] $end -$var reg 1 OvgNF mem_4 $end +$var reg 1 7# mem_4 $end $upscope $end $scope struct \[3] $end -$var reg 1 RYxHq mem_4 $end +$var reg 1 8# mem_4 $end $upscope $end $scope struct \[4] $end -$var reg 1 vxZgk mem_4 $end +$var reg 1 9# mem_4 $end $upscope $end $scope struct \[5] $end -$var reg 1 5$~C^ mem_4 $end +$var reg 1 :# mem_4 $end $upscope $end $scope struct \[6] $end -$var reg 1 xtUn" mem_4 $end +$var reg 1 ;# mem_4 $end $upscope $end $scope struct \[7] $end -$var reg 1 (z5:+ mem_4 $end +$var reg 1 <# mem_4 $end $upscope $end $scope struct \[8] $end -$var reg 1 YjR,s mem_4 $end +$var reg 1 =# mem_4 $end $upscope $end $scope struct \[9] $end -$var reg 1 rT%&} mem_4 $end +$var reg 1 ># mem_4 $end $upscope $end $scope struct \[10] $end -$var reg 1 O!KVd mem_4 $end +$var reg 1 ?# mem_4 $end $upscope $end $scope struct \[11] $end -$var reg 1 ?7>@X mem_4 $end +$var reg 1 @# mem_4 $end $upscope $end $scope struct \[12] $end -$var reg 1 nZ6qC mem_4 $end +$var reg 1 A# mem_4 $end $upscope $end $scope struct \[13] $end -$var reg 1 gYe2 mem_4 $end +$var reg 1 B# mem_4 $end $upscope $end $scope struct \[14] $end -$var reg 1 B#~Pl mem_4 $end +$var reg 1 C# mem_4 $end $upscope $end $scope struct \[15] $end -$var reg 1 lG!\@ mem_4 $end +$var reg 1 D# mem_4 $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 4 (M75i addr $end -$var wire 1 Eieoc en $end -$var wire 1 y0m-; clk $end -$var wire 1 3EUJ' data $end +$var wire 4 /" addr $end +$var wire 1 0" en $end +$var wire 1 1" clk $end +$var wire 1 2" data $end $upscope $end $scope struct w1 $end -$var wire 4 'N|N? addr $end -$var wire 1 /S-9% en $end -$var wire 1 0vX"- clk $end -$var wire 1 HE6Kx data $end -$var wire 1 hQ>V( mask $end +$var wire 4 3" addr $end +$var wire 1 4" en $end +$var wire 1 5" clk $end +$var wire 1 6" data $end +$var wire 1 7" mask $end $upscope $end $upscope $end $scope struct mem_5 $end $scope struct contents $end $scope struct \[0] $end -$var reg 1 1GGb_ mem_5 $end +$var reg 1 E# mem_5 $end $upscope $end $scope struct \[1] $end -$var reg 1 LxqC. mem_5 $end +$var reg 1 F# mem_5 $end $upscope $end $scope struct \[2] $end -$var reg 1 3&byj mem_5 $end +$var reg 1 G# mem_5 $end $upscope $end $scope struct \[3] $end -$var reg 1 ]c~pH mem_5 $end +$var reg 1 H# mem_5 $end $upscope $end $scope struct \[4] $end -$var reg 1 gn[Z# mem_5 $end +$var reg 1 I# mem_5 $end $upscope $end $scope struct \[5] $end -$var reg 1 kk4^N mem_5 $end +$var reg 1 J# mem_5 $end $upscope $end $scope struct \[6] $end -$var reg 1 FM>f& mem_5 $end +$var reg 1 K# mem_5 $end $upscope $end $scope struct \[7] $end -$var reg 1 JURf" mem_5 $end +$var reg 1 L# mem_5 $end $upscope $end $scope struct \[8] $end -$var reg 1 ^|(GS mem_5 $end +$var reg 1 M# mem_5 $end $upscope $end $scope struct \[9] $end -$var reg 1 q>Dbi mem_5 $end +$var reg 1 N# mem_5 $end $upscope $end $scope struct \[10] $end -$var reg 1 v,X*" mem_5 $end +$var reg 1 O# mem_5 $end $upscope $end $scope struct \[11] $end -$var reg 1 rU3!' mem_5 $end +$var reg 1 P# mem_5 $end $upscope $end $scope struct \[12] $end -$var reg 1 ubZS. mem_5 $end +$var reg 1 Q# mem_5 $end $upscope $end $scope struct \[13] $end -$var reg 1 lS`!+ mem_5 $end +$var reg 1 R# mem_5 $end $upscope $end $scope struct \[14] $end -$var reg 1 wlw&y mem_5 $end +$var reg 1 S# mem_5 $end $upscope $end $scope struct \[15] $end -$var reg 1 VVy9L mem_5 $end +$var reg 1 T# mem_5 $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 4 ].DK0 addr $end -$var wire 1 C#?U9 en $end -$var wire 1 E~'G) clk $end -$var wire 1 m0~w" data $end +$var wire 4 8" addr $end +$var wire 1 9" en $end +$var wire 1 :" clk $end +$var wire 1 ;" data $end $upscope $end $scope struct w1 $end -$var wire 4 6Sh6[ addr $end -$var wire 1 vYM@u en $end -$var wire 1 =hC'C clk $end -$var wire 1 %\?Z# data $end -$var wire 1 +[l=? mask $end +$var wire 4 <" addr $end +$var wire 1 =" en $end +$var wire 1 >" clk $end +$var wire 1 ?" data $end +$var wire 1 @" mask $end $upscope $end $upscope $end $scope struct mem_6 $end $scope struct contents $end $scope struct \[0] $end -$var reg 1 V#g\W mem_6 $end +$var reg 1 U# mem_6 $end $upscope $end $scope struct \[1] $end -$var reg 1 X@70L mem_6 $end +$var reg 1 V# mem_6 $end $upscope $end $scope struct \[2] $end -$var reg 1 o/;vI mem_6 $end +$var reg 1 W# mem_6 $end $upscope $end $scope struct \[3] $end -$var reg 1 nNNhp mem_6 $end +$var reg 1 X# mem_6 $end $upscope $end $scope struct \[4] $end -$var reg 1 g[SEK mem_6 $end +$var reg 1 Y# mem_6 $end $upscope $end $scope struct \[5] $end -$var reg 1 49L)5 mem_6 $end +$var reg 1 Z# mem_6 $end $upscope $end $scope struct \[6] $end -$var reg 1 fl?5< mem_6 $end +$var reg 1 [# mem_6 $end $upscope $end $scope struct \[7] $end -$var reg 1 {,;|[ mem_6 $end +$var reg 1 \# mem_6 $end $upscope $end $scope struct \[8] $end -$var reg 1 kFDen mem_6 $end +$var reg 1 ]# mem_6 $end $upscope $end $scope struct \[9] $end -$var reg 1 lu;*r mem_6 $end +$var reg 1 ^# mem_6 $end $upscope $end $scope struct \[10] $end -$var reg 1 sinoU mem_6 $end +$var reg 1 _# mem_6 $end $upscope $end $scope struct \[11] $end -$var reg 1 >o]Q( mem_6 $end +$var reg 1 `# mem_6 $end $upscope $end $scope struct \[12] $end -$var reg 1 !1]}f mem_6 $end +$var reg 1 a# mem_6 $end $upscope $end $scope struct \[13] $end -$var reg 1 >IRWA mem_6 $end +$var reg 1 b# mem_6 $end $upscope $end $scope struct \[14] $end -$var reg 1 ]GER# mem_6 $end +$var reg 1 c# mem_6 $end $upscope $end $scope struct \[15] $end -$var reg 1 s&5]X mem_6 $end +$var reg 1 d# mem_6 $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 4 ZWBn} addr $end -$var wire 1 |$cvr en $end -$var wire 1 T)in_ clk $end -$var wire 1 )McFt data $end +$var wire 4 A" addr $end +$var wire 1 B" en $end +$var wire 1 C" clk $end +$var wire 1 D" data $end $upscope $end $scope struct w1 $end -$var wire 4 gpGf3 addr $end -$var wire 1 `kT)O en $end -$var wire 1 fjh5& clk $end -$var wire 1 >&/MW data $end -$var wire 1 *XTPN mask $end +$var wire 4 E" addr $end +$var wire 1 F" en $end +$var wire 1 G" clk $end +$var wire 1 H" data $end +$var wire 1 I" mask $end $upscope $end $upscope $end $scope struct mem_7 $end $scope struct contents $end $scope struct \[0] $end -$var reg 1 <1w8% mem_7 $end +$var reg 1 e# mem_7 $end $upscope $end $scope struct \[1] $end -$var reg 1 33nkV mem_7 $end +$var reg 1 f# mem_7 $end $upscope $end $scope struct \[2] $end -$var reg 1 px}q] mem_7 $end +$var reg 1 g# mem_7 $end $upscope $end $scope struct \[3] $end -$var reg 1 cmnxp mem_7 $end +$var reg 1 h# mem_7 $end $upscope $end $scope struct \[4] $end -$var reg 1 3rQ$Z mem_7 $end +$var reg 1 i# mem_7 $end $upscope $end $scope struct \[5] $end -$var reg 1 5k{84 mem_7 $end +$var reg 1 j# mem_7 $end $upscope $end $scope struct \[6] $end -$var reg 1 PO#rR mem_7 $end +$var reg 1 k# mem_7 $end $upscope $end $scope struct \[7] $end -$var reg 1 ki$A7 mem_7 $end +$var reg 1 l# mem_7 $end $upscope $end $scope struct \[8] $end -$var reg 1 qM^Sv mem_7 $end +$var reg 1 m# mem_7 $end $upscope $end $scope struct \[9] $end -$var reg 1 dF]W- mem_7 $end +$var reg 1 n# mem_7 $end $upscope $end $scope struct \[10] $end -$var reg 1 RzEG+ mem_7 $end +$var reg 1 o# mem_7 $end $upscope $end $scope struct \[11] $end -$var reg 1 "W|s6 mem_7 $end +$var reg 1 p# mem_7 $end $upscope $end $scope struct \[12] $end -$var reg 1 shQ1m mem_7 $end +$var reg 1 q# mem_7 $end $upscope $end $scope struct \[13] $end -$var reg 1 hN^kl mem_7 $end +$var reg 1 r# mem_7 $end $upscope $end $scope struct \[14] $end -$var reg 1 fc7WM mem_7 $end +$var reg 1 s# mem_7 $end $upscope $end $scope struct \[15] $end -$var reg 1 K0W.8 mem_7 $end +$var reg 1 t# mem_7 $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 4 lJ\tx addr $end -$var wire 1 O2d5] en $end -$var wire 1 $Kx=q clk $end -$var wire 1 p[RX3 data $end +$var wire 4 J" addr $end +$var wire 1 K" en $end +$var wire 1 L" clk $end +$var wire 1 M" data $end $upscope $end $scope struct w1 $end -$var wire 4 i|V&P addr $end -$var wire 1 `A40g en $end -$var wire 1 }&U]O clk $end -$var wire 1 {g%2| data $end -$var wire 1 A%,}] mask $end +$var wire 4 N" addr $end +$var wire 1 O" en $end +$var wire 1 P" clk $end +$var wire 1 Q" data $end +$var wire 1 R" mask $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -0BF4b] -0\l3qS -0B{RxL -0aX~=L -0u\Njq -0o#t"z -05K{^g -0+UI{} -0O?gg. -0ciSpV -0kX]/, -0y(Y?# -0!ZUC~ -0xB4/Z -0R^08l -0m,8Ot -1lk3NH -0V]u6p -0U=Gh> -01Fg?Y -0x[-fM -0$1^H, -00M$4D -0CN_fu -0K/ql@ -0'%]Ik -0M[~-; -0ae(_Y -0@~%Yu -0bly?K -0;l0g- -0Pc5L -0S33J- -06|@8V -0>&bO) -0I6cQ4 -06<\}Q -1f:Ue2 -05Me%A -0o?yX1 -0_usg8 -0VrGM\ -0"CN$B -0&Kn]3 -0pidX) -0JXxH( -0alU~# -0o4-M= -1-kXQk -1b")Z[ -0o"+8} -0@E|eA -14E3| -1&r?*\ -1+Qn\G -1MoUR3 -0>{,;o -0@|$h( -0sey{< -0RbWU} -0S09. -0qH-C: -07085? -0OvgNF -0RYxHq -0vxZgk -05$~C^ -0xtUn" -0(z5:+ -0YjR,s -0rT%&} -1O!KVd -0?7>@X -0nZ6qC -0gYe2 -0B#~Pl -0lG!\@ -11GGb_ -0LxqC. -13&byj -0]c~pH -1gn[Z# -1kk4^N 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-0Vvn/E -0$\W(J -0QI!iU -0EC,z> -0mm5\_ -0sfo}Z -0)|%6{ -0t'l~] -0[|v\H$ -0B(P|B -0.7gMQ -b1000 ,SVcw -07}oLq -0a~%H' -b1000 8K@uI -0B" +b1000 A" +0C" +0G" +b1000 J" +0L" +0P" #23000000 -117/]f -15Gki< -1jJ+ac -1V1=.M -1(v:Ix -1l=z|A -1hP6aI -1Vvn/E -1$\W(J -1QI!iU -1EC,z> -1mm5\_ -1sfo}Z -1)|%6{ -1t'l~] -1[|v" +1C" +1G" +1L" +1P" #24000000 -b1001 d|7Sd -017/]f -b1001 0?lo9 -05Gki< -b1001 AvJcz -0jJ+ac -b1001 sC0ee -0V1=.M -b1001 j,j"< -0(v:Ix -b1001 OXs&> -0l=z|A -b1001 iC]Q& -0hP6aI -172ujb -b1001 "I):@ -0Vvn/E -0.[P*8 -0$\W(J -0QI!iU -0EC,z> -0mm5\_ -0sfo}Z -0)|%6{ -0t'l~] -0[|v\H$ -0B(P|B -0.7gMQ -b1001 ,SVcw -07}oLq -0a~%H' -b1001 8K@uI -0B" +b1001 A" +0C" +1D" +0G" +b1001 J" +0L" +0M" +0P" #25000000 -117/]f -15Gki< -1jJ+ac -1V1=.M -1(v:Ix -1l=z|A -1hP6aI -1Vvn/E -1$\W(J -1QI!iU -1EC,z> -1mm5\_ -1sfo}Z -1)|%6{ -1t'l~] -1[|v" +1C" +1G" +1L" +1P" #26000000 -b1010 d|7Sd -017/]f -b1010 0?lo9 -05Gki< -b1010 AvJcz -0jJ+ac -b1010 sC0ee -0V1=.M -b1010 j,j"< -0(v:Ix -1J[r\_ -b1010 OXs&> -0l=z|A -1+UTFi -b1010 iC]Q& -0hP6aI -b1010 "I):@ -0Vvn/E -0$\W(J -0QI!iU -0EC,z> -0mm5\_ -0sfo}Z -0)|%6{ -0t'l~] -0[|v\H$ -0B(P|B -0.7gMQ -b1010 ,SVcw -07}oLq -0a~%H' -b1010 8K@uI -0B" +b1010 A" +0C" +0G" +b1010 J" +0L" +0P" #27000000 -117/]f -15Gki< -1jJ+ac -1V1=.M -1(v:Ix -1l=z|A -1hP6aI -1Vvn/E -1$\W(J -1QI!iU -1EC,z> -1mm5\_ -1sfo}Z -1)|%6{ -1t'l~] -1[|v" +1C" +1G" +1L" +1P" #28000000 -b1011 d|7Sd -017/]f -b1011 0?lo9 -05Gki< -b1011 AvJcz -0jJ+ac -b1011 sC0ee -0V1=.M -b1011 j,j"< -0(v:Ix -0J[r\_ -b1011 OXs&> -0l=z|A -b1011 iC]Q& -0hP6aI -b1011 "I):@ -0Vvn/E -0$\W(J -0QI!iU -0EC,z> -0mm5\_ -0sfo}Z -0)|%6{ -0t'l~] -0[|v\H$ -0B(P|B -0.7gMQ -b1011 ,SVcw -07}oLq -0a~%H' -b1011 8K@uI -0B" +b1011 A" +0C" +0G" +b1011 J" +0L" +0P" #29000000 -117/]f -15Gki< -1jJ+ac -1V1=.M -1(v:Ix -1l=z|A -1hP6aI -1Vvn/E -1$\W(J -1QI!iU -1EC,z> -1mm5\_ -1sfo}Z -1)|%6{ -1t'l~] -1[|v" +1C" +1G" +1L" +1P" #30000000 -b1100 d|7Sd -017/]f -b1100 0?lo9 -05Gki< -b1100 AvJcz -0jJ+ac -b1100 sC0ee -0V1=.M -b1100 j,j"< -0(v:Ix -b1100 OXs&> -0l=z|A -0+UTFi -b1100 iC]Q& -0hP6aI -b1100 "I):@ -0Vvn/E -0$\W(J -0QI!iU -0EC,z> -0mm5\_ -0sfo}Z -0)|%6{ -0t'l~] -0[|v\H$ -0B(P|B -0.7gMQ -b1100 ,SVcw -07}oLq -0a~%H' -b1100 8K@uI -0B" +b1100 A" +0C" +0G" +b1100 J" +0L" +0P" #31000000 -117/]f -15Gki< -1jJ+ac -1V1=.M -1(v:Ix -1l=z|A -1hP6aI -1Vvn/E -1$\W(J -1QI!iU -1EC,z> -1mm5\_ -1sfo}Z -1)|%6{ -1t'l~] -1[|v" +1C" +1G" +1L" +1P" #32000000 -b1101 d|7Sd -017/]f -b1101 0?lo9 -05Gki< -b1101 AvJcz -0jJ+ac -b1101 sC0ee -0V1=.M -b1101 j,j"< -0(v:Ix -b1101 OXs&> -0l=z|A -b1101 iC]Q& -0hP6aI -072ujb -b1101 "I):@ -0Vvn/E -0$\W(J -0QI!iU -0EC,z> -0mm5\_ -0sfo}Z -0)|%6{ -0t'l~] -0[|v\H$ -0B(P|B -0.7gMQ -b1101 ,SVcw -07}oLq -0a~%H' -b1101 8K@uI -0B" +b1101 A" +0C" +0D" +0G" +b1101 J" +0L" +0P" #33000000 -117/]f -15Gki< -1jJ+ac -1V1=.M -1(v:Ix -1l=z|A -1hP6aI -1Vvn/E -1$\W(J -1QI!iU -1EC,z> -1mm5\_ -1sfo}Z -1)|%6{ -1t'l~] -1[|v" +1C" +1G" +1L" +1P" #34000000 -b1110 d|7Sd -017/]f -b1110 0?lo9 -05Gki< -b1110 AvJcz -0jJ+ac -b1110 sC0ee -0V1=.M -b1110 j,j"< -0(v:Ix -b1110 OXs&> -0l=z|A -b1110 iC]Q& -0hP6aI -b1110 "I):@ -0Vvn/E -1.[P*8 -0$\W(J -0QI!iU -0EC,z> -0mm5\_ -0sfo}Z -0)|%6{ -0t'l~] -0[|v\H$ -0B(P|B -0.7gMQ -b1110 ,SVcw -07}oLq -0a~%H' -b1110 8K@uI -0B" +b1110 A" +0C" +0G" +b1110 J" +0L" +1M" +0P" #35000000 -117/]f -15Gki< -1jJ+ac -1V1=.M -1(v:Ix -1l=z|A -1hP6aI -1Vvn/E -1$\W(J -1QI!iU -1EC,z> -1mm5\_ -1sfo}Z -1)|%6{ -1t'l~] -1[|v" +1C" +1G" +1L" +1P" #36000000 -b1111 d|7Sd -017/]f -b1111 0?lo9 -05Gki< -b1111 AvJcz -0jJ+ac -b1111 sC0ee -0V1=.M -b1111 j,j"< -0(v:Ix -b1111 OXs&> -0l=z|A -b1111 iC]Q& -0hP6aI -b1111 "I):@ -0Vvn/E -0.[P*8 -0$\W(J -0QI!iU -0EC,z> -0mm5\_ -0sfo}Z -0)|%6{ -0t'l~] -0[|v\H$ -0B(P|B -0.7gMQ -b1111 ,SVcw -07}oLq -0a~%H' -b1111 8K@uI -0B" +b1111 A" +0C" +0G" +b1111 J" +0L" +0M" +0P" #37000000 -117/]f -15Gki< -1jJ+ac -1V1=.M -1(v:Ix -1l=z|A -1hP6aI -1Vvn/E -1$\W(J -1QI!iU -1EC,z> -1mm5\_ -1sfo}Z -1)|%6{ -1t'l~] -1[|v" +1C" +1G" +1L" +1P" #38000000 -017/]f -05Gki< -0jJ+ac -0V1=.M -0(v:Ix -0l=z|A -0hP6aI -0Vvn/E -0$\W(J -0QI!iU -0EC,z> -0mm5\_ -0sfo}Z -0)|%6{ -0t'l~] -0[|v" +0C" +0G" +0L" +0P" diff --git a/crates/fayalite/tests/sim/expected/memories.vcd b/crates/fayalite/tests/sim/expected/memories.vcd index 7a54fbf..d8f5817 100644 --- a/crates/fayalite/tests/sim/expected/memories.vcd +++ b/crates/fayalite/tests/sim/expected/memories.vcd @@ -1,408 +1,408 @@ $timescale 1 ps $end $scope module memories $end $scope struct r $end -$var wire 4 z&0Qk addr $end -$var wire 1 o.T)# en $end -$var wire 1 :XNoK clk $end +$var wire 4 ! addr $end +$var wire 1 " en $end +$var wire 1 # clk $end $scope struct data $end -$var wire 8 Cq]A% \0 $end -$var wire 8 avKNj \1 $end +$var wire 8 $ \0 $end +$var wire 8 % \1 $end $upscope $end $upscope $end $scope struct w $end -$var wire 4 p \0 $end +$var reg 8 N \1 $end $upscope $end $upscope $end $scope struct \[6] $end $scope struct mem $end -$var reg 8 xpw5\ \0 $end -$var reg 8 dd$?K \1 $end +$var reg 8 ? \0 $end +$var reg 8 O \1 $end $upscope $end $upscope $end $scope struct \[7] $end $scope struct mem $end -$var reg 8 vH;}2 \0 $end -$var reg 8 ILB?4 \1 $end +$var reg 8 @ \0 $end +$var reg 8 P \1 $end $upscope $end $upscope $end $scope struct \[8] $end $scope struct mem $end -$var reg 8 /X4v> \0 $end -$var reg 8 &V*EE \1 $end +$var reg 8 A \0 $end +$var reg 8 Q \1 $end $upscope $end $upscope $end $scope struct \[9] $end $scope struct mem $end -$var reg 8 IczZe \0 $end -$var reg 8 unX>R \1 $end +$var reg 8 B \0 $end +$var reg 8 R \1 $end $upscope $end $upscope $end $scope struct \[10] $end $scope struct mem $end -$var reg 8 0hTyY \0 $end -$var reg 8 9K_w) \1 $end +$var reg 8 C \0 $end +$var reg 8 S \1 $end $upscope $end $upscope $end $scope struct \[11] $end $scope struct mem $end -$var reg 8 +C/Sz \0 $end -$var reg 8 }Y{:o \1 $end +$var reg 8 D \0 $end +$var reg 8 T \1 $end $upscope $end $upscope $end $scope struct \[12] $end $scope struct mem $end -$var reg 8 S6-5u \0 $end -$var reg 8 9q6)w \1 $end +$var reg 8 E \0 $end +$var reg 8 U \1 $end $upscope $end $upscope $end $scope struct \[13] $end $scope struct mem $end -$var reg 8 !c -b100011 &V*EE -b1 IczZe -b100011 unX>R -b1 0hTyY -b100011 9K_w) -b1 +C/Sz -b100011 }Y{:o -b1 S6-5u -b100011 9q6)w -b1 !c +b100011 N +b1 ? +b100011 O +b1 @ +b100011 P +b1 A +b100011 Q +b1 B +b100011 R +b1 C +b100011 S +b1 D +b100011 T +b1 E +b100011 U +b1 F +b100011 V +b1 G +b100011 W +b1 H +b100011 X +b0 ! +0" +0# +b0 $ +b0 % +b0 & +0' +0( +b0 ) +b0 * +0+ +0, +b0 - +0. +0/ +b0 0 +b0 1 +b0 2 +03 +04 +b0 5 +b0 6 +07 +08 $end #1000000 -1:XNoK -1QX!^| -1\o>8T -1DC/;" +1# +1( +1/ +14 #2000000 -1o.T)# -0:XNoK -b1 Cq]A% -b100011 avKNj -1#9)l8 -0QX!^| -b10000 G"IXQ -b100000 h\t:E -1FCuNz -1/Y7%J -1jy78F -0\o>8T -b1 \k#l -b100011 olx7O -1"7?3I -0DC/;" -b10000 0DrV' -b100000 wa!Cx -1u^b&R -1Ic\|v +1" +0# +b1 $ +b100011 % +1' +0( +b10000 ) +b100000 * +1+ +1, +1. +0/ +b1 0 +b100011 1 +13 +04 +b10000 5 +b100000 6 +17 +18 #3000000 -b10000 4d[cL -b100000 {qEUV -1:XNoK -b10000 Cq]A% -b100000 avKNj -1QX!^| -1\o>8T -b10000 \k#l -b100000 olx7O -1DC/;" +b10000 9 +b100000 I +1# +b10000 $ +b100000 % +1( +1/ +b10000 0 +b100000 1 +14 #4000000 -0:XNoK -0QX!^| -b110000 G"IXQ -b1000000 h\t:E -0FCuNz -0\o>8T -0DC/;" -b110000 0DrV' -b1000000 wa!Cx -0u^b&R +0# +0( +b110000 ) +b1000000 * +0+ +0/ +04 +b110000 5 +b1000000 6 +07 #5000000 -b10000 4d[cL -b1000000 {qEUV -1:XNoK -b1000000 avKNj -1QX!^| -1\o>8T -b1000000 olx7O -1DC/;" +b10000 9 +b1000000 I +1# +b1000000 % +1( +1/ +b1000000 1 +14 #6000000 -0:XNoK -0QX!^| -b1010000 G"IXQ -b1100000 h\t:E -1FCuNz -0/Y7%J -0\o>8T -0DC/;" -b1010000 0DrV' -b1100000 wa!Cx -1u^b&R -0Ic\|v +0# +0( +b1010000 ) +b1100000 * +1+ +0, +0/ +04 +b1010000 5 +b1100000 6 +17 +08 #7000000 -b1010000 4d[cL -b1000000 {qEUV -1:XNoK -b1010000 Cq]A% -1QX!^| -1\o>8T -b1010000 \k#l -1DC/;" +b1010000 9 +b1000000 I +1# +b1010000 $ +1( +1/ +b1010000 0 +14 #8000000 -0:XNoK -0QX!^| -b1110000 G"IXQ -b10000000 h\t:E -0FCuNz -0\o>8T -0DC/;" -b1110000 0DrV' -b10000000 wa!Cx -0u^b&R +0# +0( +b1110000 ) +b10000000 * +0+ +0/ +04 +b1110000 5 +b10000000 6 +07 #9000000 -1:XNoK -1QX!^| -1\o>8T -1DC/;" +1# +1( +1/ +14 #10000000 -0:XNoK -0#9)l8 -0QX!^| -b10010000 G"IXQ -b10100000 h\t:E -0\o>8T -0"7?3I -0DC/;" -b10010000 0DrV' -b10100000 wa!Cx +0# +0' +0( +b10010000 ) +b10100000 * +0/ +03 +04 +b10010000 5 +b10100000 6 #11000000 -1:XNoK -1QX!^| -1\o>8T -1DC/;" +1# +1( +1/ +14 #12000000 -0:XNoK -b1 p8T -b1 H,W!J -1"7?3I -0DC/;" -1u^b&R -1Ic\|v +0# +b1 & +1' +0( +1+ +1, +0/ +b1 2 +13 +04 +17 +18 #13000000 -b10010000 c`NPR -b10100000 vK:33 -1:XNoK -1QX!^| -1\o>8T -1DC/;" +b10010000 : +b10100000 J +1# +1( +1/ +14 #14000000 -0:XNoK -b10 p8T -b10 H,W!J -0DC/;" -b10110000 0DrV' -b11000000 wa!Cx +0# +b10 & +0( +b10110000 ) +b11000000 * +0/ +b10 2 +04 +b10110000 5 +b11000000 6 #15000000 -b10110000 ihYp_ -b11000000 QZb%P -1:XNoK -1QX!^| -1\o>8T -1DC/;" +b10110000 ; +b11000000 K +1# +1( +1/ +14 #16000000 -0:XNoK -0#9)l8 -0QX!^| -b11010000 G"IXQ -b11100000 h\t:E -0\o>8T -0"7?3I -0DC/;" -b11010000 0DrV' -b11100000 wa!Cx +0# +0' +0( +b11010000 ) +b11100000 * +0/ +03 +04 +b11010000 5 +b11100000 6 #17000000 -1:XNoK -1QX!^| -1\o>8T -1DC/;" +1# +1( +1/ +14 #18000000 -b1 z&0Qk -0:XNoK -b10010000 Cq]A% -b10100000 avKNj -0QX!^| -b1 ="2wN -0\o>8T -b10010000 \k#l -b10100000 olx7O -0DC/;" +b1 ! +0# +b10010000 $ +b10100000 % +0( +b1 - +0/ +b10010000 0 +b10100000 1 +04 #19000000 -1:XNoK -1QX!^| -1\o>8T -1DC/;" +1# +1( +1/ +14 #20000000 -b10 z&0Qk -0:XNoK -b10110000 Cq]A% -b11000000 avKNj -0QX!^| -b10 ="2wN -0\o>8T -b10110000 \k#l -b11000000 olx7O -0DC/;" +b10 ! +0# +b10110000 $ +b11000000 % +0( +b10 - +0/ +b10110000 0 +b11000000 1 +04 #21000000 -1:XNoK -1QX!^| -1\o>8T -1DC/;" +1# +1( +1/ +14 #22000000 -0:XNoK -0QX!^| -0\o>8T -0DC/;" +0# +0( +0/ +04 diff --git a/crates/fayalite/tests/sim/expected/memories2.vcd b/crates/fayalite/tests/sim/expected/memories2.vcd index 182029e..0ac20f1 100644 --- a/crates/fayalite/tests/sim/expected/memories2.vcd +++ b/crates/fayalite/tests/sim/expected/memories2.vcd @@ -1,363 +1,363 @@ $timescale 1 ps $end $scope module memories2 $end $scope struct rw $end -$var wire 3 xkkG> addr $end -$var wire 1 HoA{1 en $end -$var wire 1 C*2BQ clk $end -$var wire 2 ueF!x rdata $end -$var wire 1 m\l/p wmode $end -$var wire 2 WmjEh wdata $end -$var wire 1 +3E@H wmask $end +$var wire 3 ! addr $end +$var wire 1 " en $end +$var wire 1 # clk $end +$var wire 2 $ rdata $end +$var wire 1 % wmode $end +$var wire 2 & wdata $end +$var wire 1 ' wmask $end $upscope $end $scope struct mem $end $scope struct contents $end $scope struct \[0] $end $scope struct mem $end -$var string 1 ujd9u \$tag $end -$var reg 1 *5lV# HdlSome $end +$var string 1 1 \$tag $end +$var reg 1 6 HdlSome $end $upscope $end $upscope $end $scope struct \[1] $end $scope struct mem $end -$var string 1 *qL|n \$tag $end -$var reg 1 ^/FDC HdlSome $end +$var string 1 2 \$tag $end +$var reg 1 7 HdlSome $end $upscope $end $upscope $end $scope struct \[2] $end $scope struct mem $end -$var string 1 r*7|@ \$tag $end -$var reg 1 YMY"3 HdlSome $end +$var string 1 3 \$tag $end +$var reg 1 8 HdlSome $end $upscope $end $upscope $end $scope struct \[3] $end $scope struct mem $end -$var string 1 jj/6F \$tag $end -$var reg 1 S+Uy} HdlSome $end +$var string 1 4 \$tag $end +$var reg 1 9 HdlSome $end $upscope $end $upscope $end $scope struct \[4] $end $scope struct mem $end -$var string 1 H72IP \$tag $end -$var reg 1 vH{({ HdlSome $end +$var string 1 5 \$tag $end +$var reg 1 : HdlSome $end $upscope $end $upscope $end $upscope $end $scope struct rw0 $end -$var wire 3 uabMI addr $end -$var wire 1 LEn[l en $end -$var wire 1 OpH)U clk $end +$var wire 3 ( addr $end +$var wire 1 ) en $end +$var wire 1 * clk $end $scope struct rdata $end -$var string 1 [}rcZ \$tag $end -$var wire 1 5f=Y~ HdlSome $end +$var string 1 + \$tag $end +$var wire 1 , HdlSome $end $upscope $end -$var wire 1 6c_9_ wmode $end +$var wire 1 - wmode $end $scope struct wdata $end -$var string 1 $hfRN \$tag $end -$var wire 1 rop,b HdlSome $end +$var string 1 . \$tag $end +$var wire 1 / HdlSome $end $upscope $end -$var wire 1 Ly=US wmask $end +$var wire 1 0 wmask $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -sHdlSome\x20(1) ujd9u -1*5lV# -sHdlSome\x20(1) *qL|n -1^/FDC -sHdlSome\x20(1) r*7|@ -1YMY"3 -sHdlSome\x20(1) jj/6F -1S+Uy} -sHdlSome\x20(1) H72IP -1vH{({ -b0 xkkG> -0HoA{1 -0C*2BQ -b0 ueF!x -0m\l/p -b0 WmjEh -0+3E@H -b0 uabMI -0LEn[l -0OpH)U -sHdlNone\x20(0) [}rcZ -05f=Y~ -06c_9_ -sHdlNone\x20(0) $hfRN -0rop,b -0Ly=US +sHdlSome\x20(1) 1 +16 +sHdlSome\x20(1) 2 +17 +sHdlSome\x20(1) 3 +18 +sHdlSome\x20(1) 4 +19 +sHdlSome\x20(1) 5 +1: +b0 ! +0" +0# +b0 $ +0% +b0 & +0' +b0 ( +0) +0* +sHdlNone\x20(0) + +0, +0- +sHdlNone\x20(0) . +0/ +00 $end #250000 -1C*2BQ -1OpH)U +1# +1* #500000 #750000 -0C*2BQ -0OpH)U +0# +0* #1000000 -1HoA{1 -1LEn[l +1" +1) #1250000 -1C*2BQ -b11 ueF!x -1OpH)U -sHdlSome\x20(1) [}rcZ -15f=Y~ +1# +b11 $ +1* +sHdlSome\x20(1) + +1, #1500000 #1750000 -0C*2BQ -0OpH)U +0# +0* #2000000 -0HoA{1 -0LEn[l +0" +0) #2250000 -1C*2BQ -b0 ueF!x -1OpH)U -sHdlNone\x20(0) [}rcZ -05f=Y~ +1# +b0 $ +1* +sHdlNone\x20(0) + +0, #2500000 #2750000 -0C*2BQ -0OpH)U +0# +0* #3000000 -1HoA{1 -1m\l/p -1+3E@H -1LEn[l -16c_9_ -1Ly=US +1" +1% +1' +1) +1- +10 #3250000 -sHdlNone\x20(0) ujd9u -0*5lV# -1C*2BQ -1OpH)U +sHdlNone\x20(0) 1 +06 +1# +1* #3500000 #3750000 -0C*2BQ -0OpH)U +0# +0* #4000000 -0m\l/p -0+3E@H -06c_9_ -0Ly=US +0% +0' +0- +00 #4250000 -1C*2BQ -1OpH)U +1# +1* #4500000 #4750000 -0C*2BQ -0OpH)U +0# +0* #5000000 -1m\l/p -b11 WmjEh -16c_9_ -sHdlSome\x20(1) $hfRN -1rop,b +1% +b11 & +1- +sHdlSome\x20(1) . +1/ #5250000 -1C*2BQ -1OpH)U +1# +1* #5500000 #5750000 -0C*2BQ -0OpH)U +0# +0* #6000000 -b1 xkkG> -b1 WmjEh -1+3E@H -b1 uabMI -0rop,b -1Ly=US +b1 ! +b1 & +1' +b1 ( +0/ +10 #6250000 -sHdlSome\x20(1) *qL|n -0^/FDC -1C*2BQ -1OpH)U +sHdlSome\x20(1) 2 +07 +1# +1* #6500000 #6750000 -0C*2BQ -0OpH)U +0# +0* #7000000 -b10 xkkG> -b10 WmjEh -b10 uabMI -sHdlNone\x20(0) $hfRN +b10 ! +b10 & +b10 ( +sHdlNone\x20(0) . #7250000 -sHdlNone\x20(0) r*7|@ -0YMY"3 -1C*2BQ -1OpH)U +sHdlNone\x20(0) 3 +08 +1# +1* #7500000 #7750000 -0C*2BQ -0OpH)U +0# +0* #8000000 -b11 xkkG> -b11 WmjEh -b11 uabMI -sHdlSome\x20(1) $hfRN -1rop,b +b11 ! +b11 & +b11 ( +sHdlSome\x20(1) . +1/ #8250000 -sHdlSome\x20(1) jj/6F -1S+Uy} -1C*2BQ -1OpH)U +sHdlSome\x20(1) 4 +19 +1# +1* #8500000 #8750000 -0C*2BQ -0OpH)U +0# +0* #9000000 -b100 xkkG> -b10 WmjEh -b100 uabMI -sHdlNone\x20(0) $hfRN -0rop,b +b100 ! +b10 & +b100 ( +sHdlNone\x20(0) . +0/ #9250000 -sHdlNone\x20(0) H72IP -0vH{({ -1C*2BQ -1OpH)U +sHdlNone\x20(0) 5 +0: +1# +1* #9500000 #9750000 -0C*2BQ -0OpH)U +0# +0* #10000000 -b101 xkkG> -b1 WmjEh -b101 uabMI -sHdlSome\x20(1) $hfRN +b101 ! +b1 & +b101 ( +sHdlSome\x20(1) . #10250000 -1C*2BQ -1OpH)U +1# +1* #10500000 #10750000 -0C*2BQ -0OpH)U +0# +0* #11000000 -b110 xkkG> -b110 uabMI +b110 ! +b110 ( #11250000 -1C*2BQ -1OpH)U +1# +1* #11500000 #11750000 -0C*2BQ -0OpH)U +0# +0* #12000000 -b111 xkkG> -b111 uabMI +b111 ! +b111 ( #12250000 -1C*2BQ -1OpH)U +1# +1* #12500000 #12750000 -0C*2BQ -0OpH)U +0# +0* #13000000 -0m\l/p -b0 WmjEh -0+3E@H -06c_9_ -sHdlNone\x20(0) $hfRN -0Ly=US +0% +b0 & +0' +0- +sHdlNone\x20(0) . +00 #13250000 -1C*2BQ -1OpH)U +1# +1* #13500000 #13750000 -0C*2BQ -0OpH)U +0# +0* #14000000 -b110 xkkG> -b110 uabMI +b110 ! +b110 ( #14250000 -1C*2BQ -1OpH)U +1# +1* #14500000 #14750000 -0C*2BQ -0OpH)U +0# +0* #15000000 -b101 xkkG> -b101 uabMI +b101 ! +b101 ( #15250000 -1C*2BQ -1OpH)U +1# +1* #15500000 #15750000 -0C*2BQ -0OpH)U +0# +0* #16000000 -b100 xkkG> -b100 uabMI +b100 ! +b100 ( #16250000 -1C*2BQ -1OpH)U +1# +1* #16500000 #16750000 -0C*2BQ -0OpH)U +0# +0* #17000000 -b11 xkkG> -b11 uabMI +b11 ! +b11 ( #17250000 -1C*2BQ -b11 ueF!x -1OpH)U -sHdlSome\x20(1) [}rcZ -15f=Y~ +1# +b11 $ +1* +sHdlSome\x20(1) + +1, #17500000 #17750000 -0C*2BQ -0OpH)U +0# +0* #18000000 -b10 xkkG> -b10 uabMI +b10 ! +b10 ( #18250000 -1C*2BQ -b0 ueF!x -1OpH)U -sHdlNone\x20(0) [}rcZ -05f=Y~ +1# +b0 $ +1* +sHdlNone\x20(0) + +0, #18500000 #18750000 -0C*2BQ -0OpH)U +0# +0* #19000000 -b0 xkkG> -b0 uabMI +b0 ! +b0 ( #19250000 -1C*2BQ -1OpH)U +1# +1* #19500000 #19750000 -0C*2BQ -0OpH)U +0# +0* #20000000 -b1 xkkG> -b1 uabMI +b1 ! +b1 ( #20250000 -1C*2BQ -b1 ueF!x -1OpH)U -sHdlSome\x20(1) [}rcZ +1# +b1 $ +1* +sHdlSome\x20(1) + #20500000 #20750000 -0C*2BQ -0OpH)U +0# +0* #21000000 -b0 xkkG> -0HoA{1 -b0 uabMI -0LEn[l +b0 ! +0" +b0 ( +0) #21250000 -1C*2BQ -b0 ueF!x -1OpH)U -sHdlNone\x20(0) [}rcZ +1# +b0 $ +1* +sHdlNone\x20(0) + #21500000 #21750000 -0C*2BQ -0OpH)U +0# +0* #22000000 diff --git a/crates/fayalite/tests/sim/expected/memories3.vcd b/crates/fayalite/tests/sim/expected/memories3.vcd index 9495de9..32ee75e 100644 --- a/crates/fayalite/tests/sim/expected/memories3.vcd +++ b/crates/fayalite/tests/sim/expected/memories3.vcd @@ -1,836 +1,836 @@ $timescale 1 ps $end $scope module memories3 $end $scope struct r $end -$var wire 3 }Q=~y addr $end -$var wire 1 ,Ca!' en $end -$var wire 1 dJF\@ clk $end +$var wire 3 ! addr $end +$var wire 1 " en $end +$var wire 1 # clk $end $scope struct data $end -$var wire 8 "w$'Q \[0] $end -$var wire 8 mIo&U \[1] $end -$var wire 8 LJ\m% \[2] $end -$var wire 8 `Zp>N \[3] $end -$var wire 8 YR.PG \[4] $end -$var wire 8 BZ&)B \[5] $end -$var wire 8 _$[8D \[6] $end -$var wire 8 tc)n] \[7] $end +$var wire 8 $ \[0] $end +$var wire 8 % \[1] $end +$var wire 8 & \[2] $end +$var wire 8 ' \[3] $end +$var wire 8 ( \[4] $end +$var wire 8 ) \[5] $end +$var wire 8 * \[6] $end +$var wire 8 + \[7] $end $upscope $end $upscope $end $scope struct w $end -$var wire 3 bs-Rg addr $end -$var wire 1 *T~2b en $end -$var wire 1 }[YPW clk $end +$var wire 3 , addr $end +$var wire 1 - en $end +$var wire 1 . clk $end $scope struct data $end -$var wire 8 6,aYz \[0] $end -$var wire 8 Bq5kY \[1] $end -$var wire 8 :lN4y \[2] $end -$var wire 8 +9uC] \[3] $end -$var wire 8 /EG3; \[4] $end -$var wire 8 >=e$j \[5] $end -$var wire 8 >wz^~ \[6] $end -$var wire 8 CYt2z \[7] $end +$var wire 8 / \[0] $end +$var wire 8 0 \[1] $end +$var wire 8 1 \[2] $end +$var wire 8 2 \[3] $end +$var wire 8 3 \[4] $end +$var wire 8 4 \[5] $end +$var wire 8 5 \[6] $end +$var wire 8 6 \[7] $end $upscope $end $scope struct mask $end -$var wire 1 :.XL} \[0] $end -$var wire 1 0b%VN \[1] $end -$var wire 1 *w)7y \[2] $end -$var wire 1 1dg() \[3] $end -$var wire 1 s% \[7] $end $upscope $end $upscope $end $scope struct mem $end $scope struct contents $end $scope struct \[0] $end $scope struct mem $end -$var reg 8 bS^uZ \[0] $end -$var reg 8 +MZoR \[1] $end -$var reg 8 buliE \[2] $end -$var reg 8 X1my. \[3] $end -$var reg 8 pmEg% \[4] $end -$var reg 8 J;&2w \[5] $end -$var reg 8 #'ZC$ \[6] $end -$var reg 8 zdBci \[7] $end +$var reg 8 ] \[0] $end +$var reg 8 e \[1] $end +$var reg 8 m \[2] $end +$var reg 8 u \[3] $end +$var reg 8 } \[4] $end +$var reg 8 '" \[5] $end +$var reg 8 /" \[6] $end +$var reg 8 7" \[7] $end $upscope $end $upscope $end $scope struct \[1] $end $scope struct mem $end -$var reg 8 !=66X \[0] $end -$var reg 8 -#Dd6 \[1] $end -$var reg 8 l}7)5 \[2] $end -$var reg 8 8,]`a \[3] $end -$var reg 8 yES{c \[4] $end -$var reg 8 ;J^L" \[5] $end -$var reg 8 qUI{d \[6] $end -$var reg 8 %U;af \[7] $end +$var reg 8 ^ \[0] $end +$var reg 8 f \[1] $end +$var reg 8 n \[2] $end +$var reg 8 v \[3] $end +$var reg 8 ~ \[4] $end +$var reg 8 (" \[5] $end +$var reg 8 0" \[6] $end +$var reg 8 8" \[7] $end $upscope $end $upscope $end $scope struct \[2] $end $scope struct mem $end -$var reg 8 ~\!qw \[0] $end -$var reg 8 \K4+l \[1] $end -$var reg 8 V7%F. \[2] $end -$var reg 8 R@/Mx \[3] $end -$var reg 8 ,VoRT \[4] $end -$var reg 8 `L=0w \[5] $end -$var reg 8 kP[@C \[6] $end -$var reg 8 2^Xew \[7] $end +$var reg 8 _ \[0] $end +$var reg 8 g \[1] $end +$var reg 8 o \[2] $end +$var reg 8 w \[3] $end +$var reg 8 !" \[4] $end +$var reg 8 )" \[5] $end +$var reg 8 1" \[6] $end +$var reg 8 9" \[7] $end $upscope $end $upscope $end $scope struct \[3] $end $scope struct mem $end -$var reg 8 O&Qy} \[0] $end -$var reg 8 YRUF" \[1] $end -$var reg 8 c_Q \[0] $end -$var reg 8 B$aO# \[1] $end -$var reg 8 .=-:e \[2] $end -$var reg 8 WqHtO \[3] $end -$var reg 8 \P/B8 \[4] $end -$var reg 8 ~f|@~ \[5] $end -$var reg 8 [xw38 \[6] $end -$var reg 8 ,mMiC \[7] $end +$var reg 8 b \[0] $end +$var reg 8 j \[1] $end +$var reg 8 r \[2] $end +$var reg 8 z \[3] $end +$var reg 8 $" \[4] $end +$var reg 8 ," \[5] $end +$var reg 8 4" \[6] $end +$var reg 8 <" \[7] $end $upscope $end $upscope $end $scope struct \[6] $end $scope struct mem $end -$var reg 8 T){Kr \[0] $end -$var reg 8 JCt-5 \[1] $end -$var reg 8 JJ`q% \[2] $end -$var reg 8 &8m;f \[3] $end -$var reg 8 .N&;O \[4] $end -$var reg 8 9CPW} \[5] $end -$var reg 8 ~cUnd \[6] $end -$var reg 8 S6,C. \[7] $end +$var reg 8 c \[0] $end +$var reg 8 k \[1] $end +$var reg 8 s \[2] $end +$var reg 8 { \[3] $end +$var reg 8 %" \[4] $end +$var reg 8 -" \[5] $end +$var reg 8 5" \[6] $end +$var reg 8 =" \[7] $end $upscope $end $upscope $end $scope struct \[7] $end $scope struct mem $end -$var reg 8 h,t%t \[0] $end -$var reg 8 M.'tT \[1] $end -$var reg 8 WH^lq \[2] $end -$var reg 8 wk@1l \[3] $end -$var reg 8 XPVW/ \[4] $end -$var reg 8 8i**= \[5] $end -$var reg 8 T7yLi \[6] $end -$var reg 8 xPnYC \[7] $end +$var reg 8 d \[0] $end +$var reg 8 l \[1] $end +$var reg 8 t \[2] $end +$var reg 8 | \[3] $end +$var reg 8 &" \[4] $end +$var reg 8 ." \[5] $end +$var reg 8 6" \[6] $end +$var reg 8 >" \[7] $end $upscope $end $upscope $end $upscope $end $scope struct r0 $end -$var wire 3 ]7,pz addr $end -$var wire 1 ]ky*D en $end -$var wire 1 pK0f; clk $end +$var wire 3 ? addr $end +$var wire 1 @ en $end +$var wire 1 A clk $end $scope struct data $end -$var wire 8 Wz+1. \[0] $end -$var wire 8 q-WOU \[1] $end -$var wire 8 ,iWd9 \[2] $end -$var wire 8 P,^c) \[3] $end -$var wire 8 s?0AD \[4] $end -$var wire 8 {,&!. \[5] $end -$var wire 8 0~wS+ \[6] $end -$var wire 8 ZqG9i \[7] $end +$var wire 8 B \[0] $end +$var wire 8 C \[1] $end +$var wire 8 D \[2] $end +$var wire 8 E \[3] $end +$var wire 8 F \[4] $end +$var wire 8 G \[5] $end +$var wire 8 H \[6] $end +$var wire 8 I \[7] $end $upscope $end $upscope $end $scope struct w1 $end -$var wire 3 iuiB`l[ \[6] $end -$var wire 8 481V} \[7] $end +$var wire 8 M \[0] $end +$var wire 8 N \[1] $end +$var wire 8 O \[2] $end +$var wire 8 P \[3] $end +$var wire 8 Q \[4] $end +$var wire 8 R \[5] $end +$var wire 8 S \[6] $end +$var wire 8 T \[7] $end $upscope $end $scope struct mask $end -$var wire 1 E`@Pc \[0] $end -$var wire 1 Hm9Lt \[1] $end -$var wire 1 D@ZT~ \[2] $end -$var wire 1 %ZXkA \[3] $end -$var wire 1 dO-sf \[4] $end -$var wire 1 uE-x9 \[5] $end -$var wire 1 [w<$[ \[6] $end -$var wire 1 *7bb6 \[7] $end +$var wire 1 U \[0] $end +$var wire 1 V \[1] $end +$var wire 1 W \[2] $end +$var wire 1 X \[3] $end +$var wire 1 Y \[4] $end +$var wire 1 Z \[5] $end +$var wire 1 [ \[6] $end +$var wire 1 \ \[7] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -b0 bS^uZ -b0 +MZoR -b0 buliE -b0 X1my. -b0 pmEg% -b0 J;&2w -b0 #'ZC$ -b0 zdBci -b0 !=66X -b0 -#Dd6 -b0 l}7)5 -b0 8,]`a -b0 yES{c -b0 ;J^L" -b0 qUI{d -b0 %U;af -b0 ~\!qw -b0 \K4+l -b0 V7%F. -b0 R@/Mx -b0 ,VoRT -b0 `L=0w -b0 kP[@C -b0 2^Xew -b0 O&Qy} -b0 YRUF" -b0 c_Q -b0 B$aO# -b0 .=-:e -b0 WqHtO -b0 \P/B8 -b0 ~f|@~ -b0 [xw38 -b0 ,mMiC -b0 T){Kr -b0 JCt-5 -b0 JJ`q% -b0 &8m;f -b0 .N&;O -b0 9CPW} -b0 ~cUnd -b0 S6,C. -b0 h,t%t -b0 M.'tT -b0 WH^lq -b0 wk@1l -b0 XPVW/ -b0 8i**= -b0 T7yLi -b0 xPnYC -b0 }Q=~y -0,Ca!' -0dJF\@ -b0 "w$'Q -b0 mIo&U -b0 LJ\m% -b0 `Zp>N -b0 YR.PG -b0 BZ&)B -b0 _$[8D -b0 tc)n] -b0 bs-Rg -1*T~2b -0}[YPW -b10010 6,aYz -b110100 Bq5kY -b1010110 :lN4y -b1111000 +9uC] -b10011010 /EG3; -b10111100 >=e$j -b11011110 >wz^~ -b11110000 CYt2z -0:.XL} -10b%VN -0*w)7y -11dg() -1s%B`l[ -b11110000 481V} -0E`@Pc -1Hm9Lt -0D@ZT~ -1%ZXkA -1dO-sf -0uE-x9 -0[w<$[ -1*7bb6 +b0 ] +b0 e +b0 m +b0 u +b0 } +b0 '" +b0 /" +b0 7" +b0 ^ +b0 f +b0 n +b0 v +b0 ~ +b0 (" +b0 0" +b0 8" +b0 _ +b0 g +b0 o +b0 w +b0 !" +b0 )" +b0 1" +b0 9" +b0 ` +b0 h +b0 p +b0 x +b0 "" +b0 *" +b0 2" +b0 :" +b0 a +b0 i +b0 q +b0 y +b0 #" +b0 +" +b0 3" +b0 ;" +b0 b +b0 j +b0 r +b0 z +b0 $" +b0 ," +b0 4" +b0 <" +b0 c +b0 k +b0 s +b0 { +b0 %" +b0 -" +b0 5" +b0 =" +b0 d +b0 l +b0 t +b0 | +b0 &" +b0 ." +b0 6" +b0 >" +b0 ! +0" +0# +b0 $ +b0 % +b0 & +b0 ' +b0 ( +b0 ) +b0 * +b0 + +b0 , +1- +0. +b10010 / +b110100 0 +b1010110 1 +b1111000 2 +b10011010 3 +b10111100 4 +b11011110 5 +b11110000 6 +07 +18 +09 +1: +1; +0< +0= +1> +b0 ? +0@ +0A +b0 B +b0 C +b0 D +b0 E +b0 F +b0 G +b0 H +b0 I +b0 J +1K +0L +b10010 M +b110100 N +b1010110 O +b1111000 P +b10011010 Q +b10111100 R +b11011110 S +b11110000 T +0U +1V +0W +1X +1Y +0Z +0[ +1\ $end #250000 -1dJF\@ -1}[YPW -1pK0f; -1=[Eug +1# +1. +1A +1L #500000 #750000 -0dJF\@ -0}[YPW -0pK0f; -0=[Eug +0# +0. +0A +0L #1000000 -1,Ca!' -b1 bs-Rg -0*T~2b -b0 6,aYz -b0 Bq5kY -b0 :lN4y -b0 +9uC] -b0 /EG3; -b0 >=e$j -b0 >wz^~ -b0 CYt2z -00b%VN -01dg() -0s%B`l[ -b0 481V} -0Hm9Lt -0%ZXkA -0dO-sf -0*7bb6 +1" +b1 , +0- +b0 / +b0 0 +b0 1 +b0 2 +b0 3 +b0 4 +b0 5 +b0 6 +08 +0: +0; +0> +1@ +b1 J +0K +b0 M +b0 N +b0 O +b0 P +b0 Q +b0 R +b0 S +b0 T +0V +0X +0Y +0\ #1250000 -b0 bS^uZ -b110100 +MZoR -b0 buliE -b1111000 X1my. -b10011010 pmEg% -b0 J;&2w -b0 #'ZC$ -b11110000 zdBci -1dJF\@ -1}[YPW -1pK0f; -1=[Eug +b0 ] +b110100 e +b0 m +b1111000 u +b10011010 } +b0 '" +b0 /" +b11110000 7" +1# +1. +1A +1L #1500000 #1750000 -0dJF\@ -0}[YPW -0pK0f; -0=[Eug +0# +0. +0A +0L #2000000 #2250000 -1dJF\@ -1}[YPW -1pK0f; -1=[Eug +1# +1. +1A +1L #2500000 #2750000 -0dJF\@ -0}[YPW -0pK0f; -0=[Eug +0# +0. +0A +0L #3000000 -b0 bs-Rg -1*T~2b -b11111110 6,aYz -b11011100 Bq5kY -b10111010 :lN4y -b10011000 +9uC] -b1110110 /EG3; -b1010100 >=e$j -b110010 >wz^~ -b10000 CYt2z -1:.XL} -10b%VN -1*w)7y -11dg() -1s%B`l[ -b10000 481V} -1E`@Pc -1Hm9Lt -1D@ZT~ -1%ZXkA -1dO-sf -1uE-x9 -1[w<$[ -1*7bb6 +b0 , +1- +b11111110 / +b11011100 0 +b10111010 1 +b10011000 2 +b1110110 3 +b1010100 4 +b110010 5 +b10000 6 +17 +18 +19 +1: +1; +1< +1= +1> +b0 J +1K +b11111110 M +b11011100 N +b10111010 O +b10011000 P +b1110110 Q +b1010100 R +b110010 S +b10000 T +1U +1V +1W +1X +1Y +1Z +1[ +1\ #3250000 -1dJF\@ -b110100 mIo&U -b1111000 `Zp>N -b10011010 YR.PG -b11110000 tc)n] -1}[YPW -1pK0f; -b110100 q-WOU -b1111000 P,^c) -b10011010 s?0AD -b11110000 ZqG9i -1=[Eug +1# +b110100 % +b1111000 ' +b10011010 ( +b11110000 + +1. +1A +b110100 C +b1111000 E +b10011010 F +b11110000 I +1L #3500000 #3750000 -0dJF\@ -0}[YPW -0pK0f; -0=[Eug +0# +0. +0A +0L #4000000 #4250000 -b11111110 bS^uZ -b11011100 +MZoR -b10111010 buliE -b10011000 X1my. -b1110110 pmEg% -b1010100 J;&2w -b110010 #'ZC$ -b10000 zdBci -1dJF\@ -1}[YPW -1pK0f; -1=[Eug +b11111110 ] +b11011100 e +b10111010 m +b10011000 u +b1110110 } +b1010100 '" +b110010 /" +b10000 7" +1# +1. +1A +1L #4500000 #4750000 -0dJF\@ -0}[YPW -0pK0f; -0=[Eug +0# +0. +0A +0L #5000000 #5250000 -b11111110 bS^uZ -b11011100 +MZoR -b10111010 buliE -b10011000 X1my. -b1110110 pmEg% -b1010100 J;&2w -b110010 #'ZC$ -b10000 zdBci -1dJF\@ -1}[YPW -1pK0f; -1=[Eug +b11111110 ] +b11011100 e +b10111010 m +b10011000 u +b1110110 } +b1010100 '" +b110010 /" +b10000 7" +1# +1. +1A +1L #5500000 #5750000 -0dJF\@ -0}[YPW -0pK0f; -0=[Eug +0# +0. +0A +0L #6000000 -0,Ca!' -b1 bs-Rg -b10011 6,aYz -b1010111 Bq5kY -b10011011 :lN4y -b11011111 +9uC] -b10 /EG3; -b1000110 >=e$j -b10001010 >wz^~ -b11001110 CYt2z -0]ky*D -b1 iuiB`l[ -b11001110 481V} +0" +b1 , +b10011 / +b1010111 0 +b10011011 1 +b11011111 2 +b10 3 +b1000110 4 +b10001010 5 +b11001110 6 +0@ +b1 J +b10011 M +b1010111 N +b10011011 O +b11011111 P +b10 Q +b1000110 R +b10001010 S +b11001110 T #6250000 -b11111110 bS^uZ -b11011100 +MZoR -b10111010 buliE -b10011000 X1my. -b1110110 pmEg% -b1010100 J;&2w -b110010 #'ZC$ -b10000 zdBci -1dJF\@ -b11111110 "w$'Q -b11011100 mIo&U -b10111010 LJ\m% -b10011000 `Zp>N -b1110110 YR.PG -b1010100 BZ&)B -b110010 _$[8D -b10000 tc)n] -1}[YPW -1pK0f; -b11111110 Wz+1. -b11011100 q-WOU -b10111010 ,iWd9 -b10011000 P,^c) -b1110110 s?0AD -b1010100 {,&!. -b110010 0~wS+ -b10000 ZqG9i -1=[Eug +b11111110 ] +b11011100 e +b10111010 m +b10011000 u +b1110110 } +b1010100 '" +b110010 /" +b10000 7" +1# +b11111110 $ +b11011100 % +b10111010 & +b10011000 ' +b1110110 ( +b1010100 ) +b110010 * +b10000 + +1. +1A +b11111110 B +b11011100 C +b10111010 D +b10011000 E +b1110110 F +b1010100 G +b110010 H +b10000 I +1L #6500000 #6750000 -0dJF\@ -0}[YPW -0pK0f; -0=[Eug +0# +0. +0A +0L #7000000 -b10 bs-Rg -b1110100 6,aYz -b1100101 Bq5kY -b1110011 :lN4y -b1110100 +9uC] -b1101001 /EG3; -b1101110 >=e$j -b1100111 >wz^~ -b100001 CYt2z -b10 iuiB`l[ -b100001 481V} +b10 , +b1110100 / +b1100101 0 +b1110011 1 +b1110100 2 +b1101001 3 +b1101110 4 +b1100111 5 +b100001 6 +b10 J +b1110100 M +b1100101 N +b1110011 O +b1110100 P +b1101001 Q +b1101110 R +b1100111 S +b100001 T #7250000 -b10011 !=66X -b1010111 -#Dd6 -b10011011 l}7)5 -b11011111 8,]`a -b10 yES{c -b1000110 ;J^L" -b10001010 qUI{d -b11001110 %U;af -1dJF\@ -b0 "w$'Q -b0 mIo&U -b0 LJ\m% -b0 `Zp>N -b0 YR.PG -b0 BZ&)B -b0 _$[8D -b0 tc)n] -1}[YPW -1pK0f; -b0 Wz+1. -b0 q-WOU -b0 ,iWd9 -b0 P,^c) -b0 s?0AD -b0 {,&!. -b0 0~wS+ -b0 ZqG9i -1=[Eug +b10011 ^ +b1010111 f +b10011011 n +b11011111 v +b10 ~ +b1000110 (" +b10001010 0" +b11001110 8" +1# +b0 $ +b0 % +b0 & +b0 ' +b0 ( +b0 ) +b0 * +b0 + +1. +1A +b0 B +b0 C +b0 D +b0 E +b0 F +b0 G +b0 H +b0 I +1L #7500000 #7750000 -0dJF\@ -0}[YPW -0pK0f; -0=[Eug +0# +0. +0A +0L #8000000 -b11 bs-Rg -b1101101 6,aYz -b1101111 Bq5kY -b1110010 :lN4y -b1100101 +9uC] -b100000 /EG3; -b1110100 >=e$j -b1110011 >wz^~ -b1110100 CYt2z -b11 iuiB`l[ -b1110100 481V} +b11 , +b1101101 / +b1101111 0 +b1110010 1 +b1100101 2 +b100000 3 +b1110100 4 +b1110011 5 +b1110100 6 +b11 J +b1101101 M +b1101111 N +b1110010 O +b1100101 P +b100000 Q +b1110100 R +b1110011 S +b1110100 T #8250000 -b1110100 ~\!qw -b1100101 \K4+l -b1110011 V7%F. -b1110100 R@/Mx -b1101001 ,VoRT -b1101110 `L=0w -b1100111 kP[@C -b100001 2^Xew -1dJF\@ -1}[YPW -1pK0f; -1=[Eug +b1110100 _ +b1100101 g +b1110011 o +b1110100 w +b1101001 !" +b1101110 )" +b1100111 1" +b100001 9" +1# +1. +1A +1L #8500000 #8750000 -0dJF\@ -0}[YPW -0pK0f; -0=[Eug +0# +0. +0A +0L #9000000 -1,Ca!' -b0 bs-Rg -0*T~2b -b0 6,aYz -b0 Bq5kY -b0 :lN4y -b0 +9uC] -b0 /EG3; -b0 >=e$j -b0 >wz^~ -b0 CYt2z -0:.XL} -00b%VN -0*w)7y -01dg() -0s%B`l[ -b0 481V} -0E`@Pc -0Hm9Lt -0D@ZT~ -0%ZXkA -0dO-sf -0uE-x9 -0[w<$[ -0*7bb6 +1" +b0 , +0- +b0 / +b0 0 +b0 1 +b0 2 +b0 3 +b0 4 +b0 5 +b0 6 +07 +08 +09 +0: +0; +0< +0= +0> +1@ +b0 J +0K +b0 M +b0 N +b0 O +b0 P +b0 Q +b0 R +b0 S +b0 T +0U +0V +0W +0X +0Y +0Z +0[ +0\ #9250000 -b1101101 O&Qy} -b1101111 YRUF" -b1110010 N -b1110110 YR.PG -b1010100 BZ&)B -b110010 _$[8D -b10000 tc)n] -1}[YPW -1pK0f; -b11111110 Wz+1. -b11011100 q-WOU -b10111010 ,iWd9 -b10011000 P,^c) -b1110110 s?0AD -b1010100 {,&!. -b110010 0~wS+ -b10000 ZqG9i -1=[Eug +1# +b11111110 $ +b11011100 % +b10111010 & +b10011000 ' +b1110110 ( +b1010100 ) +b110010 * +b10000 + +1. +1A +b11111110 B +b11011100 C +b10111010 D +b10011000 E +b1110110 F +b1010100 G +b110010 H +b10000 I +1L #10500000 #10750000 -0dJF\@ -0}[YPW -0pK0f; -0=[Eug +0# +0. +0A +0L #11000000 -b10 }Q=~y -b10 ]7,pz +b10 ! +b10 ? #11250000 -1dJF\@ -b10011 "w$'Q -b1010111 mIo&U -b10011011 LJ\m% -b11011111 `Zp>N -b10 YR.PG -b1000110 BZ&)B -b10001010 _$[8D -b11001110 tc)n] -1}[YPW -1pK0f; -b10011 Wz+1. -b1010111 q-WOU -b10011011 ,iWd9 -b11011111 P,^c) -b10 s?0AD -b1000110 {,&!. -b10001010 0~wS+ -b11001110 ZqG9i -1=[Eug +1# +b10011 $ +b1010111 % +b10011011 & +b11011111 ' +b10 ( +b1000110 ) +b10001010 * +b11001110 + +1. +1A +b10011 B +b1010111 C +b10011011 D +b11011111 E +b10 F +b1000110 G +b10001010 H +b11001110 I +1L #11500000 #11750000 -0dJF\@ -0}[YPW -0pK0f; -0=[Eug +0# +0. +0A +0L #12000000 -b11 }Q=~y -b11 ]7,pz +b11 ! +b11 ? #12250000 -1dJF\@ -b1110100 "w$'Q -b1100101 mIo&U -b1110011 LJ\m% -b1110100 `Zp>N -b1101001 YR.PG -b1101110 BZ&)B -b1100111 _$[8D -b100001 tc)n] -1}[YPW -1pK0f; -b1110100 Wz+1. -b1100101 q-WOU -b1110011 ,iWd9 -b1110100 P,^c) -b1101001 s?0AD -b1101110 {,&!. -b1100111 0~wS+ -b100001 ZqG9i -1=[Eug +1# +b1110100 $ +b1100101 % +b1110011 & +b1110100 ' +b1101001 ( +b1101110 ) +b1100111 * +b100001 + +1. +1A +b1110100 B +b1100101 C +b1110011 D +b1110100 E +b1101001 F +b1101110 G +b1100111 H +b100001 I +1L #12500000 #12750000 -0dJF\@ -0}[YPW -0pK0f; -0=[Eug +0# +0. +0A +0L #13000000 -b0 }Q=~y -0,Ca!' -b0 ]7,pz -0]ky*D +b0 ! +0" +b0 ? +0@ #13250000 -1dJF\@ -b1101101 "w$'Q -b1101111 mIo&U -b1110010 LJ\m% -b1100101 `Zp>N -b100000 YR.PG -b1110100 BZ&)B -b1110011 _$[8D -b1110100 tc)n] -1}[YPW -1pK0f; -b1101101 Wz+1. -b1101111 q-WOU -b1110010 ,iWd9 -b1100101 P,^c) -b100000 s?0AD -b1110100 {,&!. -b1110011 0~wS+ -b1110100 ZqG9i -1=[Eug +1# +b1101101 $ +b1101111 % +b1110010 & +b1100101 ' +b100000 ( +b1110100 ) +b1110011 * +b1110100 + +1. +1A +b1101101 B +b1101111 C +b1110010 D +b1100101 E +b100000 F +b1110100 G +b1110011 H +b1110100 I +1L #13500000 #13750000 -0dJF\@ -0}[YPW -0pK0f; -0=[Eug +0# +0. +0A +0L #14000000 #14250000 -1dJF\@ -b0 "w$'Q -b0 mIo&U -b0 LJ\m% -b0 `Zp>N -b0 YR.PG -b0 BZ&)B -b0 _$[8D -b0 tc)n] -1}[YPW -1pK0f; -b0 Wz+1. -b0 q-WOU -b0 ,iWd9 -b0 P,^c) -b0 s?0AD -b0 {,&!. -b0 0~wS+ -b0 ZqG9i -1=[Eug +1# +b0 $ +b0 % +b0 & +b0 ' +b0 ( +b0 ) +b0 * +b0 + +1. +1A +b0 B +b0 C +b0 D +b0 E +b0 F +b0 G +b0 H +b0 I +1L #14500000 #14750000 -0dJF\@ -0}[YPW -0pK0f; -0=[Eug +0# +0. +0A +0L #15000000 diff --git a/crates/fayalite/tests/sim/expected/mod1.vcd b/crates/fayalite/tests/sim/expected/mod1.vcd index bd8676f..0d1a6f4 100644 --- a/crates/fayalite/tests/sim/expected/mod1.vcd +++ b/crates/fayalite/tests/sim/expected/mod1.vcd @@ -1,47 +1,47 @@ $timescale 1 ps $end $scope module mod1 $end $scope struct o $end -$var wire 4 avK(^ i $end -$var wire 2 Q2~aG o $end -$var wire 2 DXK'| i2 $end -$var wire 4 cPuix o2 $end +$var wire 4 ! i $end +$var wire 2 " o $end +$var wire 2 # i2 $end +$var wire 4 $ o2 $end $upscope $end $scope struct child $end -$var wire 4 ($5K7 i $end -$var wire 2 %6Wv" o $end -$var wire 2 +|-AU i2 $end -$var wire 4 Hw?%j o2 $end +$var wire 4 ) i $end +$var wire 2 * o $end +$var wire 2 + i2 $end +$var wire 4 , o2 $end $upscope $end $scope module mod1_child $end -$var wire 4 4}s%= i $end -$var wire 2 }IY?g o $end -$var wire 2 of42K i2 $end -$var wire 4 D9]&= o2 $end +$var wire 4 % i $end +$var wire 2 & o $end +$var wire 2 ' i2 $end +$var wire 4 ( o2 $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -b11 avK(^ -b11 Q2~aG -b10 DXK'| -b1110 cPuix -b11 4}s%= -b11 }IY?g -b10 of42K -b1110 D9]&= -b11 ($5K7 -b11 %6Wv" -b10 +|-AU -b1110 Hw?%j +b11 ! +b11 " +b10 # +b1110 $ +b11 % +b11 & +b10 ' +b1110 ( +b11 ) +b11 * +b10 + +b1110 , $end #1000000 -b1010 avK(^ -b10 Q2~aG -b1111 cPuix -b1010 4}s%= -b10 }IY?g -b1111 D9]&= -b1010 ($5K7 -b10 %6Wv" -b1111 Hw?%j +b1010 ! +b10 " +b1111 $ +b1010 % +b10 & +b1111 ( +b1010 ) +b10 * +b1111 , #2000000 diff --git a/crates/fayalite/tests/sim/expected/phantom_const.vcd b/crates/fayalite/tests/sim/expected/phantom_const.vcd index 8611124..ba3869b 100644 --- a/crates/fayalite/tests/sim/expected/phantom_const.vcd +++ b/crates/fayalite/tests/sim/expected/phantom_const.vcd @@ -1,31 +1,31 @@ $timescale 1 ps $end $scope module phantom_const $end $scope struct out $end -$var string 1 Ru)8A \[0] $end -$var string 1 y&ssi \[1] $end +$var string 1 ! \[0] $end +$var string 1 " \[1] $end $upscope $end $scope struct mem $end $scope struct contents $end $scope struct \[0] $end -$var string 1 =+olp mem $end +$var string 1 ' mem $end $upscope $end $upscope $end $scope struct r0 $end -$var string 0 U5SS1 addr $end -$var wire 1 rx@_T en $end -$var wire 1 o[(us clk $end -$var string 1 %Bg(6 data $end +$var string 0 # addr $end +$var wire 1 $ en $end +$var wire 1 % clk $end +$var string 1 & data $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -s0 =+olp -sPhantomConst([\"a\",\"b\"]) Ru)8A -sPhantomConst([\"a\",\"b\"]) y&ssi -s0 U5SS1 -0rx@_T -0o[(us -sPhantomConst(\"mem_element\") %Bg(6 +s0 ' +sPhantomConst([\"a\",\"b\"]) ! +sPhantomConst([\"a\",\"b\"]) " +s0 # +0$ +0% +sPhantomConst(\"mem_element\") & $end #1000000 diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.vcd b/crates/fayalite/tests/sim/expected/ripple_counter.vcd index 8071550..550205f 100644 --- a/crates/fayalite/tests/sim/expected/ripple_counter.vcd +++ b/crates/fayalite/tests/sim/expected/ripple_counter.vcd @@ -1,1713 +1,1713 @@ $timescale 1 ps $end $scope module ripple_counter $end -$var wire 1 IR0qP clk $end -$var wire 6 f0Cen o $end +$var wire 1 ! clk $end +$var wire 6 " o $end $scope struct bits $end -$var wire 1 -$(J- \[0] $end -$var wire 1 ," \[2] $end +$var wire 8 $ \[0] $end +$var wire 8 % \[1] $end +$var wire 8 & \[2] $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -0Xz8w) -0GIFRf -0OJ`bb -b0 G!R[n -b0 (H=Za -b0 Q7>," +0! +0" +0# +b0 $ +b0 % +b0 & $end #1000000 -1Xz8w) -b1 G!R[n +1! +b1 $ #2000000 -0Xz8w) +0! #3000000 -1Xz8w) +1! #4000000 -0Xz8w) +0! #5000000 -1Xz8w) +1! #6000000 -0Xz8w) +0! #7000000 -1Xz8w) +1! #8000000 -0Xz8w) +0! #9000000 -1Xz8w) +1! #10000000 -0Xz8w) +0! #11000000 -1Xz8w) +1! #12000000 -0Xz8w) +0! #13000000 -1Xz8w) +1! #14000000 -0Xz8w) +0! #15000000 -1GIFRf -b1 (H=Za +1" +b1 % #16000000 -0GIFRf +0" #17000000 -1Xz8w) +1! #18000000 -0Xz8w) +0! #19000000 -1Xz8w) +1! #20000000 -0Xz8w) +0! #21000000 -1Xz8w) +1! #22000000 -0Xz8w) +0! #23000000 -1OJ`bb -b1 Q7>," +1# +b1 & #24000000 -0OJ`bb +0# #25000000 -1Xz8w) -b10 G!R[n +1! +b10 $ #26000000 -0Xz8w) +0! #27000000 -1Xz8w) +1! #28000000 -0Xz8w) +0! #29000000 -1GIFRf -b10 (H=Za +1" +b10 % #30000000 -0GIFRf +0" #31000000 -1Xz8w) +1! #32000000 -0Xz8w) +0! #33000000 -1Xz8w) +1! #34000000 -0Xz8w) +0! #35000000 -1Xz8w) +1! #36000000 -0Xz8w) +0! #37000000 -1GIFRf +1" #38000000 -0GIFRf +0" #39000000 -1GIFRf +1" #40000000 -0GIFRf +0" #41000000 -1Xz8w) +1! #42000000 -0Xz8w) +0! #43000000 -1Xz8w) +1! #44000000 -0Xz8w) +0! #45000000 -1GIFRf +1" #46000000 -0GIFRf +0" #47000000 -1OJ`bb -b10 Q7>," +1# +b10 & #48000000 -0OJ`bb +0# #49000000 -1Xz8w) -b11 G!R[n +1! +b11 $ #50000000 -0Xz8w) +0! #51000000 -1Xz8w) +1! #52000000 -0Xz8w) +0! #53000000 -1OJ`bb -b11 Q7>," +1# +b11 & #54000000 -0OJ`bb +0# #55000000 -1Xz8w) +1! #56000000 -0Xz8w) +0! #57000000 -1Xz8w) +1! #58000000 -0Xz8w) +0! #59000000 -1Xz8w) +1! #60000000 -0Xz8w) +0! #61000000 -1OJ`bb +1# #62000000 -0OJ`bb +0# #63000000 -1GIFRf -b11 (H=Za +1" +b11 % #64000000 -0GIFRf +0" #65000000 -1Xz8w) -b100 G!R[n +1! +b100 $ #66000000 -0Xz8w) +0! #67000000 -1Xz8w) +1! #68000000 -0Xz8w) +0! #69000000 -1OJ`bb -b100 Q7>," +1# +b100 & #70000000 -0OJ`bb +0# #71000000 -1OJ`bb +1# #72000000 -0OJ`bb +0# #73000000 -1Xz8w) +1! #74000000 -0Xz8w) +0! #75000000 -1GIFRf -b100 (H=Za +1" +b100 % #76000000 -0GIFRf +0" #77000000 -1Xz8w) -b101 G!R[n +1! +b101 $ #78000000 -0Xz8w) +0! #79000000 -1Xz8w) +1! #80000000 -0Xz8w) +0! #81000000 -1Xz8w) +1! #82000000 -0Xz8w) +0! #83000000 -1GIFRf -b101 (H=Za +1" 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#436000000 -0Xz8w) +0! #437000000 -1Xz8w) -b100001 G!R[n +1! +b100001 $ #438000000 -0Xz8w) +0! #439000000 -1Xz8w) +1! #440000000 -0Xz8w) +0! #441000000 -1OJ`bb -b100001 Q7>," +1# +b100001 & #442000000 -0OJ`bb +0# #443000000 -1Xz8w) +1! #444000000 -0Xz8w) +0! #445000000 -1Xz8w) +1! #446000000 -0Xz8w) +0! #447000000 -1GIFRf -b100001 (H=Za +1" +b100001 % #448000000 -0GIFRf +0" #449000000 -1OJ`bb -b100010 Q7>," +1# +b100010 & #450000000 -0OJ`bb +0# #451000000 -1Xz8w) -b100010 G!R[n +1! +b100010 $ #452000000 -0Xz8w) +0! #453000000 -1Xz8w) +1! #454000000 -0Xz8w) +0! #455000000 -1OJ`bb +1# #456000000 -0OJ`bb +0# #457000000 -1OJ`bb +1# #458000000 -0OJ`bb +0# #459000000 -1Xz8w) +1! #460000000 -0Xz8w) +0! #461000000 -1GIFRf -b100010 (H=Za +1" +b100010 % #462000000 -0GIFRf +0" #463000000 -1Xz8w) -b100011 G!R[n +1! +b100011 $ #464000000 -0Xz8w) +0! #465000000 -1OJ`bb -b100011 Q7>," +1# +b100011 & #466000000 -0OJ`bb +0# #467000000 -1Xz8w) +1! #468000000 -0Xz8w) +0! #469000000 -1GIFRf -b100011 (H=Za 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#500000000 -0Xz8w) +0! #501000000 -1OJ`bb +1# #502000000 -0OJ`bb +0# #503000000 -1OJ`bb +1# #504000000 -0OJ`bb +0# #505000000 -1OJ`bb +1# #506000000 -0OJ`bb +0# #507000000 -1GIFRf -b100111 (H=Za +1" +b100111 % #508000000 -0GIFRf +0" #509000000 -1Xz8w) -b101000 G!R[n +1! +b101000 $ #510000000 -0Xz8w) +0! #511000000 -1Xz8w) +1! #512000000 -0Xz8w) +0! #513000000 -1OJ`bb -b101000 Q7>," +1# +b101000 & #514000000 -0OJ`bb +0# #515000000 -1GIFRf -b101000 (H=Za +1" +b101000 % #516000000 -0GIFRf +0" #517000000 -1Xz8w) -b101001 G!R[n +1! +b101001 $ #518000000 -0Xz8w) +0! #519000000 -1GIFRf -b101001 (H=Za +1" +b101001 % #520000000 -0GIFRf +0" #521000000 -1OJ`bb -b101001 Q7>," +1# +b101001 & #522000000 -0OJ`bb +0# #523000000 -1GIFRf -b101010 (H=Za +1" +b101010 % #524000000 -0GIFRf +0" #525000000 -1Xz8w) -b101010 G!R[n +1! +b101010 $ #526000000 -0Xz8w) +0! #527000000 -1OJ`bb -b101010 Q7>," +1# +b101010 & #528000000 -0OJ`bb +0# #529000000 -1OJ`bb -b101011 Q7>," +1# +b101011 & #530000000 -0OJ`bb +0# #531000000 -1GIFRf -b101011 (H=Za +1" +b101011 % #532000000 -0GIFRf +0" #533000000 -1GIFRf +1" #534000000 -0GIFRf +0" #535000000 -1Xz8w) -b101011 G!R[n +1! +b101011 $ #536000000 -0Xz8w) +0! #537000000 -1OJ`bb -b101100 Q7>," +1# +b101100 & #538000000 -0OJ`bb +0# #539000000 -1GIFRf -b101100 (H=Za +1" +b101100 % #540000000 -0GIFRf +0" #541000000 -1GIFRf +1" #542000000 -0GIFRf +0" #543000000 -1GIFRf +1" #544000000 -0GIFRf +0" #545000000 -1OJ`bb +1# #546000000 -0OJ`bb +0# #547000000 -1GIFRf +1" #548000000 -0GIFRf +0" #549000000 -1GIFRf +1" #550000000 -0GIFRf +0" #551000000 -1OJ`bb +1# #552000000 -0OJ`bb +0# #553000000 -1OJ`bb +1# #554000000 -0OJ`bb +0# #555000000 -1GIFRf +1" #556000000 -0GIFRf +0" #557000000 -1OJ`bb +1# #558000000 -0OJ`bb +0# #559000000 -1Xz8w) -b101100 G!R[n +1! +b101100 $ #560000000 -0Xz8w) +0! #561000000 -1OJ`bb -b101101 Q7>," +1# +b101101 & #562000000 -0OJ`bb +0# #563000000 -1GIFRf -b101101 (H=Za +1" +b101101 % #564000000 -0GIFRf +0" #565000000 -1OJ`bb +1# #566000000 -0OJ`bb +0# #567000000 -1GIFRf +1" #568000000 -0GIFRf +0" #569000000 -1OJ`bb +1# #570000000 -0OJ`bb +0# #571000000 -1GIFRf +1" #572000000 -0GIFRf +0" #573000000 -1OJ`bb +1# #574000000 -0OJ`bb +0# #575000000 -1OJ`bb +1# #576000000 -0OJ`bb +0# #577000000 -1OJ`bb +1# #578000000 -0OJ`bb +0# #579000000 -1OJ`bb +1# #580000000 -0OJ`bb +0# #581000000 -1Xz8w) -b101101 G!R[n +1! +b101101 $ #582000000 -0Xz8w) +0! #583000000 -1Xz8w) -b101110 G!R[n +1! +b101110 $ #584000000 -0Xz8w) +0! #585000000 -1OJ`bb -b101110 Q7>," +1# +b101110 & #586000000 -0OJ`bb +0# #587000000 -1OJ`bb +1# #588000000 -0OJ`bb +0# #589000000 -1Xz8w) +1! #590000000 -0Xz8w) +0! #591000000 -1GIFRf -b101110 (H=Za +1" +b101110 % #592000000 -0GIFRf +0" #593000000 -1OJ`bb -b101111 Q7>," +1# +b101111 & #594000000 -0OJ`bb +0# #595000000 -1OJ`bb +1# #596000000 -0OJ`bb +0# #597000000 -1Xz8w) -b101111 G!R[n +1! +b101111 $ #598000000 -0Xz8w) +0! #599000000 -1OJ`bb +1# #600000000 -0OJ`bb +0# #601000000 -1OJ`bb +1# #602000000 -0OJ`bb +0# #603000000 -1OJ`bb +1# #604000000 -0OJ`bb +0# #605000000 -1GIFRf -b101111 (H=Za +1" +b101111 % #606000000 -0GIFRf +0" #607000000 -1Xz8w) -b110000 G!R[n +1! +b110000 $ #608000000 -0Xz8w) +0! #609000000 -1OJ`bb -b110000 Q7>," +1# +b110000 & #610000000 -0OJ`bb +0# #611000000 -1OJ`bb +1# #612000000 -0OJ`bb +0# #613000000 -1GIFRf -b110000 (H=Za +1" +b110000 % #614000000 -0GIFRf +0" #615000000 -1GIFRf -b110001 (H=Za +1" +b110001 % #616000000 -0GIFRf +0" #617000000 -1OJ`bb -b110001 Q7>," +1# +b110001 & #618000000 -0OJ`bb +0# #619000000 -1OJ`bb +1# #620000000 -0OJ`bb +0# #621000000 -1GIFRf +1" #622000000 -0GIFRf +0" #623000000 -1OJ`bb +1# #624000000 -0OJ`bb +0# #625000000 -1OJ`bb +1# #626000000 -0OJ`bb +0# #627000000 -1OJ`bb +1# #628000000 -0OJ`bb +0# #629000000 -1OJ`bb +1# #630000000 -0OJ`bb +0# #631000000 -1Xz8w) -b110001 G!R[n +1! +b110001 $ #632000000 -0Xz8w) +0! #633000000 -1OJ`bb -b110010 Q7>," +1# +b110010 & #634000000 -0OJ`bb +0# #635000000 -1OJ`bb +1# #636000000 -0OJ`bb +0# #637000000 -1OJ`bb +1# #638000000 -0OJ`bb +0# #639000000 -1GIFRf -b110010 (H=Za +1" +b110010 % #640000000 -0GIFRf +0" #641000000 -1OJ`bb +1# #642000000 -0OJ`bb +0# #643000000 -1OJ`bb +1# #644000000 -0OJ`bb +0# #645000000 -1OJ`bb +1# #646000000 -0OJ`bb +0# #647000000 -1OJ`bb +1# #648000000 -0OJ`bb +0# diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.vcd b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.vcd index cb7bac4..555e83e 100644 --- a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.vcd +++ b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.vcd @@ -1,1467 +1,1467 @@ $timescale 1 ps $end $scope module sim_fork_join_scope $end $scope struct clocks $end -$var wire 1 `,lzL \[0] $end -$var wire 1 SA$wv \[1] $end -$var wire 1 out2 $end -$var string 1 8(7-4 out3 $end +$var string 1 # inp $end +$var string 1 $ out1 $end +$var string 1 % out2 $end +$var string 1 & out3 $end $scope struct helper1 $end $scope struct cd $end -$var wire 1 $Kwp\ clk $end -$var wire 1 nmVq' rst $end +$var wire 1 + clk $end +$var wire 1 , rst $end $upscope $end -$var string 1 qS)@z inp $end -$var string 1 ~je// out $end +$var string 1 - inp $end +$var string 1 . out $end $upscope $end $scope module sim_only_connects_helper $end $scope struct cd $end -$var wire 1 %uCn6 clk $end -$var wire 1 Apu`K rst $end +$var wire 1 ' clk $end +$var wire 1 ( rst $end $upscope $end -$var string 1 $U*lA inp $end -$var string 1 !prwC out $end +$var string 1 ) inp $end +$var string 1 * out $end $upscope $end -$var string 1 CyjVm delay1 $end -$var reg 1 z~g{\ delay1_empty $end +$var string 1 / delay1 $end +$var reg 1 0 delay1_empty $end $scope struct helper2 $end $scope struct cd $end -$var wire 1 Ph.=# clk $end -$var wire 1 !GXK\ rst $end +$var wire 1 5 clk $end +$var wire 1 6 rst $end $upscope $end -$var string 1 /YVv: inp $end -$var string 1 Kk*{# out $end +$var string 1 7 inp $end +$var string 1 8 out $end $upscope $end $scope module sim_only_connects_helper_2 $end $scope struct cd $end -$var wire 1 %uCn6" clk $end -$var wire 1 Apu`K" rst $end +$var wire 1 1 clk $end +$var wire 1 2 rst $end $upscope $end -$var string 1 $U*lA" inp $end -$var string 1 !prwC" out $end +$var string 1 3 inp $end +$var string 1 4 out $end $upscope $end $upscope $end $enddefinitions $end $dumpvars -0tq:(w -1FVlgb -s{\"extra\":\x20\"value\"} g:xf? -s{} [OKKg -s{} 9pB-> -s{} 8(7-4 -0%uCn6 -1Apu`K -s{} $U*lA -s{} !prwC -0$Kwp\ -1nmVq' -s{} qS)@z -s{} ~je// -s{} CyjVm -0z~g{\ -0%uCn6" -1Apu`K" -s{} $U*lA" -s{} !prwC" -0Ph.=# -1!GXK\ -s{} /YVv: -s{} Kk*{# +0! +1" +s{\"extra\":\x20\"value\"} # +s{} $ +s{} % +s{} & +0' +1( +s{} ) +s{} * +0+ +1, +s{} - +s{} . +s{} / +00 +01 +12 +s{} 3 +s{} 4 +05 +16 +s{} 7 +s{} 8 $end #1000000 -1tq:(w -s{\"extra\":\x20\"value\"} [OKKg -1%uCn6 -s{\"extra\":\x20\"value\"} $U*lA -1$Kwp\ -s{\"extra\":\x20\"value\"} qS)@z -1z~g{\ -1%uCn6" -1Ph.=# -s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 9pB-> -s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} !prwC -s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} ~je// -s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} $U*lA" -s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} /YVv: -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8(7-4 -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} !prwC" -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} Kk*{# +1! +s{\"extra\":\x20\"value\"} $ +1' +s{\"extra\":\x20\"value\"} ) +1+ +s{\"extra\":\x20\"value\"} - +10 +11 +15 +s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} % +s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} * +s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} . +s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 3 +s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 7 +s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} & +s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 4 +s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8 #2000000 -0tq:(w -0FVlgb -0%uCn6 -0Apu`K -0$Kwp\ -0nmVq' -0%uCn6" -0Apu`K" -0Ph.=# -0!GXK\ +0! +0" +0' +0( +0+ +0, +01 +02 +05 +06 #3000000 -1tq:(w -1%uCn6 -1$Kwp\ -s{\"extra\":\x20\"value\"} CyjVm -0z~g{\ -1%uCn6" -1Ph.=# +1! +1' +1+ +s{\"extra\":\x20\"value\"} / +00 +11 +15 #4000000 -0tq:(w -0%uCn6 -0$Kwp\ -0%uCn6" -0Ph.=# +0! +0' +0+ +01 +05 #5000000 -1tq:(w -1%uCn6 -1$Kwp\ -1%uCn6" -1Ph.=# +1! +1' +1+ +11 +15 #6000000 -0tq:(w -0%uCn6 -0$Kwp\ -0%uCn6" -0Ph.=# +0! +0' +0+ +01 +05 #7000000 -1tq:(w -1%uCn6 -1$Kwp\ -1%uCn6" -1Ph.=# +1! +1' +1+ +11 +15 #8000000 -0tq:(w -0%uCn6 -0$Kwp\ -0%uCn6" -0Ph.=# +0! +0' +0+ +01 +05 #9000000 -1tq:(w -1%uCn6 -1$Kwp\ -1%uCn6" -1Ph.=# +1! +1' +1+ +11 +15 #10000000 -0tq:(w -0%uCn6 -0$Kwp\ -0%uCn6" -0Ph.=# +0! +0' +0+ +01 +05 #11000000 -1tq:(w -1%uCn6 -1$Kwp\ -1%uCn6" -1Ph.=# +1! +1' +1+ +11 +15 #12000000 -0tq:(w -0%uCn6 -0$Kwp\ -0%uCn6" -0Ph.=# +0! +0' +0+ +01 +05 #13000000 -1tq:(w -1%uCn6 -1$Kwp\ -1%uCn6" -1Ph.=# +1! +1' +1+ +11 +15 #14000000 -0tq:(w -0%uCn6 -0$Kwp\ -0%uCn6" -0Ph.=# +0! +0' +0+ +01 +05 #15000000 -1tq:(w -1%uCn6 -1$Kwp\ -1%uCn6" -1Ph.=# +1! +1' +1+ +11 +15 #16000000 diff --git a/crates/fayalite/tests/sim/expected/sim_read_past.vcd b/crates/fayalite/tests/sim/expected/sim_read_past.vcd index e98fc97..5d0a932 100644 --- a/crates/fayalite/tests/sim/expected/sim_read_past.vcd +++ b/crates/fayalite/tests/sim/expected/sim_read_past.vcd @@ -1,1908 +1,1908 @@ $timescale 1 ps $end $scope module sim_read_past $end $scope struct clocks $end -$var wire 1 zV+7l \[0] $end -$var wire 1 7&!` cannot be shared between threads safely - --> tests/ui/simvalue_is_not_internable.rs:11:26 - | - 11 | fn f(v: SimValue<()>) -> Interned> { - | ^^^^^^^^^^^^^^^^^^^^^^ `Cell` cannot be shared between threads safely - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell` - = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock` + --> tests/ui/simvalue_is_not_internable.rs:11:26 + | +11 | fn f(v: SimValue<()>) -> Interned> { + | ^^^^^^^^^^^^^^^^^^^^^^ `Cell` cannot be shared between threads safely + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell` + = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock` note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - 22 | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `fayalite::intern::Interned` - --> src/intern.rs - | - | pub struct Interned { - | ^^^^ required by this bound in `Interned` + --> src/intern.rs + | + | pub struct Interned { + | ^^^^ required by this bound in `Interned` error[E0277]: `UnsafeCell>` cannot be shared between threads safely - --> tests/ui/simvalue_is_not_internable.rs:11:26 - | - 11 | fn f(v: SimValue<()>) -> Interned> { - | ^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell>` cannot be shared between threads safely - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell>` + --> tests/ui/simvalue_is_not_internable.rs:11:26 + | +11 | fn f(v: SimValue<()>) -> Interned> { + | ^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell>` cannot be shared between threads safely + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell>` note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - 22 | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `fayalite::intern::Interned` - --> src/intern.rs - | - | pub struct Interned { - | ^^^^ required by this bound in `Interned` + --> src/intern.rs + | + | pub struct Interned { + | ^^^^ required by this bound in `Interned` error[E0277]: `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely - --> tests/ui/simvalue_is_not_internable.rs:11:26 - | - 11 | fn f(v: SimValue<()>) -> Interned> { - | ^^^^^^^^^^^^^^^^^^^^^^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` + --> tests/ui/simvalue_is_not_internable.rs:11:26 + | +11 | fn f(v: SimValue<()>) -> Interned> { + | ^^^^^^^^^^^^^^^^^^^^^^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` note: required because it appears within the type `DynSimOnlyValue` - --> src/sim/value/sim_only_value_unsafe.rs - | - | pub struct DynSimOnlyValue(Rc); - | ^^^^^^^^^^^^^^^ + --> src/sim/value/sim_only_value_unsafe.rs + | + | pub struct DynSimOnlyValue(Rc); + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `PhantomData` - --> $RUST/core/src/marker.rs + --> $RUST/core/src/marker.rs + | + | pub struct PhantomData; + | ^^^^^^^^^^^ note: required because it appears within the type `alloc::raw_vec::RawVec` - --> $RUST/alloc/src/raw_vec/mod.rs + --> $RUST/alloc/src/raw_vec/mod.rs + | + | pub(crate) struct RawVec { + | ^^^^^^ note: required because it appears within the type `Vec` - --> $RUST/alloc/src/vec/mod.rs + --> $RUST/alloc/src/vec/mod.rs + | + | pub struct Vec { + | ^^^ note: required because it appears within the type `OpaqueSimValue` - --> src/ty.rs - | - | pub struct OpaqueSimValue { - | ^^^^^^^^^^^^^^ + --> src/ty.rs + | + | pub struct OpaqueSimValue { + | ^^^^^^^^^^^^^^ note: required because it appears within the type `value::SimValueInner<()>` - --> src/sim/value.rs - | - 51 | struct SimValueInner { - | ^^^^^^^^^^^^^ + --> src/sim/value.rs + | + | struct SimValueInner { + | ^^^^^^^^^^^^^ note: required because it appears within the type `UnsafeCell>` - --> $RUST/core/src/cell.rs + --> $RUST/core/src/cell.rs + | + | pub struct UnsafeCell { + | ^^^^^^^^^^ note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - 22 | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `fayalite::intern::Interned` - --> src/intern.rs - | - | pub struct Interned { - | ^^^^ required by this bound in `Interned` + --> src/intern.rs + | + | pub struct Interned { + | ^^^^ required by this bound in `Interned` error[E0277]: the trait bound `fayalite::prelude::SimValue<()>: Intern` is not satisfied --> tests/ui/simvalue_is_not_internable.rs:12:26 @@ -106,214 +118,238 @@ help: consider dereferencing here | + error[E0277]: `Cell` cannot be shared between threads safely - --> tests/ui/simvalue_is_not_internable.rs:12:26 - | - 12 | Intern::intern_sized(v) - | -------------------- ^ `Cell` cannot be shared between threads safely - | | - | required by a bound introduced by this call - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell` - = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock` + --> tests/ui/simvalue_is_not_internable.rs:12:26 + | +12 | Intern::intern_sized(v) + | -------------------- ^ `Cell` cannot be shared between threads safely + | | + | required by a bound introduced by this call + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell` + = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock` note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - 22 | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `intern_sized` - --> src/intern.rs - | - | pub trait Intern: Any + Send + Sync { - | ^^^^ required by this bound in `Intern::intern_sized` + --> src/intern.rs + | + | pub trait Intern: Any + Send + Sync { + | ^^^^ required by this bound in `Intern::intern_sized` ... - | fn intern_sized(self) -> Interned - | ------------ required by a bound in this associated function + | fn intern_sized(self) -> Interned + | ------------ required by a bound in this associated function help: consider dereferencing here - | - 12 | Intern::intern_sized(*v) - | + + | +12 | Intern::intern_sized(*v) + | + error[E0277]: `UnsafeCell>` cannot be shared between threads safely - --> tests/ui/simvalue_is_not_internable.rs:12:26 - | - 12 | Intern::intern_sized(v) - | -------------------- ^ `UnsafeCell>` cannot be shared between threads safely - | | - | required by a bound introduced by this call - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell>` + --> tests/ui/simvalue_is_not_internable.rs:12:26 + | +12 | Intern::intern_sized(v) + | -------------------- ^ `UnsafeCell>` cannot be shared between threads safely + | | + | required by a bound introduced by this call + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell>` note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - 22 | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `intern_sized` - --> src/intern.rs - | - | pub trait Intern: Any + Send + Sync { - | ^^^^ required by this bound in `Intern::intern_sized` + --> src/intern.rs + | + | pub trait Intern: Any + Send + Sync { + | ^^^^ required by this bound in `Intern::intern_sized` ... - | fn intern_sized(self) -> Interned - | ------------ required by a bound in this associated function + | fn intern_sized(self) -> Interned + | ------------ required by a bound in this associated function help: consider dereferencing here - | - 12 | Intern::intern_sized(*v) - | + + | +12 | Intern::intern_sized(*v) + | + error[E0277]: `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely - --> tests/ui/simvalue_is_not_internable.rs:12:26 - | - 12 | Intern::intern_sized(v) - | -------------------- ^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely - | | - | required by a bound introduced by this call - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` + --> tests/ui/simvalue_is_not_internable.rs:12:26 + | +12 | Intern::intern_sized(v) + | -------------------- ^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely + | | + | required by a bound introduced by this call + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` note: required because it appears within the type `DynSimOnlyValue` - --> src/sim/value/sim_only_value_unsafe.rs - | - | pub struct DynSimOnlyValue(Rc); - | ^^^^^^^^^^^^^^^ + --> src/sim/value/sim_only_value_unsafe.rs + | + | pub struct DynSimOnlyValue(Rc); + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `PhantomData` - --> $RUST/core/src/marker.rs + --> $RUST/core/src/marker.rs + | + | pub struct PhantomData; + | ^^^^^^^^^^^ note: required because it appears within the type `alloc::raw_vec::RawVec` - --> $RUST/alloc/src/raw_vec/mod.rs + --> $RUST/alloc/src/raw_vec/mod.rs + | + | pub(crate) struct RawVec { + | ^^^^^^ note: required because it appears within the type `Vec` - --> $RUST/alloc/src/vec/mod.rs + --> $RUST/alloc/src/vec/mod.rs + | + | pub struct Vec { + | ^^^ note: required because it appears within the type `OpaqueSimValue` - --> src/ty.rs - | - | pub struct OpaqueSimValue { - | ^^^^^^^^^^^^^^ + --> src/ty.rs + | + | pub struct OpaqueSimValue { + | ^^^^^^^^^^^^^^ note: required because it appears within the type `value::SimValueInner<()>` - --> src/sim/value.rs - | - 51 | struct SimValueInner { - | ^^^^^^^^^^^^^ + --> src/sim/value.rs + | + | struct SimValueInner { + | ^^^^^^^^^^^^^ note: required because it appears within the type `UnsafeCell>` - --> $RUST/core/src/cell.rs + --> $RUST/core/src/cell.rs + | + | pub struct UnsafeCell { + | ^^^^^^^^^^ note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - 22 | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `intern_sized` - --> src/intern.rs - | - | pub trait Intern: Any + Send + Sync { - | ^^^^ required by this bound in `Intern::intern_sized` + --> src/intern.rs + | + | pub trait Intern: Any + Send + Sync { + | ^^^^ required by this bound in `Intern::intern_sized` ... - | fn intern_sized(self) -> Interned - | ------------ required by a bound in this associated function + | fn intern_sized(self) -> Interned + | ------------ required by a bound in this associated function help: consider dereferencing here - | - 12 | Intern::intern_sized(*v) - | + + | +12 | Intern::intern_sized(*v) + | + error[E0277]: `Cell` cannot be shared between threads safely - --> tests/ui/simvalue_is_not_internable.rs:12:5 - | - 12 | Intern::intern_sized(v) - | ^^^^^^^^^^^^^^^^^^^^^^^ `Cell` cannot be shared between threads safely - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell` - = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock` + --> tests/ui/simvalue_is_not_internable.rs:12:5 + | +12 | Intern::intern_sized(v) + | ^^^^^^^^^^^^^^^^^^^^^^^ `Cell` cannot be shared between threads safely + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `Cell` + = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock` note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - 22 | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `fayalite::intern::Interned` - --> src/intern.rs - | - | pub struct Interned { - | ^^^^ required by this bound in `Interned` + --> src/intern.rs + | + | pub struct Interned { + | ^^^^ required by this bound in `Interned` error[E0277]: `UnsafeCell>` cannot be shared between threads safely - --> tests/ui/simvalue_is_not_internable.rs:12:5 - | - 12 | Intern::intern_sized(v) - | ^^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell>` cannot be shared between threads safely - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell>` + --> tests/ui/simvalue_is_not_internable.rs:12:5 + | +12 | Intern::intern_sized(v) + | ^^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell>` cannot be shared between threads safely + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell>` note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - 22 | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `fayalite::intern::Interned` - --> src/intern.rs - | - | pub struct Interned { - | ^^^^ required by this bound in `Interned` + --> src/intern.rs + | + | pub struct Interned { + | ^^^^ required by this bound in `Interned` error[E0277]: `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely - --> tests/ui/simvalue_is_not_internable.rs:12:5 - | - 12 | Intern::intern_sized(v) - | ^^^^^^^^^^^^^^^^^^^^^^^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely - | - = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` + --> tests/ui/simvalue_is_not_internable.rs:12:5 + | +12 | Intern::intern_sized(v) + | ^^^^^^^^^^^^^^^^^^^^^^^ `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` cannot be sent between threads safely + | + = help: within `fayalite::prelude::SimValue<()>`, the trait `Send` is not implemented for `Rc<(dyn value::sim_only_value_unsafe::DynSimOnlyValueTrait + 'static)>` note: required because it appears within the type `DynSimOnlyValue` - --> src/sim/value/sim_only_value_unsafe.rs - | - | pub struct DynSimOnlyValue(Rc); - | ^^^^^^^^^^^^^^^ + --> src/sim/value/sim_only_value_unsafe.rs + | + | pub struct DynSimOnlyValue(Rc); + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `PhantomData` - --> $RUST/core/src/marker.rs + --> $RUST/core/src/marker.rs + | + | pub struct PhantomData; + | ^^^^^^^^^^^ note: required because it appears within the type `alloc::raw_vec::RawVec` - --> $RUST/alloc/src/raw_vec/mod.rs + --> $RUST/alloc/src/raw_vec/mod.rs + | + | pub(crate) struct RawVec { + | ^^^^^^ note: required because it appears within the type `Vec` - --> $RUST/alloc/src/vec/mod.rs + --> $RUST/alloc/src/vec/mod.rs + | + | pub struct Vec { + | ^^^ note: required because it appears within the type `OpaqueSimValue` - --> src/ty.rs - | - | pub struct OpaqueSimValue { - | ^^^^^^^^^^^^^^ + --> src/ty.rs + | + | pub struct OpaqueSimValue { + | ^^^^^^^^^^^^^^ note: required because it appears within the type `value::SimValueInner<()>` - --> src/sim/value.rs - | - 51 | struct SimValueInner { - | ^^^^^^^^^^^^^ + --> src/sim/value.rs + | + | struct SimValueInner { + | ^^^^^^^^^^^^^ note: required because it appears within the type `UnsafeCell>` - --> $RUST/core/src/cell.rs + --> $RUST/core/src/cell.rs + | + | pub struct UnsafeCell { + | ^^^^^^^^^^ note: required because it appears within the type `util::alternating_cell::AlternatingCell>` - --> src/util/alternating_cell.rs - | - 22 | pub(crate) struct AlternatingCell { - | ^^^^^^^^^^^^^^^ + --> src/util/alternating_cell.rs + | + | pub(crate) struct AlternatingCell { + | ^^^^^^^^^^^^^^^ note: required because it appears within the type `fayalite::prelude::SimValue<()>` - --> src/sim/value.rs - | - | pub struct SimValue { - | ^^^^^^^^ + --> src/sim/value.rs + | + | pub struct SimValue { + | ^^^^^^^^ note: required by a bound in `fayalite::intern::Interned` - --> src/intern.rs - | - | pub struct Interned { - | ^^^^ required by this bound in `Interned` + --> src/intern.rs + | + | pub struct Interned { + | ^^^^ required by this bound in `Interned`