From ff94dda922ebd2a57b371ce9dd257001103edd9a Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 20 Sep 2024 18:42:24 -0700
Subject: [PATCH 001/190] support #[hdl] on functions -- enables #[hdl] usage
 in function body

---
 .../src/hdl_bundle.rs                         |  10 +-
 .../fayalite-proc-macros-impl/src/hdl_enum.rs |  12 +-
 .../src/hdl_type_common.rs                    |  28 ++-
 crates/fayalite-proc-macros-impl/src/lib.rs   | 137 ++++++----
 .../fayalite-proc-macros-impl/src/module.rs   | 236 +++++++++++++-----
 .../src/module/transform_body.rs              |  49 ++--
 .../expand_aggregate_literals.rs              |  18 +-
 .../src/module/transform_body/expand_match.rs |   5 +-
 crates/fayalite/tests/ui/hdl_types.stderr     |   2 +-
 9 files changed, 341 insertions(+), 156 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
index f29f43a..7f7d626 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
@@ -19,13 +19,13 @@ use syn::{
 #[derive(Clone, Debug)]
 pub(crate) struct ParsedBundle {
     pub(crate) attrs: Vec<Attribute>,
-    pub(crate) options: HdlAttr<ItemOptions>,
+    pub(crate) options: HdlAttr<ItemOptions, kw::hdl>,
     pub(crate) vis: Visibility,
     pub(crate) struct_token: Token![struct],
     pub(crate) ident: Ident,
     pub(crate) generics: MaybeParsed<ParsedGenerics, Generics>,
     pub(crate) fields: MaybeParsed<ParsedFieldsNamed, FieldsNamed>,
-    pub(crate) field_flips: Vec<Option<HdlAttr<kw::flip>>>,
+    pub(crate) field_flips: Vec<Option<HdlAttr<kw::flip, kw::hdl>>>,
     pub(crate) mask_type_ident: Ident,
     pub(crate) mask_type_match_variant_ident: Ident,
     pub(crate) match_variant_ident: Ident,
@@ -38,7 +38,7 @@ impl ParsedBundle {
         errors: &mut Errors,
         field: &mut Field,
         index: usize,
-    ) -> Option<HdlAttr<kw::flip>> {
+    ) -> Option<HdlAttr<kw::flip, kw::hdl>> {
         let Field {
             attrs,
             vis: _,
@@ -71,7 +71,9 @@ impl ParsedBundle {
         } = item;
         let mut errors = Errors::new();
         let mut options = errors
-            .unwrap_or_default(HdlAttr::<ItemOptions>::parse_and_take_attr(&mut attrs))
+            .unwrap_or_default(HdlAttr::<ItemOptions, kw::hdl>::parse_and_take_attr(
+                &mut attrs,
+            ))
             .unwrap_or_default();
         errors.ok(options.body.validate());
         let ItemOptions {
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
index 1e0b66b..d7e5b61 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
@@ -3,7 +3,7 @@ use crate::{
         common_derives, get_target, ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics,
         ParsedType, SplitForImpl, TypesParser, WrappedInConst,
     },
-    Errors, HdlAttr, PairsIterExt,
+    kw, Errors, HdlAttr, PairsIterExt,
 };
 use proc_macro2::TokenStream;
 use quote::{format_ident, quote_spanned, ToTokens};
@@ -29,7 +29,7 @@ crate::options! {
 pub(crate) struct ParsedVariantField {
     pub(crate) paren_token: Paren,
     pub(crate) attrs: Vec<Attribute>,
-    pub(crate) options: HdlAttr<FieldOptions>,
+    pub(crate) options: HdlAttr<FieldOptions, kw::hdl>,
     pub(crate) ty: MaybeParsed<ParsedType, Type>,
     pub(crate) comma_token: Option<Token![,]>,
 }
@@ -37,7 +37,7 @@ pub(crate) struct ParsedVariantField {
 #[derive(Clone, Debug)]
 pub(crate) struct ParsedVariant {
     pub(crate) attrs: Vec<Attribute>,
-    pub(crate) options: HdlAttr<VariantOptions>,
+    pub(crate) options: HdlAttr<VariantOptions, kw::hdl>,
     pub(crate) ident: Ident,
     pub(crate) field: Option<ParsedVariantField>,
 }
@@ -119,7 +119,7 @@ impl ParsedVariant {
 #[derive(Clone, Debug)]
 pub(crate) struct ParsedEnum {
     pub(crate) attrs: Vec<Attribute>,
-    pub(crate) options: HdlAttr<ItemOptions>,
+    pub(crate) options: HdlAttr<ItemOptions, kw::hdl>,
     pub(crate) vis: Visibility,
     pub(crate) enum_token: Token![enum],
     pub(crate) ident: Ident,
@@ -142,7 +142,9 @@ impl ParsedEnum {
         } = item;
         let mut errors = Errors::new();
         let mut options = errors
-            .unwrap_or_default(HdlAttr::<ItemOptions>::parse_and_take_attr(&mut attrs))
+            .unwrap_or_default(HdlAttr::<ItemOptions, kw::hdl>::parse_and_take_attr(
+                &mut attrs,
+            ))
             .unwrap_or_default();
         errors.ok(options.body.validate());
         let ItemOptions {
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
index 88da9a7..e33d0e0 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
@@ -1745,7 +1745,7 @@ impl<T: ParseTypes<I>, I, P: Clone> ParseTypes<Punctuated<I, P>> for Punctuated<
 pub(crate) enum UnparsedGenericParam {
     Type {
         attrs: Vec<Attribute>,
-        options: HdlAttr<TypeParamOptions>,
+        options: HdlAttr<TypeParamOptions, kw::hdl>,
         ident: Ident,
         colon_token: Token![:],
         bounds: ParsedBounds,
@@ -1753,7 +1753,7 @@ pub(crate) enum UnparsedGenericParam {
     },
     Const {
         attrs: Vec<Attribute>,
-        options: HdlAttr<ConstParamOptions>,
+        options: HdlAttr<ConstParamOptions, kw::hdl>,
         const_token: Token![const],
         ident: Ident,
         colon_token: Token![:],
@@ -2278,7 +2278,7 @@ impl ParsedBound {
 #[derive(Debug, Clone)]
 pub(crate) struct ParsedTypeParam {
     pub(crate) attrs: Vec<Attribute>,
-    pub(crate) options: HdlAttr<TypeParamOptions>,
+    pub(crate) options: HdlAttr<TypeParamOptions, kw::hdl>,
     pub(crate) ident: Ident,
     pub(crate) colon_token: Token![:],
     pub(crate) bounds: ParsedTypeBounds,
@@ -2312,7 +2312,7 @@ impl ToTokens for ParsedTypeParam {
 #[derive(Debug, Clone)]
 pub(crate) struct ParsedSizeTypeParam {
     pub(crate) attrs: Vec<Attribute>,
-    pub(crate) options: HdlAttr<TypeParamOptions>,
+    pub(crate) options: HdlAttr<TypeParamOptions, kw::hdl>,
     pub(crate) ident: Ident,
     pub(crate) colon_token: Token![:],
     pub(crate) bounds: ParsedSizeTypeBounds,
@@ -2356,7 +2356,7 @@ pub(crate) struct ParsedConstParamWhereBounds {
 #[derive(Debug, Clone)]
 pub(crate) struct ParsedConstParam {
     pub(crate) attrs: Vec<Attribute>,
-    pub(crate) options: HdlAttr<ConstParamOptions>,
+    pub(crate) options: HdlAttr<ConstParamOptions, kw::hdl>,
     pub(crate) const_token: Token![const],
     pub(crate) ident: Ident,
     pub(crate) colon_token: Token![:],
@@ -2413,7 +2413,7 @@ impl ParsedGenericParam {
     }
 }
 
-#[derive(Debug, Clone)]
+#[derive(Debug, Clone, Default)]
 pub(crate) struct ParsedGenerics {
     pub(crate) lt_token: Option<Token![<]>,
     pub(crate) params: Punctuated<ParsedGenericParam, Token![,]>,
@@ -2863,9 +2863,11 @@ impl ParsedGenerics {
             let (input_param, punct) = input_param.into_tuple();
             let (unparsed_param, late_parsed_param) = match input_param {
                 GenericParam::Lifetime(param) => {
-                    errors.unwrap_or_default(HdlAttr::<LifetimeParamOptions>::parse_and_take_attr(
-                        &mut param.attrs,
-                    ));
+                    errors.unwrap_or_default(
+                        HdlAttr::<LifetimeParamOptions, kw::hdl>::parse_and_take_attr(
+                            &mut param.attrs,
+                        ),
+                    );
                     errors.error(param, "lifetime generics are not supported by #[hdl]");
                     continue;
                 }
@@ -2879,7 +2881,9 @@ impl ParsedGenerics {
                 }) => {
                     let span = ident.span();
                     let options = errors
-                        .unwrap_or_default(HdlAttr::<TypeParamOptions>::parse_and_take_attr(attrs))
+                        .unwrap_or_default(
+                            HdlAttr::<TypeParamOptions, kw::hdl>::parse_and_take_attr(attrs),
+                        )
                         .unwrap_or_default();
                     let colon_token = colon_token.unwrap_or_else(|| Token![:](span));
                     if !bounds.is_empty() {
@@ -2917,7 +2921,9 @@ impl ParsedGenerics {
                     default,
                 }) => {
                     let options = errors
-                        .unwrap_or_default(HdlAttr::<ConstParamOptions>::parse_and_take_attr(attrs))
+                        .unwrap_or_default(
+                            HdlAttr::<ConstParamOptions, kw::hdl>::parse_and_take_attr(attrs),
+                        )
                         .unwrap_or_default();
                     if let Some(default) = default {
                         let _ = eq_token;
diff --git a/crates/fayalite-proc-macros-impl/src/lib.rs b/crates/fayalite-proc-macros-impl/src/lib.rs
index 94fb040..3ec00bf 100644
--- a/crates/fayalite-proc-macros-impl/src/lib.rs
+++ b/crates/fayalite-proc-macros-impl/src/lib.rs
@@ -9,7 +9,8 @@ use syn::{
     parse::{Parse, ParseStream, Parser},
     parse_quote,
     punctuated::Pair,
-    AttrStyle, Attribute, Error, Item, Token,
+    spanned::Spanned,
+    AttrStyle, Attribute, Error, Item, ItemFn, Token,
 };
 
 mod fold;
@@ -17,8 +18,20 @@ mod hdl_bundle;
 mod hdl_enum;
 mod hdl_type_common;
 mod module;
-//mod value_derive_common;
-//mod value_derive_struct;
+
+pub(crate) trait CustomToken:
+    Copy
+    + Spanned
+    + ToTokens
+    + std::fmt::Debug
+    + Eq
+    + std::hash::Hash
+    + Default
+    + quote::IdentFragment
+    + Parse
+{
+    const IDENT_STR: &'static str;
+}
 
 mod kw {
     pub(crate) use syn::token::Extern as extern_;
@@ -38,6 +51,10 @@ mod kw {
             }
 
             crate::fold::no_op_fold!($kw);
+
+            impl crate::CustomToken for $kw {
+                const IDENT_STR: &'static str = stringify!($kw);
+            }
         };
     }
 
@@ -46,6 +63,7 @@ mod kw {
     custom_keyword!(custom_bounds);
     custom_keyword!(flip);
     custom_keyword!(hdl);
+    custom_keyword!(hdl_module);
     custom_keyword!(input);
     custom_keyword!(instance);
     custom_keyword!(m);
@@ -68,34 +86,34 @@ mod kw {
 type Pound = Token![#]; // work around https://github.com/rust-lang/rust/issues/50676
 
 #[derive(Clone, Debug)]
-pub(crate) struct HdlAttr<T> {
+pub(crate) struct HdlAttr<T, KW> {
     pub(crate) pound_token: Pound,
     pub(crate) style: AttrStyle,
     pub(crate) bracket_token: syn::token::Bracket,
-    pub(crate) hdl: kw::hdl,
+    pub(crate) kw: KW,
     pub(crate) paren_token: Option<syn::token::Paren>,
     pub(crate) body: T,
 }
 
 crate::fold::impl_fold! {
-    struct HdlAttr<T,> {
+    struct HdlAttr<T, KW,> {
         pound_token: Pound,
         style: AttrStyle,
         bracket_token: syn::token::Bracket,
-        hdl: kw::hdl,
+        kw: KW,
         paren_token: Option<syn::token::Paren>,
         body: T,
     }
 }
 
 #[allow(dead_code)]
-impl<T> HdlAttr<T> {
-    pub(crate) fn split_body(self) -> (HdlAttr<()>, T) {
+impl<T, KW> HdlAttr<T, KW> {
+    pub(crate) fn split_body(self) -> (HdlAttr<(), KW>, T) {
         let Self {
             pound_token,
             style,
             bracket_token,
-            hdl,
+            kw,
             paren_token,
             body,
         } = self;
@@ -104,19 +122,19 @@ impl<T> HdlAttr<T> {
                 pound_token,
                 style,
                 bracket_token,
-                hdl,
+                kw,
                 paren_token,
                 body: (),
             },
             body,
         )
     }
-    pub(crate) fn replace_body<T2>(self, body: T2) -> HdlAttr<T2> {
+    pub(crate) fn replace_body<T2>(self, body: T2) -> HdlAttr<T2, KW> {
         let Self {
             pound_token,
             style,
             bracket_token,
-            hdl,
+            kw,
             paren_token,
             body: _,
         } = self;
@@ -124,17 +142,20 @@ impl<T> HdlAttr<T> {
             pound_token,
             style,
             bracket_token,
-            hdl,
+            kw,
             paren_token,
             body,
         }
     }
-    pub(crate) fn as_ref(&self) -> HdlAttr<&T> {
+    pub(crate) fn as_ref(&self) -> HdlAttr<&T, KW>
+    where
+        KW: Clone,
+    {
         let Self {
             pound_token,
             style,
             bracket_token,
-            hdl,
+            ref kw,
             paren_token,
             ref body,
         } = *self;
@@ -142,17 +163,20 @@ impl<T> HdlAttr<T> {
             pound_token,
             style,
             bracket_token,
-            hdl,
+            kw: kw.clone(),
             paren_token,
             body,
         }
     }
-    pub(crate) fn try_map<R, E, F: FnOnce(T) -> Result<R, E>>(self, f: F) -> Result<HdlAttr<R>, E> {
+    pub(crate) fn try_map<R, E, F: FnOnce(T) -> Result<R, E>>(
+        self,
+        f: F,
+    ) -> Result<HdlAttr<R, KW>, E> {
         let Self {
             pound_token,
             style,
             bracket_token,
-            hdl,
+            kw,
             paren_token,
             body,
         } = self;
@@ -160,17 +184,17 @@ impl<T> HdlAttr<T> {
             pound_token,
             style,
             bracket_token,
-            hdl,
+            kw,
             paren_token,
             body: f(body)?,
         })
     }
-    pub(crate) fn map<R, F: FnOnce(T) -> R>(self, f: F) -> HdlAttr<R> {
+    pub(crate) fn map<R, F: FnOnce(T) -> R>(self, f: F) -> HdlAttr<R, KW> {
         let Self {
             pound_token,
             style,
             bracket_token,
-            hdl,
+            kw,
             paren_token,
             body,
         } = self;
@@ -178,7 +202,7 @@ impl<T> HdlAttr<T> {
             pound_token,
             style,
             bracket_token,
-            hdl,
+            kw,
             paren_token,
             body: f(body),
         }
@@ -186,31 +210,32 @@ impl<T> HdlAttr<T> {
     fn to_attr(&self) -> Attribute
     where
         T: ToTokens,
+        KW: ToTokens,
     {
         parse_quote! { #self }
     }
 }
 
-impl<T: Default> Default for HdlAttr<T> {
+impl<T: Default, KW: Default> Default for HdlAttr<T, KW> {
     fn default() -> Self {
         T::default().into()
     }
 }
 
-impl<T> From<T> for HdlAttr<T> {
+impl<T, KW: Default> From<T> for HdlAttr<T, KW> {
     fn from(body: T) -> Self {
         HdlAttr {
             pound_token: Default::default(),
             style: AttrStyle::Outer,
             bracket_token: Default::default(),
-            hdl: Default::default(),
+            kw: Default::default(),
             paren_token: Default::default(),
             body,
         }
     }
 }
 
-impl<T: ToTokens> ToTokens for HdlAttr<T> {
+impl<T: ToTokens, KW: ToTokens + Spanned> ToTokens for HdlAttr<T, KW> {
     fn to_tokens(&self, tokens: &mut TokenStream) {
         self.pound_token.to_tokens(tokens);
         match self.style {
@@ -218,7 +243,7 @@ impl<T: ToTokens> ToTokens for HdlAttr<T> {
             AttrStyle::Outer => {}
         };
         self.bracket_token.surround(tokens, |tokens| {
-            self.hdl.to_tokens(tokens);
+            self.kw.to_tokens(tokens);
             match self.paren_token {
                 Some(paren_token) => {
                     paren_token.surround(tokens, |tokens| self.body.to_tokens(tokens))
@@ -226,7 +251,7 @@ impl<T: ToTokens> ToTokens for HdlAttr<T> {
                 None => {
                     let body = self.body.to_token_stream();
                     if !body.is_empty() {
-                        syn::token::Paren(self.hdl.span)
+                        syn::token::Paren(self.kw.span())
                             .surround(tokens, |tokens| tokens.extend([body]));
                     }
                 }
@@ -235,18 +260,24 @@ impl<T: ToTokens> ToTokens for HdlAttr<T> {
     }
 }
 
-fn is_hdl_attr(attr: &Attribute) -> bool {
-    attr.path().is_ident("hdl")
+fn is_hdl_attr<KW: CustomToken>(attr: &Attribute) -> bool {
+    attr.path().is_ident(KW::IDENT_STR)
 }
 
-impl<T: Parse> HdlAttr<T> {
-    fn parse_and_take_attr(attrs: &mut Vec<Attribute>) -> syn::Result<Option<Self>> {
+impl<T: Parse, KW: Parse> HdlAttr<T, KW> {
+    fn parse_and_take_attr(attrs: &mut Vec<Attribute>) -> syn::Result<Option<Self>>
+    where
+        KW: ToTokens,
+    {
         let mut retval = None;
         let mut errors = Errors::new();
         attrs.retain(|attr| {
-            if is_hdl_attr(attr) {
+            if let Ok(kw) = syn::parse2::<KW>(attr.path().to_token_stream()) {
                 if retval.is_some() {
-                    errors.push(Error::new_spanned(attr, "more than one #[hdl] attribute"));
+                    errors.push(Error::new_spanned(
+                        attr,
+                        format_args!("more than one #[{}] attribute", kw.to_token_stream()),
+                    ));
                 }
                 errors.unwrap_or_default(Self::parse_attr(attr).map(|v| retval = Some(v)));
                 false
@@ -257,13 +288,19 @@ impl<T: Parse> HdlAttr<T> {
         errors.finish()?;
         Ok(retval)
     }
-    fn parse_and_leave_attr(attrs: &[Attribute]) -> syn::Result<Option<Self>> {
+    fn parse_and_leave_attr(attrs: &[Attribute]) -> syn::Result<Option<Self>>
+    where
+        KW: ToTokens,
+    {
         let mut retval = None;
         let mut errors = Errors::new();
         for attr in attrs {
-            if is_hdl_attr(attr) {
+            if let Ok(kw) = syn::parse2::<KW>(attr.path().to_token_stream()) {
                 if retval.is_some() {
-                    errors.push(Error::new_spanned(attr, "more than one #[hdl] attribute"));
+                    errors.push(Error::new_spanned(
+                        attr,
+                        format_args!("more than one #[{}] attribute", kw.to_token_stream()),
+                    ));
                 }
                 errors.unwrap_or_default(Self::parse_attr(attr).map(|v| retval = Some(v)));
             }
@@ -284,7 +321,7 @@ impl<T: Parse> HdlAttr<T> {
     ) -> syn::Result<Self> {
         let bracket_content;
         let bracket_token = bracketed!(bracket_content in input);
-        let hdl = bracket_content.parse()?;
+        let kw = bracket_content.parse()?;
         let paren_content;
         let body;
         let paren_token;
@@ -305,7 +342,7 @@ impl<T: Parse> HdlAttr<T> {
             pound_token,
             style,
             bracket_token,
-            hdl,
+            kw,
             paren_token,
             body,
         })
@@ -852,25 +889,31 @@ pub(crate) fn outline_generated(contents: TokenStream, prefix: &str) -> TokenStr
     }
 }
 
-pub fn hdl_module(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
-    let options = syn::parse2::<module::ConfigOptions>(attr)?;
-    let options = HdlAttr::from(options);
-    let func = syn::parse2::<module::ModuleFn>(quote! { #options #item })?;
+fn hdl_module_impl(item: ItemFn) -> syn::Result<TokenStream> {
+    let func = module::ModuleFn::parse_from_fn(item)?;
+    let options = func.config_options();
     let mut contents = func.generate();
-    if options.body.outline_generated.is_some() {
+    if options.outline_generated.is_some() {
         contents = outline_generated(contents, "module-");
     }
     Ok(contents)
 }
 
+pub fn hdl_module(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
+    let kw = kw::hdl_module::default();
+    hdl_module_impl(syn::parse2(quote! { #[#kw(#attr)] #item })?)
+}
+
 pub fn hdl_attr(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
-    let item = syn::parse2::<Item>(quote! { #[hdl(#attr)] #item })?;
+    let kw = kw::hdl::default();
+    let item = syn::parse2::<Item>(quote! { #[#kw(#attr)] #item })?;
     match item {
         Item::Enum(item) => hdl_enum::hdl_enum(item),
         Item::Struct(item) => hdl_bundle::hdl_bundle(item),
+        Item::Fn(item) => hdl_module_impl(item),
         _ => Err(syn::Error::new(
             Span::call_site(),
-            "top-level #[hdl] can only be used on structs or enums",
+            "top-level #[hdl] can only be used on structs, enums, or functions",
         )),
     }
 }
diff --git a/crates/fayalite-proc-macros-impl/src/module.rs b/crates/fayalite-proc-macros-impl/src/module.rs
index 0945abb..6363bb3 100644
--- a/crates/fayalite-proc-macros-impl/src/module.rs
+++ b/crates/fayalite-proc-macros-impl/src/module.rs
@@ -2,6 +2,7 @@
 // See Notices.txt for copyright information
 use crate::{
     hdl_type_common::{ParsedGenerics, SplitForImpl},
+    kw,
     module::transform_body::{HdlLet, HdlLetKindIO},
     options, Errors, HdlAttr, PairsIterExt,
 };
@@ -9,7 +10,6 @@ use proc_macro2::TokenStream;
 use quote::{format_ident, quote, quote_spanned, ToTokens};
 use std::collections::HashSet;
 use syn::{
-    parse::{Parse, ParseStream},
     parse_quote,
     visit::{visit_pat, Visit},
     Attribute, Block, ConstParam, Error, FnArg, GenericParam, Generics, Ident, ItemFn, ItemStruct,
@@ -59,9 +59,9 @@ impl Visit<'_> for CheckNameConflictsWithModuleBuilderVisitor<'_> {
 
 pub(crate) type ModuleIO = HdlLet<HdlLetKindIO>;
 
-pub(crate) struct ModuleFn {
+struct ModuleFnModule {
     attrs: Vec<Attribute>,
-    config_options: HdlAttr<ConfigOptions>,
+    config_options: HdlAttr<ConfigOptions, kw::hdl_module>,
     module_kind: ModuleKind,
     vis: Visibility,
     sig: Signature,
@@ -70,6 +70,26 @@ pub(crate) struct ModuleFn {
     the_struct: TokenStream,
 }
 
+enum ModuleFnImpl {
+    Module(ModuleFnModule),
+    Fn {
+        attrs: Vec<Attribute>,
+        config_options: HdlAttr<ConfigOptions, kw::hdl>,
+        vis: Visibility,
+        sig: Signature,
+        block: Box<Block>,
+    },
+}
+
+options! {
+    pub(crate) enum HdlOrHdlModule {
+        Hdl(hdl),
+        HdlModule(hdl_module),
+    }
+}
+
+pub(crate) struct ModuleFn(ModuleFnImpl);
+
 #[derive(Clone, Copy, PartialEq, Eq, Debug, Hash)]
 pub(crate) enum ModuleKind {
     Extern,
@@ -89,14 +109,25 @@ impl Visit<'_> for ContainsSkippedIdent<'_> {
     }
 }
 
-impl Parse for ModuleFn {
-    fn parse(input: ParseStream) -> syn::Result<Self> {
+impl ModuleFn {
+    pub(crate) fn config_options(&self) -> ConfigOptions {
+        let (ModuleFnImpl::Module(ModuleFnModule {
+            config_options: HdlAttr { body, .. },
+            ..
+        })
+        | ModuleFnImpl::Fn {
+            config_options: HdlAttr { body, .. },
+            ..
+        }) = &self.0;
+        body.clone()
+    }
+    pub(crate) fn parse_from_fn(item: ItemFn) -> syn::Result<Self> {
         let ItemFn {
             mut attrs,
             vis,
             mut sig,
             block,
-        } = input.parse()?;
+        } = item;
         let Signature {
             ref constness,
             ref asyncness,
@@ -111,43 +142,60 @@ impl Parse for ModuleFn {
             ref output,
         } = sig;
         let mut errors = Errors::new();
-        let config_options = errors
-            .unwrap_or_default(HdlAttr::parse_and_take_attr(&mut attrs))
-            .unwrap_or_default();
+        let Some(mut config_options) =
+            errors.unwrap_or_default(
+                HdlAttr::<ConfigOptions, HdlOrHdlModule>::parse_and_take_attr(&mut attrs),
+            )
+        else {
+            errors.error(sig.ident, "missing #[hdl] or #[hdl_module] attribute");
+            errors.finish()?;
+            unreachable!();
+        };
         let ConfigOptions {
             outline_generated: _,
             extern_,
         } = config_options.body;
-        let module_kind = match extern_ {
-            Some(_) => ModuleKind::Extern,
-            None => ModuleKind::Normal,
+        let module_kind = match (config_options.kw, extern_) {
+            (HdlOrHdlModule::Hdl(_), None) => None,
+            (HdlOrHdlModule::Hdl(_), Some(extern2)) => {
+                config_options.body.extern_ = None;
+                errors.error(
+                    extern2.0,
+                    "extern can only be used as #[hdl_module(extern)]",
+                );
+                None
+            }
+            (HdlOrHdlModule::HdlModule(_), None) => Some(ModuleKind::Normal),
+            (HdlOrHdlModule::HdlModule(_), Some(_)) => Some(ModuleKind::Extern),
         };
-        for fn_arg in inputs {
-            match fn_arg {
-                FnArg::Receiver(_) => {
-                    errors.push(syn::Error::new_spanned(fn_arg, "self not allowed here"));
-                }
-                FnArg::Typed(fn_arg) => {
-                    visit_pat(
-                        &mut CheckNameConflictsWithModuleBuilderVisitor {
-                            errors: &mut errors,
-                        },
-                        &fn_arg.pat,
-                    );
+        if let HdlOrHdlModule::HdlModule(_) = config_options.kw {
+            for fn_arg in inputs {
+                match fn_arg {
+                    FnArg::Receiver(_) => {
+                        errors.push(syn::Error::new_spanned(fn_arg, "self not allowed here"));
+                    }
+                    FnArg::Typed(fn_arg) => {
+                        visit_pat(
+                            &mut CheckNameConflictsWithModuleBuilderVisitor {
+                                errors: &mut errors,
+                            },
+                            &fn_arg.pat,
+                        );
+                    }
                 }
             }
-        }
-        if let Some(constness) = constness {
-            errors.push(syn::Error::new_spanned(constness, "const not allowed here"));
-        }
-        if let Some(asyncness) = asyncness {
-            errors.push(syn::Error::new_spanned(asyncness, "async not allowed here"));
-        }
-        if let Some(unsafety) = unsafety {
-            errors.push(syn::Error::new_spanned(unsafety, "unsafe not allowed here"));
-        }
-        if let Some(abi) = abi {
-            errors.push(syn::Error::new_spanned(abi, "extern not allowed here"));
+            if let Some(constness) = constness {
+                errors.push(syn::Error::new_spanned(constness, "const not allowed here"));
+            }
+            if let Some(asyncness) = asyncness {
+                errors.push(syn::Error::new_spanned(asyncness, "async not allowed here"));
+            }
+            if let Some(unsafety) = unsafety {
+                errors.push(syn::Error::new_spanned(unsafety, "unsafe not allowed here"));
+            }
+            if let Some(abi) = abi {
+                errors.push(syn::Error::new_spanned(abi, "extern not allowed here"));
+            }
         }
         let mut skipped_idents = HashSet::new();
         let struct_generic_params = generics
@@ -155,14 +203,17 @@ impl Parse for ModuleFn {
             .pairs_mut()
             .filter_map_pair_value_mut(|v| match v {
                 GenericParam::Lifetime(LifetimeParam { attrs, .. }) => {
-                    errors
-                        .unwrap_or_default(HdlAttr::<crate::kw::skip>::parse_and_take_attr(attrs));
+                    errors.unwrap_or_default(
+                        HdlAttr::<crate::kw::skip, kw::hdl>::parse_and_take_attr(attrs),
+                    );
                     None
                 }
                 GenericParam::Type(TypeParam { attrs, ident, .. })
                 | GenericParam::Const(ConstParam { attrs, ident, .. }) => {
                     if errors
-                        .unwrap_or_default(HdlAttr::<crate::kw::skip>::parse_and_take_attr(attrs))
+                        .unwrap_or_default(
+                            HdlAttr::<crate::kw::skip, kw::hdl>::parse_and_take_attr(attrs),
+                        )
                         .is_some()
                     {
                         skipped_idents.insert(ident.clone());
@@ -176,6 +227,7 @@ impl Parse for ModuleFn {
         let struct_where_clause = generics
             .where_clause
             .as_mut()
+            .filter(|_| matches!(config_options.kw, HdlOrHdlModule::HdlModule(_)))
             .map(|where_clause| WhereClause {
                 where_token: where_clause.where_token,
                 predicates: where_clause
@@ -198,22 +250,26 @@ impl Parse for ModuleFn {
                     })
                     .collect(),
             });
-        let struct_generics = Generics {
-            lt_token: generics.lt_token,
-            params: struct_generic_params,
-            gt_token: generics.gt_token,
-            where_clause: struct_where_clause,
+        let struct_generics = if let HdlOrHdlModule::HdlModule(_) = config_options.kw {
+            let mut struct_generics = Generics {
+                lt_token: generics.lt_token,
+                params: struct_generic_params,
+                gt_token: generics.gt_token,
+                where_clause: struct_where_clause,
+            };
+            if let Some(variadic) = variadic {
+                errors.push(syn::Error::new_spanned(variadic, "... not allowed here"));
+            }
+            if !matches!(output, ReturnType::Default) {
+                errors.push(syn::Error::new_spanned(
+                    output,
+                    "return type not allowed here",
+                ));
+            }
+            errors.ok(ParsedGenerics::parse(&mut struct_generics))
+        } else {
+            Some(ParsedGenerics::default())
         };
-        if let Some(variadic) = variadic {
-            errors.push(syn::Error::new_spanned(variadic, "... not allowed here"));
-        }
-        if !matches!(output, ReturnType::Default) {
-            errors.push(syn::Error::new_spanned(
-                output,
-                "return type not allowed here",
-            ));
-        }
-        let struct_generics = errors.ok(ParsedGenerics::parse(&mut { struct_generics }));
         let body_results = struct_generics.as_ref().and_then(|struct_generics| {
             errors.ok(transform_body::transform_body(
                 module_kind,
@@ -224,6 +280,47 @@ impl Parse for ModuleFn {
         errors.finish()?;
         let struct_generics = struct_generics.unwrap();
         let (block, io) = body_results.unwrap();
+        let config_options = match config_options {
+            HdlAttr {
+                pound_token,
+                style,
+                bracket_token,
+                kw: HdlOrHdlModule::Hdl((kw,)),
+                paren_token,
+                body,
+            } => {
+                debug_assert!(io.is_empty());
+                return Ok(Self(ModuleFnImpl::Fn {
+                    attrs,
+                    config_options: HdlAttr {
+                        pound_token,
+                        style,
+                        bracket_token,
+                        kw,
+                        paren_token,
+                        body,
+                    },
+                    vis,
+                    sig,
+                    block,
+                }));
+            }
+            HdlAttr {
+                pound_token,
+                style,
+                bracket_token,
+                kw: HdlOrHdlModule::HdlModule((kw,)),
+                paren_token,
+                body,
+            } => HdlAttr {
+                pound_token,
+                style,
+                bracket_token,
+                kw,
+                paren_token,
+                body,
+            },
+        };
         let (_struct_impl_generics, _struct_type_generics, struct_where_clause) =
             struct_generics.split_for_impl();
         let struct_where_clause: Option<WhereClause> = parse_quote! { #struct_where_clause };
@@ -259,22 +356,22 @@ impl Parse for ModuleFn {
             }
         };
         let the_struct = crate::hdl_bundle::hdl_bundle(the_struct)?;
-        Ok(Self {
+        Ok(Self(ModuleFnImpl::Module(ModuleFnModule {
             attrs,
             config_options,
-            module_kind,
+            module_kind: module_kind.unwrap(),
             vis,
             sig,
             block,
             struct_generics,
             the_struct,
-        })
+        })))
     }
 }
 
 impl ModuleFn {
     pub(crate) fn generate(self) -> TokenStream {
-        let Self {
+        let ModuleFnModule {
             attrs,
             config_options,
             module_kind,
@@ -283,7 +380,28 @@ impl ModuleFn {
             block,
             struct_generics,
             the_struct,
-        } = self;
+        } = match self.0 {
+            ModuleFnImpl::Module(v) => v,
+            ModuleFnImpl::Fn {
+                attrs,
+                config_options,
+                vis,
+                sig,
+                block,
+            } => {
+                let ConfigOptions {
+                    outline_generated: _,
+                    extern_: _,
+                } = config_options.body;
+                return ItemFn {
+                    attrs,
+                    vis,
+                    sig,
+                    block,
+                }
+                .into_token_stream();
+            }
+        };
         let ConfigOptions {
             outline_generated: _,
             extern_: _,
diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
index 76e1d69..d4d92b2 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
@@ -925,7 +925,7 @@ with_debug_clone_and_fold! {
     #[allow(dead_code)]
     pub(crate) struct HdlLet<Kind = HdlLetKind> {
         pub(crate) attrs: Vec<Attribute>,
-        pub(crate) hdl_attr: HdlAttr<Nothing>,
+        pub(crate) hdl_attr: HdlAttr<Nothing, kw::hdl>,
         pub(crate) let_token: Token![let],
         pub(crate) mut_token: Option<Token![mut]>,
         pub(crate) name: Ident,
@@ -1112,7 +1112,7 @@ impl<T: ToString> ToTokens for ImplicitName<T> {
 }
 
 struct Visitor<'a> {
-    module_kind: ModuleKind,
+    module_kind: Option<ModuleKind>,
     errors: Errors,
     io: Vec<ModuleIO>,
     block_depth: usize,
@@ -1120,22 +1120,33 @@ struct Visitor<'a> {
 }
 
 impl Visitor<'_> {
-    fn take_hdl_attr<T: Parse>(&mut self, attrs: &mut Vec<Attribute>) -> Option<HdlAttr<T>> {
+    fn take_hdl_attr<T: Parse>(
+        &mut self,
+        attrs: &mut Vec<Attribute>,
+    ) -> Option<HdlAttr<T, kw::hdl>> {
         self.errors.unwrap_or(
             HdlAttr::parse_and_take_attr(attrs),
             Some(syn::parse2::<T>(quote! {}).unwrap().into()),
         )
     }
-    fn require_normal_module(&mut self, spanned: impl ToTokens) {
+    fn require_normal_module_or_fn(&mut self, spanned: impl ToTokens) {
         match self.module_kind {
-            ModuleKind::Extern => {
+            Some(ModuleKind::Extern) => {
                 self.errors
                     .error(spanned, "not allowed in #[hdl_module(extern)]");
             }
-            ModuleKind::Normal => {}
+            Some(ModuleKind::Normal) | None => {}
         }
     }
-    fn process_hdl_if(&mut self, hdl_attr: HdlAttr<Nothing>, expr_if: ExprIf) -> Expr {
+    fn require_module(&mut self, spanned: impl ToTokens) {
+        match self.module_kind {
+            None => {
+                self.errors.error(spanned, "not allowed in #[hdl] fn");
+            }
+            Some(_) => {}
+        }
+    }
+    fn process_hdl_if(&mut self, hdl_attr: HdlAttr<Nothing, kw::hdl>, expr_if: ExprIf) -> Expr {
         let ExprIf {
             attrs,
             if_token,
@@ -1143,7 +1154,7 @@ impl Visitor<'_> {
             then_branch,
             else_branch,
         } = expr_if;
-        self.require_normal_module(if_token);
+        self.require_normal_module_or_fn(if_token);
         let else_expr = else_branch.unzip().1.map(|else_expr| match *else_expr {
             Expr::If(expr_if) => self.process_hdl_if(hdl_attr.clone(), expr_if),
             expr => expr,
@@ -1208,11 +1219,12 @@ impl Visitor<'_> {
             .to_tokens(expr);
         });
         let mut attrs = hdl_let.attrs.clone();
+        self.require_module(kind);
         match self.module_kind {
-            ModuleKind::Extern => attrs.push(parse_quote_spanned! {hdl_let.let_token.span=>
+            Some(ModuleKind::Extern) => attrs.push(parse_quote_spanned! {hdl_let.let_token.span=>
                 #[allow(unused_variables)]
             }),
-            ModuleKind::Normal => {}
+            Some(ModuleKind::Normal) | None => {}
         }
         let let_stmt = Local {
             attrs,
@@ -1249,7 +1261,7 @@ impl Visitor<'_> {
                 },
             semi_token,
         } = hdl_let;
-        self.require_normal_module(instance);
+        self.require_normal_module_or_fn(instance);
         let mut expr = instance.to_token_stream();
         paren.surround(&mut expr, |expr| {
             let name_str = ImplicitName {
@@ -1276,7 +1288,7 @@ impl Visitor<'_> {
     fn process_hdl_let_reg_builder(&mut self, hdl_let: HdlLet<HdlLetKindRegBuilder>) -> Local {
         let name = &hdl_let.name;
         let reg_builder = hdl_let.kind.reg_builder;
-        self.require_normal_module(reg_builder);
+        self.require_normal_module_or_fn(reg_builder);
         let mut expr = reg_builder.to_token_stream();
         hdl_let.kind.reg_builder_paren.surround(&mut expr, |expr| {
             let name_str = ImplicitName {
@@ -1327,7 +1339,7 @@ impl Visitor<'_> {
     fn process_hdl_let_wire(&mut self, hdl_let: HdlLet<HdlLetKindWire>) -> Local {
         let name = &hdl_let.name;
         let wire = hdl_let.kind.wire;
-        self.require_normal_module(wire);
+        self.require_normal_module_or_fn(wire);
         let ty_expr = unwrap_or_static_type(hdl_let.kind.ty_expr.as_ref(), wire.span());
         let mut expr = wire.to_token_stream();
         hdl_let.kind.paren.surround(&mut expr, |expr| {
@@ -1361,7 +1373,7 @@ impl Visitor<'_> {
         let name = &hdl_let.name;
         let memory_fn = hdl_let.kind.memory_fn;
         let memory_fn_name = memory_fn.name();
-        self.require_normal_module(memory_fn_name);
+        self.require_normal_module_or_fn(memory_fn_name);
         let mut expr = memory_fn_name.to_token_stream();
         let (paren, arg) = match memory_fn {
             MemoryFn::Memory {
@@ -1543,7 +1555,7 @@ impl Fold for Visitor<'_> {
     }
 
     fn fold_attribute(&mut self, attr: Attribute) -> Attribute {
-        if is_hdl_attr(&attr) {
+        if is_hdl_attr::<kw::hdl>(&attr) {
             self.errors
                 .error(&attr, "#[hdl] attribute not supported here");
         }
@@ -1610,8 +1622,9 @@ impl Fold for Visitor<'_> {
     fn fold_local(&mut self, let_stmt: Local) -> Local {
         match self
             .errors
-            .ok(HdlAttr::<Nothing>::parse_and_leave_attr(&let_stmt.attrs))
-        {
+            .ok(HdlAttr::<Nothing, kw::hdl>::parse_and_leave_attr(
+                &let_stmt.attrs,
+            )) {
             None => return empty_let(),
             Some(None) => return fold_local(self, let_stmt),
             Some(Some(HdlAttr { .. })) => {}
@@ -1646,7 +1659,7 @@ impl Fold for Visitor<'_> {
 }
 
 pub(crate) fn transform_body(
-    module_kind: ModuleKind,
+    module_kind: Option<ModuleKind>,
     mut body: Box<Block>,
     parsed_generics: &ParsedGenerics,
 ) -> syn::Result<(Box<Block>, Vec<ModuleIO>)> {
diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs
index 00ee706..b5a0ad3 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-use crate::{module::transform_body::Visitor, HdlAttr};
+use crate::{kw, module::transform_body::Visitor, HdlAttr};
 use quote::{format_ident, quote_spanned};
 use syn::{
     parse::Nothing, parse_quote, parse_quote_spanned, spanned::Spanned, Expr, ExprArray, ExprPath,
@@ -10,10 +10,10 @@ use syn::{
 impl Visitor<'_> {
     pub(crate) fn process_hdl_array(
         &mut self,
-        hdl_attr: HdlAttr<Nothing>,
+        hdl_attr: HdlAttr<Nothing, kw::hdl>,
         mut expr_array: ExprArray,
     ) -> Expr {
-        self.require_normal_module(hdl_attr);
+        self.require_normal_module_or_fn(hdl_attr);
         for elem in &mut expr_array.elems {
             *elem = parse_quote_spanned! {elem.span()=>
                 ::fayalite::expr::ToExpr::to_expr(&(#elem))
@@ -23,10 +23,10 @@ impl Visitor<'_> {
     }
     pub(crate) fn process_hdl_repeat(
         &mut self,
-        hdl_attr: HdlAttr<Nothing>,
+        hdl_attr: HdlAttr<Nothing, kw::hdl>,
         mut expr_repeat: ExprRepeat,
     ) -> Expr {
-        self.require_normal_module(hdl_attr);
+        self.require_normal_module_or_fn(hdl_attr);
         let repeated_value = &expr_repeat.expr;
         *expr_repeat.expr = parse_quote_spanned! {repeated_value.span()=>
             ::fayalite::expr::ToExpr::to_expr(&(#repeated_value))
@@ -35,10 +35,10 @@ impl Visitor<'_> {
     }
     pub(crate) fn process_hdl_struct(
         &mut self,
-        hdl_attr: HdlAttr<Nothing>,
+        hdl_attr: HdlAttr<Nothing, kw::hdl>,
         expr_struct: ExprStruct,
     ) -> Expr {
-        self.require_normal_module(&hdl_attr);
+        self.require_normal_module_or_fn(&hdl_attr);
         let name_span = expr_struct.path.segments.last().unwrap().ident.span();
         let builder_ident = format_ident!("__builder", span = name_span);
         let empty_builder = if expr_struct.qself.is_some()
@@ -91,10 +91,10 @@ impl Visitor<'_> {
     }
     pub(crate) fn process_hdl_tuple(
         &mut self,
-        hdl_attr: HdlAttr<Nothing>,
+        hdl_attr: HdlAttr<Nothing, kw::hdl>,
         expr_tuple: ExprTuple,
     ) -> Expr {
-        self.require_normal_module(hdl_attr);
+        self.require_normal_module_or_fn(hdl_attr);
         parse_quote_spanned! {expr_tuple.span()=>
             ::fayalite::expr::ToExpr::to_expr(&#expr_tuple)
         }
diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
index ae21a73..1d53104 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
@@ -2,6 +2,7 @@
 // See Notices.txt for copyright information
 use crate::{
     fold::{impl_fold, DoFold},
+    kw,
     module::transform_body::{with_debug_clone_and_fold, Visitor},
     Errors, HdlAttr, PairsIterExt,
 };
@@ -749,7 +750,7 @@ struct HdlMatchParseState<'a> {
 impl Visitor<'_> {
     pub(crate) fn process_hdl_match(
         &mut self,
-        _hdl_attr: HdlAttr<Nothing>,
+        _hdl_attr: HdlAttr<Nothing, kw::hdl>,
         expr_match: ExprMatch,
     ) -> Expr {
         let span = expr_match.match_token.span();
@@ -761,7 +762,7 @@ impl Visitor<'_> {
             brace_token: _,
             arms,
         } = expr_match;
-        self.require_normal_module(match_token);
+        self.require_normal_module_or_fn(match_token);
         let mut state = HdlMatchParseState {
             match_span: span,
             errors: &mut self.errors,
diff --git a/crates/fayalite/tests/ui/hdl_types.stderr b/crates/fayalite/tests/ui/hdl_types.stderr
index e01b04f..a65d796 100644
--- a/crates/fayalite/tests/ui/hdl_types.stderr
+++ b/crates/fayalite/tests/ui/hdl_types.stderr
@@ -1,4 +1,4 @@
-error: top-level #[hdl] can only be used on structs or enums
+error: top-level #[hdl] can only be used on structs, enums, or functions
  --> tests/ui/hdl_types.rs:5:1
   |
 5 | #[hdl]

From df55a514e442d07e1ef76275bcf481146381989d Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 20 Sep 2024 18:46:56 -0700
Subject: [PATCH 002/190] add support for incomplete_wire -- a wire that you
 can supply the type of later

---
 crates/fayalite-proc-macros-impl/src/lib.rs   |  1 +
 .../src/module/transform_body.rs              | 83 +++++++++++++++++
 crates/fayalite/src/module.rs                 | 91 ++++++++++++++++++-
 crates/fayalite/src/prelude.rs                |  4 +-
 crates/fayalite/src/wire.rs                   | 60 +++++++++++-
 5 files changed, 231 insertions(+), 8 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/lib.rs b/crates/fayalite-proc-macros-impl/src/lib.rs
index 3ec00bf..903983f 100644
--- a/crates/fayalite-proc-macros-impl/src/lib.rs
+++ b/crates/fayalite-proc-macros-impl/src/lib.rs
@@ -65,6 +65,7 @@ mod kw {
     custom_keyword!(hdl);
     custom_keyword!(hdl_module);
     custom_keyword!(input);
+    custom_keyword!(incomplete_wire);
     custom_keyword!(instance);
     custom_keyword!(m);
     custom_keyword!(memory);
diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
index d4d92b2..1f9565a 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
@@ -34,6 +34,7 @@ options! {
         Instance(instance),
         RegBuilder(reg_builder),
         Wire(wire),
+        IncompleteWire(incomplete_wire),
         Memory(memory),
         MemoryArray(memory_array),
         MemoryWithInit(memory_with_init),
@@ -533,6 +534,41 @@ impl HdlLetKindToTokens for HdlLetKindWire {
     }
 }
 
+options! {
+    pub(crate) enum LetFnKindIncomplete {
+        IncompleteWire(incomplete_wire),
+    }
+}
+
+#[derive(Clone, Debug)]
+pub(crate) struct HdlLetKindIncomplete {
+    pub(crate) kind: LetFnKindIncomplete,
+    pub(crate) paren: Paren,
+}
+
+impl ParseTypes<Self> for HdlLetKindIncomplete {
+    fn parse_types(input: &mut Self, _parser: &mut TypesParser<'_>) -> Result<Self, ParseFailed> {
+        Ok(input.clone())
+    }
+}
+
+impl_fold! {
+    struct HdlLetKindIncomplete<> {
+        kind: LetFnKindIncomplete,
+        paren: Paren,
+    }
+}
+
+impl HdlLetKindToTokens for HdlLetKindIncomplete {
+    fn ty_to_tokens(&self, _tokens: &mut TokenStream) {}
+
+    fn expr_to_tokens(&self, tokens: &mut TokenStream) {
+        let Self { kind, paren } = self;
+        kind.to_tokens(tokens);
+        paren.surround(tokens, |_| {});
+    }
+}
+
 options! {
     pub(crate) enum MemoryFnName {
         Memory(memory),
@@ -697,6 +733,7 @@ impl HdlLetKindMemory {
 #[derive(Clone, Debug)]
 pub(crate) enum HdlLetKind<IOType = ParsedType> {
     IO(HdlLetKindIO<ModuleIOKind, IOType>),
+    Incomplete(HdlLetKindIncomplete),
     Instance(HdlLetKindInstance),
     RegBuilder(HdlLetKindRegBuilder),
     Wire(HdlLetKindWire),
@@ -706,6 +743,7 @@ pub(crate) enum HdlLetKind<IOType = ParsedType> {
 impl_fold! {
     enum HdlLetKind<IOType,> {
         IO(HdlLetKindIO<ModuleIOKind, IOType>),
+        Incomplete(HdlLetKindIncomplete),
         Instance(HdlLetKindInstance),
         RegBuilder(HdlLetKindRegBuilder),
         Wire(HdlLetKindWire),
@@ -720,6 +758,9 @@ impl<T: ParseTypes<I>, I> ParseTypes<HdlLetKind<I>> for HdlLetKind<T> {
     ) -> Result<Self, ParseFailed> {
         match input {
             HdlLetKind::IO(input) => ParseTypes::parse_types(input, parser).map(HdlLetKind::IO),
+            HdlLetKind::Incomplete(input) => {
+                ParseTypes::parse_types(input, parser).map(HdlLetKind::Incomplete)
+            }
             HdlLetKind::Instance(input) => {
                 ParseTypes::parse_types(input, parser).map(HdlLetKind::Instance)
             }
@@ -871,6 +912,20 @@ impl HdlLetKindParse for HdlLetKind<Type> {
                     ty_expr: paren_contents.call(parse_optional_fn_arg)?,
                 }))
             }
+            LetFnKind::IncompleteWire(incomplete_wire) => {
+                if let Some(parsed_ty) = parsed_ty {
+                    return Err(Error::new_spanned(
+                        parsed_ty.1,
+                        "type annotation not allowed for incomplete_wire",
+                    ));
+                }
+                check_empty_m_dot(m_dot, kind)?;
+                let _paren_contents;
+                Ok(Self::Incomplete(HdlLetKindIncomplete {
+                    kind: LetFnKindIncomplete::IncompleteWire(incomplete_wire),
+                    paren: parenthesized!(_paren_contents in input),
+                }))
+            }
             LetFnKind::Memory(fn_name) => HdlLetKindMemory::rest_of_parse(
                 input,
                 parsed_ty,
@@ -903,6 +958,7 @@ impl HdlLetKindToTokens for HdlLetKind {
     fn ty_to_tokens(&self, tokens: &mut TokenStream) {
         match self {
             HdlLetKind::IO(v) => v.ty_to_tokens(tokens),
+            HdlLetKind::Incomplete(v) => v.ty_to_tokens(tokens),
             HdlLetKind::Instance(v) => v.ty_to_tokens(tokens),
             HdlLetKind::RegBuilder(v) => v.ty_to_tokens(tokens),
             HdlLetKind::Wire(v) => v.ty_to_tokens(tokens),
@@ -913,6 +969,7 @@ impl HdlLetKindToTokens for HdlLetKind {
     fn expr_to_tokens(&self, tokens: &mut TokenStream) {
         match self {
             HdlLetKind::IO(v) => v.expr_to_tokens(tokens),
+            HdlLetKind::Incomplete(v) => v.expr_to_tokens(tokens),
             HdlLetKind::Instance(v) => v.expr_to_tokens(tokens),
             HdlLetKind::RegBuilder(v) => v.expr_to_tokens(tokens),
             HdlLetKind::Wire(v) => v.expr_to_tokens(tokens),
@@ -1369,6 +1426,31 @@ impl Visitor<'_> {
             semi_token: hdl_let.semi_token,
         }
     }
+    fn process_hdl_let_incomplete(&mut self, hdl_let: HdlLet<HdlLetKindIncomplete>) -> Local {
+        let name = &hdl_let.name;
+        let kind = hdl_let.kind.kind;
+        self.require_normal_module_or_fn(kind);
+        let mut expr = kind.to_token_stream();
+        hdl_let.kind.paren.surround(&mut expr, |expr| {
+            ImplicitName {
+                name,
+                span: name.span(),
+            }
+            .to_tokens(expr);
+        });
+        let mut_token = &hdl_let.mut_token;
+        Local {
+            attrs: hdl_let.attrs.clone(),
+            let_token: hdl_let.let_token,
+            pat: parse_quote! { #mut_token #name },
+            init: Some(LocalInit {
+                eq_token: hdl_let.eq_token,
+                expr: parse_quote! { #expr },
+                diverge: None,
+            }),
+            semi_token: hdl_let.semi_token,
+        }
+    }
     fn process_hdl_let_memory(&mut self, hdl_let: HdlLet<HdlLetKindMemory>) -> Local {
         let name = &hdl_let.name;
         let memory_fn = hdl_let.kind.memory_fn;
@@ -1438,6 +1520,7 @@ impl Visitor<'_> {
         }
         the_match! {
             IO => process_hdl_let_io,
+            Incomplete => process_hdl_let_incomplete,
             Instance => process_hdl_let_instance,
             RegBuilder => process_hdl_let_reg_builder,
             Wire => process_hdl_let_wire,
diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index cb57758..3a17343 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -22,7 +22,7 @@ use crate::{
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
     util::ScopedRef,
-    wire::Wire,
+    wire::{IncompleteWire, Wire},
 };
 use hashbrown::{hash_map::Entry, HashMap, HashSet};
 use num_bigint::BigInt;
@@ -118,9 +118,35 @@ pub trait BlockRef: 'static + Send + Sync + Copy + Eq + Hash + fmt::Debug {}
 
 impl BlockRef for BlockId {}
 
+pub(crate) enum IncompleteDeclaration {
+    Incomplete {
+        name: ScopedNameId,
+        source_location: SourceLocation,
+    },
+    Complete(StmtDeclaration<ModuleBuilding>),
+    Taken,
+}
+
+impl fmt::Debug for IncompleteDeclaration {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self {
+            Self::Incomplete {
+                name,
+                source_location: _,
+            } => f
+                .debug_struct("Incomplete")
+                .field("name", name)
+                .finish_non_exhaustive(),
+            Self::Complete(v) => v.fmt(f),
+            Self::Taken => f.write_str("Taken"),
+        }
+    }
+}
+
 #[derive(Debug)]
 pub struct BuilderBlock {
     memories: Vec<Rc<RefCell<MemBuilderTarget>>>,
+    incomplete_declarations: Vec<Rc<RefCell<IncompleteDeclaration>>>,
     stmts: Vec<Stmt<ModuleBuilding>>,
 }
 
@@ -831,13 +857,34 @@ impl From<NormalModuleBody<ModuleBuilding>> for NormalModuleBody {
             annotations_map: &mut HashMap<StmtDeclaration<ModuleBuilding>, Vec<TargetedAnnotation>>,
             block_id: BlockId,
         ) -> Block {
-            let BuilderBlock { memories, stmts } = &mut blocks[block_id.as_usize()];
+            let BuilderBlock {
+                memories,
+                incomplete_declarations,
+                stmts,
+            } = &mut blocks[block_id.as_usize()];
             let memories = Interned::from_iter(
                 memories
                     .drain(..)
                     .filter_map(|memory| memory.borrow().make_memory()),
             );
-            let stmts = std::mem::take(stmts);
+            let stmts = Vec::from_iter(
+                incomplete_declarations
+                    .drain(..)
+                    .map(|decl| {
+                        match std::mem::replace(
+                            &mut *decl.borrow_mut(),
+                            IncompleteDeclaration::Taken,
+                        ) {
+                            IncompleteDeclaration::Incomplete {
+                                name,
+                                source_location,
+                            } => panic!("incomplete declaration: {name:?}\nat: {source_location}"),
+                            IncompleteDeclaration::Complete(v) => Stmt::Declaration(v),
+                            IncompleteDeclaration::Taken => unreachable!(),
+                        }
+                    })
+                    .chain(stmts.drain(..)),
+            );
             let stmts = Interned::from_iter(stmts.into_iter().map(|stmt| {
                 match stmt {
                     Stmt::Connect(stmt) => stmt.into(),
@@ -908,6 +955,7 @@ impl NormalModuleBody<ModuleBuilding> {
         let index = self.body.blocks.len();
         self.body.blocks.push(BuilderBlock {
             memories: vec![],
+            incomplete_declarations: vec![],
             stmts: vec![],
         });
         BlockId(index)
@@ -1943,6 +1991,7 @@ impl ModuleBuilder {
                 body: BuilderModuleBody {
                     blocks: vec![BuilderBlock {
                         memories: vec![],
+                        incomplete_declarations: vec![],
                         stmts: vec![],
                     }],
                     annotations_map: HashMap::new(),
@@ -2156,6 +2205,42 @@ pub fn wire<T: Type>(implicit_name: ImplicitName<'_>, ty: T) -> Expr<T> {
     wire_with_loc(implicit_name.0, SourceLocation::caller(), ty)
 }
 
+#[track_caller]
+fn incomplete_declaration(
+    name: &str,
+    source_location: SourceLocation,
+) -> Rc<RefCell<IncompleteDeclaration>> {
+    ModuleBuilder::with(|m| {
+        let mut impl_ = m.impl_.borrow_mut();
+        let scoped_name = ScopedNameId(m.name, impl_.name_id_gen.gen(name.intern()));
+        drop(impl_);
+        let retval = Rc::new(RefCell::new(IncompleteDeclaration::Incomplete {
+            name: scoped_name,
+            source_location,
+        }));
+        let mut impl_ = m.impl_.borrow_mut();
+        impl_
+            .body
+            .builder_normal_body()
+            .block(m.block_stack.top())
+            .incomplete_declarations
+            .push(retval.clone());
+        retval
+    })
+}
+
+#[track_caller]
+pub fn incomplete_wire_with_loc(name: &str, source_location: SourceLocation) -> IncompleteWire {
+    IncompleteWire {
+        declaration: incomplete_declaration(name, source_location),
+    }
+}
+
+#[track_caller]
+pub fn incomplete_wire(implicit_name: ImplicitName<'_>) -> IncompleteWire {
+    incomplete_wire_with_loc(implicit_name.0, SourceLocation::caller())
+}
+
 #[track_caller]
 pub fn reg_builder_with_loc(name: &str, source_location: SourceLocation) -> RegBuilder<(), (), ()> {
     ModuleBuilder::with(|m| {
diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs
index 14c3aa7..bedece2 100644
--- a/crates/fayalite/src/prelude.rs
+++ b/crates/fayalite/src/prelude.rs
@@ -9,8 +9,8 @@ pub use crate::{
     int::{Bool, DynSize, IntCmp, KnownSize, SInt, SIntType, Size, UInt, UIntType},
     memory::{Mem, MemBuilder, ReadUnderWrite},
     module::{
-        annotate, connect, connect_any, instance, memory, memory_array, memory_with_init,
-        reg_builder, wire, Instance, Module, ModuleBuilder,
+        annotate, connect, connect_any, incomplete_wire, instance, memory, memory_array,
+        memory_with_init, reg_builder, wire, Instance, Module, ModuleBuilder,
     },
     reg::Reg,
     reset::{AsyncReset, Reset, SyncReset, ToAsyncReset, ToReset, ToSyncReset},
diff --git a/crates/fayalite/src/wire.rs b/crates/fayalite/src/wire.rs
index b84d6ae..85ab342 100644
--- a/crates/fayalite/src/wire.rs
+++ b/crates/fayalite/src/wire.rs
@@ -1,13 +1,13 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use crate::{
-    expr::Flow,
+    expr::{Expr, Flow, ToExpr},
     intern::Interned,
-    module::{NameId, ScopedNameId},
+    module::{IncompleteDeclaration, NameId, ScopedNameId, StmtDeclaration, StmtWire},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
 };
-use std::fmt;
+use std::{cell::RefCell, fmt, rc::Rc};
 
 #[derive(Copy, Clone, Eq, PartialEq, Hash)]
 pub struct Wire<T: Type> {
@@ -76,3 +76,57 @@ impl<T: Type> Wire<T> {
         true
     }
 }
+
+#[derive(Clone)]
+pub struct IncompleteWire {
+    pub(crate) declaration: Rc<RefCell<IncompleteDeclaration>>,
+}
+
+impl IncompleteWire {
+    #[track_caller]
+    pub fn complete<T: Type>(&mut self, ty: T) -> Expr<T> {
+        let canonical_type = ty.canonical();
+        let mut declaration = self.declaration.borrow_mut();
+        if let IncompleteDeclaration::Incomplete {
+            name,
+            source_location,
+        } = *declaration
+        {
+            *declaration = IncompleteDeclaration::Complete(
+                StmtWire {
+                    annotations: (),
+                    wire: Wire {
+                        name,
+                        source_location,
+                        ty: canonical_type,
+                    },
+                }
+                .into(),
+            );
+        }
+        match *declaration {
+            IncompleteDeclaration::Complete(StmtDeclaration::Wire(StmtWire {
+                wire:
+                    Wire {
+                        name,
+                        source_location,
+                        ty: wire_ty,
+                    },
+                ..
+            })) => {
+                drop(declaration);
+                assert_eq!(wire_ty, canonical_type, "type mismatch");
+                Wire {
+                    name,
+                    source_location,
+                    ty,
+                }
+                .to_expr()
+            }
+            IncompleteDeclaration::Taken => panic!("can't use wire outside of containing module"),
+            IncompleteDeclaration::Complete(_) | IncompleteDeclaration::Incomplete { .. } => {
+                unreachable!()
+            }
+        }
+    }
+}

From ff269e5def6395f4533180ceea51083d76801c07 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 20 Sep 2024 18:49:12 -0700
Subject: [PATCH 003/190] add utility functions on HdlOption, inspired by
 Option's API

---
 crates/fayalite/src/enum_.rs | 311 ++++++++++++++++++++++++++++++++++-
 1 file changed, 308 insertions(+), 3 deletions(-)

diff --git a/crates/fayalite/src/enum_.rs b/crates/fayalite/src/enum_.rs
index 384414c..13724ef 100644
--- a/crates/fayalite/src/enum_.rs
+++ b/crates/fayalite/src/enum_.rs
@@ -7,14 +7,14 @@ use crate::{
     int::Bool,
     intern::{Intern, Interned},
     module::{
-        enum_match_variants_helper, EnumMatchVariantAndInactiveScopeImpl,
-        EnumMatchVariantsIterImpl, Scope,
+        connect, enum_match_variants_helper, incomplete_wire, wire,
+        EnumMatchVariantAndInactiveScopeImpl, EnumMatchVariantsIterImpl, Scope,
     },
     source_location::SourceLocation,
     ty::{CanonicalType, MatchVariantAndInactiveScope, StaticType, Type, TypeProperties},
 };
 use hashbrown::HashMap;
-use std::{fmt, iter::FusedIterator};
+use std::{convert::Infallible, fmt, iter::FusedIterator};
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
 pub struct EnumVariant {
@@ -364,3 +364,308 @@ pub fn HdlSome<T: Type>(value: impl ToExpr<Type = T>) -> Expr<HdlOption<T>> {
     let value = value.to_expr();
     HdlOption[Expr::ty(value)].HdlSome(value)
 }
+
+impl<T: Type> HdlOption<T> {
+    #[track_caller]
+    pub fn try_map<R: Type, E>(
+        expr: Expr<Self>,
+        f: impl FnOnce(Expr<T>) -> Result<Expr<R>, E>,
+    ) -> Result<Expr<HdlOption<R>>, E> {
+        Self::try_and_then(expr, |v| Ok(HdlSome(f(v)?)))
+    }
+    #[track_caller]
+    pub fn map<R: Type>(
+        expr: Expr<Self>,
+        f: impl FnOnce(Expr<T>) -> Expr<R>,
+    ) -> Expr<HdlOption<R>> {
+        Self::and_then(expr, |v| HdlSome(f(v)))
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn try_and_then<R: Type, E>(
+        expr: Expr<Self>,
+        f: impl FnOnce(Expr<T>) -> Result<Expr<HdlOption<R>>, E>,
+    ) -> Result<Expr<HdlOption<R>>, E> {
+        // manually run match steps so we can extract the return type to construct HdlNone
+        type Wrap<T> = T;
+        #[hdl]
+        let mut and_then_out = incomplete_wire();
+        let mut iter = Self::match_variants(expr, SourceLocation::caller());
+        let none = iter.next().unwrap();
+        let some = iter.next().unwrap();
+        assert!(iter.next().is_none());
+        let (Wrap::<<Self as Type>::MatchVariant>::HdlSome(value), some_scope) =
+            Self::match_activate_scope(some)
+        else {
+            unreachable!();
+        };
+        let value = f(value).map_err(|e| {
+            and_then_out.complete(()); // avoid error
+            e
+        })?;
+        let and_then_out = and_then_out.complete(Expr::ty(value));
+        connect(and_then_out, value);
+        drop(some_scope);
+        let (Wrap::<<Self as Type>::MatchVariant>::HdlNone, none_scope) =
+            Self::match_activate_scope(none)
+        else {
+            unreachable!();
+        };
+        connect(and_then_out, Expr::ty(and_then_out).HdlNone());
+        drop(none_scope);
+        Ok(and_then_out)
+    }
+    #[track_caller]
+    pub fn and_then<R: Type>(
+        expr: Expr<Self>,
+        f: impl FnOnce(Expr<T>) -> Expr<HdlOption<R>>,
+    ) -> Expr<HdlOption<R>> {
+        match Self::try_and_then(expr, |v| Ok::<_, Infallible>(f(v))) {
+            Ok(v) => v,
+            Err(e) => match e {},
+        }
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn and<U: Type>(expr: Expr<Self>, opt_b: Expr<HdlOption<U>>) -> Expr<HdlOption<U>> {
+        #[hdl]
+        let and_out = wire(Expr::ty(opt_b));
+        connect(and_out, Expr::ty(opt_b).HdlNone());
+        #[hdl]
+        if let HdlSome(_) = expr {
+            connect(and_out, opt_b);
+        }
+        and_out
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn try_filter<E>(
+        expr: Expr<Self>,
+        f: impl FnOnce(Expr<T>) -> Result<Expr<Bool>, E>,
+    ) -> Result<Expr<Self>, E> {
+        #[hdl]
+        let filtered = wire(Expr::ty(expr));
+        connect(filtered, Expr::ty(expr).HdlNone());
+        let mut f = Some(f);
+        #[hdl]
+        if let HdlSome(v) = expr {
+            #[hdl]
+            if f.take().unwrap()(v)? {
+                connect(filtered, HdlSome(v));
+            }
+        }
+        Ok(filtered)
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn filter(expr: Expr<Self>, f: impl FnOnce(Expr<T>) -> Expr<Bool>) -> Expr<Self> {
+        match Self::try_filter(expr, |v| Ok::<_, Infallible>(f(v))) {
+            Ok(v) => v,
+            Err(e) => match e {},
+        }
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn try_inspect<E>(
+        expr: Expr<Self>,
+        f: impl FnOnce(Expr<T>) -> Result<(), E>,
+    ) -> Result<Expr<Self>, E> {
+        let mut f = Some(f);
+        #[hdl]
+        if let HdlSome(v) = expr {
+            f.take().unwrap()(v)?;
+        }
+        Ok(expr)
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn inspect(expr: Expr<Self>, f: impl FnOnce(Expr<T>)) -> Expr<Self> {
+        let mut f = Some(f);
+        #[hdl]
+        if let HdlSome(v) = expr {
+            f.take().unwrap()(v);
+        }
+        expr
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn is_none(expr: Expr<Self>) -> Expr<Bool> {
+        #[hdl]
+        let is_none_out: Bool = wire();
+        connect(is_none_out, false);
+        #[hdl]
+        if let HdlNone = expr {
+            connect(is_none_out, true);
+        }
+        is_none_out
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn is_some(expr: Expr<Self>) -> Expr<Bool> {
+        #[hdl]
+        let is_some_out: Bool = wire();
+        connect(is_some_out, false);
+        #[hdl]
+        if let HdlSome(_) = expr {
+            connect(is_some_out, true);
+        }
+        is_some_out
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn map_or<R: Type>(
+        expr: Expr<Self>,
+        default: Expr<R>,
+        f: impl FnOnce(Expr<T>) -> Expr<R>,
+    ) -> Expr<R> {
+        #[hdl]
+        let mapped = wire(Expr::ty(default));
+        let mut f = Some(f);
+        #[hdl]
+        match expr {
+            HdlSome(v) => connect(mapped, f.take().unwrap()(v)),
+            HdlNone => connect(mapped, default),
+        }
+        mapped
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn map_or_else<R: Type>(
+        expr: Expr<Self>,
+        default: impl FnOnce() -> Expr<R>,
+        f: impl FnOnce(Expr<T>) -> Expr<R>,
+    ) -> Expr<R> {
+        #[hdl]
+        let mut mapped = incomplete_wire();
+        let mut default = Some(default);
+        let mut f = Some(f);
+        let mut retval = None;
+        #[hdl]
+        match expr {
+            HdlSome(v) => {
+                let v = f.take().unwrap()(v);
+                let mapped = *retval.get_or_insert_with(|| mapped.complete(Expr::ty(v)));
+                connect(mapped, v);
+            }
+            HdlNone => {
+                let v = default.take().unwrap()();
+                let mapped = *retval.get_or_insert_with(|| mapped.complete(Expr::ty(v)));
+                connect(mapped, v);
+            }
+        }
+        retval.unwrap()
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn or(expr: Expr<Self>, opt_b: Expr<Self>) -> Expr<Self> {
+        #[hdl]
+        let or_out = wire(Expr::ty(expr));
+        connect(or_out, opt_b);
+        #[hdl]
+        if let HdlSome(_) = expr {
+            connect(or_out, expr);
+        }
+        or_out
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn or_else(expr: Expr<Self>, f: impl FnOnce() -> Expr<Self>) -> Expr<Self> {
+        #[hdl]
+        let or_else_out = wire(Expr::ty(expr));
+        connect(or_else_out, f());
+        #[hdl]
+        if let HdlSome(_) = expr {
+            connect(or_else_out, expr);
+        }
+        or_else_out
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn unwrap_or(expr: Expr<Self>, default: Expr<T>) -> Expr<T> {
+        #[hdl]
+        let unwrap_or_else_out = wire(Expr::ty(default));
+        connect(unwrap_or_else_out, default);
+        #[hdl]
+        if let HdlSome(v) = expr {
+            connect(unwrap_or_else_out, v);
+        }
+        unwrap_or_else_out
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn unwrap_or_else(expr: Expr<Self>, f: impl FnOnce() -> Expr<T>) -> Expr<T> {
+        #[hdl]
+        let unwrap_or_else_out = wire(Expr::ty(expr).HdlSome);
+        connect(unwrap_or_else_out, f());
+        #[hdl]
+        if let HdlSome(v) = expr {
+            connect(unwrap_or_else_out, v);
+        }
+        unwrap_or_else_out
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn xor(expr: Expr<Self>, opt_b: Expr<Self>) -> Expr<Self> {
+        #[hdl]
+        let xor_out = wire(Expr::ty(expr));
+        #[hdl]
+        if let HdlSome(_) = expr {
+            #[hdl]
+            if let HdlNone = opt_b {
+                connect(xor_out, expr);
+            } else {
+                connect(xor_out, Expr::ty(expr).HdlNone());
+            }
+        } else {
+            connect(xor_out, opt_b);
+        }
+        xor_out
+    }
+    #[hdl]
+    #[track_caller]
+    pub fn zip<U: Type>(expr: Expr<Self>, other: Expr<HdlOption<U>>) -> Expr<HdlOption<(T, U)>> {
+        #[hdl]
+        let zip_out = wire(HdlOption[(Expr::ty(expr).HdlSome, Expr::ty(other).HdlSome)]);
+        connect(zip_out, Expr::ty(zip_out).HdlNone());
+        #[hdl]
+        if let HdlSome(l) = expr {
+            #[hdl]
+            if let HdlSome(r) = other {
+                connect(zip_out, HdlSome((l, r)));
+            }
+        }
+        zip_out
+    }
+}
+
+impl<T: Type> HdlOption<HdlOption<T>> {
+    #[hdl]
+    #[track_caller]
+    pub fn flatten(expr: Expr<Self>) -> Expr<HdlOption<T>> {
+        #[hdl]
+        let flattened = wire(Expr::ty(expr).HdlSome);
+        #[hdl]
+        match expr {
+            HdlSome(v) => connect(flattened, v),
+            HdlNone => connect(flattened, Expr::ty(expr).HdlSome.HdlNone()),
+        }
+        flattened
+    }
+}
+
+impl<T: Type, U: Type> HdlOption<(T, U)> {
+    #[hdl]
+    #[track_caller]
+    pub fn unzip(expr: Expr<Self>) -> Expr<(HdlOption<T>, HdlOption<U>)> {
+        let (t, u) = Expr::ty(expr).HdlSome;
+        #[hdl]
+        let unzipped = wire((HdlOption[t], HdlOption[u]));
+        connect(unzipped, (HdlOption[t].HdlNone(), HdlOption[u].HdlNone()));
+        #[hdl]
+        if let HdlSome(v) = expr {
+            connect(unzipped.0, HdlSome(v.0));
+            connect(unzipped.1, HdlSome(v.1));
+        }
+        unzipped
+    }
+}

From 51ce7b079ec1b0ea53c31348be86f5c2fb52c124 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 20 Sep 2024 19:11:30 -0700
Subject: [PATCH 004/190] add ReadyValid<T>

---
 crates/fayalite/src/util.rs             |  2 ++
 crates/fayalite/src/util/ready_valid.rs | 34 +++++++++++++++++++++++++
 2 files changed, 36 insertions(+)
 create mode 100644 crates/fayalite/src/util/ready_valid.rs

diff --git a/crates/fayalite/src/util.rs b/crates/fayalite/src/util.rs
index fc5daf4..5b97e3b 100644
--- a/crates/fayalite/src/util.rs
+++ b/crates/fayalite/src/util.rs
@@ -25,3 +25,5 @@ pub use scoped_ref::ScopedRef;
 pub use misc::{
     interned_bit, iter_eq_by, BitSliceWriteWithBase, DebugAsDisplay, DebugAsRawString, MakeMutSlice,
 };
+
+pub mod ready_valid;
diff --git a/crates/fayalite/src/util/ready_valid.rs b/crates/fayalite/src/util/ready_valid.rs
new file mode 100644
index 0000000..a5893cf
--- /dev/null
+++ b/crates/fayalite/src/util/ready_valid.rs
@@ -0,0 +1,34 @@
+use crate::prelude::*;
+
+#[hdl]
+pub struct ReadyValid<T> {
+    pub data: HdlOption<T>,
+    #[hdl(flip)]
+    pub ready: Bool,
+}
+
+impl<T: Type> ReadyValid<T> {
+    #[hdl]
+    pub fn fire(expr: Expr<Self>) -> Expr<Bool> {
+        #[hdl]
+        let fire: Bool = wire();
+        #[hdl]
+        match expr.data {
+            HdlNone => connect(fire, false),
+            HdlSome(_) => connect(fire, expr.ready),
+        }
+        fire
+    }
+    #[hdl]
+    pub fn map<R: Type>(
+        expr: Expr<Self>,
+        f: impl FnOnce(Expr<T>) -> Expr<R>,
+    ) -> Expr<ReadyValid<R>> {
+        let data = HdlOption::map(expr.data, f);
+        #[hdl]
+        let mapped = wire(ReadyValid[Expr::ty(data).HdlSome]);
+        connect(mapped.data, data);
+        connect(expr.ready, mapped.ready);
+        mapped
+    }
+}

From 053391b01035ac0d4a62deea9a86a63865ebd739 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 22 Sep 2024 15:29:28 -0700
Subject: [PATCH 005/190] add script for checking copyright headers

---
 scripts/check-copyright.sh | 74 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100755 scripts/check-copyright.sh

diff --git a/scripts/check-copyright.sh b/scripts/check-copyright.sh
new file mode 100755
index 0000000..8104f9c
--- /dev/null
+++ b/scripts/check-copyright.sh
@@ -0,0 +1,74 @@
+#!/bin/bash
+# SPDX-License-Identifier: LGPL-3.0-or-later
+# See Notices.txt for copyright information
+set -e
+
+function fail()
+{
+    local error="$1"
+    echo "error: $error" >&2
+    exit 1
+}
+
+function fail_file()
+{
+    local file="$1" line="$2" error="$3"
+    fail "$file:$((line + 1)): $error"
+}
+
+function check_file()
+{
+    local file="$1" regexes=("${@:2}")
+    local lines
+    mapfile -t lines < "$file"
+    local line
+    for line in "${!regexes[@]}"; do
+        eval '[[ "${lines[i]}" =~ '"${regexes[i]}"' ]]' ||
+            fail_file "$file" "$line" "doesn't match regex: ${regexes[i]}"
+    done
+}
+
+POUND_HEADER=('^"# SPDX-License-Identifier: LGPL-3.0-or-later"$' '^"# See Notices.txt for copyright information"$')
+SLASH_HEADER=('^"// SPDX-License-Identifier: LGPL-3.0-or-later"$' '^"// See Notices.txt for copyright information"$')
+MD_HEADER=('^"<!--"$' '^"SPDX-License-Identifier: LGPL-3.0-or-later"$' '^"See Notices.txt for copyright information"$')
+JSON_HEADER=('^"{"$' '^"    \"license_header\": ["$' '^"        \"SPDX-License-Identifier: LGPL-3.0-or-later\","$' '^"        \"See Notices.txt for copyright information\""')
+
+function main()
+{
+    local IFS=$'\n'
+    [[ -z "$(git status --porcelain)" ]] || fail "git repo is dirty"
+    local file
+    for file in $(git ls-tree --name-only --full-tree -r HEAD); do
+        case "/$file" in
+        /Cargo.lock)
+            # generated file
+            ;;
+        */LICENSE.md|*/Notices.txt)
+            # copyright file
+            ;;
+        /crates/fayalite/tests/ui/*.stderr)
+            # file that can't contain copyright header
+            ;;
+        /.forgejo/workflows/*.yml|*/.gitignore|*.toml)
+            check_file "$file" "${POUND_HEADER[@]}"
+            ;;
+        *.md)
+            check_file "$file" "${MD_HEADER[@]}"
+            ;;
+        *.sh)
+            check_file "$file" '^'\''#!'\' "${POUND_HEADER[@]}"
+            ;;
+        *.rs)
+            check_file "$file" "${SLASH_HEADER[@]}"
+            ;;
+        *.json)
+            check_file "$file" "${JSON_HEADER[@]}"
+            ;;
+        *)
+            fail_file "$file" 0 "unimplemented file kind -- you need to add it to $0"
+            ;;
+        esac
+    done
+}
+
+main
\ No newline at end of file

From 10ae95fac109e48ad97ef2a93a0ad68c8776a7ed Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 22 Sep 2024 15:30:05 -0700
Subject: [PATCH 006/190] add missing copyright headers

---
 .forgejo/workflows/test.yml                                   | 2 ++
 .gitignore                                                    | 4 +++-
 README.md                                                     | 4 ++++
 crates/fayalite-proc-macros-impl/src/hdl_bundle.rs            | 2 ++
 crates/fayalite-proc-macros-impl/src/hdl_enum.rs              | 2 ++
 crates/fayalite-proc-macros-impl/src/hdl_type_common.rs       | 2 ++
 crates/fayalite/examples/blinky.rs                            | 2 ++
 crates/fayalite/src/_docs.rs                                  | 2 ++
 crates/fayalite/src/_docs/modules.rs                          | 2 ++
 crates/fayalite/src/_docs/modules/extern_module.rs            | 2 ++
 crates/fayalite/src/_docs/modules/module_bodies.rs            | 2 ++
 .../src/_docs/modules/module_bodies/hdl_array_expressions.rs  | 2 ++
 .../src/_docs/modules/module_bodies/hdl_if_statements.rs      | 2 ++
 .../src/_docs/modules/module_bodies/hdl_let_statements.rs     | 2 ++
 .../module_bodies/hdl_let_statements/inputs_outputs.rs        | 2 ++
 .../modules/module_bodies/hdl_let_statements/instances.rs     | 2 ++
 .../modules/module_bodies/hdl_let_statements/memories.rs      | 2 ++
 .../modules/module_bodies/hdl_let_statements/registers.rs     | 2 ++
 .../_docs/modules/module_bodies/hdl_let_statements/wires.rs   | 2 ++
 .../fayalite/src/_docs/modules/module_bodies/hdl_literals.rs  | 2 ++
 .../src/_docs/modules/module_bodies/hdl_match_statements.rs   | 2 ++
 .../modules/module_bodies/hdl_struct_variant_expressions.rs   | 2 ++
 crates/fayalite/src/_docs/modules/normal_module.rs            | 2 ++
 crates/fayalite/src/_docs/semantics.rs                        | 2 ++
 crates/fayalite/src/_docs/semantics/connection_semantics.rs   | 2 ++
 crates/fayalite/src/cli.rs                                    | 2 ++
 crates/fayalite/src/expr/target.rs                            | 2 ++
 crates/fayalite/src/prelude.rs                                | 2 ++
 crates/fayalite/src/util/ready_valid.rs                       | 2 ++
 crates/fayalite/src/util/scoped_ref.rs                        | 2 ++
 crates/fayalite/visit_types.json                              | 4 ++++
 31 files changed, 67 insertions(+), 1 deletion(-)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index 088ca7c..df5f59c 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: LGPL-3.0-or-later
+# See Notices.txt for copyright information
 on: [push, pull_request]
 
 jobs:
diff --git a/.gitignore b/.gitignore
index ccb5166..0655406 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,2 +1,4 @@
+# SPDX-License-Identifier: LGPL-3.0-or-later
+# See Notices.txt for copyright information
 /target
-.vscode
\ No newline at end of file
+.vscode
diff --git a/README.md b/README.md
index 6e14e9f..438550e 100644
--- a/README.md
+++ b/README.md
@@ -1,3 +1,7 @@
+<!--
+SPDX-License-Identifier: LGPL-3.0-or-later
+See Notices.txt for copyright information
+-->
 # Fayalite
 
 Fayalite is a library for designing digital hardware -- a hardware description language (HDL) embedded in the Rust programming language. Fayalite's semantics are based on [FIRRTL] as interpreted by [LLVM CIRCT](https://circt.llvm.org/docs/Dialects/FIRRTL/FIRRTLAnnotations/).
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
index 7f7d626..30cf90f 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 use crate::{
     hdl_type_common::{
         common_derives, get_target, ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedField,
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
index d7e5b61..50fb138 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 use crate::{
     hdl_type_common::{
         common_derives, get_target, ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics,
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
index e33d0e0..efbe7f3 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 use crate::{fold::impl_fold, kw, Errors, HdlAttr, PairsIterExt};
 use proc_macro2::{Span, TokenStream};
 use quote::{format_ident, quote_spanned, ToTokens};
diff --git a/crates/fayalite/examples/blinky.rs b/crates/fayalite/examples/blinky.rs
index 588ca9a..94c7910 100644
--- a/crates/fayalite/examples/blinky.rs
+++ b/crates/fayalite/examples/blinky.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 use clap::Parser;
 use fayalite::{cli, prelude::*};
 
diff --git a/crates/fayalite/src/_docs.rs b/crates/fayalite/src/_docs.rs
index 4d254a7..5b1888b 100644
--- a/crates/fayalite/src/_docs.rs
+++ b/crates/fayalite/src/_docs.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 #![doc = include_str!("../README.md")]
 
 //!
diff --git a/crates/fayalite/src/_docs/modules.rs b/crates/fayalite/src/_docs/modules.rs
index c392f2e..99b98e8 100644
--- a/crates/fayalite/src/_docs/modules.rs
+++ b/crates/fayalite/src/_docs/modules.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! # Fayalite Modules
 //!
 //! The [`#[hdl_module]`][`crate::hdl_module`] attribute is applied to a Rust
diff --git a/crates/fayalite/src/_docs/modules/extern_module.rs b/crates/fayalite/src/_docs/modules/extern_module.rs
index bf2034b..c1367d9 100644
--- a/crates/fayalite/src/_docs/modules/extern_module.rs
+++ b/crates/fayalite/src/_docs/modules/extern_module.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! These are for when you want to use modules written in
 //! some other language, such as Verilog.
 //!
diff --git a/crates/fayalite/src/_docs/modules/module_bodies.rs b/crates/fayalite/src/_docs/modules/module_bodies.rs
index bd85c61..c12ae21 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! # Module Function Bodies
 //!
 //! The `#[hdl_module]` attribute lets you have statements/expressions with `#[hdl]` annotations
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_array_expressions.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_array_expressions.rs
index c4bbfa4..c0b15ad 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_array_expressions.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_array_expressions.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! # `#[hdl]` Array Expressions
 //!
 //! `#[hdl]` can be used on Array Expressions to construct an [`Array<[T; N]>`][type@Array] expression:
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_if_statements.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_if_statements.rs
index 46bb568..7d09943 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_if_statements.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_if_statements.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! # `#[hdl] if` Statements
 //!
 //! `#[hdl] if` statements behave similarly to Rust `if` statements, except they end up as muxes
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements.rs
index c4e3e70..61d29b5 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! ## `#[hdl] let` statements
 
 pub mod inputs_outputs;
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/inputs_outputs.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/inputs_outputs.rs
index bfd7521..14169d9 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/inputs_outputs.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/inputs_outputs.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! ### Inputs/Outputs
 //!
 //! Inputs/Outputs create a Rust variable with type [`Expr<T>`] where `T` is the type of the input/output.
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/instances.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/instances.rs
index 2776754..75def03 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/instances.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/instances.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! ### Module Instances
 //!
 //! module instances are kinda like the hardware equivalent of calling a function,
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/memories.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/memories.rs
index e491eef..ddd60b9 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/memories.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/memories.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! # Memories
 //!
 //! Memories are optimized for storing large amounts of data.
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/registers.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/registers.rs
index 28db27f..5a81c5b 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/registers.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/registers.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! ### Registers
 //!
 //! Registers are memory devices that will change their state only on a clock
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs
index b22e0fd..7d92b41 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! ### Wires
 //!
 //! Wires are kinda like variables, but unlike registers,
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_literals.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_literals.rs
index a6c9b58..91710e7 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_literals.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_literals.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! # `_hdl`-suffixed literals
 //!
 //! You can have integer literals with an arbitrary number of bits like so:
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs
index c0d4ea6..9e6c511 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! # `#[hdl] match` Statements
 //!
 //! `#[hdl] match` statements behave similarly to Rust `match` statements, except they end up as muxes
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_struct_variant_expressions.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_struct_variant_expressions.rs
index 9d63895..68cd685 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_struct_variant_expressions.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_struct_variant_expressions.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! # `#[hdl]` Struct/Variant Expressions
 //!
 //! Note: Structs are also known as [Bundles] when used in Fayalite, the Bundle name comes from [FIRRTL].
diff --git a/crates/fayalite/src/_docs/modules/normal_module.rs b/crates/fayalite/src/_docs/modules/normal_module.rs
index f84678e..1267551 100644
--- a/crates/fayalite/src/_docs/modules/normal_module.rs
+++ b/crates/fayalite/src/_docs/modules/normal_module.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! # Normal Modules
 //!
 //! See also: [Extern Modules][`super::extern_module`]
diff --git a/crates/fayalite/src/_docs/semantics.rs b/crates/fayalite/src/_docs/semantics.rs
index a499e8e..2282f25 100644
--- a/crates/fayalite/src/_docs/semantics.rs
+++ b/crates/fayalite/src/_docs/semantics.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! # Fayalite Semantics
 //!
 //! Fayalite's semantics are based on [FIRRTL]. Due to their significance, some of the semantics are also documented here.
diff --git a/crates/fayalite/src/_docs/semantics/connection_semantics.rs b/crates/fayalite/src/_docs/semantics/connection_semantics.rs
index 41155bf..ba2a679 100644
--- a/crates/fayalite/src/_docs/semantics/connection_semantics.rs
+++ b/crates/fayalite/src/_docs/semantics/connection_semantics.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 //! # Connection Semantics
 //!
 //! Fayalite's connection semantics are unlike assignments in software, so be careful!
diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index f848d36..5071279 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 use crate::{
     bundle::{Bundle, BundleType},
     firrtl,
diff --git a/crates/fayalite/src/expr/target.rs b/crates/fayalite/src/expr/target.rs
index f33b286..0f85f62 100644
--- a/crates/fayalite/src/expr/target.rs
+++ b/crates/fayalite/src/expr/target.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 use crate::{
     array::Array,
     bundle::{Bundle, BundleField},
diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs
index bedece2..6a74e67 100644
--- a/crates/fayalite/src/prelude.rs
+++ b/crates/fayalite/src/prelude.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 pub use crate::{
     annotations::Annotation,
     array::{Array, ArrayType},
diff --git a/crates/fayalite/src/util/ready_valid.rs b/crates/fayalite/src/util/ready_valid.rs
index a5893cf..ec761c2 100644
--- a/crates/fayalite/src/util/ready_valid.rs
+++ b/crates/fayalite/src/util/ready_valid.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 use crate::prelude::*;
 
 #[hdl]
diff --git a/crates/fayalite/src/util/scoped_ref.rs b/crates/fayalite/src/util/scoped_ref.rs
index f168853..7705377 100644
--- a/crates/fayalite/src/util/scoped_ref.rs
+++ b/crates/fayalite/src/util/scoped_ref.rs
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
 mod safety_boundary {
     use std::{cell::Cell, ptr::NonNull};
 
diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json
index 1748e47..ad9ed25 100644
--- a/crates/fayalite/visit_types.json
+++ b/crates/fayalite/visit_types.json
@@ -1,4 +1,8 @@
 {
+    "license_header": [
+        "SPDX-License-Identifier: LGPL-3.0-or-later",
+        "See Notices.txt for copyright information"
+    ],
     "types": {
         "Module": {
             "data": {

From bdbc6d89bd8046483e8b3ad7ff3e9cde7afb0f7b Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 22 Sep 2024 15:30:53 -0700
Subject: [PATCH 007/190] add check-copyright to CI

---
 .forgejo/workflows/test.yml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index df5f59c..6e82abf 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -9,6 +9,8 @@ jobs:
       - uses: https://code.forgejo.org/actions/checkout@v3
         with:
           fetch-depth: 0
+      - run: |
+          scripts/check-copyright.sh
       - run: |
           curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.80.1
           source "$HOME/.cargo/env"

From 790bb15408536d38856e8ffcc76069baf3269b91 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 22 Sep 2024 16:01:23 -0700
Subject: [PATCH 008/190] remove reset_default from proc-macro, forgot to
 remove when removing from RegBuilder

---
 crates/fayalite-proc-macros-impl/src/lib.rs   |  1 -
 .../src/module/transform_body.rs              | 36 ++-----------------
 2 files changed, 3 insertions(+), 34 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/lib.rs b/crates/fayalite-proc-macros-impl/src/lib.rs
index 903983f..194dbf3 100644
--- a/crates/fayalite-proc-macros-impl/src/lib.rs
+++ b/crates/fayalite-proc-macros-impl/src/lib.rs
@@ -78,7 +78,6 @@ mod kw {
     custom_keyword!(output);
     custom_keyword!(reg_builder);
     custom_keyword!(reset);
-    custom_keyword!(reset_default);
     custom_keyword!(skip);
     custom_keyword!(target);
     custom_keyword!(wire);
diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
index 1f9565a..6e99e87 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
@@ -265,11 +265,6 @@ pub(crate) enum RegBuilderReset {
         paren: Paren,
         init_expr: Box<Expr>,
     },
-    ResetDefault {
-        dot_token: Token![.],
-        reset_default: kw::reset_default,
-        paren: Paren,
-    },
 }
 
 impl_fold! {
@@ -286,11 +281,6 @@ impl_fold! {
             paren: Paren,
             init_expr: Box<Expr>,
         },
-        ResetDefault {
-            dot_token: Token![.],
-            reset_default: kw::reset_default,
-            paren: Paren,
-        },
     }
 }
 
@@ -312,11 +302,6 @@ impl Parse for RegBuilderReset {
                 paren: parenthesized!(paren_contents in input),
                 init_expr: paren_contents.call(parse_single_fn_arg)?,
             }),
-            RegBuilderMethod::ResetDefault(reset_default) => Ok(Self::ResetDefault {
-                dot_token,
-                reset_default,
-                paren: parenthesized!(paren_contents in input),
-            }),
         }
     }
 }
@@ -344,15 +329,6 @@ impl ToTokens for RegBuilderReset {
                 reset.to_tokens(tokens);
                 paren.surround(tokens, |tokens| init_expr.to_tokens(tokens));
             }
-            RegBuilderReset::ResetDefault {
-                dot_token,
-                reset_default,
-                paren,
-            } => {
-                dot_token.to_tokens(tokens);
-                reset_default.to_tokens(tokens);
-                paren.surround(tokens, |_| {});
-            }
         }
     }
 }
@@ -401,8 +377,6 @@ make_builder_method_enum! {
         NoReset(no_reset),
         #[cond = need_reset]
         Reset(reset),
-        #[cond = need_reset]
-        ResetDefault(reset_default),
     }
 }
 
@@ -445,17 +419,13 @@ impl HdlLetKindRegBuilder {
         let mut clock_domain = None;
         match RegBuilderMethod::parse_dot_prefixed(&input.fork(), true, true)?.1 {
             RegBuilderMethod::ClockDomain(_) => clock_domain = Some(input.parse()?),
-            RegBuilderMethod::NoReset(_)
-            | RegBuilderMethod::Reset(_)
-            | RegBuilderMethod::ResetDefault(_) => {}
+            RegBuilderMethod::NoReset(_) | RegBuilderMethod::Reset(_) => {}
         }
         let reset = input.parse()?;
         if clock_domain.is_none() {
             match RegBuilderMethod::parse_dot_prefixed(&input.fork(), true, false)?.1 {
                 RegBuilderMethod::ClockDomain(_) => clock_domain = Some(input.parse()?),
-                RegBuilderMethod::NoReset(_)
-                | RegBuilderMethod::Reset(_)
-                | RegBuilderMethod::ResetDefault(_) => unreachable!(),
+                RegBuilderMethod::NoReset(_) | RegBuilderMethod::Reset(_) => unreachable!(),
             }
         }
         Ok(Self {
@@ -1370,7 +1340,7 @@ impl Visitor<'_> {
                 no_reset.to_tokens(&mut expr);
                 paren.surround(&mut expr, |expr| ty_expr.to_tokens(expr));
             }
-            RegBuilderReset::Reset { .. } | RegBuilderReset::ResetDefault { .. } => {
+            RegBuilderReset::Reset { .. } => {
                 hdl_let.kind.reset.to_tokens(&mut expr);
             }
         }

From 8449854cac07c28ad421211da3217a52e6de2588 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 22 Sep 2024 17:19:58 -0700
Subject: [PATCH 009/190] add ToExpr for usize/isize/NonZero<T>

---
 crates/fayalite/src/expr/ops.rs | 18 ++++++++++--------
 crates/fayalite/src/int.rs      | 28 +++++++++++++++++++++++++++-
 2 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/crates/fayalite/src/expr/ops.rs b/crates/fayalite/src/expr/ops.rs
index 4814d2d..e5d3d9b 100644
--- a/crates/fayalite/src/expr/ops.rs
+++ b/crates/fayalite/src/expr/ops.rs
@@ -1236,10 +1236,11 @@ macro_rules! impl_dyn_shl {
             }
         }
 
-        impl_binary_op_trait! {
-            #[generics(LhsWidth: Size, RhsWidth: Size)]
-            fn Shl::shl(lhs: $ty<LhsWidth>, rhs: UIntType<RhsWidth>) -> $ty {
-                $name::new(Expr::as_dyn_int(lhs), Expr::as_dyn_int(rhs)).to_expr()
+        impl<LhsWidth: Size, RhsWidth: Size> Shl<Expr<UIntType<RhsWidth>>> for Expr<$ty<LhsWidth>> {
+            type Output = Expr<$ty>;
+
+            fn shl(self, rhs: Expr<UIntType<RhsWidth>>) -> Self::Output {
+                $name::new(Expr::as_dyn_int(self), Expr::as_dyn_int(rhs)).to_expr()
             }
         }
     };
@@ -1308,10 +1309,11 @@ macro_rules! impl_dyn_shr {
             }
         }
 
-        impl_binary_op_trait! {
-            #[generics(LhsWidth: Size, RhsWidth: Size)]
-            fn Shr::shr(lhs: $ty<LhsWidth>, rhs: UIntType<RhsWidth>) -> $ty<LhsWidth> {
-                $name::new(lhs, Expr::as_dyn_int(rhs)).to_expr()
+        impl<LhsWidth: Size, RhsWidth: Size> Shr<Expr<UIntType<RhsWidth>>> for Expr<$ty<LhsWidth>> {
+            type Output = Expr<$ty<LhsWidth>>;
+
+            fn shr(self, rhs: Expr<UIntType<RhsWidth>>) -> Self::Output {
+                $name::new(self, Expr::as_dyn_int(rhs)).to_expr()
             }
         }
     };
diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index 2950086..b48f617 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -18,6 +18,7 @@ use std::{
     borrow::{BorrowMut, Cow},
     fmt,
     marker::PhantomData,
+    num::NonZero,
     ops::{Bound, Index, Not, Range, RangeBounds, RangeInclusive},
     sync::Arc,
 };
@@ -468,7 +469,11 @@ impl SInt {
 }
 
 macro_rules! impl_prim_int {
-    ($prim_int:ident, $ty:ty) => {
+    (
+        $(#[$meta:meta])*
+        $prim_int:ident, $ty:ty
+    ) => {
+        $(#[$meta])*
         impl ToExpr for $prim_int {
             type Type = $ty;
 
@@ -479,6 +484,17 @@ macro_rules! impl_prim_int {
                 )
             }
         }
+        $(#[$meta])*
+        impl ToExpr for NonZero<$prim_int> {
+            type Type = $ty;
+
+            fn to_expr(&self) -> Expr<Self::Type> {
+                <$ty>::le_bytes_to_expr_wrapping(
+                    &self.get().to_le_bytes(),
+                    <$ty as BoolOrIntType>::Width::VALUE,
+                )
+            }
+        }
     };
 }
 
@@ -493,6 +509,16 @@ impl_prim_int!(i32, SInt<32>);
 impl_prim_int!(i64, SInt<64>);
 impl_prim_int!(i128, SInt<128>);
 
+impl_prim_int!(
+    /// for portability reasons, [`usize`] always translates to [`UInt<64>`]
+    usize, UInt<64>
+);
+
+impl_prim_int!(
+    /// for portability reasons, [`isize`] always translates to [`SInt<64>`]
+    isize, SInt<64>
+);
+
 pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
     type Width: Size;
     type Signed: GenericConstBool;

From 9ad4ec0f39d2d2d26c71ca9116555340d08876a4 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 22 Sep 2024 17:26:23 -0700
Subject: [PATCH 010/190] add ty.uninit()

---
 crates/fayalite/src/expr.rs                   | 11 +++++
 crates/fayalite/src/expr/ops.rs               | 38 ++++++++++++++++
 crates/fayalite/src/firrtl.rs                 | 15 +++++++
 .../src/module/transform/simplify_enums.rs    |  1 +
 crates/fayalite/src/prelude.rs                |  2 +-
 crates/fayalite/tests/module.rs               | 43 +++++++++++++++++++
 crates/fayalite/visit_types.json              | 10 +++++
 7 files changed, 119 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite/src/expr.rs b/crates/fayalite/src/expr.rs
index 607ff1e..5ba6dbf 100644
--- a/crates/fayalite/src/expr.rs
+++ b/crates/fayalite/src/expr.rs
@@ -111,6 +111,7 @@ expr_enum! {
         BundleLiteral(ops::BundleLiteral),
         ArrayLiteral(ops::ArrayLiteral<CanonicalType, DynSize>),
         EnumLiteral(ops::EnumLiteral),
+        Uninit(ops::Uninit),
         NotU(ops::NotU),
         NotS(ops::NotS),
         NotB(ops::NotB),
@@ -697,3 +698,13 @@ pub fn check_match_expr<T: Type>(
     _check_fn: impl FnOnce(T::MatchVariant, Infallible),
 ) {
 }
+
+pub trait MakeUninitExpr: Type {
+    fn uninit(self) -> Expr<Self>;
+}
+
+impl<T: Type> MakeUninitExpr for T {
+    fn uninit(self) -> Expr<Self> {
+        ops::Uninit::new(self).to_expr()
+    }
+}
diff --git a/crates/fayalite/src/expr/ops.rs b/crates/fayalite/src/expr/ops.rs
index e5d3d9b..144a56f 100644
--- a/crates/fayalite/src/expr/ops.rs
+++ b/crates/fayalite/src/expr/ops.rs
@@ -2529,3 +2529,41 @@ impl<T: Type> ToExpr for CastBitsTo<T> {
         }
     }
 }
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+pub struct Uninit<T: Type = CanonicalType> {
+    ty: T,
+}
+
+impl<T: Type> Uninit<T> {
+    #[track_caller]
+    pub fn new(ty: T) -> Self {
+        Self { ty }
+    }
+    pub fn ty(self) -> T {
+        self.ty
+    }
+}
+
+impl<T: Type> ToLiteralBits for Uninit<T> {
+    fn to_literal_bits(&self) -> Result<Interned<BitSlice>, NotALiteralExpr> {
+        Err(NotALiteralExpr)
+    }
+}
+
+impl_get_target_none!([T: Type] Uninit<T>);
+
+impl<T: Type> ToExpr for Uninit<T> {
+    type Type = T;
+
+    fn to_expr(&self) -> Expr<Self::Type> {
+        Expr {
+            __enum: ExprEnum::Uninit(Uninit {
+                ty: self.ty.canonical(),
+            })
+            .intern(),
+            __ty: self.ty,
+            __flow: Flow::Source,
+        }
+    }
+}
diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index 5a562c0..dbbdd7d 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -912,6 +912,20 @@ impl<'a> Exporter<'a> {
         }
         ident.to_string()
     }
+    fn uninit_expr(
+        &mut self,
+        expr: ops::Uninit,
+        definitions: &RcDefinitions,
+        const_ty: bool,
+    ) -> String {
+        let ident = self.module.ns.make_new("_uninit_expr");
+        let ty = expr.ty();
+        let ty_ident = self.type_state.ty(ty);
+        let const_ = if const_ty { "const " } else { "" };
+        definitions.add_definition_line(format_args!("wire {ident}: {const_}{ty_ident}"));
+        definitions.add_definition_line(format_args!("invalidate {ident}"));
+        ident.to_string()
+    }
     fn enum_literal_expr(
         &mut self,
         expr: ops::EnumLiteral<Enum>,
@@ -1367,6 +1381,7 @@ impl<'a> Exporter<'a> {
             ExprEnum::EnumLiteral(enum_literal) => {
                 self.enum_literal_expr(enum_literal, definitions, const_ty)
             }
+            ExprEnum::Uninit(uninit) => self.uninit_expr(uninit, definitions, const_ty),
             ExprEnum::NotU(expr) => self.expr_unary("not", expr.arg(), definitions, const_ty),
             ExprEnum::NotS(expr) => self.expr_unary("not", expr.arg(), definitions, const_ty),
             ExprEnum::NotB(expr) => self.expr_unary("not", expr.arg(), definitions, const_ty),
diff --git a/crates/fayalite/src/module/transform/simplify_enums.rs b/crates/fayalite/src/module/transform/simplify_enums.rs
index 91bbba5..d6a9c02 100644
--- a/crates/fayalite/src/module/transform/simplify_enums.rs
+++ b/crates/fayalite/src/module/transform/simplify_enums.rs
@@ -287,6 +287,7 @@ impl Folder for State {
             | ExprEnum::BoolLiteral(_)
             | ExprEnum::BundleLiteral(_)
             | ExprEnum::ArrayLiteral(_)
+            | ExprEnum::Uninit(_)
             | ExprEnum::NotU(_)
             | ExprEnum::NotS(_)
             | ExprEnum::NotB(_)
diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs
index 6a74e67..b376093 100644
--- a/crates/fayalite/src/prelude.rs
+++ b/crates/fayalite/src/prelude.rs
@@ -6,7 +6,7 @@ pub use crate::{
     cli::Cli,
     clock::{Clock, ClockDomain, ToClock},
     enum_::{HdlNone, HdlOption, HdlSome},
-    expr::{CastBitsTo, CastTo, CastToBits, Expr, ReduceBits, ToExpr},
+    expr::{CastBitsTo, CastTo, CastToBits, Expr, MakeUninitExpr, ReduceBits, ToExpr},
     hdl, hdl_module,
     int::{Bool, DynSize, IntCmp, KnownSize, SInt, SIntType, Size, UInt, UIntType},
     memory::{Mem, MemBuilder, ReadUnderWrite},
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 23cd61f..c135f51 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -3139,3 +3139,46 @@ circuit check_annotations: %[[
 "#,
     };
 }
+
+#[hdl_module(outline_generated)]
+pub fn check_uninit<T: Type>(ty: T) {
+    #[hdl]
+    let o: T = m.output(ty);
+    connect(o, ty.uninit());
+}
+
+#[test]
+fn test_uninit() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_uninit((UInt[3], SInt[5], Clock));
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_uninit.fir": r"FIRRTL version 3.2.0
+circuit check_uninit:
+    type Ty0 = {`0`: UInt<3>, `1`: SInt<5>, `2`: Clock}
+    module check_uninit: @[module-XXXXXXXXXX.rs 1:1]
+        output o: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        wire _uninit_expr: Ty0
+        invalidate _uninit_expr
+        connect o, _uninit_expr @[module-XXXXXXXXXX.rs 3:1]
+",
+    };
+    let m = check_uninit(Array[HdlOption[()]][3]);
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_uninit_1.fir": r"FIRRTL version 3.2.0
+circuit check_uninit_1:
+    type Ty0 = {}
+    type Ty1 = {|HdlNone, HdlSome: Ty0|}
+    module check_uninit_1: @[module-XXXXXXXXXX.rs 1:1]
+        output o: Ty1[3] @[module-XXXXXXXXXX.rs 2:1]
+        wire _uninit_expr: Ty1[3]
+        invalidate _uninit_expr
+        connect o, _uninit_expr @[module-XXXXXXXXXX.rs 3:1]
+",
+    };
+}
diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json
index ad9ed25..cbaae05 100644
--- a/crates/fayalite/visit_types.json
+++ b/crates/fayalite/visit_types.json
@@ -283,6 +283,16 @@
             "fold_where": "T: Fold<State>",
             "visit_where": "T: Visit<State>"
         },
+        "ops::Uninit": {
+            "data": {
+                "$kind": "Struct",
+                "$constructor": "ops::Uninit::new",
+                "ty()": "Visible"
+            },
+            "generics": "<T: Type>",
+            "fold_where": "T: Fold<State>",
+            "visit_where": "T: Visit<State>"
+        },
         "ops::NotU": {
             "data": {
                 "$kind": "Struct",

From 78edfc97b2f3aec69c869999cb57acd0687ab2eb Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 22 Sep 2024 17:28:46 -0700
Subject: [PATCH 011/190] split int::IntCmp into expr::HdlPartialEq and
 expr::HdlPartialOrd

---
 crates/fayalite/src/expr.rs                   | 12 ++++
 crates/fayalite/src/expr/ops.rs               | 63 +++++++++++++++----
 crates/fayalite/src/int.rs                    |  9 ---
 .../src/module/transform/simplify_enums.rs    |  4 +-
 crates/fayalite/src/prelude.rs                |  7 ++-
 5 files changed, 69 insertions(+), 26 deletions(-)

diff --git a/crates/fayalite/src/expr.rs b/crates/fayalite/src/expr.rs
index 5ba6dbf..644d058 100644
--- a/crates/fayalite/src/expr.rs
+++ b/crates/fayalite/src/expr.rs
@@ -641,6 +641,18 @@ impl<T: PortType> GetTarget for MemPort<T> {
     }
 }
 
+pub trait HdlPartialEq<Rhs> {
+    fn cmp_eq(self, rhs: Rhs) -> Expr<Bool>;
+    fn cmp_ne(self, rhs: Rhs) -> Expr<Bool>;
+}
+
+pub trait HdlPartialOrd<Rhs>: HdlPartialEq<Rhs> {
+    fn cmp_lt(self, rhs: Rhs) -> Expr<Bool>;
+    fn cmp_le(self, rhs: Rhs) -> Expr<Bool>;
+    fn cmp_gt(self, rhs: Rhs) -> Expr<Bool>;
+    fn cmp_ge(self, rhs: Rhs) -> Expr<Bool>;
+}
+
 pub trait ReduceBits {
     type UIntOutput;
     type BoolOutput;
diff --git a/crates/fayalite/src/expr/ops.rs b/crates/fayalite/src/expr/ops.rs
index 144a56f..6069f20 100644
--- a/crates/fayalite/src/expr/ops.rs
+++ b/crates/fayalite/src/expr/ops.rs
@@ -11,11 +11,12 @@ use crate::{
             GetTarget, Target, TargetPathArrayElement, TargetPathBundleField,
             TargetPathDynArrayElement, TargetPathElement,
         },
-        CastTo, Expr, ExprEnum, Flow, NotALiteralExpr, ReduceBits, ToExpr, ToLiteralBits,
+        CastTo, Expr, ExprEnum, Flow, HdlPartialEq, HdlPartialOrd, NotALiteralExpr, ReduceBits,
+        ToExpr, ToLiteralBits,
     },
     int::{
-        Bool, BoolOrIntType, DynSize, IntCmp, IntType, KnownSize, SInt, SIntType, SIntValue, Size,
-        UInt, UIntType, UIntValue,
+        Bool, BoolOrIntType, DynSize, IntType, KnownSize, SInt, SIntType, SIntValue, Size, UInt,
+        UIntType, UIntValue,
     },
     intern::{Intern, Interned},
     reset::{AsyncReset, Reset, SyncReset, ToAsyncReset, ToReset, ToSyncReset},
@@ -1422,36 +1423,45 @@ forward_value_to_expr_binary_op_trait! {
     Shr::shr
 }
 
-pub trait IntCmpExpr<Rhs: Type>: Type {
+pub trait ExprPartialEq<Rhs: Type>: Type {
     fn cmp_eq(lhs: Expr<Self>, rhs: Expr<Rhs>) -> Expr<Bool>;
     fn cmp_ne(lhs: Expr<Self>, rhs: Expr<Rhs>) -> Expr<Bool>;
+}
+
+pub trait ExprPartialOrd<Rhs: Type>: ExprPartialEq<Rhs> {
     fn cmp_lt(lhs: Expr<Self>, rhs: Expr<Rhs>) -> Expr<Bool>;
     fn cmp_le(lhs: Expr<Self>, rhs: Expr<Rhs>) -> Expr<Bool>;
     fn cmp_gt(lhs: Expr<Self>, rhs: Expr<Rhs>) -> Expr<Bool>;
     fn cmp_ge(lhs: Expr<Self>, rhs: Expr<Rhs>) -> Expr<Bool>;
 }
 
-impl<Lhs: ToExpr, Rhs: ToExpr> IntCmp<Rhs> for Lhs
+impl<Lhs: ToExpr, Rhs: ToExpr> HdlPartialEq<Rhs> for Lhs
 where
-    Lhs::Type: IntCmpExpr<Rhs::Type>,
+    Lhs::Type: ExprPartialEq<Rhs::Type>,
 {
     fn cmp_eq(self, rhs: Rhs) -> Expr<Bool> {
-        IntCmpExpr::cmp_eq(self.to_expr(), rhs.to_expr())
+        ExprPartialEq::cmp_eq(self.to_expr(), rhs.to_expr())
     }
     fn cmp_ne(self, rhs: Rhs) -> Expr<Bool> {
-        IntCmpExpr::cmp_ne(self.to_expr(), rhs.to_expr())
+        ExprPartialEq::cmp_ne(self.to_expr(), rhs.to_expr())
     }
+}
+
+impl<Lhs: ToExpr, Rhs: ToExpr> HdlPartialOrd<Rhs> for Lhs
+where
+    Lhs::Type: ExprPartialOrd<Rhs::Type>,
+{
     fn cmp_lt(self, rhs: Rhs) -> Expr<Bool> {
-        IntCmpExpr::cmp_lt(self.to_expr(), rhs.to_expr())
+        ExprPartialOrd::cmp_lt(self.to_expr(), rhs.to_expr())
     }
     fn cmp_le(self, rhs: Rhs) -> Expr<Bool> {
-        IntCmpExpr::cmp_le(self.to_expr(), rhs.to_expr())
+        ExprPartialOrd::cmp_le(self.to_expr(), rhs.to_expr())
     }
     fn cmp_gt(self, rhs: Rhs) -> Expr<Bool> {
-        IntCmpExpr::cmp_gt(self.to_expr(), rhs.to_expr())
+        ExprPartialOrd::cmp_gt(self.to_expr(), rhs.to_expr())
     }
     fn cmp_ge(self, rhs: Rhs) -> Expr<Bool> {
-        IntCmpExpr::cmp_ge(self.to_expr(), rhs.to_expr())
+        ExprPartialOrd::cmp_ge(self.to_expr(), rhs.to_expr())
     }
 }
 
@@ -1461,6 +1471,7 @@ macro_rules! impl_compare_op {
         #[dyn_type($DynTy:ident)]
         #[to_dyn_type($lhs:ident => $dyn_lhs:expr, $rhs:ident => $dyn_rhs:expr)]
         #[type($Lhs:ty, $Rhs:ty)]
+        #[trait($Trait:ident)]
         $(
             struct $name:ident;
             fn $method:ident();
@@ -1512,7 +1523,7 @@ macro_rules! impl_compare_op {
             }
         })*
 
-        impl$(<$LhsWidth: Size, $RhsWidth: Size>)? IntCmpExpr<$Rhs> for $Lhs {
+        impl$(<$LhsWidth: Size, $RhsWidth: Size>)? $Trait<$Rhs> for $Lhs {
             $(fn $method($lhs: Expr<Self>, $rhs: Expr<$Rhs>) -> Expr<Bool> {
                 $name::new($dyn_lhs, $dyn_rhs).to_expr()
             })*
@@ -1524,8 +1535,16 @@ impl_compare_op! {
     #[dyn_type(Bool)]
     #[to_dyn_type(lhs => lhs, rhs => rhs)]
     #[type(Bool, Bool)]
+    #[trait(ExprPartialEq)]
     struct CmpEqB; fn cmp_eq(); PartialEq::eq();
     struct CmpNeB; fn cmp_ne(); PartialEq::ne();
+}
+
+impl_compare_op! {
+    #[dyn_type(Bool)]
+    #[to_dyn_type(lhs => lhs, rhs => rhs)]
+    #[type(Bool, Bool)]
+    #[trait(ExprPartialOrd)]
     struct CmpLtB; fn cmp_lt(); PartialOrd::lt();
     struct CmpLeB; fn cmp_le(); PartialOrd::le();
     struct CmpGtB; fn cmp_gt(); PartialOrd::gt();
@@ -1537,8 +1556,17 @@ impl_compare_op! {
     #[dyn_type(UInt)]
     #[to_dyn_type(lhs => Expr::as_dyn_int(lhs), rhs => Expr::as_dyn_int(rhs))]
     #[type(UIntType<LhsWidth>, UIntType<RhsWidth>)]
+    #[trait(ExprPartialEq)]
     struct CmpEqU; fn cmp_eq(); PartialEq::eq();
     struct CmpNeU; fn cmp_ne(); PartialEq::ne();
+}
+
+impl_compare_op! {
+    #[width(LhsWidth, RhsWidth)]
+    #[dyn_type(UInt)]
+    #[to_dyn_type(lhs => Expr::as_dyn_int(lhs), rhs => Expr::as_dyn_int(rhs))]
+    #[type(UIntType<LhsWidth>, UIntType<RhsWidth>)]
+    #[trait(ExprPartialOrd)]
     struct CmpLtU; fn cmp_lt(); PartialOrd::lt();
     struct CmpLeU; fn cmp_le(); PartialOrd::le();
     struct CmpGtU; fn cmp_gt(); PartialOrd::gt();
@@ -1550,8 +1578,17 @@ impl_compare_op! {
     #[dyn_type(SInt)]
     #[to_dyn_type(lhs => Expr::as_dyn_int(lhs), rhs => Expr::as_dyn_int(rhs))]
     #[type(SIntType<LhsWidth>, SIntType<RhsWidth>)]
+    #[trait(ExprPartialEq)]
     struct CmpEqS; fn cmp_eq(); PartialEq::eq();
     struct CmpNeS; fn cmp_ne(); PartialEq::ne();
+}
+
+impl_compare_op! {
+    #[width(LhsWidth, RhsWidth)]
+    #[dyn_type(SInt)]
+    #[to_dyn_type(lhs => Expr::as_dyn_int(lhs), rhs => Expr::as_dyn_int(rhs))]
+    #[type(SIntType<LhsWidth>, SIntType<RhsWidth>)]
+    #[trait(ExprPartialOrd)]
     struct CmpLtS; fn cmp_lt(); PartialOrd::lt();
     struct CmpLeS; fn cmp_le(); PartialOrd::le();
     struct CmpGtS; fn cmp_gt(); PartialOrd::gt();
diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index b48f617..e0d258a 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -679,15 +679,6 @@ impl StaticType for Bool {
     const MASK_TYPE_PROPERTIES: TypeProperties = Bool::TYPE_PROPERTIES;
 }
 
-pub trait IntCmp<Rhs> {
-    fn cmp_eq(self, rhs: Rhs) -> Expr<Bool>;
-    fn cmp_ne(self, rhs: Rhs) -> Expr<Bool>;
-    fn cmp_lt(self, rhs: Rhs) -> Expr<Bool>;
-    fn cmp_le(self, rhs: Rhs) -> Expr<Bool>;
-    fn cmp_gt(self, rhs: Rhs) -> Expr<Bool>;
-    fn cmp_ge(self, rhs: Rhs) -> Expr<Bool>;
-}
-
 impl ToLiteralBits for bool {
     fn to_literal_bits(&self) -> Result<Interned<BitSlice>, NotALiteralExpr> {
         Ok(interned_bit(*self))
diff --git a/crates/fayalite/src/module/transform/simplify_enums.rs b/crates/fayalite/src/module/transform/simplify_enums.rs
index d6a9c02..9e1e552 100644
--- a/crates/fayalite/src/module/transform/simplify_enums.rs
+++ b/crates/fayalite/src/module/transform/simplify_enums.rs
@@ -6,10 +6,10 @@ use crate::{
     enum_::{Enum, EnumType, EnumVariant},
     expr::{
         ops::{self, EnumLiteral},
-        CastBitsTo, CastToBits, Expr, ExprEnum, ToExpr,
+        CastBitsTo, CastToBits, Expr, ExprEnum, HdlPartialEq, ToExpr,
     },
     hdl,
-    int::{DynSize, IntCmp, Size, UInt, UIntType},
+    int::{DynSize, Size, UInt, UIntType},
     intern::{Intern, Interned},
     memory::{DynPortType, Mem, MemPort},
     module::{
diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs
index b376093..5dc503e 100644
--- a/crates/fayalite/src/prelude.rs
+++ b/crates/fayalite/src/prelude.rs
@@ -6,9 +6,12 @@ pub use crate::{
     cli::Cli,
     clock::{Clock, ClockDomain, ToClock},
     enum_::{HdlNone, HdlOption, HdlSome},
-    expr::{CastBitsTo, CastTo, CastToBits, Expr, MakeUninitExpr, ReduceBits, ToExpr},
+    expr::{
+        CastBitsTo, CastTo, CastToBits, Expr, HdlPartialEq, HdlPartialOrd, MakeUninitExpr,
+        ReduceBits, ToExpr,
+    },
     hdl, hdl_module,
-    int::{Bool, DynSize, IntCmp, KnownSize, SInt, SIntType, Size, UInt, UIntType},
+    int::{Bool, DynSize, KnownSize, SInt, SIntType, Size, UInt, UIntType},
     memory::{Mem, MemBuilder, ReadUnderWrite},
     module::{
         annotate, connect, connect_any, incomplete_wire, instance, memory, memory_array,

From a701f99fd6fc5eb21c138312dc93b581329bf50b Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 22 Sep 2024 18:56:26 -0700
Subject: [PATCH 012/190] add repeat()

---
 crates/fayalite/src/expr.rs    | 17 ++++++++++++++++-
 crates/fayalite/src/prelude.rs |  2 +-
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/crates/fayalite/src/expr.rs b/crates/fayalite/src/expr.rs
index 644d058..fa50852 100644
--- a/crates/fayalite/src/expr.rs
+++ b/crates/fayalite/src/expr.rs
@@ -9,7 +9,7 @@ use crate::{
         ops::ExprCastTo,
         target::{GetTarget, Target},
     },
-    int::{Bool, DynSize, IntType, SIntType, SIntValue, Size, UInt, UIntType, UIntValue},
+    int::{Bool, DynSize, IntType, SIntType, SIntValue, Size, SizeType, UInt, UIntType, UIntValue},
     intern::{Intern, Interned},
     memory::{DynPortType, MemPort, PortType},
     module::{
@@ -720,3 +720,18 @@ impl<T: Type> MakeUninitExpr for T {
         ops::Uninit::new(self).to_expr()
     }
 }
+
+pub fn repeat<T: Type, L: SizeType>(
+    element: impl ToExpr<Type = T>,
+    len: L,
+) -> Expr<ArrayType<T, L::Size>> {
+    let element = element.to_expr();
+    let canonical_element = Expr::canonical(element);
+    ops::ArrayLiteral::new(
+        Expr::ty(element),
+        std::iter::repeat(canonical_element)
+            .take(L::Size::as_usize(len))
+            .collect(),
+    )
+    .to_expr()
+}
diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs
index 5dc503e..7b7d718 100644
--- a/crates/fayalite/src/prelude.rs
+++ b/crates/fayalite/src/prelude.rs
@@ -7,7 +7,7 @@ pub use crate::{
     clock::{Clock, ClockDomain, ToClock},
     enum_::{HdlNone, HdlOption, HdlSome},
     expr::{
-        CastBitsTo, CastTo, CastToBits, Expr, HdlPartialEq, HdlPartialOrd, MakeUninitExpr,
+        repeat, CastBitsTo, CastTo, CastToBits, Expr, HdlPartialEq, HdlPartialOrd, MakeUninitExpr,
         ReduceBits, ToExpr,
     },
     hdl, hdl_module,

From f6146048d1a6fa4c06db8c0289794481c36f9a01 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 22 Sep 2024 18:57:30 -0700
Subject: [PATCH 013/190] add memory::splat_mask to generate mask types from a
 Bool

---
 crates/fayalite/src/memory.rs | 31 ++++++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite/src/memory.rs b/crates/fayalite/src/memory.rs
index e6bbea5..1762f57 100644
--- a/crates/fayalite/src/memory.rs
+++ b/crates/fayalite/src/memory.rs
@@ -7,7 +7,7 @@ use crate::{
     array::{Array, ArrayType},
     bundle::{Bundle, BundleType},
     clock::Clock,
-    expr::{Expr, Flow, ToExpr, ToLiteralBits},
+    expr::{ops::BundleLiteral, repeat, Expr, Flow, ToExpr, ToLiteralBits},
     hdl,
     int::{Bool, DynSize, Size, UInt, UIntType},
     intern::{Intern, Interned},
@@ -1050,3 +1050,32 @@ impl<Element: Type, Len: Size> MemBuilder<Element, Len> {
             .extend(annotations.into_annotations());
     }
 }
+
+pub fn splat_mask<T: Type>(ty: T, value: Expr<Bool>) -> Expr<AsMask<T>> {
+    let canonical_ty = ty.canonical();
+    match canonical_ty {
+        CanonicalType::UInt(_)
+        | CanonicalType::SInt(_)
+        | CanonicalType::Bool(_)
+        | CanonicalType::AsyncReset(_)
+        | CanonicalType::SyncReset(_)
+        | CanonicalType::Reset(_)
+        | CanonicalType::Clock(_)
+        | CanonicalType::Enum(_) => Expr::from_canonical(Expr::canonical(value)),
+        CanonicalType::Array(array) => Expr::from_canonical(Expr::canonical(repeat(
+            splat_mask(array.element(), value),
+            array.len(),
+        ))),
+        CanonicalType::Bundle(bundle) => Expr::from_canonical(Expr::canonical(
+            BundleLiteral::new(
+                bundle.mask_type(),
+                bundle
+                    .fields()
+                    .iter()
+                    .map(|field| splat_mask(field.ty, value))
+                    .collect(),
+            )
+            .to_expr(),
+        )),
+    }
+}

From 716c65edcd421fa3a28d271ec647188331c2d52a Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 22 Sep 2024 18:59:12 -0700
Subject: [PATCH 014/190] add WIP version of queue()

---
 crates/fayalite/src/util/ready_valid.rs | 130 +++++++++++++++++++++++-
 1 file changed, 129 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite/src/util/ready_valid.rs b/crates/fayalite/src/util/ready_valid.rs
index ec761c2..94154c9 100644
--- a/crates/fayalite/src/util/ready_valid.rs
+++ b/crates/fayalite/src/util/ready_valid.rs
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-use crate::prelude::*;
+use crate::{memory::splat_mask, prelude::*};
+use std::num::NonZeroUsize;
 
 #[hdl]
 pub struct ReadyValid<T> {
@@ -34,3 +35,130 @@ impl<T: Type> ReadyValid<T> {
         mapped
     }
 }
+
+// TODO: needs testing
+#[hdl_module]
+pub fn queue<T: Type>(
+    ty: T,
+    capacity: NonZeroUsize,
+    inp_ready_is_comb: bool,
+    out_valid_is_comb: bool,
+) {
+    let count_ty = UInt::range_inclusive(0..=capacity.get());
+    let index_ty = UInt::range(0..capacity.get());
+
+    #[hdl]
+    let cd: ClockDomain = m.input();
+    #[hdl]
+    let inp: ReadyValid<T> = m.input(ReadyValid[ty]);
+    #[hdl]
+    let out: ReadyValid<T> = m.output(ReadyValid[ty]);
+    #[hdl]
+    let count: UInt = m.output(count_ty);
+
+    #[hdl]
+    let inp_index = reg_builder().clock_domain(cd).reset(0.cast_to(index_ty));
+    #[hdl]
+    let out_index = reg_builder().clock_domain(cd).reset(0.cast_to(index_ty));
+    #[hdl]
+    let maybe_full = reg_builder().clock_domain(cd).reset(false);
+
+    #[hdl]
+    let mut mem = memory(ty);
+    mem.depth(capacity.get());
+    let read_port = mem.new_read_port();
+    let write_port = mem.new_write_port();
+
+    #[hdl]
+    let inp_fire: Bool = wire();
+    connect(inp_fire, ReadyValid::fire(inp));
+    #[hdl]
+    let out_fire: Bool = wire();
+    connect(out_fire, ReadyValid::fire(out));
+    #[hdl]
+    let indexes_equal: Bool = wire();
+    connect(indexes_equal, inp_index.cmp_eq(out_index));
+    #[hdl]
+    let empty: Bool = wire();
+    connect(empty, indexes_equal & !maybe_full);
+    #[hdl]
+    let full: Bool = wire();
+    connect(full, indexes_equal & maybe_full);
+
+    connect(read_port.addr, out_index);
+    connect(read_port.en, true);
+    connect(read_port.clk, cd.clk);
+    connect(write_port.addr, inp_index);
+    connect(write_port.en, inp_fire);
+    connect(write_port.clk, cd.clk);
+    connect(write_port.data, HdlOption::unwrap_or(inp.data, ty.uninit()));
+    connect(write_port.mask, splat_mask(ty, true.to_expr()));
+
+    connect(inp.ready, !full);
+    if inp_ready_is_comb {
+        #[hdl]
+        if out.ready {
+            connect(inp.ready, true);
+        }
+    }
+
+    #[hdl]
+    if !empty {
+        connect(out.data, HdlSome(read_port.data));
+    } else {
+        if out_valid_is_comb {
+            connect(out.data, inp.data);
+        } else {
+            connect(out.data, HdlOption[ty].HdlNone());
+        }
+    }
+
+    #[hdl]
+    if inp_fire.cmp_ne(out_fire) {
+        connect(maybe_full, inp_fire);
+    }
+
+    #[hdl]
+    if inp_fire {
+        #[hdl]
+        if inp_index.cmp_eq(capacity) {
+            connect_any(inp_index, 0_hdl_u0);
+        } else {
+            connect_any(inp_index, inp_index + 1_hdl_u1);
+        }
+    }
+
+    #[hdl]
+    if out_fire {
+        #[hdl]
+        if out_index.cmp_eq(capacity) {
+            connect_any(out_index, 0_hdl_u0);
+        } else {
+            connect_any(out_index, out_index + 1_hdl_u1);
+        }
+    }
+
+    #[hdl]
+    if indexes_equal {
+        connect(
+            count,
+            maybe_full.cast_to_static::<UInt<1>>() << (count_ty.width() - 1),
+        );
+    } else {
+        if capacity.is_power_of_two() {
+            debug_assert_eq!(count_ty.width(), index_ty.width() + 1);
+            #[hdl]
+            let count_lower = wire(index_ty);
+            connect(count_lower, (inp_index - out_index).cast_to(index_ty)); // wrap
+            connect(count, count_lower.cast_to(count_ty));
+        } else {
+            debug_assert_eq!(count_ty.width(), index_ty.width());
+            #[hdl]
+            if inp_index.cmp_lt(out_index) {
+                connect(count, inp_index + capacity - out_index);
+            } else {
+                connect(count, inp_index - out_index);
+            }
+        }
+    }
+}

From 28aad19bf5c96f071a6f123ed934e3e2019f34cd Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 23 Sep 2024 19:10:51 -0700
Subject: [PATCH 015/190] add assert/assume/cover

---
 crates/fayalite/src/firrtl.rs                 |  31 +++-
 crates/fayalite/src/module.rs                 | 175 +++++++++++++++++-
 .../src/module/transform/simplify_enums.rs    |   4 +-
 crates/fayalite/src/module/transform/visit.rs |   4 +-
 crates/fayalite/src/prelude.rs                |   5 +-
 crates/fayalite/tests/module.rs               |  52 ++++++
 crates/fayalite/visit_types.json              |  20 ++
 7 files changed, 282 insertions(+), 9 deletions(-)

diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index dbbdd7d..b8ba89a 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -20,8 +20,8 @@ use crate::{
     module::{
         transform::simplify_memories::simplify_memories, AnnotatedModuleIO, Block,
         ExternModuleBody, ExternModuleParameter, ExternModuleParameterValue, Module, ModuleBody,
-        NameId, NormalModuleBody, Stmt, StmtConnect, StmtDeclaration, StmtIf, StmtInstance,
-        StmtMatch, StmtReg, StmtWire,
+        NameId, NormalModuleBody, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtFormalKind,
+        StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire,
     },
     reset::{AsyncReset, Reset, SyncReset},
     source_location::SourceLocation,
@@ -1954,6 +1954,33 @@ impl<'a> Exporter<'a> {
                     )
                     .unwrap();
                 }
+                Stmt::Formal(StmtFormal {
+                    kind,
+                    clk,
+                    pred,
+                    en,
+                    text,
+                    source_location,
+                }) => {
+                    let clk = self.expr(Expr::canonical(clk), &definitions, false);
+                    let pred = self.expr(Expr::canonical(pred), &definitions, false);
+                    let en = self.expr(Expr::canonical(en), &definitions, false);
+                    let kind = match kind {
+                        StmtFormalKind::Assert => "assert",
+                        StmtFormalKind::Assume => "assume",
+                        StmtFormalKind::Cover => "cover",
+                    };
+                    let text = EscapedString {
+                        value: &text,
+                        raw: false,
+                    };
+                    writeln!(
+                        body,
+                        "{indent}{kind}({clk}, {pred}, {en}, {text}){}",
+                        FileInfo::new(source_location),
+                    )
+                    .unwrap();
+                }
                 Stmt::If(StmtIf {
                     mut cond,
                     mut source_location,
diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index 3a17343..2b7534c 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -5,7 +5,7 @@ use crate::{
     annotations::{Annotation, IntoAnnotations, TargetedAnnotation},
     array::ArrayType,
     bundle::{Bundle, BundleField, BundleType},
-    clock::ClockDomain,
+    clock::{Clock, ClockDomain},
     enum_::{Enum, EnumMatchVariantsIter, EnumType},
     expr::{
         ops::VariantAccess,
@@ -199,6 +199,52 @@ impl fmt::Debug for StmtConnect {
     }
 }
 
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
+pub enum StmtFormalKind {
+    Assert,
+    Assume,
+    Cover,
+}
+
+impl StmtFormalKind {
+    pub fn as_str(self) -> &'static str {
+        match self {
+            Self::Assert => "assert",
+            Self::Assume => "assume",
+            Self::Cover => "cover",
+        }
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash)]
+pub struct StmtFormal {
+    pub kind: StmtFormalKind,
+    pub clk: Expr<Clock>,
+    pub pred: Expr<Bool>,
+    pub en: Expr<Bool>,
+    pub text: Interned<str>,
+    pub source_location: SourceLocation,
+}
+
+impl fmt::Debug for StmtFormal {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            kind,
+            clk,
+            pred,
+            en,
+            text,
+            source_location: _,
+        } = self;
+        f.debug_struct(kind.as_str())
+            .field("clk", clk)
+            .field("pred", pred)
+            .field("en", en)
+            .field("text", text)
+            .finish_non_exhaustive()
+    }
+}
+
 #[derive(Clone, PartialEq, Eq, Hash)]
 pub struct StmtIf<S: ModuleBuildingStatus = ModuleBuilt> {
     pub cond: Expr<Bool>,
@@ -450,6 +496,8 @@ wrapper_enum! {
     pub enum Stmt<S: ModuleBuildingStatus = ModuleBuilt> {
         #[is = is_connect, as_ref = connect]
         Connect(StmtConnect),
+        #[is = is_formal, as_ref = formal]
+        Formal(StmtFormal),
         #[is = is_if, as_ref = if_]
         If(StmtIf<S>),
         #[is = is_match, as_ref = match_]
@@ -462,7 +510,7 @@ wrapper_enum! {
 impl<S: ModuleBuildingStatus> Stmt<S> {
     pub fn sub_stmt_blocks(&self) -> &[S::Block] {
         match self {
-            Stmt::Connect(_) => &[],
+            Stmt::Connect(_) | Stmt::Formal(_) => &[],
             Stmt::If(v) => &v.blocks,
             Stmt::Match(v) => &v.blocks,
             Stmt::Declaration(v) => v.sub_stmt_blocks(),
@@ -609,6 +657,14 @@ impl NameIdGen {
                                 rhs: _,
                                 source_location: _,
                             })
+                            | Stmt::Formal(StmtFormal {
+                                kind: _,
+                                clk: _,
+                                pred: _,
+                                en: _,
+                                text: _,
+                                source_location: _,
+                            })
                             | Stmt::If(StmtIf {
                                 cond: _,
                                 source_location: _,
@@ -888,6 +944,7 @@ impl From<NormalModuleBody<ModuleBuilding>> for NormalModuleBody {
             let stmts = Interned::from_iter(stmts.into_iter().map(|stmt| {
                 match stmt {
                     Stmt::Connect(stmt) => stmt.into(),
+                    Stmt::Formal(stmt) => stmt.into(),
                     Stmt::If(StmtIf {
                         cond,
                         source_location,
@@ -1608,6 +1665,7 @@ impl AssertValidityState {
                     self.set_connect_side_written(lhs, source_location, true, block);
                     self.set_connect_side_written(rhs, source_location, false, block);
                 }
+                Stmt::Formal(_) => {}
                 Stmt::If(if_stmt) => {
                     let sub_blocks = if_stmt.blocks.map(|block| self.make_block_index(block));
                     self.process_conditional_sub_blocks(block, sub_blocks)
@@ -2336,6 +2394,119 @@ pub fn match_with_loc<T: Type>(
     T::match_variants(expr.to_expr(), source_location)
 }
 
+#[track_caller]
+pub fn formal_with_enable_and_loc(
+    kind: StmtFormalKind,
+    clk: Expr<Clock>,
+    pred: Expr<Bool>,
+    en: Expr<Bool>,
+    text: &str,
+    source_location: SourceLocation,
+) {
+    ModuleBuilder::with(|m| {
+        m.impl_
+            .borrow_mut()
+            .body
+            .builder_normal_body()
+            .block(m.block_stack.top())
+            .stmts
+            .push(
+                StmtFormal {
+                    kind,
+                    clk,
+                    pred,
+                    en,
+                    text: text.intern(),
+                    source_location,
+                }
+                .into(),
+            );
+    });
+}
+
+#[track_caller]
+pub fn formal_with_enable(
+    kind: StmtFormalKind,
+    clk: Expr<Clock>,
+    pred: Expr<Bool>,
+    en: Expr<Bool>,
+    text: &str,
+) {
+    formal_with_enable_and_loc(kind, clk, pred, en, text, SourceLocation::caller());
+}
+
+#[track_caller]
+pub fn formal_with_loc(
+    kind: StmtFormalKind,
+    clk: Expr<Clock>,
+    pred: Expr<Bool>,
+    text: &str,
+    source_location: SourceLocation,
+) {
+    formal_with_enable_and_loc(kind, clk, pred, true.to_expr(), text, source_location);
+}
+
+#[track_caller]
+pub fn formal(kind: StmtFormalKind, clk: Expr<Clock>, pred: Expr<Bool>, text: &str) {
+    formal_with_loc(kind, clk, pred, text, SourceLocation::caller());
+}
+
+macro_rules! make_formal {
+    ($kind:ident, $formal_with_enable_and_loc:ident, $formal_with_enable:ident, $formal_with_loc:ident, $formal:ident) => {
+        #[track_caller]
+        pub fn $formal_with_enable_and_loc(
+            clk: Expr<Clock>,
+            pred: Expr<Bool>,
+            en: Expr<Bool>,
+            text: &str,
+            source_location: SourceLocation,
+        ) {
+            formal_with_enable_and_loc(StmtFormalKind::$kind, clk, pred, en, text, source_location);
+        }
+        #[track_caller]
+        pub fn $formal_with_enable(clk: Expr<Clock>, pred: Expr<Bool>, en: Expr<Bool>, text: &str) {
+            formal_with_enable(StmtFormalKind::$kind, clk, pred, en, text);
+        }
+        #[track_caller]
+        pub fn $formal_with_loc(
+            clk: Expr<Clock>,
+            pred: Expr<Bool>,
+            text: &str,
+            source_location: SourceLocation,
+        ) {
+            formal_with_loc(StmtFormalKind::$kind, clk, pred, text, source_location);
+        }
+        #[track_caller]
+        pub fn $formal(clk: Expr<Clock>, pred: Expr<Bool>, text: &str) {
+            formal(StmtFormalKind::$kind, clk, pred, text);
+        }
+    };
+}
+
+make_formal!(
+    Assert,
+    hdl_assert_with_enable_and_loc,
+    hdl_assert_with_enable,
+    hdl_assert_with_loc,
+    hdl_assert
+);
+
+make_formal!(
+    Assume,
+    hdl_assume_with_enable_and_loc,
+    hdl_assume_with_enable,
+    hdl_assume_with_loc,
+    hdl_assume
+);
+
+make_formal!(
+    Cover,
+    hdl_cover_with_enable_and_loc,
+    hdl_cover_with_enable,
+    hdl_cover_with_loc,
+    hdl_cover
+);
+
 #[track_caller]
 pub fn connect_any_with_loc<Lhs: ToExpr, Rhs: ToExpr>(
     lhs: Lhs,
diff --git a/crates/fayalite/src/module/transform/simplify_enums.rs b/crates/fayalite/src/module/transform/simplify_enums.rs
index 9e1e552..c817e45 100644
--- a/crates/fayalite/src/module/transform/simplify_enums.rs
+++ b/crates/fayalite/src/module/transform/simplify_enums.rs
@@ -538,7 +538,9 @@ impl Folder for State {
                 }
                 .into()),
             },
-            Stmt::Connect(_) | Stmt::If(_) | Stmt::Declaration(_) => stmt.default_fold(self),
+            Stmt::Connect(_) | Stmt::Formal(_) | Stmt::If(_) | Stmt::Declaration(_) => {
+                stmt.default_fold(self)
+            }
         }
     }
 
diff --git a/crates/fayalite/src/module/transform/visit.rs b/crates/fayalite/src/module/transform/visit.rs
index 7edfe04..440eecb 100644
--- a/crates/fayalite/src/module/transform/visit.rs
+++ b/crates/fayalite/src/module/transform/visit.rs
@@ -21,8 +21,8 @@ use crate::{
     module::{
         AnnotatedModuleIO, Block, BlockId, ExternModuleBody, ExternModuleParameter,
         ExternModuleParameterValue, Instance, Module, ModuleBody, ModuleIO, NameId,
-        NormalModuleBody, ScopedNameId, Stmt, StmtConnect, StmtDeclaration, StmtIf, StmtInstance,
-        StmtMatch, StmtReg, StmtWire,
+        NormalModuleBody, ScopedNameId, Stmt, StmtConnect, StmtDeclaration, StmtFormal,
+        StmtFormalKind, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire,
     },
     reg::Reg,
     reset::{AsyncReset, Reset, SyncReset},
diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs
index 7b7d718..16dccb9 100644
--- a/crates/fayalite/src/prelude.rs
+++ b/crates/fayalite/src/prelude.rs
@@ -14,8 +14,9 @@ pub use crate::{
     int::{Bool, DynSize, KnownSize, SInt, SIntType, Size, UInt, UIntType},
     memory::{Mem, MemBuilder, ReadUnderWrite},
     module::{
-        annotate, connect, connect_any, incomplete_wire, instance, memory, memory_array,
-        memory_with_init, reg_builder, wire, Instance, Module, ModuleBuilder,
+        annotate, connect, connect_any, hdl_assert, hdl_assert_with_enable, hdl_assume,
+        hdl_assume_with_enable, hdl_cover, hdl_cover_with_enable, incomplete_wire, instance,
+        memory, memory_array, memory_with_init, reg_builder, wire, Instance, Module, ModuleBuilder,
     },
     reg::Reg,
     reset::{AsyncReset, Reset, SyncReset, ToAsyncReset, ToReset, ToSyncReset},
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index c135f51..4139ee1 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -3182,3 +3182,55 @@ circuit check_uninit_1:
 ",
     };
 }
+
+#[hdl_module(outline_generated)]
+pub fn check_formal() {
+    #[hdl]
+    let clk: Clock = m.input();
+    #[hdl]
+    let en1: Bool = m.input();
+    #[hdl]
+    let en2: Bool = m.input();
+    #[hdl]
+    let en3: Bool = m.input();
+    #[hdl]
+    let pred1: Bool = m.input();
+    #[hdl]
+    let pred2: Bool = m.input();
+    #[hdl]
+    let pred3: Bool = m.input();
+    hdl_assert_with_enable(clk, pred1, en1, "en check 1");
+    hdl_assume_with_enable(clk, pred2, en2, "en check 2");
+    hdl_cover_with_enable(clk, pred3, en3, "en check 3");
+    hdl_assert(clk, pred1, "check 1");
+    hdl_assume(clk, pred2, "check 2");
+    hdl_cover(clk, pred3, "check 3");
+}
+
+#[test]
+fn test_formal() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_formal();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_formal.fir": r#"FIRRTL version 3.2.0
+circuit check_formal:
+    module check_formal: @[module-XXXXXXXXXX.rs 1:1]
+        input clk: Clock @[module-XXXXXXXXXX.rs 2:1]
+        input en1: UInt<1> @[module-XXXXXXXXXX.rs 3:1]
+        input en2: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
+        input en3: UInt<1> @[module-XXXXXXXXXX.rs 5:1]
+        input pred1: UInt<1> @[module-XXXXXXXXXX.rs 6:1]
+        input pred2: UInt<1> @[module-XXXXXXXXXX.rs 7:1]
+        input pred3: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
+        assert(clk, pred1, en1, "en check 1") @[module-XXXXXXXXXX.rs 9:1]
+        assume(clk, pred2, en2, "en check 2") @[module-XXXXXXXXXX.rs 10:1]
+        cover(clk, pred3, en3, "en check 3") @[module-XXXXXXXXXX.rs 11:1]
+        assert(clk, pred1, UInt<1>(0h1), "check 1") @[module-XXXXXXXXXX.rs 12:1]
+        assume(clk, pred2, UInt<1>(0h1), "check 2") @[module-XXXXXXXXXX.rs 13:1]
+        cover(clk, pred3, UInt<1>(0h1), "check 3") @[module-XXXXXXXXXX.rs 14:1]
+"#,
+    };
+}
diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json
index cbaae05..f1969eb 100644
--- a/crates/fayalite/visit_types.json
+++ b/crates/fayalite/visit_types.json
@@ -1067,6 +1067,7 @@
             "data": {
                 "$kind": "Enum",
                 "Connect": "Visible",
+                "Formal": "Visible",
                 "If": "Visible",
                 "Match": "Visible",
                 "Declaration": "Visible"
@@ -1088,6 +1089,25 @@
                 "source_location": "Visible"
             }
         },
+        "StmtFormalKind": {
+            "data": {
+                "$kind": "Enum",
+                "Assert": null,
+                "Assume": null,
+                "Cover": null
+            }
+        },
+        "StmtFormal": {
+            "data": {
+                "$kind": "Struct",
+                "kind": "Visible",
+                "clk": "Visible",
+                "pred": "Visible",
+                "en": "Visible",
+                "text": "Visible",
+                "source_location": "Visible"
+            }
+        },
         "StmtIf": {
             "data": {
                 "$kind": "Struct",

From 4ff01690a7971d390a9d5a6dff3732b9a3a6a86c Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 25 Sep 2024 01:22:35 -0700
Subject: [PATCH 016/190] clean up deps and move missed deps to workspace

---
 Cargo.toml                                  |  3 +++
 crates/fayalite-proc-macros-impl/Cargo.toml | 16 +++++++-------
 crates/fayalite-proc-macros/Cargo.toml      |  2 +-
 crates/fayalite-visit-gen/Cargo.toml        | 16 +++++++-------
 crates/fayalite/Cargo.toml                  | 24 ++++++++++-----------
 5 files changed, 32 insertions(+), 29 deletions(-)

diff --git a/Cargo.toml b/Cargo.toml
index 1608a79..9ee7445 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -19,6 +19,8 @@ fayalite-proc-macros-impl = { version = "=0.2.0", path = "crates/fayalite-proc-m
 fayalite-visit-gen = { version = "=0.2.0", path = "crates/fayalite-visit-gen" }
 base16ct = "0.2.0"
 bitvec = { version = "1.0.1", features = ["serde"] }
+clap = { version = "4.5.9", features = ["derive", "env", "string"] }
+eyre = "0.6.12"
 hashbrown = "0.14.3"
 indexmap = { version = "2.2.6", features = ["serde"] }
 num-bigint = "0.4.4"
@@ -33,3 +35,4 @@ syn = { version = "2.0.66", features = ["full", "fold", "visit", "extra-traits"]
 tempfile = "3.10.1"
 thiserror = "1.0.61"
 trybuild = "1.0"
+which = "6.0.1"
diff --git a/crates/fayalite-proc-macros-impl/Cargo.toml b/crates/fayalite-proc-macros-impl/Cargo.toml
index 31c4465..d56f03d 100644
--- a/crates/fayalite-proc-macros-impl/Cargo.toml
+++ b/crates/fayalite-proc-macros-impl/Cargo.toml
@@ -13,11 +13,11 @@ rust-version.workspace = true
 version.workspace = true
 
 [dependencies]
-base16ct = { workspace = true }
-num-bigint = { workspace = true }
-prettyplease = { workspace = true }
-proc-macro2 = { workspace = true }
-quote = { workspace = true }
-sha2 = { workspace = true }
-syn = { workspace = true }
-tempfile = { workspace = true }
+base16ct.workspace = true
+num-bigint.workspace = true
+prettyplease.workspace = true
+proc-macro2.workspace = true
+quote.workspace = true
+sha2.workspace = true
+syn.workspace = true
+tempfile.workspace = true
diff --git a/crates/fayalite-proc-macros/Cargo.toml b/crates/fayalite-proc-macros/Cargo.toml
index 08c630a..6941d12 100644
--- a/crates/fayalite-proc-macros/Cargo.toml
+++ b/crates/fayalite-proc-macros/Cargo.toml
@@ -16,4 +16,4 @@ version.workspace = true
 proc-macro = true
 
 [dependencies]
-fayalite-proc-macros-impl = { workspace = true }
+fayalite-proc-macros-impl.workspace = true
diff --git a/crates/fayalite-visit-gen/Cargo.toml b/crates/fayalite-visit-gen/Cargo.toml
index 6da95d2..5a98947 100644
--- a/crates/fayalite-visit-gen/Cargo.toml
+++ b/crates/fayalite-visit-gen/Cargo.toml
@@ -13,11 +13,11 @@ rust-version.workspace = true
 version.workspace = true
 
 [dependencies]
-indexmap = { workspace = true }
-prettyplease = { workspace = true }
-proc-macro2 = { workspace = true }
-quote = { workspace = true }
-serde = { workspace = true }
-serde_json = { workspace = true }
-syn = { workspace = true }
-thiserror = { workspace = true }
+indexmap.workspace = true
+prettyplease.workspace = true
+proc-macro2.workspace = true
+quote.workspace = true
+serde.workspace = true
+serde_json.workspace = true
+syn.workspace = true
+thiserror.workspace = true
diff --git a/crates/fayalite/Cargo.toml b/crates/fayalite/Cargo.toml
index 555f7f5..55a29ad 100644
--- a/crates/fayalite/Cargo.toml
+++ b/crates/fayalite/Cargo.toml
@@ -14,22 +14,22 @@ rust-version.workspace = true
 version.workspace = true
 
 [dependencies]
-bitvec = { workspace = true }
-hashbrown = { workspace = true }
-num-bigint = { workspace = true }
-num-traits = { workspace = true }
-fayalite-proc-macros = { workspace = true }
-serde = { workspace = true }
-serde_json = { workspace = true }
-clap = { version = "4.5.9", features = ["derive", "env"] }
-eyre = "0.6.12"
-which = "6.0.1"
+bitvec.workspace = true
+clap.workspace = true
+eyre.workspace = true
+fayalite-proc-macros.workspace = true
+hashbrown.workspace = true
+num-bigint.workspace = true
+num-traits.workspace = true
+serde_json.workspace = true
+serde.workspace = true
+which.workspace = true
 
 [dev-dependencies]
-trybuild = { workspace = true }
+trybuild.workspace = true
 
 [build-dependencies]
-fayalite-visit-gen = { workspace = true }
+fayalite-visit-gen.workspace = true
 
 [features]
 unstable-doc = []

From f32c0a78636fb4c6527662ad3da97d61f765b0fb Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 25 Sep 2024 01:28:11 -0700
Subject: [PATCH 017/190] switch to #[derive(Parser)] instead of
 #[derive(Args)]

---
 crates/fayalite/src/cli.rs | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index 5071279..d1bbfb1 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -8,7 +8,7 @@ use crate::{
 };
 use clap::{
     builder::{OsStringValueParser, TypedValueParser},
-    Args, Parser, Subcommand, ValueEnum, ValueHint,
+    Parser, Subcommand, ValueEnum, ValueHint,
 };
 use eyre::{eyre, Report};
 use std::{error, ffi::OsString, fmt, io, path::PathBuf, process};
@@ -42,7 +42,7 @@ pub trait RunPhase<Arg> {
     fn run(&self, arg: Arg) -> Result<Self::Output>;
 }
 
-#[derive(Args, Debug)]
+#[derive(Parser, Debug, Clone)]
 #[non_exhaustive]
 pub struct BaseArgs {
     /// the directory to put the generated main output file and associated files in
@@ -62,7 +62,7 @@ impl BaseArgs {
     }
 }
 
-#[derive(Args, Debug)]
+#[derive(Parser, Debug, Clone)]
 #[non_exhaustive]
 pub struct FirrtlArgs {
     #[command(flatten)]
@@ -140,7 +140,7 @@ impl VerilogDialect {
     }
 }
 
-#[derive(Args, Debug)]
+#[derive(Parser, Debug, Clone)]
 #[non_exhaustive]
 pub struct VerilogArgs {
     #[command(flatten)]

From efc3a539ed771fcd9ec53a8dc231bc7268224000 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 25 Sep 2024 01:36:15 -0700
Subject: [PATCH 018/190] support redirecting subprocesses' stdout/stderr to
 print!() so it gets captured for rust tests

---
 Cargo.lock                                    | 73 +++++++++++++------
 Cargo.toml                                    |  1 +
 crates/fayalite/Cargo.toml                    |  1 +
 crates/fayalite/src/cli.rs                    | 33 ++++++++-
 crates/fayalite/src/util.rs                   |  1 +
 .../fayalite/src/util/streaming_read_utf8.rs  | 31 ++++++++
 6 files changed, 116 insertions(+), 24 deletions(-)
 create mode 100644 crates/fayalite/src/util/streaming_read_utf8.rs

diff --git a/Cargo.lock b/Cargo.lock
index 1c17ac7..1c237af 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -56,7 +56,7 @@ version = "1.1.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "ad186efb764318d35165f1758e7dcef3b10628e26d41a44bc5550652e6804391"
 dependencies = [
- "windows-sys",
+ "windows-sys 0.52.0",
 ]
 
 [[package]]
@@ -66,7 +66,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "61a38449feb7068f52bb06c12759005cf459ee52bb4adc1d5a7c4322d716fb19"
 dependencies = [
  "anstyle",
- "windows-sys",
+ "windows-sys 0.52.0",
 ]
 
 [[package]]
@@ -218,7 +218,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "a258e46cdc063eb8519c00b9fc845fc47bcfca4130e2f08e88665ceda8474245"
 dependencies = [
  "libc",
- "windows-sys",
+ "windows-sys 0.52.0",
 ]
 
 [[package]]
@@ -249,6 +249,7 @@ dependencies = [
  "hashbrown",
  "num-bigint",
  "num-traits",
+ "os_pipe",
  "serde",
  "serde_json",
  "trybuild",
@@ -334,7 +335,7 @@ version = "0.5.9"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "e3d1354bf6b7235cb4a0576c2619fd4ed18183f689b12b006a0ee7329eeff9a5"
 dependencies = [
- "windows-sys",
+ "windows-sys 0.52.0",
 ]
 
 [[package]]
@@ -413,6 +414,16 @@ version = "1.19.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "3fdb12b2476b595f9358c5161aa467c2438859caa136dec86c26fdd2efe17b92"
 
+[[package]]
+name = "os_pipe"
+version = "1.2.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5ffd2b0a5634335b135d5728d84c5e0fd726954b87111f7506a61c502280d982"
+dependencies = [
+ "libc",
+ "windows-sys 0.59.0",
+]
+
 [[package]]
 name = "prettyplease"
 version = "0.2.20"
@@ -457,7 +468,7 @@ dependencies = [
  "errno",
  "libc",
  "linux-raw-sys",
- "windows-sys",
+ "windows-sys 0.52.0",
 ]
 
 [[package]]
@@ -541,7 +552,7 @@ dependencies = [
  "cfg-if",
  "fastrand",
  "rustix",
- "windows-sys",
+ "windows-sys 0.52.0",
 ]
 
 [[package]]
@@ -665,14 +676,24 @@ dependencies = [
 ]
 
 [[package]]
-name = "windows-targets"
-version = "0.52.4"
+name = "windows-sys"
+version = "0.59.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7dd37b7e5ab9018759f893a1952c9420d060016fc19a472b4bb20d1bdd694d1b"
+checksum = "1e38bc4d79ed67fd075bcc251a1c39b32a1776bbe92e5bef1f0bf1f8c531853b"
+dependencies = [
+ "windows-targets",
+]
+
+[[package]]
+name = "windows-targets"
+version = "0.52.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9b724f72796e036ab90c1021d4780d4d3d648aca59e491e6b98e725b84e99973"
 dependencies = [
  "windows_aarch64_gnullvm",
  "windows_aarch64_msvc",
  "windows_i686_gnu",
+ "windows_i686_gnullvm",
  "windows_i686_msvc",
  "windows_x86_64_gnu",
  "windows_x86_64_gnullvm",
@@ -681,45 +702,51 @@ dependencies = [
 
 [[package]]
 name = "windows_aarch64_gnullvm"
-version = "0.52.4"
+version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "bcf46cf4c365c6f2d1cc93ce535f2c8b244591df96ceee75d8e83deb70a9cac9"
+checksum = "32a4622180e7a0ec044bb555404c800bc9fd9ec262ec147edd5989ccd0c02cd3"
 
 [[package]]
 name = "windows_aarch64_msvc"
-version = "0.52.4"
+version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "da9f259dd3bcf6990b55bffd094c4f7235817ba4ceebde8e6d11cd0c5633b675"
+checksum = "09ec2a7bb152e2252b53fa7803150007879548bc709c039df7627cabbd05d469"
 
 [[package]]
 name = "windows_i686_gnu"
-version = "0.52.4"
+version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b474d8268f99e0995f25b9f095bc7434632601028cf86590aea5c8a5cb7801d3"
+checksum = "8e9b5ad5ab802e97eb8e295ac6720e509ee4c243f69d781394014ebfe8bbfa0b"
+
+[[package]]
+name = "windows_i686_gnullvm"
+version = "0.52.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0eee52d38c090b3caa76c563b86c3a4bd71ef1a819287c19d586d7334ae8ed66"
 
 [[package]]
 name = "windows_i686_msvc"
-version = "0.52.4"
+version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1515e9a29e5bed743cb4415a9ecf5dfca648ce85ee42e15873c3cd8610ff8e02"
+checksum = "240948bc05c5e7c6dabba28bf89d89ffce3e303022809e73deaefe4f6ec56c66"
 
 [[package]]
 name = "windows_x86_64_gnu"
-version = "0.52.4"
+version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5eee091590e89cc02ad514ffe3ead9eb6b660aedca2183455434b93546371a03"
+checksum = "147a5c80aabfbf0c7d901cb5895d1de30ef2907eb21fbbab29ca94c5b08b1a78"
 
 [[package]]
 name = "windows_x86_64_gnullvm"
-version = "0.52.4"
+version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "77ca79f2451b49fa9e2af39f0747fe999fcda4f5e241b2898624dca97a1f2177"
+checksum = "24d5b23dc417412679681396f2b49f3de8c1473deb516bd34410872eff51ed0d"
 
 [[package]]
 name = "windows_x86_64_msvc"
-version = "0.52.4"
+version = "0.52.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "32b752e52a2da0ddfbdbcc6fceadfeede4c939ed16d13e648833a61dfb611ed8"
+checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec"
 
 [[package]]
 name = "winsafe"
diff --git a/Cargo.toml b/Cargo.toml
index 9ee7445..15d13b6 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -25,6 +25,7 @@ hashbrown = "0.14.3"
 indexmap = { version = "2.2.6", features = ["serde"] }
 num-bigint = "0.4.4"
 num-traits = "0.2.16"
+os_pipe = "1.2.1"
 prettyplease = "0.2.20"
 proc-macro2 = "1.0.83"
 quote = "1.0.36"
diff --git a/crates/fayalite/Cargo.toml b/crates/fayalite/Cargo.toml
index 55a29ad..2306e7a 100644
--- a/crates/fayalite/Cargo.toml
+++ b/crates/fayalite/Cargo.toml
@@ -21,6 +21,7 @@ fayalite-proc-macros.workspace = true
 hashbrown.workspace = true
 num-bigint.workspace = true
 num-traits.workspace = true
+os_pipe.workspace = true
 serde_json.workspace = true
 serde.workspace = true
 which.workspace = true
diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index d1bbfb1..1dbf85f 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -5,6 +5,7 @@ use crate::{
     firrtl,
     intern::Interned,
     module::Module,
+    util::streaming_read_utf8::streaming_read_utf8,
 };
 use clap::{
     builder::{OsStringValueParser, TypedValueParser},
@@ -51,6 +52,8 @@ pub struct BaseArgs {
     /// the stem of the generated main output file, e.g. to get foo.v, pass --file-stem=foo
     #[arg(long)]
     pub file_stem: Option<String>,
+    #[arg(skip = false)]
+    pub redirect_output_for_rust_test: bool,
 }
 
 impl BaseArgs {
@@ -60,6 +63,34 @@ impl BaseArgs {
             top_fir_file_stem: self.file_stem.clone(),
         }
     }
+    /// handles possibly redirecting the command's output for Rust tests
+    pub fn run_external_command(
+        &self,
+        mut command: process::Command,
+    ) -> io::Result<process::ExitStatus> {
+        if self.redirect_output_for_rust_test {
+            let (reader, writer) = os_pipe::pipe()?;
+            let mut reader = io::BufReader::new(reader);
+            command.stderr(writer.try_clone()?);
+            command.stdout(writer); // must not leave writer around after spawning child
+            command.stdin(process::Stdio::null());
+            let mut child = command.spawn()?;
+            drop(command); // close writers
+            Ok(loop {
+                let status = child.try_wait()?;
+                streaming_read_utf8(&mut reader, |s| {
+                    // use print! so output goes to Rust test output capture
+                    print!("{s}");
+                    io::Result::Ok(())
+                })?;
+                if let Some(status) = status {
+                    break status;
+                }
+            })
+        } else {
+            command.status()
+        }
+    }
 }
 
 #[derive(Parser, Debug, Clone)]
@@ -188,7 +219,7 @@ impl VerilogArgs {
         }
         cmd.args(&self.firtool_extra_args);
         cmd.current_dir(&self.firrtl.base.output);
-        let status = cmd.status()?;
+        let status = self.firrtl.base.run_external_command(cmd)?;
         if status.success() {
             Ok(output)
         } else {
diff --git a/crates/fayalite/src/util.rs b/crates/fayalite/src/util.rs
index 5b97e3b..95f5793 100644
--- a/crates/fayalite/src/util.rs
+++ b/crates/fayalite/src/util.rs
@@ -6,6 +6,7 @@ mod const_cmp;
 mod const_usize;
 mod misc;
 mod scoped_ref;
+pub(crate) mod streaming_read_utf8;
 
 #[doc(inline)]
 pub use const_bool::{ConstBool, ConstBoolDispatch, ConstBoolDispatchTag, GenericConstBool};
diff --git a/crates/fayalite/src/util/streaming_read_utf8.rs b/crates/fayalite/src/util/streaming_read_utf8.rs
new file mode 100644
index 0000000..bd8bdc8
--- /dev/null
+++ b/crates/fayalite/src/util/streaming_read_utf8.rs
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+use std::{
+    io::{self, BufRead},
+    str,
+};
+
+pub(crate) fn streaming_read_utf8<R: BufRead, E: From<io::Error>>(
+    reader: R,
+    mut callback: impl FnMut(&str) -> Result<(), E>,
+) -> Result<(), E> {
+    let mut buf = [0; 4];
+    let mut buf_len = 0;
+    for byte in reader.bytes() {
+        buf[buf_len] = byte?;
+        buf_len += 1;
+        match str::from_utf8(&buf[..buf_len]) {
+            Ok(buf) => {
+                callback(buf)?;
+                buf_len = 0;
+            }
+            Err(e) => {
+                if e.error_len().is_some() {
+                    callback("\u{FFFD}")?; // replacement character
+                    buf_len = 0;
+                }
+            }
+        }
+    }
+    Ok(())
+}

From bb860d54ccba824a26427b02cc5888dafd9745de Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 25 Sep 2024 01:47:48 -0700
Subject: [PATCH 019/190] add command line options for selecting which
 transforms to apply when generating firrtl

---
 crates/fayalite/src/cli.rs                    |   6 +-
 crates/fayalite/src/firrtl.rs                 | 133 ++++++++++++++++--
 .../src/module/transform/simplify_enums.rs    |  10 +-
 3 files changed, 137 insertions(+), 12 deletions(-)

diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index 1dbf85f..c171c22 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -2,7 +2,7 @@
 // See Notices.txt for copyright information
 use crate::{
     bundle::{Bundle, BundleType},
-    firrtl,
+    firrtl::{self, ExportOptions},
     intern::Interned,
     module::Module,
     util::streaming_read_utf8::streaming_read_utf8,
@@ -98,6 +98,8 @@ impl BaseArgs {
 pub struct FirrtlArgs {
     #[command(flatten)]
     pub base: BaseArgs,
+    #[command(flatten)]
+    pub export_options: ExportOptions,
 }
 
 #[derive(Debug)]
@@ -118,7 +120,7 @@ impl FirrtlArgs {
     fn run_impl(&self, top_module: Module<Bundle>) -> Result<FirrtlOutput> {
         let firrtl::FileBackend {
             top_fir_file_stem, ..
-        } = firrtl::export(self.base.to_firrtl_file_backend(), &top_module)?;
+        } = firrtl::export(self.base.to_firrtl_file_backend(), &top_module, self.export_options)?;
         Ok(FirrtlOutput {
             file_stem: top_fir_file_stem.expect(
                 "export is known to set the file stem from the circuit name if not provided",
diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index b8ba89a..ba37bcc 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -18,10 +18,14 @@ use crate::{
     intern::{Intern, Interned},
     memory::{Mem, PortKind, PortName, ReadUnderWrite},
     module::{
-        transform::simplify_memories::simplify_memories, AnnotatedModuleIO, Block,
-        ExternModuleBody, ExternModuleParameter, ExternModuleParameterValue, Module, ModuleBody,
-        NameId, NormalModuleBody, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtFormalKind,
-        StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire,
+        transform::{
+            simplify_enums::{simplify_enums, SimplifyEnumsError, SimplifyEnumsKind},
+            simplify_memories::simplify_memories,
+        },
+        AnnotatedModuleIO, Block, ExternModuleBody, ExternModuleParameter,
+        ExternModuleParameterValue, Module, ModuleBody, NameId, NormalModuleBody, Stmt,
+        StmtConnect, StmtDeclaration, StmtFormal, StmtFormalKind, StmtIf, StmtInstance, StmtMatch,
+        StmtReg, StmtWire,
     },
     reset::{AsyncReset, Reset, SyncReset},
     source_location::SourceLocation,
@@ -32,6 +36,7 @@ use crate::{
     },
 };
 use bitvec::slice::BitSlice;
+use clap::value_parser;
 use hashbrown::{HashMap, HashSet};
 use num_traits::Signed;
 use serde::Serialize;
@@ -476,6 +481,7 @@ trait WrappedFileBackendTrait {
         circuit_name: String,
         contents: String,
     ) -> Result<(), WrappedError>;
+    fn simplify_enums_error(&mut self, error: SimplifyEnumsError) -> WrappedError;
 }
 
 struct WrappedFileBackend<B: FileBackendTrait> {
@@ -533,6 +539,11 @@ impl<B: FileBackendTrait> WrappedFileBackendTrait for WrappedFileBackend<B> {
                 WrappedError
             })
     }
+
+    fn simplify_enums_error(&mut self, error: SimplifyEnumsError) -> WrappedError {
+        self.error = Err(error.into());
+        WrappedError
+    }
 }
 
 #[derive(Clone)]
@@ -2225,7 +2236,7 @@ impl<'a> Exporter<'a> {
 }
 
 pub trait FileBackendTrait {
-    type Error;
+    type Error: From<SimplifyEnumsError>;
     type Path: AsRef<Self::Path> + fmt::Debug + ?Sized;
     type PathBuf: AsRef<Self::Path> + fmt::Debug;
     fn path_to_string(&mut self, path: &Self::Path) -> Result<String, Self::Error>;
@@ -2370,6 +2381,7 @@ impl Default for TestBackendPrivate {
 pub struct TestBackend {
     pub files: BTreeMap<String, String>,
     pub error_after: Option<i64>,
+    pub options: ExportOptions,
     #[doc(hidden)]
     /// `#[non_exhaustive]` except allowing struct update syntax
     pub __private: TestBackendPrivate,
@@ -2380,6 +2392,7 @@ impl fmt::Debug for TestBackend {
         let Self {
             files,
             error_after,
+            options,
             __private: TestBackendPrivate { module_var_name },
         } = self;
         writeln!(
@@ -2394,6 +2407,9 @@ impl fmt::Debug for TestBackend {
         if *error_after != Option::default() {
             writeln!(f, "        error_after: {error_after:?},")?;
         }
+        if *options != ExportOptions::default() {
+            writeln!(f, "        options: {options:?},")?;
+        }
         write!(f, "    }};")
     }
 }
@@ -2409,6 +2425,12 @@ impl fmt::Display for TestBackendError {
 
 impl Error for TestBackendError {}
 
+impl From<SimplifyEnumsError> for TestBackendError {
+    fn from(value: SimplifyEnumsError) -> Self {
+        TestBackendError(value.to_string())
+    }
+}
+
 impl TestBackend {
     #[track_caller]
     pub fn step_error_after(&mut self, args: &dyn fmt::Debug) -> Result<(), TestBackendError> {
@@ -2465,9 +2487,20 @@ impl FileBackendTrait for TestBackend {
 
 fn export_impl(
     file_backend: &mut dyn WrappedFileBackendTrait,
-    top_module: Interned<Module<Bundle>>,
+    mut top_module: Interned<Module<Bundle>>,
+    options: ExportOptions,
 ) -> Result<(), WrappedError> {
-    let top_module = simplify_memories(top_module);
+    let ExportOptions {
+        simplify_memories: do_simplify_memories,
+        simplify_enums: do_simplify_enums,
+    } = options;
+    if let Some(kind) = do_simplify_enums {
+        top_module =
+            simplify_enums(top_module, kind).map_err(|e| file_backend.simplify_enums_error(e))?;
+    }
+    if do_simplify_memories {
+        top_module = simplify_memories(top_module);
+    }
     let indent_depth = Cell::new(0);
     let mut global_ns = Namespace::default();
     let circuit_name = global_ns.get(top_module.name_id());
@@ -2488,20 +2521,102 @@ fn export_impl(
     .run(top_module)
 }
 
+#[derive(Clone)]
+struct OptionSimplifyEnumsKindValueParser;
+
+impl OptionSimplifyEnumsKindValueParser {
+    const NONE_NAME: &'static str = "off";
+}
+
+impl clap::builder::TypedValueParser for OptionSimplifyEnumsKindValueParser {
+    type Value = Option<SimplifyEnumsKind>;
+
+    fn parse_ref(
+        &self,
+        cmd: &clap::Command,
+        arg: Option<&clap::Arg>,
+        value: &std::ffi::OsStr,
+    ) -> Result<Self::Value, clap::Error> {
+        if value == Self::NONE_NAME {
+            Ok(None)
+        } else {
+            Ok(Some(
+                value_parser!(SimplifyEnumsKind).parse_ref(cmd, arg, value)?,
+            ))
+        }
+    }
+
+    fn possible_values(
+        &self,
+    ) -> Option<Box<dyn Iterator<Item = clap::builder::PossibleValue> + '_>> {
+        Some(Box::new(
+            [Self::NONE_NAME.into()]
+                .into_iter()
+                .chain(value_parser!(SimplifyEnumsKind).possible_values()?)
+                .collect::<Vec<_>>()
+                .into_iter(),
+        ))
+    }
+}
+
+#[derive(clap::Parser, Copy, Clone, PartialEq, Eq, Hash)]
+#[non_exhaustive]
+pub struct ExportOptions {
+    #[clap(long = "no-simplify-memories", action = clap::ArgAction::SetFalse)]
+    pub simplify_memories: bool,
+    #[clap(long, value_parser = OptionSimplifyEnumsKindValueParser, default_value = OptionSimplifyEnumsKindValueParser::NONE_NAME)]
+    pub simplify_enums: std::option::Option<SimplifyEnumsKind>,
+}
+
+impl fmt::Debug for ExportOptions {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.write_str("ExportOptions {")?;
+        if f.alternate() {
+            f.write_str("\n")?;
+        }
+        let mut sep = if f.alternate() { "\n    " } else { " " };
+        let comma_sep = if f.alternate() { ",\n    " } else { ", " };
+        let default = ExportOptions::default();
+        if self.simplify_memories != default.simplify_memories {
+            write!(f, "{sep}simplify_memories: {:?}", self.simplify_memories)?;
+            sep = comma_sep;
+        }
+        if self.simplify_enums != default.simplify_enums {
+            write!(f, "{sep}simplify_enums: {:?}", self.simplify_enums)?;
+            sep = comma_sep;
+        }
+        write!(
+            f,
+            "{sep}..ExportOptions::default(){}",
+            if f.alternate() { "\n}" } else { " }" }
+        )
+    }
+}
+
+impl Default for ExportOptions {
+    fn default() -> Self {
+        Self {
+            simplify_memories: true,
+            simplify_enums: None,
+        }
+    }
+}
+
 pub fn export<T: BundleType, B: FileBackendTrait>(
     file_backend: B,
     top_module: &Module<T>,
+    options: ExportOptions,
 ) -> Result<B, B::Error> {
     let top_module = Intern::intern_sized(top_module.canonical());
     WrappedFileBackend::with(file_backend, |file_backend| {
-        export_impl(file_backend, top_module)
+        export_impl(file_backend, top_module, options)
     })
 }
 
 #[doc(hidden)]
 #[track_caller]
 pub fn assert_export_firrtl_impl<T: BundleType>(top_module: &Module<T>, expected: TestBackend) {
-    let result = export(TestBackend::default(), top_module).unwrap();
+    let result = export(TestBackend::default(), top_module, expected.options).unwrap();
     if result != expected {
         panic!(
             "assert_export_firrtl failed:\nyou can update the expected output by using:\n-------START-------\n{result:?}\n-------END-------"
diff --git a/crates/fayalite/src/module/transform/simplify_enums.rs b/crates/fayalite/src/module/transform/simplify_enums.rs
index c817e45..cf85875 100644
--- a/crates/fayalite/src/module/transform/simplify_enums.rs
+++ b/crates/fayalite/src/module/transform/simplify_enums.rs
@@ -41,6 +41,12 @@ impl fmt::Display for SimplifyEnumsError {
 
 impl std::error::Error for SimplifyEnumsError {}
 
+impl From<SimplifyEnumsError> for std::io::Error {
+    fn from(value: SimplifyEnumsError) -> Self {
+        std::io::Error::new(std::io::ErrorKind::Other, value)
+    }
+}
+
 #[hdl]
 struct TagAndBody<T, BodyWidth: Size> {
     tag: T,
@@ -595,10 +601,12 @@ impl Folder for State {
     }
 }
 
-#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, clap::ValueEnum)]
 pub enum SimplifyEnumsKind {
     SimplifyToEnumsWithNoBody,
+    #[clap(name = "replace-with-bundle-of-uints")]
     ReplaceWithBundleOfUInts,
+    #[clap(name = "replace-with-uint")]
     ReplaceWithUInt,
 }
 

From 45dbb554d07e8a0ea05b0e88ae79bc88f616f968 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 25 Sep 2024 01:52:41 -0700
Subject: [PATCH 020/190] add formal subcommand

---
 Cargo.lock                    |   1 +
 crates/fayalite/Cargo.toml    |   1 +
 crates/fayalite/src/cli.rs    | 312 +++++++++++++++++++++++++++++++---
 crates/fayalite/src/firrtl.rs |   7 +-
 4 files changed, 297 insertions(+), 24 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 1c237af..fa6fb6b 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -252,6 +252,7 @@ dependencies = [
  "os_pipe",
  "serde",
  "serde_json",
+ "tempfile",
  "trybuild",
  "which",
 ]
diff --git a/crates/fayalite/Cargo.toml b/crates/fayalite/Cargo.toml
index 2306e7a..21089c0 100644
--- a/crates/fayalite/Cargo.toml
+++ b/crates/fayalite/Cargo.toml
@@ -24,6 +24,7 @@ num-traits.workspace = true
 os_pipe.workspace = true
 serde_json.workspace = true
 serde.workspace = true
+tempfile.workspace = true
 which.workspace = true
 
 [dev-dependencies]
diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index c171c22..a771de6 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -13,6 +13,7 @@ use clap::{
 };
 use eyre::{eyre, Report};
 use std::{error, ffi::OsString, fmt, io, path::PathBuf, process};
+use tempfile::TempDir;
 
 pub type Result<T = (), E = CliError> = std::result::Result<T, E>;
 
@@ -47,21 +48,40 @@ pub trait RunPhase<Arg> {
 #[non_exhaustive]
 pub struct BaseArgs {
     /// the directory to put the generated main output file and associated files in
-    #[arg(short, long, value_hint = ValueHint::DirPath)]
-    pub output: PathBuf,
+    #[arg(short, long, value_hint = ValueHint::DirPath, required = true)]
+    pub output: Option<PathBuf>,
     /// the stem of the generated main output file, e.g. to get foo.v, pass --file-stem=foo
     #[arg(long)]
     pub file_stem: Option<String>,
+    #[arg(long, env = "FAYALITE_KEEP_TEMP_DIR")]
+    pub keep_temp_dir: bool,
     #[arg(skip = false)]
     pub redirect_output_for_rust_test: bool,
 }
 
 impl BaseArgs {
-    pub fn to_firrtl_file_backend(&self) -> firrtl::FileBackend {
-        firrtl::FileBackend {
-            dir_path: self.output.clone(),
-            top_fir_file_stem: self.file_stem.clone(),
-        }
+    fn make_firrtl_file_backend(&self) -> Result<(firrtl::FileBackend, Option<TempDir>)> {
+        let (dir_path, temp_dir) = match &self.output {
+            Some(output) => (output.clone(), None),
+            None => {
+                let temp_dir = TempDir::new()?;
+                if self.keep_temp_dir {
+                    let temp_dir = temp_dir.into_path();
+                    println!("created temporary directory: {}", temp_dir.display());
+                    (temp_dir, None)
+                } else {
+                    (temp_dir.path().to_path_buf(), Some(temp_dir))
+                }
+            }
+        };
+        Ok((
+            firrtl::FileBackend {
+                dir_path,
+                top_fir_file_stem: self.file_stem.clone(),
+                circuit_name: None,
+            },
+            temp_dir,
+        ))
     }
     /// handles possibly redirecting the command's output for Rust tests
     pub fn run_external_command(
@@ -106,25 +126,37 @@ pub struct FirrtlArgs {
 #[non_exhaustive]
 pub struct FirrtlOutput {
     pub file_stem: String,
+    pub top_module: String,
+    pub output_dir: PathBuf,
+    pub temp_dir: Option<TempDir>,
 }
 
 impl FirrtlOutput {
-    pub fn firrtl_file(&self, args: &FirrtlArgs) -> PathBuf {
-        let mut retval = args.base.output.join(&self.file_stem);
-        retval.set_extension("fir");
+    pub fn file_with_ext(&self, ext: &str) -> PathBuf {
+        let mut retval = self.output_dir.join(&self.file_stem);
+        retval.set_extension(ext);
         retval
     }
+    pub fn firrtl_file(&self) -> PathBuf {
+        self.file_with_ext("fir")
+    }
 }
 
 impl FirrtlArgs {
     fn run_impl(&self, top_module: Module<Bundle>) -> Result<FirrtlOutput> {
+        let (file_backend, temp_dir) = self.base.make_firrtl_file_backend()?;
         let firrtl::FileBackend {
-            top_fir_file_stem, ..
-        } = firrtl::export(self.base.to_firrtl_file_backend(), &top_module, self.export_options)?;
+            top_fir_file_stem,
+            circuit_name,
+            dir_path,
+        } = firrtl::export(file_backend, &top_module, self.export_options)?;
         Ok(FirrtlOutput {
             file_stem: top_fir_file_stem.expect(
                 "export is known to set the file stem from the circuit name if not provided",
             ),
+            top_module: circuit_name.expect("export is known to set the circuit name"),
+            output_dir: dir_path,
+            temp_dir,
         })
     }
 }
@@ -155,7 +187,22 @@ pub enum VerilogDialect {
     Yosys,
 }
 
+impl fmt::Display for VerilogDialect {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.write_str(self.as_str())
+    }
+}
+
 impl VerilogDialect {
+    pub fn as_str(self) -> &'static str {
+        match self {
+            VerilogDialect::Questa => "questa",
+            VerilogDialect::Spyglass => "spyglass",
+            VerilogDialect::Verilator => "verilator",
+            VerilogDialect::Vivado => "vivado",
+            VerilogDialect::Yosys => "yosys",
+        }
+    }
     pub fn firtool_extra_args(self) -> &'static [&'static str] {
         match self {
             VerilogDialect::Questa => &["--lowering-options=emitWireInPorts"],
@@ -191,6 +238,8 @@ pub struct VerilogArgs {
     /// adapt the generated Verilog for a particular toolchain
     #[arg(long)]
     pub verilog_dialect: Option<VerilogDialect>,
+    #[arg(long, short = 'g')]
+    pub debug: bool,
 }
 
 #[derive(Debug)]
@@ -200,28 +249,37 @@ pub struct VerilogOutput {
 }
 
 impl VerilogOutput {
-    pub fn verilog_file(&self, args: &VerilogArgs) -> PathBuf {
-        let mut retval = args.firrtl.base.output.join(&self.firrtl.file_stem);
-        retval.set_extension("v");
-        retval
+    pub fn verilog_file(&self) -> PathBuf {
+        self.firrtl.file_with_ext("v")
     }
 }
 
 impl VerilogArgs {
     fn run_impl(&self, firrtl_output: FirrtlOutput) -> Result<VerilogOutput> {
+        let Self {
+            firrtl,
+            firtool,
+            firtool_extra_args,
+            verilog_dialect,
+            debug,
+        } = self;
         let output = VerilogOutput {
             firrtl: firrtl_output,
         };
-        let mut cmd = process::Command::new(&self.firtool);
-        cmd.arg(output.firrtl.firrtl_file(&self.firrtl));
+        let mut cmd = process::Command::new(firtool);
+        cmd.arg(output.firrtl.firrtl_file());
         cmd.arg("-o");
-        cmd.arg(output.verilog_file(self));
-        if let Some(dialect) = self.verilog_dialect {
+        cmd.arg(output.verilog_file());
+        if *debug {
+            cmd.arg("-g");
+            cmd.arg("--preserve-values=named");
+        }
+        if let Some(dialect) = verilog_dialect {
             cmd.args(dialect.firtool_extra_args());
         }
-        cmd.args(&self.firtool_extra_args);
-        cmd.current_dir(&self.firrtl.base.output);
-        let status = self.firrtl.base.run_external_command(cmd)?;
+        cmd.args(firtool_extra_args);
+        cmd.current_dir(&output.firrtl.output_dir);
+        let status = firrtl.base.run_external_command(cmd)?;
         if status.success() {
             Ok(output)
         } else {
@@ -244,12 +302,217 @@ where
     }
 }
 
+#[derive(ValueEnum, Copy, Clone, Debug, PartialEq, Eq, Hash, Default)]
+#[non_exhaustive]
+pub enum FormalMode {
+    #[default]
+    BMC,
+    Prove,
+    Live,
+    Cover,
+}
+
+impl FormalMode {
+    pub fn as_str(self) -> &'static str {
+        match self {
+            FormalMode::BMC => "bmc",
+            FormalMode::Prove => "prove",
+            FormalMode::Live => "live",
+            FormalMode::Cover => "cover",
+        }
+    }
+}
+
+impl fmt::Display for FormalMode {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.write_str(self.as_str())
+    }
+}
+
+#[derive(Clone)]
+struct FormalAdjustArgs;
+
+impl clap::FromArgMatches for FormalAdjustArgs {
+    fn from_arg_matches(_matches: &clap::ArgMatches) -> Result<Self, clap::Error> {
+        Ok(Self)
+    }
+
+    fn update_from_arg_matches(&mut self, _matches: &clap::ArgMatches) -> Result<(), clap::Error> {
+        Ok(())
+    }
+}
+
+impl clap::Args for FormalAdjustArgs {
+    fn augment_args(cmd: clap::Command) -> clap::Command {
+        cmd.mut_arg("output", |arg| arg.required(false))
+            .mut_arg("verilog_dialect", |arg| {
+                arg.default_value(VerilogDialect::Yosys.to_string())
+                    .hide(true)
+            })
+    }
+
+    fn augment_args_for_update(cmd: clap::Command) -> clap::Command {
+        Self::augment_args(cmd)
+    }
+}
+
+#[derive(Parser, Clone)]
+#[non_exhaustive]
+pub struct FormalArgs {
+    #[command(flatten)]
+    pub verilog: VerilogArgs,
+    #[arg(
+        long,
+        default_value = "sby",
+        env = "SBY",
+        value_hint = ValueHint::CommandName,
+        value_parser = OsStringValueParser::new().try_map(which::which)
+    )]
+    pub sby: PathBuf,
+    #[arg(long)]
+    pub sby_extra_args: Vec<OsString>,
+    #[arg(long, default_value_t)]
+    pub mode: FormalMode,
+    #[arg(long, default_value_t = Self::DEFAULT_DEPTH)]
+    pub depth: u64,
+    #[arg(long)]
+    pub solver: Option<String>,
+    #[arg(long)]
+    pub smtbmc_extra_args: Vec<String>,
+    #[command(flatten)]
+    _formal_adjust_args: FormalAdjustArgs,
+}
+
+impl fmt::Debug for FormalArgs {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            verilog,
+            sby,
+            sby_extra_args,
+            mode,
+            depth,
+            solver,
+            smtbmc_extra_args,
+            _formal_adjust_args: _,
+        } = self;
+        f.debug_struct("FormalArgs")
+            .field("verilog", &verilog)
+            .field("sby", &sby)
+            .field("sby_extra_args", &sby_extra_args)
+            .field("mode", &mode)
+            .field("depth", &depth)
+            .field("solver", &solver)
+            .field("smtbmc_extra_args", &smtbmc_extra_args)
+            .finish_non_exhaustive()
+    }
+}
+
+impl FormalArgs {
+    pub const DEFAULT_DEPTH: u64 = 20;
+}
+
+#[derive(Debug)]
+#[non_exhaustive]
+pub struct FormalOutput {
+    pub verilog: VerilogOutput,
+}
+
+impl FormalOutput {
+    pub fn sby_file(&self) -> PathBuf {
+        self.verilog.firrtl.file_with_ext("sby")
+    }
+}
+
+impl FormalArgs {
+    fn sby_contents(&self, output: &FormalOutput) -> String {
+        let Self {
+            verilog: _,
+            sby: _,
+            sby_extra_args: _,
+            mode,
+            depth,
+            smtbmc_extra_args,
+            solver,
+            _formal_adjust_args: _,
+        } = self;
+        struct OptArg<T>(Option<T>);
+        impl<T: fmt::Display> fmt::Display for OptArg<T> {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                if let Some(v) = &self.0 {
+                    f.write_str(" ")?;
+                    v.fmt(f)
+                } else {
+                    Ok(())
+                }
+            }
+        }
+        let space_solver = OptArg(solver.as_ref());
+        let smtbmc_options = smtbmc_extra_args.join(" ");
+        let verilog_file = output
+            .verilog
+            .verilog_file()
+            .into_os_string()
+            .into_string()
+            .ok()
+            .expect("verilog file path is not UTF-8");
+        let top_module = &output.verilog.firrtl.top_module;
+        format!(
+            "[options]\n\
+            mode {mode}\n\
+            depth {depth}\n\
+            wait on\n\
+            \n\
+            [engines]\n\
+            smtbmc{space_solver} -- -- {smtbmc_options}\n\
+            \n\
+            [script]\n\
+            read_verilog -sv -formal {verilog_file}\n\
+            prep -top {top_module}\n
+            "
+        )
+    }
+    fn run_impl(&self, verilog_output: VerilogOutput) -> Result<FormalOutput> {
+        let output = FormalOutput {
+            verilog: verilog_output,
+        };
+        let sby_file = output.sby_file();
+        std::fs::write(&sby_file, self.sby_contents(&output))?;
+        let mut cmd = process::Command::new(&self.sby);
+        cmd.arg("-f");
+        cmd.arg(sby_file);
+        cmd.args(&self.sby_extra_args);
+        cmd.current_dir(&output.verilog.firrtl.output_dir);
+        let status = self.verilog.firrtl.base.run_external_command(cmd)?;
+        if status.success() {
+            Ok(output)
+        } else {
+            Err(CliError(eyre!(
+                "running {} failed: {status}",
+                self.sby.display()
+            )))
+        }
+    }
+}
+
+impl<Arg> RunPhase<Arg> for FormalArgs
+where
+    VerilogArgs: RunPhase<Arg, Output = VerilogOutput>,
+{
+    type Output = FormalOutput;
+    fn run(&self, arg: Arg) -> Result<Self::Output> {
+        let verilog_output = self.verilog.run(arg)?;
+        self.run_impl(verilog_output)
+    }
+}
+
 #[derive(Subcommand, Debug)]
 enum CliCommand {
     /// Generate FIRRTL
     Firrtl(FirrtlArgs),
     /// Generate Verilog
     Verilog(VerilogArgs),
+    /// Run a formal proof
+    Formal(FormalArgs),
 }
 
 /// a simple CLI
@@ -335,6 +598,9 @@ where
             CliCommand::Verilog(c) => {
                 c.run(arg)?;
             }
+            CliCommand::Formal(c) => {
+                c.run(arg)?;
+            }
         }
         Ok(())
     }
diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index ba37bcc..4a1547d 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -2311,6 +2311,7 @@ impl<T: ?Sized + FileBackendTrait> FileBackendTrait for &'_ mut T {
 #[non_exhaustive]
 pub struct FileBackend {
     pub dir_path: PathBuf,
+    pub circuit_name: Option<String>,
     pub top_fir_file_stem: Option<String>,
 }
 
@@ -2318,6 +2319,7 @@ impl FileBackend {
     pub fn new(dir_path: impl AsRef<Path>) -> Self {
         Self {
             dir_path: dir_path.as_ref().to_owned(),
+            circuit_name: None,
             top_fir_file_stem: None,
         }
     }
@@ -2353,7 +2355,10 @@ impl FileBackendTrait for FileBackend {
         circuit_name: String,
         contents: String,
     ) -> Result<(), Self::Error> {
-        let top_fir_file_stem = self.top_fir_file_stem.get_or_insert(circuit_name);
+        let top_fir_file_stem = self
+            .top_fir_file_stem
+            .get_or_insert_with(|| circuit_name.clone());
+        self.circuit_name = Some(circuit_name);
         let mut path = self.dir_path.join(top_fir_file_stem);
         if let Some(parent) = path.parent().filter(|v| !v.as_os_str().is_empty()) {
             fs::create_dir_all(parent)?;

From 5fc7dbd6e9a6c698d817643cb8ff670310614d40 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 25 Sep 2024 01:54:07 -0700
Subject: [PATCH 021/190] add assert_formal helper for running formal proofs in
 rust tests

---
 crates/fayalite/src/lib.rs     |  1 +
 crates/fayalite/src/testing.rs | 36 ++++++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+)
 create mode 100644 crates/fayalite/src/testing.rs

diff --git a/crates/fayalite/src/lib.rs b/crates/fayalite/src/lib.rs
index 83b61b2..70ce724 100644
--- a/crates/fayalite/src/lib.rs
+++ b/crates/fayalite/src/lib.rs
@@ -50,4 +50,5 @@ pub mod ty;
 pub mod util;
 //pub mod valueless;
 pub mod prelude;
+pub mod testing;
 pub mod wire;
diff --git a/crates/fayalite/src/testing.rs b/crates/fayalite/src/testing.rs
new file mode 100644
index 0000000..8046f05
--- /dev/null
+++ b/crates/fayalite/src/testing.rs
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+use crate::{
+    cli::{FormalArgs, FormalMode, FormalOutput, RunPhase},
+    firrtl::ExportOptions,
+};
+use clap::Parser;
+use std::sync::OnceLock;
+
+fn assert_formal_helper() -> FormalArgs {
+    static FORMAL_ARGS: OnceLock<FormalArgs> = OnceLock::new();
+    // ensure we only run parsing once, so errors from env vars don't produce overlapping output if we're called on multiple threads
+    FORMAL_ARGS
+        .get_or_init(|| FormalArgs::parse_from(["fayalite::testing::assert_formal"]))
+        .clone()
+}
+
+#[track_caller]
+pub fn assert_formal<M>(
+    module: M,
+    mode: FormalMode,
+    depth: u64,
+    solver: Option<&str>,
+    export_options: ExportOptions,
+) where
+    FormalArgs: RunPhase<M, Output = FormalOutput>,
+{
+    let mut args = assert_formal_helper();
+    args.verilog.firrtl.base.redirect_output_for_rust_test = true;
+    args.verilog.firrtl.export_options = export_options;
+    args.verilog.debug = true;
+    args.mode = mode;
+    args.depth = depth;
+    args.solver = solver.map(String::from);
+    args.run(module).expect("testing::assert_formal() failed");
+}

From e661aeab114312c6ec74b27c18ba1c89394254e4 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 25 Sep 2024 01:55:48 -0700
Subject: [PATCH 022/190] add WIP formal proof for queue()

---
 crates/fayalite/src/util/ready_valid.rs | 103 ++++++++++++++++++++++++
 1 file changed, 103 insertions(+)

diff --git a/crates/fayalite/src/util/ready_valid.rs b/crates/fayalite/src/util/ready_valid.rs
index 94154c9..ab19cd1 100644
--- a/crates/fayalite/src/util/ready_valid.rs
+++ b/crates/fayalite/src/util/ready_valid.rs
@@ -162,3 +162,106 @@ pub fn queue<T: Type>(
         }
     }
 }
+
+#[cfg(todo)]
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use crate::{
+        cli::FormalMode, firrtl::ExportOptions,
+        module::transform::simplify_enums::SimplifyEnumsKind, testing::assert_formal,
+    };
+
+    #[test]
+    fn test_queue() {
+        #[hdl_module]
+        fn queue_test(capacity: NonZeroUsize, inp_ready_is_comb: bool, out_valid_is_comb: bool) {
+            #[hdl]
+            let clk: Clock = m.input();
+            #[hdl]
+            let rst: SyncReset = m.input();
+            #[hdl]
+            let inp_data: HdlOption<UInt<8>> = m.input();
+            #[hdl]
+            let out_ready: Bool = m.input();
+            #[hdl]
+            let cd = wire();
+            connect(
+                cd,
+                #[hdl]
+                ClockDomain {
+                    clk,
+                    rst: rst.to_reset(),
+                },
+            );
+            #[hdl]
+            let dut = instance(queue(
+                UInt[ConstUsize::<8>],
+                capacity,
+                inp_ready_is_comb,
+                out_valid_is_comb,
+            ));
+            connect(dut.cd, cd);
+            connect(dut.inp.data, inp_data);
+            connect(dut.out.ready, out_ready);
+            #[hdl]
+            let count = reg_builder().clock_domain(cd).reset(0u32);
+            #[hdl]
+            let next_count = wire();
+            connect(next_count, count);
+            connect(count, next_count);
+            #[hdl]
+            if ReadyValid::fire(dut.inp) & !ReadyValid::fire(dut.out) {
+                connect_any(next_count, count + 1u8);
+            } else if !ReadyValid::fire(dut.inp) & ReadyValid::fire(dut.out) {
+                connect_any(next_count, count - 1u8);
+            }
+            hdl_assert(clk, count.cmp_eq(dut.count), "");
+            #[hdl]
+            let index = reg_builder().clock_domain(cd).reset(HdlNone::<UInt<32>>());
+            #[hdl]
+            let data = reg_builder().clock_domain(cd).reset(HdlNone());
+            #[hdl]
+            match index {
+                HdlNone =>
+                {
+                    #[hdl]
+                    if ReadyValid::fire(dut.inp) {
+                        connect(index, HdlSome(0u32));
+                        connect(data, dut.inp.data);
+                    }
+                }
+                HdlSome(cur_index) =>
+                {
+                    #[hdl]
+                    if cur_index.cmp_ge(next_count) {
+                        connect(index, HdlNone());
+                        #[hdl]
+                        if let HdlSome(data) = data {
+                            #[hdl]
+                            if let HdlSome(out_data) = dut.out.data {
+                                hdl_assert(clk, data.cmp_eq(out_data), "");
+                            } else {
+                                hdl_assert(clk, false.to_expr(), "");
+                            }
+                        } else {
+                            hdl_assert(clk, false.to_expr(), "");
+                        }
+                    } else {
+                        connect(index, HdlSome((cur_index + 1u8).cast_to_static()));
+                    }
+                }
+            }
+        }
+        assert_formal(
+            queue_test(NonZeroUsize::new(2).unwrap(), false, false),
+            FormalMode::BMC,
+            20,
+            None,
+            ExportOptions {
+                simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
+                ..ExportOptions::default()
+            },
+        );
+    }
+}

From 04752c5037761626e58cc91e7c2e78aa231b7904 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 25 Sep 2024 21:50:49 -0700
Subject: [PATCH 023/190] add test for connect_any with nested enums with
 different-sized variant bodies

simplify_enums is currently broken in that case
---
 crates/fayalite/tests/module.rs | 130 ++++++++++++++++++++++++++++++++
 1 file changed, 130 insertions(+)

diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 4139ee1..cddf808 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -3234,3 +3234,133 @@ circuit check_formal:
 "#,
     };
 }
+
+#[hdl]
+pub enum OneOfThree<A, B, C> {
+    A(A),
+    B(B),
+    C(C),
+}
+
+#[hdl_module(outline_generated)]
+pub fn check_enum_connect_any() {
+    #[hdl]
+    let index: UInt<2> = m.input();
+    #[hdl]
+    let i0: OneOfThree<UInt<0>, HdlOption<SInt<0>>, Bool> = m.input();
+    #[hdl]
+    let i1: OneOfThree<UInt<1>, HdlOption<SInt<1>>, Bool> = m.input();
+    #[hdl]
+    let i2: OneOfThree<UInt<2>, HdlOption<SInt<2>>, Bool> = m.input();
+    #[hdl]
+    let i3: OneOfThree<UInt<3>, HdlOption<SInt<3>>, Bool> = m.input();
+    #[hdl]
+    let o0: OneOfThree<UInt<0>, HdlOption<SInt<0>>, Bool> = m.output();
+    #[hdl]
+    let o1: OneOfThree<UInt<1>, HdlOption<SInt<1>>, Bool> = m.output();
+    #[hdl]
+    let o2: OneOfThree<UInt<2>, HdlOption<SInt<2>>, Bool> = m.output();
+    #[hdl]
+    let o3: OneOfThree<UInt<3>, HdlOption<SInt<3>>, Bool> = m.output();
+    #[hdl]
+    if index.cmp_eq(0u8) {
+        connect_any(o0, i0);
+        connect_any(o1, i1);
+        connect_any(o2, i2);
+        connect_any(o3, i3);
+    } else if index.cmp_eq(1u8) {
+        connect_any(o0, i1);
+        connect_any(o1, i2);
+        connect_any(o2, i3);
+        connect_any(o3, i0);
+    } else if index.cmp_eq(2u8) {
+        connect_any(o0, i2);
+        connect_any(o1, i3);
+        connect_any(o2, i0);
+        connect_any(o3, i1);
+    } else {
+        connect_any(o0, i3);
+        connect_any(o1, i0);
+        connect_any(o2, i1);
+        connect_any(o3, i2);
+    }
+}
+
+#[cfg(todo)]
+#[test]
+fn test_enum_connect_any() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_enum_connect_any();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_enum_connect_any.fir": r"FIRRTL version 3.2.0
+circuit check_enum_connect_any:
+    type Ty0 = {|HdlNone, HdlSome: SInt<0>|}
+    type Ty1 = {|A: UInt<0>, B: Ty0, C: UInt<1>|}
+    type Ty2 = {|HdlNone, HdlSome: SInt<1>|}
+    type Ty3 = {|A: UInt<1>, B: Ty2, C: UInt<1>|}
+    type Ty4 = {|HdlNone, HdlSome: SInt<2>|}
+    type Ty5 = {|A: UInt<2>, B: Ty4, C: UInt<1>|}
+    type Ty6 = {|HdlNone, HdlSome: SInt<3>|}
+    type Ty7 = {|A: UInt<3>, B: Ty6, C: UInt<1>|}
+    module check_enum_connect_any: @[module-XXXXXXXXXX.rs 1:1]
+        input index: UInt<2> @[module-XXXXXXXXXX.rs 2:1]
+        input i0: Ty1 @[module-XXXXXXXXXX.rs 3:1]
+        input i1: Ty3 @[module-XXXXXXXXXX.rs 4:1]
+        input i2: Ty5 @[module-XXXXXXXXXX.rs 5:1]
+        input i3: Ty7 @[module-XXXXXXXXXX.rs 6:1]
+        output o0: Ty1 @[module-XXXXXXXXXX.rs 7:1]
+        output o1: Ty3 @[module-XXXXXXXXXX.rs 8:1]
+        output o2: Ty5 @[module-XXXXXXXXXX.rs 9:1]
+        output o3: Ty7 @[module-XXXXXXXXXX.rs 10:1]
+        when eq(index, UInt<8>(0h0)): @[module-XXXXXXXXXX.rs 11:1]
+            connect o0, i0 @[module-XXXXXXXXXX.rs 12:1]
+            connect o1, i1 @[module-XXXXXXXXXX.rs 13:1]
+            connect o2, i2 @[module-XXXXXXXXXX.rs 14:1]
+            connect o3, i3 @[module-XXXXXXXXXX.rs 15:1]
+        else when eq(index, UInt<8>(0h1)): @[module-XXXXXXXXXX.rs 16:1]
+            connect o0, i1 @[module-XXXXXXXXXX.rs 17:1]
+            connect o1, i2 @[module-XXXXXXXXXX.rs 18:1]
+            connect o2, i3 @[module-XXXXXXXXXX.rs 19:1]
+            connect o3, i0 @[module-XXXXXXXXXX.rs 20:1]
+        else when eq(index, UInt<8>(0h2)): @[module-XXXXXXXXXX.rs 21:1]
+            connect o0, i2 @[module-XXXXXXXXXX.rs 22:1]
+            connect o1, i3 @[module-XXXXXXXXXX.rs 23:1]
+            connect o2, i0 @[module-XXXXXXXXXX.rs 24:1]
+            connect o3, i1 @[module-XXXXXXXXXX.rs 25:1]
+        else:
+            connect o0, i3 @[module-XXXXXXXXXX.rs 26:1]
+            connect o1, i0 @[module-XXXXXXXXXX.rs 27:1]
+            connect o2, i1 @[module-XXXXXXXXXX.rs 28:1]
+            connect o3, i2 @[module-XXXXXXXXXX.rs 29:1]
+",
+    };
+    // FIXME: simplify_enums is broken when connecting enums that contain
+    // UInt/SInt where their widths don't match. it should recurse into the
+    // enum bodies so it can properly sign/zero-extend or truncate the
+    // contained UInt/SInt fields.
+    let orig_m = m.canonical().intern();
+    let m = simplify_enums(orig_m, SimplifyEnumsKind::SimplifyToEnumsWithNoBody).unwrap();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_enum_connect_any.fir": r"TODO",
+    };
+    let m = simplify_enums(orig_m, SimplifyEnumsKind::ReplaceWithBundleOfUInts).unwrap();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_enum_connect_any.fir": r"TODO",
+    };
+    let m = simplify_enums(orig_m, SimplifyEnumsKind::ReplaceWithUInt).unwrap();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_enum_connect_any.fir": r"TODO",
+    };
+}

From d2ba313f0f1abf3d1f27f56e3047fa3231052471 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 30 Sep 2024 21:19:20 -0700
Subject: [PATCH 024/190] fix simplify_memories trying to connect Bool with
 UInt

---
 crates/fayalite/src/module/transform/simplify_memories.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/crates/fayalite/src/module/transform/simplify_memories.rs b/crates/fayalite/src/module/transform/simplify_memories.rs
index 0df1e81..19fb0ec 100644
--- a/crates/fayalite/src/module/transform/simplify_memories.rs
+++ b/crates/fayalite/src/module/transform/simplify_memories.rs
@@ -569,7 +569,7 @@ impl ModuleState {
                     port_wmask.map(Expr::from_canonical),
                     connect_read_enum,
                     connect_write_enum,
-                    connect_write_enum,
+                    connect_write,
                 ),
                 CanonicalType::Array(array_type) => {
                     input_array_types.push(array_type);

From 1e2831da47cca6df7e97f3d936fedbb5269f5f02 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 30 Sep 2024 21:20:35 -0700
Subject: [PATCH 025/190] add validation of connects and matches when
 validating module

this is useful for catching errors in transformation passes
---
 crates/fayalite/src/module.rs | 87 ++++++++++++++++++++++-------------
 1 file changed, 56 insertions(+), 31 deletions(-)

diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index 2b7534c..e88b37a 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -185,6 +185,40 @@ pub struct StmtConnect {
     pub source_location: SourceLocation,
 }
 
+impl StmtConnect {
+    #[track_caller]
+    fn assert_validity_with_original_types(&self, lhs_orig_ty: impl Type, rhs_orig_ty: impl Type) {
+        let Self {
+            lhs,
+            rhs,
+            source_location,
+        } = *self;
+        assert!(
+            Expr::ty(lhs).can_connect(Expr::ty(rhs)),
+            "can't connect types that are not equivalent:\nlhs type:\n{lhs_orig_ty:?}\nrhs type:\n{rhs_orig_ty:?}\nat: {source_location}",
+        );
+        assert!(
+            matches!(Expr::flow(lhs), Flow::Sink | Flow::Duplex),
+            "can't connect to source, connect lhs must have sink or duplex flow\nat: {source_location}"
+        );
+        assert!(
+            lhs.target().is_some(),
+            "can't connect to non-target\nat: {source_location}"
+        );
+        match Expr::flow(rhs) {
+            Flow::Source | Flow::Duplex => {}
+            Flow::Sink => assert!(
+                Expr::ty(rhs).is_passive(),
+                "can't connect from sink with non-passive type\nat: {source_location}"
+            ),
+        }
+    }
+    #[track_caller]
+    fn assert_validity(&self) {
+        self.assert_validity_with_original_types(Expr::ty(self.lhs), Expr::ty(self.rhs));
+    }
+}
+
 impl fmt::Debug for StmtConnect {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
@@ -283,6 +317,13 @@ pub struct StmtMatch<S: ModuleBuildingStatus = ModuleBuilt> {
     pub blocks: Interned<[S::Block]>,
 }
 
+impl StmtMatch {
+    #[track_caller]
+    fn assert_validity(&self) {
+        assert_eq!(Expr::ty(self.expr).variants().len(), self.blocks.len());
+    }
+}
+
 impl<S: ModuleBuildingStatus> fmt::Debug for StmtMatch<S> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
@@ -1657,11 +1698,13 @@ impl AssertValidityState {
         }
         for stmt in stmts {
             match stmt {
-                Stmt::Connect(StmtConnect {
-                    lhs,
-                    rhs,
-                    source_location,
-                }) => {
+                Stmt::Connect(connect) => {
+                    connect.assert_validity();
+                    let StmtConnect {
+                        lhs,
+                        rhs,
+                        source_location,
+                    } = connect;
                     self.set_connect_side_written(lhs, source_location, true, block);
                     self.set_connect_side_written(rhs, source_location, false, block);
                 }
@@ -1671,6 +1714,7 @@ impl AssertValidityState {
                     self.process_conditional_sub_blocks(block, sub_blocks)
                 }
                 Stmt::Match(match_stmt) => {
+                    match_stmt.assert_validity();
                     let sub_blocks = Vec::from_iter(
                         match_stmt
                             .blocks
@@ -2517,24 +2561,12 @@ pub fn connect_any_with_loc<Lhs: ToExpr, Rhs: ToExpr>(
     let rhs_orig = rhs.to_expr();
     let lhs = Expr::canonical(lhs_orig);
     let rhs = Expr::canonical(rhs_orig);
-    assert!(
-        Expr::ty(lhs).can_connect(Expr::ty(rhs)),
-        "can't connect types that are not equivalent:\nlhs type:\n{:?}\nrhs type:\n{:?}",
-        Expr::ty(lhs_orig),
-        Expr::ty(rhs_orig)
-    );
-    assert!(
-        matches!(Expr::flow(lhs), Flow::Sink | Flow::Duplex),
-        "can't connect to source, connect lhs must have sink or duplex flow"
-    );
-    assert!(lhs.target().is_some(), "can't connect to non-target");
-    match Expr::flow(rhs) {
-        Flow::Source | Flow::Duplex => {}
-        Flow::Sink => assert!(
-            Expr::ty(rhs).is_passive(),
-            "can't connect from sink with non-passive type"
-        ),
-    }
+    let connect = StmtConnect {
+        lhs,
+        rhs,
+        source_location,
+    };
+    connect.assert_validity_with_original_types(Expr::ty(lhs_orig), Expr::ty(rhs_orig));
     ModuleBuilder::with(|m| {
         m.impl_
             .borrow_mut()
@@ -2542,14 +2574,7 @@ pub fn connect_any_with_loc<Lhs: ToExpr, Rhs: ToExpr>(
             .builder_normal_body()
             .block(m.block_stack.top())
             .stmts
-            .push(
-                StmtConnect {
-                    lhs,
-                    rhs,
-                    source_location,
-                }
-                .into(),
-            );
+            .push(connect.into());
     });
 }
 

From 30a38bc8da427c08c2ba9db159fb1424df288ebe Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 30 Sep 2024 22:31:16 -0700
Subject: [PATCH 026/190] fix simplify_enums to properly handle nested enums
 and connects with different types

---
 .../src/module/transform/simplify_enums.rs    | 693 +++++++++++++-----
 crates/fayalite/tests/module.rs               | 585 ++++++++++++---
 2 files changed, 1028 insertions(+), 250 deletions(-)

diff --git a/crates/fayalite/src/module/transform/simplify_enums.rs b/crates/fayalite/src/module/transform/simplify_enums.rs
index cf85875..3b3677b 100644
--- a/crates/fayalite/src/module/transform/simplify_enums.rs
+++ b/crates/fayalite/src/module/transform/simplify_enums.rs
@@ -2,19 +2,20 @@
 // See Notices.txt for copyright information
 use crate::{
     array::{Array, ArrayType},
-    bundle::{Bundle, BundleType},
+    bundle::{Bundle, BundleField, BundleType},
     enum_::{Enum, EnumType, EnumVariant},
     expr::{
         ops::{self, EnumLiteral},
-        CastBitsTo, CastToBits, Expr, ExprEnum, HdlPartialEq, ToExpr,
+        CastBitsTo, CastTo, CastToBits, Expr, ExprEnum, HdlPartialEq, ToExpr,
     },
     hdl,
-    int::{DynSize, Size, UInt, UIntType},
-    intern::{Intern, Interned},
+    int::UInt,
+    intern::{Intern, Interned, Memoize},
     memory::{DynPortType, Mem, MemPort},
     module::{
         transform::visit::{Fold, Folder},
-        Block, Module, NameIdGen, ScopedNameId, Stmt, StmtConnect, StmtIf, StmtMatch, StmtWire,
+        Block, Module, NameId, NameIdGen, ScopedNameId, Stmt, StmtConnect, StmtIf, StmtMatch,
+        StmtWire,
     },
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
@@ -47,25 +48,65 @@ impl From<SimplifyEnumsError> for std::io::Error {
     }
 }
 
+fn contains_any_enum_types(ty: CanonicalType) -> bool {
+    #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+    struct TheMemoize;
+    impl Memoize for TheMemoize {
+        type Input = CanonicalType;
+        type InputOwned = CanonicalType;
+        type Output = bool;
+
+        fn inner(self, ty: &Self::Input) -> Self::Output {
+            match *ty {
+                CanonicalType::Array(array_type) => contains_any_enum_types(array_type.element()),
+                CanonicalType::Enum(_) => true,
+                CanonicalType::Bundle(bundle) => bundle
+                    .fields()
+                    .iter()
+                    .any(|field| contains_any_enum_types(field.ty)),
+                CanonicalType::UInt(_)
+                | CanonicalType::SInt(_)
+                | CanonicalType::Bool(_)
+                | CanonicalType::AsyncReset(_)
+                | CanonicalType::SyncReset(_)
+                | CanonicalType::Reset(_)
+                | CanonicalType::Clock(_) => false,
+            }
+        }
+    }
+    TheMemoize.get_owned(ty)
+}
+
 #[hdl]
-struct TagAndBody<T, BodyWidth: Size> {
-    tag: T,
-    body: UIntType<BodyWidth>,
+struct TagAndBody<Tag, Body> {
+    tag: Tag,
+    body: Body,
 }
 
 #[derive(Clone, Debug)]
 enum EnumTypeState {
-    TagEnumAndBody(TagAndBody<Enum, DynSize>),
-    TagUIntAndBody(TagAndBody<UInt, DynSize>),
+    TagEnumAndBody(TagAndBody<Enum, UInt>),
+    TagUIntAndBody(TagAndBody<UInt, UInt>),
     UInt(UInt),
     Unchanged,
 }
 
+struct ModuleState {
+    name_id_gen: NameIdGen,
+    module_name: NameId,
+}
+
+impl ModuleState {
+    fn gen_name(&mut self, name: &str) -> ScopedNameId {
+        ScopedNameId(self.module_name, self.name_id_gen.gen(name.intern()))
+    }
+}
+
 struct State {
     enum_types: HashMap<Enum, EnumTypeState>,
     replacement_mem_ports: HashMap<MemPort<DynPortType>, Wire<CanonicalType>>,
     kind: SimplifyEnumsKind,
-    name_id_gen: NameIdGen,
+    module_state_stack: Vec<ModuleState>,
 }
 
 impl State {
@@ -113,6 +154,377 @@ impl State {
         self.enum_types.insert(enum_type, retval.clone());
         Ok(retval)
     }
+    #[hdl]
+    fn handle_enum_literal(
+        &mut self,
+        unfolded_enum_type: Enum,
+        variant_index: usize,
+        folded_variant_value: Option<Expr<CanonicalType>>,
+    ) -> Result<Expr<CanonicalType>, SimplifyEnumsError> {
+        Ok(
+            match self.get_or_make_enum_type_state(unfolded_enum_type)? {
+                EnumTypeState::TagEnumAndBody(TagAndBody { tag, body }) => Expr::canonical(
+                    #[hdl]
+                    TagAndBody {
+                        tag: EnumLiteral::new_by_index(tag, variant_index, None),
+                        body: match folded_variant_value {
+                            Some(variant_value) => variant_value.cast_to_bits().cast_to(body),
+                            None => body.zero().to_expr(),
+                        },
+                    },
+                ),
+                EnumTypeState::TagUIntAndBody(TagAndBody { tag, body }) => Expr::canonical(
+                    #[hdl]
+                    TagAndBody {
+                        tag: tag.from_int_wrapping(variant_index),
+                        body: match folded_variant_value {
+                            Some(folded_variant_value) => {
+                                folded_variant_value.cast_to_bits().cast_to(body)
+                            }
+                            None => body.zero().to_expr(),
+                        },
+                    },
+                ),
+                EnumTypeState::UInt(_) => {
+                    let tag = UInt[unfolded_enum_type.discriminant_bit_width()];
+                    let body = UInt[unfolded_enum_type.type_properties().bit_width - tag.width()];
+                    Expr::canonical(
+                        (#[hdl]
+                        TagAndBody {
+                            tag: tag.from_int_wrapping(variant_index),
+                            body: match folded_variant_value {
+                                Some(folded_variant_value) => {
+                                    folded_variant_value.cast_to_bits().cast_to(body)
+                                }
+                                None => body.zero().to_expr(),
+                            },
+                        })
+                        .cast_to_bits(),
+                    )
+                }
+                EnumTypeState::Unchanged => Expr::canonical(
+                    ops::EnumLiteral::new_by_index(
+                        unfolded_enum_type,
+                        variant_index,
+                        folded_variant_value,
+                    )
+                    .to_expr(),
+                ),
+            },
+        )
+    }
+    fn handle_variant_access(
+        &mut self,
+        unfolded_enum_type: Enum,
+        folded_base_expr: Expr<CanonicalType>,
+        variant_index: usize,
+    ) -> Result<Expr<CanonicalType>, SimplifyEnumsError> {
+        let unfolded_variant_type = unfolded_enum_type.variants()[variant_index].ty;
+        Ok(
+            match self.get_or_make_enum_type_state(unfolded_enum_type)? {
+                EnumTypeState::TagEnumAndBody(_) | EnumTypeState::TagUIntAndBody(_) => {
+                    match unfolded_variant_type {
+                        Some(variant_type) => Expr::canonical(
+                            Expr::<TagAndBody<CanonicalType, UInt>>::from_canonical(
+                                folded_base_expr,
+                            )
+                            .body[..variant_type.bit_width()]
+                                .cast_bits_to(variant_type.fold(self)?),
+                        ),
+                        None => Expr::canonical(().to_expr()),
+                    }
+                }
+                EnumTypeState::UInt(_) => match unfolded_variant_type {
+                    Some(variant_type) => {
+                        let base_int = Expr::<UInt>::from_canonical(folded_base_expr);
+                        let variant_type_bit_width = variant_type.bit_width();
+                        Expr::canonical(
+                            base_int[unfolded_enum_type.discriminant_bit_width()..]
+                                [..variant_type_bit_width]
+                                .cast_bits_to(variant_type.fold(self)?),
+                        )
+                    }
+                    None => Expr::canonical(().to_expr()),
+                },
+                EnumTypeState::Unchanged => match unfolded_variant_type {
+                    Some(_) => ops::VariantAccess::new_by_index(
+                        Expr::from_canonical(folded_base_expr),
+                        variant_index,
+                    )
+                    .to_expr(),
+                    None => Expr::canonical(().to_expr()),
+                },
+            },
+        )
+    }
+    fn handle_match(
+        &mut self,
+        unfolded_enum_type: Enum,
+        folded_expr: Expr<CanonicalType>,
+        source_location: SourceLocation,
+        folded_blocks: &[Block],
+    ) -> Result<Stmt, SimplifyEnumsError> {
+        match self.get_or_make_enum_type_state(unfolded_enum_type)? {
+            EnumTypeState::TagEnumAndBody(_) => Ok(StmtMatch {
+                expr: Expr::<TagAndBody<Enum, UInt>>::from_canonical(folded_expr).tag,
+                source_location,
+                blocks: folded_blocks.intern(),
+            }
+            .into()),
+            EnumTypeState::TagUIntAndBody(_) => {
+                let int_tag_expr = Expr::<TagAndBody<UInt, UInt>>::from_canonical(folded_expr).tag;
+                Ok(match_int_tag(int_tag_expr, source_location, &folded_blocks).into())
+            }
+            EnumTypeState::UInt(_) => {
+                let int_tag_expr = Expr::<UInt>::from_canonical(folded_expr)
+                    [..unfolded_enum_type.discriminant_bit_width()];
+                Ok(match_int_tag(int_tag_expr, source_location, &folded_blocks).into())
+            }
+            EnumTypeState::Unchanged => Ok(StmtMatch {
+                expr: Expr::from_canonical(folded_expr),
+                source_location,
+                blocks: folded_blocks.intern(),
+            }
+            .into()),
+        }
+    }
+    fn handle_stmt_connect_array(
+        &mut self,
+        unfolded_lhs_ty: Array,
+        unfolded_rhs_ty: Array,
+        folded_lhs: Expr<Array>,
+        folded_rhs: Expr<Array>,
+        source_location: SourceLocation,
+        output_stmts: &mut Vec<Stmt>,
+    ) -> Result<(), SimplifyEnumsError> {
+        assert_eq!(unfolded_lhs_ty.len(), unfolded_rhs_ty.len());
+        let unfolded_lhs_element_ty = unfolded_lhs_ty.element();
+        let unfolded_rhs_element_ty = unfolded_rhs_ty.element();
+        for array_index in 0..unfolded_lhs_ty.len() {
+            self.handle_stmt_connect(
+                unfolded_lhs_element_ty,
+                unfolded_rhs_element_ty,
+                folded_lhs[array_index],
+                folded_rhs[array_index],
+                source_location,
+                output_stmts,
+            )?;
+        }
+        Ok(())
+    }
+    fn handle_stmt_connect_bundle(
+        &mut self,
+        unfolded_lhs_ty: Bundle,
+        unfolded_rhs_ty: Bundle,
+        folded_lhs: Expr<Bundle>,
+        folded_rhs: Expr<Bundle>,
+        source_location: SourceLocation,
+        output_stmts: &mut Vec<Stmt>,
+    ) -> Result<(), SimplifyEnumsError> {
+        let unfolded_lhs_fields = unfolded_lhs_ty.fields();
+        let unfolded_rhs_fields = unfolded_rhs_ty.fields();
+        assert_eq!(unfolded_lhs_fields.len(), unfolded_rhs_fields.len());
+        for (
+            field_index,
+            (
+                &BundleField {
+                    name,
+                    flipped,
+                    ty: unfolded_lhs_field_ty,
+                },
+                unfolded_rhs_field,
+            ),
+        ) in unfolded_lhs_fields
+            .iter()
+            .zip(&unfolded_rhs_fields)
+            .enumerate()
+        {
+            assert_eq!(name, unfolded_rhs_field.name);
+            assert_eq!(flipped, unfolded_rhs_field.flipped);
+            let folded_lhs_field =
+                ops::FieldAccess::new_by_index(folded_lhs, field_index).to_expr();
+            let folded_rhs_field =
+                ops::FieldAccess::new_by_index(folded_rhs, field_index).to_expr();
+            if flipped {
+                // swap lhs/rhs
+                self.handle_stmt_connect(
+                    unfolded_rhs_field.ty,
+                    unfolded_lhs_field_ty,
+                    folded_rhs_field,
+                    folded_lhs_field,
+                    source_location,
+                    output_stmts,
+                )?;
+            } else {
+                self.handle_stmt_connect(
+                    unfolded_lhs_field_ty,
+                    unfolded_rhs_field.ty,
+                    folded_lhs_field,
+                    folded_rhs_field,
+                    source_location,
+                    output_stmts,
+                )?;
+            }
+        }
+        Ok(())
+    }
+    fn handle_stmt_connect_enum(
+        &mut self,
+        unfolded_lhs_ty: Enum,
+        unfolded_rhs_ty: Enum,
+        folded_lhs: Expr<CanonicalType>,
+        folded_rhs: Expr<CanonicalType>,
+        source_location: SourceLocation,
+        output_stmts: &mut Vec<Stmt>,
+    ) -> Result<(), SimplifyEnumsError> {
+        let unfolded_lhs_variants = unfolded_lhs_ty.variants();
+        let unfolded_rhs_variants = unfolded_rhs_ty.variants();
+        assert_eq!(unfolded_lhs_variants.len(), unfolded_rhs_variants.len());
+        let mut folded_blocks = vec![];
+        for (
+            variant_index,
+            (
+                &EnumVariant {
+                    name,
+                    ty: unfolded_lhs_variant_ty,
+                },
+                unfolded_rhs_variant,
+            ),
+        ) in unfolded_lhs_variants
+            .iter()
+            .zip(&unfolded_rhs_variants)
+            .enumerate()
+        {
+            let mut output_stmts = vec![];
+            assert_eq!(name, unfolded_rhs_variant.name);
+            assert_eq!(
+                unfolded_lhs_variant_ty.is_some(),
+                unfolded_rhs_variant.ty.is_some()
+            );
+            let folded_variant_value =
+                if let (Some(unfolded_lhs_variant_ty), Some(unfolded_rhs_variant_ty)) =
+                    (unfolded_lhs_variant_ty, unfolded_rhs_variant.ty)
+                {
+                    let lhs_wire = Wire::new_unchecked(
+                        self.module_state_stack
+                            .last_mut()
+                            .unwrap()
+                            .gen_name("__connect_variant_body"),
+                        source_location,
+                        unfolded_lhs_variant_ty.fold(self)?,
+                    );
+                    output_stmts.push(
+                        StmtWire {
+                            annotations: Interned::default(),
+                            wire: lhs_wire,
+                        }
+                        .into(),
+                    );
+                    let lhs_wire = lhs_wire.to_expr();
+                    let folded_rhs_variant =
+                        self.handle_variant_access(unfolded_rhs_ty, folded_rhs, variant_index)?;
+                    self.handle_stmt_connect(
+                        unfolded_lhs_variant_ty,
+                        unfolded_rhs_variant_ty,
+                        lhs_wire,
+                        folded_rhs_variant,
+                        source_location,
+                        &mut output_stmts,
+                    )?;
+                    Some(lhs_wire)
+                } else {
+                    None
+                };
+            output_stmts.push(
+                StmtConnect {
+                    lhs: folded_lhs,
+                    rhs: self.handle_enum_literal(
+                        unfolded_lhs_ty,
+                        variant_index,
+                        folded_variant_value,
+                    )?,
+                    source_location,
+                }
+                .into(),
+            );
+            folded_blocks.push(Block {
+                memories: Interned::default(),
+                stmts: Intern::intern_owned(output_stmts),
+            });
+        }
+        output_stmts.push(self.handle_match(
+            unfolded_rhs_ty,
+            folded_rhs,
+            source_location,
+            &folded_blocks,
+        )?);
+        Ok(())
+    }
+    fn handle_stmt_connect(
+        &mut self,
+        unfolded_lhs_ty: CanonicalType,
+        unfolded_rhs_ty: CanonicalType,
+        folded_lhs: Expr<CanonicalType>,
+        folded_rhs: Expr<CanonicalType>,
+        source_location: SourceLocation,
+        output_stmts: &mut Vec<Stmt>,
+    ) -> Result<(), SimplifyEnumsError> {
+        let needs_expansion = unfolded_lhs_ty != unfolded_rhs_ty
+            && (contains_any_enum_types(unfolded_lhs_ty)
+                || contains_any_enum_types(unfolded_rhs_ty));
+        if !needs_expansion {
+            output_stmts.push(
+                StmtConnect {
+                    lhs: folded_lhs,
+                    rhs: folded_rhs,
+                    source_location,
+                }
+                .into(),
+            );
+            return Ok(());
+        }
+        println!(
+            r"handle_stmt_connect(
+    unfolded_lhs_ty: {unfolded_lhs_ty:?},
+    unfolded_rhs_ty: {unfolded_rhs_ty:?},
+    folded_lhs: {folded_lhs:?},
+    folded_rhs: {folded_rhs:?},
+)"
+        );
+        match unfolded_lhs_ty {
+            CanonicalType::Array(unfolded_lhs_ty) => self.handle_stmt_connect_array(
+                unfolded_lhs_ty,
+                Array::from_canonical(unfolded_rhs_ty),
+                Expr::from_canonical(folded_lhs),
+                Expr::from_canonical(folded_rhs),
+                source_location,
+                output_stmts,
+            ),
+            CanonicalType::Enum(unfolded_lhs_ty) => self.handle_stmt_connect_enum(
+                unfolded_lhs_ty,
+                Enum::from_canonical(unfolded_rhs_ty),
+                folded_lhs,
+                folded_rhs,
+                source_location,
+                output_stmts,
+            ),
+            CanonicalType::Bundle(unfolded_lhs_ty) => self.handle_stmt_connect_bundle(
+                unfolded_lhs_ty,
+                Bundle::from_canonical(unfolded_rhs_ty),
+                Expr::from_canonical(folded_lhs),
+                Expr::from_canonical(folded_rhs),
+                source_location,
+                output_stmts,
+            ),
+            CanonicalType::UInt(_)
+            | CanonicalType::SInt(_)
+            | CanonicalType::Bool(_)
+            | CanonicalType::AsyncReset(_)
+            | CanonicalType::SyncReset(_)
+            | CanonicalType::Reset(_)
+            | CanonicalType::Clock(_) => unreachable!(),
+        }
+    }
 }
 
 fn connect_port(
@@ -183,6 +595,42 @@ fn connect_port(
     }
 }
 
+fn match_int_tag(
+    int_tag_expr: Expr<UInt>,
+    source_location: SourceLocation,
+    folded_blocks: &[Block],
+) -> StmtIf {
+    let mut blocks_iter = folded_blocks.iter().copied().enumerate();
+    let (_, last_block) = blocks_iter.next_back().unwrap_or_default();
+    let Some((next_to_last_variant_index, next_to_last_block)) = blocks_iter.next_back() else {
+        return StmtIf {
+            cond: true.to_expr(),
+            source_location,
+            blocks: [last_block, Block::default()],
+        };
+    };
+    let mut retval = StmtIf {
+        cond: int_tag_expr
+            .cmp_eq(Expr::ty(int_tag_expr).from_int_wrapping(next_to_last_variant_index)),
+        source_location,
+        blocks: [next_to_last_block, last_block],
+    };
+    for (variant_index, block) in blocks_iter.rev() {
+        retval = StmtIf {
+            cond: int_tag_expr.cmp_eq(Expr::ty(int_tag_expr).from_int_wrapping(variant_index)),
+            source_location,
+            blocks: [
+                block,
+                Block {
+                    memories: Default::default(),
+                    stmts: [Stmt::from(retval)][..].intern(),
+                },
+            ],
+        };
+    }
+    retval
+}
+
 impl Folder for State {
     type Error = SimplifyEnumsError;
 
@@ -191,96 +639,33 @@ impl Folder for State {
     }
 
     fn fold_module<T: BundleType>(&mut self, v: Module<T>) -> Result<Module<T>, Self::Error> {
-        let old_name_id_gen =
-            std::mem::replace(&mut self.name_id_gen, NameIdGen::for_module(v.canonical()));
+        self.module_state_stack.push(ModuleState {
+            name_id_gen: NameIdGen::for_module(v.canonical()),
+            module_name: v.name_id(),
+        });
         let retval = Fold::default_fold(v, self);
-        self.name_id_gen = old_name_id_gen;
+        self.module_state_stack.pop();
         retval
     }
 
     fn fold_expr_enum(&mut self, op: ExprEnum) -> Result<ExprEnum, Self::Error> {
         match op {
-            ExprEnum::EnumLiteral(op) => Ok(match self.get_or_make_enum_type_state(op.ty())? {
-                EnumTypeState::TagEnumAndBody(TagAndBody { tag, body }) => *Expr::expr_enum(
-                    <TagAndBody<Enum, DynSize> as BundleType>::Builder::default()
-                        .field_tag(EnumLiteral::new_by_index(tag, op.variant_index(), None))
-                        .field_body(match op.variant_value() {
-                            Some(variant_value) => variant_value.fold(self)?.cast_to_bits(),
-                            None => body.zero().to_expr(),
-                        })
-                        .to_expr(),
-                ),
-                EnumTypeState::TagUIntAndBody(TagAndBody { tag, body }) => *Expr::expr_enum(
-                    <TagAndBody<UInt, DynSize> as BundleType>::Builder::default()
-                        .field_tag(tag.from_int_wrapping(op.variant_index()))
-                        .field_body(match op.variant_value() {
-                            Some(variant_value) => variant_value.fold(self)?.cast_to_bits(),
-                            None => body.zero().to_expr(),
-                        })
-                        .to_expr(),
-                ),
-                EnumTypeState::UInt(_) => *Expr::expr_enum(
-                    <TagAndBody<UInt, DynSize> as BundleType>::Builder::default()
-                        .field_tag(
-                            UIntType::new(op.ty().discriminant_bit_width())
-                                .from_int_wrapping(op.variant_index()),
-                        )
-                        .field_body(match op.variant_value() {
-                            Some(variant_value) => variant_value.fold(self)?.cast_to_bits(),
-                            None => UIntType::new(
-                                op.ty().type_properties().bit_width
-                                    - op.ty().discriminant_bit_width(),
-                            )
-                            .zero()
-                            .to_expr(),
-                        })
-                        .cast_to_bits(),
-                ),
-                EnumTypeState::Unchanged => ExprEnum::EnumLiteral(ops::EnumLiteral::new_by_index(
+            ExprEnum::EnumLiteral(op) => {
+                let folded_variant_value = op.variant_value().map(|v| v.fold(self)).transpose()?;
+                Ok(*Expr::expr_enum(self.handle_enum_literal(
                     op.ty(),
                     op.variant_index(),
-                    op.variant_value().map(|v| v.fold(self)).transpose()?,
-                )),
-            }),
-            ExprEnum::VariantAccess(op) => Ok(
-                match self.get_or_make_enum_type_state(Expr::ty(op.base()))? {
-                    EnumTypeState::TagEnumAndBody(_) | EnumTypeState::TagUIntAndBody(_) => {
-                        match op.variant_type() {
-                            Some(variant_type) => *Expr::expr_enum(
-                                Expr::<TagAndBody<CanonicalType, DynSize>>::from_canonical(
-                                    (*Expr::expr_enum(op.base())).fold(self)?.to_expr(),
-                                )
-                                .body[..variant_type.bit_width()]
-                                    .cast_bits_to(variant_type),
-                            ),
-                            None => *Expr::expr_enum(().to_expr()),
-                        }
-                    }
-                    EnumTypeState::UInt(_) => match op.variant_type() {
-                        Some(variant_type) => {
-                            let base_int = Expr::<UInt>::from_canonical(
-                                (*Expr::expr_enum(op.base())).fold(self)?.to_expr(),
-                            );
-                            dbg!(base_int);
-                            let base_ty = Expr::ty(op.base());
-                            let variant_type_bit_width = variant_type.bit_width();
-                            *Expr::expr_enum(
-                                base_int[base_ty.discriminant_bit_width()..]
-                                    [..variant_type_bit_width]
-                                    .cast_bits_to(variant_type),
-                            )
-                        }
-                        None => *Expr::expr_enum(().to_expr()),
-                    },
-                    EnumTypeState::Unchanged => match op.variant_type() {
-                        Some(_) => ExprEnum::VariantAccess(ops::VariantAccess::new_by_index(
-                            op.base().fold(self)?,
-                            op.variant_index(),
-                        )),
-                        None => *Expr::expr_enum(().to_expr()),
-                    },
-                },
-            ),
+                    folded_variant_value,
+                )?))
+            }
+            ExprEnum::VariantAccess(op) => {
+                let folded_base_expr = Expr::canonical(op.base()).fold(self)?;
+                Ok(*Expr::expr_enum(self.handle_variant_access(
+                    Expr::ty(op.base()),
+                    folded_base_expr,
+                    op.variant_index(),
+                )?))
+            }
             ExprEnum::MemPort(mem_port) => Ok(
                 if let Some(&wire) = self.replacement_mem_ports.get(&mem_port) {
                     ExprEnum::Wire(wire)
@@ -424,11 +809,15 @@ impl Folder for State {
                     if wire_ty == new_port_ty {
                         continue;
                     }
-                    let wire_name = self.name_id_gen.gen(
-                        (*format!("{}_{}", memory.scoped_name().1 .0, port.port_name())).intern(),
-                    );
                     let wire = Wire::new_unchecked(
-                        ScopedNameId(memory.scoped_name().0, wire_name),
+                        self.module_state_stack
+                            .last_mut()
+                            .unwrap()
+                            .gen_name(&format!(
+                                "{}_{}",
+                                memory.scoped_name().1 .0,
+                                port.port_name()
+                            )),
                         port.source_location(),
                         wire_ty,
                     );
@@ -471,82 +860,50 @@ impl Folder for State {
     }
 
     fn fold_stmt(&mut self, stmt: Stmt) -> Result<Stmt, Self::Error> {
-        fn match_int_tag(
-            state: &mut State,
-            int_tag_expr: Expr<UInt>,
-            source_location: SourceLocation,
-            blocks: Interned<[Block]>,
-        ) -> Result<StmtIf, SimplifyEnumsError> {
-            let mut blocks_iter = blocks.iter().copied().enumerate();
-            let (_, last_block) = blocks_iter.next_back().unwrap_or_default();
-            let Some((next_to_last_variant_index, next_to_last_block)) = blocks_iter.next_back()
-            else {
-                return Ok(StmtIf {
-                    cond: true.to_expr(),
-                    source_location,
-                    blocks: [last_block.fold(state)?, Block::default()],
-                });
-            };
-            let mut retval = StmtIf {
-                cond: int_tag_expr
-                    .cmp_eq(Expr::ty(int_tag_expr).from_int_wrapping(next_to_last_variant_index)),
-                source_location,
-                blocks: [next_to_last_block.fold(state)?, last_block.fold(state)?],
-            };
-            for (variant_index, block) in blocks_iter.rev() {
-                retval = StmtIf {
-                    cond: int_tag_expr
-                        .cmp_eq(Expr::ty(int_tag_expr).from_int_wrapping(variant_index)),
-                    source_location,
-                    blocks: [
-                        block.fold(state)?,
-                        Block {
-                            memories: Default::default(),
-                            stmts: [Stmt::from(retval)][..].intern(),
-                        },
-                    ],
-                };
-            }
-            Ok(retval)
-        }
         match stmt {
             Stmt::Match(StmtMatch {
                 expr,
                 source_location,
                 blocks,
-            }) => match self.get_or_make_enum_type_state(Expr::ty(expr))? {
-                EnumTypeState::TagEnumAndBody(_) => Ok(StmtMatch {
-                    expr: Expr::<TagAndBody<Enum, DynSize>>::from_canonical(
-                        Expr::canonical(expr).fold(self)?,
-                    )
-                    .tag,
-                    source_location,
-                    blocks: blocks.fold(self)?,
-                }
-                .into()),
-                EnumTypeState::TagUIntAndBody(_) => {
-                    let int_tag_expr = Expr::<TagAndBody<UInt, DynSize>>::from_canonical(
-                        Expr::canonical(expr).fold(self)?,
-                    )
-                    .tag;
-                    Ok(match_int_tag(self, int_tag_expr, source_location, blocks)?.into())
-                }
-                EnumTypeState::UInt(_) => {
-                    let int_tag_expr =
-                        Expr::<UInt>::from_canonical(Expr::canonical(expr).fold(self)?)
-                            [..Expr::ty(expr).discriminant_bit_width()];
-                    Ok(match_int_tag(self, int_tag_expr, source_location, blocks)?.into())
-                }
-                EnumTypeState::Unchanged => Ok(StmtMatch {
-                    expr: expr.fold(self)?,
-                    source_location,
-                    blocks: blocks.fold(self)?,
-                }
-                .into()),
-            },
-            Stmt::Connect(_) | Stmt::Formal(_) | Stmt::If(_) | Stmt::Declaration(_) => {
-                stmt.default_fold(self)
+            }) => {
+                let folded_expr = Expr::canonical(expr).fold(self)?;
+                let folded_blocks = blocks.fold(self)?;
+                self.handle_match(Expr::ty(expr), folded_expr, source_location, &folded_blocks)
             }
+            Stmt::Connect(StmtConnect {
+                lhs,
+                rhs,
+                source_location,
+            }) => {
+                let folded_lhs = lhs.fold(self)?;
+                let folded_rhs = rhs.fold(self)?;
+                let mut output_stmts = vec![];
+                self.handle_stmt_connect(
+                    Expr::ty(lhs),
+                    Expr::ty(rhs),
+                    folded_lhs,
+                    folded_rhs,
+                    source_location,
+                    &mut output_stmts,
+                )?;
+                if output_stmts.len() == 1 {
+                    Ok(output_stmts.pop().unwrap())
+                } else {
+                    Ok(StmtIf {
+                        cond: true.to_expr(),
+                        source_location,
+                        blocks: [
+                            Block {
+                                memories: Interned::default(),
+                                stmts: Intern::intern_owned(output_stmts),
+                            },
+                            Block::default(),
+                        ],
+                    }
+                    .into())
+                }
+            }
+            Stmt::Formal(_) | Stmt::If(_) | Stmt::Declaration(_) => stmt.default_fold(self),
         }
     }
 
@@ -618,6 +975,6 @@ pub fn simplify_enums(
         enum_types: HashMap::new(),
         replacement_mem_ports: HashMap::new(),
         kind,
-        name_id_gen: NameIdGen::default(),
+        module_state_stack: vec![],
     })
 }
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index cddf808..9d5a898 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -514,7 +514,6 @@ circuit check_enum_literals:
     type Ty1 = {tag: Ty0, body: UInt<8>}
     type Ty2 = {|A, B, C|}
     type Ty3 = {tag: Ty2, body: UInt<8>}
-    type Ty4 = {tag: Ty2, body: UInt<3>}
     module check_enum_literals: @[module-XXXXXXXXXX.rs 1:1]
         input i: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
         output o: Ty1 @[module-XXXXXXXXXX.rs 3:1]
@@ -534,7 +533,7 @@ circuit check_enum_literals:
             connect _bundle_literal_expr_2.body, i
             connect o2, _bundle_literal_expr_2 @[module-XXXXXXXXXX.rs 9:1]
         else:
-            wire _bundle_literal_expr_3: Ty4
+            wire _bundle_literal_expr_3: Ty3
             connect _bundle_literal_expr_3.tag, {|A, B, C|}(C)
             wire _array_literal_expr: UInt<1>[3]
             connect _array_literal_expr[0], bits(i, 0, 0)
@@ -546,7 +545,7 @@ circuit check_enum_literals:
             connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
             wire _cast_to_bits_expr: UInt<3>
             connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
-            connect _bundle_literal_expr_3.body, _cast_to_bits_expr
+            connect _bundle_literal_expr_3.body, pad(_cast_to_bits_expr, 8)
             connect o2, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 10:1]
 ",
     };
@@ -559,7 +558,6 @@ circuit check_enum_literals:
 circuit check_enum_literals:
     type Ty0 = {tag: UInt<1>, body: UInt<8>}
     type Ty1 = {tag: UInt<2>, body: UInt<8>}
-    type Ty2 = {tag: UInt<2>, body: UInt<3>}
     module check_enum_literals: @[module-XXXXXXXXXX.rs 1:1]
         input i: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
         output o: Ty0 @[module-XXXXXXXXXX.rs 3:1]
@@ -579,7 +577,7 @@ circuit check_enum_literals:
             connect _bundle_literal_expr_2.body, i
             connect o2, _bundle_literal_expr_2 @[module-XXXXXXXXXX.rs 9:1]
         else:
-            wire _bundle_literal_expr_3: Ty2
+            wire _bundle_literal_expr_3: Ty1
             connect _bundle_literal_expr_3.tag, UInt<2>(0h2)
             wire _array_literal_expr: UInt<1>[3]
             connect _array_literal_expr[0], bits(i, 0, 0)
@@ -591,7 +589,7 @@ circuit check_enum_literals:
             connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
             wire _cast_to_bits_expr: UInt<3>
             connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
-            connect _bundle_literal_expr_3.body, _cast_to_bits_expr
+            connect _bundle_literal_expr_3.body, pad(_cast_to_bits_expr, 8)
             connect o2, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 10:1]
 ",
     };
@@ -604,7 +602,6 @@ circuit check_enum_literals:
 circuit check_enum_literals:
     type Ty0 = {tag: UInt<1>, body: UInt<8>}
     type Ty1 = {tag: UInt<2>, body: UInt<8>}
-    type Ty2 = {tag: UInt<2>, body: UInt<3>}
     module check_enum_literals: @[module-XXXXXXXXXX.rs 1:1]
         input i: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
         output o: UInt<9> @[module-XXXXXXXXXX.rs 3:1]
@@ -639,7 +636,7 @@ circuit check_enum_literals:
             connect _cast_to_bits_expr_2, cat(_cast_bundle_to_bits_expr_2.body, _cast_bundle_to_bits_expr_2.tag)
             connect o2, _cast_to_bits_expr_2 @[module-XXXXXXXXXX.rs 9:1]
         else:
-            wire _bundle_literal_expr_3: Ty2
+            wire _bundle_literal_expr_3: Ty1
             connect _bundle_literal_expr_3.tag, UInt<2>(0h2)
             wire _array_literal_expr: UInt<1>[3]
             connect _array_literal_expr[0], bits(i, 0, 0)
@@ -651,11 +648,11 @@ circuit check_enum_literals:
             connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
             wire _cast_to_bits_expr_3: UInt<3>
             connect _cast_to_bits_expr_3, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
-            connect _bundle_literal_expr_3.body, _cast_to_bits_expr_3
-            wire _cast_bundle_to_bits_expr_3: Ty2
+            connect _bundle_literal_expr_3.body, pad(_cast_to_bits_expr_3, 8)
+            wire _cast_bundle_to_bits_expr_3: Ty1
             connect _cast_bundle_to_bits_expr_3.tag, _bundle_literal_expr_3.tag
             connect _cast_bundle_to_bits_expr_3.body, _bundle_literal_expr_3.body
-            wire _cast_to_bits_expr_4: UInt<5>
+            wire _cast_to_bits_expr_4: UInt<10>
             connect _cast_to_bits_expr_4, cat(_cast_bundle_to_bits_expr_3.body, _cast_bundle_to_bits_expr_3.tag)
             connect o2, _cast_to_bits_expr_4 @[module-XXXXXXXXXX.rs 10:1]
 ",
@@ -3245,48 +3242,25 @@ pub enum OneOfThree<A, B, C> {
 #[hdl_module(outline_generated)]
 pub fn check_enum_connect_any() {
     #[hdl]
-    let index: UInt<2> = m.input();
+    let swap: Bool = m.input();
     #[hdl]
-    let i0: OneOfThree<UInt<0>, HdlOption<SInt<0>>, Bool> = m.input();
+    let i1: OneOfThree<UInt<1>, HdlOption<SInt<1>>, HdlOption<()>> = m.input();
     #[hdl]
-    let i1: OneOfThree<UInt<1>, HdlOption<SInt<1>>, Bool> = m.input();
+    let i2: OneOfThree<UInt<2>, HdlOption<SInt<2>>, HdlOption<()>> = m.input();
     #[hdl]
-    let i2: OneOfThree<UInt<2>, HdlOption<SInt<2>>, Bool> = m.input();
+    let o1: OneOfThree<UInt<1>, HdlOption<SInt<1>>, HdlOption<()>> = m.output();
     #[hdl]
-    let i3: OneOfThree<UInt<3>, HdlOption<SInt<3>>, Bool> = m.input();
+    let o2: OneOfThree<UInt<2>, HdlOption<SInt<2>>, HdlOption<()>> = m.output();
     #[hdl]
-    let o0: OneOfThree<UInt<0>, HdlOption<SInt<0>>, Bool> = m.output();
-    #[hdl]
-    let o1: OneOfThree<UInt<1>, HdlOption<SInt<1>>, Bool> = m.output();
-    #[hdl]
-    let o2: OneOfThree<UInt<2>, HdlOption<SInt<2>>, Bool> = m.output();
-    #[hdl]
-    let o3: OneOfThree<UInt<3>, HdlOption<SInt<3>>, Bool> = m.output();
-    #[hdl]
-    if index.cmp_eq(0u8) {
-        connect_any(o0, i0);
+    if swap {
+        connect_any(o1, i2);
+        connect_any(o2, i1);
+    } else {
         connect_any(o1, i1);
         connect_any(o2, i2);
-        connect_any(o3, i3);
-    } else if index.cmp_eq(1u8) {
-        connect_any(o0, i1);
-        connect_any(o1, i2);
-        connect_any(o2, i3);
-        connect_any(o3, i0);
-    } else if index.cmp_eq(2u8) {
-        connect_any(o0, i2);
-        connect_any(o1, i3);
-        connect_any(o2, i0);
-        connect_any(o3, i1);
-    } else {
-        connect_any(o0, i3);
-        connect_any(o1, i0);
-        connect_any(o2, i1);
-        connect_any(o3, i2);
     }
 }
 
-#[cfg(todo)]
 #[test]
 fn test_enum_connect_any() {
     let _n = SourceLocation::normalize_files_for_tests();
@@ -3297,44 +3271,24 @@ fn test_enum_connect_any() {
         m =>
         "/test/check_enum_connect_any.fir": r"FIRRTL version 3.2.0
 circuit check_enum_connect_any:
-    type Ty0 = {|HdlNone, HdlSome: SInt<0>|}
-    type Ty1 = {|A: UInt<0>, B: Ty0, C: UInt<1>|}
-    type Ty2 = {|HdlNone, HdlSome: SInt<1>|}
-    type Ty3 = {|A: UInt<1>, B: Ty2, C: UInt<1>|}
+    type Ty0 = {|HdlNone, HdlSome: SInt<1>|}
+    type Ty1 = {}
+    type Ty2 = {|HdlNone, HdlSome: Ty1|}
+    type Ty3 = {|A: UInt<1>, B: Ty0, C: Ty2|}
     type Ty4 = {|HdlNone, HdlSome: SInt<2>|}
-    type Ty5 = {|A: UInt<2>, B: Ty4, C: UInt<1>|}
-    type Ty6 = {|HdlNone, HdlSome: SInt<3>|}
-    type Ty7 = {|A: UInt<3>, B: Ty6, C: UInt<1>|}
+    type Ty5 = {|A: UInt<2>, B: Ty4, C: Ty2|}
     module check_enum_connect_any: @[module-XXXXXXXXXX.rs 1:1]
-        input index: UInt<2> @[module-XXXXXXXXXX.rs 2:1]
-        input i0: Ty1 @[module-XXXXXXXXXX.rs 3:1]
-        input i1: Ty3 @[module-XXXXXXXXXX.rs 4:1]
-        input i2: Ty5 @[module-XXXXXXXXXX.rs 5:1]
-        input i3: Ty7 @[module-XXXXXXXXXX.rs 6:1]
-        output o0: Ty1 @[module-XXXXXXXXXX.rs 7:1]
-        output o1: Ty3 @[module-XXXXXXXXXX.rs 8:1]
-        output o2: Ty5 @[module-XXXXXXXXXX.rs 9:1]
-        output o3: Ty7 @[module-XXXXXXXXXX.rs 10:1]
-        when eq(index, UInt<8>(0h0)): @[module-XXXXXXXXXX.rs 11:1]
-            connect o0, i0 @[module-XXXXXXXXXX.rs 12:1]
-            connect o1, i1 @[module-XXXXXXXXXX.rs 13:1]
-            connect o2, i2 @[module-XXXXXXXXXX.rs 14:1]
-            connect o3, i3 @[module-XXXXXXXXXX.rs 15:1]
-        else when eq(index, UInt<8>(0h1)): @[module-XXXXXXXXXX.rs 16:1]
-            connect o0, i1 @[module-XXXXXXXXXX.rs 17:1]
-            connect o1, i2 @[module-XXXXXXXXXX.rs 18:1]
-            connect o2, i3 @[module-XXXXXXXXXX.rs 19:1]
-            connect o3, i0 @[module-XXXXXXXXXX.rs 20:1]
-        else when eq(index, UInt<8>(0h2)): @[module-XXXXXXXXXX.rs 21:1]
-            connect o0, i2 @[module-XXXXXXXXXX.rs 22:1]
-            connect o1, i3 @[module-XXXXXXXXXX.rs 23:1]
-            connect o2, i0 @[module-XXXXXXXXXX.rs 24:1]
-            connect o3, i1 @[module-XXXXXXXXXX.rs 25:1]
+        input swap: UInt<1> @[module-XXXXXXXXXX.rs 2:1]
+        input i1: Ty3 @[module-XXXXXXXXXX.rs 3:1]
+        input i2: Ty5 @[module-XXXXXXXXXX.rs 4:1]
+        output o1: Ty3 @[module-XXXXXXXXXX.rs 5:1]
+        output o2: Ty5 @[module-XXXXXXXXXX.rs 6:1]
+        when swap: @[module-XXXXXXXXXX.rs 7:1]
+            connect o1, i2 @[module-XXXXXXXXXX.rs 8:1]
+            connect o2, i1 @[module-XXXXXXXXXX.rs 9:1]
         else:
-            connect o0, i3 @[module-XXXXXXXXXX.rs 26:1]
-            connect o1, i0 @[module-XXXXXXXXXX.rs 27:1]
-            connect o2, i1 @[module-XXXXXXXXXX.rs 28:1]
-            connect o3, i2 @[module-XXXXXXXXXX.rs 29:1]
+            connect o1, i1 @[module-XXXXXXXXXX.rs 10:1]
+            connect o2, i2 @[module-XXXXXXXXXX.rs 11:1]
 ",
     };
     // FIXME: simplify_enums is broken when connecting enums that contain
@@ -3347,20 +3301,487 @@ circuit check_enum_connect_any:
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
-        "/test/check_enum_connect_any.fir": r"TODO",
+        "/test/check_enum_connect_any.fir": r"FIRRTL version 3.2.0
+circuit check_enum_connect_any:
+    type Ty0 = {|A, B, C|}
+    type Ty1 = {tag: Ty0, body: UInt<2>}
+    type Ty2 = {tag: Ty0, body: UInt<3>}
+    type Ty3 = {|HdlNone, HdlSome|}
+    type Ty4 = {tag: Ty3, body: UInt<1>}
+    type Ty5 = {tag: Ty3, body: UInt<2>}
+    type Ty6 = {tag: UInt<1>, body: UInt<2>}
+    type Ty7 = {tag: UInt<1>, body: UInt<1>}
+    type Ty8 = {tag: Ty3, body: UInt<0>}
+    type Ty9 = {tag: UInt<1>, body: UInt<0>}
+    module check_enum_connect_any: @[module-XXXXXXXXXX.rs 1:1]
+        input swap: UInt<1> @[module-XXXXXXXXXX.rs 2:1]
+        input i1: Ty1 @[module-XXXXXXXXXX.rs 3:1]
+        input i2: Ty2 @[module-XXXXXXXXXX.rs 4:1]
+        output o1: Ty1 @[module-XXXXXXXXXX.rs 5:1]
+        output o2: Ty2 @[module-XXXXXXXXXX.rs 6:1]
+        when swap: @[module-XXXXXXXXXX.rs 7:1]
+            match i2.tag: @[module-XXXXXXXXXX.rs 8:1]
+                A:
+                    wire __connect_variant_body: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
+                    connect __connect_variant_body, bits(i2.body, 1, 0) @[module-XXXXXXXXXX.rs 8:1]
+                    wire _bundle_literal_expr: Ty1
+                    connect _bundle_literal_expr.tag, {|A, B, C|}(A)
+                    connect _bundle_literal_expr.body, pad(__connect_variant_body, 2)
+                    connect o1, _bundle_literal_expr @[module-XXXXXXXXXX.rs 8:1]
+                B:
+                    wire __connect_variant_body_1: Ty4 @[module-XXXXXXXXXX.rs 8:1]
+                    wire _cast_bits_to_bundle_expr: Ty5
+                    wire _cast_bits_to_bundle_expr_flattened: Ty6
+                    connect _cast_bits_to_bundle_expr_flattened.tag, bits(bits(i2.body, 2, 0), 0, 0)
+                    wire _cast_bits_to_enum_expr: Ty3
+                    when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened.tag, 0)):
+                        connect _cast_bits_to_enum_expr, {|HdlNone, HdlSome|}(HdlNone)
+                    else:
+                        connect _cast_bits_to_enum_expr, {|HdlNone, HdlSome|}(HdlSome)
+                    connect _cast_bits_to_bundle_expr.tag, _cast_bits_to_enum_expr
+                    connect _cast_bits_to_bundle_expr_flattened.body, bits(bits(i2.body, 2, 0), 2, 1)
+                    connect _cast_bits_to_bundle_expr.body, _cast_bits_to_bundle_expr_flattened.body
+                    match _cast_bits_to_bundle_expr.tag: @[module-XXXXXXXXXX.rs 8:1]
+                        HdlNone:
+                            wire _bundle_literal_expr_1: Ty4
+                            connect _bundle_literal_expr_1.tag, {|HdlNone, HdlSome|}(HdlNone)
+                            connect _bundle_literal_expr_1.body, UInt<1>(0h0)
+                            connect __connect_variant_body_1, _bundle_literal_expr_1 @[module-XXXXXXXXXX.rs 8:1]
+                        HdlSome:
+                            wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1]
+                            wire _cast_bits_to_bundle_expr_1: Ty5
+                            wire _cast_bits_to_bundle_expr_flattened_1: Ty6
+                            connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 2, 0), 0, 0)
+                            wire _cast_bits_to_enum_expr_1: Ty3
+                            when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_1.tag, 0)):
+                                connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlNone)
+                            else:
+                                connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlSome)
+                            connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_enum_expr_1
+                            connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1)
+                            connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
+                            connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
+                            wire _bundle_literal_expr_2: Ty4
+                            connect _bundle_literal_expr_2.tag, {|HdlNone, HdlSome|}(HdlSome)
+                            connect _bundle_literal_expr_2.body, asUInt(__connect_variant_body_2)
+                            connect __connect_variant_body_1, _bundle_literal_expr_2 @[module-XXXXXXXXXX.rs 8:1]
+                    wire _bundle_literal_expr_3: Ty1
+                    connect _bundle_literal_expr_3.tag, {|A, B, C|}(B)
+                    wire _cast_bundle_to_bits_expr: Ty7
+                    wire _cast_enum_to_bits_expr: UInt<1>
+                    match __connect_variant_body_1.tag:
+                        HdlNone:
+                            connect _cast_enum_to_bits_expr, UInt<1>(0)
+                        HdlSome:
+                            connect _cast_enum_to_bits_expr, UInt<1>(1)
+                    connect _cast_bundle_to_bits_expr.tag, _cast_enum_to_bits_expr
+                    connect _cast_bundle_to_bits_expr.body, __connect_variant_body_1.body
+                    wire _cast_to_bits_expr: UInt<2>
+                    connect _cast_to_bits_expr, cat(_cast_bundle_to_bits_expr.body, _cast_bundle_to_bits_expr.tag)
+                    connect _bundle_literal_expr_3.body, _cast_to_bits_expr
+                    connect o1, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 8:1]
+                C:
+                    wire __connect_variant_body_3: Ty8 @[module-XXXXXXXXXX.rs 8:1]
+                    wire _cast_bits_to_bundle_expr_2: Ty8
+                    wire _cast_bits_to_bundle_expr_flattened_2: Ty9
+                    connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i2.body, 0, 0), 0, 0)
+                    wire _cast_bits_to_enum_expr_2: Ty3
+                    when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_2.tag, 0)):
+                        connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlNone)
+                    else:
+                        connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlSome)
+                    connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_enum_expr_2
+                    connect _cast_bits_to_bundle_expr_flattened_2.body, UInt<0>(0)
+                    connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
+                    connect __connect_variant_body_3, _cast_bits_to_bundle_expr_2 @[module-XXXXXXXXXX.rs 8:1]
+                    wire _bundle_literal_expr_4: Ty1
+                    connect _bundle_literal_expr_4.tag, {|A, B, C|}(C)
+                    wire _cast_bundle_to_bits_expr_1: Ty9
+                    wire _cast_enum_to_bits_expr_1: UInt<1>
+                    match __connect_variant_body_3.tag:
+                        HdlNone:
+                            connect _cast_enum_to_bits_expr_1, UInt<1>(0)
+                        HdlSome:
+                            connect _cast_enum_to_bits_expr_1, UInt<1>(1)
+                    connect _cast_bundle_to_bits_expr_1.tag, _cast_enum_to_bits_expr_1
+                    connect _cast_bundle_to_bits_expr_1.body, __connect_variant_body_3.body
+                    wire _cast_to_bits_expr_1: UInt<1>
+                    connect _cast_to_bits_expr_1, cat(_cast_bundle_to_bits_expr_1.body, _cast_bundle_to_bits_expr_1.tag)
+                    connect _bundle_literal_expr_4.body, pad(_cast_to_bits_expr_1, 2)
+                    connect o1, _bundle_literal_expr_4 @[module-XXXXXXXXXX.rs 8:1]
+            match i1.tag: @[module-XXXXXXXXXX.rs 9:1]
+                A:
+                    wire __connect_variant_body_4: UInt<2> @[module-XXXXXXXXXX.rs 9:1]
+                    connect __connect_variant_body_4, bits(i1.body, 0, 0) @[module-XXXXXXXXXX.rs 9:1]
+                    wire _bundle_literal_expr_5: Ty2
+                    connect _bundle_literal_expr_5.tag, {|A, B, C|}(A)
+                    connect _bundle_literal_expr_5.body, pad(__connect_variant_body_4, 3)
+                    connect o2, _bundle_literal_expr_5 @[module-XXXXXXXXXX.rs 9:1]
+                B:
+                    wire __connect_variant_body_5: Ty5 @[module-XXXXXXXXXX.rs 9:1]
+                    wire _cast_bits_to_bundle_expr_3: Ty4
+                    wire _cast_bits_to_bundle_expr_flattened_3: Ty7
+                    connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 1, 0), 0, 0)
+                    wire _cast_bits_to_enum_expr_3: Ty3
+                    when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_3.tag, 0)):
+                        connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlNone)
+                    else:
+                        connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlSome)
+                    connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_enum_expr_3
+                    connect _cast_bits_to_bundle_expr_flattened_3.body, bits(bits(i1.body, 1, 0), 1, 1)
+                    connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
+                    match _cast_bits_to_bundle_expr_3.tag: @[module-XXXXXXXXXX.rs 9:1]
+                        HdlNone:
+                            wire _bundle_literal_expr_6: Ty5
+                            connect _bundle_literal_expr_6.tag, {|HdlNone, HdlSome|}(HdlNone)
+                            connect _bundle_literal_expr_6.body, UInt<2>(0h0)
+                            connect __connect_variant_body_5, _bundle_literal_expr_6 @[module-XXXXXXXXXX.rs 9:1]
+                        HdlSome:
+                            wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1]
+                            wire _cast_bits_to_bundle_expr_4: Ty4
+                            wire _cast_bits_to_bundle_expr_flattened_4: Ty7
+                            connect _cast_bits_to_bundle_expr_flattened_4.tag, bits(bits(i1.body, 1, 0), 0, 0)
+                            wire _cast_bits_to_enum_expr_4: Ty3
+                            when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_4.tag, 0)):
+                                connect _cast_bits_to_enum_expr_4, {|HdlNone, HdlSome|}(HdlNone)
+                            else:
+                                connect _cast_bits_to_enum_expr_4, {|HdlNone, HdlSome|}(HdlSome)
+                            connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_enum_expr_4
+                            connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1)
+                            connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body
+                            connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
+                            wire _bundle_literal_expr_7: Ty5
+                            connect _bundle_literal_expr_7.tag, {|HdlNone, HdlSome|}(HdlSome)
+                            connect _bundle_literal_expr_7.body, asUInt(__connect_variant_body_6)
+                            connect __connect_variant_body_5, _bundle_literal_expr_7 @[module-XXXXXXXXXX.rs 9:1]
+                    wire _bundle_literal_expr_8: Ty2
+                    connect _bundle_literal_expr_8.tag, {|A, B, C|}(B)
+                    wire _cast_bundle_to_bits_expr_2: Ty6
+                    wire _cast_enum_to_bits_expr_2: UInt<1>
+                    match __connect_variant_body_5.tag:
+                        HdlNone:
+                            connect _cast_enum_to_bits_expr_2, UInt<1>(0)
+                        HdlSome:
+                            connect _cast_enum_to_bits_expr_2, UInt<1>(1)
+                    connect _cast_bundle_to_bits_expr_2.tag, _cast_enum_to_bits_expr_2
+                    connect _cast_bundle_to_bits_expr_2.body, __connect_variant_body_5.body
+                    wire _cast_to_bits_expr_2: UInt<3>
+                    connect _cast_to_bits_expr_2, cat(_cast_bundle_to_bits_expr_2.body, _cast_bundle_to_bits_expr_2.tag)
+                    connect _bundle_literal_expr_8.body, _cast_to_bits_expr_2
+                    connect o2, _bundle_literal_expr_8 @[module-XXXXXXXXXX.rs 9:1]
+                C:
+                    wire __connect_variant_body_7: Ty8 @[module-XXXXXXXXXX.rs 9:1]
+                    wire _cast_bits_to_bundle_expr_5: Ty8
+                    wire _cast_bits_to_bundle_expr_flattened_5: Ty9
+                    connect _cast_bits_to_bundle_expr_flattened_5.tag, bits(bits(i1.body, 0, 0), 0, 0)
+                    wire _cast_bits_to_enum_expr_5: Ty3
+                    when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_5.tag, 0)):
+                        connect _cast_bits_to_enum_expr_5, {|HdlNone, HdlSome|}(HdlNone)
+                    else:
+                        connect _cast_bits_to_enum_expr_5, {|HdlNone, HdlSome|}(HdlSome)
+                    connect _cast_bits_to_bundle_expr_5.tag, _cast_bits_to_enum_expr_5
+                    connect _cast_bits_to_bundle_expr_flattened_5.body, UInt<0>(0)
+                    connect _cast_bits_to_bundle_expr_5.body, _cast_bits_to_bundle_expr_flattened_5.body
+                    connect __connect_variant_body_7, _cast_bits_to_bundle_expr_5 @[module-XXXXXXXXXX.rs 9:1]
+                    wire _bundle_literal_expr_9: Ty2
+                    connect _bundle_literal_expr_9.tag, {|A, B, C|}(C)
+                    wire _cast_bundle_to_bits_expr_3: Ty9
+                    wire _cast_enum_to_bits_expr_3: UInt<1>
+                    match __connect_variant_body_7.tag:
+                        HdlNone:
+                            connect _cast_enum_to_bits_expr_3, UInt<1>(0)
+                        HdlSome:
+                            connect _cast_enum_to_bits_expr_3, UInt<1>(1)
+                    connect _cast_bundle_to_bits_expr_3.tag, _cast_enum_to_bits_expr_3
+                    connect _cast_bundle_to_bits_expr_3.body, __connect_variant_body_7.body
+                    wire _cast_to_bits_expr_3: UInt<1>
+                    connect _cast_to_bits_expr_3, cat(_cast_bundle_to_bits_expr_3.body, _cast_bundle_to_bits_expr_3.tag)
+                    connect _bundle_literal_expr_9.body, pad(_cast_to_bits_expr_3, 3)
+                    connect o2, _bundle_literal_expr_9 @[module-XXXXXXXXXX.rs 9:1]
+        else:
+            connect o1, i1 @[module-XXXXXXXXXX.rs 10:1]
+            connect o2, i2 @[module-XXXXXXXXXX.rs 11:1]
+",
     };
     let m = simplify_enums(orig_m, SimplifyEnumsKind::ReplaceWithBundleOfUInts).unwrap();
     dbg!(m);
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
-        "/test/check_enum_connect_any.fir": r"TODO",
-    };
+        "/test/check_enum_connect_any.fir": r"FIRRTL version 3.2.0
+circuit check_enum_connect_any:
+    type Ty0 = {tag: UInt<2>, body: UInt<2>}
+    type Ty1 = {tag: UInt<2>, body: UInt<3>}
+    type Ty2 = {tag: UInt<1>, body: UInt<1>}
+    type Ty3 = {tag: UInt<1>, body: UInt<2>}
+    type Ty4 = {tag: UInt<1>, body: UInt<0>}
+    module check_enum_connect_any: @[module-XXXXXXXXXX.rs 1:1]
+        input swap: UInt<1> @[module-XXXXXXXXXX.rs 2:1]
+        input i1: Ty0 @[module-XXXXXXXXXX.rs 3:1]
+        input i2: Ty1 @[module-XXXXXXXXXX.rs 4:1]
+        output o1: Ty0 @[module-XXXXXXXXXX.rs 5:1]
+        output o2: Ty1 @[module-XXXXXXXXXX.rs 6:1]
+        when swap: @[module-XXXXXXXXXX.rs 7:1]
+            when eq(i2.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 8:1]
+                wire __connect_variant_body: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
+                connect __connect_variant_body, bits(i2.body, 1, 0) @[module-XXXXXXXXXX.rs 8:1]
+                wire _bundle_literal_expr: Ty0
+                connect _bundle_literal_expr.tag, UInt<2>(0h0)
+                connect _bundle_literal_expr.body, pad(__connect_variant_body, 2)
+                connect o1, _bundle_literal_expr @[module-XXXXXXXXXX.rs 8:1]
+            else when eq(i2.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 8:1]
+                wire __connect_variant_body_1: Ty2 @[module-XXXXXXXXXX.rs 8:1]
+                wire _cast_bits_to_bundle_expr: Ty3
+                wire _cast_bits_to_bundle_expr_flattened: Ty3
+                connect _cast_bits_to_bundle_expr_flattened.tag, bits(bits(i2.body, 2, 0), 0, 0)
+                connect _cast_bits_to_bundle_expr.tag, _cast_bits_to_bundle_expr_flattened.tag
+                connect _cast_bits_to_bundle_expr_flattened.body, bits(bits(i2.body, 2, 0), 2, 1)
+                connect _cast_bits_to_bundle_expr.body, _cast_bits_to_bundle_expr_flattened.body
+                when eq(_cast_bits_to_bundle_expr.tag, UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 8:1]
+                    wire _bundle_literal_expr_1: Ty2
+                    connect _bundle_literal_expr_1.tag, UInt<1>(0h0)
+                    connect _bundle_literal_expr_1.body, UInt<1>(0h0)
+                    connect __connect_variant_body_1, _bundle_literal_expr_1 @[module-XXXXXXXXXX.rs 8:1]
+                else:
+                    wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1]
+                    wire _cast_bits_to_bundle_expr_1: Ty3
+                    wire _cast_bits_to_bundle_expr_flattened_1: Ty3
+                    connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 2, 0), 0, 0)
+                    connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_bundle_expr_flattened_1.tag
+                    connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1)
+                    connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
+                    connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
+                    wire _bundle_literal_expr_2: Ty2
+                    connect _bundle_literal_expr_2.tag, UInt<1>(0h1)
+                    connect _bundle_literal_expr_2.body, asUInt(__connect_variant_body_2)
+                    connect __connect_variant_body_1, _bundle_literal_expr_2 @[module-XXXXXXXXXX.rs 8:1]
+                wire _bundle_literal_expr_3: Ty0
+                connect _bundle_literal_expr_3.tag, UInt<2>(0h1)
+                wire _cast_bundle_to_bits_expr: Ty2
+                connect _cast_bundle_to_bits_expr.tag, __connect_variant_body_1.tag
+                connect _cast_bundle_to_bits_expr.body, __connect_variant_body_1.body
+                wire _cast_to_bits_expr: UInt<2>
+                connect _cast_to_bits_expr, cat(_cast_bundle_to_bits_expr.body, _cast_bundle_to_bits_expr.tag)
+                connect _bundle_literal_expr_3.body, _cast_to_bits_expr
+                connect o1, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 8:1]
+            else:
+                wire __connect_variant_body_3: Ty4 @[module-XXXXXXXXXX.rs 8:1]
+                wire _cast_bits_to_bundle_expr_2: Ty4
+                wire _cast_bits_to_bundle_expr_flattened_2: Ty4
+                connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i2.body, 0, 0), 0, 0)
+                connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_bundle_expr_flattened_2.tag
+                connect _cast_bits_to_bundle_expr_flattened_2.body, UInt<0>(0)
+                connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
+                connect __connect_variant_body_3, _cast_bits_to_bundle_expr_2 @[module-XXXXXXXXXX.rs 8:1]
+                wire _bundle_literal_expr_4: Ty0
+                connect _bundle_literal_expr_4.tag, UInt<2>(0h2)
+                wire _cast_bundle_to_bits_expr_1: Ty4
+                connect _cast_bundle_to_bits_expr_1.tag, __connect_variant_body_3.tag
+                connect _cast_bundle_to_bits_expr_1.body, __connect_variant_body_3.body
+                wire _cast_to_bits_expr_1: UInt<1>
+                connect _cast_to_bits_expr_1, cat(_cast_bundle_to_bits_expr_1.body, _cast_bundle_to_bits_expr_1.tag)
+                connect _bundle_literal_expr_4.body, pad(_cast_to_bits_expr_1, 2)
+                connect o1, _bundle_literal_expr_4 @[module-XXXXXXXXXX.rs 8:1]
+            when eq(i1.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
+                wire __connect_variant_body_4: UInt<2> @[module-XXXXXXXXXX.rs 9:1]
+                connect __connect_variant_body_4, bits(i1.body, 0, 0) @[module-XXXXXXXXXX.rs 9:1]
+                wire _bundle_literal_expr_5: Ty1
+                connect _bundle_literal_expr_5.tag, UInt<2>(0h0)
+                connect _bundle_literal_expr_5.body, pad(__connect_variant_body_4, 3)
+                connect o2, _bundle_literal_expr_5 @[module-XXXXXXXXXX.rs 9:1]
+            else when eq(i1.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 9:1]
+                wire __connect_variant_body_5: Ty3 @[module-XXXXXXXXXX.rs 9:1]
+                wire _cast_bits_to_bundle_expr_3: Ty2
+                wire _cast_bits_to_bundle_expr_flattened_3: Ty2
+                connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 1, 0), 0, 0)
+                connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_bundle_expr_flattened_3.tag
+                connect _cast_bits_to_bundle_expr_flattened_3.body, bits(bits(i1.body, 1, 0), 1, 1)
+                connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
+                when eq(_cast_bits_to_bundle_expr_3.tag, UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
+                    wire _bundle_literal_expr_6: Ty3
+                    connect _bundle_literal_expr_6.tag, UInt<1>(0h0)
+                    connect _bundle_literal_expr_6.body, UInt<2>(0h0)
+                    connect __connect_variant_body_5, _bundle_literal_expr_6 @[module-XXXXXXXXXX.rs 9:1]
+                else:
+                    wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1]
+                    wire _cast_bits_to_bundle_expr_4: Ty2
+                    wire _cast_bits_to_bundle_expr_flattened_4: Ty2
+                    connect _cast_bits_to_bundle_expr_flattened_4.tag, bits(bits(i1.body, 1, 0), 0, 0)
+                    connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_bundle_expr_flattened_4.tag
+                    connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1)
+                    connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body
+                    connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
+                    wire _bundle_literal_expr_7: Ty3
+                    connect _bundle_literal_expr_7.tag, UInt<1>(0h1)
+                    connect _bundle_literal_expr_7.body, asUInt(__connect_variant_body_6)
+                    connect __connect_variant_body_5, _bundle_literal_expr_7 @[module-XXXXXXXXXX.rs 9:1]
+                wire _bundle_literal_expr_8: Ty1
+                connect _bundle_literal_expr_8.tag, UInt<2>(0h1)
+                wire _cast_bundle_to_bits_expr_2: Ty3
+                connect _cast_bundle_to_bits_expr_2.tag, __connect_variant_body_5.tag
+                connect _cast_bundle_to_bits_expr_2.body, __connect_variant_body_5.body
+                wire _cast_to_bits_expr_2: UInt<3>
+                connect _cast_to_bits_expr_2, cat(_cast_bundle_to_bits_expr_2.body, _cast_bundle_to_bits_expr_2.tag)
+                connect _bundle_literal_expr_8.body, _cast_to_bits_expr_2
+                connect o2, _bundle_literal_expr_8 @[module-XXXXXXXXXX.rs 9:1]
+            else:
+                wire __connect_variant_body_7: Ty4 @[module-XXXXXXXXXX.rs 9:1]
+                wire _cast_bits_to_bundle_expr_5: Ty4
+                wire _cast_bits_to_bundle_expr_flattened_5: Ty4
+                connect _cast_bits_to_bundle_expr_flattened_5.tag, bits(bits(i1.body, 0, 0), 0, 0)
+                connect _cast_bits_to_bundle_expr_5.tag, _cast_bits_to_bundle_expr_flattened_5.tag
+                connect _cast_bits_to_bundle_expr_flattened_5.body, UInt<0>(0)
+                connect _cast_bits_to_bundle_expr_5.body, _cast_bits_to_bundle_expr_flattened_5.body
+                connect __connect_variant_body_7, _cast_bits_to_bundle_expr_5 @[module-XXXXXXXXXX.rs 9:1]
+                wire _bundle_literal_expr_9: Ty1
+                connect _bundle_literal_expr_9.tag, UInt<2>(0h2)
+                wire _cast_bundle_to_bits_expr_3: Ty4
+                connect _cast_bundle_to_bits_expr_3.tag, __connect_variant_body_7.tag
+                connect _cast_bundle_to_bits_expr_3.body, __connect_variant_body_7.body
+                wire _cast_to_bits_expr_3: UInt<1>
+                connect _cast_to_bits_expr_3, cat(_cast_bundle_to_bits_expr_3.body, _cast_bundle_to_bits_expr_3.tag)
+                connect _bundle_literal_expr_9.body, pad(_cast_to_bits_expr_3, 3)
+                connect o2, _bundle_literal_expr_9 @[module-XXXXXXXXXX.rs 9:1]
+        else:
+            connect o1, i1 @[module-XXXXXXXXXX.rs 10:1]
+            connect o2, i2 @[module-XXXXXXXXXX.rs 11:1]
+",
+    }
     let m = simplify_enums(orig_m, SimplifyEnumsKind::ReplaceWithUInt).unwrap();
     dbg!(m);
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
-        "/test/check_enum_connect_any.fir": r"TODO",
+        "/test/check_enum_connect_any.fir": r"FIRRTL version 3.2.0
+circuit check_enum_connect_any:
+    type Ty0 = {tag: UInt<2>, body: UInt<2>}
+    type Ty1 = {tag: UInt<1>, body: UInt<1>}
+    type Ty2 = {tag: UInt<2>, body: UInt<3>}
+    type Ty3 = {tag: UInt<1>, body: UInt<2>}
+    module check_enum_connect_any: @[module-XXXXXXXXXX.rs 1:1]
+        input swap: UInt<1> @[module-XXXXXXXXXX.rs 2:1]
+        input i1: UInt<4> @[module-XXXXXXXXXX.rs 3:1]
+        input i2: UInt<5> @[module-XXXXXXXXXX.rs 4:1]
+        output o1: UInt<4> @[module-XXXXXXXXXX.rs 5:1]
+        output o2: UInt<5> @[module-XXXXXXXXXX.rs 6:1]
+        when swap: @[module-XXXXXXXXXX.rs 7:1]
+            when eq(bits(i2, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 8:1]
+                wire __connect_variant_body: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
+                connect __connect_variant_body, bits(bits(i2, 4, 2), 1, 0) @[module-XXXXXXXXXX.rs 8:1]
+                wire _bundle_literal_expr: Ty0
+                connect _bundle_literal_expr.tag, UInt<2>(0h0)
+                connect _bundle_literal_expr.body, pad(__connect_variant_body, 2)
+                wire _cast_bundle_to_bits_expr: Ty0
+                connect _cast_bundle_to_bits_expr.tag, _bundle_literal_expr.tag
+                connect _cast_bundle_to_bits_expr.body, _bundle_literal_expr.body
+                wire _cast_to_bits_expr: UInt<4>
+                connect _cast_to_bits_expr, cat(_cast_bundle_to_bits_expr.body, _cast_bundle_to_bits_expr.tag)
+                connect o1, _cast_to_bits_expr @[module-XXXXXXXXXX.rs 8:1]
+            else when eq(bits(i2, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 8:1]
+                wire __connect_variant_body_1: UInt<2> @[module-XXXXXXXXXX.rs 8:1]
+                when eq(bits(bits(bits(i2, 4, 2), 2, 0), 0, 0), UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 8:1]
+                    wire _bundle_literal_expr_1: Ty1
+                    connect _bundle_literal_expr_1.tag, UInt<1>(0h0)
+                    connect _bundle_literal_expr_1.body, UInt<1>(0h0)
+                    wire _cast_bundle_to_bits_expr_1: Ty1
+                    connect _cast_bundle_to_bits_expr_1.tag, _bundle_literal_expr_1.tag
+                    connect _cast_bundle_to_bits_expr_1.body, _bundle_literal_expr_1.body
+                    wire _cast_to_bits_expr_1: UInt<2>
+                    connect _cast_to_bits_expr_1, cat(_cast_bundle_to_bits_expr_1.body, _cast_bundle_to_bits_expr_1.tag)
+                    connect __connect_variant_body_1, _cast_to_bits_expr_1 @[module-XXXXXXXXXX.rs 8:1]
+                else:
+                    wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1]
+                    connect __connect_variant_body_2, asSInt(bits(bits(bits(bits(i2, 4, 2), 2, 0), 2, 1), 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
+                    wire _bundle_literal_expr_2: Ty1
+                    connect _bundle_literal_expr_2.tag, UInt<1>(0h1)
+                    connect _bundle_literal_expr_2.body, asUInt(__connect_variant_body_2)
+                    wire _cast_bundle_to_bits_expr_2: Ty1
+                    connect _cast_bundle_to_bits_expr_2.tag, _bundle_literal_expr_2.tag
+                    connect _cast_bundle_to_bits_expr_2.body, _bundle_literal_expr_2.body
+                    wire _cast_to_bits_expr_2: UInt<2>
+                    connect _cast_to_bits_expr_2, cat(_cast_bundle_to_bits_expr_2.body, _cast_bundle_to_bits_expr_2.tag)
+                    connect __connect_variant_body_1, _cast_to_bits_expr_2 @[module-XXXXXXXXXX.rs 8:1]
+                wire _bundle_literal_expr_3: Ty0
+                connect _bundle_literal_expr_3.tag, UInt<2>(0h1)
+                connect _bundle_literal_expr_3.body, __connect_variant_body_1
+                wire _cast_bundle_to_bits_expr_3: Ty0
+                connect _cast_bundle_to_bits_expr_3.tag, _bundle_literal_expr_3.tag
+                connect _cast_bundle_to_bits_expr_3.body, _bundle_literal_expr_3.body
+                wire _cast_to_bits_expr_3: UInt<4>
+                connect _cast_to_bits_expr_3, cat(_cast_bundle_to_bits_expr_3.body, _cast_bundle_to_bits_expr_3.tag)
+                connect o1, _cast_to_bits_expr_3 @[module-XXXXXXXXXX.rs 8:1]
+            else:
+                wire __connect_variant_body_3: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
+                connect __connect_variant_body_3, bits(bits(i2, 4, 2), 0, 0) @[module-XXXXXXXXXX.rs 8:1]
+                wire _bundle_literal_expr_4: Ty0
+                connect _bundle_literal_expr_4.tag, UInt<2>(0h2)
+                connect _bundle_literal_expr_4.body, pad(__connect_variant_body_3, 2)
+                wire _cast_bundle_to_bits_expr_4: Ty0
+                connect _cast_bundle_to_bits_expr_4.tag, _bundle_literal_expr_4.tag
+                connect _cast_bundle_to_bits_expr_4.body, _bundle_literal_expr_4.body
+                wire _cast_to_bits_expr_4: UInt<4>
+                connect _cast_to_bits_expr_4, cat(_cast_bundle_to_bits_expr_4.body, _cast_bundle_to_bits_expr_4.tag)
+                connect o1, _cast_to_bits_expr_4 @[module-XXXXXXXXXX.rs 8:1]
+            when eq(bits(i1, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
+                wire __connect_variant_body_4: UInt<2> @[module-XXXXXXXXXX.rs 9:1]
+                connect __connect_variant_body_4, bits(bits(i1, 3, 2), 0, 0) @[module-XXXXXXXXXX.rs 9:1]
+                wire _bundle_literal_expr_5: Ty2
+                connect _bundle_literal_expr_5.tag, UInt<2>(0h0)
+                connect _bundle_literal_expr_5.body, pad(__connect_variant_body_4, 3)
+                wire _cast_bundle_to_bits_expr_5: Ty2
+                connect _cast_bundle_to_bits_expr_5.tag, _bundle_literal_expr_5.tag
+                connect _cast_bundle_to_bits_expr_5.body, _bundle_literal_expr_5.body
+                wire _cast_to_bits_expr_5: UInt<5>
+                connect _cast_to_bits_expr_5, cat(_cast_bundle_to_bits_expr_5.body, _cast_bundle_to_bits_expr_5.tag)
+                connect o2, _cast_to_bits_expr_5 @[module-XXXXXXXXXX.rs 9:1]
+            else when eq(bits(i1, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 9:1]
+                wire __connect_variant_body_5: UInt<3> @[module-XXXXXXXXXX.rs 9:1]
+                when eq(bits(bits(bits(i1, 3, 2), 1, 0), 0, 0), UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
+                    wire _bundle_literal_expr_6: Ty3
+                    connect _bundle_literal_expr_6.tag, UInt<1>(0h0)
+                    connect _bundle_literal_expr_6.body, UInt<2>(0h0)
+                    wire _cast_bundle_to_bits_expr_6: Ty3
+                    connect _cast_bundle_to_bits_expr_6.tag, _bundle_literal_expr_6.tag
+                    connect _cast_bundle_to_bits_expr_6.body, _bundle_literal_expr_6.body
+                    wire _cast_to_bits_expr_6: UInt<3>
+                    connect _cast_to_bits_expr_6, cat(_cast_bundle_to_bits_expr_6.body, _cast_bundle_to_bits_expr_6.tag)
+                    connect __connect_variant_body_5, _cast_to_bits_expr_6 @[module-XXXXXXXXXX.rs 9:1]
+                else:
+                    wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1]
+                    connect __connect_variant_body_6, asSInt(bits(bits(bits(bits(i1, 3, 2), 1, 0), 1, 1), 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
+                    wire _bundle_literal_expr_7: Ty3
+                    connect _bundle_literal_expr_7.tag, UInt<1>(0h1)
+                    connect _bundle_literal_expr_7.body, asUInt(__connect_variant_body_6)
+                    wire _cast_bundle_to_bits_expr_7: Ty3
+                    connect _cast_bundle_to_bits_expr_7.tag, _bundle_literal_expr_7.tag
+                    connect _cast_bundle_to_bits_expr_7.body, _bundle_literal_expr_7.body
+                    wire _cast_to_bits_expr_7: UInt<3>
+                    connect _cast_to_bits_expr_7, cat(_cast_bundle_to_bits_expr_7.body, _cast_bundle_to_bits_expr_7.tag)
+                    connect __connect_variant_body_5, _cast_to_bits_expr_7 @[module-XXXXXXXXXX.rs 9:1]
+                wire _bundle_literal_expr_8: Ty2
+                connect _bundle_literal_expr_8.tag, UInt<2>(0h1)
+                connect _bundle_literal_expr_8.body, __connect_variant_body_5
+                wire _cast_bundle_to_bits_expr_8: Ty2
+                connect _cast_bundle_to_bits_expr_8.tag, _bundle_literal_expr_8.tag
+                connect _cast_bundle_to_bits_expr_8.body, _bundle_literal_expr_8.body
+                wire _cast_to_bits_expr_8: UInt<5>
+                connect _cast_to_bits_expr_8, cat(_cast_bundle_to_bits_expr_8.body, _cast_bundle_to_bits_expr_8.tag)
+                connect o2, _cast_to_bits_expr_8 @[module-XXXXXXXXXX.rs 9:1]
+            else:
+                wire __connect_variant_body_7: UInt<1> @[module-XXXXXXXXXX.rs 9:1]
+                connect __connect_variant_body_7, bits(bits(i1, 3, 2), 0, 0) @[module-XXXXXXXXXX.rs 9:1]
+                wire _bundle_literal_expr_9: Ty2
+                connect _bundle_literal_expr_9.tag, UInt<2>(0h2)
+                connect _bundle_literal_expr_9.body, pad(__connect_variant_body_7, 3)
+                wire _cast_bundle_to_bits_expr_9: Ty2
+                connect _cast_bundle_to_bits_expr_9.tag, _bundle_literal_expr_9.tag
+                connect _cast_bundle_to_bits_expr_9.body, _bundle_literal_expr_9.body
+                wire _cast_to_bits_expr_9: UInt<5>
+                connect _cast_to_bits_expr_9, cat(_cast_bundle_to_bits_expr_9.body, _cast_bundle_to_bits_expr_9.tag)
+                connect o2, _cast_to_bits_expr_9 @[module-XXXXXXXXXX.rs 9:1]
+        else:
+            connect o1, i1 @[module-XXXXXXXXXX.rs 10:1]
+            connect o2, i2 @[module-XXXXXXXXXX.rs 11:1]
+",
     };
 }

From edcea1adc3304d72766559790f070c8dd7eb099e Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 30 Sep 2024 22:33:27 -0700
Subject: [PATCH 027/190] add firrtl comments when connecting expressions with
 different types

---
 crates/fayalite/src/firrtl.rs   |   9 +++
 crates/fayalite/tests/module.rs | 102 ++++++++++++++++++++++++++++++++
 2 files changed, 111 insertions(+)

diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index 4a1547d..79db858 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -1956,6 +1956,15 @@ impl<'a> Exporter<'a> {
                     rhs,
                     source_location,
                 }) => {
+                    if Expr::ty(lhs) != Expr::ty(rhs) {
+                        writeln!(
+                            body,
+                            "{indent}; connect different types:\n{indent}; lhs: {:?}\n{indent}; rhs: {:?}",
+                            Expr::ty(lhs),
+                            Expr::ty(rhs),
+                        )
+                        .unwrap();
+                    }
                     let lhs = self.expr(lhs, &definitions, false);
                     let rhs = self.expr(rhs, &definitions, false);
                     writeln!(
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 9d5a898..4dfeca5 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -722,6 +722,9 @@ circuit check_struct_enum_match:
                     A:
                         connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
                     B(_match_arm_value):
+                        ; connect different types:
+                        ; lhs: UInt<8>
+                        ; rhs: UInt<9>
                         connect o[0], add(_match_arm_value, UInt<8>(0h2)) @[module-XXXXXXXXXX.rs 8:1]
                     C(_match_arm_value_1):
                         connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
@@ -738,6 +741,9 @@ circuit check_struct_enum_match:
             B(_match_arm_value_4):
                 connect o[2], _match_arm_value_4 @[module-XXXXXXXXXX.rs 15:1]
             C(_match_arm_value_5):
+                ; connect different types:
+                ; lhs: UInt<8>
+                ; rhs: UInt<1>
                 connect o[2], _match_arm_value_5[1] @[module-XXXXXXXXXX.rs 16:1]
         match i2: @[module-XXXXXXXXXX.rs 17:1]
             A:
@@ -752,6 +758,9 @@ circuit check_struct_enum_match:
             B(_match_arm_value_8):
                 connect o[4], UInt<8>(0h1) @[module-XXXXXXXXXX.rs 23:1]
             C(_match_arm_value_9):
+                ; connect different types:
+                ; lhs: UInt<8>
+                ; rhs: UInt<1>
                 connect o[4], _match_arm_value_9[2] @[module-XXXXXXXXXX.rs 24:1]
 ",
     };
@@ -777,6 +786,9 @@ circuit check_struct_enum_match:
                     A:
                         connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
                     B:
+                        ; connect different types:
+                        ; lhs: UInt<8>
+                        ; rhs: UInt<9>
                         connect o[0], add(bits(i2.body, 7, 0), UInt<8>(0h2)) @[module-XXXXXXXXXX.rs 8:1]
                     C:
                         connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
@@ -801,6 +813,9 @@ circuit check_struct_enum_match:
                 connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1]
                 connect _cast_bits_to_array_expr_flattened[2], bits(bits(i2.body, 2, 0), 2, 2)
                 connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2]
+                ; connect different types:
+                ; lhs: UInt<8>
+                ; rhs: UInt<1>
                 connect o[2], _cast_bits_to_array_expr[1] @[module-XXXXXXXXXX.rs 16:1]
         match i2.tag: @[module-XXXXXXXXXX.rs 17:1]
             A:
@@ -823,6 +838,9 @@ circuit check_struct_enum_match:
                 connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1]
                 connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(i2.body, 2, 0), 2, 2)
                 connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
+                ; connect different types:
+                ; lhs: UInt<8>
+                ; rhs: UInt<1>
                 connect o[4], _cast_bits_to_array_expr_1[2] @[module-XXXXXXXXXX.rs 24:1]
 ",
     };
@@ -843,6 +861,9 @@ circuit check_struct_enum_match:
             when eq(i2.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 6:1]
                 connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
             else when eq(i2.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 6:1]
+                ; connect different types:
+                ; lhs: UInt<8>
+                ; rhs: UInt<9>
                 connect o[0], add(bits(i2.body, 7, 0), UInt<8>(0h2)) @[module-XXXXXXXXXX.rs 8:1]
             else:
                 connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
@@ -865,6 +886,9 @@ circuit check_struct_enum_match:
             connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1]
             connect _cast_bits_to_array_expr_flattened[2], bits(bits(i2.body, 2, 0), 2, 2)
             connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2]
+            ; connect different types:
+            ; lhs: UInt<8>
+            ; rhs: UInt<1>
             connect o[2], _cast_bits_to_array_expr[1] @[module-XXXXXXXXXX.rs 16:1]
         when eq(i2.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 17:1]
             connect o[3], UInt<8>(0h0) @[module-XXXXXXXXXX.rs 18:1]
@@ -885,6 +909,9 @@ circuit check_struct_enum_match:
             connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1]
             connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(i2.body, 2, 0), 2, 2)
             connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
+            ; connect different types:
+            ; lhs: UInt<8>
+            ; rhs: UInt<1>
             connect o[4], _cast_bits_to_array_expr_1[2] @[module-XXXXXXXXXX.rs 24:1]
 ",
     };
@@ -903,6 +930,9 @@ circuit check_struct_enum_match:
             when eq(bits(i2, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 6:1]
                 connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
             else when eq(bits(i2, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 6:1]
+                ; connect different types:
+                ; lhs: UInt<8>
+                ; rhs: UInt<9>
                 connect o[0], add(bits(bits(i2, 9, 2), 7, 0), UInt<8>(0h2)) @[module-XXXXXXXXXX.rs 8:1]
             else:
                 connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
@@ -925,6 +955,9 @@ circuit check_struct_enum_match:
             connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1]
             connect _cast_bits_to_array_expr_flattened[2], bits(bits(bits(i2, 9, 2), 2, 0), 2, 2)
             connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2]
+            ; connect different types:
+            ; lhs: UInt<8>
+            ; rhs: UInt<1>
             connect o[2], _cast_bits_to_array_expr[1] @[module-XXXXXXXXXX.rs 16:1]
         when eq(bits(i2, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 17:1]
             connect o[3], UInt<8>(0h0) @[module-XXXXXXXXXX.rs 18:1]
@@ -945,6 +978,9 @@ circuit check_struct_enum_match:
             connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1]
             connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(bits(i2, 9, 2), 2, 0), 2, 2)
             connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
+            ; connect different types:
+            ; lhs: UInt<8>
+            ; rhs: UInt<1>
             connect o[4], _cast_bits_to_array_expr_1[2] @[module-XXXXXXXXXX.rs 24:1]
 ",
     };
@@ -2454,10 +2490,16 @@ circuit check_memory_of_enum: %[[
         connect mem_1.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
         connect mem_1.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
         connect mem_1.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
+        ; connect different types:
+        ; lhs: UInt<4>
+        ; rhs: UInt<8>
         connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
         connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
         connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
         connect rdata, mem_r0.data @[module-XXXXXXXXXX.rs 13:1]
+        ; connect different types:
+        ; lhs: UInt<4>
+        ; rhs: UInt<8>
         connect mem_w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
         connect mem_w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
         connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
@@ -2578,10 +2620,16 @@ circuit check_memory_of_enum: %[[
         connect mem_w1_1.data, mem_w1.data @[module-XXXXXXXXXX.rs 14:1]
         connect mem_w1_1.mask.tag, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
         connect mem_w1_1.mask.body, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
+        ; connect different types:
+        ; lhs: UInt<4>
+        ; rhs: UInt<8>
         connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
         connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
         connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
         connect rdata, mem_r0.data @[module-XXXXXXXXXX.rs 13:1]
+        ; connect different types:
+        ; lhs: UInt<4>
+        ; rhs: UInt<8>
         connect mem_w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
         connect mem_w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
         connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
@@ -2702,10 +2750,16 @@ circuit check_memory_of_enum: %[[
         connect mem_w1_1.data, mem_w1.data @[module-XXXXXXXXXX.rs 14:1]
         connect mem_w1_1.mask.tag, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
         connect mem_w1_1.mask.body, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
+        ; connect different types:
+        ; lhs: UInt<4>
+        ; rhs: UInt<8>
         connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
         connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
         connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
         connect rdata, mem_r0.data @[module-XXXXXXXXXX.rs 13:1]
+        ; connect different types:
+        ; lhs: UInt<4>
+        ; rhs: UInt<8>
         connect mem_w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
         connect mem_w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
         connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
@@ -2778,10 +2832,16 @@ circuit check_memory_of_enum: %[[
             read-under-write => old
             reader => r0
             writer => w1
+        ; connect different types:
+        ; lhs: UInt<4>
+        ; rhs: UInt<8>
         connect `mem`.r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
         connect `mem`.r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
         connect `mem`.r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
         connect rdata, `mem`.r0.data @[module-XXXXXXXXXX.rs 13:1]
+        ; connect different types:
+        ; lhs: UInt<4>
+        ; rhs: UInt<8>
         connect `mem`.w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
         connect `mem`.w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
         connect `mem`.w1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
@@ -3284,7 +3344,13 @@ circuit check_enum_connect_any:
         output o1: Ty3 @[module-XXXXXXXXXX.rs 5:1]
         output o2: Ty5 @[module-XXXXXXXXXX.rs 6:1]
         when swap: @[module-XXXXXXXXXX.rs 7:1]
+            ; connect different types:
+            ; lhs: Enum {A(UInt<1>), B(Enum {HdlNone, HdlSome(SInt<1>)}), C(Enum {HdlNone, HdlSome(Bundle {})})}
+            ; rhs: Enum {A(UInt<2>), B(Enum {HdlNone, HdlSome(SInt<2>)}), C(Enum {HdlNone, HdlSome(Bundle {})})}
             connect o1, i2 @[module-XXXXXXXXXX.rs 8:1]
+            ; connect different types:
+            ; lhs: Enum {A(UInt<2>), B(Enum {HdlNone, HdlSome(SInt<2>)}), C(Enum {HdlNone, HdlSome(Bundle {})})}
+            ; rhs: Enum {A(UInt<1>), B(Enum {HdlNone, HdlSome(SInt<1>)}), C(Enum {HdlNone, HdlSome(Bundle {})})}
             connect o2, i1 @[module-XXXXXXXXXX.rs 9:1]
         else:
             connect o1, i1 @[module-XXXXXXXXXX.rs 10:1]
@@ -3323,6 +3389,9 @@ circuit check_enum_connect_any:
             match i2.tag: @[module-XXXXXXXXXX.rs 8:1]
                 A:
                     wire __connect_variant_body: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
+                    ; connect different types:
+                    ; lhs: UInt<1>
+                    ; rhs: UInt<2>
                     connect __connect_variant_body, bits(i2.body, 1, 0) @[module-XXXXXXXXXX.rs 8:1]
                     wire _bundle_literal_expr: Ty1
                     connect _bundle_literal_expr.tag, {|A, B, C|}(A)
@@ -3360,6 +3429,9 @@ circuit check_enum_connect_any:
                             connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_enum_expr_1
                             connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1)
                             connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
+                            ; connect different types:
+                            ; lhs: SInt<1>
+                            ; rhs: SInt<2>
                             connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
                             wire _bundle_literal_expr_2: Ty4
                             connect _bundle_literal_expr_2.tag, {|HdlNone, HdlSome|}(HdlSome)
@@ -3412,6 +3484,9 @@ circuit check_enum_connect_any:
             match i1.tag: @[module-XXXXXXXXXX.rs 9:1]
                 A:
                     wire __connect_variant_body_4: UInt<2> @[module-XXXXXXXXXX.rs 9:1]
+                    ; connect different types:
+                    ; lhs: UInt<2>
+                    ; rhs: UInt<1>
                     connect __connect_variant_body_4, bits(i1.body, 0, 0) @[module-XXXXXXXXXX.rs 9:1]
                     wire _bundle_literal_expr_5: Ty2
                     connect _bundle_literal_expr_5.tag, {|A, B, C|}(A)
@@ -3449,6 +3524,9 @@ circuit check_enum_connect_any:
                             connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_enum_expr_4
                             connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1)
                             connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body
+                            ; connect different types:
+                            ; lhs: SInt<2>
+                            ; rhs: SInt<1>
                             connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
                             wire _bundle_literal_expr_7: Ty5
                             connect _bundle_literal_expr_7.tag, {|HdlNone, HdlSome|}(HdlSome)
@@ -3524,6 +3602,9 @@ circuit check_enum_connect_any:
         when swap: @[module-XXXXXXXXXX.rs 7:1]
             when eq(i2.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 8:1]
                 wire __connect_variant_body: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
+                ; connect different types:
+                ; lhs: UInt<1>
+                ; rhs: UInt<2>
                 connect __connect_variant_body, bits(i2.body, 1, 0) @[module-XXXXXXXXXX.rs 8:1]
                 wire _bundle_literal_expr: Ty0
                 connect _bundle_literal_expr.tag, UInt<2>(0h0)
@@ -3550,6 +3631,9 @@ circuit check_enum_connect_any:
                     connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_bundle_expr_flattened_1.tag
                     connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1)
                     connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
+                    ; connect different types:
+                    ; lhs: SInt<1>
+                    ; rhs: SInt<2>
                     connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
                     wire _bundle_literal_expr_2: Ty2
                     connect _bundle_literal_expr_2.tag, UInt<1>(0h1)
@@ -3584,6 +3668,9 @@ circuit check_enum_connect_any:
                 connect o1, _bundle_literal_expr_4 @[module-XXXXXXXXXX.rs 8:1]
             when eq(i1.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
                 wire __connect_variant_body_4: UInt<2> @[module-XXXXXXXXXX.rs 9:1]
+                ; connect different types:
+                ; lhs: UInt<2>
+                ; rhs: UInt<1>
                 connect __connect_variant_body_4, bits(i1.body, 0, 0) @[module-XXXXXXXXXX.rs 9:1]
                 wire _bundle_literal_expr_5: Ty1
                 connect _bundle_literal_expr_5.tag, UInt<2>(0h0)
@@ -3610,6 +3697,9 @@ circuit check_enum_connect_any:
                     connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_bundle_expr_flattened_4.tag
                     connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1)
                     connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body
+                    ; connect different types:
+                    ; lhs: SInt<2>
+                    ; rhs: SInt<1>
                     connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
                     wire _bundle_literal_expr_7: Ty3
                     connect _bundle_literal_expr_7.tag, UInt<1>(0h1)
@@ -3667,6 +3757,9 @@ circuit check_enum_connect_any:
         when swap: @[module-XXXXXXXXXX.rs 7:1]
             when eq(bits(i2, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 8:1]
                 wire __connect_variant_body: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
+                ; connect different types:
+                ; lhs: UInt<1>
+                ; rhs: UInt<2>
                 connect __connect_variant_body, bits(bits(i2, 4, 2), 1, 0) @[module-XXXXXXXXXX.rs 8:1]
                 wire _bundle_literal_expr: Ty0
                 connect _bundle_literal_expr.tag, UInt<2>(0h0)
@@ -3691,6 +3784,9 @@ circuit check_enum_connect_any:
                     connect __connect_variant_body_1, _cast_to_bits_expr_1 @[module-XXXXXXXXXX.rs 8:1]
                 else:
                     wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1]
+                    ; connect different types:
+                    ; lhs: SInt<1>
+                    ; rhs: SInt<2>
                     connect __connect_variant_body_2, asSInt(bits(bits(bits(bits(i2, 4, 2), 2, 0), 2, 1), 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
                     wire _bundle_literal_expr_2: Ty1
                     connect _bundle_literal_expr_2.tag, UInt<1>(0h1)
@@ -3724,6 +3820,9 @@ circuit check_enum_connect_any:
                 connect o1, _cast_to_bits_expr_4 @[module-XXXXXXXXXX.rs 8:1]
             when eq(bits(i1, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
                 wire __connect_variant_body_4: UInt<2> @[module-XXXXXXXXXX.rs 9:1]
+                ; connect different types:
+                ; lhs: UInt<2>
+                ; rhs: UInt<1>
                 connect __connect_variant_body_4, bits(bits(i1, 3, 2), 0, 0) @[module-XXXXXXXXXX.rs 9:1]
                 wire _bundle_literal_expr_5: Ty2
                 connect _bundle_literal_expr_5.tag, UInt<2>(0h0)
@@ -3748,6 +3847,9 @@ circuit check_enum_connect_any:
                     connect __connect_variant_body_5, _cast_to_bits_expr_6 @[module-XXXXXXXXXX.rs 9:1]
                 else:
                     wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1]
+                    ; connect different types:
+                    ; lhs: SInt<2>
+                    ; rhs: SInt<1>
                     connect __connect_variant_body_6, asSInt(bits(bits(bits(bits(i1, 3, 2), 1, 0), 1, 1), 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
                     wire _bundle_literal_expr_7: Ty3
                     connect _bundle_literal_expr_7.tag, UInt<1>(0h1)

From 186488a82e7ff45e638b87bcd8c1510043b5cbbf Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 30 Sep 2024 23:31:45 -0700
Subject: [PATCH 028/190] remove FIXME now that simplify_enums is fixed

---
 crates/fayalite/tests/module.rs | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 4dfeca5..9927d69 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -3357,10 +3357,6 @@ circuit check_enum_connect_any:
             connect o2, i2 @[module-XXXXXXXXXX.rs 11:1]
 ",
     };
-    // FIXME: simplify_enums is broken when connecting enums that contain
-    // UInt/SInt where their widths don't match. it should recurse into the
-    // enum bodies so it can properly sign/zero-extend or truncate the
-    // contained UInt/SInt fields.
     let orig_m = m.canonical().intern();
     let m = simplify_enums(orig_m, SimplifyEnumsKind::SimplifyToEnumsWithNoBody).unwrap();
     dbg!(m);

From 9d66fcc54893388cc21543717ad634432eb1db6b Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 1 Oct 2024 00:05:39 -0700
Subject: [PATCH 029/190] improve ExportOptions support in
 `assert_export_firrtl!`

---
 crates/fayalite/src/firrtl.rs | 174 ++++++++++++++++++++++++++++++----
 1 file changed, 155 insertions(+), 19 deletions(-)

diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index 79db858..e1c9c5e 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -2378,15 +2378,17 @@ impl FileBackendTrait for FileBackend {
 }
 
 #[doc(hidden)]
-#[derive(PartialEq, Eq)]
+#[derive(PartialEq, Eq, Clone, Copy)]
 pub struct TestBackendPrivate {
     pub module_var_name: &'static str,
+    pub included_fields: &'static [&'static str],
 }
 
 impl Default for TestBackendPrivate {
     fn default() -> Self {
         Self {
             module_var_name: "m",
+            included_fields: &[],
         }
     }
 }
@@ -2407,7 +2409,11 @@ impl fmt::Debug for TestBackend {
             files,
             error_after,
             options,
-            __private: TestBackendPrivate { module_var_name },
+            __private:
+                TestBackendPrivate {
+                    module_var_name,
+                    included_fields,
+                },
         } = self;
         writeln!(
             f,
@@ -2415,14 +2421,43 @@ impl fmt::Debug for TestBackend {
         )?;
         writeln!(f, "    assert_export_firrtl! {{")?;
         writeln!(f, "        {module_var_name} =>")?;
-        for (file, content) in files {
-            writeln!(f, "        {file:?}: {:?},", DebugAsRawString(content))?;
-        }
-        if *error_after != Option::default() {
+        if *error_after != Option::default() || included_fields.contains(&"error_after") {
             writeln!(f, "        error_after: {error_after:?},")?;
         }
-        if *options != ExportOptions::default() {
-            writeln!(f, "        options: {options:?},")?;
+        if *options != ExportOptions::default() || included_fields.contains(&"options") {
+            struct DebugWithForceIncludeFields<'a> {
+                options: ExportOptions,
+                included_fields: &'a [&'a str],
+            }
+            impl fmt::Debug for DebugWithForceIncludeFields<'_> {
+                fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                    self.options.debug_fmt(f, |field| {
+                        self.included_fields.iter().any(|included_field| {
+                            if let Some(("options", suffix)) = included_field.split_once(".") {
+                                suffix == field
+                            } else {
+                                false
+                            }
+                        })
+                    })
+                }
+            }
+            let options_str = format!(
+                "{:#?}",
+                DebugWithForceIncludeFields {
+                    options: *options,
+                    included_fields
+                }
+            );
+            let mut sep = "        options: ";
+            for line in options_str.lines() {
+                write!(f, "{sep}{line}")?;
+                sep = "\n        ";
+            }
+            writeln!(f, ",")?;
+        }
+        for (file, content) in files {
+            writeln!(f, "        {file:?}: {:?},", DebugAsRawString(content))?;
         }
         write!(f, "    }};")
     }
@@ -2507,6 +2542,7 @@ fn export_impl(
     let ExportOptions {
         simplify_memories: do_simplify_memories,
         simplify_enums: do_simplify_enums,
+        __private: _,
     } = options;
     if let Some(kind) = do_simplify_enums {
         top_module =
@@ -2573,30 +2609,71 @@ impl clap::builder::TypedValueParser for OptionSimplifyEnumsKindValueParser {
     }
 }
 
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+pub struct ExportOptionsPrivate(());
+
 #[derive(clap::Parser, Copy, Clone, PartialEq, Eq, Hash)]
-#[non_exhaustive]
 pub struct ExportOptions {
     #[clap(long = "no-simplify-memories", action = clap::ArgAction::SetFalse)]
     pub simplify_memories: bool,
     #[clap(long, value_parser = OptionSimplifyEnumsKindValueParser, default_value = OptionSimplifyEnumsKindValueParser::NONE_NAME)]
     pub simplify_enums: std::option::Option<SimplifyEnumsKind>,
+    #[doc(hidden)]
+    #[clap(skip = ExportOptionsPrivate(()))]
+    /// `#[non_exhaustive]` except allowing struct update syntax
+    pub __private: ExportOptionsPrivate,
 }
 
 impl fmt::Debug for ExportOptions {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.debug_fmt(f, |_| false)
+    }
+}
+
+impl ExportOptions {
+    fn debug_fmt(
+        &self,
+        f: &mut fmt::Formatter<'_>,
+        force_include_field: impl Fn(&str) -> bool,
+    ) -> fmt::Result {
+        let Self {
+            simplify_memories,
+            simplify_enums,
+            __private: _,
+        } = *self;
         f.write_str("ExportOptions {")?;
-        if f.alternate() {
-            f.write_str("\n")?;
-        }
         let mut sep = if f.alternate() { "\n    " } else { " " };
         let comma_sep = if f.alternate() { ",\n    " } else { ", " };
         let default = ExportOptions::default();
-        if self.simplify_memories != default.simplify_memories {
-            write!(f, "{sep}simplify_memories: {:?}", self.simplify_memories)?;
+        if simplify_memories != default.simplify_memories
+            || force_include_field("simplify_memories")
+        {
+            write!(f, "{sep}simplify_memories: {:?}", simplify_memories)?;
             sep = comma_sep;
         }
-        if self.simplify_enums != default.simplify_enums {
-            write!(f, "{sep}simplify_enums: {:?}", self.simplify_enums)?;
+        if simplify_enums != default.simplify_enums || force_include_field("simplify_enums") {
+            write!(f, "{sep}simplify_enums: ")?;
+            macro_rules! debug_cases {
+                ($($ident:ident $(($($args:tt)*))?,)*) => {
+                    match simplify_enums {
+                        // use more complex stringify to avoid the compiler inserting spaces
+                        $($ident $(($($args)*))? => {
+                            f.write_str(concat!(
+                                stringify!($ident),
+                                $("(",
+                                    $(stringify!($args),)*
+                                ")")?
+                            ))?;
+                        })*
+                    }
+                };
+            }
+            debug_cases! {
+                Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody),
+                Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
+                Some(SimplifyEnumsKind::ReplaceWithUInt),
+                None,
+            }
             sep = comma_sep;
         }
         write!(
@@ -2612,6 +2689,7 @@ impl Default for ExportOptions {
         Self {
             simplify_memories: true,
             simplify_enums: None,
+            __private: ExportOptionsPrivate(()),
         }
     }
 }
@@ -2630,7 +2708,17 @@ pub fn export<T: BundleType, B: FileBackendTrait>(
 #[doc(hidden)]
 #[track_caller]
 pub fn assert_export_firrtl_impl<T: BundleType>(top_module: &Module<T>, expected: TestBackend) {
-    let result = export(TestBackend::default(), top_module, expected.options).unwrap();
+    let result = export(
+        TestBackend {
+            files: BTreeMap::default(),
+            error_after: expected.error_after,
+            options: expected.options,
+            __private: expected.__private,
+        },
+        top_module,
+        expected.options,
+    )
+    .unwrap();
     if result != expected {
         panic!(
             "assert_export_firrtl failed:\nyou can update the expected output by using:\n-------START-------\n{result:?}\n-------END-------"
@@ -2647,21 +2735,69 @@ pub fn make_test_expected_files(v: &[(&str, &str)]) -> BTreeMap<String, String>
 macro_rules! assert_export_firrtl {
     {
         $m:ident =>
-        $($file_name:literal: $file_contents:literal,)*
         $($field:ident: $value:expr,)*
+        @parsed_fields($($field_strings:expr,)*)
+        $($file_name:literal: $file_contents:literal,)*
     } => {
         $crate::firrtl::assert_export_firrtl_impl(
             &$m,
             $crate::firrtl::TestBackend {
+                $($field: $value,)*
                 files: $crate::firrtl::make_test_expected_files(&[
                     $(($file_name, $file_contents),)*
                 ]),
-                $($field: $value,)*
                 __private: $crate::firrtl::TestBackendPrivate {
                     module_var_name: stringify!($m),
+                    included_fields: &[$($field_strings,)*],
                 },
                 ..<$crate::firrtl::TestBackend as $crate::__std::default::Default>::default()
             },
         );
     };
+    {
+        $m:ident =>
+        $($parsed_fields:ident: $parsed_field_values:expr,)*
+        @parsed_fields($($field_strings:expr,)*)
+        options: ExportOptions {
+            $($export_option_fields:ident: $parsed_export_option_field_values:expr,)*
+            ..$export_option_default:expr
+        },
+        $($rest:tt)*
+    } => {
+        $crate::assert_export_firrtl!(
+            $m =>
+            $($parsed_fields: $parsed_field_values,)*
+            options: ExportOptions {
+                $($export_option_fields: $parsed_export_option_field_values,)*
+                ..$export_option_default
+            },
+            @parsed_fields($($field_strings,)* "options", $(concat!("options.", stringify!($export_option_fields)),)*)
+            $($rest)*
+        );
+    };
+    {
+        $m:ident =>
+        $($parsed_fields:ident: $parsed_field_values:expr,)*
+        @parsed_fields($($field_strings:expr,)*)
+        $field:ident: $field_value:expr,
+        $($rest:tt)*
+    } => {
+        $crate::assert_export_firrtl!(
+            $m =>
+            $($parsed_fields: $parsed_field_values,)*
+            $field: $field_value,
+            @parsed_fields($($field_strings,)* stringify!($field),)
+            $($rest)*
+        );
+    };
+    {
+        $m:ident =>
+        $($rest:tt)*
+    } => {
+        $crate::assert_export_firrtl!(
+            $m =>
+            @parsed_fields()
+            $($rest)*
+        );
+    };
 }

From d089095667d767258a17abcd5c0356f341d74696 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 1 Oct 2024 00:07:48 -0700
Subject: [PATCH 030/190] change default to
 --simplify-enums=replace-with-bundle-of-uints

---
 crates/fayalite/src/firrtl.rs   |   4 +-
 crates/fayalite/tests/module.rs | 112 ++++++++++++++++++++++----------
 2 files changed, 80 insertions(+), 36 deletions(-)

diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index e1c9c5e..13f211f 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -2616,7 +2616,7 @@ pub struct ExportOptionsPrivate(());
 pub struct ExportOptions {
     #[clap(long = "no-simplify-memories", action = clap::ArgAction::SetFalse)]
     pub simplify_memories: bool,
-    #[clap(long, value_parser = OptionSimplifyEnumsKindValueParser, default_value = OptionSimplifyEnumsKindValueParser::NONE_NAME)]
+    #[clap(long, value_parser = OptionSimplifyEnumsKindValueParser, default_value = "replace-with-bundle-of-uints")]
     pub simplify_enums: std::option::Option<SimplifyEnumsKind>,
     #[doc(hidden)]
     #[clap(skip = ExportOptionsPrivate(()))]
@@ -2688,7 +2688,7 @@ impl Default for ExportOptions {
     fn default() -> Self {
         Self {
             simplify_memories: true,
-            simplify_enums: None,
+            simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
             __private: ExportOptionsPrivate(()),
         }
     }
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 9927d69..b4998da 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -1,11 +1,8 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use fayalite::{
-    annotations::CustomFirrtlAnnotation,
-    assert_export_firrtl,
-    intern::Intern,
-    module::transform::simplify_enums::{simplify_enums, SimplifyEnumsKind},
-    prelude::*,
+    annotations::CustomFirrtlAnnotation, assert_export_firrtl, firrtl::ExportOptions,
+    intern::Intern, module::transform::simplify_enums::SimplifyEnumsKind, prelude::*,
     ty::StaticType,
 };
 use serde_json::json;
@@ -86,6 +83,10 @@ fn test_mymodule() {
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
         "/test/my_module.fir": r"FIRRTL version 3.2.0
 circuit my_module:
     type Ty0 = {`0`: UInt<32>, `1`: SInt<5>}
@@ -481,6 +482,10 @@ fn test_enum_literals() {
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
         "/test/check_enum_literals.fir": r"FIRRTL version 3.2.0
 circuit check_enum_literals:
     type Ty0 = {|HdlNone, HdlSome: UInt<8>|}
@@ -502,12 +507,13 @@ circuit check_enum_literals:
             connect o2, {|A, B: UInt<8>, C: UInt<1>[3]|}(C, _array_literal_expr) @[module-XXXXXXXXXX.rs 10:1]
 ",
     };
-    let orig_m = m.canonical().intern();
-    let m = simplify_enums(orig_m, SimplifyEnumsKind::SimplifyToEnumsWithNoBody).unwrap();
-    dbg!(m);
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody),
+            ..ExportOptions::default()
+        },
         "/test/check_enum_literals.fir": r"FIRRTL version 3.2.0
 circuit check_enum_literals:
     type Ty0 = {|HdlNone, HdlSome|}
@@ -549,11 +555,13 @@ circuit check_enum_literals:
             connect o2, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 10:1]
 ",
     };
-    let m = simplify_enums(orig_m, SimplifyEnumsKind::ReplaceWithBundleOfUInts).unwrap();
-    dbg!(m);
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
+            ..ExportOptions::default()
+        },
         "/test/check_enum_literals.fir": r"FIRRTL version 3.2.0
 circuit check_enum_literals:
     type Ty0 = {tag: UInt<1>, body: UInt<8>}
@@ -593,11 +601,13 @@ circuit check_enum_literals:
             connect o2, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 10:1]
 ",
     };
-    let m = simplify_enums(orig_m, SimplifyEnumsKind::ReplaceWithUInt).unwrap();
-    dbg!(m);
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: Some(SimplifyEnumsKind::ReplaceWithUInt),
+            ..ExportOptions::default()
+        },
         "/test/check_enum_literals.fir": r"FIRRTL version 3.2.0
 circuit check_enum_literals:
     type Ty0 = {tag: UInt<1>, body: UInt<8>}
@@ -708,6 +718,10 @@ fn test_struct_enum_match() {
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
         "/test/check_struct_enum_match.fir": r"FIRRTL version 3.2.0
 circuit check_struct_enum_match:
     type Ty0 = {|HdlNone, HdlSome: UInt<8>|}
@@ -764,12 +778,13 @@ circuit check_struct_enum_match:
                 connect o[4], _match_arm_value_9[2] @[module-XXXXXXXXXX.rs 24:1]
 ",
     };
-    let orig_m = m.canonical().intern();
-    let m = simplify_enums(orig_m, SimplifyEnumsKind::SimplifyToEnumsWithNoBody).unwrap();
-    dbg!(m);
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody),
+            ..ExportOptions::default()
+        },
         "/test/check_struct_enum_match.fir": r"FIRRTL version 3.2.0
 circuit check_struct_enum_match:
     type Ty0 = {|HdlNone, HdlSome|}
@@ -844,11 +859,13 @@ circuit check_struct_enum_match:
                 connect o[4], _cast_bits_to_array_expr_1[2] @[module-XXXXXXXXXX.rs 24:1]
 ",
     };
-    let m = simplify_enums(orig_m, SimplifyEnumsKind::ReplaceWithBundleOfUInts).unwrap();
-    dbg!(m);
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
+            ..ExportOptions::default()
+        },
         "/test/check_struct_enum_match.fir": r"FIRRTL version 3.2.0
 circuit check_struct_enum_match:
     type Ty0 = {tag: UInt<1>, body: UInt<8>}
@@ -915,11 +932,13 @@ circuit check_struct_enum_match:
             connect o[4], _cast_bits_to_array_expr_1[2] @[module-XXXXXXXXXX.rs 24:1]
 ",
     };
-    let m = simplify_enums(orig_m, SimplifyEnumsKind::ReplaceWithUInt).unwrap();
-    dbg!(m);
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: Some(SimplifyEnumsKind::ReplaceWithUInt),
+            ..ExportOptions::default()
+        },
         "/test/check_struct_enum_match.fir": r"FIRRTL version 3.2.0
 circuit check_struct_enum_match:
     module check_struct_enum_match: @[module-XXXXXXXXXX.rs 1:1]
@@ -2419,6 +2438,10 @@ fn test_memory_of_enum() {
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
         "/test/check_memory_of_enum.fir": r#"FIRRTL version 3.2.0
 circuit check_memory_of_enum: %[[
   {
@@ -2524,12 +2547,13 @@ circuit check_memory_of_enum: %[[
 0000111101
 ",
     };
-    let orig_m = m.canonical().intern();
-    let m = simplify_enums(orig_m, SimplifyEnumsKind::SimplifyToEnumsWithNoBody).unwrap();
-    dbg!(m);
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody),
+            ..ExportOptions::default()
+        },
         "/test/check_memory_of_enum.fir": r#"FIRRTL version 3.2.0
 circuit check_memory_of_enum: %[[
   {
@@ -2671,11 +2695,12 @@ circuit check_memory_of_enum: %[[
 01
 ",
     };
-    let m = simplify_enums(orig_m, SimplifyEnumsKind::ReplaceWithBundleOfUInts).unwrap();
-    dbg!(m);
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            ..ExportOptions::default()
+        },
         "/test/check_memory_of_enum.fir": r#"FIRRTL version 3.2.0
 circuit check_memory_of_enum: %[[
   {
@@ -2801,11 +2826,13 @@ circuit check_memory_of_enum: %[[
 01
 ",
     };
-    let m = simplify_enums(orig_m, SimplifyEnumsKind::ReplaceWithUInt).unwrap();
-    dbg!(m);
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: Some(SimplifyEnumsKind::ReplaceWithUInt),
+            ..ExportOptions::default()
+        },
         "/test/check_memory_of_enum.fir": r#"FIRRTL version 3.2.0
 circuit check_memory_of_enum: %[[
   {
@@ -2906,6 +2933,10 @@ fn test_memory_of_array_of_enum() {
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
         "/test/check_memory_of_array_of_enum.fir": r"FIRRTL version 3.2.0
 circuit check_memory_of_array_of_enum:
     type Ty0 = {|A, B: UInt<8>, C: UInt<1>[3]|}
@@ -3227,6 +3258,10 @@ circuit check_uninit:
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
         "/test/check_uninit_1.fir": r"FIRRTL version 3.2.0
 circuit check_uninit_1:
     type Ty0 = {}
@@ -3329,6 +3364,10 @@ fn test_enum_connect_any() {
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
         "/test/check_enum_connect_any.fir": r"FIRRTL version 3.2.0
 circuit check_enum_connect_any:
     type Ty0 = {|HdlNone, HdlSome: SInt<1>|}
@@ -3357,12 +3396,13 @@ circuit check_enum_connect_any:
             connect o2, i2 @[module-XXXXXXXXXX.rs 11:1]
 ",
     };
-    let orig_m = m.canonical().intern();
-    let m = simplify_enums(orig_m, SimplifyEnumsKind::SimplifyToEnumsWithNoBody).unwrap();
-    dbg!(m);
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody),
+            ..ExportOptions::default()
+        },
         "/test/check_enum_connect_any.fir": r"FIRRTL version 3.2.0
 circuit check_enum_connect_any:
     type Ty0 = {|A, B, C|}
@@ -3577,11 +3617,13 @@ circuit check_enum_connect_any:
             connect o2, i2 @[module-XXXXXXXXXX.rs 11:1]
 ",
     };
-    let m = simplify_enums(orig_m, SimplifyEnumsKind::ReplaceWithBundleOfUInts).unwrap();
-    dbg!(m);
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
+            ..ExportOptions::default()
+        },
         "/test/check_enum_connect_any.fir": r"FIRRTL version 3.2.0
 circuit check_enum_connect_any:
     type Ty0 = {tag: UInt<2>, body: UInt<2>}
@@ -3732,12 +3774,14 @@ circuit check_enum_connect_any:
             connect o1, i1 @[module-XXXXXXXXXX.rs 10:1]
             connect o2, i2 @[module-XXXXXXXXXX.rs 11:1]
 ",
-    }
-    let m = simplify_enums(orig_m, SimplifyEnumsKind::ReplaceWithUInt).unwrap();
-    dbg!(m);
+    };
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
+        options: ExportOptions {
+            simplify_enums: Some(SimplifyEnumsKind::ReplaceWithUInt),
+            ..ExportOptions::default()
+        },
         "/test/check_enum_connect_any.fir": r"FIRRTL version 3.2.0
 circuit check_enum_connect_any:
     type Ty0 = {tag: UInt<2>, body: UInt<2>}

From 6e0b6c000d41a6b68d5b17462e016b6d6959c18c Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 1 Oct 2024 18:30:46 -0700
Subject: [PATCH 031/190] remove stray debugging prints

---
 .../fayalite/src/module/transform/simplify_enums.rs  | 12 ++----------
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/crates/fayalite/src/module/transform/simplify_enums.rs b/crates/fayalite/src/module/transform/simplify_enums.rs
index 3b3677b..edb4b97 100644
--- a/crates/fayalite/src/module/transform/simplify_enums.rs
+++ b/crates/fayalite/src/module/transform/simplify_enums.rs
@@ -483,14 +483,6 @@ impl State {
             );
             return Ok(());
         }
-        println!(
-            r"handle_stmt_connect(
-    unfolded_lhs_ty: {unfolded_lhs_ty:?},
-    unfolded_rhs_ty: {unfolded_rhs_ty:?},
-    folded_lhs: {folded_lhs:?},
-    folded_rhs: {folded_rhs:?},
-)"
-        );
         match unfolded_lhs_ty {
             CanonicalType::Array(unfolded_lhs_ty) => self.handle_stmt_connect_array(
                 unfolded_lhs_ty,
@@ -535,11 +527,11 @@ fn connect_port(
 ) {
     if Expr::ty(lhs) == Expr::ty(rhs) {
         stmts.push(
-            dbg!(StmtConnect {
+            StmtConnect {
                 lhs,
                 rhs,
                 source_location,
-            })
+            }
             .into(),
         );
         return;

From 2a25dd9d7b74f5b6953e3833cec66cdc66954ee7 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 1 Oct 2024 18:31:44 -0700
Subject: [PATCH 032/190] fix annotations getting lost

---
 crates/fayalite/src/module.rs | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index e88b37a..f93758a 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -2272,7 +2272,8 @@ pub fn annotate<T: Type>(target: Expr<T>, annotations: impl IntoAnnotations) {
             .body
             .annotations_map
             .entry(decl)
-            .or_default();
+            .or_default()
+            .extend(annotations);
     });
 }
 

From d0b406d288e0c8fef53ddc1703f1557ce81a250e Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 1 Oct 2024 18:33:32 -0700
Subject: [PATCH 033/190] add more annotation kinds

---
 crates/fayalite/src/annotations.rs            | 25 +++++
 crates/fayalite/src/firrtl.rs                 | 49 +++++++---
 crates/fayalite/src/module/transform/visit.rs |  5 +-
 crates/fayalite/tests/module.rs               | 94 ++++++++++++++++++-
 crates/fayalite/visit_types.json              | 29 ++++++
 5 files changed, 187 insertions(+), 15 deletions(-)

diff --git a/crates/fayalite/src/annotations.rs b/crates/fayalite/src/annotations.rs
index 8e645c3..6b96d01 100644
--- a/crates/fayalite/src/annotations.rs
+++ b/crates/fayalite/src/annotations.rs
@@ -118,10 +118,35 @@ pub struct CustomFirrtlAnnotation {
     pub additional_fields: CustomFirrtlAnnotationFields,
 }
 
+#[derive(Copy, Clone, PartialEq, Eq, Debug, Hash, Serialize, Deserialize)]
+pub struct SVAttributeAnnotation {
+    pub text: Interned<str>,
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Debug, Hash, Serialize, Deserialize)]
+pub struct BlackBoxInlineAnnotation {
+    pub path: Interned<str>,
+    pub text: Interned<str>,
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Debug, Hash, Serialize, Deserialize)]
+pub struct BlackBoxPathAnnotation {
+    pub path: Interned<str>,
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Debug, Hash, Serialize, Deserialize)]
+pub struct DocStringAnnotation {
+    pub text: Interned<str>,
+}
+
 #[derive(Clone, PartialEq, Eq, Hash, Debug)]
 #[non_exhaustive]
 pub enum Annotation {
     DontTouch,
+    SVAttribute(SVAttributeAnnotation),
+    BlackBoxInline(BlackBoxInlineAnnotation),
+    BlackBoxPath(BlackBoxPathAnnotation),
+    DocString(DocStringAnnotation),
     CustomFirrtl(CustomFirrtlAnnotation),
 }
 
diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index 13f211f..0be61b5 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -2,7 +2,10 @@
 // See Notices.txt for copyright information
 #![allow(clippy::type_complexity)]
 use crate::{
-    annotations::CustomFirrtlAnnotation,
+    annotations::{
+        Annotation, BlackBoxInlineAnnotation, BlackBoxPathAnnotation, CustomFirrtlAnnotation,
+        DocStringAnnotation, SVAttributeAnnotation,
+    },
     array::Array,
     bundle::{Bundle, BundleField, BundleType},
     clock::Clock,
@@ -665,6 +668,17 @@ enum AnnotationData {
     },
     #[serde(rename = "firrtl.transforms.DontTouchAnnotation")]
     DontTouch,
+    #[serde(rename = "firrtl.AttributeAnnotation")]
+    AttributeAnnotation { description: Interned<str> },
+    #[serde(rename = "firrtl.transforms.BlackBoxInlineAnno")]
+    BlackBoxInlineAnno {
+        name: Interned<str>,
+        text: Interned<str>,
+    },
+    #[serde(rename = "firrtl.transforms.BlackBoxPathAnno")]
+    BlackBoxPathAnno { path: Interned<str> },
+    #[serde(rename = "firrtl.DocStringAnnotation")]
+    DocStringAnnotation { description: Interned<str> },
     #[allow(dead_code)]
     #[serde(untagged)]
     Other {
@@ -675,7 +689,7 @@ enum AnnotationData {
 }
 
 #[derive(Serialize)]
-struct Annotation {
+struct FirrtlAnnotation {
     #[serde(flatten)]
     data: AnnotationData,
     target: AnnotationTarget,
@@ -690,7 +704,7 @@ struct Exporter<'a> {
     module: ModuleState,
     type_state: TypeState,
     circuit_name: Ident,
-    annotations: Vec<Annotation>,
+    annotations: Vec<FirrtlAnnotation>,
 }
 
 struct PushIndent<'a> {
@@ -1770,7 +1784,7 @@ impl<'a> Exporter<'a> {
             memory_name.0.to_string(),
             contents,
         )?;
-        self.annotations.push(Annotation {
+        self.annotations.push(FirrtlAnnotation {
             data: AnnotationData::MemoryFileInline {
                 filename,
                 hex_or_binary,
@@ -1789,14 +1803,25 @@ impl<'a> Exporter<'a> {
         });
         Ok(())
     }
-    fn annotation(
-        &mut self,
-        path: AnnotationTargetPath,
-        annotation: &crate::annotations::Annotation,
-    ) {
+    fn annotation(&mut self, path: AnnotationTargetPath, annotation: &Annotation) {
         let data = match annotation {
-            crate::annotations::Annotation::DontTouch => AnnotationData::DontTouch,
-            crate::annotations::Annotation::CustomFirrtl(CustomFirrtlAnnotation {
+            Annotation::DontTouch => AnnotationData::DontTouch,
+            Annotation::SVAttribute(SVAttributeAnnotation { text }) => {
+                AnnotationData::AttributeAnnotation { description: *text }
+            }
+            Annotation::BlackBoxInline(BlackBoxInlineAnnotation { path, text }) => {
+                AnnotationData::BlackBoxInlineAnno {
+                    name: *path,
+                    text: *text,
+                }
+            }
+            Annotation::BlackBoxPath(BlackBoxPathAnnotation { path }) => {
+                AnnotationData::BlackBoxPathAnno { path: *path }
+            }
+            Annotation::DocString(DocStringAnnotation { text }) => {
+                AnnotationData::DocStringAnnotation { description: *text }
+            }
+            Annotation::CustomFirrtl(CustomFirrtlAnnotation {
                 class,
                 additional_fields,
             }) => AnnotationData::Other {
@@ -1804,7 +1829,7 @@ impl<'a> Exporter<'a> {
                 additional_fields: (*additional_fields).into(),
             },
         };
-        self.annotations.push(Annotation {
+        self.annotations.push(FirrtlAnnotation {
             data,
             target: AnnotationTarget {
                 circuit: self.circuit_name,
diff --git a/crates/fayalite/src/module/transform/visit.rs b/crates/fayalite/src/module/transform/visit.rs
index 440eecb..77079dd 100644
--- a/crates/fayalite/src/module/transform/visit.rs
+++ b/crates/fayalite/src/module/transform/visit.rs
@@ -2,7 +2,10 @@
 // See Notices.txt for copyright information
 #![allow(clippy::multiple_bound_locations)]
 use crate::{
-    annotations::{Annotation, CustomFirrtlAnnotation, TargetedAnnotation},
+    annotations::{
+        Annotation, BlackBoxInlineAnnotation, BlackBoxPathAnnotation, CustomFirrtlAnnotation,
+        DocStringAnnotation, SVAttributeAnnotation, TargetedAnnotation,
+    },
     array::ArrayType,
     bundle::{Bundle, BundleField, BundleType},
     clock::Clock,
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index b4998da..70b3f56 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -1,8 +1,15 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use fayalite::{
-    annotations::CustomFirrtlAnnotation, assert_export_firrtl, firrtl::ExportOptions,
-    intern::Intern, module::transform::simplify_enums::SimplifyEnumsKind, prelude::*,
+    annotations::{
+        BlackBoxInlineAnnotation, BlackBoxPathAnnotation, CustomFirrtlAnnotation,
+        DocStringAnnotation, SVAttributeAnnotation,
+    },
+    assert_export_firrtl,
+    firrtl::ExportOptions,
+    intern::Intern,
+    module::transform::simplify_enums::SimplifyEnumsKind,
+    prelude::*,
     ty::StaticType,
 };
 use serde_json::json;
@@ -3058,6 +3065,14 @@ pub fn check_annotations() {
         .try_into()
         .unwrap(),
     }));
+    m.annotate_module(Annotation::DocString(DocStringAnnotation {
+        text: r"This module is used as a test that fayalite's firrtl
+backend properly emits annotations.
+
+Testing...
+"
+        .intern(),
+    }));
     #[hdl]
     let raddr: UInt<8> = m.input();
     annotate(raddr, Annotation::DontTouch);
@@ -3139,6 +3154,40 @@ pub fn check_annotations() {
     connect(write_port.clk, clk);
     connect(write_port.data, wdata);
     connect(write_port.mask, wmask);
+    #[hdl_module(extern)]
+    fn black_box1() {
+        m.verilog_name("BlackBox1");
+        m.annotate_module(Annotation::BlackBoxInline(BlackBoxInlineAnnotation {
+            path: "black_box1.v".intern(),
+            text: r"(* blackbox *)
+module BlackBox1();
+endmodule
+"
+            .intern(),
+        }));
+    }
+    #[hdl]
+    let black_box1_instance = instance(black_box1());
+    annotate(black_box1_instance, Annotation::DontTouch);
+    #[hdl_module(extern)]
+    fn black_box2() {
+        m.verilog_name("BlackBox2");
+        m.annotate_module(Annotation::BlackBoxPath(BlackBoxPathAnnotation {
+            path: "black_box2.v".intern(),
+        }));
+    }
+    #[hdl]
+    let black_box2_instance = instance(black_box2());
+    annotate(black_box2_instance, Annotation::DontTouch);
+    #[hdl]
+    let a_wire: (SInt<1>, Bool) = wire();
+    annotate(
+        a_wire.1,
+        Annotation::SVAttribute(SVAttributeAnnotation {
+            text: "custom_sv_attr = \"abc\"".intern(),
+        }),
+    );
+    connect(a_wire, (0_hdl_i1, false));
 }
 
 #[test]
@@ -3156,6 +3205,11 @@ circuit check_annotations: %[[
     "bar": "a nice module!",
     "target": "~check_annotations|check_annotations"
   },
+  {
+    "class": "firrtl.DocStringAnnotation",
+    "description": "This module is used as a test that fayalite's firrtl\nbackend properly emits annotations.\n\nTesting...\n",
+    "target": "~check_annotations|check_annotations"
+  },
   {
     "class": "firrtl.transforms.DontTouchAnnotation",
     "target": "~check_annotations|check_annotations>raddr"
@@ -3196,10 +3250,35 @@ circuit check_annotations: %[[
     "class": "some.annotation.Class",
     "baz": "first mask bit",
     "target": "~check_annotations|check_annotations>mem.w1.data[0]"
+  },
+  {
+    "class": "firrtl.transforms.DontTouchAnnotation",
+    "target": "~check_annotations|check_annotations>black_box1_instance"
+  },
+  {
+    "class": "firrtl.transforms.DontTouchAnnotation",
+    "target": "~check_annotations|check_annotations>black_box2_instance"
+  },
+  {
+    "class": "firrtl.AttributeAnnotation",
+    "description": "custom_sv_attr = \"abc\"",
+    "target": "~check_annotations|check_annotations>a_wire.1"
+  },
+  {
+    "class": "firrtl.transforms.BlackBoxInlineAnno",
+    "name": "black_box1.v",
+    "text": "(* blackbox *)\nmodule BlackBox1();\nendmodule\n",
+    "target": "~check_annotations|black_box1"
+  },
+  {
+    "class": "firrtl.transforms.BlackBoxPathAnno",
+    "path": "black_box2.v",
+    "target": "~check_annotations|black_box2"
   }
 ]]
     type Ty0 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: UInt<4>[2], mask: UInt<1>[2]}
     type Ty1 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: UInt<4>[2]}
+    type Ty2 = {`0`: SInt<1>, `1`: UInt<1>}
     module check_annotations: @[module-XXXXXXXXXX.rs 1:1]
         input raddr: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
         output rdata: UInt<4>[2] @[module-XXXXXXXXXX.rs 3:1]
@@ -3224,6 +3303,17 @@ circuit check_annotations: %[[
         connect `mem`.w1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
         connect `mem`.w1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
         connect `mem`.w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
+        inst black_box1_instance of black_box1 @[module-XXXXXXXXXX.rs 21:1]
+        inst black_box2_instance of black_box2 @[module-XXXXXXXXXX.rs 23:1]
+        wire a_wire: Ty2 @[module-XXXXXXXXXX.rs 24:1]
+        wire _bundle_literal_expr: Ty2
+        connect _bundle_literal_expr.`0`, SInt<1>(0h0)
+        connect _bundle_literal_expr.`1`, UInt<1>(0h0)
+        connect a_wire, _bundle_literal_expr @[module-XXXXXXXXXX.rs 25:1]
+    extmodule black_box1: @[module-XXXXXXXXXX.rs 20:1]
+        defname = BlackBox1
+    extmodule black_box2: @[module-XXXXXXXXXX.rs 22:1]
+        defname = BlackBox2
 "#,
     };
 }
diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json
index f1969eb..7064df2 100644
--- a/crates/fayalite/visit_types.json
+++ b/crates/fayalite/visit_types.json
@@ -1164,9 +1164,38 @@
             "data": {
                 "$kind": "Enum",
                 "DontTouch": null,
+                "SVAttribute": "Visible",
+                "BlackBoxInline": "Visible",
+                "BlackBoxPath": "Visible",
+                "DocString": "Visible",
                 "CustomFirrtl": "Visible"
             }
         },
+        "SVAttributeAnnotation": {
+            "data": {
+                "$kind": "Struct",
+                "text": "Visible"
+            }
+        },
+        "BlackBoxInlineAnnotation": {
+            "data": {
+                "$kind": "Struct",
+                "path": "Visible",
+                "text": "Visible"
+            }
+        },
+        "BlackBoxPathAnnotation": {
+            "data": {
+                "$kind": "Struct",
+                "path": "Visible"
+            }
+        },
+        "DocStringAnnotation": {
+            "data": {
+                "$kind": "Struct",
+                "text": "Visible"
+            }
+        },
         "CustomFirrtlAnnotation": {
             "data": {
                 "$kind": "Opaque"

From e8c393f3bbbd7677864847f054adeefaaf55ea4f Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 1 Oct 2024 18:40:52 -0700
Subject: [PATCH 034/190] sort pub mod items

---
 crates/fayalite/src/lib.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/crates/fayalite/src/lib.rs b/crates/fayalite/src/lib.rs
index 70ce724..9192645 100644
--- a/crates/fayalite/src/lib.rs
+++ b/crates/fayalite/src/lib.rs
@@ -43,12 +43,12 @@ pub mod int;
 pub mod intern;
 pub mod memory;
 pub mod module;
+pub mod prelude;
 pub mod reg;
 pub mod reset;
 pub mod source_location;
+pub mod testing;
 pub mod ty;
 pub mod util;
 //pub mod valueless;
-pub mod prelude;
-pub mod testing;
 pub mod wire;

From f35d88d2bbe5f95ec46773727e5d375b4f90ffff Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 1 Oct 2024 18:41:41 -0700
Subject: [PATCH 035/190] remove unused valueless.rs

---
 crates/fayalite/src/lib.rs       |  2 -
 crates/fayalite/src/valueless.rs | 88 --------------------------------
 2 files changed, 90 deletions(-)
 delete mode 100644 crates/fayalite/src/valueless.rs

diff --git a/crates/fayalite/src/lib.rs b/crates/fayalite/src/lib.rs
index 9192645..6e1ccd3 100644
--- a/crates/fayalite/src/lib.rs
+++ b/crates/fayalite/src/lib.rs
@@ -30,7 +30,6 @@ pub struct __;
 #[cfg(feature = "unstable-doc")]
 pub mod _docs;
 
-// FIXME: finish
 pub mod annotations;
 pub mod array;
 pub mod bundle;
@@ -50,5 +49,4 @@ pub mod source_location;
 pub mod testing;
 pub mod ty;
 pub mod util;
-//pub mod valueless;
 pub mod wire;
diff --git a/crates/fayalite/src/valueless.rs b/crates/fayalite/src/valueless.rs
deleted file mode 100644
index d34905e..0000000
--- a/crates/fayalite/src/valueless.rs
+++ /dev/null
@@ -1,88 +0,0 @@
-// SPDX-License-Identifier: LGPL-3.0-or-later
-// See Notices.txt for copyright information
-use crate::{
-    int::{DynIntType, DynSIntType, DynUIntType, IntTypeTrait, SIntType},
-    ty::{Type, Value},
-};
-use std::ops::RangeBounds;
-
-#[derive(Copy, Clone, Debug, Hash, Eq, PartialEq, Default)]
-pub struct Valueless<T> {
-    pub ty: T,
-}
-
-impl<T: Type> Valueless<T> {
-    pub fn to_canonical(&self) -> Valueless<T::CanonicalType> {
-        Valueless {
-            ty: self.ty.canonical(),
-        }
-    }
-    pub fn from_canonical(v: Valueless<T::CanonicalType>) -> Self {
-        Valueless {
-            ty: T::from_canonical_type(v.ty),
-        }
-    }
-}
-
-mod sealed {
-    pub trait Sealed {}
-}
-
-pub trait ValuelessTr: sealed::Sealed {
-    type Type: Type<Value = Self::Value>;
-    type Value: Value<Type = Self::Type>;
-}
-
-impl<T> sealed::Sealed for Valueless<T> {}
-
-impl<T: Type> ValuelessTr for Valueless<T> {
-    type Type = T;
-    type Value = T::Value;
-}
-
-impl<T: IntTypeTrait> Valueless<T> {
-    pub fn signum(&self) -> Valueless<SIntType<2>> {
-        Valueless::default()
-    }
-    pub fn as_same_width_uint(self) -> Valueless<T::SameWidthUInt> {
-        Valueless {
-            ty: self.ty.as_same_width_uint(),
-        }
-    }
-    pub fn as_same_width_sint(self) -> Valueless<T::SameWidthSInt> {
-        Valueless {
-            ty: self.ty.as_same_width_sint(),
-        }
-    }
-    pub fn as_same_value_uint(self) -> Valueless<DynUIntType> {
-        Valueless {
-            ty: self.ty.as_same_value_uint(),
-        }
-    }
-    pub fn as_same_value_sint(self) -> Valueless<DynSIntType> {
-        Valueless {
-            ty: self.ty.as_same_value_sint(),
-        }
-    }
-    pub fn concat<HighType: IntTypeTrait>(
-        &self,
-        high_part: Valueless<HighType>,
-    ) -> Valueless<DynIntType<HighType::Signed>> {
-        let ty = DynIntType::new(
-            self.ty
-                .width()
-                .checked_add(high_part.ty.width())
-                .expect("result has too many bits"),
-        );
-        Valueless { ty }
-    }
-    pub fn repeat(&self, count: usize) -> Valueless<DynIntType<T::Signed>> {
-        let width = self.ty.width();
-        let ty = DynIntType::new(width.checked_mul(count).expect("result has too many bits"));
-        Valueless { ty }
-    }
-    pub fn slice<I: RangeBounds<usize>>(&self, index: I) -> Valueless<DynUIntType> {
-        let ty = self.ty.slice(index);
-        Valueless { ty }
-    }
-}

From f3d6528f5b1e23cb3e9a1ef338c477738c7d7b08 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 1 Oct 2024 19:54:17 -0700
Subject: [PATCH 036/190] make annotations easier to use

---
 crates/fayalite/src/annotations.rs            | 138 ++++++++++++++++--
 crates/fayalite/src/firrtl.rs                 |   4 +-
 crates/fayalite/src/module/transform/visit.rs |   2 +-
 crates/fayalite/src/prelude.rs                |   5 +-
 crates/fayalite/tests/module.rs               |  58 ++++----
 crates/fayalite/visit_types.json              |   7 +-
 6 files changed, 163 insertions(+), 51 deletions(-)

diff --git a/crates/fayalite/src/annotations.rs b/crates/fayalite/src/annotations.rs
index 6b96d01..8eff4a0 100644
--- a/crates/fayalite/src/annotations.rs
+++ b/crates/fayalite/src/annotations.rs
@@ -8,6 +8,7 @@ use serde::{Deserialize, Serialize};
 use std::{
     fmt,
     hash::{Hash, Hasher},
+    iter::FusedIterator,
     ops::Deref,
 };
 
@@ -118,6 +119,9 @@ pub struct CustomFirrtlAnnotation {
     pub additional_fields: CustomFirrtlAnnotationFields,
 }
 
+#[derive(Copy, Clone, PartialEq, Eq, Debug, Hash, Serialize, Deserialize)]
+pub struct DontTouchAnnotation;
+
 #[derive(Copy, Clone, PartialEq, Eq, Debug, Hash, Serialize, Deserialize)]
 pub struct SVAttributeAnnotation {
     pub text: Interned<str>,
@@ -139,15 +143,63 @@ pub struct DocStringAnnotation {
     pub text: Interned<str>,
 }
 
-#[derive(Clone, PartialEq, Eq, Hash, Debug)]
-#[non_exhaustive]
-pub enum Annotation {
-    DontTouch,
-    SVAttribute(SVAttributeAnnotation),
-    BlackBoxInline(BlackBoxInlineAnnotation),
-    BlackBoxPath(BlackBoxPathAnnotation),
-    DocString(DocStringAnnotation),
-    CustomFirrtl(CustomFirrtlAnnotation),
+macro_rules! make_annotation_enum {
+    (
+        $(#[$meta:meta])*
+        $vis:vis enum $Annotation:ident {
+            $($Variant:ident($T:ident),)*
+        }
+    ) => {
+        $(#[$meta])*
+        $vis enum $Annotation {
+            $($Variant($T),)*
+        }
+
+        $(impl IntoAnnotations for $T {
+            type IntoAnnotations = [$Annotation; 1];
+
+            fn into_annotations(self) -> Self::IntoAnnotations {
+                [$Annotation::$Variant(self)]
+            }
+        }
+
+        impl IntoAnnotations for &'_ $T {
+            type IntoAnnotations = [$Annotation; 1];
+
+            fn into_annotations(self) -> Self::IntoAnnotations {
+                [$Annotation::$Variant(*self)]
+            }
+        }
+
+        impl IntoAnnotations for &'_ mut $T {
+            type IntoAnnotations = [$Annotation; 1];
+
+            fn into_annotations(self) -> Self::IntoAnnotations {
+                [$Annotation::$Variant(*self)]
+            }
+        }
+
+        impl IntoAnnotations for Box<$T> {
+            type IntoAnnotations = [$Annotation; 1];
+
+            fn into_annotations(self) -> Self::IntoAnnotations {
+                [$Annotation::$Variant(*self)]
+            }
+        })*
+    };
+}
+
+make_annotation_enum! {
+    #[derive(Clone, PartialEq, Eq, Hash, Debug)]
+    #[non_exhaustive]
+    pub enum Annotation {
+        DontTouch(DontTouchAnnotation),
+        SVAttribute(SVAttributeAnnotation),
+        BlackBoxInline(BlackBoxInlineAnnotation),
+        BlackBoxPath(BlackBoxPathAnnotation),
+        DocString(DocStringAnnotation),
+        CustomFirrtl(CustomFirrtlAnnotation),
+    }
 }
 
 #[derive(Clone, PartialEq, Eq, Hash, Debug)]
@@ -212,10 +264,70 @@ impl IntoAnnotations for &'_ mut Annotation {
     }
 }
 
-impl<T: IntoIterator<Item = Annotation>> IntoAnnotations for T {
-    type IntoAnnotations = Self;
+pub struct IterIntoAnnotations<T: Iterator<Item: IntoAnnotations>> {
+    outer: T,
+    inner: Option<<<T::Item as IntoAnnotations>::IntoAnnotations as IntoIterator>::IntoIter>,
+}
 
-    fn into_annotations(self) -> Self::IntoAnnotations {
-        self
+impl<T: Iterator<Item: IntoAnnotations>> Iterator for IterIntoAnnotations<T> {
+    type Item = Annotation;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        loop {
+            if let Some(inner) = &mut self.inner {
+                let Some(retval) = inner.next() else {
+                    self.inner = None;
+                    continue;
+                };
+                return Some(retval);
+            } else {
+                self.inner = Some(self.outer.next()?.into_annotations().into_iter());
+            }
+        }
+    }
+
+    fn size_hint(&self) -> (usize, Option<usize>) {
+        if let (0, Some(0)) = self.outer.size_hint() {
+            self.inner
+                .as_ref()
+                .map(|v| v.size_hint())
+                .unwrap_or((0, Some(0)))
+        } else {
+            (
+                self.inner.as_ref().map(|v| v.size_hint().0).unwrap_or(0),
+                None,
+            )
+        }
+    }
+
+    fn fold<B, F>(self, init: B, f: F) -> B
+    where
+        Self: Sized,
+        F: FnMut(B, Self::Item) -> B,
+    {
+        self.inner
+            .into_iter()
+            .chain(self.outer.map(|v| v.into_annotations().into_iter()))
+            .flatten()
+            .fold(init, f)
+    }
+}
+
+impl<
+        T: FusedIterator<
+            Item: IntoAnnotations<IntoAnnotations: IntoIterator<IntoIter: FusedIterator>>,
+        >,
+    > FusedIterator for IterIntoAnnotations<T>
+{
+}
+
+impl<T: IntoIterator<Item: IntoAnnotations>> IntoAnnotations for T {
+    type IntoAnnotations = IterIntoAnnotations<T::IntoIter>;
+
+    fn into_annotations(self) -> Self::IntoAnnotations {
+        IterIntoAnnotations {
+            outer: self.into_iter(),
+            inner: None,
+        }
     }
 }
diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index 0be61b5..5a2cc00 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -4,7 +4,7 @@
 use crate::{
     annotations::{
         Annotation, BlackBoxInlineAnnotation, BlackBoxPathAnnotation, CustomFirrtlAnnotation,
-        DocStringAnnotation, SVAttributeAnnotation,
+        DocStringAnnotation, DontTouchAnnotation, SVAttributeAnnotation,
     },
     array::Array,
     bundle::{Bundle, BundleField, BundleType},
@@ -1805,7 +1805,7 @@ impl<'a> Exporter<'a> {
     }
     fn annotation(&mut self, path: AnnotationTargetPath, annotation: &Annotation) {
         let data = match annotation {
-            Annotation::DontTouch => AnnotationData::DontTouch,
+            Annotation::DontTouch(DontTouchAnnotation {}) => AnnotationData::DontTouch,
             Annotation::SVAttribute(SVAttributeAnnotation { text }) => {
                 AnnotationData::AttributeAnnotation { description: *text }
             }
diff --git a/crates/fayalite/src/module/transform/visit.rs b/crates/fayalite/src/module/transform/visit.rs
index 77079dd..1165a46 100644
--- a/crates/fayalite/src/module/transform/visit.rs
+++ b/crates/fayalite/src/module/transform/visit.rs
@@ -4,7 +4,7 @@
 use crate::{
     annotations::{
         Annotation, BlackBoxInlineAnnotation, BlackBoxPathAnnotation, CustomFirrtlAnnotation,
-        DocStringAnnotation, SVAttributeAnnotation, TargetedAnnotation,
+        DocStringAnnotation, DontTouchAnnotation, SVAttributeAnnotation, TargetedAnnotation,
     },
     array::ArrayType,
     bundle::{Bundle, BundleField, BundleType},
diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs
index 16dccb9..c793775 100644
--- a/crates/fayalite/src/prelude.rs
+++ b/crates/fayalite/src/prelude.rs
@@ -1,7 +1,10 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 pub use crate::{
-    annotations::Annotation,
+    annotations::{
+        BlackBoxInlineAnnotation, BlackBoxPathAnnotation, CustomFirrtlAnnotation,
+        DocStringAnnotation, DontTouchAnnotation, SVAttributeAnnotation,
+    },
     array::{Array, ArrayType},
     cli::Cli,
     clock::{Clock, ClockDomain, ToClock},
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 70b3f56..856cbf0 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -1,16 +1,8 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use fayalite::{
-    annotations::{
-        BlackBoxInlineAnnotation, BlackBoxPathAnnotation, CustomFirrtlAnnotation,
-        DocStringAnnotation, SVAttributeAnnotation,
-    },
-    assert_export_firrtl,
-    firrtl::ExportOptions,
-    intern::Intern,
-    module::transform::simplify_enums::SimplifyEnumsKind,
-    prelude::*,
-    ty::StaticType,
+    assert_export_firrtl, firrtl::ExportOptions, intern::Intern,
+    module::transform::simplify_enums::SimplifyEnumsKind, prelude::*, ty::StaticType,
 };
 use serde_json::json;
 
@@ -3057,30 +3049,30 @@ circuit check_memory_of_array_of_enum:
 
 #[hdl_module(outline_generated)]
 pub fn check_annotations() {
-    m.annotate_module(Annotation::CustomFirrtl(CustomFirrtlAnnotation {
+    m.annotate_module(CustomFirrtlAnnotation {
         class: "the.annotation.Example".intern(),
         additional_fields: json!({
             "bar": "a nice module!",
         })
         .try_into()
         .unwrap(),
-    }));
-    m.annotate_module(Annotation::DocString(DocStringAnnotation {
+    });
+    m.annotate_module(DocStringAnnotation {
         text: r"This module is used as a test that fayalite's firrtl
 backend properly emits annotations.
 
 Testing...
 "
         .intern(),
-    }));
+    });
     #[hdl]
     let raddr: UInt<8> = m.input();
-    annotate(raddr, Annotation::DontTouch);
+    annotate(raddr, DontTouchAnnotation);
     #[hdl]
     let rdata: Array<UInt<4>, 2> = m.output();
     annotate(
         rdata,
-        Annotation::CustomFirrtl(CustomFirrtlAnnotation {
+        CustomFirrtlAnnotation {
             class: "the.annotation.ExampleClass".intern(),
             additional_fields: json!({
                 "foo": "bar",
@@ -3088,7 +3080,7 @@ Testing...
             })
             .try_into()
             .unwrap(),
-        }),
+        },
     );
     #[hdl]
     let waddr: UInt<8> = m.input();
@@ -3098,21 +3090,21 @@ Testing...
     let wmask: Array<Bool, 2> = m.input();
     annotate(
         wmask[1],
-        Annotation::CustomFirrtl(CustomFirrtlAnnotation {
+        CustomFirrtlAnnotation {
             class: "some.annotation.Class".intern(),
             additional_fields: json!({
                 "baz": "second mask bit",
             })
             .try_into()
             .unwrap(),
-        }),
+        },
     );
     #[hdl]
     let clk: Clock = m.input();
     #[hdl]
     let mut mem = memory();
     mem.depth(0x100);
-    mem.annotate(Annotation::CustomFirrtl(CustomFirrtlAnnotation {
+    mem.annotate(CustomFirrtlAnnotation {
         class: "the.annotation.ExampleClass2".intern(),
         additional_fields: json!({
             "bar": "foo",
@@ -3120,18 +3112,18 @@ Testing...
         })
         .try_into()
         .unwrap(),
-    }));
+    });
     let read_port = mem.new_read_port();
     annotate(
         read_port,
-        Annotation::CustomFirrtl(CustomFirrtlAnnotation {
+        CustomFirrtlAnnotation {
             class: "the.annotation.ExampleClass3".intern(),
             additional_fields: json!({
                 "foo": "my read port",
             })
             .try_into()
             .unwrap(),
-        }),
+        },
     );
     connect_any(read_port.addr, raddr);
     connect(read_port.en, true);
@@ -3140,14 +3132,14 @@ Testing...
     let write_port = mem.new_write_port();
     annotate(
         write_port.data[0],
-        Annotation::CustomFirrtl(CustomFirrtlAnnotation {
+        CustomFirrtlAnnotation {
             class: "some.annotation.Class".intern(),
             additional_fields: json!({
                 "baz": "first mask bit",
             })
             .try_into()
             .unwrap(),
-        }),
+        },
     );
     connect_any(write_port.addr, waddr);
     connect(write_port.en, true);
@@ -3157,35 +3149,35 @@ Testing...
     #[hdl_module(extern)]
     fn black_box1() {
         m.verilog_name("BlackBox1");
-        m.annotate_module(Annotation::BlackBoxInline(BlackBoxInlineAnnotation {
+        m.annotate_module(BlackBoxInlineAnnotation {
             path: "black_box1.v".intern(),
             text: r"(* blackbox *)
 module BlackBox1();
 endmodule
 "
             .intern(),
-        }));
+        });
     }
     #[hdl]
     let black_box1_instance = instance(black_box1());
-    annotate(black_box1_instance, Annotation::DontTouch);
+    annotate(black_box1_instance, DontTouchAnnotation);
     #[hdl_module(extern)]
     fn black_box2() {
         m.verilog_name("BlackBox2");
-        m.annotate_module(Annotation::BlackBoxPath(BlackBoxPathAnnotation {
+        m.annotate_module(BlackBoxPathAnnotation {
             path: "black_box2.v".intern(),
-        }));
+        });
     }
     #[hdl]
     let black_box2_instance = instance(black_box2());
-    annotate(black_box2_instance, Annotation::DontTouch);
+    annotate(black_box2_instance, DontTouchAnnotation);
     #[hdl]
     let a_wire: (SInt<1>, Bool) = wire();
     annotate(
         a_wire.1,
-        Annotation::SVAttribute(SVAttributeAnnotation {
+        SVAttributeAnnotation {
             text: "custom_sv_attr = \"abc\"".intern(),
-        }),
+        },
     );
     connect(a_wire, (0_hdl_i1, false));
 }
diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json
index 7064df2..09ae23f 100644
--- a/crates/fayalite/visit_types.json
+++ b/crates/fayalite/visit_types.json
@@ -1163,7 +1163,7 @@
         "Annotation": {
             "data": {
                 "$kind": "Enum",
-                "DontTouch": null,
+                "DontTouch": "Visible",
                 "SVAttribute": "Visible",
                 "BlackBoxInline": "Visible",
                 "BlackBoxPath": "Visible",
@@ -1171,6 +1171,11 @@
                 "CustomFirrtl": "Visible"
             }
         },
+        "DontTouchAnnotation": {
+            "data": {
+                "$kind": "Struct"
+            }
+        },
         "SVAttributeAnnotation": {
             "data": {
                 "$kind": "Struct",

From 0cf01600b3b3883929ffb1edae914fa216c9c434 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 1 Oct 2024 19:56:17 -0700
Subject: [PATCH 037/190] add mod formal and move assert/assume/cover stuff to
 it

---
 crates/fayalite/src/firrtl.rs                 |  11 +-
 crates/fayalite/src/formal.rs                 | 186 ++++++++++++++++++
 crates/fayalite/src/lib.rs                    |   1 +
 crates/fayalite/src/module.rs                 | 146 ++------------
 crates/fayalite/src/module/transform/visit.rs |   5 +-
 crates/fayalite/src/prelude.rs                |   9 +-
 crates/fayalite/visit_types.json              |   2 +-
 7 files changed, 218 insertions(+), 142 deletions(-)
 create mode 100644 crates/fayalite/src/formal.rs

diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index 5a2cc00..ef955ea 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -17,6 +17,7 @@ use crate::{
         },
         Expr, ExprEnum,
     },
+    formal::FormalKind,
     int::{Bool, DynSize, IntType, SIntValue, UInt, UIntValue},
     intern::{Intern, Interned},
     memory::{Mem, PortKind, PortName, ReadUnderWrite},
@@ -27,8 +28,8 @@ use crate::{
         },
         AnnotatedModuleIO, Block, ExternModuleBody, ExternModuleParameter,
         ExternModuleParameterValue, Module, ModuleBody, NameId, NormalModuleBody, Stmt,
-        StmtConnect, StmtDeclaration, StmtFormal, StmtFormalKind, StmtIf, StmtInstance, StmtMatch,
-        StmtReg, StmtWire,
+        StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg,
+        StmtWire,
     },
     reset::{AsyncReset, Reset, SyncReset},
     source_location::SourceLocation,
@@ -2011,9 +2012,9 @@ impl<'a> Exporter<'a> {
                     let pred = self.expr(Expr::canonical(pred), &definitions, false);
                     let en = self.expr(Expr::canonical(en), &definitions, false);
                     let kind = match kind {
-                        StmtFormalKind::Assert => "assert",
-                        StmtFormalKind::Assume => "assume",
-                        StmtFormalKind::Cover => "cover",
+                        FormalKind::Assert => "assert",
+                        FormalKind::Assume => "assume",
+                        FormalKind::Cover => "cover",
                     };
                     let text = EscapedString {
                         value: &text,
diff --git a/crates/fayalite/src/formal.rs b/crates/fayalite/src/formal.rs
new file mode 100644
index 0000000..5e90b59
--- /dev/null
+++ b/crates/fayalite/src/formal.rs
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+use crate::{intern::Intern, prelude::*};
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
+pub enum FormalKind {
+    Assert,
+    Assume,
+    Cover,
+}
+
+impl FormalKind {
+    pub fn as_str(self) -> &'static str {
+        match self {
+            Self::Assert => "assert",
+            Self::Assume => "assume",
+            Self::Cover => "cover",
+        }
+    }
+}
+
+#[track_caller]
+pub fn formal_stmt_with_enable_and_loc(
+    kind: FormalKind,
+    clk: Expr<Clock>,
+    pred: Expr<Bool>,
+    en: Expr<Bool>,
+    text: &str,
+    source_location: SourceLocation,
+) {
+    crate::module::add_stmt_formal(crate::module::StmtFormal {
+        kind,
+        clk,
+        pred,
+        en,
+        text: text.intern(),
+        source_location,
+    });
+}
+
+#[track_caller]
+pub fn formal_stmt_with_enable(
+    kind: FormalKind,
+    clk: Expr<Clock>,
+    pred: Expr<Bool>,
+    en: Expr<Bool>,
+    text: &str,
+) {
+    formal_stmt_with_enable_and_loc(kind, clk, pred, en, text, SourceLocation::caller());
+}
+
+#[track_caller]
+pub fn formal_stmt_with_loc(
+    kind: FormalKind,
+    clk: Expr<Clock>,
+    pred: Expr<Bool>,
+    text: &str,
+    source_location: SourceLocation,
+) {
+    formal_stmt_with_enable_and_loc(kind, clk, pred, true.to_expr(), text, source_location);
+}
+
+#[track_caller]
+pub fn formal_stmt(kind: FormalKind, clk: Expr<Clock>, pred: Expr<Bool>, text: &str) {
+    formal_stmt_with_loc(kind, clk, pred, text, SourceLocation::caller());
+}
+
+macro_rules! make_formal {
+    ($kind:ident, $formal_stmt_with_enable_and_loc:ident, $formal_stmt_with_enable:ident, $formal_stmt_with_loc:ident, $formal_stmt:ident) => {
+        #[track_caller]
+        pub fn $formal_stmt_with_enable_and_loc(
+            clk: Expr<Clock>,
+            pred: Expr<Bool>,
+            en: Expr<Bool>,
+            text: &str,
+            source_location: SourceLocation,
+        ) {
+            formal_stmt_with_enable_and_loc(
+                FormalKind::$kind,
+                clk,
+                pred,
+                en,
+                text,
+                source_location,
+            );
+        }
+        #[track_caller]
+        pub fn $formal_stmt_with_enable(
+            clk: Expr<Clock>,
+            pred: Expr<Bool>,
+            en: Expr<Bool>,
+            text: &str,
+        ) {
+            formal_stmt_with_enable(FormalKind::$kind, clk, pred, en, text);
+        }
+        #[track_caller]
+        pub fn $formal_stmt_with_loc(
+            clk: Expr<Clock>,
+            pred: Expr<Bool>,
+            text: &str,
+            source_location: SourceLocation,
+        ) {
+            formal_stmt_with_loc(FormalKind::$kind, clk, pred, text, source_location);
+        }
+        #[track_caller]
+        pub fn $formal_stmt(clk: Expr<Clock>, pred: Expr<Bool>, text: &str) {
+            formal_stmt(FormalKind::$kind, clk, pred, text);
+        }
+    };
+}
+
+make_formal!(
+    Assert,
+    hdl_assert_with_enable_and_loc,
+    hdl_assert_with_enable,
+    hdl_assert_with_loc,
+    hdl_assert
+);
+
+make_formal!(
+    Assume,
+    hdl_assume_with_enable_and_loc,
+    hdl_assume_with_enable,
+    hdl_assume_with_loc,
+    hdl_assume
+);
+
+make_formal!(
+    Cover,
+    hdl_cover_with_enable_and_loc,
+    hdl_cover_with_enable,
+    hdl_cover_with_loc,
+    hdl_cover
+);
+
+pub trait MakeFormalExpr: Type {}
+
+impl<T: Type> MakeFormalExpr for T {}
+
+#[hdl]
+pub fn formal_global_clock() -> Expr<Clock> {
+    #[hdl_module(extern)]
+    fn formal_global_clock() {
+        #[hdl]
+        let clk: Clock = m.output();
+        m.annotate_module(BlackBoxInlineAnnotation {
+            path: "fayalite_formal_global_clock.v".intern(),
+            text: r"module __fayalite_formal_global_clock(output clk);
+    (* gclk *)
+    reg clk;
+endmodule
+"
+            .intern(),
+        });
+        m.verilog_name("__fayalite_formal_global_clock");
+    }
+    #[hdl]
+    let formal_global_clock = instance(formal_global_clock());
+    formal_global_clock.clk
+}
+
+#[hdl]
+pub fn formal_reset() -> Expr<AsyncReset> {
+    #[hdl_module(extern)]
+    fn formal_reset() {
+        #[hdl]
+        let rst: AsyncReset = m.output();
+        m.annotate_module(BlackBoxInlineAnnotation {
+            path: "fayalite_formal_reset.v".intern(),
+            text: r"module __fayalite_formal_reset(output rst);
+    reg rst;
+    (* gclk *)
+    reg gclk;
+    initial rst = 1;
+    always @(posedge gclk)
+        rst <= 0;
+endmodule
+"
+            .intern(),
+        });
+        m.verilog_name("__fayalite_formal_reset");
+    }
+    #[hdl]
+    let formal_reset = instance(formal_reset());
+    formal_reset.rst
+}
diff --git a/crates/fayalite/src/lib.rs b/crates/fayalite/src/lib.rs
index 6e1ccd3..eedb1bb 100644
--- a/crates/fayalite/src/lib.rs
+++ b/crates/fayalite/src/lib.rs
@@ -38,6 +38,7 @@ pub mod clock;
 pub mod enum_;
 pub mod expr;
 pub mod firrtl;
+pub mod formal;
 pub mod int;
 pub mod intern;
 pub mod memory;
diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index f93758a..872c75f 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -15,6 +15,7 @@ use crate::{
         },
         Expr, Flow, ToExpr,
     },
+    formal::FormalKind,
     int::{Bool, DynSize, Size},
     intern::{Intern, Interned},
     memory::{Mem, MemBuilder, MemBuilderTarget, PortName},
@@ -233,26 +234,9 @@ impl fmt::Debug for StmtConnect {
     }
 }
 
-#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
-pub enum StmtFormalKind {
-    Assert,
-    Assume,
-    Cover,
-}
-
-impl StmtFormalKind {
-    pub fn as_str(self) -> &'static str {
-        match self {
-            Self::Assert => "assert",
-            Self::Assume => "assume",
-            Self::Cover => "cover",
-        }
-    }
-}
-
 #[derive(Clone, PartialEq, Eq, Hash)]
 pub struct StmtFormal {
-    pub kind: StmtFormalKind,
+    pub kind: FormalKind,
     pub clk: Expr<Clock>,
     pub pred: Expr<Bool>,
     pub en: Expr<Bool>,
@@ -279,6 +263,19 @@ impl fmt::Debug for StmtFormal {
     }
 }
 
+#[track_caller]
+pub(crate) fn add_stmt_formal(formal: StmtFormal) {
+    ModuleBuilder::with(|m| {
+        m.impl_
+            .borrow_mut()
+            .body
+            .builder_normal_body()
+            .block(m.block_stack.top())
+            .stmts
+            .push(formal.into());
+    });
+}
+
 #[derive(Clone, PartialEq, Eq, Hash)]
 pub struct StmtIf<S: ModuleBuildingStatus = ModuleBuilt> {
     pub cond: Expr<Bool>,
@@ -2439,119 +2436,6 @@ pub fn match_with_loc<T: Type>(
     T::match_variants(expr.to_expr(), source_location)
 }
 
-#[track_caller]
-pub fn formal_with_enable_and_loc(
-    kind: StmtFormalKind,
-    clk: Expr<Clock>,
-    pred: Expr<Bool>,
-    en: Expr<Bool>,
-    text: &str,
-    source_location: SourceLocation,
-) {
-    ModuleBuilder::with(|m| {
-        m.impl_
-            .borrow_mut()
-            .body
-            .builder_normal_body()
-            .block(m.block_stack.top())
-            .stmts
-            .push(
-                StmtFormal {
-                    kind,
-                    clk,
-                    pred,
-                    en,
-                    text: text.intern(),
-                    source_location,
-                }
-                .into(),
-            );
-    });
-}
-
-#[track_caller]
-pub fn formal_with_enable(
-    kind: StmtFormalKind,
-    clk: Expr<Clock>,
-    pred: Expr<Bool>,
-    en: Expr<Bool>,
-    text: &str,
-) {
-    formal_with_enable_and_loc(kind, clk, pred, en, text, SourceLocation::caller());
-}
-
-#[track_caller]
-pub fn formal_with_loc(
-    kind: StmtFormalKind,
-    clk: Expr<Clock>,
-    pred: Expr<Bool>,
-    text: &str,
-    source_location: SourceLocation,
-) {
-    formal_with_enable_and_loc(kind, clk, pred, true.to_expr(), text, source_location);
-}
-
-#[track_caller]
-pub fn formal(kind: StmtFormalKind, clk: Expr<Clock>, pred: Expr<Bool>, text: &str) {
-    formal_with_loc(kind, clk, pred, text, SourceLocation::caller());
-}
-
-macro_rules! make_formal {
-    ($kind:ident, $formal_with_enable_and_loc:ident, $formal_with_enable:ident, $formal_with_loc:ident, $formal:ident) => {
-        #[track_caller]
-        pub fn $formal_with_enable_and_loc(
-            clk: Expr<Clock>,
-            pred: Expr<Bool>,
-            en: Expr<Bool>,
-            text: &str,
-            source_location: SourceLocation,
-        ) {
-            formal_with_enable_and_loc(StmtFormalKind::$kind, clk, pred, en, text, source_location);
-        }
-        #[track_caller]
-        pub fn $formal_with_enable(clk: Expr<Clock>, pred: Expr<Bool>, en: Expr<Bool>, text: &str) {
-            formal_with_enable(StmtFormalKind::$kind, clk, pred, en, text);
-        }
-        #[track_caller]
-        pub fn $formal_with_loc(
-            clk: Expr<Clock>,
-            pred: Expr<Bool>,
-            text: &str,
-            source_location: SourceLocation,
-        ) {
-            formal_with_loc(StmtFormalKind::$kind, clk, pred, text, source_location);
-        }
-        #[track_caller]
-        pub fn $formal(clk: Expr<Clock>, pred: Expr<Bool>, text: &str) {
-            formal(StmtFormalKind::$kind, clk, pred, text);
-        }
-    };
-}
-
-make_formal!(
-    Assert,
-    hdl_assert_with_enable_and_loc,
-    hdl_assert_with_enable,
-    hdl_assert_with_loc,
-    hdl_assert
-);
-
-make_formal!(
-    Assume,
-    hdl_assume_with_enable_and_loc,
-    hdl_assume_with_enable,
-    hdl_assume_with_loc,
-    hdl_assume
-);
-
-make_formal!(
-    Cover,
-    hdl_cover_with_enable_and_loc,
-    hdl_cover_with_enable,
-    hdl_cover_with_loc,
-    hdl_cover
-);
-
 #[track_caller]
 pub fn connect_any_with_loc<Lhs: ToExpr, Rhs: ToExpr>(
     lhs: Lhs,
diff --git a/crates/fayalite/src/module/transform/visit.rs b/crates/fayalite/src/module/transform/visit.rs
index 1165a46..2e1e48f 100644
--- a/crates/fayalite/src/module/transform/visit.rs
+++ b/crates/fayalite/src/module/transform/visit.rs
@@ -18,14 +18,15 @@ use crate::{
         },
         Expr, ExprEnum,
     },
+    formal::FormalKind,
     int::{Bool, SIntType, SIntValue, Size, UIntType, UIntValue},
     intern::{Intern, Interned},
     memory::{Mem, MemPort, PortKind, PortName, PortType, ReadUnderWrite},
     module::{
         AnnotatedModuleIO, Block, BlockId, ExternModuleBody, ExternModuleParameter,
         ExternModuleParameterValue, Instance, Module, ModuleBody, ModuleIO, NameId,
-        NormalModuleBody, ScopedNameId, Stmt, StmtConnect, StmtDeclaration, StmtFormal,
-        StmtFormalKind, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire,
+        NormalModuleBody, ScopedNameId, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtIf,
+        StmtInstance, StmtMatch, StmtReg, StmtWire,
     },
     reg::Reg,
     reset::{AsyncReset, Reset, SyncReset},
diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs
index c793775..f1a9736 100644
--- a/crates/fayalite/src/prelude.rs
+++ b/crates/fayalite/src/prelude.rs
@@ -13,13 +13,16 @@ pub use crate::{
         repeat, CastBitsTo, CastTo, CastToBits, Expr, HdlPartialEq, HdlPartialOrd, MakeUninitExpr,
         ReduceBits, ToExpr,
     },
+    formal::{
+        formal_global_clock, formal_reset, hdl_assert, hdl_assert_with_enable, hdl_assume,
+        hdl_assume_with_enable, hdl_cover, hdl_cover_with_enable, MakeFormalExpr,
+    },
     hdl, hdl_module,
     int::{Bool, DynSize, KnownSize, SInt, SIntType, Size, UInt, UIntType},
     memory::{Mem, MemBuilder, ReadUnderWrite},
     module::{
-        annotate, connect, connect_any, hdl_assert, hdl_assert_with_enable, hdl_assume,
-        hdl_assume_with_enable, hdl_cover, hdl_cover_with_enable, incomplete_wire, instance,
-        memory, memory_array, memory_with_init, reg_builder, wire, Instance, Module, ModuleBuilder,
+        annotate, connect, connect_any, incomplete_wire, instance, memory, memory_array,
+        memory_with_init, reg_builder, wire, Instance, Module, ModuleBuilder,
     },
     reg::Reg,
     reset::{AsyncReset, Reset, SyncReset, ToAsyncReset, ToReset, ToSyncReset},
diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json
index 09ae23f..366ee2f 100644
--- a/crates/fayalite/visit_types.json
+++ b/crates/fayalite/visit_types.json
@@ -1089,7 +1089,7 @@
                 "source_location": "Visible"
             }
         },
-        "StmtFormalKind": {
+        "FormalKind": {
             "data": {
                 "$kind": "Enum",
                 "Assert": null,

From 1c63a441a9ca35edfaec23fee0de21b6d48f4c10 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 3 Oct 2024 00:27:28 -0700
Subject: [PATCH 038/190] add needed tools to CI

---
 .forgejo/workflows/test.yml | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index 6e82abf..762c1f8 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -11,10 +11,28 @@ jobs:
           fetch-depth: 0
       - run: |
           scripts/check-copyright.sh
+      - run: |
+          apt-get update -qq
+          apt-get install -qq cvc5 z3
       - run: |
           curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.80.1
           source "$HOME/.cargo/env"
           echo "$PATH" >> "$GITHUB_PATH"
+      - run: |
+          git clone --depth=1 --branch=yosys-0.45 https://github.com/YosysHQ/sby.git
+          make -C sby install
+      - run: |
+          git clone --depth=1 --branch=0.45 https://github.com/YosysHQ/yosys.git
+          cd yosys
+          autoconf -f
+          ./configure
+          make install -j6
+      - run: |
+          wget -O firrtl.tar.gz https://github.com/llvm/circt/releases/download/firtool-1.86.0/firrtl-bin-linux-x64.tar.gz
+          sha256sum -c - <<<'bf6f4ab18ae76f135c944efbd81e25391c31c1bd0617c58ab0592640abefee14  firrtl.tar.gz'
+          tar -xvaf firrtl.tar.gz
+          export PATH="$(realpath firtool-1.86.0/bin):$PATH"
+          echo "$PATH" >> "$GITHUB_PATH"
       - uses: https://github.com/Swatinem/rust-cache@v2
         with:
           save-if: ${{ github.ref == 'refs/heads/master' }}

From 4497f09ea011eec88543c7d8d7616af24946bede Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 3 Oct 2024 00:39:18 -0700
Subject: [PATCH 039/190] fix wrong build steps

---
 .forgejo/workflows/test.yml | 2 --
 1 file changed, 2 deletions(-)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index 762c1f8..da9376e 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -24,8 +24,6 @@ jobs:
       - run: |
           git clone --depth=1 --branch=0.45 https://github.com/YosysHQ/yosys.git
           cd yosys
-          autoconf -f
-          ./configure
           make install -j6
       - run: |
           wget -O firrtl.tar.gz https://github.com/llvm/circt/releases/download/firtool-1.86.0/firrtl-bin-linux-x64.tar.gz

From eb65bec26ef2b8d511c0de9641bf1d323d9267e2 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 3 Oct 2024 00:44:04 -0700
Subject: [PATCH 040/190] add yosys deps

---
 .forgejo/workflows/test.yml | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index da9376e..b97b9de 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -13,7 +13,10 @@ jobs:
           scripts/check-copyright.sh
       - run: |
           apt-get update -qq
-          apt-get install -qq cvc5 z3
+          apt-get install -qq cvc5 z3 build-essential clang lld bison flex \
+            libreadline-dev gawk tcl-dev libffi-dev git \
+            graphviz xdot pkg-config python3 libboost-system-dev \
+            libboost-python-dev libboost-filesystem-dev zlib1g-dev
       - run: |
           curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.80.1
           source "$HOME/.cargo/env"
@@ -22,7 +25,7 @@ jobs:
           git clone --depth=1 --branch=yosys-0.45 https://github.com/YosysHQ/sby.git
           make -C sby install
       - run: |
-          git clone --depth=1 --branch=0.45 https://github.com/YosysHQ/yosys.git
+          git clone --depth=1 --recursive --branch=0.45 https://github.com/YosysHQ/yosys.git
           cd yosys
           make install -j6
       - run: |

From bc26fe32fd15e46c562bbea3dfed2ae5f33fdad1 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 3 Oct 2024 01:01:06 -0700
Subject: [PATCH 041/190] add ccache and clean up deps

---
 .forgejo/workflows/test.yml | 29 +++++++++++++++++++++++++----
 1 file changed, 25 insertions(+), 4 deletions(-)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index b97b9de..a6c9726 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -13,10 +13,31 @@ jobs:
           scripts/check-copyright.sh
       - run: |
           apt-get update -qq
-          apt-get install -qq cvc5 z3 build-essential clang lld bison flex \
-            libreadline-dev gawk tcl-dev libffi-dev git \
-            graphviz xdot pkg-config python3 libboost-system-dev \
-            libboost-python-dev libboost-filesystem-dev zlib1g-dev
+          apt-get install -qq \
+            bison \
+            build-essential \
+            ccache \
+            clang \
+            cvc5 \
+            flex \
+            gawk \
+            git \
+            libboost-filesystem-dev \
+            libboost-python-dev \
+            libboost-system-dev \
+            libffi-dev \
+            libreadline-dev \
+            lld \
+            pkg-config \
+            python3 \
+            tcl-dev \
+            z3 \
+            zlib1g-dev \
+      - name: ccache
+        uses: https://github.com/hendrikmuhs/ccache-action@v1
+      - run: |
+          export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
+          echo "$PATH" >> "$GITHUB_PATH"
       - run: |
           curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.80.1
           source "$HOME/.cargo/env"

From 3e2fb9b94f9841fb930ff6ac5940865561d4e567 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 3 Oct 2024 01:08:01 -0700
Subject: [PATCH 042/190] WIP getting queue formal to pass -- passes for
 capacity <= 2

---
 crates/fayalite/src/cli.rs              |  89 ++++++++---
 crates/fayalite/src/formal.rs           |  15 +-
 crates/fayalite/src/testing.rs          |  86 +++++++++-
 crates/fayalite/src/util/ready_valid.rs | 199 ++++++++++++++++++------
 crates/fayalite/tests/module.rs         |  31 +++-
 5 files changed, 343 insertions(+), 77 deletions(-)

diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index a771de6..cbef722 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -12,7 +12,14 @@ use clap::{
     Parser, Subcommand, ValueEnum, ValueHint,
 };
 use eyre::{eyre, Report};
-use std::{error, ffi::OsString, fmt, io, path::PathBuf, process};
+use std::{
+    error,
+    ffi::OsString,
+    fmt::{self, Write},
+    fs, io, mem,
+    path::{Path, PathBuf},
+    process,
+};
 use tempfile::TempDir;
 
 pub type Result<T = (), E = CliError> = std::result::Result<T, E>;
@@ -246,15 +253,51 @@ pub struct VerilogArgs {
 #[non_exhaustive]
 pub struct VerilogOutput {
     pub firrtl: FirrtlOutput,
+    pub verilog_files: Vec<PathBuf>,
 }
 
 impl VerilogOutput {
-    pub fn verilog_file(&self) -> PathBuf {
+    pub fn main_verilog_file(&self) -> PathBuf {
         self.firrtl.file_with_ext("v")
     }
+    fn unadjusted_verilog_file(&self) -> PathBuf {
+        self.firrtl.file_with_ext("unadjusted.v")
+    }
 }
 
 impl VerilogArgs {
+    fn process_unadjusted_verilog_file(&self, mut output: VerilogOutput) -> Result<VerilogOutput> {
+        let input = fs::read_to_string(output.unadjusted_verilog_file())?;
+        let file_separator_prefix = "\n// ----- 8< ----- FILE \"";
+        let file_separator_suffix = "\" ----- 8< -----\n\n";
+        let mut input = &*input;
+        let main_verilog_file = output.main_verilog_file();
+        let mut file_name: Option<&Path> = Some(&main_verilog_file);
+        loop {
+            let (chunk, next_file_name) = if let Some((chunk, rest)) =
+                input.split_once(file_separator_prefix)
+            {
+                let Some((next_file_name, rest)) = rest.split_once(file_separator_suffix) else {
+                    return Err(CliError(eyre!("parsing firtool's output failed: found {file_separator_prefix:?} but no {file_separator_suffix:?}")));
+                };
+                input = rest;
+                (chunk, Some(next_file_name.as_ref()))
+            } else {
+                (mem::take(&mut input), None)
+            };
+            let Some(file_name) = mem::replace(&mut file_name, next_file_name) else {
+                break;
+            };
+            let file_name = output.firrtl.output_dir.join(file_name);
+            fs::write(&file_name, chunk)?;
+            if let Some(extension) = file_name.extension() {
+                if extension == "v" || extension == "sv" {
+                    output.verilog_files.push(file_name);
+                }
+            }
+        }
+        Ok(output)
+    }
     fn run_impl(&self, firrtl_output: FirrtlOutput) -> Result<VerilogOutput> {
         let Self {
             firrtl,
@@ -265,14 +308,15 @@ impl VerilogArgs {
         } = self;
         let output = VerilogOutput {
             firrtl: firrtl_output,
+            verilog_files: vec![],
         };
         let mut cmd = process::Command::new(firtool);
         cmd.arg(output.firrtl.firrtl_file());
         cmd.arg("-o");
-        cmd.arg(output.verilog_file());
+        cmd.arg(output.unadjusted_verilog_file());
         if *debug {
             cmd.arg("-g");
-            cmd.arg("--preserve-values=named");
+            cmd.arg("--preserve-values=all");
         }
         if let Some(dialect) = verilog_dialect {
             cmd.args(dialect.firtool_extra_args());
@@ -281,7 +325,7 @@ impl VerilogArgs {
         cmd.current_dir(&output.firrtl.output_dir);
         let status = firrtl.base.run_external_command(cmd)?;
         if status.success() {
-            Ok(output)
+            self.process_unadjusted_verilog_file(output)
         } else {
             Err(CliError(eyre!(
                 "running {} failed: {status}",
@@ -424,7 +468,7 @@ impl FormalOutput {
 }
 
 impl FormalArgs {
-    fn sby_contents(&self, output: &FormalOutput) -> String {
+    fn sby_contents(&self, output: &FormalOutput) -> Result<String> {
         let Self {
             verilog: _,
             sby: _,
@@ -448,15 +492,8 @@ impl FormalArgs {
         }
         let space_solver = OptArg(solver.as_ref());
         let smtbmc_options = smtbmc_extra_args.join(" ");
-        let verilog_file = output
-            .verilog
-            .verilog_file()
-            .into_os_string()
-            .into_string()
-            .ok()
-            .expect("verilog file path is not UTF-8");
         let top_module = &output.verilog.firrtl.top_module;
-        format!(
+        let mut retval = format!(
             "[options]\n\
             mode {mode}\n\
             depth {depth}\n\
@@ -465,18 +502,30 @@ impl FormalArgs {
             [engines]\n\
             smtbmc{space_solver} -- -- {smtbmc_options}\n\
             \n\
-            [script]\n\
-            read_verilog -sv -formal {verilog_file}\n\
-            prep -top {top_module}\n
-            "
-        )
+            [script]\n"
+        );
+        for verilog_file in &output.verilog.verilog_files {
+            let verilog_file = verilog_file
+                .to_str()
+                .ok_or_else(|| CliError(eyre!("verilog file path is not UTF-8")))?;
+            if verilog_file.contains(|ch: char| {
+                (ch != ' ' && ch != '\t' && ch.is_ascii_whitespace()) || ch == '"'
+            }) {
+                return Err(CliError(eyre!(
+                    "verilog file path contains characters that aren't permitted"
+                )));
+            }
+            writeln!(retval, "read_verilog -sv -formal \"{verilog_file}\"").unwrap();
+        }
+        writeln!(retval, "prep -top {top_module}").unwrap();
+        Ok(retval)
     }
     fn run_impl(&self, verilog_output: VerilogOutput) -> Result<FormalOutput> {
         let output = FormalOutput {
             verilog: verilog_output,
         };
         let sby_file = output.sby_file();
-        std::fs::write(&sby_file, self.sby_contents(&output))?;
+        std::fs::write(&sby_file, self.sby_contents(&output)?)?;
         let mut cmd = process::Command::new(&self.sby);
         cmd.arg("-f");
         cmd.arg(sby_file);
diff --git a/crates/fayalite/src/formal.rs b/crates/fayalite/src/formal.rs
index 5e90b59..eab1969 100644
--- a/crates/fayalite/src/formal.rs
+++ b/crates/fayalite/src/formal.rs
@@ -1,6 +1,10 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-use crate::{intern::Intern, prelude::*};
+use crate::{
+    intern::{Intern, Interned},
+    prelude::*,
+};
+use std::sync::OnceLock;
 
 #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
 pub enum FormalKind {
@@ -32,7 +36,7 @@ pub fn formal_stmt_with_enable_and_loc(
         kind,
         clk,
         pred,
-        en,
+        en: en & !formal_reset().cast_to_static::<Bool>(),
         text: text.intern(),
         source_location,
     });
@@ -160,11 +164,11 @@ endmodule
 }
 
 #[hdl]
-pub fn formal_reset() -> Expr<AsyncReset> {
+pub fn formal_reset() -> Expr<SyncReset> {
     #[hdl_module(extern)]
     fn formal_reset() {
         #[hdl]
-        let rst: AsyncReset = m.output();
+        let rst: SyncReset = m.output();
         m.annotate_module(BlackBoxInlineAnnotation {
             path: "fayalite_formal_reset.v".intern(),
             text: r"module __fayalite_formal_reset(output rst);
@@ -180,7 +184,8 @@ endmodule
         });
         m.verilog_name("__fayalite_formal_reset");
     }
+    static MOD: OnceLock<Interned<Module<formal_reset>>> = OnceLock::new();
     #[hdl]
-    let formal_reset = instance(formal_reset());
+    let formal_reset = instance(*MOD.get_or_init(formal_reset));
     formal_reset.rst
 }
diff --git a/crates/fayalite/src/testing.rs b/crates/fayalite/src/testing.rs
index 8046f05..a647f47 100644
--- a/crates/fayalite/src/testing.rs
+++ b/crates/fayalite/src/testing.rs
@@ -5,7 +5,14 @@ use crate::{
     firrtl::ExportOptions,
 };
 use clap::Parser;
-use std::sync::OnceLock;
+use hashbrown::HashMap;
+use serde::Deserialize;
+use std::{
+    fmt::Write,
+    path::{Path, PathBuf},
+    process::Command,
+    sync::{Mutex, OnceLock},
+};
 
 fn assert_formal_helper() -> FormalArgs {
     static FORMAL_ARGS: OnceLock<FormalArgs> = OnceLock::new();
@@ -15,8 +22,84 @@ fn assert_formal_helper() -> FormalArgs {
         .clone()
 }
 
+#[derive(Deserialize)]
+struct CargoMetadata {
+    target_directory: String,
+}
+
+fn get_cargo_target_dir() -> &'static Path {
+    static RETVAL: OnceLock<PathBuf> = OnceLock::new();
+    RETVAL.get_or_init(|| {
+        let output = Command::new(
+            std::env::var_os("CARGO")
+                .as_deref()
+                .unwrap_or("cargo".as_ref()),
+        )
+        .arg("metadata")
+        .output()
+        .expect("can't run `cargo metadata`");
+        if !output.status.success() {
+            panic!(
+                "can't run `cargo metadata`:\n{}\nexited with status: {}",
+                String::from_utf8_lossy(&output.stderr),
+                output.status
+            );
+        }
+        let CargoMetadata { target_directory } =
+            serde_json::from_slice(&output.stdout).expect("can't parse output of `cargo metadata`");
+        PathBuf::from(target_directory)
+    })
+}
+
+#[track_caller]
+fn get_assert_formal_target_path(test_name: &dyn std::fmt::Display) -> PathBuf {
+    static DIRS: Mutex<Option<HashMap<String, u64>>> = Mutex::new(None);
+    let test_name = test_name.to_string();
+    // don't use line/column numbers since that constantly changes as you edit tests
+    let file = std::panic::Location::caller().file();
+    // simple reproducible hash
+    let simple_hash = file.bytes().chain(test_name.bytes()).fold(
+        ((file.len() as u32) << 16).wrapping_add(test_name.len() as u32),
+        |mut h, b| {
+            h = h.wrapping_mul(0xaa0d184b);
+            h ^= h.rotate_right(5);
+            h ^= h.rotate_right(13);
+            h.wrapping_add(b as u32)
+        },
+    );
+    let mut dir = String::with_capacity(64);
+    write!(dir, "{simple_hash:08x}-").unwrap();
+    for ch in Path::new(file)
+        .file_stem()
+        .unwrap_or_default()
+        .to_str()
+        .unwrap()
+        .chars()
+        .chain(['-'])
+        .chain(test_name.chars())
+    {
+        dir.push(match ch {
+            ch if ch.is_alphanumeric() => ch,
+            '_' | '-' | '+' | '.' | ',' | ' ' => ch,
+            _ => '_',
+        });
+    }
+    let index = *DIRS
+        .lock()
+        .unwrap()
+        .get_or_insert_with(HashMap::new)
+        .entry_ref(&dir)
+        .and_modify(|v| *v += 1)
+        .or_insert(0);
+    write!(dir, ".{index}").unwrap();
+    get_cargo_target_dir()
+        .join("fayalite_assert_formal")
+        .join(dir)
+}
+
 #[track_caller]
 pub fn assert_formal<M>(
+    test_name: impl std::fmt::Display,
     module: M,
     mode: FormalMode,
     depth: u64,
@@ -27,6 +110,7 @@ pub fn assert_formal<M>(
 {
     let mut args = assert_formal_helper();
     args.verilog.firrtl.base.redirect_output_for_rust_test = true;
+    args.verilog.firrtl.base.output = Some(get_assert_formal_target_path(&test_name));
     args.verilog.firrtl.export_options = export_options;
     args.verilog.debug = true;
     args.mode = mode;
diff --git a/crates/fayalite/src/util/ready_valid.rs b/crates/fayalite/src/util/ready_valid.rs
index ab19cd1..41299a6 100644
--- a/crates/fayalite/src/util/ready_valid.rs
+++ b/crates/fayalite/src/util/ready_valid.rs
@@ -23,6 +23,19 @@ impl<T: Type> ReadyValid<T> {
         fire
     }
     #[hdl]
+    pub fn fire_data(expr: impl ToExpr<Type = Self>) -> Expr<HdlOption<T>> {
+        let expr = expr.to_expr();
+        let option_ty = Expr::ty(expr).data;
+        #[hdl]
+        let fire_data = wire(option_ty);
+        connect(fire_data, option_ty.HdlNone());
+        #[hdl]
+        if expr.ready {
+            connect(fire_data, expr.data);
+        }
+        fire_data
+    }
+    #[hdl]
     pub fn map<R: Type>(
         expr: Expr<Self>,
         f: impl FnOnce(Expr<T>) -> Expr<R>,
@@ -163,7 +176,6 @@ pub fn queue<T: Type>(
     }
 }
 
-#[cfg(todo)]
 #[cfg(test)]
 mod tests {
     use super::*;
@@ -171,27 +183,39 @@ mod tests {
         cli::FormalMode, firrtl::ExportOptions,
         module::transform::simplify_enums::SimplifyEnumsKind, testing::assert_formal,
     };
+    use std::num::NonZero;
 
-    #[test]
-    fn test_queue() {
+    #[track_caller]
+    fn test_queue(capacity: NonZeroUsize, inp_ready_is_comb: bool, out_valid_is_comb: bool) {
+        assert_formal(
+            format_args!("test_queue_{capacity}_{inp_ready_is_comb}_{out_valid_is_comb}"),
+            queue_test(capacity, inp_ready_is_comb, out_valid_is_comb),
+            FormalMode::BMC,
+            20,
+            None,
+            ExportOptions {
+                simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
+                ..ExportOptions::default()
+            },
+        );
         #[hdl_module]
         fn queue_test(capacity: NonZeroUsize, inp_ready_is_comb: bool, out_valid_is_comb: bool) {
-            #[hdl]
-            let clk: Clock = m.input();
-            #[hdl]
-            let rst: SyncReset = m.input();
             #[hdl]
             let inp_data: HdlOption<UInt<8>> = m.input();
             #[hdl]
             let out_ready: Bool = m.input();
             #[hdl]
+            let start_check: Bool = m.input();
+            #[hdl]
+            let clk: Clock = m.input();
+            #[hdl]
             let cd = wire();
             connect(
                 cd,
                 #[hdl]
                 ClockDomain {
                     clk,
-                    rst: rst.to_reset(),
+                    rst: formal_reset().to_reset(),
                 },
             );
             #[hdl]
@@ -216,52 +240,139 @@ mod tests {
             } else if !ReadyValid::fire(dut.inp) & ReadyValid::fire(dut.out) {
                 connect_any(next_count, count - 1u8);
             }
-            hdl_assert(clk, count.cmp_eq(dut.count), "");
+            hdl_assert(cd.clk, count.cmp_eq(dut.count), "");
             #[hdl]
-            let index = reg_builder().clock_domain(cd).reset(HdlNone::<UInt<32>>());
+            let started_check = reg_builder().clock_domain(cd).reset(false);
             #[hdl]
-            let data = reg_builder().clock_domain(cd).reset(HdlNone());
+            let steps_till_output = reg_builder().clock_domain(cd).reset(0u32);
             #[hdl]
-            match index {
-                HdlNone =>
-                {
-                    #[hdl]
-                    if ReadyValid::fire(dut.inp) {
-                        connect(index, HdlSome(0u32));
-                        connect(data, dut.inp.data);
-                    }
+            let expected_output = reg_builder().clock_domain(cd).reset(HdlNone());
+            #[hdl]
+            if start_check & !started_check {
+                #[hdl]
+                if let HdlSome(inp) = ReadyValid::fire_data(dut.inp) {
+                    connect(started_check, true);
+                    connect_any(
+                        steps_till_output,
+                        count + (!ReadyValid::fire(dut.out)).cast_to(UInt[1]),
+                    );
+                    connect(expected_output, HdlSome(inp));
                 }
-                HdlSome(cur_index) =>
+            } else if started_check & steps_till_output.cmp_ne(0u32) & ReadyValid::fire(dut.out) {
+                connect_any(steps_till_output, steps_till_output - 1u32);
+            }
+            #[hdl]
+            let stored_output = reg_builder().clock_domain(cd).reset(HdlNone());
+            #[hdl]
+            if let HdlSome(out) = ReadyValid::fire_data(dut.out) {
+                #[hdl]
+                if (start_check & !started_check) | (started_check & steps_till_output.cmp_ne(0u32))
                 {
+                    connect(stored_output, HdlSome(out));
+                }
+            }
+            #[hdl]
+            if started_check & steps_till_output.cmp_eq(0u32) {
+                #[hdl]
+                if let HdlSome(expected_output) = expected_output {
                     #[hdl]
-                    if cur_index.cmp_ge(next_count) {
-                        connect(index, HdlNone());
-                        #[hdl]
-                        if let HdlSome(data) = data {
-                            #[hdl]
-                            if let HdlSome(out_data) = dut.out.data {
-                                hdl_assert(clk, data.cmp_eq(out_data), "");
-                            } else {
-                                hdl_assert(clk, false.to_expr(), "");
-                            }
-                        } else {
-                            hdl_assert(clk, false.to_expr(), "");
-                        }
+                    if let HdlSome(stored_output) = stored_output {
+                        hdl_assert(cd.clk, stored_output.cmp_eq(expected_output), "");
                     } else {
-                        connect(index, HdlSome((cur_index + 1u8).cast_to_static()));
+                        hdl_assert(cd.clk, false.to_expr(), "");
                     }
+                } else {
+                    hdl_assert(cd.clk, false.to_expr(), "");
                 }
             }
         }
-        assert_formal(
-            queue_test(NonZeroUsize::new(2).unwrap(), false, false),
-            FormalMode::BMC,
-            20,
-            None,
-            ExportOptions {
-                simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
-                ..ExportOptions::default()
-            },
-        );
+    }
+
+    #[test]
+    fn test_1_false_false() {
+        test_queue(NonZero::new(1).unwrap(), false, false);
+    }
+
+    #[test]
+    fn test_1_false_true() {
+        test_queue(NonZero::new(1).unwrap(), false, true);
+    }
+
+    #[test]
+    fn test_1_true_false() {
+        test_queue(NonZero::new(1).unwrap(), true, false);
+    }
+
+    #[test]
+    fn test_1_true_true() {
+        test_queue(NonZero::new(1).unwrap(), true, true);
+    }
+
+    #[test]
+    fn test_2_false_false() {
+        test_queue(NonZero::new(2).unwrap(), false, false);
+    }
+
+    #[test]
+    fn test_2_false_true() {
+        test_queue(NonZero::new(2).unwrap(), false, true);
+    }
+
+    #[test]
+    fn test_2_true_false() {
+        test_queue(NonZero::new(2).unwrap(), true, false);
+    }
+
+    #[test]
+    fn test_2_true_true() {
+        test_queue(NonZero::new(2).unwrap(), true, true);
+    }
+
+    #[cfg(todo)]
+    #[test]
+    fn test_3_false_false() {
+        test_queue(NonZero::new(3).unwrap(), false, false);
+    }
+
+    #[cfg(todo)]
+    #[test]
+    fn test_3_false_true() {
+        test_queue(NonZero::new(3).unwrap(), false, true);
+    }
+
+    #[cfg(todo)]
+    #[test]
+    fn test_3_true_false() {
+        test_queue(NonZero::new(3).unwrap(), true, false);
+    }
+
+    #[cfg(todo)]
+    #[test]
+    fn test_3_true_true() {
+        test_queue(NonZero::new(3).unwrap(), true, true);
+    }
+
+    #[cfg(todo)]
+    #[test]
+    fn test_4_false_false() {
+        test_queue(NonZero::new(4).unwrap(), false, false);
+    }
+
+    #[cfg(todo)]
+    #[test]
+    fn test_4_false_true() {
+        test_queue(NonZero::new(4).unwrap(), false, true);
+    }
+
+    #[cfg(todo)]
+    #[test]
+    fn test_4_true_false() {
+        test_queue(NonZero::new(4).unwrap(), true, false);
+    }
+
+    #[cfg(todo)]
+    #[test]
+    fn test_4_true_true() {
+        test_queue(NonZero::new(4).unwrap(), true, true);
     }
 }
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 856cbf0..7d12739 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -3390,7 +3390,15 @@ fn test_formal() {
     assert_export_firrtl! {
         m =>
         "/test/check_formal.fir": r#"FIRRTL version 3.2.0
-circuit check_formal:
+circuit check_formal: %[[
+  {
+    "class": "firrtl.transforms.BlackBoxInlineAnno",
+    "name": "fayalite_formal_reset.v",
+    "text": "module __fayalite_formal_reset(output rst);\n    reg rst;\n    (* gclk *)\n    reg gclk;\n    initial rst = 1;\n    always @(posedge gclk)\n        rst <= 0;\nendmodule\n",
+    "target": "~check_formal|formal_reset"
+  }
+]]
+    type Ty0 = {rst: UInt<1>}
     module check_formal: @[module-XXXXXXXXXX.rs 1:1]
         input clk: Clock @[module-XXXXXXXXXX.rs 2:1]
         input en1: UInt<1> @[module-XXXXXXXXXX.rs 3:1]
@@ -3399,12 +3407,21 @@ circuit check_formal:
         input pred1: UInt<1> @[module-XXXXXXXXXX.rs 6:1]
         input pred2: UInt<1> @[module-XXXXXXXXXX.rs 7:1]
         input pred3: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
-        assert(clk, pred1, en1, "en check 1") @[module-XXXXXXXXXX.rs 9:1]
-        assume(clk, pred2, en2, "en check 2") @[module-XXXXXXXXXX.rs 10:1]
-        cover(clk, pred3, en3, "en check 3") @[module-XXXXXXXXXX.rs 11:1]
-        assert(clk, pred1, UInt<1>(0h1), "check 1") @[module-XXXXXXXXXX.rs 12:1]
-        assume(clk, pred2, UInt<1>(0h1), "check 2") @[module-XXXXXXXXXX.rs 13:1]
-        cover(clk, pred3, UInt<1>(0h1), "check 3") @[module-XXXXXXXXXX.rs 14:1]
+        inst formal_reset of formal_reset @[formal.rs 189:24]
+        assert(clk, pred1, and(en1, not(formal_reset.rst)), "en check 1") @[module-XXXXXXXXXX.rs 9:1]
+        inst formal_reset_1 of formal_reset @[formal.rs 189:24]
+        assume(clk, pred2, and(en2, not(formal_reset_1.rst)), "en check 2") @[module-XXXXXXXXXX.rs 10:1]
+        inst formal_reset_2 of formal_reset @[formal.rs 189:24]
+        cover(clk, pred3, and(en3, not(formal_reset_2.rst)), "en check 3") @[module-XXXXXXXXXX.rs 11:1]
+        inst formal_reset_3 of formal_reset @[formal.rs 189:24]
+        assert(clk, pred1, and(UInt<1>(0h1), not(formal_reset_3.rst)), "check 1") @[module-XXXXXXXXXX.rs 12:1]
+        inst formal_reset_4 of formal_reset @[formal.rs 189:24]
+        assume(clk, pred2, and(UInt<1>(0h1), not(formal_reset_4.rst)), "check 2") @[module-XXXXXXXXXX.rs 13:1]
+        inst formal_reset_5 of formal_reset @[formal.rs 189:24]
+        cover(clk, pred3, and(UInt<1>(0h1), not(formal_reset_5.rst)), "check 3") @[module-XXXXXXXXXX.rs 14:1]
+    extmodule formal_reset: @[formal.rs 168:5]
+        output rst: UInt<1> @[formal.rs 171:32]
+        defname = __fayalite_formal_reset
 "#,
     };
 }

From 4084a70485eeb0f78b7a13187053997d66a19405 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 3 Oct 2024 01:43:46 -0700
Subject: [PATCH 043/190] switch default solver to z3

---
 crates/fayalite/src/cli.rs     | 18 +++---------------
 crates/fayalite/src/testing.rs |  4 +++-
 2 files changed, 6 insertions(+), 16 deletions(-)

diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index cbef722..b0b818c 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -419,8 +419,8 @@ pub struct FormalArgs {
     pub mode: FormalMode,
     #[arg(long, default_value_t = Self::DEFAULT_DEPTH)]
     pub depth: u64,
-    #[arg(long)]
-    pub solver: Option<String>,
+    #[arg(long, default_value = "z3")]
+    pub solver: String,
     #[arg(long)]
     pub smtbmc_extra_args: Vec<String>,
     #[command(flatten)]
@@ -479,18 +479,6 @@ impl FormalArgs {
             solver,
             _formal_adjust_args: _,
         } = self;
-        struct OptArg<T>(Option<T>);
-        impl<T: fmt::Display> fmt::Display for OptArg<T> {
-            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-                if let Some(v) = &self.0 {
-                    f.write_str(" ")?;
-                    v.fmt(f)
-                } else {
-                    Ok(())
-                }
-            }
-        }
-        let space_solver = OptArg(solver.as_ref());
         let smtbmc_options = smtbmc_extra_args.join(" ");
         let top_module = &output.verilog.firrtl.top_module;
         let mut retval = format!(
@@ -500,7 +488,7 @@ impl FormalArgs {
             wait on\n\
             \n\
             [engines]\n\
-            smtbmc{space_solver} -- -- {smtbmc_options}\n\
+            smtbmc {solver} -- -- {smtbmc_options}\n\
             \n\
             [script]\n"
         );
diff --git a/crates/fayalite/src/testing.rs b/crates/fayalite/src/testing.rs
index a647f47..07252f1 100644
--- a/crates/fayalite/src/testing.rs
+++ b/crates/fayalite/src/testing.rs
@@ -115,6 +115,8 @@ pub fn assert_formal<M>(
     args.verilog.debug = true;
     args.mode = mode;
     args.depth = depth;
-    args.solver = solver.map(String::from);
+    if let Some(solver) = solver {
+        args.solver = solver.into();
+    }
     args.run(module).expect("testing::assert_formal() failed");
 }

From 15a28aa7a778dbba5422f6f9e40e8c530fc0e31a Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 3 Oct 2024 01:44:06 -0700
Subject: [PATCH 044/190] install python3-click -- needed by symbiyosys

---
 .forgejo/workflows/test.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index a6c9726..83d291b 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -30,6 +30,7 @@ jobs:
             lld \
             pkg-config \
             python3 \
+            python3-click \
             tcl-dev \
             z3 \
             zlib1g-dev \

From 343805f80b14982495fd4c208b906e7bc694a4f0 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 3 Oct 2024 23:04:14 -0700
Subject: [PATCH 045/190] fix #[hdl] to work with unusual identifier hygiene
 from macros

---
 .../src/hdl_bundle.rs                         | 109 +++++++++---------
 .../fayalite-proc-macros-impl/src/hdl_enum.rs |  96 +++++++--------
 .../src/hdl_type_common.rs                    |  39 +++++--
 crates/fayalite/src/ty.rs                     |   4 +-
 crates/fayalite/tests/hdl_types.rs            |  66 +++++++++++
 5 files changed, 202 insertions(+), 112 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
index 30cf90f..f3a589a 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
@@ -431,6 +431,7 @@ impl ToTokens for ParsedBundle {
             builder_ident,
             mask_type_builder_ident,
         } = self;
+        let span = ident.span();
         let ItemOptions {
             outline_generated: _,
             target,
@@ -440,7 +441,7 @@ impl ToTokens for ParsedBundle {
         } = &options.body;
         let target = get_target(target, ident);
         let mut item_attrs = attrs.clone();
-        item_attrs.push(common_derives(ident.span()));
+        item_attrs.push(common_derives(span));
         ItemStruct {
             attrs: item_attrs,
             vis: vis.clone(),
@@ -462,19 +463,19 @@ impl ToTokens for ParsedBundle {
                     .map(|ParsedField { ident, ty, .. }| {
                         let ident = ident.as_ref().unwrap();
                         let expr = ty.make_hdl_type_expr(context);
-                        quote_spanned! {ident.span()=>
+                        quote_spanned! {span=>
                             #ident: #expr,
                         }
                     })
                     .collect();
-                parse_quote_spanned! {ident.span()=>
+                parse_quote_spanned! {span=>
                     #target {
                         #(#fields)*
                     }
                 }
             })
         }
-        let mut wrapped_in_const = WrappedInConst::new(tokens, ident.span());
+        let mut wrapped_in_const = WrappedInConst::new(tokens, span);
         let tokens = wrapped_in_const.inner();
         let builder = Builder {
             vis: vis.clone(),
@@ -488,9 +489,8 @@ impl ToTokens for ParsedBundle {
         let unfilled_builder_ty = builder.builder_struct_ty(|_| BuilderFieldState::Unfilled);
         let filled_builder_ty = builder.builder_struct_ty(|_| BuilderFieldState::Filled);
         let mut mask_type_fields = FieldsNamed::from(fields.clone());
-        for Field { ident, ty, .. } in &mut mask_type_fields.named {
-            let ident = ident.as_ref().unwrap();
-            *ty = parse_quote_spanned! {ident.span()=>
+        for Field { ty, .. } in &mut mask_type_fields.named {
+            *ty = parse_quote_spanned! {span=>
                 <#ty as ::fayalite::ty::Type>::MaskType
             };
         }
@@ -509,8 +509,8 @@ impl ToTokens for ParsedBundle {
             mask_type_builder.builder_struct_ty(|_| BuilderFieldState::Filled);
         ItemStruct {
             attrs: vec![
-                common_derives(ident.span()),
-                parse_quote_spanned! {ident.span()=>
+                common_derives(span),
+                parse_quote_spanned! {span=>
                     #[allow(non_camel_case_types, dead_code)]
                 },
             ],
@@ -523,16 +523,15 @@ impl ToTokens for ParsedBundle {
         }
         .to_tokens(tokens);
         let mut mask_type_match_variant_fields = mask_type_fields;
-        for Field { ident, ty, .. } in &mut mask_type_match_variant_fields.named {
-            let ident = ident.as_ref().unwrap();
-            *ty = parse_quote_spanned! {ident.span()=>
+        for Field { ty, .. } in &mut mask_type_match_variant_fields.named {
+            *ty = parse_quote_spanned! {span=>
                 ::fayalite::expr::Expr<#ty>
             };
         }
         ItemStruct {
             attrs: vec![
-                common_derives(ident.span()),
-                parse_quote_spanned! {ident.span()=>
+                common_derives(span),
+                parse_quote_spanned! {span=>
                     #[allow(non_camel_case_types, dead_code)]
                 },
             ],
@@ -545,16 +544,15 @@ impl ToTokens for ParsedBundle {
         }
         .to_tokens(tokens);
         let mut match_variant_fields = FieldsNamed::from(fields.clone());
-        for Field { ident, ty, .. } in &mut match_variant_fields.named {
-            let ident = ident.as_ref().unwrap();
-            *ty = parse_quote_spanned! {ident.span()=>
+        for Field { ty, .. } in &mut match_variant_fields.named {
+            *ty = parse_quote_spanned! {span=>
                 ::fayalite::expr::Expr<#ty>
             };
         }
         ItemStruct {
             attrs: vec![
-                common_derives(ident.span()),
-                parse_quote_spanned! {ident.span()=>
+                common_derives(span),
+                parse_quote_spanned! {span=>
                     #[allow(non_camel_case_types, dead_code)]
                 },
             ],
@@ -566,17 +564,20 @@ impl ToTokens for ParsedBundle {
             semi_token: None,
         }
         .to_tokens(tokens);
+        let this_token = Ident::new("__this", span);
+        let fields_token = Ident::new("__fields", span);
+        let self_token = Token![self](span);
         let match_variant_body_fields = Vec::from_iter(fields.named().into_iter().map(|field| {
             let ident: &Ident = field.ident().as_ref().unwrap();
             let ident_str = ident.to_string();
-            quote_spanned! {ident.span()=>
-                #ident: ::fayalite::expr::Expr::field(__this, #ident_str),
+            quote_spanned! {span=>
+                #ident: ::fayalite::expr::Expr::field(#this_token, #ident_str),
             }
         }));
         let mask_type_body_fields = Vec::from_iter(fields.named().into_iter().map(|field| {
             let ident: &Ident = field.ident().as_ref().unwrap();
-            quote_spanned! {ident.span()=>
-                #ident: ::fayalite::ty::Type::mask_type(&self.#ident),
+            quote_spanned! {span=>
+                #ident: ::fayalite::ty::Type::mask_type(&#self_token.#ident),
             }
         }));
         let from_canonical_body_fields =
@@ -585,13 +586,13 @@ impl ToTokens for ParsedBundle {
                     let ident: &Ident = field.ident().as_ref().unwrap();
                     let ident_str = ident.to_string();
                     let flipped = flip.is_some();
-                    quote_spanned! {ident.span()=>
+                    quote_spanned! {span=>
                         #ident: {
                             let ::fayalite::bundle::BundleField {
                                 name: __name,
                                 flipped: __flipped,
                                 ty: __ty,
-                            } = __fields[#index];
+                            } = #fields_token[#index];
                             ::fayalite::__std::assert_eq!(&*__name, #ident_str);
                             ::fayalite::__std::assert_eq!(__flipped, #flipped);
                             ::fayalite::ty::Type::from_canonical(__ty)
@@ -604,17 +605,17 @@ impl ToTokens for ParsedBundle {
                 let ident: &Ident = field.ident().as_ref().unwrap();
                 let ident_str = ident.to_string();
                 let flipped = flip.is_some();
-                quote_spanned! {ident.span()=>
+                quote_spanned! {span=>
                     ::fayalite::bundle::BundleField {
                         name: ::fayalite::intern::Intern::intern(#ident_str),
                         flipped: #flipped,
-                        ty: ::fayalite::ty::Type::canonical(&self.#ident),
+                        ty: ::fayalite::ty::Type::canonical(&#self_token.#ident),
                     },
                 }
             },
         ));
         let fields_len = fields.named().into_iter().len();
-        quote_spanned! {ident.span()=>
+        quote_spanned! {span=>
             #[automatically_derived]
             impl #impl_generics ::fayalite::ty::Type for #mask_type_ident #type_generics
             #where_clause
@@ -630,7 +631,7 @@ impl ToTokens for ParsedBundle {
                     <Self as ::fayalite::ty::Type>::MatchVariantAndInactiveScope,
                 >;
                 fn match_variants(
-                    __this: ::fayalite::expr::Expr<Self>,
+                    #this_token: ::fayalite::expr::Expr<Self>,
                     __source_location: ::fayalite::source_location::SourceLocation,
                 ) -> <Self as ::fayalite::ty::Type>::MatchVariantsIter {
                     let __retval = #mask_type_match_variant_ident {
@@ -638,19 +639,19 @@ impl ToTokens for ParsedBundle {
                     };
                     ::fayalite::__std::iter::once(::fayalite::ty::MatchVariantWithoutScope(__retval))
                 }
-                fn mask_type(&self) -> <Self as ::fayalite::ty::Type>::MaskType {
-                    *self
+                fn mask_type(&#self_token) -> <Self as ::fayalite::ty::Type>::MaskType {
+                    *#self_token
                 }
-                fn canonical(&self) -> ::fayalite::ty::CanonicalType {
-                    ::fayalite::ty::Type::canonical(&::fayalite::bundle::Bundle::new(::fayalite::bundle::BundleType::fields(self)))
+                fn canonical(&#self_token) -> ::fayalite::ty::CanonicalType {
+                    ::fayalite::ty::Type::canonical(&::fayalite::bundle::Bundle::new(::fayalite::bundle::BundleType::fields(#self_token)))
                 }
                 #[track_caller]
                 fn from_canonical(__canonical_type: ::fayalite::ty::CanonicalType) -> Self {
                     let ::fayalite::ty::CanonicalType::Bundle(__bundle) = __canonical_type else {
                         ::fayalite::__std::panic!("expected bundle");
                     };
-                    let __fields = ::fayalite::bundle::BundleType::fields(&__bundle);
-                    ::fayalite::__std::assert_eq!(__fields.len(), #fields_len, "bundle has wrong number of fields");
+                    let #fields_token = ::fayalite::bundle::BundleType::fields(&__bundle);
+                    ::fayalite::__std::assert_eq!(#fields_token.len(), #fields_len, "bundle has wrong number of fields");
                     Self {
                         #(#from_canonical_body_fields)*
                     }
@@ -665,7 +666,7 @@ impl ToTokens for ParsedBundle {
             {
                 type Builder = #unfilled_mask_type_builder_ty;
                 type FilledBuilder = #filled_mask_type_builder_ty;
-                fn fields(&self) -> ::fayalite::intern::Interned<[::fayalite::bundle::BundleField]> {
+                fn fields(&#self_token) -> ::fayalite::intern::Interned<[::fayalite::bundle::BundleField]> {
                     ::fayalite::intern::Intern::intern(&[#(#fields_body_fields)*][..])
                 }
             }
@@ -680,8 +681,8 @@ impl ToTokens for ParsedBundle {
             impl #impl_generics ::fayalite::ty::TypeWithDeref for #mask_type_ident #type_generics
             #where_clause
             {
-                fn expr_deref(__this: &::fayalite::expr::Expr<Self>) -> &<Self as ::fayalite::ty::Type>::MatchVariant {
-                    let __this = *__this;
+                fn expr_deref(#this_token: &::fayalite::expr::Expr<Self>) -> &<Self as ::fayalite::ty::Type>::MatchVariant {
+                    let #this_token = *#this_token;
                     let __retval = #mask_type_match_variant_ident {
                         #(#match_variant_body_fields)*
                     };
@@ -703,7 +704,7 @@ impl ToTokens for ParsedBundle {
                     <Self as ::fayalite::ty::Type>::MatchVariantAndInactiveScope,
                 >;
                 fn match_variants(
-                    __this: ::fayalite::expr::Expr<Self>,
+                    #this_token: ::fayalite::expr::Expr<Self>,
                     __source_location: ::fayalite::source_location::SourceLocation,
                 ) -> <Self as ::fayalite::ty::Type>::MatchVariantsIter {
                     let __retval = #match_variant_ident {
@@ -711,21 +712,21 @@ impl ToTokens for ParsedBundle {
                     };
                     ::fayalite::__std::iter::once(::fayalite::ty::MatchVariantWithoutScope(__retval))
                 }
-                fn mask_type(&self) -> <Self as ::fayalite::ty::Type>::MaskType {
+                fn mask_type(&#self_token) -> <Self as ::fayalite::ty::Type>::MaskType {
                     #mask_type_ident {
                         #(#mask_type_body_fields)*
                     }
                 }
-                fn canonical(&self) -> ::fayalite::ty::CanonicalType {
-                    ::fayalite::ty::Type::canonical(&::fayalite::bundle::Bundle::new(::fayalite::bundle::BundleType::fields(self)))
+                fn canonical(&#self_token) -> ::fayalite::ty::CanonicalType {
+                    ::fayalite::ty::Type::canonical(&::fayalite::bundle::Bundle::new(::fayalite::bundle::BundleType::fields(#self_token)))
                 }
                 #[track_caller]
                 fn from_canonical(__canonical_type: ::fayalite::ty::CanonicalType) -> Self {
                     let ::fayalite::ty::CanonicalType::Bundle(__bundle) = __canonical_type else {
                         ::fayalite::__std::panic!("expected bundle");
                     };
-                    let __fields = ::fayalite::bundle::BundleType::fields(&__bundle);
-                    ::fayalite::__std::assert_eq!(__fields.len(), #fields_len, "bundle has wrong number of fields");
+                    let #fields_token = ::fayalite::bundle::BundleType::fields(&__bundle);
+                    ::fayalite::__std::assert_eq!(#fields_token.len(), #fields_len, "bundle has wrong number of fields");
                     Self {
                         #(#from_canonical_body_fields)*
                     }
@@ -740,7 +741,7 @@ impl ToTokens for ParsedBundle {
             {
                 type Builder = #unfilled_builder_ty;
                 type FilledBuilder = #filled_builder_ty;
-                fn fields(&self) -> ::fayalite::intern::Interned<[::fayalite::bundle::BundleField]> {
+                fn fields(&#self_token) -> ::fayalite::intern::Interned<[::fayalite::bundle::BundleField]> {
                     ::fayalite::intern::Intern::intern(&[#(#fields_body_fields)*][..])
                 }
             }
@@ -755,8 +756,8 @@ impl ToTokens for ParsedBundle {
             impl #impl_generics ::fayalite::ty::TypeWithDeref for #target #type_generics
             #where_clause
             {
-                fn expr_deref(__this: &::fayalite::expr::Expr<Self>) -> &<Self as ::fayalite::ty::Type>::MatchVariant {
-                    let __this = *__this;
+                fn expr_deref(#this_token: &::fayalite::expr::Expr<Self>) -> &<Self as ::fayalite::ty::Type>::MatchVariant {
+                    let #this_token = *#this_token;
                     let __retval = #match_variant_ident {
                         #(#match_variant_body_fields)*
                     };
@@ -772,7 +773,7 @@ impl ToTokens for ParsedBundle {
             let static_type_body_fields = Vec::from_iter(fields.named().into_iter().map(|field| {
                 let ident: &Ident = field.ident().as_ref().unwrap();
                 let ty = field.ty();
-                quote_spanned! {ident.span()=>
+                quote_spanned! {span=>
                     #ident: <#ty as ::fayalite::ty::StaticType>::TYPE,
                 }
             }));
@@ -780,28 +781,26 @@ impl ToTokens for ParsedBundle {
                 Vec::from_iter(fields.named().into_iter().map(|field| {
                     let ident: &Ident = field.ident().as_ref().unwrap();
                     let ty = field.ty();
-                    quote_spanned! {ident.span()=>
+                    quote_spanned! {span=>
                         #ident: <#ty as ::fayalite::ty::StaticType>::MASK_TYPE,
                     }
                 }));
-            let type_properties = format_ident!("__type_properties", span = ident.span());
+            let type_properties = format_ident!("__type_properties", span = span);
             let type_properties_fields = Vec::from_iter(fields.named().into_iter().zip(field_flips).map(|(field, field_flip)| {
-                let ident: &Ident = field.ident().as_ref().unwrap();
                 let flipped = field_flip.is_some();
                 let ty = field.ty();
-                quote_spanned! {ident.span()=>
+                quote_spanned! {span=>
                     let #type_properties = #type_properties.field(#flipped, <#ty as ::fayalite::ty::StaticType>::TYPE_PROPERTIES);
                 }
             }));
             let type_properties_mask_fields = Vec::from_iter(fields.named().into_iter().zip(field_flips).map(|(field, field_flip)| {
-                let ident: &Ident = field.ident().as_ref().unwrap();
                 let flipped = field_flip.is_some();
                 let ty = field.ty();
-                quote_spanned! {ident.span()=>
+                quote_spanned! {span=>
                     let #type_properties = #type_properties.field(#flipped, <#ty as ::fayalite::ty::StaticType>::MASK_TYPE_PROPERTIES);
                 }
             }));
-            quote_spanned! {ident.span()=>
+            quote_spanned! {span=>
                 #[automatically_derived]
                 impl #static_impl_generics ::fayalite::ty::StaticType for #mask_type_ident #static_type_generics
                 #static_where_clause
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
index 50fb138..adddd74 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
@@ -204,6 +204,7 @@ impl ToTokens for ParsedEnum {
             variants,
             match_variant_ident,
         } = self;
+        let span = ident.span();
         let ItemOptions {
             outline_generated: _,
             target,
@@ -213,8 +214,8 @@ impl ToTokens for ParsedEnum {
         } = &options.body;
         let target = get_target(target, ident);
         let mut struct_attrs = attrs.clone();
-        struct_attrs.push(common_derives(ident.span()));
-        struct_attrs.push(parse_quote_spanned! {ident.span()=>
+        struct_attrs.push(common_derives(span));
+        struct_attrs.push(parse_quote_spanned! {span=>
             #[allow(non_snake_case)]
         });
         let struct_fields = Punctuated::from_iter(variants.pairs().map_pair_value_ref(
@@ -238,8 +239,8 @@ impl ToTokens for ParsedEnum {
                     colon_token = Token![:](paren_token.span.open());
                     ty.clone().into()
                 } else {
-                    colon_token = Token![:](ident.span());
-                    parse_quote_spanned! {ident.span()=>
+                    colon_token = Token![:](span);
+                    parse_quote_spanned! {span=>
                         ()
                     }
                 };
@@ -282,30 +283,30 @@ impl ToTokens for ParsedEnum {
                         }) = field
                         {
                             let expr = ty.make_hdl_type_expr(context);
-                            quote_spanned! {ident.span()=>
+                            quote_spanned! {span=>
                                 #ident: #expr,
                             }
                         } else {
-                            quote_spanned! {ident.span()=>
+                            quote_spanned! {span=>
                                 #ident: (),
                             }
                         }
                     })
                     .collect();
-                parse_quote_spanned! {ident.span()=>
+                parse_quote_spanned! {span=>
                     #target {
                         #(#fields)*
                     }
                 }
             })
         }
-        let mut wrapped_in_const = WrappedInConst::new(tokens, ident.span());
+        let mut wrapped_in_const = WrappedInConst::new(tokens, span);
         let tokens = wrapped_in_const.inner();
         {
-            let mut wrapped_in_const = WrappedInConst::new(tokens, ident.span());
+            let mut wrapped_in_const = WrappedInConst::new(tokens, span);
             let tokens = wrapped_in_const.inner();
             let mut enum_attrs = attrs.clone();
-            enum_attrs.push(parse_quote_spanned! {ident.span()=>
+            enum_attrs.push(parse_quote_spanned! {span=>
                 #[allow(dead_code)]
             });
             ItemEnum {
@@ -354,7 +355,7 @@ impl ToTokens for ParsedEnum {
             .to_tokens(tokens);
         }
         let mut enum_attrs = attrs.clone();
-        enum_attrs.push(parse_quote_spanned! {ident.span()=>
+        enum_attrs.push(parse_quote_spanned! {span=>
             #[allow(dead_code, non_camel_case_types)]
         });
         ItemEnum {
@@ -389,7 +390,7 @@ impl ToTokens for ParsedEnum {
                                     mutability: FieldMutability::None,
                                     ident: None,
                                     colon_token: None,
-                                    ty: parse_quote_spanned! {ident.span()=>
+                                    ty: parse_quote_spanned! {span=>
                                         ::fayalite::expr::Expr<#ty>
                                     },
                                 },
@@ -403,21 +404,22 @@ impl ToTokens for ParsedEnum {
             )),
         }
         .to_tokens(tokens);
+        let self_token = Token![self](span);
         for (index, ParsedVariant { ident, field, .. }) in variants.iter().enumerate() {
             if let Some(ParsedVariantField { ty, .. }) = field {
-                quote_spanned! {ident.span()=>
+                quote_spanned! {span=>
                     #[automatically_derived]
                     impl #impl_generics #target #type_generics
                     #where_clause
                     {
                         #[allow(non_snake_case, dead_code)]
                         #vis fn #ident<__V: ::fayalite::expr::ToExpr<Type = #ty>>(
-                            self,
+                            #self_token,
                             v: __V,
                         ) -> ::fayalite::expr::Expr<Self> {
                             ::fayalite::expr::ToExpr::to_expr(
                                 &::fayalite::expr::ops::EnumLiteral::new_by_index(
-                                    self,
+                                    #self_token,
                                     #index,
                                     ::fayalite::__std::option::Option::Some(
                                         ::fayalite::expr::Expr::canonical(
@@ -430,16 +432,16 @@ impl ToTokens for ParsedEnum {
                     }
                 }
             } else {
-                quote_spanned! {ident.span()=>
+                quote_spanned! {span=>
                     #[automatically_derived]
                     impl #impl_generics #target #type_generics
                     #where_clause
                     {
                         #[allow(non_snake_case, dead_code)]
-                        #vis fn #ident(self) -> ::fayalite::expr::Expr<Self> {
+                        #vis fn #ident(#self_token) -> ::fayalite::expr::Expr<Self> {
                             ::fayalite::expr::ToExpr::to_expr(
                                 &::fayalite::expr::ops::EnumLiteral::new_by_index(
-                                    self,
+                                    #self_token,
                                     #index,
                                     ::fayalite::__std::option::Option::None,
                                 ),
@@ -450,46 +452,48 @@ impl ToTokens for ParsedEnum {
             }
             .to_tokens(tokens);
         }
+        let variants_token = Ident::new("variants", span);
         let from_canonical_body_fields = Vec::from_iter(variants.iter().enumerate().map(
             |(index, ParsedVariant { ident, field, .. })| {
                 let ident_str = ident.to_string();
                 let val = if field.is_some() {
                     let missing_value_msg = format!("expected variant {ident} to have a field");
-                    quote_spanned! {ident.span()=>
+                    quote_spanned! {span=>
                         ::fayalite::ty::Type::from_canonical(ty.expect(#missing_value_msg))
                     }
                 } else {
-                    quote_spanned! {ident.span()=>
+                    quote_spanned! {span=>
                         ::fayalite::__std::assert!(ty.is_none());
                     }
                 };
-                quote_spanned! {ident.span()=>
+                quote_spanned! {span=>
                     #ident: {
                         let ::fayalite::enum_::EnumVariant {
                             name,
                             ty,
-                        } = variants[#index];
+                        } = #variants_token[#index];
                         ::fayalite::__std::assert_eq!(&*name, #ident_str);
                         #val
                     },
                 }
             },
         ));
+        let variant_access_token = Ident::new("variant_access", span);
         let match_active_scope_match_arms = Vec::from_iter(variants.iter().enumerate().map(
             |(index, ParsedVariant { ident, field, .. })| {
                 if field.is_some() {
-                    quote_spanned! {ident.span()=>
+                    quote_spanned! {span=>
                         #index => #match_variant_ident::#ident(
                             ::fayalite::expr::ToExpr::to_expr(
                                 &::fayalite::expr::ops::VariantAccess::new_by_index(
-                                    variant_access.base(),
-                                    variant_access.variant_index(),
+                                    #variant_access_token.base(),
+                                    #variant_access_token.variant_index(),
                                 ),
                             ),
                         ),
                     }
                 } else {
-                    quote_spanned! {ident.span()=>
+                    quote_spanned! {span=>
                         #index => #match_variant_ident::#ident,
                     }
                 }
@@ -507,16 +511,16 @@ impl ToTokens for ParsedEnum {
                 match field {
                     Some(ParsedVariantField { options, .. }) => {
                         let FieldOptions {} = options.body;
-                        quote_spanned! {ident.span()=>
+                        quote_spanned! {span=>
                             ::fayalite::enum_::EnumVariant {
                                 name: ::fayalite::intern::Intern::intern(#ident_str),
                                 ty: ::fayalite::__std::option::Option::Some(
-                                    ::fayalite::ty::Type::canonical(&self.#ident),
+                                    ::fayalite::ty::Type::canonical(&#self_token.#ident),
                                 ),
                             },
                         }
                     }
-                    None => quote_spanned! {ident.span()=>
+                    None => quote_spanned! {span=>
                         ::fayalite::enum_::EnumVariant {
                             name: ::fayalite::intern::Intern::intern(#ident_str),
                             ty: ::fayalite::__std::option::Option::None,
@@ -526,7 +530,7 @@ impl ToTokens for ParsedEnum {
             },
         ));
         let variants_len = variants.len();
-        quote_spanned! {ident.span()=>
+        quote_spanned! {span=>
             #[automatically_derived]
             impl #impl_generics ::fayalite::ty::Type for #target #type_generics
             #where_clause
@@ -544,11 +548,11 @@ impl ToTokens for ParsedEnum {
                 ) -> <Self as ::fayalite::ty::Type>::MatchVariantsIter {
                     ::fayalite::module::enum_match_variants_helper(this, source_location)
                 }
-                fn mask_type(&self) -> <Self as ::fayalite::ty::Type>::MaskType {
+                fn mask_type(&#self_token) -> <Self as ::fayalite::ty::Type>::MaskType {
                     ::fayalite::int::Bool
                 }
-                fn canonical(&self) -> ::fayalite::ty::CanonicalType {
-                    ::fayalite::ty::CanonicalType::Enum(::fayalite::enum_::Enum::new(::fayalite::enum_::EnumType::variants(self)))
+                fn canonical(&#self_token) -> ::fayalite::ty::CanonicalType {
+                    ::fayalite::ty::CanonicalType::Enum(::fayalite::enum_::Enum::new(::fayalite::enum_::EnumType::variants(#self_token)))
                 }
                 #[track_caller]
                 #[allow(non_snake_case)]
@@ -556,8 +560,8 @@ impl ToTokens for ParsedEnum {
                     let ::fayalite::ty::CanonicalType::Enum(enum_) = canonical_type else {
                         ::fayalite::__std::panic!("expected enum");
                     };
-                    let variants = ::fayalite::enum_::EnumType::variants(&enum_);
-                    ::fayalite::__std::assert_eq!(variants.len(), #variants_len, "enum has wrong number of variants");
+                    let #variants_token = ::fayalite::enum_::EnumType::variants(&enum_);
+                    ::fayalite::__std::assert_eq!(#variants_token.len(), #variants_len, "enum has wrong number of variants");
                     Self {
                         #(#from_canonical_body_fields)*
                     }
@@ -573,16 +577,16 @@ impl ToTokens for ParsedEnum {
                 fn match_activate_scope(
                     v: <Self as ::fayalite::ty::Type>::MatchVariantAndInactiveScope,
                 ) -> (<Self as ::fayalite::ty::Type>::MatchVariant, <Self as ::fayalite::ty::Type>::MatchActiveScope) {
-                    let (variant_access, scope) = v.activate();
+                    let (#variant_access_token, scope) = v.activate();
                     (
-                        match variant_access.variant_index() {
+                        match #variant_access_token.variant_index() {
                             #(#match_active_scope_match_arms)*
                             #variants_len.. => ::fayalite::__std::panic!("invalid variant index"),
                         },
                         scope,
                     )
                 }
-                fn variants(&self) -> ::fayalite::intern::Interned<[::fayalite::enum_::EnumVariant]> {
+                fn variants(&#self_token) -> ::fayalite::intern::Interned<[::fayalite::enum_::EnumVariant]> {
                     ::fayalite::intern::Intern::intern(&[
                         #(#variants_body_variants)*
                     ][..])
@@ -597,34 +601,34 @@ impl ToTokens for ParsedEnum {
             let static_type_body_variants =
                 Vec::from_iter(variants.iter().map(|ParsedVariant { ident, field, .. }| {
                     if let Some(_) = field {
-                        quote_spanned! {ident.span()=>
+                        quote_spanned! {span=>
                             #ident: ::fayalite::ty::StaticType::TYPE,
                         }
                     } else {
-                        quote_spanned! {ident.span()=>
+                        quote_spanned! {span=>
                             #ident: (),
                         }
                     }
                 }));
-            let type_properties = format_ident!("__type_properties", span = ident.span());
+            let type_properties = format_ident!("__type_properties", span = span);
             let type_properties_variants =
-                Vec::from_iter(variants.iter().map(|ParsedVariant { ident, field, .. }| {
+                Vec::from_iter(variants.iter().map(|ParsedVariant { field, .. }| {
                     let variant = if let Some(ParsedVariantField { ty, .. }) = field {
-                        quote_spanned! {ident.span()=>
+                        quote_spanned! {span=>
                             ::fayalite::__std::option::Option::Some(
                                 <#ty as ::fayalite::ty::StaticType>::TYPE_PROPERTIES,
                             )
                         }
                     } else {
-                        quote_spanned! {ident.span()=>
+                        quote_spanned! {span=>
                             ::fayalite::__std::option::Option::None
                         }
                     };
-                    quote_spanned! {ident.span()=>
+                    quote_spanned! {span=>
                         let #type_properties = #type_properties.variant(#variant);
                     }
                 }));
-            quote_spanned! {ident.span()=>
+            quote_spanned! {span=>
                 #[automatically_derived]
                 impl #static_impl_generics ::fayalite::ty::StaticType
                 for #target #static_type_generics
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
index efbe7f3..e7561fe 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
@@ -1896,6 +1896,7 @@ pub(crate) mod known_items {
     impl_known_item!(::fayalite::array::ArrayType);
     impl_known_item!(::fayalite::bundle::BundleType);
     impl_known_item!(::fayalite::enum_::EnumType);
+    impl_known_item!(::fayalite::int::BoolOrIntType);
     impl_known_item!(::fayalite::int::DynSize);
     impl_known_item!(::fayalite::int::IntType);
     impl_known_item!(::fayalite::int::KnownSize);
@@ -2085,6 +2086,7 @@ macro_rules! impl_bounds {
 impl_bounds! {
     #[struct = ParsedBounds]
     pub(crate) enum ParsedBound {
+        BoolOrIntType,
         BundleType,
         EnumType,
         IntType,
@@ -2098,6 +2100,7 @@ impl_bounds! {
 impl_bounds! {
     #[struct = ParsedTypeBounds]
     pub(crate) enum ParsedTypeBound {
+        BoolOrIntType,
         BundleType,
         EnumType,
         IntType,
@@ -2109,6 +2112,7 @@ impl_bounds! {
 impl From<ParsedTypeBound> for ParsedBound {
     fn from(value: ParsedTypeBound) -> Self {
         match value {
+            ParsedTypeBound::BoolOrIntType(v) => ParsedBound::BoolOrIntType(v),
             ParsedTypeBound::BundleType(v) => ParsedBound::BundleType(v),
             ParsedTypeBound::EnumType(v) => ParsedBound::EnumType(v),
             ParsedTypeBound::IntType(v) => ParsedBound::IntType(v),
@@ -2121,6 +2125,7 @@ impl From<ParsedTypeBound> for ParsedBound {
 impl From<ParsedTypeBounds> for ParsedBounds {
     fn from(value: ParsedTypeBounds) -> Self {
         let ParsedTypeBounds {
+            BoolOrIntType,
             BundleType,
             EnumType,
             IntType,
@@ -2128,6 +2133,7 @@ impl From<ParsedTypeBounds> for ParsedBounds {
             Type,
         } = value;
         Self {
+            BoolOrIntType,
             BundleType,
             EnumType,
             IntType,
@@ -2143,6 +2149,10 @@ impl ParsedTypeBound {
     fn implied_bounds(self) -> ParsedTypeBounds {
         let span = self.span();
         match self {
+            Self::BoolOrIntType(v) => ParsedTypeBounds::from_iter([
+                ParsedTypeBound::from(v),
+                ParsedTypeBound::Type(known_items::Type(span)),
+            ]),
             Self::BundleType(v) => ParsedTypeBounds::from_iter([
                 ParsedTypeBound::from(v),
                 ParsedTypeBound::Type(known_items::Type(span)),
@@ -2153,6 +2163,7 @@ impl ParsedTypeBound {
             ]),
             Self::IntType(v) => ParsedTypeBounds::from_iter([
                 ParsedTypeBound::from(v),
+                ParsedTypeBound::BoolOrIntType(known_items::BoolOrIntType(span)),
                 ParsedTypeBound::Type(known_items::Type(span)),
             ]),
             Self::StaticType(v) => ParsedTypeBounds::from_iter([
@@ -2185,6 +2196,7 @@ impl From<ParsedSizeTypeBounds> for ParsedBounds {
     fn from(value: ParsedSizeTypeBounds) -> Self {
         let ParsedSizeTypeBounds { KnownSize, Size } = value;
         Self {
+            BoolOrIntType: None,
             BundleType: None,
             EnumType: None,
             IntType: None,
@@ -2260,6 +2272,7 @@ pub(crate) enum ParsedBoundCategory {
 impl ParsedBound {
     fn categorize(self) -> ParsedBoundCategory {
         match self {
+            Self::BoolOrIntType(v) => ParsedBoundCategory::Type(ParsedTypeBound::BoolOrIntType(v)),
             Self::BundleType(v) => ParsedBoundCategory::Type(ParsedTypeBound::BundleType(v)),
             Self::EnumType(v) => ParsedBoundCategory::Type(ParsedTypeBound::EnumType(v)),
             Self::IntType(v) => ParsedBoundCategory::Type(ParsedTypeBound::IntType(v)),
@@ -2575,6 +2588,7 @@ impl ParsedGenerics {
                 }
             })
             .collect();
+        let param_token = Ident::new("__param", ident.span());
         for (param_count, (generics_accumulation_type, next_param)) in generics_accumulation_types
             .iter()
             .zip(&self.params)
@@ -2623,7 +2637,7 @@ impl ParsedGenerics {
                         next_generics.split_for_impl();
                     let next_turbofish = next_type_generics.as_turbofish();
                     let mut param: Expr = parse_quote_spanned! {ident.span()=>
-                        __param
+                        #param_token
                     };
                     let mut generics = next_generics.clone();
                     let mut index_type = param_ident.clone();
@@ -2638,7 +2652,7 @@ impl ParsedGenerics {
                             is_const: false,
                         });
                         param = parse_quote_spanned! {ident.span()=>
-                            ::fayalite::ty::TypeOrDefault::get(__param, || #default_expr)
+                            ::fayalite::ty::TypeOrDefault::get(#param_token, || #default_expr)
                         };
                         let context = MakeHdlTypeExprContext {
                             named_param_values: self_members[..param_count]
@@ -2703,7 +2717,7 @@ impl ParsedGenerics {
                         {
                             type Output = #next_target #next_type_generics;
 
-                            fn index(&self, __param: #index_type) -> &Self::Output {
+                            fn index(&self, #param_token: #index_type) -> &Self::Output {
                                 ::fayalite::intern::Interned::<_>::into_inner(
                                     ::fayalite::intern::Intern::intern_sized(#output_expr),
                                 )
@@ -2724,7 +2738,7 @@ impl ParsedGenerics {
                                 .iter()
                                 .cloned()
                                 .chain([parse_quote_spanned! {ident.span()=>
-                                    __param
+                                    #param_token
                                 }])
                                 .collect(),
                             is_const: false,
@@ -2763,7 +2777,7 @@ impl ParsedGenerics {
                             {
                                 type Output = #next_target #next_target_args;
 
-                                fn index(&self, __param: #param_ident) -> &Self::Output {
+                                fn index(&self, #param_token: #param_ident) -> &Self::Output {
                                     ::fayalite::intern::Interned::<_>::into_inner(
                                         ::fayalite::intern::Intern::intern_sized(#output_expr),
                                     )
@@ -2791,7 +2805,7 @@ impl ParsedGenerics {
                             .iter()
                             .cloned()
                             .chain([parse_quote_spanned! {ident.span()=>
-                                __param
+                                #param_token
                             }])
                             .collect(),
                         is_const: false,
@@ -2833,7 +2847,7 @@ impl ParsedGenerics {
                         {
                             type Output = #next_target #next_target_args;
 
-                            fn index(&self, __param: __Param) -> &Self::Output {
+                            fn index(&self, #param_token: __Param) -> &Self::Output {
                                 ::fayalite::intern::Interned::<_>::into_inner(
                                     ::fayalite::intern::Intern::intern_sized(#output_expr),
                                 )
@@ -3145,16 +3159,21 @@ impl ParsedGenerics {
                                 .Type
                                 .get_or_insert_with(|| known_items::Type(bound.span()));
                             match bound {
-                                ParsedTypeBound::BundleType(_)
+                                ParsedTypeBound::BoolOrIntType(_)
+                                | ParsedTypeBound::BundleType(_)
                                 | ParsedTypeBound::EnumType(_)
                                 | ParsedTypeBound::IntType(_) => {
                                     errors.error(bound, "bound on mask type not implemented");
                                 }
                                 ParsedTypeBound::StaticType(bound) => {
                                     if bounds.StaticType.is_none() {
-                                        errors.error(bound, "StaticType bound on mask type without corresponding StaticType bound on original type is not implemented");
+                                        errors.error(
+                                            bound,
+                                            "StaticType bound on mask type without corresponding \
+                                            StaticType bound on original type is not implemented",
+                                        );
                                     }
-                                },
+                                }
                                 ParsedTypeBound::Type(_) => {}
                             }
                         }
diff --git a/crates/fayalite/src/ty.rs b/crates/fayalite/src/ty.rs
index c7081eb..380d2e6 100644
--- a/crates/fayalite/src/ty.rs
+++ b/crates/fayalite/src/ty.rs
@@ -210,7 +210,9 @@ impl sealed::BaseTypeSealed for CanonicalType {}
 
 impl BaseType for CanonicalType {}
 
-pub trait TypeOrDefault<D: Type>: sealed::TypeOrDefaultSealed {
+pub trait TypeOrDefault<D: Type>:
+    sealed::TypeOrDefaultSealed + Copy + Eq + Hash + fmt::Debug
+{
     type Type: Type;
     fn get<F: FnOnce() -> D>(self, default: F) -> Self::Type;
 }
diff --git a/crates/fayalite/tests/hdl_types.rs b/crates/fayalite/tests/hdl_types.rs
index d043013..3f11de3 100644
--- a/crates/fayalite/tests/hdl_types.rs
+++ b/crates/fayalite/tests/hdl_types.rs
@@ -29,3 +29,69 @@ pub enum E<T> {
 pub struct S2<T = ()> {
     pub v: E<T>,
 }
+
+// check that #[hdl] properly handles hygiene
+macro_rules! types_in_macros {
+    ($a:ident, $b:ident, $c:ident, $d:ident, $e:ident, $f:ident, $A:ident, $B:ident, $C:ident, $D:ident, $E:ident, $F:ident) => {
+        #[hdl]
+        struct $F {}
+        #[hdl]
+        struct $A<$B, $C: Size, const $D: usize, $E = $F> {
+            $a: $B,
+            $b: UIntType<$C>,
+            $c: SInt<$D>,
+            $d: HdlOption<$E>,
+            $e: $E,
+            $f: $F,
+        }
+        #[allow(non_camel_case_types)]
+        #[hdl]
+        enum $B<$C: Size, const $D: usize, $E = $F> {
+            $a($A<(), $C, $D, $E>),
+            $b(UIntType<$C>),
+            $c(SInt<$D>),
+            $d,
+            $e($E),
+            $f($F),
+        }
+    };
+    // ensure every identifier has different hygiene
+    () => {
+        types_in_macros!(a);
+    };
+    ($a:ident) => {
+        types_in_macros!($a, b);
+    };
+    ($a:ident, $b:ident) => {
+        types_in_macros!($a, $b, c);
+    };
+    ($a:ident, $b:ident, $c:ident) => {
+        types_in_macros!($a, $b, $c, d);
+    };
+    ($a:ident, $b:ident, $c:ident, $d:ident) => {
+        types_in_macros!($a, $b, $c, $d, e);
+    };
+    ($a:ident, $b:ident, $c:ident, $d:ident, $e:ident) => {
+        types_in_macros!($a, $b, $c, $d, $e, f);
+    };
+    ($a:ident, $b:ident, $c:ident, $d:ident, $e:ident, $f:ident) => {
+        types_in_macros!($a, $b, $c, $d, $e, $f, A);
+    };
+    ($a:ident, $b:ident, $c:ident, $d:ident, $e:ident, $f:ident, $A:ident) => {
+        types_in_macros!($a, $b, $c, $d, $e, $f, $A, B);
+    };
+    ($a:ident, $b:ident, $c:ident, $d:ident, $e:ident, $f:ident, $A:ident, $B:ident) => {
+        types_in_macros!($a, $b, $c, $d, $e, $f, $A, $B, C);
+    };
+    ($a:ident, $b:ident, $c:ident, $d:ident, $e:ident, $f:ident, $A:ident, $B:ident, $C:ident) => {
+        types_in_macros!($a, $b, $c, $d, $e, $f, $A, $B, $C, D);
+    };
+    ($a:ident, $b:ident, $c:ident, $d:ident, $e:ident, $f:ident, $A:ident, $B:ident, $C:ident, $D:ident) => {
+        types_in_macros!($a, $b, $c, $d, $e, $f, $A, $B, $C, $D, E);
+    };
+    ($a:ident, $b:ident, $c:ident, $d:ident, $e:ident, $f:ident, $A:ident, $B:ident, $C:ident, $D:ident, $E:ident) => {
+        types_in_macros!($a, $b, $c, $d, $e, $f, $A, $B, $C, $D, $E, F);
+    };
+}
+
+types_in_macros!();

From 0d54b9a2a9abd7c8b34566ae6e55ca0d508c6a21 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 3 Oct 2024 23:07:14 -0700
Subject: [PATCH 046/190] queue formal proof passes!

---
 crates/fayalite/src/cli.rs              |   2 +-
 crates/fayalite/src/formal.rs           |  70 +++++++++-
 crates/fayalite/src/prelude.rs          |   5 +-
 crates/fayalite/src/testing.rs          |   4 +-
 crates/fayalite/src/util/ready_valid.rs | 170 +++++++++++++++---------
 crates/fayalite/tests/module.rs         |  18 +--
 6 files changed, 183 insertions(+), 86 deletions(-)

diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index b0b818c..f1d69d2 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -516,7 +516,7 @@ impl FormalArgs {
         std::fs::write(&sby_file, self.sby_contents(&output)?)?;
         let mut cmd = process::Command::new(&self.sby);
         cmd.arg("-f");
-        cmd.arg(sby_file);
+        cmd.arg(sby_file.file_name().unwrap());
         cmd.args(&self.sby_extra_args);
         cmd.current_dir(&output.verilog.firrtl.output_dir);
         let status = self.verilog.firrtl.base.run_external_command(cmd)?;
diff --git a/crates/fayalite/src/formal.rs b/crates/fayalite/src/formal.rs
index eab1969..17d3122 100644
--- a/crates/fayalite/src/formal.rs
+++ b/crates/fayalite/src/formal.rs
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use crate::{
-    intern::{Intern, Interned},
+    int::BoolOrIntType,
+    intern::{Intern, Interned, Memoize},
     prelude::*,
 };
 use std::sync::OnceLock;
@@ -172,12 +173,7 @@ pub fn formal_reset() -> Expr<SyncReset> {
         m.annotate_module(BlackBoxInlineAnnotation {
             path: "fayalite_formal_reset.v".intern(),
             text: r"module __fayalite_formal_reset(output rst);
-    reg rst;
-    (* gclk *)
-    reg gclk;
-    initial rst = 1;
-    always @(posedge gclk)
-        rst <= 0;
+    assign rst = $initstate;
 endmodule
 "
             .intern(),
@@ -189,3 +185,63 @@ endmodule
     let formal_reset = instance(*MOD.get_or_init(formal_reset));
     formal_reset.rst
 }
+
+macro_rules! make_any_const_fn {
+    ($ident:ident, $verilog_attribute:literal) => {
+        #[hdl]
+        pub fn $ident<T: BoolOrIntType>(ty: T) -> Expr<T> {
+            #[hdl_module(extern)]
+            pub(super) fn $ident<T: BoolOrIntType>(ty: T) {
+                #[hdl]
+                let out: T = m.output(ty);
+                let width = ty.width();
+                let verilog_bitslice = if width == 1 {
+                    String::new()
+                } else {
+                    format!(" [{}:0]", width - 1)
+                };
+                m.annotate_module(BlackBoxInlineAnnotation {
+                    path: Intern::intern_owned(format!(
+                        "fayalite_{}_{width}.v",
+                        stringify!($ident),
+                    )),
+                    text: Intern::intern_owned(format!(
+                        r"module __fayalite_{}_{width}(output{verilog_bitslice} out);
+    (* {} *)
+    reg{verilog_bitslice} out;
+endmodule
+",
+                        stringify!($ident),
+                        $verilog_attribute,
+                    )),
+                });
+                m.verilog_name(format!("__fayalite_{}_{width}", stringify!($ident)));
+            }
+            #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+            struct TheMemoize<T>(T);
+            impl<T: BoolOrIntType> Memoize for TheMemoize<T> {
+                type Input = ();
+                type InputOwned = ();
+                type Output = Option<Interned<Module<$ident<T>>>>;
+                fn inner(self, _input: &Self::Input) -> Self::Output {
+                    if self.0.width() == 0 {
+                        None
+                    } else {
+                        Some($ident(self.0))
+                    }
+                }
+            }
+            let Some(module) = TheMemoize(ty).get_owned(()) else {
+                return 0_hdl_u0.cast_bits_to(ty);
+            };
+            #[hdl]
+            let $ident = instance(module);
+            $ident.out
+        }
+    };
+}
+
+make_any_const_fn!(any_const, "anyconst");
+make_any_const_fn!(any_seq, "anyseq");
+make_any_const_fn!(all_const, "allconst");
+make_any_const_fn!(all_seq, "allseq");
diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs
index f1a9736..46d9e6e 100644
--- a/crates/fayalite/src/prelude.rs
+++ b/crates/fayalite/src/prelude.rs
@@ -14,8 +14,9 @@ pub use crate::{
         ReduceBits, ToExpr,
     },
     formal::{
-        formal_global_clock, formal_reset, hdl_assert, hdl_assert_with_enable, hdl_assume,
-        hdl_assume_with_enable, hdl_cover, hdl_cover_with_enable, MakeFormalExpr,
+        all_const, all_seq, any_const, any_seq, formal_global_clock, formal_reset, hdl_assert,
+        hdl_assert_with_enable, hdl_assume, hdl_assume_with_enable, hdl_cover,
+        hdl_cover_with_enable, MakeFormalExpr,
     },
     hdl, hdl_module,
     int::{Bool, DynSize, KnownSize, SInt, SIntType, Size, UInt, UIntType},
diff --git a/crates/fayalite/src/testing.rs b/crates/fayalite/src/testing.rs
index 07252f1..4517e34 100644
--- a/crates/fayalite/src/testing.rs
+++ b/crates/fayalite/src/testing.rs
@@ -68,7 +68,6 @@ fn get_assert_formal_target_path(test_name: &dyn std::fmt::Display) -> PathBuf {
         },
     );
     let mut dir = String::with_capacity(64);
-    write!(dir, "{simple_hash:08x}-").unwrap();
     for ch in Path::new(file)
         .file_stem()
         .unwrap_or_default()
@@ -84,6 +83,7 @@ fn get_assert_formal_target_path(test_name: &dyn std::fmt::Display) -> PathBuf {
             _ => '_',
         });
     }
+    write!(dir, "-{simple_hash:08x}").unwrap();
     let index = *DIRS
         .lock()
         .unwrap()
@@ -91,7 +91,7 @@ fn get_assert_formal_target_path(test_name: &dyn std::fmt::Display) -> PathBuf {
         .entry_ref(&dir)
         .and_modify(|v| *v += 1)
         .or_insert(0);
-    write!(dir, ".{index}").unwrap();
+    write!(dir, "-{index}").unwrap();
     get_cargo_target_dir()
         .join("fayalite_assert_formal")
         .join(dir)
diff --git a/crates/fayalite/src/util/ready_valid.rs b/crates/fayalite/src/util/ready_valid.rs
index 41299a6..f3d5653 100644
--- a/crates/fayalite/src/util/ready_valid.rs
+++ b/crates/fayalite/src/util/ready_valid.rs
@@ -49,7 +49,6 @@ impl<T: Type> ReadyValid<T> {
     }
 }
 
-// TODO: needs testing
 #[hdl_module]
 pub fn queue<T: Type>(
     ty: T,
@@ -134,7 +133,7 @@ pub fn queue<T: Type>(
     #[hdl]
     if inp_fire {
         #[hdl]
-        if inp_index.cmp_eq(capacity) {
+        if inp_index.cmp_eq(capacity.get() - 1) {
             connect_any(inp_index, 0_hdl_u0);
         } else {
             connect_any(inp_index, inp_index + 1_hdl_u1);
@@ -144,7 +143,7 @@ pub fn queue<T: Type>(
     #[hdl]
     if out_fire {
         #[hdl]
-        if out_index.cmp_eq(capacity) {
+        if out_index.cmp_eq(capacity.get() - 1) {
             connect_any(out_index, 0_hdl_u0);
         } else {
             connect_any(out_index, out_index + 1_hdl_u1);
@@ -153,10 +152,12 @@ pub fn queue<T: Type>(
 
     #[hdl]
     if indexes_equal {
-        connect(
-            count,
-            maybe_full.cast_to_static::<UInt<1>>() << (count_ty.width() - 1),
-        );
+        #[hdl]
+        if maybe_full {
+            connect_any(count, capacity);
+        } else {
+            connect_any(count, 0_hdl_u0);
+        }
     } else {
         if capacity.is_power_of_two() {
             debug_assert_eq!(count_ty.width(), index_ty.width() + 1);
@@ -182,6 +183,7 @@ mod tests {
     use crate::{
         cli::FormalMode, firrtl::ExportOptions,
         module::transform::simplify_enums::SimplifyEnumsKind, testing::assert_formal,
+        ty::StaticType,
     };
     use std::num::NonZero;
 
@@ -190,8 +192,8 @@ mod tests {
         assert_formal(
             format_args!("test_queue_{capacity}_{inp_ready_is_comb}_{out_valid_is_comb}"),
             queue_test(capacity, inp_ready_is_comb, out_valid_is_comb),
-            FormalMode::BMC,
-            20,
+            FormalMode::Prove,
+            14,
             None,
             ExportOptions {
                 simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
@@ -200,12 +202,6 @@ mod tests {
         );
         #[hdl_module]
         fn queue_test(capacity: NonZeroUsize, inp_ready_is_comb: bool, out_valid_is_comb: bool) {
-            #[hdl]
-            let inp_data: HdlOption<UInt<8>> = m.input();
-            #[hdl]
-            let out_ready: Bool = m.input();
-            #[hdl]
-            let start_check: Bool = m.input();
             #[hdl]
             let clk: Clock = m.input();
             #[hdl]
@@ -219,6 +215,24 @@ mod tests {
                 },
             );
             #[hdl]
+            let inp_data: HdlOption<UInt<8>> = wire();
+            #[hdl]
+            if any_seq(Bool) {
+                connect(inp_data, HdlSome(any_seq(UInt::<8>::TYPE)));
+            } else {
+                connect(inp_data, HdlNone());
+            }
+            #[hdl]
+            let out_ready: Bool = wire();
+            connect(out_ready, any_seq(Bool));
+            let index_ty: UInt<32> = UInt::TYPE;
+            #[hdl]
+            let index_to_check = wire();
+            connect(index_to_check, any_const(index_ty));
+            let index_max = !index_ty.zero();
+            // we saturate at index_max, so only check indexes where we properly maintain position
+            hdl_assume(clk, index_to_check.cmp_ne(index_max), "");
+            #[hdl]
             let dut = instance(queue(
                 UInt[ConstUsize::<8>],
                 capacity,
@@ -228,63 +242,97 @@ mod tests {
             connect(dut.cd, cd);
             connect(dut.inp.data, inp_data);
             connect(dut.out.ready, out_ready);
+            hdl_assume(
+                clk,
+                index_to_check.cmp_ne(!Expr::ty(index_to_check).zero()),
+                "",
+            );
+
             #[hdl]
-            let count = reg_builder().clock_domain(cd).reset(0u32);
+            let expected_count = reg_builder().clock_domain(cd).reset(0u32);
             #[hdl]
-            let next_count = wire();
-            connect(next_count, count);
-            connect(count, next_count);
+            let next_expected_count = wire();
+            connect(next_expected_count, expected_count);
+            connect(expected_count, next_expected_count);
             #[hdl]
             if ReadyValid::fire(dut.inp) & !ReadyValid::fire(dut.out) {
-                connect_any(next_count, count + 1u8);
+                connect_any(next_expected_count, expected_count + 1u8);
             } else if !ReadyValid::fire(dut.inp) & ReadyValid::fire(dut.out) {
-                connect_any(next_count, count - 1u8);
+                connect_any(next_expected_count, expected_count - 1u8);
             }
-            hdl_assert(cd.clk, count.cmp_eq(dut.count), "");
+            hdl_assert(cd.clk, expected_count.cmp_eq(dut.count), "");
+
             #[hdl]
-            let started_check = reg_builder().clock_domain(cd).reset(false);
+            let prev_out_ready = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
+            connect_any(
+                prev_out_ready,
+                (prev_out_ready << 1) | out_ready.cast_to(UInt[1]),
+            );
             #[hdl]
-            let steps_till_output = reg_builder().clock_domain(cd).reset(0u32);
+            let prev_inp_valid = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
+            connect_any(
+                prev_inp_valid,
+                (prev_inp_valid << 1) | HdlOption::is_some(inp_data).cast_to(UInt[1]),
+            );
+            hdl_assume(clk, (prev_out_ready & prev_inp_valid).cmp_ne(0u8), "");
+
             #[hdl]
-            let expected_output = reg_builder().clock_domain(cd).reset(HdlNone());
+            let inp_index = reg_builder().clock_domain(cd).reset(index_ty.zero());
             #[hdl]
-            if start_check & !started_check {
+            let stored_inp_data = reg_builder().clock_domain(cd).reset(0u8);
+
+            #[hdl]
+            if let HdlSome(data) = ReadyValid::fire_data(dut.inp) {
                 #[hdl]
-                if let HdlSome(inp) = ReadyValid::fire_data(dut.inp) {
-                    connect(started_check, true);
-                    connect_any(
-                        steps_till_output,
-                        count + (!ReadyValid::fire(dut.out)).cast_to(UInt[1]),
-                    );
-                    connect(expected_output, HdlSome(inp));
-                }
-            } else if started_check & steps_till_output.cmp_ne(0u32) & ReadyValid::fire(dut.out) {
-                connect_any(steps_till_output, steps_till_output - 1u32);
-            }
-            #[hdl]
-            let stored_output = reg_builder().clock_domain(cd).reset(HdlNone());
-            #[hdl]
-            if let HdlSome(out) = ReadyValid::fire_data(dut.out) {
-                #[hdl]
-                if (start_check & !started_check) | (started_check & steps_till_output.cmp_ne(0u32))
-                {
-                    connect(stored_output, HdlSome(out));
-                }
-            }
-            #[hdl]
-            if started_check & steps_till_output.cmp_eq(0u32) {
-                #[hdl]
-                if let HdlSome(expected_output) = expected_output {
+                if inp_index.cmp_lt(index_max) {
+                    connect_any(inp_index, inp_index + 1u8);
                     #[hdl]
-                    if let HdlSome(stored_output) = stored_output {
-                        hdl_assert(cd.clk, stored_output.cmp_eq(expected_output), "");
-                    } else {
-                        hdl_assert(cd.clk, false.to_expr(), "");
+                    if inp_index.cmp_eq(index_to_check) {
+                        connect(stored_inp_data, data);
                     }
-                } else {
-                    hdl_assert(cd.clk, false.to_expr(), "");
                 }
             }
+
+            #[hdl]
+            if inp_index.cmp_lt(index_to_check) {
+                hdl_assert(clk, stored_inp_data.cmp_eq(0u8), "");
+            }
+
+            #[hdl]
+            let out_index = reg_builder().clock_domain(cd).reset(index_ty.zero());
+            #[hdl]
+            let stored_out_data = reg_builder().clock_domain(cd).reset(0u8);
+
+            #[hdl]
+            if let HdlSome(data) = ReadyValid::fire_data(dut.out) {
+                #[hdl]
+                if out_index.cmp_lt(index_max) {
+                    connect_any(out_index, out_index + 1u8);
+                    #[hdl]
+                    if out_index.cmp_eq(index_to_check) {
+                        connect(stored_out_data, data);
+                    }
+                }
+            }
+
+            #[hdl]
+            if out_index.cmp_lt(index_to_check) {
+                hdl_assert(clk, stored_out_data.cmp_eq(0u8), "");
+            }
+
+            hdl_assert(clk, inp_index.cmp_ge(out_index), "");
+
+            #[hdl]
+            if inp_index.cmp_lt(index_max) & out_index.cmp_lt(index_max) {
+                hdl_assert(clk, expected_count.cmp_eq(inp_index - out_index), "");
+            } else {
+                hdl_assert(clk, expected_count.cmp_ge(inp_index - out_index), "");
+            }
+
+            #[hdl]
+            if inp_index.cmp_gt(index_to_check) & out_index.cmp_gt(index_to_check) {
+                hdl_assert(clk, stored_inp_data.cmp_eq(stored_out_data), "");
+            }
         }
     }
 
@@ -328,49 +376,41 @@ mod tests {
         test_queue(NonZero::new(2).unwrap(), true, true);
     }
 
-    #[cfg(todo)]
     #[test]
     fn test_3_false_false() {
         test_queue(NonZero::new(3).unwrap(), false, false);
     }
 
-    #[cfg(todo)]
     #[test]
     fn test_3_false_true() {
         test_queue(NonZero::new(3).unwrap(), false, true);
     }
 
-    #[cfg(todo)]
     #[test]
     fn test_3_true_false() {
         test_queue(NonZero::new(3).unwrap(), true, false);
     }
 
-    #[cfg(todo)]
     #[test]
     fn test_3_true_true() {
         test_queue(NonZero::new(3).unwrap(), true, true);
     }
 
-    #[cfg(todo)]
     #[test]
     fn test_4_false_false() {
         test_queue(NonZero::new(4).unwrap(), false, false);
     }
 
-    #[cfg(todo)]
     #[test]
     fn test_4_false_true() {
         test_queue(NonZero::new(4).unwrap(), false, true);
     }
 
-    #[cfg(todo)]
     #[test]
     fn test_4_true_false() {
         test_queue(NonZero::new(4).unwrap(), true, false);
     }
 
-    #[cfg(todo)]
     #[test]
     fn test_4_true_true() {
         test_queue(NonZero::new(4).unwrap(), true, true);
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 7d12739..0d690f2 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -3394,7 +3394,7 @@ circuit check_formal: %[[
   {
     "class": "firrtl.transforms.BlackBoxInlineAnno",
     "name": "fayalite_formal_reset.v",
-    "text": "module __fayalite_formal_reset(output rst);\n    reg rst;\n    (* gclk *)\n    reg gclk;\n    initial rst = 1;\n    always @(posedge gclk)\n        rst <= 0;\nendmodule\n",
+    "text": "module __fayalite_formal_reset(output rst);\n    assign rst = $initstate;\nendmodule\n",
     "target": "~check_formal|formal_reset"
   }
 ]]
@@ -3407,20 +3407,20 @@ circuit check_formal: %[[
         input pred1: UInt<1> @[module-XXXXXXXXXX.rs 6:1]
         input pred2: UInt<1> @[module-XXXXXXXXXX.rs 7:1]
         input pred3: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
-        inst formal_reset of formal_reset @[formal.rs 189:24]
+        inst formal_reset of formal_reset @[formal.rs 185:24]
         assert(clk, pred1, and(en1, not(formal_reset.rst)), "en check 1") @[module-XXXXXXXXXX.rs 9:1]
-        inst formal_reset_1 of formal_reset @[formal.rs 189:24]
+        inst formal_reset_1 of formal_reset @[formal.rs 185:24]
         assume(clk, pred2, and(en2, not(formal_reset_1.rst)), "en check 2") @[module-XXXXXXXXXX.rs 10:1]
-        inst formal_reset_2 of formal_reset @[formal.rs 189:24]
+        inst formal_reset_2 of formal_reset @[formal.rs 185:24]
         cover(clk, pred3, and(en3, not(formal_reset_2.rst)), "en check 3") @[module-XXXXXXXXXX.rs 11:1]
-        inst formal_reset_3 of formal_reset @[formal.rs 189:24]
+        inst formal_reset_3 of formal_reset @[formal.rs 185:24]
         assert(clk, pred1, and(UInt<1>(0h1), not(formal_reset_3.rst)), "check 1") @[module-XXXXXXXXXX.rs 12:1]
-        inst formal_reset_4 of formal_reset @[formal.rs 189:24]
+        inst formal_reset_4 of formal_reset @[formal.rs 185:24]
         assume(clk, pred2, and(UInt<1>(0h1), not(formal_reset_4.rst)), "check 2") @[module-XXXXXXXXXX.rs 13:1]
-        inst formal_reset_5 of formal_reset @[formal.rs 189:24]
+        inst formal_reset_5 of formal_reset @[formal.rs 185:24]
         cover(clk, pred3, and(UInt<1>(0h1), not(formal_reset_5.rst)), "check 3") @[module-XXXXXXXXXX.rs 14:1]
-    extmodule formal_reset: @[formal.rs 168:5]
-        output rst: UInt<1> @[formal.rs 171:32]
+    extmodule formal_reset: @[formal.rs 169:5]
+        output rst: UInt<1> @[formal.rs 172:32]
         defname = __fayalite_formal_reset
 "#,
     };

From 9f154e6b9619a081b94628cacecffbdc2504c25f Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 3 Oct 2024 23:36:39 -0700
Subject: [PATCH 047/190] try caching ccache manually

---
 .forgejo/workflows/test.yml | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index 83d291b..962449e 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -34,8 +34,13 @@ jobs:
             tcl-dev \
             z3 \
             zlib1g-dev \
-      - name: ccache
-        uses: https://github.com/hendrikmuhs/ccache-action@v1
+      - name: Cache ccache dir
+        uses: https://code.forgejo.org/actions/checkout@v3
+        with:
+          path: ~/.ccache
+          key: ${{ runner.os }}-${{ github.sha }}
+          restore-keys: |
+            ${{ runner.os }}-
       - run: |
           export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
           echo "$PATH" >> "$GITHUB_PATH"

From c0d4de56a9756fecc6e9d4a66017258304363018 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 3 Oct 2024 23:40:44 -0700
Subject: [PATCH 048/190] try to make yosys build faster

---
 .forgejo/workflows/test.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index 962449e..4cbd5f2 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -53,8 +53,8 @@ jobs:
           make -C sby install
       - run: |
           git clone --depth=1 --recursive --branch=0.45 https://github.com/YosysHQ/yosys.git
-          cd yosys
-          make install -j6
+          make -C yosys -j$(nproc)
+          make -C yosys install
       - run: |
           wget -O firrtl.tar.gz https://github.com/llvm/circt/releases/download/firtool-1.86.0/firrtl-bin-linux-x64.tar.gz
           sha256sum -c - <<<'bf6f4ab18ae76f135c944efbd81e25391c31c1bd0617c58ab0592640abefee14  firrtl.tar.gz'

From 487af0715413be3cbd99cfa343e46749599c4cbb Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 4 Oct 2024 01:03:17 -0700
Subject: [PATCH 049/190] yosys build runs out of memory

---
 .forgejo/workflows/test.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index 4cbd5f2..ef58281 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -53,7 +53,7 @@ jobs:
           make -C sby install
       - run: |
           git clone --depth=1 --recursive --branch=0.45 https://github.com/YosysHQ/yosys.git
-          make -C yosys -j$(nproc)
+          make -C yosys -j2
           make -C yosys install
       - run: |
           wget -O firrtl.tar.gz https://github.com/llvm/circt/releases/download/firtool-1.86.0/firrtl-bin-linux-x64.tar.gz

From b7f11011643f4e4ab5fc32c9ddab6aa6eb726060 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 4 Oct 2024 17:03:51 -0700
Subject: [PATCH 050/190] reduce parallelism to fit within the number of
 available cpus even when running sby in prove mode (which likes to run 2 smt
 solvers in parallel)

---
 crates/fayalite/src/cli.rs | 182 +++++++++++++++++++++++++++++++++----
 1 file changed, 162 insertions(+), 20 deletions(-)

diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index f1d69d2..fa1b247 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -17,8 +17,10 @@ use std::{
     ffi::OsString,
     fmt::{self, Write},
     fs, io, mem,
+    num::NonZeroUsize,
     path::{Path, PathBuf},
     process,
+    sync::{Condvar, Mutex, OnceLock},
 };
 use tempfile::TempDir;
 
@@ -46,9 +48,109 @@ impl From<io::Error> for CliError {
     }
 }
 
+#[derive(Debug)]
+pub struct AcquiredJob {
+    job_count: NonZeroUsize,
+}
+
+impl Drop for AcquiredJob {
+    fn drop(&mut self) {
+        Self::change_job_count(Some(self.job_count), None);
+    }
+}
+
+impl AcquiredJob {
+    pub fn max_available_job_count() -> NonZeroUsize {
+        static RETVAL: OnceLock<NonZeroUsize> = OnceLock::new();
+        *RETVAL.get_or_init(|| {
+            std::thread::available_parallelism().unwrap_or(NonZeroUsize::new(1).unwrap())
+        })
+    }
+    fn change_job_count(released: Option<NonZeroUsize>, acquired: Option<NonZeroUsize>) {
+        static AVAILABLE_JOB_COUNT: OnceLock<Mutex<usize>> = OnceLock::new();
+        static COND_VAR: Condvar = Condvar::new();
+        let mut available_job_count_lock = AVAILABLE_JOB_COUNT
+            .get_or_init(|| Mutex::new(Self::max_available_job_count().get()))
+            .lock()
+            .unwrap();
+        if let Some(released) = released {
+            *available_job_count_lock = available_job_count_lock
+                .checked_add(released.get())
+                .expect("tried to release too many jobs");
+            COND_VAR.notify_all();
+        }
+        if let Some(acquired) = acquired {
+            loop {
+                match available_job_count_lock.checked_sub(acquired.get()) {
+                    Some(jobs_left) => {
+                        *available_job_count_lock = jobs_left;
+                        break;
+                    }
+                    None => {
+                        available_job_count_lock = COND_VAR.wait(available_job_count_lock).unwrap()
+                    }
+                }
+            }
+        }
+    }
+    pub fn job_count(&self) -> NonZeroUsize {
+        self.job_count
+    }
+    pub fn increase_job_count<R>(
+        &mut self,
+        new_minimum_count: NonZeroUsize,
+        f: impl FnOnce(&mut AcquiredJob) -> R,
+    ) -> R {
+        if new_minimum_count <= self.job_count {
+            return f(self);
+        }
+        struct ReleaseOnDrop<'a> {
+            acquired_job: &'a mut AcquiredJob,
+            old_job_count: NonZeroUsize,
+        }
+        impl Drop for ReleaseOnDrop<'_> {
+            fn drop(&mut self) {
+                AcquiredJob::change_job_count(
+                    NonZeroUsize::new(self.acquired_job.job_count.get() - self.old_job_count.get()),
+                    None,
+                );
+                self.acquired_job.job_count = self.old_job_count;
+            }
+        }
+        let release_on_drop = ReleaseOnDrop {
+            old_job_count: self.job_count,
+            acquired_job: self,
+        };
+        // release our current jobs when acquiring new jobs to avoid deadlock
+        Self::change_job_count(Some(release_on_drop.old_job_count), Some(new_minimum_count));
+        release_on_drop.acquired_job.job_count = new_minimum_count;
+        let retval = f(release_on_drop.acquired_job);
+        drop(release_on_drop);
+        retval
+    }
+    pub fn acquire_jobs(job_count: NonZeroUsize) -> Self {
+        Self::change_job_count(None, Some(job_count));
+        Self { job_count }
+    }
+    pub fn run_command<R>(
+        &mut self,
+        mut cmd: std::process::Command,
+        f: impl FnOnce(&mut std::process::Command) -> std::io::Result<R>,
+    ) -> std::io::Result<R> {
+        // TODO: if we implement a make job server, add the proper env vars to cmd
+        f(&mut cmd)
+    }
+}
+
 pub trait RunPhase<Arg> {
     type Output;
-    fn run(&self, arg: Arg) -> Result<Self::Output>;
+    fn run(&self, arg: Arg) -> Result<Self::Output> {
+        self.run_with_job(
+            arg,
+            &mut AcquiredJob::acquire_jobs(NonZeroUsize::new(1).unwrap()),
+        )
+    }
+    fn run_with_job(&self, arg: Arg, acquired_job: &mut AcquiredJob) -> Result<Self::Output>;
 }
 
 #[derive(Parser, Debug, Clone)]
@@ -93,6 +195,7 @@ impl BaseArgs {
     /// handles possibly redirecting the command's output for Rust tests
     pub fn run_external_command(
         &self,
+        _acquired_job: &mut AcquiredJob,
         mut command: process::Command,
     ) -> io::Result<process::ExitStatus> {
         if self.redirect_output_for_rust_test {
@@ -150,7 +253,11 @@ impl FirrtlOutput {
 }
 
 impl FirrtlArgs {
-    fn run_impl(&self, top_module: Module<Bundle>) -> Result<FirrtlOutput> {
+    fn run_impl(
+        &self,
+        top_module: Module<Bundle>,
+        _acquired_job: &mut AcquiredJob,
+    ) -> Result<FirrtlOutput> {
         let (file_backend, temp_dir) = self.base.make_firrtl_file_backend()?;
         let firrtl::FileBackend {
             top_fir_file_stem,
@@ -170,15 +277,23 @@ impl FirrtlArgs {
 
 impl<T: BundleType> RunPhase<Module<T>> for FirrtlArgs {
     type Output = FirrtlOutput;
-    fn run(&self, top_module: Module<T>) -> Result<Self::Output> {
-        self.run_impl(top_module.canonical())
+    fn run_with_job(
+        &self,
+        top_module: Module<T>,
+        acquired_job: &mut AcquiredJob,
+    ) -> Result<Self::Output> {
+        self.run_impl(top_module.canonical(), acquired_job)
     }
 }
 
 impl<T: BundleType> RunPhase<Interned<Module<T>>> for FirrtlArgs {
     type Output = FirrtlOutput;
-    fn run(&self, top_module: Interned<Module<T>>) -> Result<Self::Output> {
-        self.run(*top_module)
+    fn run_with_job(
+        &self,
+        top_module: Interned<Module<T>>,
+        acquired_job: &mut AcquiredJob,
+    ) -> Result<Self::Output> {
+        self.run_with_job(*top_module, acquired_job)
     }
 }
 
@@ -298,7 +413,11 @@ impl VerilogArgs {
         }
         Ok(output)
     }
-    fn run_impl(&self, firrtl_output: FirrtlOutput) -> Result<VerilogOutput> {
+    fn run_impl(
+        &self,
+        firrtl_output: FirrtlOutput,
+        acquired_job: &mut AcquiredJob,
+    ) -> Result<VerilogOutput> {
         let Self {
             firrtl,
             firtool,
@@ -323,7 +442,7 @@ impl VerilogArgs {
         }
         cmd.args(firtool_extra_args);
         cmd.current_dir(&output.firrtl.output_dir);
-        let status = firrtl.base.run_external_command(cmd)?;
+        let status = firrtl.base.run_external_command(acquired_job, cmd)?;
         if status.success() {
             self.process_unadjusted_verilog_file(output)
         } else {
@@ -340,9 +459,9 @@ where
     FirrtlArgs: RunPhase<Arg, Output = FirrtlOutput>,
 {
     type Output = VerilogOutput;
-    fn run(&self, arg: Arg) -> Result<Self::Output> {
-        let firrtl_output = self.firrtl.run(arg)?;
-        self.run_impl(firrtl_output)
+    fn run_with_job(&self, arg: Arg, acquired_job: &mut AcquiredJob) -> Result<Self::Output> {
+        let firrtl_output = self.firrtl.run_with_job(arg, acquired_job)?;
+        self.run_impl(firrtl_output, acquired_job)
     }
 }
 
@@ -365,6 +484,14 @@ impl FormalMode {
             FormalMode::Cover => "cover",
         }
     }
+    fn needs_extra_job(self) -> bool {
+        match self {
+            FormalMode::BMC => false,
+            FormalMode::Prove => true,
+            FormalMode::Live => false,
+            FormalMode::Cover => false,
+        }
+    }
 }
 
 impl fmt::Display for FormalMode {
@@ -508,7 +635,11 @@ impl FormalArgs {
         writeln!(retval, "prep -top {top_module}").unwrap();
         Ok(retval)
     }
-    fn run_impl(&self, verilog_output: VerilogOutput) -> Result<FormalOutput> {
+    fn run_impl(
+        &self,
+        verilog_output: VerilogOutput,
+        acquired_job: &mut AcquiredJob,
+    ) -> Result<FormalOutput> {
         let output = FormalOutput {
             verilog: verilog_output,
         };
@@ -519,7 +650,18 @@ impl FormalArgs {
         cmd.arg(sby_file.file_name().unwrap());
         cmd.args(&self.sby_extra_args);
         cmd.current_dir(&output.verilog.firrtl.output_dir);
-        let status = self.verilog.firrtl.base.run_external_command(cmd)?;
+        let new_minimum_count = if self.mode.needs_extra_job() {
+            NonZeroUsize::new(2).unwrap()
+        } else {
+            NonZeroUsize::new(1).unwrap()
+        };
+        let new_minimum_count = AcquiredJob::max_available_job_count().min(new_minimum_count);
+        let status = acquired_job.increase_job_count(new_minimum_count, |acquired_job| {
+            self.verilog
+                .firrtl
+                .base
+                .run_external_command(acquired_job, cmd)
+        })?;
         if status.success() {
             Ok(output)
         } else {
@@ -536,9 +678,9 @@ where
     VerilogArgs: RunPhase<Arg, Output = VerilogOutput>,
 {
     type Output = FormalOutput;
-    fn run(&self, arg: Arg) -> Result<Self::Output> {
-        let verilog_output = self.verilog.run(arg)?;
-        self.run_impl(verilog_output)
+    fn run_with_job(&self, arg: Arg, acquired_job: &mut AcquiredJob) -> Result<Self::Output> {
+        let verilog_output = self.verilog.run_with_job(arg, acquired_job)?;
+        self.run_impl(verilog_output, acquired_job)
     }
 }
 
@@ -627,16 +769,16 @@ where
     FirrtlArgs: RunPhase<T, Output = FirrtlOutput>,
 {
     type Output = ();
-    fn run(&self, arg: T) -> Result<Self::Output> {
+    fn run_with_job(&self, arg: T, acquired_job: &mut AcquiredJob) -> Result<Self::Output> {
         match &self.subcommand {
             CliCommand::Firrtl(c) => {
-                c.run(arg)?;
+                c.run_with_job(arg, acquired_job)?;
             }
             CliCommand::Verilog(c) => {
-                c.run(arg)?;
+                c.run_with_job(arg, acquired_job)?;
             }
             CliCommand::Formal(c) => {
-                c.run(arg)?;
+                c.run_with_job(arg, acquired_job)?;
             }
         }
         Ok(())

From ec77559e2b9d2460674082ec5be3691381028991 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 4 Oct 2024 17:10:06 -0700
Subject: [PATCH 051/190] fix cache action name

---
 .forgejo/workflows/test.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index ef58281..68ded33 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -35,7 +35,7 @@ jobs:
             z3 \
             zlib1g-dev \
       - name: Cache ccache dir
-        uses: https://code.forgejo.org/actions/checkout@v3
+        uses: https://code.forgejo.org/actions/cache@v3
         with:
           path: ~/.ccache
           key: ${{ runner.os }}-${{ github.sha }}

From e05c3686880e8d0d433356d866bd6e38a26dd8fc Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 6 Oct 2024 18:50:09 -0700
Subject: [PATCH 052/190] change register names to end in `_reg` by convention

---
 crates/fayalite/examples/blinky.rs            |   8 +-
 .../hdl_let_statements/registers.rs           |   9 +-
 crates/fayalite/src/util/ready_valid.rs       | 125 ++++++++++--------
 crates/fayalite/tests/module.rs               |  14 +-
 4 files changed, 87 insertions(+), 69 deletions(-)

diff --git a/crates/fayalite/examples/blinky.rs b/crates/fayalite/examples/blinky.rs
index 94c7910..87b77c1 100644
--- a/crates/fayalite/examples/blinky.rs
+++ b/crates/fayalite/examples/blinky.rs
@@ -17,15 +17,15 @@ fn blinky(clock_frequency: u64) {
     let max_value = clock_frequency / 2 - 1;
     let int_ty = UInt::range_inclusive(0..=max_value);
     #[hdl]
-    let counter: UInt = reg_builder().clock_domain(cd).reset(0u8.cast_to(int_ty));
+    let counter_reg: UInt = reg_builder().clock_domain(cd).reset(0u8.cast_to(int_ty));
     #[hdl]
     let output_reg: Bool = reg_builder().clock_domain(cd).reset(false);
     #[hdl]
-    if counter.cmp_eq(max_value) {
-        connect_any(counter, 0u8);
+    if counter_reg.cmp_eq(max_value) {
+        connect_any(counter_reg, 0u8);
         connect(output_reg, !output_reg);
     } else {
-        connect_any(counter, counter + 1_hdl_u1);
+        connect_any(counter_reg, counter_reg + 1_hdl_u1);
     }
     #[hdl]
     let led: Bool = m.output();
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/registers.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/registers.rs
index 5a81c5b..2876389 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/registers.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/registers.rs
@@ -9,6 +9,9 @@
 //!
 //! Registers follow [connection semantics], which are unlike assignments in software, so you should read it.
 //!
+//! By convention, register names end in `_reg` -- this helps you tell which values are written
+//! immediately or on the next clock edge when connecting to them.
+//!
 //! ```
 //! # use fayalite::prelude::*;
 //! # #[hdl_module]
@@ -18,11 +21,11 @@
 //! #[hdl]
 //! let cd: ClockDomain = m.input();
 //! #[hdl]
-//! let my_register: UInt<8> = reg_builder().clock_domain(cd).reset(8_hdl_u8);
+//! let my_reg: UInt<8> = reg_builder().clock_domain(cd).reset(8_hdl_u8);
 //! #[hdl]
 //! if v {
-//!     // my_register is only changed when both `v` is set and `cd`'s clock edge occurs.
-//!     connect(my_register, 0x45_hdl_u8);
+//!     // my_reg is only changed when both `v` is set and `cd`'s clock edge occurs.
+//!     connect(my_reg, 0x45_hdl_u8);
 //! }
 //! # }
 //! ```
diff --git a/crates/fayalite/src/util/ready_valid.rs b/crates/fayalite/src/util/ready_valid.rs
index f3d5653..4fe480d 100644
--- a/crates/fayalite/src/util/ready_valid.rs
+++ b/crates/fayalite/src/util/ready_valid.rs
@@ -69,11 +69,11 @@ pub fn queue<T: Type>(
     let count: UInt = m.output(count_ty);
 
     #[hdl]
-    let inp_index = reg_builder().clock_domain(cd).reset(0.cast_to(index_ty));
+    let inp_index_reg = reg_builder().clock_domain(cd).reset(0.cast_to(index_ty));
     #[hdl]
-    let out_index = reg_builder().clock_domain(cd).reset(0.cast_to(index_ty));
+    let out_index_reg = reg_builder().clock_domain(cd).reset(0.cast_to(index_ty));
     #[hdl]
-    let maybe_full = reg_builder().clock_domain(cd).reset(false);
+    let maybe_full_reg = reg_builder().clock_domain(cd).reset(false);
 
     #[hdl]
     let mut mem = memory(ty);
@@ -89,18 +89,18 @@ pub fn queue<T: Type>(
     connect(out_fire, ReadyValid::fire(out));
     #[hdl]
     let indexes_equal: Bool = wire();
-    connect(indexes_equal, inp_index.cmp_eq(out_index));
+    connect(indexes_equal, inp_index_reg.cmp_eq(out_index_reg));
     #[hdl]
     let empty: Bool = wire();
-    connect(empty, indexes_equal & !maybe_full);
+    connect(empty, indexes_equal & !maybe_full_reg);
     #[hdl]
     let full: Bool = wire();
-    connect(full, indexes_equal & maybe_full);
+    connect(full, indexes_equal & maybe_full_reg);
 
-    connect(read_port.addr, out_index);
+    connect(read_port.addr, out_index_reg);
     connect(read_port.en, true);
     connect(read_port.clk, cd.clk);
-    connect(write_port.addr, inp_index);
+    connect(write_port.addr, inp_index_reg);
     connect(write_port.en, inp_fire);
     connect(write_port.clk, cd.clk);
     connect(write_port.data, HdlOption::unwrap_or(inp.data, ty.uninit()));
@@ -127,33 +127,33 @@ pub fn queue<T: Type>(
 
     #[hdl]
     if inp_fire.cmp_ne(out_fire) {
-        connect(maybe_full, inp_fire);
+        connect(maybe_full_reg, inp_fire);
     }
 
     #[hdl]
     if inp_fire {
         #[hdl]
-        if inp_index.cmp_eq(capacity.get() - 1) {
-            connect_any(inp_index, 0_hdl_u0);
+        if inp_index_reg.cmp_eq(capacity.get() - 1) {
+            connect_any(inp_index_reg, 0_hdl_u0);
         } else {
-            connect_any(inp_index, inp_index + 1_hdl_u1);
+            connect_any(inp_index_reg, inp_index_reg + 1_hdl_u1);
         }
     }
 
     #[hdl]
     if out_fire {
         #[hdl]
-        if out_index.cmp_eq(capacity.get() - 1) {
-            connect_any(out_index, 0_hdl_u0);
+        if out_index_reg.cmp_eq(capacity.get() - 1) {
+            connect_any(out_index_reg, 0_hdl_u0);
         } else {
-            connect_any(out_index, out_index + 1_hdl_u1);
+            connect_any(out_index_reg, out_index_reg + 1_hdl_u1);
         }
     }
 
     #[hdl]
     if indexes_equal {
         #[hdl]
-        if maybe_full {
+        if maybe_full_reg {
             connect_any(count, capacity);
         } else {
             connect_any(count, 0_hdl_u0);
@@ -163,15 +163,18 @@ pub fn queue<T: Type>(
             debug_assert_eq!(count_ty.width(), index_ty.width() + 1);
             #[hdl]
             let count_lower = wire(index_ty);
-            connect(count_lower, (inp_index - out_index).cast_to(index_ty)); // wrap
+            connect(
+                count_lower,
+                (inp_index_reg - out_index_reg).cast_to(index_ty),
+            ); // wrap
             connect(count, count_lower.cast_to(count_ty));
         } else {
             debug_assert_eq!(count_ty.width(), index_ty.width());
             #[hdl]
-            if inp_index.cmp_lt(out_index) {
-                connect(count, inp_index + capacity - out_index);
+            if inp_index_reg.cmp_lt(out_index_reg) {
+                connect(count, inp_index_reg + capacity - out_index_reg);
             } else {
-                connect(count, inp_index - out_index);
+                connect(count, inp_index_reg - out_index_reg);
             }
         }
     }
@@ -249,89 +252,101 @@ mod tests {
             );
 
             #[hdl]
-            let expected_count = reg_builder().clock_domain(cd).reset(0u32);
+            let expected_count_reg = reg_builder().clock_domain(cd).reset(0u32);
             #[hdl]
             let next_expected_count = wire();
-            connect(next_expected_count, expected_count);
-            connect(expected_count, next_expected_count);
+            connect(next_expected_count, expected_count_reg);
+            connect(expected_count_reg, next_expected_count);
             #[hdl]
             if ReadyValid::fire(dut.inp) & !ReadyValid::fire(dut.out) {
-                connect_any(next_expected_count, expected_count + 1u8);
+                connect_any(next_expected_count, expected_count_reg + 1u8);
             } else if !ReadyValid::fire(dut.inp) & ReadyValid::fire(dut.out) {
-                connect_any(next_expected_count, expected_count - 1u8);
+                connect_any(next_expected_count, expected_count_reg - 1u8);
             }
-            hdl_assert(cd.clk, expected_count.cmp_eq(dut.count), "");
+            hdl_assert(cd.clk, expected_count_reg.cmp_eq(dut.count), "");
 
             #[hdl]
-            let prev_out_ready = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
+            let prev_out_ready_reg = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
             connect_any(
-                prev_out_ready,
-                (prev_out_ready << 1) | out_ready.cast_to(UInt[1]),
+                prev_out_ready_reg,
+                (prev_out_ready_reg << 1) | out_ready.cast_to(UInt[1]),
             );
             #[hdl]
-            let prev_inp_valid = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
+            let prev_inp_valid_reg = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
             connect_any(
-                prev_inp_valid,
-                (prev_inp_valid << 1) | HdlOption::is_some(inp_data).cast_to(UInt[1]),
+                prev_inp_valid_reg,
+                (prev_inp_valid_reg << 1) | HdlOption::is_some(inp_data).cast_to(UInt[1]),
+            );
+            hdl_assume(
+                clk,
+                (prev_out_ready_reg & prev_inp_valid_reg).cmp_ne(0u8),
+                "",
             );
-            hdl_assume(clk, (prev_out_ready & prev_inp_valid).cmp_ne(0u8), "");
 
             #[hdl]
-            let inp_index = reg_builder().clock_domain(cd).reset(index_ty.zero());
+            let inp_index_reg = reg_builder().clock_domain(cd).reset(index_ty.zero());
             #[hdl]
-            let stored_inp_data = reg_builder().clock_domain(cd).reset(0u8);
+            let stored_inp_data_reg = reg_builder().clock_domain(cd).reset(0u8);
 
             #[hdl]
             if let HdlSome(data) = ReadyValid::fire_data(dut.inp) {
                 #[hdl]
-                if inp_index.cmp_lt(index_max) {
-                    connect_any(inp_index, inp_index + 1u8);
+                if inp_index_reg.cmp_lt(index_max) {
+                    connect_any(inp_index_reg, inp_index_reg + 1u8);
                     #[hdl]
-                    if inp_index.cmp_eq(index_to_check) {
-                        connect(stored_inp_data, data);
+                    if inp_index_reg.cmp_eq(index_to_check) {
+                        connect(stored_inp_data_reg, data);
                     }
                 }
             }
 
             #[hdl]
-            if inp_index.cmp_lt(index_to_check) {
-                hdl_assert(clk, stored_inp_data.cmp_eq(0u8), "");
+            if inp_index_reg.cmp_lt(index_to_check) {
+                hdl_assert(clk, stored_inp_data_reg.cmp_eq(0u8), "");
             }
 
             #[hdl]
-            let out_index = reg_builder().clock_domain(cd).reset(index_ty.zero());
+            let out_index_reg = reg_builder().clock_domain(cd).reset(index_ty.zero());
             #[hdl]
-            let stored_out_data = reg_builder().clock_domain(cd).reset(0u8);
+            let stored_out_data_reg = reg_builder().clock_domain(cd).reset(0u8);
 
             #[hdl]
             if let HdlSome(data) = ReadyValid::fire_data(dut.out) {
                 #[hdl]
-                if out_index.cmp_lt(index_max) {
-                    connect_any(out_index, out_index + 1u8);
+                if out_index_reg.cmp_lt(index_max) {
+                    connect_any(out_index_reg, out_index_reg + 1u8);
                     #[hdl]
-                    if out_index.cmp_eq(index_to_check) {
-                        connect(stored_out_data, data);
+                    if out_index_reg.cmp_eq(index_to_check) {
+                        connect(stored_out_data_reg, data);
                     }
                 }
             }
 
             #[hdl]
-            if out_index.cmp_lt(index_to_check) {
-                hdl_assert(clk, stored_out_data.cmp_eq(0u8), "");
+            if out_index_reg.cmp_lt(index_to_check) {
+                hdl_assert(clk, stored_out_data_reg.cmp_eq(0u8), "");
             }
 
-            hdl_assert(clk, inp_index.cmp_ge(out_index), "");
+            hdl_assert(clk, inp_index_reg.cmp_ge(out_index_reg), "");
 
             #[hdl]
-            if inp_index.cmp_lt(index_max) & out_index.cmp_lt(index_max) {
-                hdl_assert(clk, expected_count.cmp_eq(inp_index - out_index), "");
+            if inp_index_reg.cmp_lt(index_max) & out_index_reg.cmp_lt(index_max) {
+                hdl_assert(
+                    clk,
+                    expected_count_reg.cmp_eq(inp_index_reg - out_index_reg),
+                    "",
+                );
             } else {
-                hdl_assert(clk, expected_count.cmp_ge(inp_index - out_index), "");
+                hdl_assert(
+                    clk,
+                    expected_count_reg.cmp_ge(inp_index_reg - out_index_reg),
+                    "",
+                );
             }
 
             #[hdl]
-            if inp_index.cmp_gt(index_to_check) & out_index.cmp_gt(index_to_check) {
-                hdl_assert(clk, stored_inp_data.cmp_eq(stored_out_data), "");
+            if inp_index_reg.cmp_gt(index_to_check) & out_index_reg.cmp_gt(index_to_check) {
+                hdl_assert(clk, stored_inp_data_reg.cmp_eq(stored_out_data_reg), "");
             }
         }
     }
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 0d690f2..69438f2 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -41,13 +41,13 @@ pub fn my_module(width: usize) {
     #[hdl]
     let m2 = instance(module2());
     #[hdl]
-    let r: UInt<8> = reg_builder().clock_domain(clock_domain).reset(8_hdl_u8);
+    let r_reg: UInt<8> = reg_builder().clock_domain(clock_domain).reset(8_hdl_u8);
     connect(m2.i, i);
-    connect(r, m2.o);
+    connect(r_reg, m2.o);
     connect(
         o,
         #[hdl]
-        [r, r, b'\r'_hdl],
+        [r_reg, r_reg, b'\r'_hdl],
     );
     connect(o[1], 30_hdl_u8);
     connect(o2, i2);
@@ -109,12 +109,12 @@ circuit my_module:
         connect _bundle_literal_expr.`1`, SInt<5>(-0h3)
         connect o3, _bundle_literal_expr @[module-XXXXXXXXXX.rs 12:1]
         inst m2 of module2 @[module-XXXXXXXXXX.rs 13:1]
-        regreset r: UInt<8>, clock_domain.clk, clock_domain.rst, UInt<8>(0h8) @[module-XXXXXXXXXX.rs 14:1]
+        regreset r_reg: UInt<8>, clock_domain.clk, clock_domain.rst, UInt<8>(0h8) @[module-XXXXXXXXXX.rs 14:1]
         connect m2.i, i @[module-XXXXXXXXXX.rs 15:1]
-        connect r, m2.o @[module-XXXXXXXXXX.rs 16:1]
+        connect r_reg, m2.o @[module-XXXXXXXXXX.rs 16:1]
         wire _array_literal_expr: UInt<8>[3]
-        connect _array_literal_expr[0], r
-        connect _array_literal_expr[1], r
+        connect _array_literal_expr[0], r_reg
+        connect _array_literal_expr[1], r_reg
         connect _array_literal_expr[2], UInt<8>(0hD)
         connect o, _array_literal_expr @[module-XXXXXXXXXX.rs 17:1]
         connect o[1], UInt<8>(0h1E) @[module-XXXXXXXXXX.rs 18:1]

From 2e8b73d2fc8c0161deb56da86ef1cd2679978607 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 6 Oct 2024 19:04:48 -0700
Subject: [PATCH 053/190] rename fire/fire_data to firing/firing_data

---
 crates/fayalite/src/util/ready_valid.rs | 46 ++++++++++++-------------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/crates/fayalite/src/util/ready_valid.rs b/crates/fayalite/src/util/ready_valid.rs
index 4fe480d..82d3f1e 100644
--- a/crates/fayalite/src/util/ready_valid.rs
+++ b/crates/fayalite/src/util/ready_valid.rs
@@ -12,28 +12,28 @@ pub struct ReadyValid<T> {
 
 impl<T: Type> ReadyValid<T> {
     #[hdl]
-    pub fn fire(expr: Expr<Self>) -> Expr<Bool> {
+    pub fn firing(expr: Expr<Self>) -> Expr<Bool> {
         #[hdl]
-        let fire: Bool = wire();
+        let firing: Bool = wire();
         #[hdl]
         match expr.data {
-            HdlNone => connect(fire, false),
-            HdlSome(_) => connect(fire, expr.ready),
+            HdlNone => connect(firing, false),
+            HdlSome(_) => connect(firing, expr.ready),
         }
-        fire
+        firing
     }
     #[hdl]
-    pub fn fire_data(expr: impl ToExpr<Type = Self>) -> Expr<HdlOption<T>> {
+    pub fn firing_data(expr: impl ToExpr<Type = Self>) -> Expr<HdlOption<T>> {
         let expr = expr.to_expr();
         let option_ty = Expr::ty(expr).data;
         #[hdl]
-        let fire_data = wire(option_ty);
-        connect(fire_data, option_ty.HdlNone());
+        let firing_data = wire(option_ty);
+        connect(firing_data, option_ty.HdlNone());
         #[hdl]
         if expr.ready {
-            connect(fire_data, expr.data);
+            connect(firing_data, expr.data);
         }
-        fire_data
+        firing_data
     }
     #[hdl]
     pub fn map<R: Type>(
@@ -82,11 +82,11 @@ pub fn queue<T: Type>(
     let write_port = mem.new_write_port();
 
     #[hdl]
-    let inp_fire: Bool = wire();
-    connect(inp_fire, ReadyValid::fire(inp));
+    let inp_firing: Bool = wire();
+    connect(inp_firing, ReadyValid::firing(inp));
     #[hdl]
-    let out_fire: Bool = wire();
-    connect(out_fire, ReadyValid::fire(out));
+    let out_firing: Bool = wire();
+    connect(out_firing, ReadyValid::firing(out));
     #[hdl]
     let indexes_equal: Bool = wire();
     connect(indexes_equal, inp_index_reg.cmp_eq(out_index_reg));
@@ -101,7 +101,7 @@ pub fn queue<T: Type>(
     connect(read_port.en, true);
     connect(read_port.clk, cd.clk);
     connect(write_port.addr, inp_index_reg);
-    connect(write_port.en, inp_fire);
+    connect(write_port.en, inp_firing);
     connect(write_port.clk, cd.clk);
     connect(write_port.data, HdlOption::unwrap_or(inp.data, ty.uninit()));
     connect(write_port.mask, splat_mask(ty, true.to_expr()));
@@ -126,12 +126,12 @@ pub fn queue<T: Type>(
     }
 
     #[hdl]
-    if inp_fire.cmp_ne(out_fire) {
-        connect(maybe_full_reg, inp_fire);
+    if inp_firing.cmp_ne(out_firing) {
+        connect(maybe_full_reg, inp_firing);
     }
 
     #[hdl]
-    if inp_fire {
+    if inp_firing {
         #[hdl]
         if inp_index_reg.cmp_eq(capacity.get() - 1) {
             connect_any(inp_index_reg, 0_hdl_u0);
@@ -141,7 +141,7 @@ pub fn queue<T: Type>(
     }
 
     #[hdl]
-    if out_fire {
+    if out_firing {
         #[hdl]
         if out_index_reg.cmp_eq(capacity.get() - 1) {
             connect_any(out_index_reg, 0_hdl_u0);
@@ -258,9 +258,9 @@ mod tests {
             connect(next_expected_count, expected_count_reg);
             connect(expected_count_reg, next_expected_count);
             #[hdl]
-            if ReadyValid::fire(dut.inp) & !ReadyValid::fire(dut.out) {
+            if ReadyValid::firing(dut.inp) & !ReadyValid::firing(dut.out) {
                 connect_any(next_expected_count, expected_count_reg + 1u8);
-            } else if !ReadyValid::fire(dut.inp) & ReadyValid::fire(dut.out) {
+            } else if !ReadyValid::firing(dut.inp) & ReadyValid::firing(dut.out) {
                 connect_any(next_expected_count, expected_count_reg - 1u8);
             }
             hdl_assert(cd.clk, expected_count_reg.cmp_eq(dut.count), "");
@@ -289,7 +289,7 @@ mod tests {
             let stored_inp_data_reg = reg_builder().clock_domain(cd).reset(0u8);
 
             #[hdl]
-            if let HdlSome(data) = ReadyValid::fire_data(dut.inp) {
+            if let HdlSome(data) = ReadyValid::firing_data(dut.inp) {
                 #[hdl]
                 if inp_index_reg.cmp_lt(index_max) {
                     connect_any(inp_index_reg, inp_index_reg + 1u8);
@@ -311,7 +311,7 @@ mod tests {
             let stored_out_data_reg = reg_builder().clock_domain(cd).reset(0u8);
 
             #[hdl]
-            if let HdlSome(data) = ReadyValid::fire_data(dut.out) {
+            if let HdlSome(data) = ReadyValid::firing_data(dut.out) {
                 #[hdl]
                 if out_index_reg.cmp_lt(index_max) {
                     connect_any(out_index_reg, out_index_reg + 1u8);

From f403eed7c087fc8a345cfd48941315d0e44a18dc Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 6 Oct 2024 20:08:39 -0700
Subject: [PATCH 054/190] only run tests once, since they are quite slow

---
 .forgejo/workflows/test.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index 68ded33..3173827 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -65,5 +65,5 @@ jobs:
         with:
           save-if: ${{ github.ref == 'refs/heads/master' }}
       - run: cargo test
-      - run: cargo test --features=unstable-doc
+      - run: cargo build --tests --features=unstable-doc
       - run: cargo doc --features=unstable-doc

From aec383c0af018cfaec0d12207a25d8bc4e74fa75 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 6 Oct 2024 20:57:42 -0700
Subject: [PATCH 055/190] try to fix ccache

---
 .forgejo/workflows/test.yml | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index 3173827..1246015 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -37,11 +37,17 @@ jobs:
       - name: Cache ccache dir
         uses: https://code.forgejo.org/actions/cache@v3
         with:
-          path: ~/.ccache
+          path: .ccache
           key: ${{ runner.os }}-${{ github.sha }}
           restore-keys: |
             ${{ runner.os }}-
-      - run: |
+      - name: Setup ccache
+        run: |
+          ccache --set-config=cache_dir="${{ github.workspace }}/.ccache"
+          ccache --set-config=compression=true
+          ccache --set-config=compression_level=6
+          ccache -M 4G
+          ccache -z
           export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
           echo "$PATH" >> "$GITHUB_PATH"
       - run: |

From eed0afc6ab2f656794eaf3fbfa2978abed21e0b7 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 7 Oct 2024 19:05:20 -0700
Subject: [PATCH 056/190] add some utility From<Interned<T>> impls

---
 crates/fayalite/src/intern.rs | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/crates/fayalite/src/intern.rs b/crates/fayalite/src/intern.rs
index 81d8434..9bd4d56 100644
--- a/crates/fayalite/src/intern.rs
+++ b/crates/fayalite/src/intern.rs
@@ -764,6 +764,24 @@ where
     }
 }
 
+impl<T: 'static + Clone + Send + Sync, C: InternContext> From<Interned<[T], C>> for Vec<T> {
+    fn from(value: Interned<[T], C>) -> Self {
+        Vec::from(&*value.guard())
+    }
+}
+
+impl<T: 'static + Clone + Send + Sync, C: InternContext> From<Interned<[T], C>> for Box<[T]> {
+    fn from(value: Interned<[T], C>) -> Self {
+        Box::from(&*value.guard())
+    }
+}
+
+impl<C: InternContext> From<Interned<str, C>> for String {
+    fn from(value: Interned<str, C>) -> Self {
+        String::from(&*value.guard())
+    }
+}
+
 impl<I, C: InternContext<AllContextsAreIdentical = ConstBool<true>> + Default> Default
     for Interned<[I], C>
 where

From 30b9a5e48d531c6be2d08707cfcceacdb694a21b Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 7 Oct 2024 19:06:01 -0700
Subject: [PATCH 057/190] change NameId to have an opaque Id so output firrtl
 doesn't depend on how many modules of the same name were ever created

---
 crates/fayalite/src/firrtl.rs                 |  35 ++-
 crates/fayalite/src/module.rs                 | 196 +++++----------
 .../src/module/transform/simplify_enums.rs    |   7 +-
 .../src/module/transform/simplify_memories.rs |  19 +-
 crates/fayalite/tests/module.rs               | 224 +++++++++---------
 crates/fayalite/visit_types.json              |   2 +-
 6 files changed, 204 insertions(+), 279 deletions(-)

diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index ef955ea..bc75ccc 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -27,7 +27,7 @@ use crate::{
             simplify_memories::simplify_memories,
         },
         AnnotatedModuleIO, Block, ExternModuleBody, ExternModuleParameter,
-        ExternModuleParameterValue, Module, ModuleBody, NameId, NormalModuleBody, Stmt,
+        ExternModuleParameterValue, Module, ModuleBody, NameOptId, NormalModuleBody, Stmt,
         StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg,
         StmtWire,
     },
@@ -187,9 +187,9 @@ struct NameMaker {
 }
 
 impl NameMaker {
-    fn make(&mut self, name: NameId) -> Ident {
-        let mut num: usize = name.1;
-        let name = String::from(&*name.0);
+    fn make(&mut self, name: impl Into<String>) -> Ident {
+        let mut num = 0usize;
+        let name: String = name.into();
         // remove all invalid characters -- all valid characters are ASCII, so we can just remove invalid bytes
         let mut name = String::from_iter(
             name.bytes()
@@ -221,7 +221,7 @@ impl NameMaker {
 #[derive(Default)]
 struct Namespace {
     name_maker: NameMaker,
-    map: HashMap<NameId, Ident>,
+    map: HashMap<NameOptId, Ident>,
 }
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
@@ -247,10 +247,11 @@ impl From<PortName> for Ident {
 }
 
 impl Namespace {
-    fn get(&mut self, name: NameId) -> Ident {
+    fn get(&mut self, name: impl Into<NameOptId>) -> Ident {
+        let name: NameOptId = name.into();
         #[cold]
-        fn make(name_maker: &mut NameMaker, name: NameId) -> Ident {
-            name_maker.make(name)
+        fn make(name_maker: &mut NameMaker, name: NameOptId) -> Ident {
+            name_maker.make(name.0)
         }
         *self
             .map
@@ -258,7 +259,7 @@ impl Namespace {
             .or_insert_with(|| make(&mut self.name_maker, name))
     }
     fn make_new(&mut self, prefix: &str) -> Ident {
-        self.name_maker.make(NameId(prefix.intern(), 0))
+        self.name_maker.make(prefix)
     }
 }
 
@@ -368,7 +369,7 @@ impl TypeState {
         Ident(Intern::intern_owned(format!("Ty{id}")))
     }
     fn get_bundle_field(&mut self, ty: Bundle, name: Interned<str>) -> Ident {
-        self.bundle_ns(ty).borrow_mut().get(NameId(name, 0))
+        self.bundle_ns(ty).borrow_mut().get(name)
     }
     fn bundle_def(&self, ty: Bundle) -> (Ident, Rc<RefCell<Namespace>>) {
         self.bundle_defs.get_or_make(ty, |&ty, definitions| {
@@ -382,7 +383,7 @@ impl TypeState {
                 if flipped {
                     body.push_str("flip ");
                 }
-                write!(body, "{}: ", ns.get(NameId(name, 0))).unwrap();
+                write!(body, "{}: ", ns.get(name)).unwrap();
                 body.push_str(&self.ty(ty));
             }
             body.push('}');
@@ -406,7 +407,7 @@ impl TypeState {
             for EnumVariant { name, ty } in ty.variants() {
                 body.push_str(separator);
                 separator = ", ";
-                write!(body, "{}", variants.get(NameId(name, 0))).unwrap();
+                write!(body, "{}", variants.get(name)).unwrap();
                 if let Some(ty) = ty {
                     body.push_str(": ");
                     body.push_str(&self.ty(ty));
@@ -428,11 +429,7 @@ impl TypeState {
         self.enum_def(ty).0
     }
     fn get_enum_variant(&mut self, ty: Enum, name: Interned<str>) -> Ident {
-        self.enum_def(ty)
-            .1
-            .variants
-            .borrow_mut()
-            .get(NameId(name, 0))
+        self.enum_def(ty).1.variants.borrow_mut().get(name)
     }
     fn ty<T: Type>(&self, ty: T) -> String {
         match ty.canonical() {
@@ -929,7 +926,7 @@ impl<'a> Exporter<'a> {
         ) in expr.field_values().into_iter().zip(ty.fields())
         {
             debug_assert!(!flipped, "can't have bundle literal with flipped field -- this should have been caught in BundleLiteral::new_unchecked");
-            let name = bundle_ns.borrow_mut().get(NameId(name, 0));
+            let name = bundle_ns.borrow_mut().get(name);
             let field_value = self.expr(Expr::canonical(field_value), definitions, const_ty);
             definitions.add_definition_line(format_args!("connect {ident}.{name}, {field_value}"));
         }
@@ -2199,7 +2196,7 @@ impl<'a> Exporter<'a> {
         } in module.module_io().iter()
         {
             self.targeted_annotations(module_name, vec![], annotations);
-            let name = self.module.ns.get(NameId(module_io.name(), 0));
+            let name = self.module.ns.get(module_io.name_id());
             let ty = self.type_state.ty(module_io.ty());
             if module_io.is_input() {
                 writeln!(
diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index 872c75f..2ba3800 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -36,9 +36,10 @@ use std::{
     iter::FusedIterator,
     marker::PhantomData,
     mem,
+    num::NonZeroU64,
     ops::Deref,
     rc::Rc,
-    sync::Mutex,
+    sync::atomic::AtomicU64,
 };
 
 pub mod transform;
@@ -602,8 +603,48 @@ impl BlockStack {
     }
 }
 
+#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)]
+pub struct Id(NonZeroU64);
+
+impl Id {
+    pub fn new() -> Self {
+        static NEXT_ID: AtomicU64 = AtomicU64::new(1);
+        Self(
+            NonZeroU64::new(NEXT_ID.fetch_add(1, std::sync::atomic::Ordering::Relaxed))
+                .expect("Id::new ran out of ids"),
+        )
+    }
+}
+
 #[derive(Copy, Clone, Eq, PartialEq, Hash)]
-pub struct NameId(pub Interned<str>, pub usize);
+pub struct NameOptId(pub Interned<str>, pub Option<Id>);
+
+impl fmt::Debug for NameOptId {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        fmt::Display::fmt(self, f)
+    }
+}
+
+impl fmt::Display for NameOptId {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.write_str(&self.0)
+    }
+}
+
+impl From<Interned<str>> for NameOptId {
+    fn from(name: Interned<str>) -> Self {
+        Self(name, None)
+    }
+}
+
+impl From<NameId> for NameOptId {
+    fn from(name_id: NameId) -> Self {
+        Self(name_id.0, Some(name_id.1))
+    }
+}
+
+#[derive(Copy, Clone, Eq, PartialEq, Hash)]
+pub struct NameId(pub Interned<str>, pub Id);
 
 impl fmt::Debug for NameId {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
@@ -613,13 +654,7 @@ impl fmt::Debug for NameId {
 
 impl fmt::Display for NameId {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        if self.0.is_empty() {
-            write!(f, "{}", self.1)
-        } else if self.1 == 0 {
-            f.write_str(&self.0)
-        } else {
-            write!(f, "{}_{}", self.0, self.1)
-        }
+        f.write_str(&self.0)
     }
 }
 
@@ -648,106 +683,6 @@ impl fmt::Debug for TargetName {
     }
 }
 
-#[derive(Default)]
-pub struct NameIdGen(HashMap<Interned<str>, usize>);
-
-impl NameIdGen {
-    pub fn gen(&mut self, name: Interned<str>) -> NameId {
-        let next_id = self.0.entry(name).or_default();
-        let id = *next_id;
-        *next_id += 1;
-        NameId(name, id)
-    }
-    pub fn mark_as_used(&mut self, name_id: NameId) {
-        let next_id = self.0.entry(name_id.0).or_default();
-        *next_id = (*next_id).max(name_id.1 + 1);
-    }
-    pub fn for_module(module: Module<Bundle>) -> Self {
-        let mut retval = Self::default();
-        let Module {
-            name: _,
-            source_location: _,
-            body,
-            io_ty: _,
-            module_io,
-            module_annotations: _,
-        } = module;
-        for module_io in &module_io {
-            retval.mark_as_used(module_io.module_io.name_id());
-        }
-        match body {
-            ModuleBody::Extern(ExternModuleBody {
-                verilog_name: _,
-                parameters: _,
-            }) => {}
-            ModuleBody::Normal(NormalModuleBody { body }) => {
-                let mut blocks = vec![body];
-                while let Some(block) = blocks.pop() {
-                    let Block { memories, stmts } = block;
-                    for memory in memories {
-                        retval.mark_as_used(memory.scoped_name().1);
-                    }
-                    for stmt in &stmts {
-                        blocks.extend_from_slice(stmt.sub_stmt_blocks());
-                        match stmt {
-                            Stmt::Connect(StmtConnect {
-                                lhs: _,
-                                rhs: _,
-                                source_location: _,
-                            })
-                            | Stmt::Formal(StmtFormal {
-                                kind: _,
-                                clk: _,
-                                pred: _,
-                                en: _,
-                                text: _,
-                                source_location: _,
-                            })
-                            | Stmt::If(StmtIf {
-                                cond: _,
-                                source_location: _,
-                                blocks: _,
-                            })
-                            | Stmt::Match(StmtMatch {
-                                expr: _,
-                                source_location: _,
-                                blocks: _,
-                            }) => {}
-                            Stmt::Declaration(StmtDeclaration::Instance(StmtInstance {
-                                annotations: _,
-                                instance,
-                            })) => {
-                                retval.mark_as_used(instance.name_id());
-                            }
-                            Stmt::Declaration(StmtDeclaration::Reg(StmtReg {
-                                annotations: _,
-                                reg,
-                            })) => {
-                                retval.mark_as_used(reg.name_id());
-                            }
-                            Stmt::Declaration(StmtDeclaration::Wire(StmtWire {
-                                annotations: _,
-                                wire,
-                            })) => {
-                                retval.mark_as_used(wire.name_id());
-                            }
-                        }
-                    }
-                }
-            }
-        }
-        retval
-    }
-    pub fn gen_module_name(name: Interned<str>) -> NameId {
-        static MODULE_NAME_GEN: Mutex<Option<NameIdGen>> = Mutex::new(None);
-        MODULE_NAME_GEN
-            .lock()
-            .unwrap()
-            .get_or_insert_with(NameIdGen::default)
-            .gen(name)
-    }
-}
-
 #[derive(Copy, Clone, Eq, PartialEq, Hash)]
 pub struct Instance<T: BundleType> {
     scoped_name: ScopedNameId,
@@ -836,7 +771,6 @@ struct ModuleBuilderImpl {
     body: ModuleBodyBuilding,
     io: Vec<AnnotatedModuleIO<ModuleBuilding>>,
     io_indexes: HashMap<ModuleIO<CanonicalType>, usize>,
-    name_id_gen: NameIdGen,
     module_annotations: Vec<Annotation>,
 }
 
@@ -1941,9 +1875,7 @@ impl<T: Type> RegBuilder<Expr<ClockDomain>, Option<Expr<T>>, T> {
             ty,
         } = self;
         ModuleBuilder::with(|module_builder| {
-            let mut impl_ = module_builder.impl_.borrow_mut();
-            let scoped_name = ScopedNameId(module_builder.name, impl_.name_id_gen.gen(name));
-            drop(impl_);
+            let scoped_name = ScopedNameId(module_builder.name, NameId(name, Id::new()));
             let reg = Reg::new_unchecked(scoped_name, source_location, ty, clock_domain, init);
             let retval = reg.to_expr();
             // convert before borrow_mut since ModuleBuilder could be reentered by T::canonical()
@@ -1991,8 +1923,13 @@ impl ModuleBuilder {
         is_input: bool,
         ty: IO,
     ) -> Expr<IO> {
-        let module_io =
-            ModuleIO::<IO>::new_unchecked(self.name, name.intern(), source_location, is_input, ty);
+        let module_io = ModuleIO::<IO>::new_unchecked(
+            self.name,
+            NameId(name.intern(), Id::new()),
+            source_location,
+            is_input,
+            ty,
+        );
         let retval = module_io.to_expr();
         let module_io = module_io.canonical();
         let mut impl_ = self.impl_.borrow_mut();
@@ -2080,7 +2017,7 @@ impl ModuleBuilder {
         module_kind: ModuleKind,
         f: impl FnOnce(&Self) -> Result<(), E>,
     ) -> Result<Interned<Module<T>>, E> {
-        let name = NameIdGen::gen_module_name(name.intern());
+        let name = NameId(name.intern(), Id::new());
         let body = match module_kind {
             ModuleKind::Extern => ModuleBody::Extern(ExternModuleBody {
                 verilog_name: name.0,
@@ -2105,7 +2042,6 @@ impl ModuleBuilder {
                 body,
                 io: vec![],
                 io_indexes: HashMap::new(),
-                name_id_gen: NameIdGen::default(),
                 module_annotations: vec![],
             }),
         };
@@ -2277,9 +2213,7 @@ pub fn annotate<T: Type>(target: Expr<T>, annotations: impl IntoAnnotations) {
 #[track_caller]
 pub fn wire_with_loc<T: Type>(name: &str, source_location: SourceLocation, ty: T) -> Expr<T> {
     ModuleBuilder::with(|m| {
-        let mut impl_ = m.impl_.borrow_mut();
-        let scoped_name = ScopedNameId(m.name, impl_.name_id_gen.gen(name.intern()));
-        drop(impl_);
+        let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
         let wire = Wire::<T>::new_unchecked(scoped_name, source_location, ty);
         let retval = wire.to_expr();
         let canonical_wire = wire.canonical();
@@ -2311,9 +2245,7 @@ fn incomplete_declaration(
     source_location: SourceLocation,
 ) -> Rc<RefCell<IncompleteDeclaration>> {
     ModuleBuilder::with(|m| {
-        let mut impl_ = m.impl_.borrow_mut();
-        let scoped_name = ScopedNameId(m.name, impl_.name_id_gen.gen(name.intern()));
-        drop(impl_);
+        let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
         let retval = Rc::new(RefCell::new(IncompleteDeclaration::Incomplete {
             name: scoped_name,
             source_location,
@@ -2489,9 +2421,7 @@ pub fn instance_with_loc<T: BundleType>(
     source_location: SourceLocation,
 ) -> Expr<T> {
     ModuleBuilder::with(|m| {
-        let mut impl_ = m.impl_.borrow_mut();
-        let scoped_name = ScopedNameId(m.name, impl_.name_id_gen.gen(name.intern()));
-        drop(impl_);
+        let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
         let instance = Instance::<T> {
             scoped_name,
             instantiated,
@@ -2530,9 +2460,7 @@ fn memory_impl<Element: Type, Len: Size>(
     source_location: SourceLocation,
 ) -> MemBuilder<Element, Len> {
     ModuleBuilder::with(|m| {
-        let mut impl_ = m.impl_.borrow_mut();
-        let scoped_name = ScopedNameId(m.name, impl_.name_id_gen.gen(name.intern()));
-        drop(impl_);
+        let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
         let (retval, target_mem) = MemBuilder::new(scoped_name, source_location, mem_element_type);
         let mut impl_ = m.impl_.borrow_mut();
         let body = impl_.body.builder_normal_body();
@@ -2608,6 +2536,7 @@ pub fn memory<Element: Type>(
 pub struct ModuleIO<T: Type> {
     containing_module_name: NameId,
     bundle_field: BundleField,
+    id: Id,
     ty: T,
     source_location: SourceLocation,
 }
@@ -2627,12 +2556,14 @@ impl<T: Type> ModuleIO<T> {
         let Self {
             containing_module_name,
             bundle_field,
+            id,
             ty: _,
             source_location,
         } = *self;
         ModuleIO {
             containing_module_name,
             bundle_field,
+            id,
             ty: bundle_field.ty,
             source_location,
         }
@@ -2656,7 +2587,7 @@ impl<T: Type> ModuleIO<T> {
         self.bundle_field.name
     }
     pub fn name_id(&self) -> NameId {
-        NameId(self.bundle_field.name, 0)
+        NameId(self.bundle_field.name, self.id)
     }
     pub fn scoped_name(&self) -> ScopedNameId {
         ScopedNameId(self.containing_module_name, self.name_id())
@@ -2666,7 +2597,7 @@ impl<T: Type> ModuleIO<T> {
     }
     pub fn new_unchecked(
         containing_module_name: NameId,
-        name: Interned<str>,
+        name: NameId,
         source_location: SourceLocation,
         is_input: bool,
         ty: T,
@@ -2674,10 +2605,11 @@ impl<T: Type> ModuleIO<T> {
         Self {
             containing_module_name,
             bundle_field: BundleField {
-                name,
+                name: name.0,
                 flipped: is_input,
                 ty: ty.canonical(),
             },
+            id: name.1,
             ty,
             source_location,
         }
diff --git a/crates/fayalite/src/module/transform/simplify_enums.rs b/crates/fayalite/src/module/transform/simplify_enums.rs
index edb4b97..f398006 100644
--- a/crates/fayalite/src/module/transform/simplify_enums.rs
+++ b/crates/fayalite/src/module/transform/simplify_enums.rs
@@ -14,8 +14,7 @@ use crate::{
     memory::{DynPortType, Mem, MemPort},
     module::{
         transform::visit::{Fold, Folder},
-        Block, Module, NameId, NameIdGen, ScopedNameId, Stmt, StmtConnect, StmtIf, StmtMatch,
-        StmtWire,
+        Block, Id, Module, NameId, ScopedNameId, Stmt, StmtConnect, StmtIf, StmtMatch, StmtWire,
     },
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
@@ -92,13 +91,12 @@ enum EnumTypeState {
 }
 
 struct ModuleState {
-    name_id_gen: NameIdGen,
     module_name: NameId,
 }
 
 impl ModuleState {
     fn gen_name(&mut self, name: &str) -> ScopedNameId {
-        ScopedNameId(self.module_name, self.name_id_gen.gen(name.intern()))
+        ScopedNameId(self.module_name, NameId(name.intern(), Id::new()))
     }
 }
 
@@ -632,7 +630,6 @@ impl Folder for State {
 
     fn fold_module<T: BundleType>(&mut self, v: Module<T>) -> Result<Module<T>, Self::Error> {
         self.module_state_stack.push(ModuleState {
-            name_id_gen: NameIdGen::for_module(v.canonical()),
             module_name: v.name_id(),
         });
         let retval = Fold::default_fold(v, self);
diff --git a/crates/fayalite/src/module/transform/simplify_memories.rs b/crates/fayalite/src/module/transform/simplify_memories.rs
index 19fb0ec..71e459c 100644
--- a/crates/fayalite/src/module/transform/simplify_memories.rs
+++ b/crates/fayalite/src/module/transform/simplify_memories.rs
@@ -10,7 +10,7 @@ use crate::{
     memory::{Mem, MemPort, PortType},
     module::{
         transform::visit::{Fold, Folder},
-        Block, Module, NameId, NameIdGen, ScopedNameId, Stmt, StmtConnect, StmtWire,
+        Block, Id, Module, NameId, ScopedNameId, Stmt, StmtConnect, StmtWire,
     },
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
@@ -417,7 +417,6 @@ impl SplitMemState<'_, '_> {
 
 struct ModuleState {
     output_module: Option<Interned<Module<Bundle>>>,
-    name_id_gen: NameIdGen,
     memories: HashMap<ScopedNameId, MemState>,
 }
 
@@ -626,10 +625,10 @@ impl ModuleState {
         mem_name_path: &str,
         split_state: &SplitState<'_>,
     ) -> Mem {
-        let mem_name = self.name_id_gen.gen(Intern::intern_owned(format!(
-            "{}{mem_name_path}",
-            input_mem.scoped_name().1 .0
-        )));
+        let mem_name = NameId(
+            Intern::intern_owned(format!("{}{mem_name_path}", input_mem.scoped_name().1 .0)),
+            Id::new(),
+        );
         let mem_name = ScopedNameId(input_mem.scoped_name().0, mem_name);
         let output_element_type = match single_type {
             SingleType::UInt(ty) => ty.canonical(),
@@ -753,9 +752,10 @@ impl ModuleState {
                     let port_ty = port.ty();
                     let NameId(mem_name, _) = input_mem.scoped_name().1;
                     let port_name = port.port_name();
-                    let wire_name = self
-                        .name_id_gen
-                        .gen(Intern::intern_owned(format!("{mem_name}_{port_name}")));
+                    let wire_name = NameId(
+                        Intern::intern_owned(format!("{mem_name}_{port_name}")),
+                        Id::new(),
+                    );
                     let wire = Wire::new_unchecked(
                         ScopedNameId(input_mem.scoped_name().0, wire_name),
                         port.source_location(),
@@ -887,7 +887,6 @@ impl Folder for State {
             module,
             ModuleState {
                 output_module: None,
-                name_id_gen: NameIdGen::for_module(*module),
                 memories: HashMap::new(),
             },
         );
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 69438f2..b0b1fb6 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -175,9 +175,9 @@ circuit check_array_repeat:
     #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
     assert_export_firrtl! {
         m =>
-        "/test/check_array_repeat_1.fir": r"FIRRTL version 3.2.0
-circuit check_array_repeat_1:
-    module check_array_repeat_1: @[module-XXXXXXXXXX.rs 1:1]
+        "/test/check_array_repeat.fir": r"FIRRTL version 3.2.0
+circuit check_array_repeat:
+    module check_array_repeat: @[module-XXXXXXXXXX.rs 1:1]
         input i: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
         output o: UInt<8>[4] @[module-XXXXXXXXXX.rs 3:1]
         wire _array_literal_expr: UInt<8>[4]
@@ -1672,9 +1672,9 @@ fn test_memory_of_arrays() {
 circuit check_memory_of_arrays: %[[
   {
     "class": "firrtl.annotations.MemoryFileInlineAnnotation",
-    "filename": "/test/check_memory_of_arrays/mem_1.mem",
+    "filename": "/test/check_memory_of_arrays/mem.mem",
     "hexOrBinary": "h",
-    "target": "~check_memory_of_arrays|check_memory_of_arrays>mem_1"
+    "target": "~check_memory_of_arrays|check_memory_of_arrays>mem"
   }
 ]]
     type Ty0 = {addr: UInt<4>, en: UInt<1>, clk: Clock, flip data: UInt<8>[2][3]}
@@ -1688,7 +1688,7 @@ circuit check_memory_of_arrays: %[[
         input wdata: UInt<8>[2][3] @[module-XXXXXXXXXX.rs 5:1]
         input wmask: UInt<1>[2][3] @[module-XXXXXXXXXX.rs 6:1]
         input clk: Clock @[module-XXXXXXXXXX.rs 7:1]
-        mem mem_1: @[module-XXXXXXXXXX.rs 8:1]
+        mem `mem`: @[module-XXXXXXXXXX.rs 8:1]
             data-type => UInt<8>[6]
             depth => 16
             read-latency => 0
@@ -1698,30 +1698,30 @@ circuit check_memory_of_arrays: %[[
             writer => w1
         wire mem_r0: Ty0 @[module-XXXXXXXXXX.rs 9:1]
         wire mem_w1: Ty1 @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_r0.data[0][0], mem_1.r0.data[0] @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_r0.data[0][1], mem_1.r0.data[1] @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_r0.data[1][0], mem_1.r0.data[2] @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_r0.data[1][1], mem_1.r0.data[3] @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_r0.data[2][0], mem_1.r0.data[4] @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_r0.data[2][1], mem_1.r0.data[5] @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_1.w1.data[0], mem_w1.data[0][0] @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.mask[0], mem_w1.mask[0][0] @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.data[1], mem_w1.data[0][1] @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.mask[1], mem_w1.mask[0][1] @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.data[2], mem_w1.data[1][0] @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.mask[2], mem_w1.mask[1][0] @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.data[3], mem_w1.data[1][1] @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.mask[3], mem_w1.mask[1][1] @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.data[4], mem_w1.data[2][0] @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.mask[4], mem_w1.mask[2][0] @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.data[5], mem_w1.data[2][1] @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.mask[5], mem_w1.mask[2][1] @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_1.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_1.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_1.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_r0.data[0][0], `mem`.r0.data[0] @[module-XXXXXXXXXX.rs 9:1]
+        connect mem_r0.data[0][1], `mem`.r0.data[1] @[module-XXXXXXXXXX.rs 9:1]
+        connect mem_r0.data[1][0], `mem`.r0.data[2] @[module-XXXXXXXXXX.rs 9:1]
+        connect mem_r0.data[1][1], `mem`.r0.data[3] @[module-XXXXXXXXXX.rs 9:1]
+        connect mem_r0.data[2][0], `mem`.r0.data[4] @[module-XXXXXXXXXX.rs 9:1]
+        connect mem_r0.data[2][1], `mem`.r0.data[5] @[module-XXXXXXXXXX.rs 9:1]
+        connect `mem`.w1.data[0], mem_w1.data[0][0] @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.mask[0], mem_w1.mask[0][0] @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.data[1], mem_w1.data[0][1] @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.mask[1], mem_w1.mask[0][1] @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.data[2], mem_w1.data[1][0] @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.mask[2], mem_w1.mask[1][0] @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.data[3], mem_w1.data[1][1] @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.mask[3], mem_w1.mask[1][1] @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.data[4], mem_w1.data[2][0] @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.mask[4], mem_w1.mask[2][0] @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.data[5], mem_w1.data[2][1] @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.mask[5], mem_w1.mask[2][1] @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
+        connect `mem`.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
+        connect `mem`.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
+        connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
         connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
         connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
         connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
@@ -1732,7 +1732,7 @@ circuit check_memory_of_arrays: %[[
         connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
         connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
 "#,
-        "/test/check_memory_of_arrays/mem_1.mem": r"000000000000
+        "/test/check_memory_of_arrays/mem.mem": r"000000000000
 020103020101
 04080c080402
 061b1b120903
@@ -2445,9 +2445,9 @@ fn test_memory_of_enum() {
 circuit check_memory_of_enum: %[[
   {
     "class": "firrtl.annotations.MemoryFileInlineAnnotation",
-    "filename": "/test/check_memory_of_enum/mem_1.mem",
+    "filename": "/test/check_memory_of_enum/mem.mem",
     "hexOrBinary": "b",
-    "target": "~check_memory_of_enum|check_memory_of_enum>mem_1"
+    "target": "~check_memory_of_enum|check_memory_of_enum>mem"
   }
 ]]
     type Ty0 = {|A, B: UInt<8>, C: UInt<1>[3]|}
@@ -2462,7 +2462,7 @@ circuit check_memory_of_enum: %[[
         input wdata: Ty0 @[module-XXXXXXXXXX.rs 5:1]
         input wmask: UInt<1> @[module-XXXXXXXXXX.rs 6:1]
         input clk: Clock @[module-XXXXXXXXXX.rs 7:1]
-        mem mem_1: @[module-XXXXXXXXXX.rs 8:1]
+        mem `mem`: @[module-XXXXXXXXXX.rs 8:1]
             data-type => UInt<10>
             depth => 16
             read-latency => 0
@@ -2474,10 +2474,10 @@ circuit check_memory_of_enum: %[[
         wire mem_w1: Ty2 @[module-XXXXXXXXXX.rs 14:1]
         wire _cast_bits_to_enum_expr: Ty0
         wire _cast_bits_to_enum_expr_body: UInt<8>
-        connect _cast_bits_to_enum_expr_body, head(mem_1.r0.data, 8)
-        when eq(UInt<2>(0), tail(mem_1.r0.data, 8)):
+        connect _cast_bits_to_enum_expr_body, head(`mem`.r0.data, 8)
+        when eq(UInt<2>(0), tail(`mem`.r0.data, 8)):
             connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(A)
-        else when eq(UInt<2>(1), tail(mem_1.r0.data, 8)):
+        else when eq(UInt<2>(1), tail(`mem`.r0.data, 8)):
             connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(B, _cast_bits_to_enum_expr_body)
         else:
             wire _cast_bits_to_array_expr: UInt<1>[3]
@@ -2504,14 +2504,14 @@ circuit check_memory_of_enum: %[[
                 wire _cast_to_bits_expr: UInt<3>
                 connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
                 connect _cast_enum_to_bits_expr, pad(cat(_cast_to_bits_expr, UInt<2>(2)), 10)
-        connect mem_1.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.mask, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_1.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_1.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_1.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.mask, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
+        connect `mem`.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
+        connect `mem`.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
+        connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
         ; connect different types:
         ; lhs: UInt<4>
         ; rhs: UInt<8>
@@ -2528,7 +2528,7 @@ circuit check_memory_of_enum: %[[
         connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
         connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
 "#,
-        "/test/check_memory_of_enum/mem_1.mem": r"0000000000
+        "/test/check_memory_of_enum/mem.mem": r"0000000000
 0000000110
 0000001010
 0000010010
@@ -2602,7 +2602,7 @@ circuit check_memory_of_enum: %[[
             reader => r0
             writer => w1
         wire mem_r0: Ty2 @[module-XXXXXXXXXX.rs 9:1]
-        wire mem_w1_1: Ty4 @[module-XXXXXXXXXX.rs 14:1]
+        wire mem_w1: Ty4 @[module-XXXXXXXXXX.rs 14:1]
         wire _cast_bits_to_enum_expr: Ty0
         when eq(UInt<2>(0), tail(mem_tag.r0.data, 0)):
             connect _cast_bits_to_enum_expr, {|A, B, C|}(A)
@@ -2612,7 +2612,7 @@ circuit check_memory_of_enum: %[[
             connect _cast_bits_to_enum_expr, {|A, B, C|}(C)
         connect mem_r0.data.tag, _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 9:1]
         wire _cast_enum_to_bits_expr: UInt<2>
-        match mem_w1_1.data.tag:
+        match mem_w1.data.tag:
             A:
                 connect _cast_enum_to_bits_expr, UInt<2>(0)
             B:
@@ -2620,29 +2620,29 @@ circuit check_memory_of_enum: %[[
             C:
                 connect _cast_enum_to_bits_expr, UInt<2>(2)
         connect mem_tag.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_tag.w1.mask, mem_w1_1.mask.tag @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_tag.w1.mask, mem_w1.mask.tag @[module-XXXXXXXXXX.rs 14:1]
         connect mem_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
         connect mem_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
         connect mem_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_tag.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_tag.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_tag.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_tag.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_tag.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_tag.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
         connect mem_r0.data.body, mem_body.r0.data @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_body.w1.data, mem_w1_1.data.body @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_body.w1.mask, mem_w1_1.mask.body @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_body.w1.data, mem_w1.data.body @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_body.w1.mask, mem_w1.mask.body @[module-XXXXXXXXXX.rs 14:1]
         connect mem_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
         connect mem_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
         connect mem_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_body.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_body.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_body.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
-        wire mem_w1: Ty9 @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_w1_1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_w1_1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_w1_1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_w1_1.data, mem_w1.data @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_w1_1.mask.tag, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_w1_1.mask.body, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_body.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_body.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_body.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
+        wire mem_w1_1: Ty9 @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_w1.data, mem_w1_1.data @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_w1.mask.tag, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_w1.mask.body, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
         ; connect different types:
         ; lhs: UInt<4>
         ; rhs: UInt<8>
@@ -2653,11 +2653,11 @@ circuit check_memory_of_enum: %[[
         ; connect different types:
         ; lhs: UInt<4>
         ; rhs: UInt<8>
-        connect mem_w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
-        connect mem_w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
-        connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
-        connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
-        connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
+        connect mem_w1_1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
+        connect mem_w1_1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
+        connect mem_w1_1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
+        connect mem_w1_1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
+        connect mem_w1_1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
 "#,
         "/test/check_memory_of_enum/mem_body.mem": r"00
 01
@@ -2748,32 +2748,32 @@ circuit check_memory_of_enum: %[[
             reader => r0
             writer => w1
         wire mem_r0: Ty1 @[module-XXXXXXXXXX.rs 9:1]
-        wire mem_w1_1: Ty3 @[module-XXXXXXXXXX.rs 14:1]
+        wire mem_w1: Ty3 @[module-XXXXXXXXXX.rs 14:1]
         connect mem_r0.data.tag, mem_tag.r0.data @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_tag.w1.data, mem_w1_1.data.tag @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_tag.w1.mask, mem_w1_1.mask.tag @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_tag.w1.data, mem_w1.data.tag @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_tag.w1.mask, mem_w1.mask.tag @[module-XXXXXXXXXX.rs 14:1]
         connect mem_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
         connect mem_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
         connect mem_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_tag.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_tag.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_tag.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_tag.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_tag.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_tag.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
         connect mem_r0.data.body, mem_body.r0.data @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_body.w1.data, mem_w1_1.data.body @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_body.w1.mask, mem_w1_1.mask.body @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_body.w1.data, mem_w1.data.body @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_body.w1.mask, mem_w1.mask.body @[module-XXXXXXXXXX.rs 14:1]
         connect mem_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
         connect mem_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
         connect mem_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_body.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_body.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_body.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
-        wire mem_w1: Ty8 @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_w1_1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_w1_1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_w1_1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_w1_1.data, mem_w1.data @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_w1_1.mask.tag, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_w1_1.mask.body, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_body.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_body.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_body.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
+        wire mem_w1_1: Ty8 @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_w1.data, mem_w1_1.data @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_w1.mask.tag, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
+        connect mem_w1.mask.body, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
         ; connect different types:
         ; lhs: UInt<4>
         ; rhs: UInt<8>
@@ -2784,11 +2784,11 @@ circuit check_memory_of_enum: %[[
         ; connect different types:
         ; lhs: UInt<4>
         ; rhs: UInt<8>
-        connect mem_w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
-        connect mem_w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
-        connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
-        connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
-        connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
+        connect mem_w1_1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
+        connect mem_w1_1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
+        connect mem_w1_1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
+        connect mem_w1_1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
+        connect mem_w1_1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
 "#,
         "/test/check_memory_of_enum/mem_body.mem": r"00
 01
@@ -2950,7 +2950,7 @@ circuit check_memory_of_array_of_enum:
         input wdata: Ty0[2] @[module-XXXXXXXXXX.rs 5:1]
         input wmask: UInt<1>[2] @[module-XXXXXXXXXX.rs 6:1]
         input clk: Clock @[module-XXXXXXXXXX.rs 7:1]
-        mem mem_1: @[module-XXXXXXXXXX.rs 8:1]
+        mem `mem`: @[module-XXXXXXXXXX.rs 8:1]
             data-type => UInt<10>[2]
             depth => 256
             read-latency => 0
@@ -2962,10 +2962,10 @@ circuit check_memory_of_array_of_enum:
         wire mem_w1: Ty2 @[module-XXXXXXXXXX.rs 14:1]
         wire _cast_bits_to_enum_expr: Ty0
         wire _cast_bits_to_enum_expr_body: UInt<8>
-        connect _cast_bits_to_enum_expr_body, head(mem_1.r0.data[0], 8)
-        when eq(UInt<2>(0), tail(mem_1.r0.data[0], 8)):
+        connect _cast_bits_to_enum_expr_body, head(`mem`.r0.data[0], 8)
+        when eq(UInt<2>(0), tail(`mem`.r0.data[0], 8)):
             connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(A)
-        else when eq(UInt<2>(1), tail(mem_1.r0.data[0], 8)):
+        else when eq(UInt<2>(1), tail(`mem`.r0.data[0], 8)):
             connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(B, _cast_bits_to_enum_expr_body)
         else:
             wire _cast_bits_to_array_expr: UInt<1>[3]
@@ -2980,10 +2980,10 @@ circuit check_memory_of_array_of_enum:
         connect mem_r0.data[0], _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 9:1]
         wire _cast_bits_to_enum_expr_1: Ty0
         wire _cast_bits_to_enum_expr_body_1: UInt<8>
-        connect _cast_bits_to_enum_expr_body_1, head(mem_1.r0.data[1], 8)
-        when eq(UInt<2>(0), tail(mem_1.r0.data[1], 8)):
+        connect _cast_bits_to_enum_expr_body_1, head(`mem`.r0.data[1], 8)
+        when eq(UInt<2>(0), tail(`mem`.r0.data[1], 8)):
             connect _cast_bits_to_enum_expr_1, {|A, B: UInt<8>, C: UInt<1>[3]|}(A)
-        else when eq(UInt<2>(1), tail(mem_1.r0.data[1], 8)):
+        else when eq(UInt<2>(1), tail(`mem`.r0.data[1], 8)):
             connect _cast_bits_to_enum_expr_1, {|A, B: UInt<8>, C: UInt<1>[3]|}(B, _cast_bits_to_enum_expr_body_1)
         else:
             wire _cast_bits_to_array_expr_1: UInt<1>[3]
@@ -3010,8 +3010,8 @@ circuit check_memory_of_array_of_enum:
                 wire _cast_to_bits_expr: UInt<3>
                 connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
                 connect _cast_enum_to_bits_expr, pad(cat(_cast_to_bits_expr, UInt<2>(2)), 10)
-        connect mem_1.w1.data[0], _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.mask[0], mem_w1.mask[0] @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.data[0], _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.mask[0], mem_w1.mask[0] @[module-XXXXXXXXXX.rs 14:1]
         wire _cast_enum_to_bits_expr_1: UInt<10>
         match mem_w1.data[1]:
             A:
@@ -3026,14 +3026,14 @@ circuit check_memory_of_array_of_enum:
                 wire _cast_to_bits_expr_1: UInt<3>
                 connect _cast_to_bits_expr_1, cat(_cast_array_to_bits_expr_1[2], cat(_cast_array_to_bits_expr_1[1], _cast_array_to_bits_expr_1[0]))
                 connect _cast_enum_to_bits_expr_1, pad(cat(_cast_to_bits_expr_1, UInt<2>(2)), 10)
-        connect mem_1.w1.data[1], _cast_enum_to_bits_expr_1 @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.mask[1], mem_w1.mask[1] @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_1.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_1.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
-        connect mem_1.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
-        connect mem_1.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.data[1], _cast_enum_to_bits_expr_1 @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.mask[1], mem_w1.mask[1] @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
+        connect `mem`.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
+        connect `mem`.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
+        connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
+        connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
         connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
         connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
         connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
@@ -3344,11 +3344,11 @@ circuit check_uninit:
             simplify_enums: None,
             ..ExportOptions::default()
         },
-        "/test/check_uninit_1.fir": r"FIRRTL version 3.2.0
-circuit check_uninit_1:
+        "/test/check_uninit.fir": r"FIRRTL version 3.2.0
+circuit check_uninit:
     type Ty0 = {}
     type Ty1 = {|HdlNone, HdlSome: Ty0|}
-    module check_uninit_1: @[module-XXXXXXXXXX.rs 1:1]
+    module check_uninit: @[module-XXXXXXXXXX.rs 1:1]
         output o: Ty1[3] @[module-XXXXXXXXXX.rs 2:1]
         wire _uninit_expr: Ty1[3]
         invalidate _uninit_expr
diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json
index 366ee2f..182efd9 100644
--- a/crates/fayalite/visit_types.json
+++ b/crates/fayalite/visit_types.json
@@ -28,7 +28,7 @@
                 "$kind": "Struct",
                 "$constructor": "ModuleIO::new_unchecked",
                 "containing_module_name_id()": "Visible",
-                "name()": "Visible",
+                "name_id()": "Visible",
                 "source_location()": "Visible",
                 "is_input()": "Visible",
                 "ty()": "Visible"

From 44ca1a607a04a5eddf327b4ffbaa9c54c6b6b5d1 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 7 Oct 2024 20:27:39 -0700
Subject: [PATCH 058/190] remove unused AGCContext

---
 crates/fayalite/src/intern.rs | 128 ----------------------------------
 1 file changed, 128 deletions(-)

diff --git a/crates/fayalite/src/intern.rs b/crates/fayalite/src/intern.rs
index 9bd4d56..c38f26f 100644
--- a/crates/fayalite/src/intern.rs
+++ b/crates/fayalite/src/intern.rs
@@ -198,7 +198,6 @@ impl<T: ?Sized + Sync + Send + 'static> LazyInterned<T> {
 pub trait InternedCompare {
     type InternedCompareKey: Ord + Hash;
     fn interned_compare_key_ref(this: &Self) -> Self::InternedCompareKey;
-    fn interned_compare_key_weak(this: &std::sync::Weak<Self>) -> Self::InternedCompareKey;
 }
 
 /// Warning: doesn't do what you want with `T = dyn Trait`,
@@ -272,9 +271,6 @@ impl<T> InternedCompare for T {
     fn interned_compare_key_ref(this: &Self) -> Self::InternedCompareKey {
         PtrEqWithMetadata(this)
     }
-    fn interned_compare_key_weak(this: &std::sync::Weak<Self>) -> Self::InternedCompareKey {
-        PtrEqWithMetadata(this.as_ptr())
-    }
 }
 
 impl<T> InternedCompare for [T] {
@@ -282,9 +278,6 @@ impl<T> InternedCompare for [T] {
     fn interned_compare_key_ref(this: &Self) -> Self::InternedCompareKey {
         PtrEqWithMetadata(this)
     }
-    fn interned_compare_key_weak(this: &std::sync::Weak<Self>) -> Self::InternedCompareKey {
-        PtrEqWithMetadata(this.as_ptr())
-    }
 }
 
 #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
@@ -295,9 +288,6 @@ impl InternedCompare for BitSlice {
     fn interned_compare_key_ref(this: &Self) -> Self::InternedCompareKey {
         BitSlicePtrEq(this.as_bitptr(), this.len())
     }
-    fn interned_compare_key_weak(_this: &std::sync::Weak<Self>) -> Self::InternedCompareKey {
-        unreachable!("not currently implementable since Weak<BitSlice> can't be constructed")
-    }
 }
 
 impl InternedCompare for str {
@@ -305,9 +295,6 @@ impl InternedCompare for str {
     fn interned_compare_key_ref(this: &Self) -> Self::InternedCompareKey {
         PtrEqWithMetadata(this)
     }
-    fn interned_compare_key_weak(this: &std::sync::Weak<Self>) -> Self::InternedCompareKey {
-        PtrEqWithMetadata(this.as_ptr())
-    }
 }
 
 pub trait InternContext: 'static + Send + Sync + Hash + Ord + fmt::Debug + Clone {
@@ -408,121 +395,6 @@ impl BitSliceInternContext for GlobalContext {
     }
 }
 
-#[derive(Clone)]
-pub struct AGCContext(std::sync::Arc<TypeIdMap>);
-
-impl AGCContext {
-    pub fn new() -> Self {
-        Self(std::sync::Arc::new(TypeIdMap::new()))
-    }
-}
-
-impl Default for AGCContext {
-    fn default() -> Self {
-        Self::new()
-    }
-}
-
-#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
-pub struct AGCContextId(*const ());
-
-impl fmt::Debug for AGCContextId {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.0.fmt(f)
-    }
-}
-
-impl AGCContext {
-    pub fn id(&self) -> AGCContextId {
-        AGCContextId(std::sync::Arc::as_ptr(&self.0).cast())
-    }
-}
-
-impl Hash for AGCContext {
-    fn hash<H: Hasher>(&self, state: &mut H) {
-        self.id().hash(state);
-    }
-}
-
-impl Ord for AGCContext {
-    fn cmp(&self, other: &Self) -> Ordering {
-        self.id().cmp(&other.id())
-    }
-}
-
-impl PartialOrd for AGCContext {
-    fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
-        Some(self.cmp(other))
-    }
-}
-
-impl Eq for AGCContext {}
-
-impl PartialEq for AGCContext {
-    fn eq(&self, other: &Self) -> bool {
-        self.id().eq(&other.id())
-    }
-}
-
-impl fmt::Debug for AGCContext {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        f.debug_struct("AGCContext")
-            .field("id", &self.id())
-            .finish_non_exhaustive()
-    }
-}
-
-impl InternContext for AGCContext {
-    type InternedImpl<T: ?Sized + 'static + Send + Sync> = std::sync::Weak<T>;
-    type InternedGuardImpl<T: ?Sized + 'static + Send + Sync> = std::sync::Arc<T>;
-    type AllContextsAreIdentical = ConstBool<false>;
-
-    fn interned_compare_key<T: InternedCompare + ?Sized + 'static + Send + Sync>(
-        v: &Self::InternedImpl<T>,
-    ) -> T::InternedCompareKey {
-        T::interned_compare_key_weak(v)
-    }
-    fn guard<T: ?Sized + 'static + Send + Sync>(
-        v: &Self::InternedImpl<T>,
-    ) -> Self::InternedGuardImpl<T> {
-        v.upgrade().expect("expired")
-    }
-    fn try_guard<T: ?Sized + 'static + Send + Sync>(
-        v: &Self::InternedImpl<T>,
-    ) -> Option<Self::InternedGuardImpl<T>> {
-        v.upgrade()
-    }
-    fn unguard<T: ?Sized + 'static + Send + Sync>(
-        v: &Self::InternedGuardImpl<T>,
-    ) -> Self::InternedImpl<T> {
-        std::sync::Arc::downgrade(v)
-    }
-    fn alloc_str(&self, value: Cow<'_, str>) -> Self::InternedGuardImpl<str> {
-        match value {
-            Cow::Borrowed(value) => value.into(),
-            Cow::Owned(value) => value.into(),
-        }
-    }
-    fn alloc_slice<T: Clone + Send + Sync + 'static>(
-        &self,
-        value: Cow<'_, [T]>,
-    ) -> Self::InternedGuardImpl<[T]> {
-        match value {
-            Cow::Borrowed(value) => value.into(),
-            Cow::Owned(value) => value.into(),
-        }
-    }
-    fn alloc_sized<T: Clone + Send + Sync + 'static>(
-        &self,
-        value: Cow<'_, T>,
-    ) -> Self::InternedGuardImpl<T> {
-        std::sync::Arc::new(value.into_owned())
-    }
-    fn interner<T: ?Sized + Send + Sync + 'static>(&self) -> &Interner<T, Self> {
-        self.0.get_or_insert_default()
-    }
-}
-
 pub trait Intern<C: InternContext = GlobalContext>: Any + Send + Sync {
     fn intern_with_ctx(&self, context: &C) -> Interned<Self, C>;
     fn intern_sized_with_ctx(self, context: &C) -> Interned<Self, C>

From f12322aa2a858533cc413048f2f42350b596e515 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 7 Oct 2024 21:33:56 -0700
Subject: [PATCH 059/190] remove interning contexts

---
 .../src/hdl_bundle.rs                         |   4 +-
 .../src/hdl_type_common.rs                    |   6 +-
 crates/fayalite/src/array.rs                  |   6 +-
 crates/fayalite/src/bundle.rs                 |   2 +-
 crates/fayalite/src/expr/ops.rs               |   8 +-
 crates/fayalite/src/int.rs                    |   2 +-
 crates/fayalite/src/intern.rs                 | 575 +++++-------------
 crates/fayalite/src/ty.rs                     |   2 +-
 8 files changed, 154 insertions(+), 451 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
index f3a589a..b13aa08 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
@@ -686,7 +686,7 @@ impl ToTokens for ParsedBundle {
                     let __retval = #mask_type_match_variant_ident {
                         #(#match_variant_body_fields)*
                     };
-                    ::fayalite::intern::Interned::<_>::into_inner(::fayalite::intern::Intern::intern_sized(__retval))
+                    ::fayalite::intern::Interned::into_inner(::fayalite::intern::Intern::intern_sized(__retval))
                 }
             }
             #[automatically_derived]
@@ -761,7 +761,7 @@ impl ToTokens for ParsedBundle {
                     let __retval = #match_variant_ident {
                         #(#match_variant_body_fields)*
                     };
-                    ::fayalite::intern::Interned::<_>::into_inner(::fayalite::intern::Intern::intern_sized(__retval))
+                    ::fayalite::intern::Interned::into_inner(::fayalite::intern::Intern::intern_sized(__retval))
                 }
             }
         }
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
index e7561fe..239f32b 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
@@ -2718,7 +2718,7 @@ impl ParsedGenerics {
                             type Output = #next_target #next_type_generics;
 
                             fn index(&self, #param_token: #index_type) -> &Self::Output {
-                                ::fayalite::intern::Interned::<_>::into_inner(
+                                ::fayalite::intern::Interned::into_inner(
                                     ::fayalite::intern::Intern::intern_sized(#output_expr),
                                 )
                             }
@@ -2778,7 +2778,7 @@ impl ParsedGenerics {
                                 type Output = #next_target #next_target_args;
 
                                 fn index(&self, #param_token: #param_ident) -> &Self::Output {
-                                    ::fayalite::intern::Interned::<_>::into_inner(
+                                    ::fayalite::intern::Interned::into_inner(
                                         ::fayalite::intern::Intern::intern_sized(#output_expr),
                                     )
                                 }
@@ -2848,7 +2848,7 @@ impl ParsedGenerics {
                             type Output = #next_target #next_target_args;
 
                             fn index(&self, #param_token: __Param) -> &Self::Output {
-                                ::fayalite::intern::Interned::<_>::into_inner(
+                                ::fayalite::intern::Interned::into_inner(
                                     ::fayalite::intern::Intern::intern_sized(#output_expr),
                                 )
                             }
diff --git a/crates/fayalite/src/array.rs b/crates/fayalite/src/array.rs
index d543322..a3aea79 100644
--- a/crates/fayalite/src/array.rs
+++ b/crates/fayalite/src/array.rs
@@ -187,7 +187,7 @@ impl<T: Type, Len: Size> TypeWithDeref for ArrayType<T, Len> {
         let base = Expr::as_dyn_array(*this);
         let base_ty = Expr::ty(base);
         let retval = Vec::from_iter((0..base_ty.len()).map(|i| ArrayIndex::new(base, i).to_expr()));
-        Interned::<_>::into_inner(Intern::intern_sized(
+        Interned::into_inner(Intern::intern_sized(
             Len::ArrayMatch::<T>::try_from(retval)
                 .ok()
                 .expect("unreachable"),
@@ -202,7 +202,7 @@ impl<T: Type> Index<T> for ArrayWithoutGenerics {
     type Output = ArrayWithoutLen<T>;
 
     fn index(&self, element: T) -> &Self::Output {
-        Interned::<_>::into_inner(Intern::intern_sized(ArrayWithoutLen { element }))
+        Interned::into_inner(Intern::intern_sized(ArrayWithoutLen { element }))
     }
 }
 
@@ -215,6 +215,6 @@ impl<T: Type, L: SizeType> Index<L> for ArrayWithoutLen<T> {
     type Output = ArrayType<T, L::Size>;
 
     fn index(&self, len: L) -> &Self::Output {
-        Interned::<_>::into_inner(Intern::intern_sized(ArrayType::new(self.element, len)))
+        Interned::into_inner(Intern::intern_sized(ArrayType::new(self.element, len)))
     }
 }
diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs
index 95c87f9..199c2b2 100644
--- a/crates/fayalite/src/bundle.rs
+++ b/crates/fayalite/src/bundle.rs
@@ -377,7 +377,7 @@ macro_rules! impl_tuples {
         impl<$($T: Type,)*> TypeWithDeref for ($($T,)*) {
             fn expr_deref(this: &Expr<Self>) -> &Self::MatchVariant {
                 let _ = this;
-                Interned::<_>::into_inner(($(Expr::field(*this, stringify!($num)),)*).intern_sized())
+                Interned::into_inner(($(Expr::field(*this, stringify!($num)),)*).intern_sized())
             }
         }
         impl<$($T: StaticType,)*> StaticType for ($($T,)*) {
diff --git a/crates/fayalite/src/expr/ops.rs b/crates/fayalite/src/expr/ops.rs
index 6069f20..3579641 100644
--- a/crates/fayalite/src/expr/ops.rs
+++ b/crates/fayalite/src/expr/ops.rs
@@ -2057,7 +2057,7 @@ impl<ElementType: Type, Len: Size> ExprIndex<usize> for ArrayType<ElementType, L
 
     #[track_caller]
     fn expr_index(this: &Expr<Self>, index: usize) -> &Expr<Self::Output> {
-        Interned::<_>::into_inner(
+        Interned::into_inner(
             ArrayIndex::<ElementType>::new(Expr::as_dyn_array(*this), index)
                 .to_expr()
                 .intern_sized(),
@@ -2154,7 +2154,7 @@ impl<ElementType: Type, Len: Size, Width: Size> ExprIndex<Expr<UIntType<Width>>>
     type Output = ElementType;
 
     fn expr_index(this: &Expr<Self>, index: Expr<UIntType<Width>>) -> &Expr<Self::Output> {
-        Interned::<_>::into_inner(
+        Interned::into_inner(
             DynArrayIndex::<ElementType>::new(Expr::as_dyn_array(*this), Expr::as_dyn_int(index))
                 .to_expr()
                 .intern_sized(),
@@ -2279,7 +2279,7 @@ macro_rules! impl_int_slice {
                 let base = Expr::as_dyn_int(*this);
                 let base_ty = Expr::ty(base);
                 let range = base_ty.slice_index_to_range(index);
-                Interned::<_>::into_inner($name::new(base, range).to_expr().intern_sized())
+                Interned::into_inner($name::new(base, range).to_expr().intern_sized())
             }
         }
 
@@ -2291,7 +2291,7 @@ macro_rules! impl_int_slice {
                 let base = Expr::as_dyn_int(*this);
                 let base_ty = Expr::ty(base);
                 assert!(index < base_ty.width());
-                Interned::<_>::into_inner(
+                Interned::into_inner(
                     $name::new(base, index..(index + 1))
                         .to_expr()
                         .cast_to_static::<Bool>()
diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index e0d258a..f529198 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -301,7 +301,7 @@ macro_rules! impl_int {
             type Output = $name<Width::Size>;
 
             fn index(&self, width: Width) -> &Self::Output {
-                Interned::<_>::into_inner(Intern::intern_sized($name::new(width)))
+                Interned::into_inner(Intern::intern_sized($name::new(width)))
             }
         }
 
diff --git a/crates/fayalite/src/intern.rs b/crates/fayalite/src/intern.rs
index c38f26f..3780ad3 100644
--- a/crates/fayalite/src/intern.rs
+++ b/crates/fayalite/src/intern.rs
@@ -1,10 +1,7 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 #![allow(clippy::type_complexity)]
-use crate::{
-    intern::type_map::TypeIdMap,
-    util::{ConstBool, GenericConstBool},
-};
+use crate::intern::type_map::TypeIdMap;
 use bitvec::{ptr::BitPtr, slice::BitSlice, vec::BitVec};
 use hashbrown::{hash_map::RawEntryMut, HashMap, HashTable};
 use serde::{Deserialize, Serialize};
@@ -297,221 +294,94 @@ impl InternedCompare for str {
     }
 }
 
-pub trait InternContext: 'static + Send + Sync + Hash + Ord + fmt::Debug + Clone {
-    type InternedImpl<T: ?Sized + 'static + Send + Sync>: 'static + Send + Sync + Clone;
-    type InternedGuardImpl<T: ?Sized + 'static + Send + Sync>: 'static
-        + Send
-        + Sync
-        + Clone
-        + Borrow<T>;
-    type AllContextsAreIdentical: GenericConstBool;
-    fn interned_compare_key<T: InternedCompare + ?Sized + 'static + Send + Sync>(
-        v: &Self::InternedImpl<T>,
-    ) -> T::InternedCompareKey {
-        T::interned_compare_key_ref(Self::guard(v).borrow())
+pub trait Intern: Any + Send + Sync {
+    fn intern(&self) -> Interned<Self>;
+    fn intern_sized(self) -> Interned<Self>
+    where
+        Self: Clone,
+    {
+        Self::intern_owned(self)
     }
-    fn guard<T: ?Sized + 'static + Send + Sync>(
-        v: &Self::InternedImpl<T>,
-    ) -> Self::InternedGuardImpl<T>;
-    fn try_guard<T: ?Sized + 'static + Send + Sync>(
-        v: &Self::InternedImpl<T>,
-    ) -> Option<Self::InternedGuardImpl<T>>;
-    fn into_guard<T: ?Sized + 'static + Send + Sync>(
-        v: Self::InternedImpl<T>,
-    ) -> Self::InternedGuardImpl<T> {
-        Self::guard(&v)
+    fn intern_owned(this: <Self as ToOwned>::Owned) -> Interned<Self>
+    where
+        Self: ToOwned,
+    {
+        Self::intern_cow(Cow::Owned(this))
     }
-    fn unguard<T: ?Sized + 'static + Send + Sync>(
-        v: &Self::InternedGuardImpl<T>,
-    ) -> Self::InternedImpl<T>;
-    fn unguard_move<T: ?Sized + 'static + Send + Sync>(
-        v: Self::InternedGuardImpl<T>,
-    ) -> Self::InternedImpl<T> {
-        Self::unguard(&v)
+    fn intern_cow(this: Cow<'_, Self>) -> Interned<Self>
+    where
+        Self: ToOwned,
+    {
+        this.intern()
     }
-    fn alloc_str(&self, value: Cow<'_, str>) -> Self::InternedGuardImpl<str>;
-    fn alloc_slice<T: Clone + Send + Sync + 'static>(
-        &self,
-        value: Cow<'_, [T]>,
-    ) -> Self::InternedGuardImpl<[T]>;
-    fn alloc_sized<T: Clone + Send + Sync + 'static>(
-        &self,
-        value: Cow<'_, T>,
-    ) -> Self::InternedGuardImpl<T>;
-    fn interner<T: ?Sized + Send + Sync + 'static>(&self) -> &Interner<T, Self>;
 }
 
-pub trait BitSliceInternContext: InternContext {
-    fn alloc_bit_slice(&self, value: Cow<'_, BitSlice>) -> Self::InternedGuardImpl<BitSlice>;
+pub struct Interner<T: ?Sized + 'static + Send + Sync> {
+    map: Mutex<HashMap<&'static T, ()>>,
 }
 
-#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)]
-pub struct GlobalContext;
-
-impl InternContext for GlobalContext {
-    type InternedImpl<T: ?Sized + 'static + Send + Sync> = &'static T;
-    type InternedGuardImpl<T: ?Sized + 'static + Send + Sync> = &'static T;
-    type AllContextsAreIdentical = ConstBool<true>;
-
-    fn guard<T: ?Sized + 'static + Send + Sync>(
-        v: &Self::InternedImpl<T>,
-    ) -> Self::InternedGuardImpl<T> {
-        *v
-    }
-    fn try_guard<T: ?Sized + 'static + Send + Sync>(
-        v: &Self::InternedImpl<T>,
-    ) -> Option<Self::InternedGuardImpl<T>> {
-        Some(*v)
-    }
-    fn unguard<T: ?Sized + 'static + Send + Sync>(
-        v: &Self::InternedGuardImpl<T>,
-    ) -> Self::InternedImpl<T> {
-        *v
-    }
-    fn alloc_str(&self, value: Cow<'_, str>) -> Self::InternedGuardImpl<str> {
-        value.into_owned().leak()
-    }
-    fn alloc_slice<T: Clone + Send + Sync + 'static>(
-        &self,
-        value: Cow<'_, [T]>,
-    ) -> Self::InternedGuardImpl<[T]> {
-        value.into_owned().leak()
-    }
-    fn alloc_sized<T: Clone + Send + Sync + 'static>(
-        &self,
-        value: Cow<'_, T>,
-    ) -> Self::InternedGuardImpl<T> {
-        Box::leak(Box::new(value.into_owned()))
-    }
-    fn interner<T: ?Sized + 'static + Send + Sync>(&self) -> &Interner<T, Self> {
+impl<T: ?Sized + 'static + Send + Sync> Interner<T> {
+    fn get() -> &'static Interner<T> {
         static TYPE_ID_MAP: TypeIdMap = TypeIdMap::new();
         TYPE_ID_MAP.get_or_insert_default()
     }
 }
 
-impl BitSliceInternContext for GlobalContext {
-    fn alloc_bit_slice(&self, value: Cow<'_, BitSlice>) -> Self::InternedGuardImpl<BitSlice> {
-        value.into_owned().leak()
-    }
-}
-
-pub trait Intern<C: InternContext = GlobalContext>: Any + Send + Sync {
-    fn intern_with_ctx(&self, context: &C) -> Interned<Self, C>;
-    fn intern_sized_with_ctx(self, context: &C) -> Interned<Self, C>
-    where
-        Self: Clone,
-    {
-        Self::intern_owned_with_ctx(self, context)
-    }
-    fn intern_owned_with_ctx(this: <Self as ToOwned>::Owned, context: &C) -> Interned<Self, C>
-    where
-        Self: ToOwned,
-    {
-        Self::intern_cow_with_ctx(Cow::Owned(this), context)
-    }
-    fn intern_cow_with_ctx(this: Cow<'_, Self>, context: &C) -> Interned<Self, C>
-    where
-        Self: ToOwned,
-    {
-        this.intern_with_ctx(context)
-    }
-    fn intern(&self) -> Interned<Self, C>
-    where
-        C: InternContext<AllContextsAreIdentical = ConstBool<true>> + Default,
-    {
-        self.intern_with_ctx(&C::default())
-    }
-    fn intern_sized(self) -> Interned<Self, C>
-    where
-        Self: Clone,
-        C: InternContext<AllContextsAreIdentical = ConstBool<true>> + Default,
-    {
-        self.intern_sized_with_ctx(&C::default())
-    }
-    fn intern_owned(this: <Self as ToOwned>::Owned) -> Interned<Self, C>
-    where
-        Self: ToOwned,
-        C: InternContext<AllContextsAreIdentical = ConstBool<true>> + Default,
-    {
-        Self::intern_owned_with_ctx(this, &C::default())
-    }
-    fn intern_cow(this: Cow<'_, Self>) -> Interned<Self, C>
-    where
-        Self: ToOwned,
-        C: InternContext<AllContextsAreIdentical = ConstBool<true>> + Default,
-    {
-        Self::intern_cow_with_ctx(this, &C::default())
-    }
-}
-
-pub struct Interner<T: ?Sized + 'static + Send + Sync, C: InternContext> {
-    map: Mutex<HashMap<C::InternedGuardImpl<T>, ()>>,
-    _phantom: PhantomData<fn(&C)>,
-}
-
-impl<T: ?Sized + 'static + Send + Sync, C: InternContext> Default for Interner<T, C> {
+impl<T: ?Sized + 'static + Send + Sync> Default for Interner<T> {
     fn default() -> Self {
         Self {
             map: Default::default(),
-            _phantom: Default::default(),
         }
     }
 }
 
-impl<T: ?Sized + 'static + Send + Sync + Hash + Eq + ToOwned, C: InternContext> Interner<T, C> {
-    fn intern<F: FnOnce(Cow<'_, T>) -> C::InternedGuardImpl<T>>(
+impl<T: ?Sized + 'static + Send + Sync + Hash + Eq + ToOwned> Interner<T> {
+    fn intern<F: FnOnce(Cow<'_, T>) -> &'static T>(
         &self,
         alloc: F,
         value: Cow<'_, T>,
-    ) -> Interned<T, C> {
+    ) -> Interned<T> {
         let mut map = self.map.lock().unwrap();
         let hasher = map.hasher().clone();
         let hash = hasher.hash_one(&*value);
-        let inner = match map
-            .raw_entry_mut()
-            .from_hash(hash, |k| k.borrow() == &*value)
-        {
-            RawEntryMut::Occupied(entry) => C::unguard(entry.key()),
-            RawEntryMut::Vacant(entry) => C::unguard(
-                entry
-                    .insert_with_hasher(hash, alloc(value), (), |k| hasher.hash_one(k.borrow()))
-                    .0,
-            ),
+        let inner = match map.raw_entry_mut().from_hash(hash, |k| **k == *value) {
+            RawEntryMut::Occupied(entry) => *entry.key(),
+            RawEntryMut::Vacant(entry) => {
+                *entry
+                    .insert_with_hasher(hash, alloc(value), (), |k| hasher.hash_one(&**k))
+                    .0
+            }
         };
-        Interned {
-            inner,
-            _phantom: PhantomData,
-        }
+        Interned { inner }
     }
 }
 
-impl<T: Clone + 'static + Send + Sync + Hash + Eq, C: InternContext> Interner<T, C> {
-    fn intern_sized(&self, context: &C, value: Cow<'_, T>) -> Interned<T, C> {
-        self.intern(|value| context.alloc_sized(value), value)
+impl<T: Clone + 'static + Send + Sync + Hash + Eq> Interner<T> {
+    fn intern_sized(&self, value: Cow<'_, T>) -> Interned<T> {
+        self.intern(|value| Box::leak(Box::new(value.into_owned())), value)
     }
 }
 
-impl<T: Clone + 'static + Send + Sync + Hash + Eq, C: InternContext> Interner<[T], C> {
-    fn intern_slice(&self, context: &C, value: Cow<'_, [T]>) -> Interned<[T], C> {
-        self.intern(|value| context.alloc_slice(value), value)
+impl<T: Clone + 'static + Send + Sync + Hash + Eq> Interner<[T]> {
+    fn intern_slice(&self, value: Cow<'_, [T]>) -> Interned<[T]> {
+        self.intern(|value| value.into_owned().leak(), value)
     }
 }
 
-impl<C: BitSliceInternContext> Interner<BitSlice, C> {
-    fn intern_bit_slice(&self, context: &C, value: Cow<'_, BitSlice>) -> Interned<BitSlice, C> {
-        self.intern(|value| context.alloc_bit_slice(value), value)
+impl Interner<BitSlice> {
+    fn intern_bit_slice(&self, value: Cow<'_, BitSlice>) -> Interned<BitSlice> {
+        self.intern(|value| value.into_owned().leak(), value)
     }
 }
 
-impl<C: InternContext> Interner<str, C> {
-    fn intern_str(&self, context: &C, value: Cow<'_, str>) -> Interned<str, C> {
-        self.intern(|value| context.alloc_str(value), value)
+impl Interner<str> {
+    fn intern_str(&self, value: Cow<'_, str>) -> Interned<str> {
+        self.intern(|value| value.into_owned().leak(), value)
     }
 }
 
-pub struct Interned<T: ?Sized + 'static + Send + Sync, C: InternContext = GlobalContext> {
-    inner: C::InternedImpl<T>,
-    _phantom: PhantomData<&'static C>,
+pub struct Interned<T: ?Sized + 'static + Send + Sync> {
+    inner: &'static T,
 }
 
 macro_rules! forward_fmt_trait {
@@ -522,23 +392,9 @@ macro_rules! forward_fmt_trait {
             }
         }
 
-        impl<T: ?Sized + 'static + Send + Sync + fmt::$Tr, C: InternContext> fmt::$Tr
-            for Interned<T, C>
-        {
+        impl<T: ?Sized + 'static + Send + Sync + fmt::$Tr> fmt::$Tr for Interned<T> {
             fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-                if let Some(guard) = C::try_guard(&self.inner) {
-                    guard.borrow().fmt(f)
-                } else {
-                    write!(f, "<Expired>")
-                }
-            }
-        }
-
-        impl<T: ?Sized + 'static + Send + Sync + fmt::$Tr, C: InternContext> fmt::$Tr
-            for Guard<T, C>
-        {
-            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-                self.inner.borrow().fmt(f)
+                self.inner.fmt(f)
             }
         }
     };
@@ -554,18 +410,16 @@ forward_fmt_trait!(UpperExp);
 forward_fmt_trait!(UpperHex);
 
 #[derive(Clone, Debug)]
-pub struct InternedSliceIter<T: Clone + 'static + Send + Sync, C: InternContext> {
-    slice: Interned<[T], C>,
+pub struct InternedSliceIter<T: Clone + 'static + Send + Sync> {
+    slice: Interned<[T]>,
     index: std::ops::Range<usize>,
 }
 
-impl<T: Clone + 'static + Send + Sync, C: InternContext> Iterator for InternedSliceIter<T, C> {
+impl<T: Clone + 'static + Send + Sync> Iterator for InternedSliceIter<T> {
     type Item = T;
 
     fn next(&mut self) -> Option<Self::Item> {
-        self.index
-            .next()
-            .map(|index| self.slice.guard()[index].clone())
+        self.index.next().map(|index| self.slice[index].clone())
     }
 
     fn size_hint(&self) -> (usize, Option<usize>) {
@@ -573,233 +427,186 @@ impl<T: Clone + 'static + Send + Sync, C: InternContext> Iterator for InternedSl
     }
 }
 
-impl<T: Clone + 'static + Send + Sync, C: InternContext> DoubleEndedIterator
-    for InternedSliceIter<T, C>
-{
+impl<T: Clone + 'static + Send + Sync> DoubleEndedIterator for InternedSliceIter<T> {
     fn next_back(&mut self) -> Option<Self::Item> {
         self.index
             .next_back()
-            .map(|index| self.slice.guard()[index].clone())
+            .map(|index| self.slice[index].clone())
     }
 }
 
-impl<T: Clone + 'static + Send + Sync, C: InternContext> FusedIterator for InternedSliceIter<T, C> {}
+impl<T: Clone + 'static + Send + Sync> FusedIterator for InternedSliceIter<T> {}
 
-impl<T: Clone + 'static + Send + Sync, C: InternContext> ExactSizeIterator
-    for InternedSliceIter<T, C>
-{
-}
+impl<T: Clone + 'static + Send + Sync> ExactSizeIterator for InternedSliceIter<T> {}
 
-impl<T: Clone + 'static + Send + Sync, C: InternContext> IntoIterator for Interned<[T], C> {
+impl<T: Clone + 'static + Send + Sync> IntoIterator for Interned<[T]> {
     type Item = T;
-    type IntoIter = InternedSliceIter<T, C>;
+    type IntoIter = InternedSliceIter<T>;
 
     fn into_iter(self) -> Self::IntoIter {
         InternedSliceIter {
-            index: 0..self.guard().len(),
+            index: 0..self.len(),
             slice: self,
         }
     }
 }
 
-impl<'a, T: 'static + Send + Sync, C: InternContext> IntoIterator for &'a Interned<[T], C>
-where
-    C::InternedImpl<[T]>: Borrow<[T]>,
-{
+impl<'a, T: 'static + Send + Sync> IntoIterator for &'a Interned<[T]> {
     type Item = &'a T;
     type IntoIter = std::slice::Iter<'a, T>;
 
     fn into_iter(self) -> Self::IntoIter {
-        self.inner.borrow().iter()
+        self.inner.iter()
     }
 }
 
-impl<'a, T: 'static + Send + Sync, C: InternContext> IntoIterator for &'a mut Interned<[T], C>
-where
-    C::InternedImpl<[T]>: Borrow<[T]>,
-{
+impl<'a, T: 'static + Send + Sync> IntoIterator for &'a mut Interned<[T]> {
     type Item = &'a T;
     type IntoIter = std::slice::Iter<'a, T>;
 
     fn into_iter(self) -> Self::IntoIter {
-        self.inner.borrow().iter()
+        self.inner.iter()
     }
 }
 
-impl<I: Clone, C: InternContext<AllContextsAreIdentical = ConstBool<true>> + Default>
-    FromIterator<I> for Interned<[I], C>
+impl<I: Clone> FromIterator<I> for Interned<[I]>
 where
-    [I]: Intern<C>,
+    [I]: Intern,
 {
     fn from_iter<T: IntoIterator<Item = I>>(iter: T) -> Self {
         Intern::intern_owned(Vec::from_iter(iter))
     }
 }
 
-impl<T: 'static + Clone + Send + Sync, C: InternContext> From<Interned<[T], C>> for Vec<T> {
-    fn from(value: Interned<[T], C>) -> Self {
-        Vec::from(&*value.guard())
+impl<T: 'static + Clone + Send + Sync> From<Interned<[T]>> for Vec<T> {
+    fn from(value: Interned<[T]>) -> Self {
+        Vec::from(&*value)
     }
 }
 
-impl<T: 'static + Clone + Send + Sync, C: InternContext> From<Interned<[T], C>> for Box<[T]> {
-    fn from(value: Interned<[T], C>) -> Self {
-        Box::from(&*value.guard())
+impl<T: 'static + Clone + Send + Sync> From<Interned<[T]>> for Box<[T]> {
+    fn from(value: Interned<[T]>) -> Self {
+        Box::from(&*value)
     }
 }
 
-impl<C: InternContext> From<Interned<str, C>> for String {
-    fn from(value: Interned<str, C>) -> Self {
-        String::from(&*value.guard())
+impl From<Interned<str>> for String {
+    fn from(value: Interned<str>) -> Self {
+        String::from(&*value)
     }
 }
 
-impl<I, C: InternContext<AllContextsAreIdentical = ConstBool<true>> + Default> Default
-    for Interned<[I], C>
+impl<I> Default for Interned<[I]>
 where
-    [I]: Intern<C>,
+    [I]: Intern,
 {
     fn default() -> Self {
         [][..].intern()
     }
 }
 
-impl<C: InternContext<AllContextsAreIdentical = ConstBool<true>> + Default> Default
-    for Interned<str, C>
-where
-    str: Intern<C>,
-{
+impl Default for Interned<str> {
     fn default() -> Self {
         "".intern()
     }
 }
 
-impl<C: BitSliceInternContext<AllContextsAreIdentical = ConstBool<true>> + Default> Default
-    for Interned<BitSlice, C>
-where
-    BitSlice: Intern<C>,
-{
+impl Default for Interned<BitSlice> {
     fn default() -> Self {
         <&BitSlice>::default().intern()
     }
 }
 
-impl<I: Clone + Default, C: InternContext<AllContextsAreIdentical = ConstBool<true>> + Default>
-    Default for Interned<I, C>
+impl<I: Clone + Default> Default for Interned<I>
 where
-    I: Intern<C>,
+    I: Intern,
 {
     fn default() -> Self {
         I::default().intern()
     }
 }
 
-impl<T: ?Sized + 'static + Send + Sync, C: InternContext> Interned<T, C> {
+impl<T: ?Sized + 'static + Send + Sync> Interned<T> {
     pub fn cast_unchecked<U: ?Sized + 'static + Send + Sync>(
         this: Self,
-        f: impl FnOnce(C::InternedImpl<T>) -> C::InternedImpl<U>,
-    ) -> Interned<U, C> {
+        f: impl FnOnce(&'static T) -> &'static U,
+    ) -> Interned<U> {
         Interned {
             inner: f(this.inner),
-            _phantom: PhantomData,
         }
     }
     pub fn try_cast_unchecked<U: ?Sized + 'static + Send + Sync, E>(
         this: Self,
-        f: impl FnOnce(C::InternedImpl<T>) -> Result<C::InternedImpl<U>, E>,
-    ) -> Result<Interned<U, C>, E> {
+        f: impl FnOnce(&'static T) -> Result<&'static U, E>,
+    ) -> Result<Interned<U>, E> {
         Ok(Interned {
             inner: f(this.inner)?,
-            _phantom: PhantomData,
         })
     }
-    pub fn into_inner(this: Self) -> C::InternedImpl<T> {
+    pub fn into_inner(this: Self) -> &'static T {
         this.inner
     }
-    pub fn get_ref(this: &Self) -> &C::InternedImpl<T> {
+    pub fn get_ref(this: &Self) -> &&'static T {
         &this.inner
     }
-    pub fn guard(&self) -> Guard<T, C> {
-        Guard {
-            inner: C::guard(&self.inner),
-            _phantom: PhantomData,
-        }
-    }
 }
 
-impl<T: ?Sized + 'static + Send + Sync, C: InternContext> Clone for Interned<T, C> {
+impl<T: ?Sized + 'static + Send + Sync> Clone for Interned<T> {
     fn clone(&self) -> Self {
-        Interned {
-            inner: self.inner.clone(),
-            _phantom: PhantomData,
-        }
+        *self
     }
 }
 
-impl<T: ?Sized + 'static + Send + Sync, C: InternContext> Copy for Interned<T, C> where
-    C::InternedImpl<T>: Copy
-{
-}
+impl<T: ?Sized + 'static + Send + Sync> Copy for Interned<T> where &'static T: Copy {}
 
-impl<T: ?Sized + 'static + Send + Sync, C: InternContext> Deref for Interned<T, C>
+impl<T: ?Sized + 'static + Send + Sync> Deref for Interned<T>
 where
-    C::InternedImpl<T>: Borrow<T>,
+    &'static T: Borrow<T>,
 {
     type Target = T;
 
     fn deref(&self) -> &Self::Target {
-        self.inner.borrow()
+        self.inner
     }
 }
 
-impl<T: ?Sized + 'static + Send + Sync + InternedCompare, C: InternContext> PartialEq
-    for Interned<T, C>
-{
+impl<T: ?Sized + 'static + Send + Sync + InternedCompare> PartialEq for Interned<T> {
     fn eq(&self, other: &Self) -> bool {
-        <C as InternContext>::interned_compare_key(&self.inner)
-            == <C as InternContext>::interned_compare_key(&other.inner)
+        T::interned_compare_key_ref(self.inner) == T::interned_compare_key_ref(other.inner)
     }
 }
 
-impl<T: ?Sized + 'static + Send + Sync + InternedCompare, C: InternContext> Eq for Interned<T, C> {}
+impl<T: ?Sized + 'static + Send + Sync + InternedCompare> Eq for Interned<T> {}
 
-impl<T: ?Sized + 'static + Send + Sync + InternedCompare, C: InternContext> PartialOrd
-    for Interned<T, C>
-{
+impl<T: ?Sized + 'static + Send + Sync + InternedCompare> PartialOrd for Interned<T> {
     fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
         Some(self.cmp(other))
     }
 }
 
-impl<T: ?Sized + 'static + Send + Sync + InternedCompare, C: InternContext> Ord for Interned<T, C> {
+impl<T: ?Sized + 'static + Send + Sync + InternedCompare> Ord for Interned<T> {
     fn cmp(&self, other: &Self) -> Ordering {
-        <C as InternContext>::interned_compare_key(&self.inner)
-            .cmp(&<C as InternContext>::interned_compare_key(&other.inner))
+        T::interned_compare_key_ref(self.inner).cmp(&T::interned_compare_key_ref(other.inner))
     }
 }
 
-impl<T: ?Sized + 'static + Send + Sync + InternedCompare, C: InternContext> Hash
-    for Interned<T, C>
-{
+impl<T: ?Sized + 'static + Send + Sync + InternedCompare> Hash for Interned<T> {
     fn hash<H: Hasher>(&self, state: &mut H) {
-        <C as InternContext>::interned_compare_key(&self.inner).hash(state);
+        T::interned_compare_key_ref(self.inner).hash(state);
     }
 }
 
-impl<T: ?Sized + 'static + Send + Sync + Serialize, C: InternContext> Serialize for Interned<T, C> {
+impl<T: ?Sized + 'static + Send + Sync + Serialize> Serialize for Interned<T> {
     fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
     where
         S: serde::Serializer,
     {
-        self.guard().serialize(serializer)
+        T::serialize(self, serializer)
     }
 }
 
-impl<
-        'de,
-        T: 'static + Send + Sync + Deserialize<'de> + Clone + Intern<C>,
-        C: InternContext<AllContextsAreIdentical = ConstBool<true>> + Default,
-    > Deserialize<'de> for Interned<T, C>
+impl<'de, T: 'static + Send + Sync + Deserialize<'de> + Clone + Intern> Deserialize<'de>
+    for Interned<T>
 {
     fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
     where
@@ -809,13 +616,9 @@ impl<
     }
 }
 
-impl<
-        'de,
-        T: 'static + Send + Sync + Clone,
-        C: InternContext<AllContextsAreIdentical = ConstBool<true>> + Default,
-    > Deserialize<'de> for Interned<[T], C>
+impl<'de, T: 'static + Send + Sync + Clone> Deserialize<'de> for Interned<[T]>
 where
-    [T]: Intern<C>,
+    [T]: Intern,
     Vec<T>: Deserialize<'de>,
 {
     fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
@@ -826,11 +629,7 @@ where
     }
 }
 
-impl<'de, C: BitSliceInternContext<AllContextsAreIdentical = ConstBool<true>> + Default>
-    Deserialize<'de> for Interned<BitSlice, C>
-where
-    BitSlice: Intern<C>,
-{
+impl<'de> Deserialize<'de> for Interned<BitSlice> {
     fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
     where
         D: serde::Deserializer<'de>,
@@ -839,11 +638,7 @@ where
     }
 }
 
-impl<'de, C: InternContext<AllContextsAreIdentical = ConstBool<true>> + Default> Deserialize<'de>
-    for Interned<str, C>
-where
-    str: Intern<C>,
-{
+impl<'de> Deserialize<'de> for Interned<str> {
     fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
     where
         D: serde::Deserializer<'de>,
@@ -852,175 +647,83 @@ where
     }
 }
 
-pub struct Guard<T: ?Sized + 'static + Send + Sync, C: InternContext = GlobalContext> {
-    inner: C::InternedGuardImpl<T>,
-    _phantom: PhantomData<&'static C>,
-}
-
-impl<T: ?Sized + 'static + Send + Sync, C: InternContext> Guard<T, C> {
-    pub fn cast_unchecked<U: ?Sized + 'static + Send + Sync>(
-        this: Self,
-        f: impl FnOnce(C::InternedGuardImpl<T>) -> C::InternedGuardImpl<U>,
-    ) -> Guard<U, C> {
-        Guard {
-            inner: f(this.inner),
-            _phantom: PhantomData,
-        }
-    }
-    pub fn try_cast_unchecked<U: ?Sized + 'static + Send + Sync, E>(
-        this: Self,
-        f: impl FnOnce(C::InternedGuardImpl<T>) -> Result<C::InternedGuardImpl<U>, E>,
-    ) -> Result<Guard<U, C>, E> {
-        Ok(Guard {
-            inner: f(this.inner)?,
-            _phantom: PhantomData,
-        })
-    }
-    pub fn into_inner(this: Self) -> C::InternedGuardImpl<T> {
-        this.inner
-    }
-    pub fn get_ref(this: &Self) -> &C::InternedGuardImpl<T> {
-        &this.inner
-    }
-    pub fn unguard(&self) -> Interned<T, C> {
-        Interned {
-            inner: C::unguard(&self.inner),
-            _phantom: PhantomData,
-        }
-    }
-}
-
-impl<T: ?Sized + 'static + Send + Sync, C: InternContext> Clone for Guard<T, C> {
-    fn clone(&self) -> Self {
-        Guard {
-            inner: self.inner.clone(),
-            _phantom: PhantomData,
-        }
-    }
-}
-
-impl<T: ?Sized + 'static + Send + Sync, C: InternContext> Copy for Guard<T, C> where
-    C::InternedGuardImpl<T>: Copy
-{
-}
-
-impl<T: ?Sized + 'static + Send + Sync, C: InternContext> Deref for Guard<T, C> {
-    type Target = T;
-
-    fn deref(&self) -> &Self::Target {
-        self.inner.borrow()
-    }
-}
-
-impl<T: ?Sized + 'static + Send + Sync + InternedCompare, C: InternContext> PartialEq
-    for Guard<T, C>
-{
-    fn eq(&self, other: &Self) -> bool {
-        T::interned_compare_key_ref(self.inner.borrow())
-            == T::interned_compare_key_ref(other.inner.borrow())
-    }
-}
-
-impl<T: ?Sized + 'static + Send + Sync + InternedCompare, C: InternContext> Eq for Guard<T, C> {}
-
-impl<T: ?Sized + 'static + Send + Sync + InternedCompare, C: InternContext> PartialOrd
-    for Guard<T, C>
-{
-    fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
-        Some(self.cmp(other))
-    }
-}
-
-impl<T: ?Sized + 'static + Send + Sync + InternedCompare, C: InternContext> Ord for Guard<T, C> {
-    fn cmp(&self, other: &Self) -> Ordering {
-        T::interned_compare_key_ref(self.inner.borrow())
-            .cmp(&T::interned_compare_key_ref(other.inner.borrow()))
-    }
-}
-
-impl<T: ?Sized + 'static + Send + Sync + InternedCompare, C: InternContext> Hash for Guard<T, C> {
-    fn hash<H: Hasher>(&self, state: &mut H) {
-        T::interned_compare_key_ref(self.inner.borrow()).hash(state);
-    }
-}
-
-impl<T: Clone + Send + Sync + 'static + Hash + Eq, C: InternContext> Intern<C> for T {
-    fn intern_with_ctx(&self, context: &C) -> Interned<Self, C> {
-        Self::intern_cow_with_ctx(Cow::Borrowed(self), context)
+impl<T: Clone + Send + Sync + 'static + Hash + Eq> Intern for T {
+    fn intern(&self) -> Interned<Self> {
+        Self::intern_cow(Cow::Borrowed(self))
     }
 
-    fn intern_owned_with_ctx(this: <Self as ToOwned>::Owned, context: &C) -> Interned<Self, C>
+    fn intern_owned(this: <Self as ToOwned>::Owned) -> Interned<Self>
     where
         Self: ToOwned,
     {
-        Self::intern_cow_with_ctx(Cow::Owned(this), context)
+        Self::intern_cow(Cow::Owned(this))
     }
 
-    fn intern_cow_with_ctx(this: Cow<'_, Self>, context: &C) -> Interned<Self, C>
+    fn intern_cow(this: Cow<'_, Self>) -> Interned<Self>
     where
         Self: ToOwned,
     {
-        context.interner().intern_sized(context, this)
+        Interner::get().intern_sized(this)
     }
 }
 
-impl<T: Clone + Send + Sync + 'static + Hash + Eq, C: InternContext> Intern<C> for [T] {
-    fn intern_with_ctx(&self, context: &C) -> Interned<Self, C> {
-        Self::intern_cow_with_ctx(Cow::Borrowed(self), context)
+impl<T: Clone + Send + Sync + 'static + Hash + Eq> Intern for [T] {
+    fn intern(&self) -> Interned<Self> {
+        Self::intern_cow(Cow::Borrowed(self))
     }
 
-    fn intern_owned_with_ctx(this: <Self as ToOwned>::Owned, context: &C) -> Interned<Self, C>
+    fn intern_owned(this: <Self as ToOwned>::Owned) -> Interned<Self>
     where
         Self: ToOwned,
     {
-        Self::intern_cow_with_ctx(Cow::Owned(this), context)
+        Self::intern_cow(Cow::Owned(this))
     }
 
-    fn intern_cow_with_ctx(this: Cow<'_, Self>, context: &C) -> Interned<Self, C>
+    fn intern_cow(this: Cow<'_, Self>) -> Interned<Self>
     where
         Self: ToOwned,
     {
-        context.interner().intern_slice(context, this)
+        Interner::get().intern_slice(this)
     }
 }
 
-impl<C: BitSliceInternContext> Intern<C> for BitSlice {
-    fn intern_with_ctx(&self, context: &C) -> Interned<Self, C> {
-        Self::intern_cow_with_ctx(Cow::Borrowed(self), context)
+impl Intern for BitSlice {
+    fn intern(&self) -> Interned<Self> {
+        Self::intern_cow(Cow::Borrowed(self))
     }
 
-    fn intern_owned_with_ctx(this: <Self as ToOwned>::Owned, context: &C) -> Interned<Self, C>
+    fn intern_owned(this: <Self as ToOwned>::Owned) -> Interned<Self>
     where
         Self: ToOwned,
     {
-        Self::intern_cow_with_ctx(Cow::Owned(this), context)
+        Self::intern_cow(Cow::Owned(this))
     }
 
-    fn intern_cow_with_ctx(this: Cow<'_, Self>, context: &C) -> Interned<Self, C>
+    fn intern_cow(this: Cow<'_, Self>) -> Interned<Self>
     where
         Self: ToOwned,
     {
-        context.interner().intern_bit_slice(context, this)
+        Interner::get().intern_bit_slice(this)
     }
 }
 
-impl<C: InternContext> Intern<C> for str {
-    fn intern_with_ctx(&self, context: &C) -> Interned<Self, C> {
-        Self::intern_cow_with_ctx(Cow::Borrowed(self), context)
+impl Intern for str {
+    fn intern(&self) -> Interned<Self> {
+        Self::intern_cow(Cow::Borrowed(self))
     }
 
-    fn intern_owned_with_ctx(this: <Self as ToOwned>::Owned, context: &C) -> Interned<Self, C>
+    fn intern_owned(this: <Self as ToOwned>::Owned) -> Interned<Self>
     where
         Self: ToOwned,
     {
-        Self::intern_cow_with_ctx(Cow::Owned(this), context)
+        Self::intern_cow(Cow::Owned(this))
     }
 
-    fn intern_cow_with_ctx(this: Cow<'_, Self>, context: &C) -> Interned<Self, C>
+    fn intern_cow(this: Cow<'_, Self>) -> Interned<Self>
     where
         Self: ToOwned,
     {
-        context.interner().intern_str(context, this)
+        Interner::get().intern_str(this)
     }
 }
 
diff --git a/crates/fayalite/src/ty.rs b/crates/fayalite/src/ty.rs
index 380d2e6..69080c9 100644
--- a/crates/fayalite/src/ty.rs
+++ b/crates/fayalite/src/ty.rs
@@ -330,6 +330,6 @@ impl<T: Type> Index<T> for AsMaskWithoutGenerics {
     type Output = T::MaskType;
 
     fn index(&self, ty: T) -> &Self::Output {
-        Interned::<_>::into_inner(Intern::intern_sized(ty.mask_type()))
+        Interned::into_inner(Intern::intern_sized(ty.mask_type()))
     }
 }

From ed1aea41f31776568aef509157dbb5708b855e3f Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 7 Oct 2024 21:49:18 -0700
Subject: [PATCH 060/190] clean up some clippy warnings

---
 .../fayalite-proc-macros-impl/src/hdl_bundle.rs   |  3 +--
 crates/fayalite-proc-macros-impl/src/hdl_enum.rs  |  2 +-
 .../src/hdl_type_common.rs                        |  6 +++---
 crates/fayalite/src/bundle.rs                     | 10 +++++++++-
 crates/fayalite/src/enum_.rs                      |  9 +++++++--
 crates/fayalite/src/int.rs                        |  4 ++--
 crates/fayalite/src/memory.rs                     |  4 ++--
 crates/fayalite/src/module.rs                     | 15 ++++++++-------
 .../src/module/transform/simplify_enums.rs        | 11 ++++-------
 .../src/module/transform/simplify_memories.rs     |  2 +-
 crates/fayalite/src/util/scoped_ref.rs            |  6 ++++++
 crates/fayalite/tests/module.rs                   |  2 +-
 12 files changed, 45 insertions(+), 29 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
index b13aa08..cf08c7e 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
@@ -58,8 +58,7 @@ impl ParsedBundle {
         }
         *mutability = FieldMutability::None;
         colon_token.get_or_insert(Token![:](ident.span()));
-        let options = errors.unwrap_or_default(HdlAttr::parse_and_take_attr(attrs));
-        options
+        errors.unwrap_or_default(HdlAttr::parse_and_take_attr(attrs))
     }
     fn parse(item: ItemStruct) -> syn::Result<Self> {
         let ItemStruct {
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
index adddd74..1d16177 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
@@ -600,7 +600,7 @@ impl ToTokens for ParsedEnum {
                 static_generics.split_for_impl();
             let static_type_body_variants =
                 Vec::from_iter(variants.iter().map(|ParsedVariant { ident, field, .. }| {
-                    if let Some(_) = field {
+                    if field.is_some() {
                         quote_spanned! {span=>
                             #ident: ::fayalite::ty::StaticType::TYPE,
                         }
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
index 239f32b..e36f68e 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
@@ -1410,7 +1410,7 @@ impl ParseTypes<Path> for ParsedType {
         let mut args = None;
         let segments = Punctuated::from_iter(segments.pairs_mut().map_pair_value_mut(|segment| {
             let PathSegment { ident, arguments } = segment;
-            if let Some(_) = args {
+            if args.is_some() {
                 parser
                     .errors()
                     .error(&ident, "associated types/consts are not yet implemented");
@@ -1594,7 +1594,7 @@ impl ParseTypes<Path> for ParsedConstGenericType {
         let mut args = None;
         let segments = Punctuated::from_iter(segments.pairs_mut().map_pair_value_mut(|segment| {
             let PathSegment { ident, arguments } = segment;
-            if let Some(_) = args {
+            if args.is_some() {
                 parser
                     .errors()
                     .error(&ident, "associated types/consts are not yet implemented");
@@ -3554,7 +3554,7 @@ impl SplitForImpl for Generics {
         Self::TypeGenerics<'_>,
         Self::WhereClause<'_>,
     ) {
-        Generics::split_for_impl(&self)
+        Generics::split_for_impl(self)
     }
 }
 
diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs
index 199c2b2..b338322 100644
--- a/crates/fayalite/src/bundle.rs
+++ b/crates/fayalite/src/bundle.rs
@@ -144,6 +144,12 @@ impl BundleTypePropertiesBuilder {
     }
 }
 
+impl Default for BundleTypePropertiesBuilder {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
 impl Bundle {
     #[track_caller]
     pub fn new(fields: Interned<[BundleField]>) -> Self {
@@ -342,6 +348,7 @@ macro_rules! impl_tuples {
                 std::iter::once(MatchVariantWithoutScope(($(Expr::field(this, stringify!($num)),)*)))
             }
             fn mask_type(&self) -> Self::MaskType {
+                #![allow(clippy::unused_unit)]
                 let ($($var,)*) = self;
                 ($($var.mask_type(),)*)
             }
@@ -350,6 +357,7 @@ macro_rules! impl_tuples {
             }
             #[track_caller]
             fn from_canonical(canonical_type: CanonicalType) -> Self {
+                #![allow(clippy::unused_unit)]
                 let CanonicalType::Bundle(bundle) = canonical_type else {
                     panic!("expected bundle");
                 };
@@ -358,7 +366,7 @@ macro_rules! impl_tuples {
                 };
                 $(let BundleField { name, flipped, ty } = $var;
                 assert_eq!(&*name, stringify!($num));
-                assert_eq!(flipped, false);
+                assert!(!flipped);
                 let $var = $T::from_canonical(ty);)*
                 ($($var,)*)
             }
diff --git a/crates/fayalite/src/enum_.rs b/crates/fayalite/src/enum_.rs
index 13724ef..2ed0b8e 100644
--- a/crates/fayalite/src/enum_.rs
+++ b/crates/fayalite/src/enum_.rs
@@ -169,6 +169,12 @@ impl EnumTypePropertiesBuilder {
     }
 }
 
+impl Default for EnumTypePropertiesBuilder {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
 impl Enum {
     #[track_caller]
     pub fn new(variants: Interned<[EnumVariant]>) -> Self {
@@ -399,9 +405,8 @@ impl<T: Type> HdlOption<T> {
         else {
             unreachable!();
         };
-        let value = f(value).map_err(|e| {
+        let value = f(value).inspect_err(|_| {
             and_then_out.complete(()); // avoid error
-            e
         })?;
         let and_then_out = and_then_out.complete(Expr::ty(value));
         connect(and_then_out, value);
diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index f529198..dd631d0 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -147,7 +147,7 @@ where
 
     fn try_from_usize(v: usize) -> Option<Self::SizeType> {
         if v == VALUE {
-            Some(Self::SizeType::default())
+            Some(ConstUsize)
         } else {
             None
         }
@@ -560,7 +560,7 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
     }
     fn bits_to_expr(bits: Cow<'_, BitSlice>) -> Expr<Self>;
     fn le_bytes_to_expr_wrapping(bytes: &[u8], bit_width: usize) -> Expr<Self> {
-        let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
+        let bitslice = BitSlice::<u8, Lsb0>::from_slice(bytes);
         let bitslice = &bitslice[..bit_width.min(bitslice.len())];
         let mut bits = BitVec::new();
         bits.extend_from_bitslice(bitslice);
diff --git a/crates/fayalite/src/memory.rs b/crates/fayalite/src/memory.rs
index 1762f57..f583a8c 100644
--- a/crates/fayalite/src/memory.rs
+++ b/crates/fayalite/src/memory.rs
@@ -634,7 +634,7 @@ impl<Element: Type, Len: Size> Mem<Element, Len> {
         self.0.source_location
     }
     pub fn array_type(self) -> ArrayType<Element, Len> {
-        self.0.array_type.clone()
+        self.0.array_type
     }
     pub fn initial_value(self) -> Option<Interned<BitSlice>> {
         self.0.initial_value
@@ -987,7 +987,7 @@ impl<Element: Type, Len: Size> MemBuilder<Element, Len> {
     #[allow(clippy::result_unit_err)]
     pub fn get_array_type(&self) -> Result<ArrayType<Element, Len>, ()> {
         Ok(ArrayType::new(
-            self.mem_element_type.clone(),
+            self.mem_element_type,
             Len::from_usize(self.get_depth()?),
         ))
     }
diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index 2ba3800..7d6949c 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -607,6 +607,10 @@ impl BlockStack {
 pub struct Id(NonZeroU64);
 
 impl Id {
+    #[allow(
+        clippy::new_without_default,
+        reason = "returns a different value each time, so there isn't really a default value"
+    )]
     pub fn new() -> Self {
         static NEXT_ID: AtomicU64 = AtomicU64::new(1);
         Self(
@@ -945,7 +949,7 @@ impl From<NormalModuleBody<ModuleBuilding>> for NormalModuleBody {
                     Stmt::Declaration(decl) => {
                         let annotations = annotations_map
                             .remove(&decl)
-                            .map(|v| Intern::intern_owned(v))
+                            .map(Intern::intern_owned)
                             .unwrap_or_default();
                         match decl {
                             StmtDeclaration::Wire(StmtWire {
@@ -1615,10 +1619,7 @@ impl AssertValidityState {
         let module = self.module;
         if block == 0 {
             for module_io in &*module.module_io {
-                self.insert_new_base(
-                    TargetBase::intern_sized(module_io.module_io.clone().into()),
-                    block,
-                );
+                self.insert_new_base(TargetBase::intern_sized(module_io.module_io.into()), block);
             }
         }
         let Block { memories, stmts } = self.blocks[block];
@@ -1934,7 +1935,7 @@ impl ModuleBuilder {
         let module_io = module_io.canonical();
         let mut impl_ = self.impl_.borrow_mut();
         let impl_ = &mut *impl_;
-        impl_.io_indexes.insert(module_io.clone(), impl_.io.len());
+        impl_.io_indexes.insert(module_io, impl_.io.len());
         impl_.io.push(AnnotatedModuleIO {
             annotations: vec![],
             module_io,
@@ -2478,7 +2479,7 @@ pub fn memory_array_with_loc<Element: Type, Len: Size>(
     mem_array_type: ArrayType<Element, Len>,
     source_location: SourceLocation,
 ) -> MemBuilder<Element, Len> {
-    let mut retval = memory_impl(name, mem_array_type.element().clone(), source_location);
+    let mut retval = memory_impl(name, mem_array_type.element(), source_location);
     retval.depth(mem_array_type.len());
     retval
 }
diff --git a/crates/fayalite/src/module/transform/simplify_enums.rs b/crates/fayalite/src/module/transform/simplify_enums.rs
index f398006..bb57cf0 100644
--- a/crates/fayalite/src/module/transform/simplify_enums.rs
+++ b/crates/fayalite/src/module/transform/simplify_enums.rs
@@ -271,12 +271,12 @@ impl State {
             .into()),
             EnumTypeState::TagUIntAndBody(_) => {
                 let int_tag_expr = Expr::<TagAndBody<UInt, UInt>>::from_canonical(folded_expr).tag;
-                Ok(match_int_tag(int_tag_expr, source_location, &folded_blocks).into())
+                Ok(match_int_tag(int_tag_expr, source_location, folded_blocks).into())
             }
             EnumTypeState::UInt(_) => {
                 let int_tag_expr = Expr::<UInt>::from_canonical(folded_expr)
                     [..unfolded_enum_type.discriminant_bit_width()];
-                Ok(match_int_tag(int_tag_expr, source_location, &folded_blocks).into())
+                Ok(match_int_tag(int_tag_expr, source_location, folded_blocks).into())
             }
             EnumTypeState::Unchanged => Ok(StmtMatch {
                 expr: Expr::from_canonical(folded_expr),
@@ -929,13 +929,10 @@ impl Folder for State {
         unreachable!()
     }
 
-    fn fold_enum_literal<T: EnumType>(
+    fn fold_enum_literal<T: EnumType + Fold<Self>>(
         &mut self,
         _v: ops::EnumLiteral<T>,
-    ) -> Result<ops::EnumLiteral<T>, Self::Error>
-    where
-        T: Fold<Self>,
-    {
+    ) -> Result<ops::EnumLiteral<T>, Self::Error> {
         unreachable!()
     }
 
diff --git a/crates/fayalite/src/module/transform/simplify_memories.rs b/crates/fayalite/src/module/transform/simplify_memories.rs
index 71e459c..e8f9cbf 100644
--- a/crates/fayalite/src/module/transform/simplify_memories.rs
+++ b/crates/fayalite/src/module/transform/simplify_memories.rs
@@ -766,7 +766,7 @@ impl ModuleState {
                     output_stmts.push(
                         StmtWire {
                             annotations: Default::default(),
-                            wire: canonical_wire.clone(),
+                            wire: canonical_wire,
                         }
                         .into(),
                     );
diff --git a/crates/fayalite/src/util/scoped_ref.rs b/crates/fayalite/src/util/scoped_ref.rs
index 7705377..27f2f89 100644
--- a/crates/fayalite/src/util/scoped_ref.rs
+++ b/crates/fayalite/src/util/scoped_ref.rs
@@ -106,3 +106,9 @@ impl<T: ?Sized> ScopedRef<T> {
         self.0.with_opt(f)
     }
 }
+
+impl<T: ?Sized> Default for ScopedRef<T> {
+    fn default() -> Self {
+        Self::new()
+    }
+}
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index b0b1fb6..222f7ba 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -2258,7 +2258,7 @@ pub fn check_memory_of_bundle() {
     let wmask: (Bool, Bool) = m.input();
     #[hdl]
     let clk: Clock = m.input();
-    let mem_init = Vec::from_iter((0..0x10u8).map(|i| (i ^ 3, (i ^ i / 2).cast_to_static())));
+    let mem_init = Vec::from_iter((0..0x10u8).map(|i| (i ^ 3, (i ^ (i / 2)).cast_to_static())));
     #[hdl]
     let mut mem = memory_with_init(mem_init);
     let read_port = mem.new_read_port();

From 017c14a2f15d8ccc0c32ba4d1a1032d6a8b704e7 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 7 Oct 2024 22:05:30 -0700
Subject: [PATCH 061/190] don't use #[allow(..., reason = "...")] since that's
 not stable yet on rust 1.80.1

---
 crates/fayalite/src/module.rs | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index 7d6949c..7387832 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -607,10 +607,8 @@ impl BlockStack {
 pub struct Id(NonZeroU64);
 
 impl Id {
-    #[allow(
-        clippy::new_without_default,
-        reason = "returns a different value each time, so there isn't really a default value"
-    )]
+    // returns a different value each time, so there isn't really a default value
+    #[allow(clippy::new_without_default)]
     pub fn new() -> Self {
         static NEXT_ID: AtomicU64 = AtomicU64::new(1);
         Self(

From 99180eb3b4f37164994cea8a6b17291dfa4fed46 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 7 Oct 2024 21:59:50 -0700
Subject: [PATCH 062/190] fix clippy lints in generated code

---
 crates/fayalite-proc-macros-impl/src/hdl_bundle.rs    |  4 ++--
 .../fayalite-proc-macros-impl/src/hdl_type_common.rs  |  1 +
 crates/fayalite-proc-macros-impl/src/module.rs        | 11 ++++++++++-
 3 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
index cf08c7e..eefa8be 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
@@ -584,7 +584,7 @@ impl ToTokens for ParsedBundle {
                 |((index, field), flip)| {
                     let ident: &Ident = field.ident().as_ref().unwrap();
                     let ident_str = ident.to_string();
-                    let flipped = flip.is_some();
+                    let not_flipped = flip.is_none().then(|| Token![!](span));
                     quote_spanned! {span=>
                         #ident: {
                             let ::fayalite::bundle::BundleField {
@@ -593,7 +593,7 @@ impl ToTokens for ParsedBundle {
                                 ty: __ty,
                             } = #fields_token[#index];
                             ::fayalite::__std::assert_eq!(&*__name, #ident_str);
-                            ::fayalite::__std::assert_eq!(__flipped, #flipped);
+                            ::fayalite::__std::assert!(#not_flipped __flipped);
                             ::fayalite::ty::Type::from_canonical(__ty)
                         },
                     }
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
index e36f68e..b6ab88d 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
@@ -66,6 +66,7 @@ impl Drop for WrappedInConst<'_> {
     fn drop(&mut self) {
         let inner = &self.inner;
         quote_spanned! {self.span=>
+            #[allow(clippy::type_complexity)]
             const _: () = {
                 #inner
             };
diff --git a/crates/fayalite-proc-macros-impl/src/module.rs b/crates/fayalite-proc-macros-impl/src/module.rs
index 6363bb3..0852f58 100644
--- a/crates/fayalite-proc-macros-impl/src/module.rs
+++ b/crates/fayalite-proc-macros-impl/src/module.rs
@@ -450,12 +450,21 @@ impl ModuleFn {
         let fn_name_str = fn_name.to_string();
         let (_, body_type_generics, _) = body_fn.sig.generics.split_for_impl();
         let body_turbofish_type_generics = body_type_generics.as_turbofish();
+        let body_lambda = if param_names.is_empty() {
+            quote! {
+                __body #body_turbofish_type_generics
+            }
+        } else {
+            quote! {
+                |m| __body #body_turbofish_type_generics(m, #(#param_names,)*)
+            }
+        };
         let block = parse_quote! {{
             #body_fn
             ::fayalite::module::ModuleBuilder::run(
                 #fn_name_str,
                 #module_kind_value,
-                |m| __body #body_turbofish_type_generics(m, #(#param_names,)*),
+                #body_lambda,
             )
         }};
         let outer_fn = ItemFn {

From bf907c38721ebc804d6aaf0bf5ed6798d8604dab Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 7 Oct 2024 23:31:24 -0700
Subject: [PATCH 063/190] cache results of formal proofs

---
 Cargo.lock                 |  48 +++++++++++++
 Cargo.toml                 |   1 +
 crates/fayalite/Cargo.toml |   1 +
 crates/fayalite/src/cli.rs | 141 ++++++++++++++++++++++++++++++++-----
 4 files changed, 175 insertions(+), 16 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index fa6fb6b..1e6f88c 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -69,6 +69,18 @@ dependencies = [
  "windows-sys 0.52.0",
 ]
 
+[[package]]
+name = "arrayref"
+version = "0.3.9"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "76a2e8124351fda1ef8aaaa3bbd7ebbcb486bbcd4225aca0aa0d84bb2db8fecb"
+
+[[package]]
+name = "arrayvec"
+version = "0.7.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7c02d123df017efcdfbd739ef81735b36c5ba83ec3c59c80a9d7ecc718f92e50"
+
 [[package]]
 name = "autocfg"
 version = "1.1.0"
@@ -109,6 +121,20 @@ dependencies = [
  "wyz",
 ]
 
+[[package]]
+name = "blake3"
+version = "1.5.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d82033247fd8e890df8f740e407ad4d038debb9eb1f40533fffb32e7d17dc6f7"
+dependencies = [
+ "arrayref",
+ "arrayvec",
+ "cc",
+ "cfg-if",
+ "constant_time_eq",
+ "serde",
+]
+
 [[package]]
 name = "block-buffer"
 version = "0.10.4"
@@ -118,6 +144,15 @@ dependencies = [
  "generic-array",
 ]
 
+[[package]]
+name = "cc"
+version = "1.1.28"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2e80e3b6a3ab07840e1cae9b0666a63970dc28e8ed5ffbcdacbfc760c281bfc1"
+dependencies = [
+ "shlex",
+]
+
 [[package]]
 name = "cfg-if"
 version = "1.0.0"
@@ -170,6 +205,12 @@ version = "1.0.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "0b6a852b24ab71dffc585bcb46eaf7959d175cb865a7152e35b348d1b2960422"
 
+[[package]]
+name = "constant_time_eq"
+version = "0.3.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7c74b8349d32d297c9134b8c88677813a227df8f779daa29bfc29c183fe3dca6"
+
 [[package]]
 name = "cpufeatures"
 version = "0.2.12"
@@ -242,6 +283,7 @@ name = "fayalite"
 version = "0.2.0"
 dependencies = [
  "bitvec",
+ "blake3",
  "clap",
  "eyre",
  "fayalite-proc-macros",
@@ -521,6 +563,12 @@ dependencies = [
  "digest",
 ]
 
+[[package]]
+name = "shlex"
+version = "1.3.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0fda2ff0d084019ba4d7c6f371c95d8fd75ce3524c3cb8fb653a3023f6323e64"
+
 [[package]]
 name = "strsim"
 version = "0.11.1"
diff --git a/Cargo.toml b/Cargo.toml
index 15d13b6..699d57f 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -19,6 +19,7 @@ fayalite-proc-macros-impl = { version = "=0.2.0", path = "crates/fayalite-proc-m
 fayalite-visit-gen = { version = "=0.2.0", path = "crates/fayalite-visit-gen" }
 base16ct = "0.2.0"
 bitvec = { version = "1.0.1", features = ["serde"] }
+blake3 = { version = "1.5.4", features = ["serde"] }
 clap = { version = "4.5.9", features = ["derive", "env", "string"] }
 eyre = "0.6.12"
 hashbrown = "0.14.3"
diff --git a/crates/fayalite/Cargo.toml b/crates/fayalite/Cargo.toml
index 21089c0..828d759 100644
--- a/crates/fayalite/Cargo.toml
+++ b/crates/fayalite/Cargo.toml
@@ -15,6 +15,7 @@ version.workspace = true
 
 [dependencies]
 bitvec.workspace = true
+blake3.workspace = true
 clap.workspace = true
 eyre.workspace = true
 fayalite-proc-macros.workspace = true
diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index fa1b247..a3649cc 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -12,6 +12,7 @@ use clap::{
     Parser, Subcommand, ValueEnum, ValueHint,
 };
 use eyre::{eyre, Report};
+use serde::{Deserialize, Serialize};
 use std::{
     error,
     ffi::OsString,
@@ -197,8 +198,9 @@ impl BaseArgs {
         &self,
         _acquired_job: &mut AcquiredJob,
         mut command: process::Command,
+        mut captured_output: Option<&mut String>,
     ) -> io::Result<process::ExitStatus> {
-        if self.redirect_output_for_rust_test {
+        if self.redirect_output_for_rust_test || captured_output.is_some() {
             let (reader, writer) = os_pipe::pipe()?;
             let mut reader = io::BufReader::new(reader);
             command.stderr(writer.try_clone()?);
@@ -209,6 +211,9 @@ impl BaseArgs {
             Ok(loop {
                 let status = child.try_wait()?;
                 streaming_read_utf8(&mut reader, |s| {
+                    if let Some(captured_output) = captured_output.as_deref_mut() {
+                        captured_output.push_str(s);
+                    }
                     // use print! so output goes to Rust test output capture
                     print!("{s}");
                     io::Result::Ok(())
@@ -369,6 +374,7 @@ pub struct VerilogArgs {
 pub struct VerilogOutput {
     pub firrtl: FirrtlOutput,
     pub verilog_files: Vec<PathBuf>,
+    pub contents_hash: Option<blake3::Hash>,
 }
 
 impl VerilogOutput {
@@ -386,6 +392,7 @@ impl VerilogArgs {
         let file_separator_prefix = "\n// ----- 8< ----- FILE \"";
         let file_separator_suffix = "\" ----- 8< -----\n\n";
         let mut input = &*input;
+        output.contents_hash = Some(blake3::hash(input.as_bytes()));
         let main_verilog_file = output.main_verilog_file();
         let mut file_name: Option<&Path> = Some(&main_verilog_file);
         loop {
@@ -428,6 +435,7 @@ impl VerilogArgs {
         let output = VerilogOutput {
             firrtl: firrtl_output,
             verilog_files: vec![],
+            contents_hash: None,
         };
         let mut cmd = process::Command::new(firtool);
         cmd.arg(output.firrtl.firrtl_file());
@@ -442,7 +450,7 @@ impl VerilogArgs {
         }
         cmd.args(firtool_extra_args);
         cmd.current_dir(&output.firrtl.output_dir);
-        let status = firrtl.base.run_external_command(acquired_job, cmd)?;
+        let status = firrtl.base.run_external_command(acquired_job, cmd, None)?;
         if status.success() {
             self.process_unadjusted_verilog_file(output)
         } else {
@@ -541,7 +549,7 @@ pub struct FormalArgs {
     )]
     pub sby: PathBuf,
     #[arg(long)]
-    pub sby_extra_args: Vec<OsString>,
+    pub sby_extra_args: Vec<String>,
     #[arg(long, default_value_t)]
     pub mode: FormalMode,
     #[arg(long, default_value_t = Self::DEFAULT_DEPTH)]
@@ -550,6 +558,8 @@ pub struct FormalArgs {
     pub solver: String,
     #[arg(long)]
     pub smtbmc_extra_args: Vec<String>,
+    #[arg(long, default_value_t = true, env = "FAYALITE_CACHE_RESULTS")]
+    pub cache_results: bool,
     #[command(flatten)]
     _formal_adjust_args: FormalAdjustArgs,
 }
@@ -564,16 +574,18 @@ impl fmt::Debug for FormalArgs {
             depth,
             solver,
             smtbmc_extra_args,
+            cache_results,
             _formal_adjust_args: _,
         } = self;
         f.debug_struct("FormalArgs")
-            .field("verilog", &verilog)
-            .field("sby", &sby)
-            .field("sby_extra_args", &sby_extra_args)
-            .field("mode", &mode)
-            .field("depth", &depth)
-            .field("solver", &solver)
-            .field("smtbmc_extra_args", &smtbmc_extra_args)
+            .field("verilog", verilog)
+            .field("sby", sby)
+            .field("sby_extra_args", sby_extra_args)
+            .field("mode", mode)
+            .field("depth", depth)
+            .field("solver", solver)
+            .field("smtbmc_extra_args", smtbmc_extra_args)
+            .field("cache_results", cache_results)
             .finish_non_exhaustive()
     }
 }
@@ -592,6 +604,48 @@ impl FormalOutput {
     pub fn sby_file(&self) -> PathBuf {
         self.verilog.firrtl.file_with_ext("sby")
     }
+    pub fn cache_file(&self) -> PathBuf {
+        self.verilog.firrtl.file_with_ext("cache.json")
+    }
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Hash, Serialize, Deserialize)]
+#[non_exhaustive]
+pub struct FormalCacheOutput {}
+
+#[derive(Debug, Clone, PartialEq, Eq, Hash, Serialize, Deserialize)]
+#[non_exhaustive]
+pub enum FormalCacheVersion {
+    V1,
+}
+
+impl FormalCacheVersion {
+    pub const CURRENT: Self = Self::V1;
+}
+
+#[derive(Debug, Clone, PartialEq, Eq, Hash, Serialize, Deserialize)]
+#[non_exhaustive]
+pub struct FormalCache {
+    pub version: FormalCacheVersion,
+    pub contents_hash: blake3::Hash,
+    pub stdout_stderr: String,
+    pub result: Result<FormalCacheOutput, String>,
+}
+
+impl FormalCache {
+    pub fn new(
+        version: FormalCacheVersion,
+        contents_hash: blake3::Hash,
+        stdout_stderr: String,
+        result: Result<FormalCacheOutput, String>,
+    ) -> Self {
+        Self {
+            version,
+            contents_hash,
+            stdout_stderr,
+            result,
+        }
+    }
 }
 
 impl FormalArgs {
@@ -604,6 +658,7 @@ impl FormalArgs {
             depth,
             smtbmc_extra_args,
             solver,
+            cache_results: _,
             _formal_adjust_args: _,
         } = self;
         let smtbmc_options = smtbmc_extra_args.join(" ");
@@ -644,7 +699,19 @@ impl FormalArgs {
             verilog: verilog_output,
         };
         let sby_file = output.sby_file();
-        std::fs::write(&sby_file, self.sby_contents(&output)?)?;
+        let sby_contents = self.sby_contents(&output)?;
+        let contents_hash = output.verilog.contents_hash.map(|verilog_hash| {
+            let mut hasher = blake3::Hasher::new();
+            hasher.update(verilog_hash.as_bytes());
+            hasher.update(sby_contents.as_bytes());
+            hasher.update(&(self.sby_extra_args.len() as u64).to_le_bytes());
+            for sby_extra_arg in self.sby_extra_args.iter() {
+                hasher.update(&(sby_extra_arg.len() as u64).to_le_bytes());
+                hasher.update(sby_extra_arg.as_bytes());
+            }
+            hasher.finalize()
+        });
+        std::fs::write(&sby_file, sby_contents)?;
         let mut cmd = process::Command::new(&self.sby);
         cmd.arg("-f");
         cmd.arg(sby_file.file_name().unwrap());
@@ -656,20 +723,62 @@ impl FormalArgs {
             NonZeroUsize::new(1).unwrap()
         };
         let new_minimum_count = AcquiredJob::max_available_job_count().min(new_minimum_count);
+        let mut captured_output = String::new();
+        let cache_file = output.cache_file();
+        let do_cache = if let Some(contents_hash) = contents_hash.filter(|_| self.cache_results) {
+            if let Some(FormalCache {
+                version: FormalCacheVersion::CURRENT,
+                contents_hash: cache_contents_hash,
+                stdout_stderr,
+                result,
+            }) = fs::read(&cache_file)
+                .ok()
+                .and_then(|v| serde_json::from_slice(&v).ok())
+            {
+                if cache_contents_hash == contents_hash {
+                    println!("Using cached formal result:\n{stdout_stderr}");
+                    return match result {
+                        Ok(FormalCacheOutput {}) => Ok(output),
+                        Err(error) => Err(CliError(eyre::Report::msg(error))),
+                    };
+                }
+            }
+            true
+        } else {
+            false
+        };
+        let _ = fs::remove_file(&cache_file);
         let status = acquired_job.increase_job_count(new_minimum_count, |acquired_job| {
-            self.verilog
-                .firrtl
-                .base
-                .run_external_command(acquired_job, cmd)
+            self.verilog.firrtl.base.run_external_command(
+                acquired_job,
+                cmd,
+                do_cache.then_some(&mut captured_output),
+            )
         })?;
-        if status.success() {
+        let result = if status.success() {
             Ok(output)
         } else {
             Err(CliError(eyre!(
                 "running {} failed: {status}",
                 self.sby.display()
             )))
+        };
+        if do_cache {
+            fs::write(
+                cache_file,
+                serde_json::to_string_pretty(&FormalCache {
+                    version: FormalCacheVersion::CURRENT,
+                    contents_hash: contents_hash.unwrap(),
+                    stdout_stderr: captured_output,
+                    result: match &result {
+                        Ok(FormalOutput { verilog: _ }) => Ok(FormalCacheOutput {}),
+                        Err(error) => Err(error.to_string()),
+                    },
+                })
+                .expect("serialization shouldn't ever fail"),
+            )?;
         }
+        result
     }
 }
 

From 59cef3f398322efd7d2d6da05a812e97b68c198a Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 10 Oct 2024 20:48:09 -0700
Subject: [PATCH 064/190] add PhantomData as a hdl bundle

---
 .../src/hdl_type_common.rs                    | 192 ++++++++++++++++--
 crates/fayalite/src/bundle.rs                 |  82 ++++++++
 crates/fayalite/tests/hdl_types.rs            |   3 +
 3 files changed, 255 insertions(+), 22 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
index b6ab88d..506c153 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
@@ -1273,6 +1273,130 @@ make_parsed_type_or_const! {
     }
 }
 
+#[derive(Debug, Clone)]
+pub(crate) struct ParsedTypePhantomData {
+    pub(crate) phantom_data: known_items::PhantomData,
+    pub(crate) lt_token: Token![<],
+    pub(crate) ty: Box<ParsedType>,
+    pub(crate) gt_token: Token![>],
+}
+
+impl_fold! {
+    struct ParsedTypePhantomData<> {
+        phantom_data: known_items::PhantomData,
+        lt_token: Token![<],
+        ty: Box<ParsedType>,
+        gt_token: Token![>],
+    }
+}
+
+impl ParsedTypePhantomData {
+    pub(crate) fn try_from_named(
+        named: ParsedTypeNamed,
+        parser: &mut TypesParser<'_>,
+    ) -> Result<Result<Self, ParsedTypeNamed>, ParseFailed> {
+        let ParsedTypeNamed { path, args } = named;
+        let parsed_path = known_items::PhantomData::parse_path(path);
+        let phantom_data = match parsed_path {
+            Ok(phantom_data) => phantom_data,
+            Err(path) => return Ok(Err(ParsedTypeNamed { path, args })),
+        };
+        let Some(ParsedGenericArguments {
+            colon2_token: _,
+            lt_token,
+            args,
+            gt_token,
+        }) = args
+        else {
+            parser
+                .errors()
+                .error(phantom_data, "PhantomData requires generic arguments");
+            return Err(ParseFailed);
+        };
+        let args_len = args.len();
+        if args_len != 1 {
+            parser.errors().error(
+                phantom_data,
+                format_args!(
+                    "wrong number of generic arguments supplied: got {args_len}, expected 1"
+                ),
+            );
+            return Err(ParseFailed);
+        }
+        let ty = args.into_iter().next().unwrap();
+        let ParsedGenericArgument::Type(ty) = ty else {
+            parser.errors().error(ty, "expected a type");
+            return Err(ParseFailed);
+        };
+        Ok(Ok(Self {
+            phantom_data,
+            lt_token,
+            ty: Box::new(ty),
+            gt_token,
+        }))
+    }
+}
+
+impl From<ParsedTypePhantomData> for Type {
+    fn from(value: ParsedTypePhantomData) -> Type {
+        let ParsedTypePhantomData {
+            phantom_data,
+            lt_token,
+            ty,
+            gt_token,
+        } = value;
+        let path = phantom_data.path;
+        let mut args = Punctuated::new();
+        args.push(GenericArgument::Type(ty.into()));
+        let args = AngleBracketedGenericArguments {
+            colon2_token: Some(Token![::](lt_token.span)),
+            lt_token,
+            args,
+            gt_token,
+        };
+        let mut segments = path.segments;
+        segments.last_mut().unwrap().arguments = PathArguments::AngleBracketed(args);
+        Type::Path(TypePath {
+            qself: None,
+            path: Path {
+                leading_colon: path.leading_colon,
+                segments,
+            },
+        })
+    }
+}
+
+impl MakeHdlTypeExpr for ParsedTypePhantomData {
+    fn make_hdl_type_expr(&self, _context: &MakeHdlTypeExprContext) -> Expr {
+        let ParsedTypePhantomData {
+            phantom_data,
+            lt_token: _,
+            ty: _,
+            gt_token: _,
+        } = self;
+        Expr::Path(ExprPath {
+            attrs: vec![],
+            qself: None,
+            path: phantom_data.path.clone(),
+        })
+    }
+}
+
+impl ToTokens for ParsedTypePhantomData {
+    fn to_tokens(&self, tokens: &mut TokenStream) {
+        let Self {
+            phantom_data,
+            lt_token,
+            ty,
+            gt_token,
+        } = self;
+        phantom_data.to_tokens(tokens);
+        lt_token.to_tokens(tokens);
+        ty.to_tokens(tokens);
+        gt_token.to_tokens(tokens);
+    }
+}
+
 #[derive(Debug, Clone)]
 pub(crate) enum ParsedType {
     Delimited(ParsedTypeDelimited),
@@ -1280,6 +1404,7 @@ pub(crate) enum ParsedType {
     NamedParam(ParsedTypeNamedParam),
     Tuple(ParsedTypeTuple),
     ConstUsize(ParsedTypeConstUsize),
+    PhantomData(ParsedTypePhantomData),
     Array(ParsedTypeArray),
     UInt(ParsedTypeUInt),
     SInt(ParsedTypeSInt),
@@ -1294,6 +1419,7 @@ impl_fold! {
         NamedParam(ParsedTypeNamedParam),
         Tuple(ParsedTypeTuple),
         ConstUsize(ParsedTypeConstUsize),
+        PhantomData(ParsedTypePhantomData),
         Array(ParsedTypeArray),
         UInt(ParsedTypeUInt),
         SInt(ParsedTypeSInt),
@@ -1310,6 +1436,7 @@ impl From<ParsedType> for Type {
             ParsedType::NamedParam(v) => v.into(),
             ParsedType::Tuple(v) => v.into(),
             ParsedType::ConstUsize(v) => v.into(),
+            ParsedType::PhantomData(v) => v.into(),
             ParsedType::Array(v) => v.into(),
             ParsedType::UInt(v) => v.into(),
             ParsedType::SInt(v) => v.into(),
@@ -1360,6 +1487,7 @@ impl ToTokens for ParsedType {
             ParsedType::Named(ty) => ty.to_tokens(tokens),
             ParsedType::Tuple(ty) => ty.to_tokens(tokens),
             ParsedType::ConstUsize(ty) => ty.to_tokens(tokens),
+            ParsedType::PhantomData(ty) => ty.to_tokens(tokens),
             ParsedType::Array(ty) => ty.to_tokens(tokens),
             ParsedType::UInt(ty) => ty.to_tokens(tokens),
             ParsedType::SInt(ty) => ty.to_tokens(tokens),
@@ -1467,6 +1595,10 @@ impl ParseTypes<Path> for ParsedType {
             Ok(v) => return Ok(Self::ConstUsize(v)),
             Err(named) => named,
         };
+        let named = match ParsedTypePhantomData::try_from_named(named, parser)? {
+            Ok(v) => return Ok(Self::PhantomData(v)),
+            Err(named) => named,
+        };
         let named = match ParsedTypeUInt::try_from_named(named, parser)? {
             Ok(v) => return Ok(Self::UInt(v)),
             Err(named) => named,
@@ -1784,7 +1916,7 @@ pub(crate) mod known_items {
 
             #[allow(non_snake_case, dead_code)]
             pub(crate) fn $known_item(span: Span) -> $known_item {
-                let segments = $known_item::PATH_SEGMENTS.iter()
+                let segments = $known_item::PATH_SEGMENTS[0].iter()
                     .copied()
                     .map(|seg| PathSegment::from(Ident::new(seg, span)))
                     .collect();
@@ -1810,20 +1942,21 @@ pub(crate) mod known_items {
                             return Ok(Self { span: ident.span(), path });
                         }
                     }
-                    if path.segments.len() == Self::PATH_SEGMENTS.len()
-                        && path
-                            .segments
-                            .iter()
-                            .zip(Self::PATH_SEGMENTS)
-                            .all(|(seg, expected)| {
-                                matches!(seg.arguments, PathArguments::None)
-                                && seg.ident == *expected
-                            })
-                    {
-                        Ok(Self { span: path.segments.last().unwrap().ident.span(), path })
-                    } else {
-                        Err(path)
+                    for &path_segments in Self::PATH_SEGMENTS.iter() {
+                        if path.segments.len() == path_segments.len()
+                            && path
+                                .segments
+                                .iter()
+                                .zip(path_segments)
+                                .all(|(seg, expected)| {
+                                    matches!(seg.arguments, PathArguments::None)
+                                    && seg.ident == *expected
+                                })
+                        {
+                            return Ok(Self { span: path.segments.last().unwrap().ident.span(), path });
+                        }
                     }
+                    Err(path)
                 }
                 #[allow(dead_code)]
                 pub(crate) fn parse_path_with_arguments(mut path: Path) -> Result<(Self, PathArguments), Path> {
@@ -1878,19 +2011,24 @@ pub(crate) mod known_items {
     }
 
     macro_rules! impl_known_item {
-        ($([$(::$head:ident)*])? ::$next:ident $(::$tail:ident)+) => {
-            impl_known_item!([$($(::$head)*)? ::$next] $(::$tail)+);
-        };
-        ([$(::$seg:ident)+] ::$known_item:ident) => {
+        ($(#[alias = $(::$alias:ident)+])* [$(::$seg:ident)+] ::$known_item:ident) => {
             impl_known_item_body!($known_item);
 
             impl $known_item {
-                pub(crate) const PATH_SEGMENTS: &'static [&'static str] = &[
-                    $(stringify!($seg),)+
-                    stringify!($known_item),
+                pub(crate) const PATH_SEGMENTS: &'static [&'static [&'static str]] = &[
+                    &[
+                        $(stringify!($seg),)+
+                        stringify!($known_item),
+                    ],
+                    $(&[
+                        $(stringify!($alias),)+
+                    ],)*
                 ];
             }
         };
+        ($(#[alias = $(::$alias:ident)+])* $([$(::$head:ident)*])? ::$next:ident $(::$tail:ident)+) => {
+            impl_known_item!($(#[alias = $(::$alias)+])* [$($(::$head)*)? ::$next] $(::$tail)+);
+        };
     }
 
     impl_known_item!(::fayalite::array::Array);
@@ -1911,7 +2049,16 @@ pub(crate) mod known_items {
     impl_known_item!(::fayalite::ty::Type);
     impl_known_item!(::fayalite::ty::Type::MaskType);
     impl_known_item!(::fayalite::util::ConstUsize);
-    impl_known_item!(::fayalite::__std::primitive::usize);
+    impl_known_item!(
+        #[alias = ::std::primitive::usize]
+        #[alias = ::core::primitive::usize]
+        ::fayalite::__std::primitive::usize
+    );
+    impl_known_item!(
+        #[alias = ::std::marker::PhantomData]
+        #[alias = ::core::marker::PhantomData]
+        ::fayalite::__std::marker::PhantomData
+    );
 }
 
 macro_rules! impl_bounds {
@@ -3969,6 +4116,7 @@ impl MakeHdlTypeExpr for ParsedType {
             Self::NamedParam(v) => v.make_hdl_type_expr(context),
             Self::Tuple(v) => v.make_hdl_type_expr(context),
             Self::ConstUsize(v) => v.make_hdl_type_expr(context),
+            Self::PhantomData(v) => v.make_hdl_type_expr(context),
             Self::Array(v) => v.make_hdl_type_expr(context),
             Self::UInt(v) => v.make_hdl_type_expr(context),
             Self::SInt(v) => v.make_hdl_type_expr(context),
diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs
index b338322..843eb6c 100644
--- a/crates/fayalite/src/bundle.rs
+++ b/crates/fayalite/src/bundle.rs
@@ -446,3 +446,85 @@ impl_tuples! {
         {#[num = 11, field = field_11] v11: T11}
     ]
 }
+
+impl<T: ?Sized + Send + Sync + 'static> Type for PhantomData<T> {
+    type BaseType = Bundle;
+    type MaskType = ();
+    type MatchVariant = PhantomData<T>;
+    type MatchActiveScope = ();
+    type MatchVariantAndInactiveScope = MatchVariantWithoutScope<Self::MatchVariant>;
+    type MatchVariantsIter = std::iter::Once<Self::MatchVariantAndInactiveScope>;
+    fn match_variants(
+        this: Expr<Self>,
+        source_location: SourceLocation,
+    ) -> Self::MatchVariantsIter {
+        let _ = this;
+        let _ = source_location;
+        std::iter::once(MatchVariantWithoutScope(PhantomData))
+    }
+    fn mask_type(&self) -> Self::MaskType {
+        ()
+    }
+    fn canonical(&self) -> CanonicalType {
+        Bundle::new(self.fields()).canonical()
+    }
+    #[track_caller]
+    fn from_canonical(canonical_type: CanonicalType) -> Self {
+        let CanonicalType::Bundle(bundle) = canonical_type else {
+            panic!("expected bundle");
+        };
+        assert!(
+            bundle.fields().is_empty(),
+            "bundle has wrong number of fields"
+        );
+        PhantomData
+    }
+    fn source_location() -> SourceLocation {
+        SourceLocation::builtin()
+    }
+}
+
+pub struct PhantomDataBuilder<T: ?Sized + Send + Sync + 'static>(PhantomData<T>);
+
+impl<T: ?Sized + Send + Sync + 'static> Default for PhantomDataBuilder<T> {
+    fn default() -> Self {
+        Self(PhantomData)
+    }
+}
+
+impl<T: ?Sized + Send + Sync + 'static> ToExpr for PhantomDataBuilder<T> {
+    type Type = PhantomData<T>;
+
+    fn to_expr(&self) -> Expr<Self::Type> {
+        PhantomData.to_expr()
+    }
+}
+
+impl<T: ?Sized + Send + Sync + 'static> BundleType for PhantomData<T> {
+    type Builder = PhantomDataBuilder<T>;
+    type FilledBuilder = PhantomDataBuilder<T>;
+    fn fields(&self) -> Interned<[BundleField]> {
+        Interned::default()
+    }
+}
+
+impl<T: ?Sized + Send + Sync + 'static> TypeWithDeref for PhantomData<T> {
+    fn expr_deref(_this: &Expr<Self>) -> &Self::MatchVariant {
+        &PhantomData
+    }
+}
+
+impl<T: ?Sized + Send + Sync + 'static> StaticType for PhantomData<T> {
+    const TYPE: Self = PhantomData;
+    const MASK_TYPE: Self::MaskType = ();
+    const TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES;
+    const MASK_TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES;
+}
+
+impl<T: ?Sized + Send + Sync + 'static> ToExpr for PhantomData<T> {
+    type Type = PhantomData<T>;
+
+    fn to_expr(&self) -> Expr<Self::Type> {
+        BundleLiteral::new(PhantomData, Interned::default()).to_expr()
+    }
+}
diff --git a/crates/fayalite/tests/hdl_types.rs b/crates/fayalite/tests/hdl_types.rs
index 3f11de3..bd7c0fd 100644
--- a/crates/fayalite/tests/hdl_types.rs
+++ b/crates/fayalite/tests/hdl_types.rs
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use fayalite::prelude::*;
+use std::marker::PhantomData;
 
 #[hdl(outline_generated)]
 pub struct S<T, Len: Size, T2> {
@@ -8,6 +9,8 @@ pub struct S<T, Len: Size, T2> {
     b: UInt<3>,
     pub(crate) c: ArrayType<UInt<1>, Len>,
     pub d: T2,
+    pub e: PhantomData<T>,
+    pub f: PhantomData<Len>,
 }
 
 #[hdl(outline_generated)]

From 1a2149b0406fd29fa2032532dfba3b371cf74a26 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 10 Oct 2024 20:53:29 -0700
Subject: [PATCH 065/190] silence warnings for field names that start with _

---
 crates/fayalite-proc-macros-impl/src/hdl_bundle.rs | 2 +-
 crates/fayalite/tests/hdl_types.rs                 | 3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
index eefa8be..79326e2 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
@@ -340,7 +340,7 @@ impl ToTokens for Builder {
                 }));
             quote_spanned! {self.ident.span()=>
                 #[automatically_derived]
-                #[allow(non_camel_case_types, dead_code)]
+                #[allow(non_camel_case_types, non_snake_case, dead_code)]
                 impl #impl_generics #unfilled_ty
                 #where_clause
                 {
diff --git a/crates/fayalite/tests/hdl_types.rs b/crates/fayalite/tests/hdl_types.rs
index bd7c0fd..bed1a82 100644
--- a/crates/fayalite/tests/hdl_types.rs
+++ b/crates/fayalite/tests/hdl_types.rs
@@ -9,8 +9,7 @@ pub struct S<T, Len: Size, T2> {
     b: UInt<3>,
     pub(crate) c: ArrayType<UInt<1>, Len>,
     pub d: T2,
-    pub e: PhantomData<T>,
-    pub f: PhantomData<Len>,
+    pub _phantom: PhantomData<(T, Len)>,
 }
 
 #[hdl(outline_generated)]

From d0694cbd521496fe019ed8a755e77f3361f83289 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 10 Oct 2024 22:58:15 -0700
Subject: [PATCH 066/190] add disabled test for #[hdl] struct S4<W: KnownSize,
 W2: KnownSize> which type errors

---
 crates/fayalite/tests/hdl_types.rs | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/crates/fayalite/tests/hdl_types.rs b/crates/fayalite/tests/hdl_types.rs
index bed1a82..b8cbff3 100644
--- a/crates/fayalite/tests/hdl_types.rs
+++ b/crates/fayalite/tests/hdl_types.rs
@@ -32,6 +32,13 @@ pub struct S2<T = ()> {
     pub v: E<T>,
 }
 
+#[cfg(todo)]
+#[hdl(outline_generated)]
+pub struct S4<W: KnownSize, W2: KnownSize> {
+    pub v: UIntType<W>,
+    pub v2: SIntType<W2>,
+}
+
 // check that #[hdl] properly handles hygiene
 macro_rules! types_in_macros {
     ($a:ident, $b:ident, $c:ident, $d:ident, $e:ident, $f:ident, $A:ident, $B:ident, $C:ident, $D:ident, $E:ident, $F:ident) => {

From 4909724995ff630fa028e5481577dafcb53384ed Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 10 Oct 2024 23:34:46 -0700
Subject: [PATCH 067/190] add more thorough checks that bounds are properly
 handled on #[hdl] structs

---
 crates/fayalite/tests/hdl_types.rs | 95 +++++++++++++++++++++++++++---
 1 file changed, 88 insertions(+), 7 deletions(-)

diff --git a/crates/fayalite/tests/hdl_types.rs b/crates/fayalite/tests/hdl_types.rs
index b8cbff3..71450fc 100644
--- a/crates/fayalite/tests/hdl_types.rs
+++ b/crates/fayalite/tests/hdl_types.rs
@@ -1,6 +1,13 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use fayalite::prelude::*;
+#[cfg(todo)]
+use fayalite::{
+    bundle::BundleType,
+    enum_::EnumType,
+    int::{BoolOrIntType, IntType},
+    ty::StaticType,
+};
 use std::marker::PhantomData;
 
 #[hdl(outline_generated)]
@@ -32,13 +39,6 @@ pub struct S2<T = ()> {
     pub v: E<T>,
 }
 
-#[cfg(todo)]
-#[hdl(outline_generated)]
-pub struct S4<W: KnownSize, W2: KnownSize> {
-    pub v: UIntType<W>,
-    pub v2: SIntType<W2>,
-}
-
 // check that #[hdl] properly handles hygiene
 macro_rules! types_in_macros {
     ($a:ident, $b:ident, $c:ident, $d:ident, $e:ident, $f:ident, $A:ident, $B:ident, $C:ident, $D:ident, $E:ident, $F:ident) => {
@@ -104,3 +104,84 @@ macro_rules! types_in_macros {
 }
 
 types_in_macros!();
+
+mod bound_kind {
+    use fayalite::prelude::*;
+
+    #[hdl]
+    pub struct Type<T> {
+        v: T,
+    }
+
+    #[hdl]
+    pub struct Size<T: ::fayalite::int::Size> {
+        v: UIntType<T>,
+    }
+}
+
+macro_rules! check_bounds {
+    ($name:ident<$(#[$field:ident, $kind:ident] $var:ident: $($bound:ident +)*),*>) => {
+        #[cfg(todo)]
+        #[hdl(outline_generated)]
+        struct $name<$($var: $($bound +)*,)*> {
+            $($field: bound_kind::$kind<$var>,)*
+        }
+    };
+}
+
+check_bounds!(CheckBoundsS0<#[a, Size] A: Size +>);
+check_bounds!(CheckBoundsS1<#[a, Size] A: KnownSize +>);
+check_bounds!(CheckBoundsT0<#[a, Type] A: Type +>);
+check_bounds!(CheckBoundsT1<#[a, Type] A: BoolOrIntType +>);
+check_bounds!(CheckBoundsT2<#[a, Type] A: BundleType +>);
+check_bounds!(CheckBoundsT3<#[a, Type] A: EnumType +>);
+check_bounds!(CheckBoundsT4<#[a, Type] A: IntType +>);
+check_bounds!(CheckBoundsT5<#[a, Type] A: StaticType +>);
+check_bounds!(CheckBoundsSS0<#[a, Size] A: Size +, #[b, Size] B: Size +>);
+check_bounds!(CheckBoundsSS1<#[a, Size] A: KnownSize +, #[b, Size] B: Size +>);
+check_bounds!(CheckBoundsST0<#[a, Size] A: Size +, #[b, Type] B: Type +>);
+check_bounds!(CheckBoundsST1<#[a, Size] A: KnownSize +, #[b, Type] B: Type +>);
+check_bounds!(CheckBoundsTS0<#[a, Type] A: Type +, #[b, Size] B: Size +>);
+check_bounds!(CheckBoundsTS1<#[a, Type] A: BoolOrIntType +, #[b, Size] B: Size +>);
+check_bounds!(CheckBoundsTS2<#[a, Type] A: BundleType +, #[b, Size] B: Size +>);
+check_bounds!(CheckBoundsTS3<#[a, Type] A: EnumType +, #[b, Size] B: Size +>);
+check_bounds!(CheckBoundsTS4<#[a, Type] A: IntType +, #[b, Size] B: Size +>);
+check_bounds!(CheckBoundsTS5<#[a, Type] A: StaticType +, #[b, Size] B: Size +>);
+check_bounds!(CheckBoundsTT0<#[a, Type] A: Type +, #[b, Type] B: Type +>);
+check_bounds!(CheckBoundsTT1<#[a, Type] A: BoolOrIntType +, #[b, Type] B: Type +>);
+check_bounds!(CheckBoundsTT2<#[a, Type] A: BundleType +, #[b, Type] B: Type +>);
+check_bounds!(CheckBoundsTT3<#[a, Type] A: EnumType +, #[b, Type] B: Type +>);
+check_bounds!(CheckBoundsTT4<#[a, Type] A: IntType +, #[b, Type] B: Type +>);
+check_bounds!(CheckBoundsTT5<#[a, Type] A: StaticType +, #[b, Type] B: Type +>);
+check_bounds!(CheckBoundsSSS0<#[a, Size] A: Size +, #[b, Size] B: Size +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsSSS1<#[a, Size] A: KnownSize +, #[b, Size] B: Size +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsSST0<#[a, Size] A: Size +, #[b, Size] B: Size +, #[c, Type] C: Type +>);
+check_bounds!(CheckBoundsSST1<#[a, Size] A: KnownSize +, #[b, Size] B: Size +, #[c, Type] C: Type +>);
+check_bounds!(CheckBoundsSTS0<#[a, Size] A: Size +, #[b, Type] B: Type +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsSTS1<#[a, Size] A: KnownSize +, #[b, Type] B: Type +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsSTT0<#[a, Size] A: Size +, #[b, Type] B: Type +, #[c, Type] C: Type +>);
+check_bounds!(CheckBoundsSTT1<#[a, Size] A: KnownSize +, #[b, Type] B: Type +, #[c, Type] C: Type +>);
+check_bounds!(CheckBoundsTSS0<#[a, Type] A: Type +, #[b, Size] B: Size +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsTSS1<#[a, Type] A: BoolOrIntType +, #[b, Size] B: Size +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsTSS2<#[a, Type] A: BundleType +, #[b, Size] B: Size +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsTSS3<#[a, Type] A: EnumType +, #[b, Size] B: Size +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsTSS4<#[a, Type] A: IntType +, #[b, Size] B: Size +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsTSS5<#[a, Type] A: StaticType +, #[b, Size] B: Size +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsTST0<#[a, Type] A: Type +, #[b, Size] B: Size +, #[c, Type] C: Type +>);
+check_bounds!(CheckBoundsTST1<#[a, Type] A: BoolOrIntType +, #[b, Size] B: Size +, #[c, Type] C: Type +>);
+check_bounds!(CheckBoundsTST2<#[a, Type] A: BundleType +, #[b, Size] B: Size +, #[c, Type] C: Type +>);
+check_bounds!(CheckBoundsTST3<#[a, Type] A: EnumType +, #[b, Size] B: Size +, #[c, Type] C: Type +>);
+check_bounds!(CheckBoundsTST4<#[a, Type] A: IntType +, #[b, Size] B: Size +, #[c, Type] C: Type +>);
+check_bounds!(CheckBoundsTST5<#[a, Type] A: StaticType +, #[b, Size] B: Size +, #[c, Type] C: Type +>);
+check_bounds!(CheckBoundsTTS0<#[a, Type] A: Type +, #[b, Type] B: Type +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsTTS1<#[a, Type] A: BoolOrIntType +, #[b, Type] B: Type +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsTTS2<#[a, Type] A: BundleType +, #[b, Type] B: Type +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsTTS3<#[a, Type] A: EnumType +, #[b, Type] B: Type +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsTTS4<#[a, Type] A: IntType +, #[b, Type] B: Type +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsTTS5<#[a, Type] A: StaticType +, #[b, Type] B: Type +, #[c, Size] C: Size +>);
+check_bounds!(CheckBoundsTTT0<#[a, Type] A: Type +, #[b, Type] B: Type +, #[c, Type] C: Type +>);
+check_bounds!(CheckBoundsTTT1<#[a, Type] A: BoolOrIntType +, #[b, Type] B: Type +, #[c, Type] C: Type +>);
+check_bounds!(CheckBoundsTTT2<#[a, Type] A: BundleType +, #[b, Type] B: Type +, #[c, Type] C: Type +>);
+check_bounds!(CheckBoundsTTT3<#[a, Type] A: EnumType +, #[b, Type] B: Type +, #[c, Type] C: Type +>);
+check_bounds!(CheckBoundsTTT4<#[a, Type] A: IntType +, #[b, Type] B: Type +, #[c, Type] C: Type +>);
+check_bounds!(CheckBoundsTTT5<#[a, Type] A: StaticType +, #[b, Type] B: Type +, #[c, Type] C: Type +>);

From d0229fbcfb11666b5abf7ae487ffe335866f9326 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 11 Oct 2024 17:30:49 -0700
Subject: [PATCH 068/190] get #[hdl] struct S<A: KnownSize, B: KnownSize> to
 work

---
 crates/fayalite/src/array.rs       |  2 +-
 crates/fayalite/src/int.rs         | 51 ++++++++++++++++++------------
 crates/fayalite/tests/hdl_types.rs |  4 +--
 3 files changed, 32 insertions(+), 25 deletions(-)

diff --git a/crates/fayalite/src/array.rs b/crates/fayalite/src/array.rs
index a3aea79..f617f91 100644
--- a/crates/fayalite/src/array.rs
+++ b/crates/fayalite/src/array.rs
@@ -85,7 +85,7 @@ impl<T: Type, Len: Size> ArrayType<T, Len> {
     }
 }
 
-impl<T: Type, Len: KnownSize> ArrayType<T, Len> {
+impl<T: Type, Len: KnownSize + Size<SizeType = Len>> ArrayType<T, Len> {
     pub fn new_static(element: T) -> Self {
         Self::new(element, Len::SizeType::default())
     }
diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index dd631d0..03b2c88 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -32,8 +32,23 @@ mod sealed {
 pub const DYN_SIZE: usize = !0;
 pub type DynSize = ConstUsize<DYN_SIZE>;
 
-pub trait KnownSize: GenericConstUsize + Size<SizeType = Self> {
+pub trait KnownSize:
+    GenericConstUsize + sealed::SizeTypeSealed + sealed::SizeSealed + Default
+{
     const SIZE: Self;
+    type ArrayMatch<Element: Type>: AsRef<[Expr<Element>]>
+        + AsMut<[Expr<Element>]>
+        + BorrowMut<[Expr<Element>]>
+        + 'static
+        + Send
+        + Sync
+        + Eq
+        + Clone
+        + std::hash::Hash
+        + std::fmt::Debug
+        + IntoIterator<Item = Expr<Element>>
+        + TryFrom<Vec<Expr<Element>>>
+        + Into<Vec<Expr<Element>>>;
 }
 
 macro_rules! known_widths {
@@ -44,6 +59,7 @@ macro_rules! known_widths {
             v
         }> {
             const SIZE: Self = Self;
+            type ArrayMatch<Element: Type> = [Expr<Element>; Self::VALUE];
         }
     };
     ([2 $($rest:tt)*] $($bits:literal)+) => {
@@ -55,6 +71,7 @@ macro_rules! known_widths {
         known_widths!([$($rest)*] 1);
         impl KnownSize for ConstUsize<{2 $(* $rest)*}> {
             const SIZE: Self = Self;
+            type ArrayMatch<Element: Type> = [Expr<Element>; Self::VALUE];
         }
     };
 }
@@ -124,30 +141,24 @@ impl<const VALUE: usize> sealed::SizeSealed for ConstUsize<VALUE> {}
 
 impl<const VALUE: usize> sealed::SizeTypeSealed for ConstUsize<VALUE> {}
 
-impl<const VALUE: usize> SizeType for ConstUsize<VALUE>
-where
-    ConstUsize<VALUE>: KnownSize,
-{
-    type Size = ConstUsize<VALUE>;
+impl<T: KnownSize> SizeType for T {
+    type Size = T;
 }
 
-impl<const VALUE: usize> Size for ConstUsize<VALUE>
-where
-    ConstUsize<VALUE>: KnownSize,
-{
-    type ArrayMatch<Element: Type> = [Expr<Element>; VALUE];
+impl<T: KnownSize> Size for T {
+    type ArrayMatch<Element: Type> = <T as KnownSize>::ArrayMatch<Element>;
 
-    const KNOWN_VALUE: Option<usize> = Some(VALUE);
+    const KNOWN_VALUE: Option<usize> = Some(T::VALUE);
 
-    type SizeType = ConstUsize<VALUE>;
+    type SizeType = T;
 
     fn as_usize(_size_type: Self::SizeType) -> usize {
-        VALUE
+        T::VALUE
     }
 
     fn try_from_usize(v: usize) -> Option<Self::SizeType> {
-        if v == VALUE {
-            Some(ConstUsize)
+        if v == T::VALUE {
+            Some(T::SIZE)
         } else {
             None
         }
@@ -252,9 +263,7 @@ macro_rules! impl_int {
 
         impl<Width: KnownSize> $name<Width> {
             pub fn new_static() -> Self {
-                Self {
-                    width: Width::SizeType::default(),
-                }
+                Self { width: Width::SIZE }
             }
         }
 
@@ -526,9 +535,9 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
     fn new(width: <Self::Width as Size>::SizeType) -> Self;
     fn new_static() -> Self
     where
-        Self::Width: KnownSize,
+        Self::Width: KnownSize + Size<SizeType = Self::Width>,
     {
-        Self::new(<Self::Width as Size>::SizeType::default())
+        Self::new(Self::Width::default())
     }
     fn as_same_width_sint(self) -> SIntType<Self::Width> {
         SIntType::new(Self::Width::from_usize(self.width()))
diff --git a/crates/fayalite/tests/hdl_types.rs b/crates/fayalite/tests/hdl_types.rs
index 71450fc..4509146 100644
--- a/crates/fayalite/tests/hdl_types.rs
+++ b/crates/fayalite/tests/hdl_types.rs
@@ -1,11 +1,10 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-use fayalite::prelude::*;
-#[cfg(todo)]
 use fayalite::{
     bundle::BundleType,
     enum_::EnumType,
     int::{BoolOrIntType, IntType},
+    prelude::*,
     ty::StaticType,
 };
 use std::marker::PhantomData;
@@ -121,7 +120,6 @@ mod bound_kind {
 
 macro_rules! check_bounds {
     ($name:ident<$(#[$field:ident, $kind:ident] $var:ident: $($bound:ident +)*),*>) => {
-        #[cfg(todo)]
         #[hdl(outline_generated)]
         struct $name<$($var: $($bound +)*,)*> {
             $($field: bound_kind::$kind<$var>,)*

From 3939ce2360138c75c53972368069c8f882111571 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 14 Oct 2024 17:47:58 -0700
Subject: [PATCH 069/190] add Bundle and Enum to prelude

---
 crates/fayalite/src/prelude.rs | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs
index 46d9e6e..9e7a85e 100644
--- a/crates/fayalite/src/prelude.rs
+++ b/crates/fayalite/src/prelude.rs
@@ -6,9 +6,10 @@ pub use crate::{
         DocStringAnnotation, DontTouchAnnotation, SVAttributeAnnotation,
     },
     array::{Array, ArrayType},
+    bundle::Bundle,
     cli::Cli,
     clock::{Clock, ClockDomain, ToClock},
-    enum_::{HdlNone, HdlOption, HdlSome},
+    enum_::{Enum, HdlNone, HdlOption, HdlSome},
     expr::{
         repeat, CastBitsTo, CastTo, CastToBits, Expr, HdlPartialEq, HdlPartialOrd, MakeUninitExpr,
         ReduceBits, ToExpr,

From 3d0f95cfe5a910f79177babf8fe12483f83e96f9 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 15 Oct 2024 01:48:48 -0700
Subject: [PATCH 070/190] formal: add workaround for wires disappearing because
 yosys optimizes them out

---
 crates/fayalite/src/cli.rs | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index a3649cc..1dace37 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -687,7 +687,11 @@ impl FormalArgs {
             }
             writeln!(retval, "read_verilog -sv -formal \"{verilog_file}\"").unwrap();
         }
-        writeln!(retval, "prep -top {top_module}").unwrap();
+        // workaround for wires disappearing -- set `keep` on all wires
+        writeln!(retval, "hierarchy -top {top_module}").unwrap();
+        writeln!(retval, "proc").unwrap();
+        writeln!(retval, "setattr -set keep 1 w:\\*").unwrap();
+        writeln!(retval, "prep").unwrap();
         Ok(retval)
     }
     fn run_impl(

From 42effd1132091e2f14af416c64412d4047c76aff Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 15 Oct 2024 20:32:33 -0700
Subject: [PATCH 071/190] switch to using a make job server for managing test
 parallelism

---
 Cargo.lock                             |  60 ++++++++
 Cargo.toml                             |   2 +
 crates/fayalite/Cargo.toml             |   2 +
 crates/fayalite/src/cli.rs             | 129 +----------------
 crates/fayalite/src/util.rs            |   1 +
 crates/fayalite/src/util/job_server.rs | 193 +++++++++++++++++++++++++
 6 files changed, 265 insertions(+), 122 deletions(-)
 create mode 100644 crates/fayalite/src/util/job_server.rs

diff --git a/Cargo.lock b/Cargo.lock
index 1e6f88c..7a2a2ac 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -230,6 +230,27 @@ dependencies = [
  "typenum",
 ]
 
+[[package]]
+name = "ctor"
+version = "0.2.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "edb49164822f3ee45b17acd4a208cfc1251410cf0cad9a833234c9890774dd9f"
+dependencies = [
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "derive_destructure2"
+version = "0.1.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "64b697ac90ff296f0fc031ee5a61c7ac31fb9fff50e3fb32873b09223613fc0c"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
 [[package]]
 name = "digest"
 version = "0.10.7"
@@ -285,10 +306,12 @@ dependencies = [
  "bitvec",
  "blake3",
  "clap",
+ "ctor",
  "eyre",
  "fayalite-proc-macros",
  "fayalite-visit-gen",
  "hashbrown",
+ "jobslot",
  "num-bigint",
  "num-traits",
  "os_pipe",
@@ -350,6 +373,17 @@ dependencies = [
  "version_check",
 ]
 
+[[package]]
+name = "getrandom"
+version = "0.2.14"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "94b22e06ecb0110981051723910cbf0b5f5e09a2062dd7663334ee79a9d1286c"
+dependencies = [
+ "cfg-if",
+ "libc",
+ "wasi",
+]
+
 [[package]]
 name = "glob"
 version = "0.3.1"
@@ -410,6 +444,20 @@ version = "1.0.10"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "b1a46d1a171d865aa5f83f92695765caa047a9b4cbae2cbf37dbd613a793fd4c"
 
+[[package]]
+name = "jobslot"
+version = "0.2.19"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "fe10868679d7a24c2c67d862d0e64a342ce9aef7cdde9ce8019bd35d353d458d"
+dependencies = [
+ "cfg-if",
+ "derive_destructure2",
+ "getrandom",
+ "libc",
+ "scopeguard",
+ "windows-sys 0.59.0",
+]
+
 [[package]]
 name = "libc"
 version = "0.2.153"
@@ -520,6 +568,12 @@ version = "1.0.17"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "e86697c916019a8588c99b5fac3cead74ec0b4b819707a682fd4d23fa0ce1ba1"
 
+[[package]]
+name = "scopeguard"
+version = "1.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "94143f37725109f92c262ed2cf5e59bce7498c01bcc1502d7b9afe439a4e9f49"
+
 [[package]]
 name = "serde"
 version = "1.0.202"
@@ -672,6 +726,12 @@ version = "0.9.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "49874b5167b65d7193b8aba1567f5c7d93d001cafc34600cee003eda787e483f"
 
+[[package]]
+name = "wasi"
+version = "0.11.0+wasi-snapshot-preview1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9c8d87e72b64a3b4db28d11ce29237c246188f4f51057d65a7eab63b7987e423"
+
 [[package]]
 name = "which"
 version = "6.0.1"
diff --git a/Cargo.toml b/Cargo.toml
index 699d57f..da104c2 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -21,9 +21,11 @@ base16ct = "0.2.0"
 bitvec = { version = "1.0.1", features = ["serde"] }
 blake3 = { version = "1.5.4", features = ["serde"] }
 clap = { version = "4.5.9", features = ["derive", "env", "string"] }
+ctor = "0.2.8"
 eyre = "0.6.12"
 hashbrown = "0.14.3"
 indexmap = { version = "2.2.6", features = ["serde"] }
+jobslot = "0.2.19"
 num-bigint = "0.4.4"
 num-traits = "0.2.16"
 os_pipe = "1.2.1"
diff --git a/crates/fayalite/Cargo.toml b/crates/fayalite/Cargo.toml
index 828d759..5724a80 100644
--- a/crates/fayalite/Cargo.toml
+++ b/crates/fayalite/Cargo.toml
@@ -17,9 +17,11 @@ version.workspace = true
 bitvec.workspace = true
 blake3.workspace = true
 clap.workspace = true
+ctor.workspace = true
 eyre.workspace = true
 fayalite-proc-macros.workspace = true
 hashbrown.workspace = true
+jobslot.workspace = true
 num-bigint.workspace = true
 num-traits.workspace = true
 os_pipe.workspace = true
diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index 1dace37..a236c77 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -5,7 +5,7 @@ use crate::{
     firrtl::{self, ExportOptions},
     intern::Interned,
     module::Module,
-    util::streaming_read_utf8::streaming_read_utf8,
+    util::{job_server::AcquiredJob, streaming_read_utf8::streaming_read_utf8},
 };
 use clap::{
     builder::{OsStringValueParser, TypedValueParser},
@@ -18,10 +18,8 @@ use std::{
     ffi::OsString,
     fmt::{self, Write},
     fs, io, mem,
-    num::NonZeroUsize,
     path::{Path, PathBuf},
     process,
-    sync::{Condvar, Mutex, OnceLock},
 };
 use tempfile::TempDir;
 
@@ -49,107 +47,10 @@ impl From<io::Error> for CliError {
     }
 }
 
-#[derive(Debug)]
-pub struct AcquiredJob {
-    job_count: NonZeroUsize,
-}
-
-impl Drop for AcquiredJob {
-    fn drop(&mut self) {
-        Self::change_job_count(Some(self.job_count), None);
-    }
-}
-
-impl AcquiredJob {
-    pub fn max_available_job_count() -> NonZeroUsize {
-        static RETVAL: OnceLock<NonZeroUsize> = OnceLock::new();
-        *RETVAL.get_or_init(|| {
-            std::thread::available_parallelism().unwrap_or(NonZeroUsize::new(1).unwrap())
-        })
-    }
-    fn change_job_count(released: Option<NonZeroUsize>, acquired: Option<NonZeroUsize>) {
-        static AVAILABLE_JOB_COUNT: OnceLock<Mutex<usize>> = OnceLock::new();
-        static COND_VAR: Condvar = Condvar::new();
-        let mut available_job_count_lock = AVAILABLE_JOB_COUNT
-            .get_or_init(|| Mutex::new(Self::max_available_job_count().get()))
-            .lock()
-            .unwrap();
-        if let Some(released) = released {
-            *available_job_count_lock = available_job_count_lock
-                .checked_add(released.get())
-                .expect("tried to release too many jobs");
-            COND_VAR.notify_all();
-        }
-        if let Some(acquired) = acquired {
-            loop {
-                match available_job_count_lock.checked_sub(acquired.get()) {
-                    Some(jobs_left) => {
-                        *available_job_count_lock = jobs_left;
-                        break;
-                    }
-                    None => {
-                        available_job_count_lock = COND_VAR.wait(available_job_count_lock).unwrap()
-                    }
-                }
-            }
-        }
-    }
-    pub fn job_count(&self) -> NonZeroUsize {
-        self.job_count
-    }
-    pub fn increase_job_count<R>(
-        &mut self,
-        new_minimum_count: NonZeroUsize,
-        f: impl FnOnce(&mut AcquiredJob) -> R,
-    ) -> R {
-        if new_minimum_count <= self.job_count {
-            return f(self);
-        }
-        struct ReleaseOnDrop<'a> {
-            acquired_job: &'a mut AcquiredJob,
-            old_job_count: NonZeroUsize,
-        }
-        impl Drop for ReleaseOnDrop<'_> {
-            fn drop(&mut self) {
-                AcquiredJob::change_job_count(
-                    NonZeroUsize::new(self.acquired_job.job_count.get() - self.old_job_count.get()),
-                    None,
-                );
-                self.acquired_job.job_count = self.old_job_count;
-            }
-        }
-        let release_on_drop = ReleaseOnDrop {
-            old_job_count: self.job_count,
-            acquired_job: self,
-        };
-        // release our current jobs when acquiring new jobs to avoid deadlock
-        Self::change_job_count(Some(release_on_drop.old_job_count), Some(new_minimum_count));
-        release_on_drop.acquired_job.job_count = new_minimum_count;
-        let retval = f(release_on_drop.acquired_job);
-        drop(release_on_drop);
-        retval
-    }
-    pub fn acquire_jobs(job_count: NonZeroUsize) -> Self {
-        Self::change_job_count(None, Some(job_count));
-        Self { job_count }
-    }
-    pub fn run_command<R>(
-        &mut self,
-        mut cmd: std::process::Command,
-        f: impl FnOnce(&mut std::process::Command) -> std::io::Result<R>,
-    ) -> std::io::Result<R> {
-        // TODO: if we implement a make job server, add the proper env vars to cmd
-        f(&mut cmd)
-    }
-}
-
 pub trait RunPhase<Arg> {
     type Output;
     fn run(&self, arg: Arg) -> Result<Self::Output> {
-        self.run_with_job(
-            arg,
-            &mut AcquiredJob::acquire_jobs(NonZeroUsize::new(1).unwrap()),
-        )
+        self.run_with_job(arg, &mut AcquiredJob::acquire())
     }
     fn run_with_job(&self, arg: Arg, acquired_job: &mut AcquiredJob) -> Result<Self::Output>;
 }
@@ -492,14 +393,6 @@ impl FormalMode {
             FormalMode::Cover => "cover",
         }
     }
-    fn needs_extra_job(self) -> bool {
-        match self {
-            FormalMode::BMC => false,
-            FormalMode::Prove => true,
-            FormalMode::Live => false,
-            FormalMode::Cover => false,
-        }
-    }
 }
 
 impl fmt::Display for FormalMode {
@@ -721,12 +614,6 @@ impl FormalArgs {
         cmd.arg(sby_file.file_name().unwrap());
         cmd.args(&self.sby_extra_args);
         cmd.current_dir(&output.verilog.firrtl.output_dir);
-        let new_minimum_count = if self.mode.needs_extra_job() {
-            NonZeroUsize::new(2).unwrap()
-        } else {
-            NonZeroUsize::new(1).unwrap()
-        };
-        let new_minimum_count = AcquiredJob::max_available_job_count().min(new_minimum_count);
         let mut captured_output = String::new();
         let cache_file = output.cache_file();
         let do_cache = if let Some(contents_hash) = contents_hash.filter(|_| self.cache_results) {
@@ -752,13 +639,11 @@ impl FormalArgs {
             false
         };
         let _ = fs::remove_file(&cache_file);
-        let status = acquired_job.increase_job_count(new_minimum_count, |acquired_job| {
-            self.verilog.firrtl.base.run_external_command(
-                acquired_job,
-                cmd,
-                do_cache.then_some(&mut captured_output),
-            )
-        })?;
+        let status = self.verilog.firrtl.base.run_external_command(
+            acquired_job,
+            cmd,
+            do_cache.then_some(&mut captured_output),
+        )?;
         let result = if status.success() {
             Ok(output)
         } else {
diff --git a/crates/fayalite/src/util.rs b/crates/fayalite/src/util.rs
index 95f5793..f66654f 100644
--- a/crates/fayalite/src/util.rs
+++ b/crates/fayalite/src/util.rs
@@ -27,4 +27,5 @@ pub use misc::{
     interned_bit, iter_eq_by, BitSliceWriteWithBase, DebugAsDisplay, DebugAsRawString, MakeMutSlice,
 };
 
+pub mod job_server;
 pub mod ready_valid;
diff --git a/crates/fayalite/src/util/job_server.rs b/crates/fayalite/src/util/job_server.rs
new file mode 100644
index 0000000..376ddc0
--- /dev/null
+++ b/crates/fayalite/src/util/job_server.rs
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use ctor::ctor;
+use jobslot::{Acquired, Client};
+use std::{
+    ffi::OsString,
+    mem,
+    num::NonZeroUsize,
+    sync::{Condvar, Mutex, Once, OnceLock},
+    thread::spawn,
+};
+
+fn get_or_make_client() -> &'static Client {
+    #[ctor]
+    static CLIENT: OnceLock<Client> = unsafe {
+        match Client::from_env() {
+            Some(client) => OnceLock::from(client),
+            None => OnceLock::new(),
+        }
+    };
+
+    CLIENT.get_or_init(|| {
+        let mut available_parallelism = None;
+        let mut args = std::env::args_os().skip(1);
+        while let Some(arg) = args.next() {
+            const TEST_THREADS_OPTION: &'static [u8] = b"--test-threads";
+            if arg.as_encoded_bytes().starts_with(TEST_THREADS_OPTION) {
+                match arg.as_encoded_bytes().get(TEST_THREADS_OPTION.len()) {
+                    Some(b'=') => {
+                        let mut arg = arg.into_encoded_bytes();
+                        arg.drain(..=TEST_THREADS_OPTION.len());
+                        available_parallelism = Some(arg);
+                        break;
+                    }
+                    None => {
+                        available_parallelism = args.next().map(OsString::into_encoded_bytes);
+                        break;
+                    }
+                    _ => {}
+                }
+            }
+        }
+        let available_parallelism = if let Some(available_parallelism) = available_parallelism
+            .as_deref()
+            .and_then(|v| std::str::from_utf8(v).ok())
+            .and_then(|v| v.parse().ok())
+        {
+            available_parallelism
+        } else if let Ok(available_parallelism) = std::thread::available_parallelism() {
+            available_parallelism
+        } else {
+            NonZeroUsize::new(1).unwrap()
+        };
+        Client::new_with_fifo(available_parallelism.get() - 1).expect("failed to create job server")
+    })
+}
+
+struct State {
+    waiting_count: usize,
+    available: Vec<Acquired>,
+    implicit_available: bool,
+}
+
+impl State {
+    fn total_available(&self) -> usize {
+        self.available.len() + self.implicit_available as usize
+    }
+    fn additional_waiting(&self) -> usize {
+        self.waiting_count.saturating_sub(self.total_available())
+    }
+}
+
+static STATE: Mutex<State> = Mutex::new(State {
+    waiting_count: 0,
+    available: Vec::new(),
+    implicit_available: true,
+});
+static COND_VAR: Condvar = Condvar::new();
+
+#[derive(Debug)]
+enum AcquiredJobInner {
+    FromJobServer(Acquired),
+    ImplicitJob,
+}
+
+#[derive(Debug)]
+pub struct AcquiredJob {
+    job: AcquiredJobInner,
+}
+
+impl AcquiredJob {
+    fn start_acquire_thread() {
+        static STARTED_THREAD: Once = Once::new();
+        STARTED_THREAD.call_once(|| {
+            spawn(|| {
+                let mut acquired = None;
+                let client = get_or_make_client();
+                let mut state = STATE.lock().unwrap();
+                loop {
+                    state = if state.additional_waiting() == 0 {
+                        if acquired.is_some() {
+                            drop(state);
+                            drop(acquired.take()); // drop Acquired outside of lock
+                            STATE.lock().unwrap()
+                        } else {
+                            COND_VAR.wait(state).unwrap()
+                        }
+                    } else if acquired.is_some() {
+                        // allocate space before moving Acquired to ensure we
+                        // drop Acquired outside of the lock on panic
+                        state.available.reserve(1);
+                        state.available.push(acquired.take().unwrap());
+                        COND_VAR.notify_all();
+                        state
+                    } else {
+                        drop(state);
+                        acquired = Some(
+                            client
+                                .acquire()
+                                .expect("can't acquire token from job server"),
+                        );
+                        STATE.lock().unwrap()
+                    };
+                }
+            });
+        });
+    }
+    fn acquire_inner(block: bool) -> Option<Self> {
+        Self::start_acquire_thread();
+        let mut state = STATE.lock().unwrap();
+        loop {
+            if let Some(acquired) = state.available.pop() {
+                return Some(Self {
+                    job: AcquiredJobInner::FromJobServer(acquired),
+                });
+            }
+            if state.implicit_available {
+                state.implicit_available = false;
+                return Some(Self {
+                    job: AcquiredJobInner::ImplicitJob,
+                });
+            }
+            if !block {
+                return None;
+            }
+            state.waiting_count += 1;
+            state = COND_VAR.wait(state).unwrap();
+            state.waiting_count -= 1;
+        }
+    }
+    pub fn try_acquire() -> Option<Self> {
+        Self::acquire_inner(false)
+    }
+    pub fn acquire() -> Self {
+        Self::acquire_inner(true).expect("failed to acquire token")
+    }
+    pub fn run_command<R>(
+        &mut self,
+        cmd: std::process::Command,
+        f: impl FnOnce(&mut std::process::Command) -> std::io::Result<R>,
+    ) -> std::io::Result<R> {
+        get_or_make_client().configure_make_and_run_with_fifo(cmd, f)
+    }
+}
+
+impl Drop for AcquiredJob {
+    fn drop(&mut self) {
+        let mut state = STATE.lock().unwrap();
+        match &self.job {
+            AcquiredJobInner::FromJobServer(_) => {
+                if state.waiting_count > state.available.len() + state.implicit_available as usize {
+                    // allocate space before moving Acquired to ensure we
+                    // drop Acquired outside of the lock on panic
+                    state.available.reserve(1);
+                    let AcquiredJobInner::FromJobServer(acquired) =
+                        mem::replace(&mut self.job, AcquiredJobInner::ImplicitJob)
+                    else {
+                        unreachable!()
+                    };
+                    state.available.push(acquired);
+                    COND_VAR.notify_all();
+                }
+            }
+            AcquiredJobInner::ImplicitJob => {
+                state.implicit_available = true;
+                if state.waiting_count > state.available.len() {
+                    COND_VAR.notify_all();
+                }
+            }
+        }
+    }
+}

From cb17913004259b6e0908a477a67e5a6b621b5c1c Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 15 Oct 2024 21:32:38 -0700
Subject: [PATCH 072/190] limit sby to one thread each since it seems not to
 respect job count in parallel mode

---
 crates/fayalite/src/cli.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index a236c77..1030474 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -610,6 +610,7 @@ impl FormalArgs {
         });
         std::fs::write(&sby_file, sby_contents)?;
         let mut cmd = process::Command::new(&self.sby);
+        cmd.arg("-j1"); // sby seems not to respect job count in parallel mode
         cmd.arg("-f");
         cmd.arg(sby_file.file_name().unwrap());
         cmd.args(&self.sby_extra_args);

From 0c9c48a06651671d74a0c5114625aa2e3674a54b Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 17 Oct 2024 21:05:18 -0700
Subject: [PATCH 073/190] split out deps into separate workflow with better
 caching using deps.yml from cpu.git

---
 .forgejo/workflows/deps.yml | 77 +++++++++++++++++++++++++++++++++++++
 .forgejo/workflows/test.yml | 41 +++++++-------------
 2 files changed, 90 insertions(+), 28 deletions(-)
 create mode 100644 .forgejo/workflows/deps.yml

diff --git a/.forgejo/workflows/deps.yml b/.forgejo/workflows/deps.yml
new file mode 100644
index 0000000..3b7e537
--- /dev/null
+++ b/.forgejo/workflows/deps.yml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: LGPL-3.0-or-later
+# See Notices.txt for copyright information
+on:
+  workflow_call:
+    outputs:
+      cache-primary-key:
+        value: ${{ jobs.deps.outputs.cache-primary-key }}
+
+jobs:
+  deps:
+    runs-on: debian-12
+    outputs:
+      cache-primary-key: ${{ steps.restore-deps.outputs.cache-primary-key }}
+    steps:
+      - uses: https://code.forgejo.org/actions/checkout@v3
+        with:
+          fetch-depth: 0
+      - uses: https://code.forgejo.org/actions/cache/restore@v3
+        id: restore-deps
+        with:
+          path: deps
+          key: deps-${{ runner.os }}-${{ hashFiles('.forgejo/workflows/deps.yml') }}
+          lookup-only: true
+      - name: Install Apt packages
+        if: steps.restore-deps.outputs.cache-hit != 'true'
+        run: |
+          apt-get update -qq
+          apt-get install -qq \
+            bison \
+            build-essential \
+            ccache \
+            clang \
+            cvc5 \
+            flex \
+            gawk \
+            g++ \
+            git \
+            libboost-filesystem-dev \
+            libboost-python-dev \
+            libboost-system-dev \
+            libffi-dev \
+            libreadline-dev \
+            lld \
+            pkg-config \
+            python3 \
+            python3-click \
+            tcl-dev \
+            zlib1g-dev
+      - name: Install Firtool
+        if: steps.restore-deps.outputs.cache-hit != 'true'
+        run: |
+          mkdir -p deps
+          wget -O deps/firrtl.tar.gz https://github.com/llvm/circt/releases/download/firtool-1.86.0/firrtl-bin-linux-x64.tar.gz
+          sha256sum -c - <<<'bf6f4ab18ae76f135c944efbd81e25391c31c1bd0617c58ab0592640abefee14  deps/firrtl.tar.gz'
+          tar -C deps -xvaf deps/firrtl.tar.gz
+          rm -rf deps/firtool
+          mv deps/firtool-1.86.0 deps/firtool
+      - name: Get SymbiYosys
+        if: steps.restore-deps.outputs.cache-hit != 'true'
+        run: |
+          git clone --depth=1 --branch=yosys-0.45 https://github.com/YosysHQ/sby.git deps/sby
+      - name: Build Z3
+        if: steps.restore-deps.outputs.cache-hit != 'true'
+        run: |
+          git clone --depth=1 --recursive --branch=z3-4.13.3 https://github.com/Z3Prover/z3.git deps/z3
+          (cd deps/z3; PYTHON=python3 ./configure --prefix=/usr/local)
+          make -C deps/z3/build -j"$(nproc)"
+      - name: Build Yosys
+        if: steps.restore-deps.outputs.cache-hit != 'true'
+        run: |
+          git clone --depth=1 --recursive --branch=0.45 https://github.com/YosysHQ/yosys.git deps/yosys
+          make -C deps/yosys -j"$(nproc)"
+      - uses: https://code.forgejo.org/actions/cache/save@v3
+        if: steps.restore-deps.outputs.cache-hit != 'true'
+        with:
+          path: deps
+          key: ${{ steps.restore-deps.outputs.cache-primary-key }}
diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index 1246015..969d691 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -3,8 +3,11 @@
 on: [push, pull_request]
 
 jobs:
+  deps:
+    uses: ./.forgejo/workflows/deps.yml
   test:
     runs-on: debian-12
+    needs: deps
     steps:
       - uses: https://code.forgejo.org/actions/checkout@v3
         with:
@@ -33,39 +36,21 @@ jobs:
             python3-click \
             tcl-dev \
             z3 \
-            zlib1g-dev \
-      - name: Cache ccache dir
-        uses: https://code.forgejo.org/actions/cache@v3
-        with:
-          path: .ccache
-          key: ${{ runner.os }}-${{ github.sha }}
-          restore-keys: |
-            ${{ runner.os }}-
-      - name: Setup ccache
-        run: |
-          ccache --set-config=cache_dir="${{ github.workspace }}/.ccache"
-          ccache --set-config=compression=true
-          ccache --set-config=compression_level=6
-          ccache -M 4G
-          ccache -z
-          export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
-          echo "$PATH" >> "$GITHUB_PATH"
+            zlib1g-dev
       - run: |
           curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.80.1
           source "$HOME/.cargo/env"
           echo "$PATH" >> "$GITHUB_PATH"
+      - uses: https://code.forgejo.org/actions/cache/restore@v3
+        with:
+          path: deps
+          key: ${{ needs.deps.outputs.cache-primary-key }}
+          fail-on-cache-miss: true
       - run: |
-          git clone --depth=1 --branch=yosys-0.45 https://github.com/YosysHQ/sby.git
-          make -C sby install
-      - run: |
-          git clone --depth=1 --recursive --branch=0.45 https://github.com/YosysHQ/yosys.git
-          make -C yosys -j2
-          make -C yosys install
-      - run: |
-          wget -O firrtl.tar.gz https://github.com/llvm/circt/releases/download/firtool-1.86.0/firrtl-bin-linux-x64.tar.gz
-          sha256sum -c - <<<'bf6f4ab18ae76f135c944efbd81e25391c31c1bd0617c58ab0592640abefee14  firrtl.tar.gz'
-          tar -xvaf firrtl.tar.gz
-          export PATH="$(realpath firtool-1.86.0/bin):$PATH"
+          make -C deps/z3/build install
+          make -C deps/sby install
+          make -C deps/yosys install
+          export PATH="$(realpath deps/firtool/bin):$PATH"
           echo "$PATH" >> "$GITHUB_PATH"
       - uses: https://github.com/Swatinem/rust-cache@v2
         with:

From 5bd0de48b70aae1fea8ea9ab65704f7b86524488 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 30 Oct 2024 19:36:05 -0700
Subject: [PATCH 074/190] change to version 0.2.1

---
 Cargo.lock | 8 ++++----
 Cargo.toml | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 7a2a2ac..500bd34 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -301,7 +301,7 @@ checksum = "25cbce373ec4653f1a01a31e8a5e5ec0c622dc27ff9c4e6606eefef5cbbed4a5"
 
 [[package]]
 name = "fayalite"
-version = "0.2.0"
+version = "0.2.1"
 dependencies = [
  "bitvec",
  "blake3",
@@ -324,14 +324,14 @@ dependencies = [
 
 [[package]]
 name = "fayalite-proc-macros"
-version = "0.2.0"
+version = "0.2.1"
 dependencies = [
  "fayalite-proc-macros-impl",
 ]
 
 [[package]]
 name = "fayalite-proc-macros-impl"
-version = "0.2.0"
+version = "0.2.1"
 dependencies = [
  "base16ct",
  "num-bigint",
@@ -345,7 +345,7 @@ dependencies = [
 
 [[package]]
 name = "fayalite-visit-gen"
-version = "0.2.0"
+version = "0.2.1"
 dependencies = [
  "indexmap",
  "prettyplease",
diff --git a/Cargo.toml b/Cargo.toml
index da104c2..b6b8616 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -5,7 +5,7 @@ resolver = "2"
 members = ["crates/*"]
 
 [workspace.package]
-version = "0.2.0"
+version = "0.2.1"
 license = "LGPL-3.0-or-later"
 edition = "2021"
 repository = "https://git.libre-chip.org/libre-chip/fayalite"
@@ -14,9 +14,9 @@ categories = ["simulation", "development-tools", "compilers"]
 rust-version = "1.80.1"
 
 [workspace.dependencies]
-fayalite-proc-macros = { version = "=0.2.0", path = "crates/fayalite-proc-macros" }
-fayalite-proc-macros-impl = { version = "=0.2.0", path = "crates/fayalite-proc-macros-impl" }
-fayalite-visit-gen = { version = "=0.2.0", path = "crates/fayalite-visit-gen" }
+fayalite-proc-macros = { version = "=0.2.1", path = "crates/fayalite-proc-macros" }
+fayalite-proc-macros-impl = { version = "=0.2.1", path = "crates/fayalite-proc-macros-impl" }
+fayalite-visit-gen = { version = "=0.2.1", path = "crates/fayalite-visit-gen" }
 base16ct = "0.2.0"
 bitvec = { version = "1.0.1", features = ["serde"] }
 blake3 = { version = "1.5.4", features = ["serde"] }

From 20cf0abbcc01d5734ffcfca4c4533d7c72f3a821 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 30 Oct 2024 20:46:11 -0700
Subject: [PATCH 075/190] fix using #[hdl] types like S<{ 1 + 2 }>

---
 crates/fayalite-proc-macros-impl/src/hdl_type_common.rs | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
index 506c153..3f3f817 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
@@ -4163,7 +4163,13 @@ impl MakeHdlTypeExpr for ParsedExpr {
         match self {
             ParsedExpr::Delimited(expr) => expr.make_hdl_type_expr(context),
             ParsedExpr::NamedParamConst(expr) => expr.make_hdl_type_expr(context),
-            ParsedExpr::Other(expr) => (**expr).clone(),
+            ParsedExpr::Other(expr) => {
+                let span = expr.span();
+                let const_usize = known_items::ConstUsize(span);
+                parse_quote_spanned! {expr.span()=>
+                    #const_usize::<{ #expr }>
+                }
+            }
         }
     }
 }

From ee15fd2b9415b68d97cb68074f581c50fa5e1485 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 30 Oct 2024 20:47:10 -0700
Subject: [PATCH 076/190] support #[hdl] type aliases

---
 .../src/hdl_type_alias.rs                     | 133 ++++++++++++++++++
 crates/fayalite-proc-macros-impl/src/lib.rs   |   8 +-
 crates/fayalite/tests/hdl_types.rs            |   8 ++
 crates/fayalite/tests/ui/hdl_types.stderr     |   2 +-
 4 files changed, 148 insertions(+), 3 deletions(-)
 create mode 100644 crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs
new file mode 100644
index 0000000..e5d5f7b
--- /dev/null
+++ b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+use crate::{
+    hdl_type_common::{
+        get_target, ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType,
+        TypesParser,
+    },
+    kw, Errors, HdlAttr,
+};
+use proc_macro2::TokenStream;
+use quote::ToTokens;
+use syn::{parse_quote_spanned, Attribute, Generics, Ident, ItemType, Token, Type, Visibility};
+
+#[derive(Clone, Debug)]
+pub(crate) struct ParsedTypeAlias {
+    pub(crate) attrs: Vec<Attribute>,
+    pub(crate) options: HdlAttr<ItemOptions, kw::hdl>,
+    pub(crate) vis: Visibility,
+    pub(crate) type_token: Token![type],
+    pub(crate) ident: Ident,
+    pub(crate) generics: MaybeParsed<ParsedGenerics, Generics>,
+    pub(crate) eq_token: Token![=],
+    pub(crate) ty: MaybeParsed<ParsedType, Type>,
+    pub(crate) semi_token: Token![;],
+}
+
+impl ParsedTypeAlias {
+    fn parse(item: ItemType) -> syn::Result<Self> {
+        let ItemType {
+            mut attrs,
+            vis,
+            type_token,
+            ident,
+            mut generics,
+            eq_token,
+            ty,
+            semi_token,
+        } = item;
+        let mut errors = Errors::new();
+        let mut options = errors
+            .unwrap_or_default(HdlAttr::<ItemOptions, kw::hdl>::parse_and_take_attr(
+                &mut attrs,
+            ))
+            .unwrap_or_default();
+        errors.ok(options.body.validate());
+        let ItemOptions {
+            outline_generated: _,
+            target: _,
+            custom_bounds,
+            no_static,
+            no_runtime_generics: _,
+        } = options.body;
+        if let Some((no_static,)) = no_static {
+            errors.error(no_static, "no_static is not valid on type aliases");
+        }
+        let generics = if custom_bounds.is_some() {
+            MaybeParsed::Unrecognized(generics)
+        } else if let Some(generics) = errors.ok(ParsedGenerics::parse(&mut generics)) {
+            MaybeParsed::Parsed(generics)
+        } else {
+            MaybeParsed::Unrecognized(generics)
+        };
+        let ty = TypesParser::maybe_run(generics.as_ref(), *ty, &mut errors);
+        errors.finish()?;
+        Ok(Self {
+            attrs,
+            options,
+            vis,
+            type_token,
+            ident,
+            generics,
+            eq_token,
+            ty,
+            semi_token,
+        })
+    }
+}
+
+impl ToTokens for ParsedTypeAlias {
+    fn to_tokens(&self, tokens: &mut TokenStream) {
+        let Self {
+            attrs,
+            options,
+            vis,
+            type_token,
+            ident,
+            generics,
+            eq_token,
+            ty,
+            semi_token,
+        } = self;
+        let ItemOptions {
+            outline_generated: _,
+            target,
+            custom_bounds: _,
+            no_static: _,
+            no_runtime_generics,
+        } = &options.body;
+        let target = get_target(target, ident);
+        let mut type_attrs = attrs.clone();
+        type_attrs.push(parse_quote_spanned! {ident.span()=>
+            #[allow(type_alias_bounds)]
+        });
+        ItemType {
+            attrs: type_attrs,
+            vis: vis.clone(),
+            type_token: *type_token,
+            ident: ident.clone(),
+            generics: generics.into(),
+            eq_token: *eq_token,
+            ty: Box::new(ty.clone().into()),
+            semi_token: *semi_token,
+        }
+        .to_tokens(tokens);
+        if let (MaybeParsed::Parsed(generics), MaybeParsed::Parsed(ty), None) =
+            (generics, ty, no_runtime_generics)
+        {
+            generics.make_runtime_generics(tokens, vis, ident, &target, |context| {
+                ty.make_hdl_type_expr(context)
+            })
+        }
+    }
+}
+
+pub(crate) fn hdl_type_alias_impl(item: ItemType) -> syn::Result<TokenStream> {
+    let item = ParsedTypeAlias::parse(item)?;
+    let outline_generated = item.options.body.outline_generated;
+    let mut contents = item.to_token_stream();
+    if outline_generated.is_some() {
+        contents = crate::outline_generated(contents, "hdl-type-alias-");
+    }
+    Ok(contents)
+}
diff --git a/crates/fayalite-proc-macros-impl/src/lib.rs b/crates/fayalite-proc-macros-impl/src/lib.rs
index 194dbf3..0ffd4d4 100644
--- a/crates/fayalite-proc-macros-impl/src/lib.rs
+++ b/crates/fayalite-proc-macros-impl/src/lib.rs
@@ -16,6 +16,7 @@ use syn::{
 mod fold;
 mod hdl_bundle;
 mod hdl_enum;
+mod hdl_type_alias;
 mod hdl_type_common;
 mod module;
 
@@ -850,6 +851,7 @@ macro_rules! options {
     };
 }
 
+use crate::hdl_type_alias::hdl_type_alias_impl;
 pub(crate) use options;
 
 pub(crate) fn outline_generated(contents: TokenStream, prefix: &str) -> TokenStream {
@@ -906,14 +908,16 @@ pub fn hdl_module(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStre
 
 pub fn hdl_attr(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
     let kw = kw::hdl::default();
-    let item = syn::parse2::<Item>(quote! { #[#kw(#attr)] #item })?;
+    let item = quote! { #[#kw(#attr)] #item };
+    let item = syn::parse2::<Item>(item)?;
     match item {
         Item::Enum(item) => hdl_enum::hdl_enum(item),
         Item::Struct(item) => hdl_bundle::hdl_bundle(item),
         Item::Fn(item) => hdl_module_impl(item),
+        Item::Type(item) => hdl_type_alias_impl(item),
         _ => Err(syn::Error::new(
             Span::call_site(),
-            "top-level #[hdl] can only be used on structs, enums, or functions",
+            "top-level #[hdl] can only be used on structs, enums, type aliases, or functions",
         )),
     }
 }
diff --git a/crates/fayalite/tests/hdl_types.rs b/crates/fayalite/tests/hdl_types.rs
index 4509146..b191016 100644
--- a/crates/fayalite/tests/hdl_types.rs
+++ b/crates/fayalite/tests/hdl_types.rs
@@ -31,6 +31,8 @@ pub enum E<T> {
     A,
     B(UInt<3>),
     C(T),
+    D(TyAlias2),
+    E(TyAlias<Bool, ConstUsize<1>, { 1 + 2 }>),
 }
 
 #[hdl(outline_generated)]
@@ -38,6 +40,12 @@ pub struct S2<T = ()> {
     pub v: E<T>,
 }
 
+#[hdl(outline_generated)]
+pub type TyAlias<T, Sz: Size, const C: usize, D = ()> = Array<S<T, Sz, D>, C>;
+
+#[hdl(outline_generated)]
+pub type TyAlias2 = TyAlias<UInt<8>, ConstUsize<24>, 5>;
+
 // check that #[hdl] properly handles hygiene
 macro_rules! types_in_macros {
     ($a:ident, $b:ident, $c:ident, $d:ident, $e:ident, $f:ident, $A:ident, $B:ident, $C:ident, $D:ident, $E:ident, $F:ident) => {
diff --git a/crates/fayalite/tests/ui/hdl_types.stderr b/crates/fayalite/tests/ui/hdl_types.stderr
index a65d796..d3a3617 100644
--- a/crates/fayalite/tests/ui/hdl_types.stderr
+++ b/crates/fayalite/tests/ui/hdl_types.stderr
@@ -1,4 +1,4 @@
-error: top-level #[hdl] can only be used on structs, enums, or functions
+error: top-level #[hdl] can only be used on structs, enums, type aliases, or functions
  --> tests/ui/hdl_types.rs:5:1
   |
 5 | #[hdl]

From 3d5d8c54b6f2b7bbb0a31458c00139359ca3006e Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 30 Oct 2024 20:55:02 -0700
Subject: [PATCH 077/190] add repository to cache key

---
 .forgejo/workflows/deps.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.forgejo/workflows/deps.yml b/.forgejo/workflows/deps.yml
index 3b7e537..ffaca53 100644
--- a/.forgejo/workflows/deps.yml
+++ b/.forgejo/workflows/deps.yml
@@ -19,7 +19,7 @@ jobs:
         id: restore-deps
         with:
           path: deps
-          key: deps-${{ runner.os }}-${{ hashFiles('.forgejo/workflows/deps.yml') }}
+          key: ${{ github.repository }}-deps-${{ runner.os }}-${{ hashFiles('.forgejo/workflows/deps.yml') }}
           lookup-only: true
       - name: Install Apt packages
         if: steps.restore-deps.outputs.cache-hit != 'true'

From c1f1a8b74982965acb86274d1a621fcdb1a4d751 Mon Sep 17 00:00:00 2001
From: Cesar Strauss <cesar.strauss@inpe.br>
Date: Wed, 20 Nov 2024 17:39:00 -0300
Subject: [PATCH 078/190] Add test module exercising formal verification.

---
 crates/fayalite/tests/formal.rs | 133 ++++++++++++++++++++++++++++++++
 1 file changed, 133 insertions(+)
 create mode 100644 crates/fayalite/tests/formal.rs

diff --git a/crates/fayalite/tests/formal.rs b/crates/fayalite/tests/formal.rs
new file mode 100644
index 0000000..46b8292
--- /dev/null
+++ b/crates/fayalite/tests/formal.rs
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+//! Formal tests in Fayalite
+
+use fayalite::{
+    cli::FormalMode,
+    clock::{Clock, ClockDomain},
+    expr::{CastTo, HdlPartialEq},
+    firrtl::ExportOptions,
+    formal::{any_seq, formal_reset, hdl_assert, hdl_assume},
+    hdl_module,
+    int::{Bool, UInt},
+    module::{connect, connect_any, reg_builder, wire},
+    reset::ToReset,
+    testing::assert_formal,
+};
+
+/// Test hidden state
+///
+/// Hidden state can cause problems for induction, since the formal engine
+/// can assign invalid values to the state registers, making it traverse
+/// valid but unreachable states.
+///
+/// One solution is to go sufficiently in the past so the engine is forced
+/// to eventually take a reachable state. This may be hampered by
+/// existence of loops, then assumptions may be added to break them.
+///
+/// Another solution is to "open the black box" and add additional
+/// assertions involving the hidden state, so that the unreachable states
+/// become invalid as well.
+///
+/// Both approaches are taken here.
+///
+/// See [Claire Wolf's presentation] and [Zipcpu blog article].
+///
+/// [Claire Wolf's presentation]: https://web.archive.org/web/20200115081517fw_/http://www.clifford.at/papers/2017/smtbmc-sby/
+/// [Zipcpu blog article]: https://zipcpu.com/blog/2018/03/10/induction-exercise.html
+mod hidden_state {
+    use super::*;
+    /// Test hidden state by shift registers
+    ///
+    /// The code implement the ideas from an article in the [Zipcpu blog]. Two
+    /// shift registers are fed from the same input, so they should always have
+    /// the same value. However the only observable is a comparison of their
+    /// last bit, all the others are hidden. To complicate matters, an enable
+    /// signal causes a loop in state space.
+    ///
+    /// [Zipcpu blog]: https://zipcpu.com/blog/2018/03/10/induction-exercise.html
+    #[test]
+    fn shift_register() {
+        enum ConstraintMode {
+            WithExtraAssertions,
+            WithExtraAssumptions,
+        }
+        use ConstraintMode::*;
+        #[hdl_module]
+        fn test_module(constraint_mode: ConstraintMode) {
+            #[hdl]
+            let clk: Clock = m.input();
+            #[hdl]
+            let cd = wire();
+            connect(
+                cd,
+                #[hdl]
+                ClockDomain {
+                    clk,
+                    rst: formal_reset().to_reset(),
+                },
+            );
+            // input signal for the shift registers
+            #[hdl]
+            let i: Bool = wire();
+            connect(i, any_seq(Bool));
+            // shift enable signal
+            #[hdl]
+            let en: Bool = wire();
+            connect(en, any_seq(Bool));
+            // comparison output
+            #[hdl]
+            let o: Bool = wire();
+            // shift registers, with enable
+            #[hdl]
+            let r1 = reg_builder().clock_domain(cd).reset(0u8);
+            #[hdl]
+            let r2 = reg_builder().clock_domain(cd).reset(0u8);
+            #[hdl]
+            if en {
+                connect_any(r1, (r1 << 1) | i.cast_to(UInt[1]));
+                connect_any(r2, (r2 << 1) | i.cast_to(UInt[1]));
+            }
+            // compare last bits of both shift registers
+            connect(o, r1[7].cmp_eq(r2[7]));
+
+            // what we want to prove: last bits are always equal
+            hdl_assert(clk, o, "");
+
+            // additional terms below are only needed to assist with the induction proof
+            match constraint_mode {
+                WithExtraAssertions => {
+                    // "Open the box": add assertions about hidden state.
+                    // In this case, the hidden bits are also always equal.
+                    hdl_assert(clk, r1.cmp_eq(r2), "");
+                }
+                WithExtraAssumptions => {
+                    // Break the loop, do not allow "en" to remain low forever
+                    #[hdl]
+                    let past_en_reg = reg_builder().clock_domain(cd).reset(false);
+                    connect(past_en_reg, en);
+                    hdl_assume(clk, past_en_reg | en, "");
+                }
+            }
+        }
+        // we need a minimum of 16 steps so we can constrain all eight shift register bits,
+        // given that we are allowed to disable the shift once every two cycles.
+        assert_formal(
+            "shift_register_with_assumptions",
+            test_module(WithExtraAssumptions),
+            FormalMode::Prove,
+            16,
+            None,
+            ExportOptions::default(),
+        );
+        // here a couple of cycles is enough
+        assert_formal(
+            "shift_register_with_assertions",
+            test_module(WithExtraAssertions),
+            FormalMode::Prove,
+            2,
+            None,
+            ExportOptions::default(),
+        );
+    }
+}

From 3ea0d9892412cbdae1dc8b886d9339e51c532c52 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 20 Nov 2024 22:51:40 -0800
Subject: [PATCH 079/190] always write formal cache json

---
 crates/fayalite/src/cli.rs | 28 +++++++++++++---------------
 1 file changed, 13 insertions(+), 15 deletions(-)

diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index 1030474..66741ef 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -653,21 +653,19 @@ impl FormalArgs {
                 self.sby.display()
             )))
         };
-        if do_cache {
-            fs::write(
-                cache_file,
-                serde_json::to_string_pretty(&FormalCache {
-                    version: FormalCacheVersion::CURRENT,
-                    contents_hash: contents_hash.unwrap(),
-                    stdout_stderr: captured_output,
-                    result: match &result {
-                        Ok(FormalOutput { verilog: _ }) => Ok(FormalCacheOutput {}),
-                        Err(error) => Err(error.to_string()),
-                    },
-                })
-                .expect("serialization shouldn't ever fail"),
-            )?;
-        }
+        fs::write(
+            cache_file,
+            serde_json::to_string_pretty(&FormalCache {
+                version: FormalCacheVersion::CURRENT,
+                contents_hash: contents_hash.unwrap(),
+                stdout_stderr: captured_output,
+                result: match &result {
+                    Ok(FormalOutput { verilog: _ }) => Ok(FormalCacheOutput {}),
+                    Err(error) => Err(error.to_string()),
+                },
+            })
+            .expect("serialization shouldn't ever fail"),
+        )?;
         result
     }
 }

From 6f904148c492a4a5d00ba4030f65b4c7e58140b8 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 7 Nov 2024 01:19:07 -0800
Subject: [PATCH 080/190] WIP adding simulator

---
 crates/fayalite/src/lib.rs             |   1 +
 crates/fayalite/src/sim.rs             | 206 +++++++++++
 crates/fayalite/src/sim/interpreter.rs | 464 +++++++++++++++++++++++++
 3 files changed, 671 insertions(+)
 create mode 100644 crates/fayalite/src/sim.rs
 create mode 100644 crates/fayalite/src/sim/interpreter.rs

diff --git a/crates/fayalite/src/lib.rs b/crates/fayalite/src/lib.rs
index eedb1bb..fba7ada 100644
--- a/crates/fayalite/src/lib.rs
+++ b/crates/fayalite/src/lib.rs
@@ -46,6 +46,7 @@ pub mod module;
 pub mod prelude;
 pub mod reg;
 pub mod reset;
+pub mod sim;
 pub mod source_location;
 pub mod testing;
 pub mod ty;
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
new file mode 100644
index 0000000..3aa69a6
--- /dev/null
+++ b/crates/fayalite/src/sim.rs
@@ -0,0 +1,206 @@
+//! Fayalite Simulation
+
+use crate::{
+    bundle::{Bundle, BundleType},
+    enum_::Enum,
+    expr::Expr,
+    int::Bool,
+    intern::{Intern, Interned},
+    module::{
+        Block, Module, ModuleBody, NormalModuleBody, Stmt, StmtConnect, StmtFormal, StmtIf,
+        StmtMatch,
+    },
+    sim::interpreter::{Insn, Insns, InsnsBuilding},
+    source_location::SourceLocation,
+};
+use hashbrown::HashMap;
+use std::{cell::RefCell, rc::Rc};
+
+mod interpreter;
+
+#[derive(Debug)]
+struct CompilingModule {
+    compiled_module: Option<CompiledModule>,
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+enum CondStack {
+    Always,
+    IfTrue {
+        parent: Interned<CondStack>,
+        cond: Expr<Bool>,
+        source_location: SourceLocation,
+    },
+    IfFalse {
+        parent: Interned<CondStack>,
+        cond: Expr<Bool>,
+        source_location: SourceLocation,
+    },
+    MatchArm {
+        parent: Interned<CondStack>,
+        enum_expr: Expr<Enum>,
+        variant_index: usize,
+        source_location: SourceLocation,
+    },
+}
+
+#[derive(Debug)]
+pub struct Compiler {
+    insns: Insns<InsnsBuilding>,
+    modules: HashMap<Interned<Module<Bundle>>, Rc<RefCell<CompilingModule>>>,
+    module_queue: Vec<Interned<Module<Bundle>>>,
+}
+
+impl Compiler {
+    pub fn new() -> Self {
+        Self {
+            insns: Insns::new(),
+            modules: HashMap::new(),
+            module_queue: Vec::new(),
+        }
+    }
+    pub fn add_module(&mut self, module: Interned<Module<Bundle>>) {
+        self.modules.entry(module).or_insert_with(|| {
+            self.module_queue.push(module);
+            Rc::new(RefCell::new(CompilingModule {
+                compiled_module: None,
+            }))
+        });
+    }
+    fn compile_block(
+        &mut self,
+        module: Interned<Module<Bundle>>,
+        block: Block,
+        cond_stack: Interned<CondStack>,
+    ) {
+        let Block { memories, stmts } = block;
+        for memory in memories {
+            todo!("implement memory");
+        }
+        for stmt in stmts {
+            match stmt {
+                Stmt::Connect(StmtConnect {
+                    lhs,
+                    rhs,
+                    source_location,
+                }) => todo!(),
+                Stmt::Formal(StmtFormal {
+                    kind,
+                    clk,
+                    pred,
+                    en,
+                    text,
+                    source_location,
+                }) => todo!("implement simulating formal statements"),
+                Stmt::If(StmtIf {
+                    cond,
+                    source_location,
+                    blocks: [then_block, else_block],
+                }) => {
+                    self.compile_block(
+                        module,
+                        then_block,
+                        CondStack::IfTrue {
+                            parent: cond_stack,
+                            cond,
+                            source_location,
+                        }
+                        .intern_sized(),
+                    );
+                    self.compile_block(
+                        module,
+                        else_block,
+                        CondStack::IfFalse {
+                            parent: cond_stack,
+                            cond,
+                            source_location,
+                        }
+                        .intern_sized(),
+                    );
+                }
+                Stmt::Match(StmtMatch {
+                    expr,
+                    source_location,
+                    blocks,
+                }) => {
+                    for (variant_index, block) in blocks.into_iter().enumerate() {
+                        self.compile_block(
+                            module,
+                            block,
+                            CondStack::MatchArm {
+                                parent: cond_stack,
+                                enum_expr: expr,
+                                variant_index,
+                                source_location,
+                            }
+                            .intern_sized(),
+                        );
+                    }
+                }
+                Stmt::Declaration(stmt_declaration) => todo!(),
+            }
+        }
+    }
+    fn compile_module(&mut self, module: Interned<Module<Bundle>>) -> CompiledModule {
+        let step_entry_pc = self.insns.next_insn_pc();
+        match module.body() {
+            ModuleBody::Normal(NormalModuleBody { body }) => {
+                self.compile_block(module, body, CondStack::Always.intern_sized())
+            }
+            ModuleBody::Extern(_extern_module_body) => {
+                todo!("simulating extern module: {}", module.name_id());
+            }
+        }
+        self.insns.push(Insn::Return, module.source_location());
+        CompiledModule { step_entry_pc }
+    }
+    pub fn run(mut self) -> Compiled {
+        while let Some(module) = self.module_queue.pop() {
+            let compiling_module = self.modules[&module].clone();
+            let mut compiling_module = compiling_module.borrow_mut();
+            let CompilingModule { compiled_module } = &mut *compiling_module;
+            assert!(compiled_module.is_none());
+            *compiled_module = Some(self.compile_module(module));
+        }
+        Compiled {
+            insns: Insns::from(self.insns).intern_sized(),
+            modules: self
+                .modules
+                .into_iter()
+                .map(|(module, compiling_module)| {
+                    (
+                        module,
+                        Rc::into_inner(compiling_module)
+                            .expect("only reference is Compiler::modules")
+                            .into_inner()
+                            .compiled_module
+                            .expect("module is compiled by Compiler::run"),
+                    )
+                })
+                .collect(),
+        }
+    }
+}
+
+#[derive(Debug)]
+struct CompiledModule {
+    step_entry_pc: usize,
+}
+
+#[derive(Debug)]
+pub struct Compiled {
+    insns: Interned<Insns>,
+    modules: HashMap<Interned<Module<Bundle>>, CompiledModule>,
+}
+
+impl Compiled {
+    pub fn new<T: BundleType>(module: Module<T>) -> Self {
+        let mut compiler = Compiler::new();
+        compiler.add_module(module.canonical().intern());
+        compiler.run()
+    }
+}
+
+pub struct Simulation {
+    state: interpreter::State,
+}
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
new file mode 100644
index 0000000..eed64e4
--- /dev/null
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -0,0 +1,464 @@
+use crate::{
+    intern::{Intern, Interned},
+    source_location::SourceLocation,
+};
+use num_bigint::BigInt;
+use std::{convert::Infallible, fmt, hash::Hash};
+
+pub(crate) type SmallUInt = u64;
+pub(crate) type SmallSInt = i64;
+
+macro_rules! impl_insns {
+    (
+        #[next_macro = $next_macro:ident, branch_macro = $branch_macro:ident]
+        $vis:vis fn $State:ident::$run:ident(&mut $self:ident, $insns:ident: &[$Insn:ident]) -> $run_ret_ty:ty {
+            #[pc]
+            let mut $pc:ident: usize = $pc_init:expr;
+            setup! {
+                $($setup:tt)*
+            }
+            $(let mut $local:ident = $local_init:expr;)*
+            main_loop!();
+            cleanup! {
+                $($cleanup:tt)*
+            }
+        }
+        $(
+            $(#[$insn_meta:meta])*
+            $insn_name:ident $({
+                $(
+                    $(#[$field_meta:meta])*
+                    $field_name:ident: $field_ty:ty,
+                )*
+            })? => $block:block
+        )+
+    ) => {
+        #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)]
+        $vis enum $Insn {
+            $(
+                $(#[$insn_meta])*
+                $insn_name $({
+                    $(
+                        $(#[$field_meta])*
+                        $field_name: $field_ty,
+                    )*
+                })?,
+            )+
+        }
+
+        impl $State {
+            $vis fn $run(&mut $self, $insns: &[$Insn]) -> $run_ret_ty {
+                let mut $pc: usize = $pc_init;
+                $($setup)*
+                let mut insn = $insns[$pc];
+                let retval = 'main_loop: loop {
+                    macro_rules! $next_macro {
+                        () => {
+                            $pc += 1;
+                            insn = $insns[$pc];
+                            continue 'main_loop;
+                        };
+                    }
+                    macro_rules! $branch_macro {
+                        ($next_pc:expr) => {
+                            $pc = $next_pc;
+                            insn = $insns[$pc];
+                            continue 'main_loop;
+                        };
+                    }
+                    let _: Infallible = match insn {
+                        $(
+                            $Insn::$insn_name $({
+                                $(
+                                    $field_name,
+                                )*
+                            })? => {
+                                $block
+                            }
+                        )+
+                    };
+                };
+                $($cleanup)*
+                retval
+            }
+        }
+    };
+}
+
+pub(crate) trait InsnsBuildingKind: Copy + Eq + fmt::Debug + Hash + Default {
+    type BoxedSlice<T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static>: fmt::Debug
+        + Clone
+        + Eq
+        + std::ops::Deref<Target = [T]>;
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+pub(crate) struct InsnsBuildingDone;
+
+impl InsnsBuildingKind for InsnsBuildingDone {
+    type BoxedSlice<T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static> = Interned<[T]>;
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+pub(crate) struct InsnsBuilding;
+
+impl InsnsBuildingKind for InsnsBuilding {
+    type BoxedSlice<T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static> = Vec<T>;
+}
+
+#[derive(Clone, PartialEq, Eq, Hash)]
+pub(crate) struct Insns<BK: InsnsBuildingKind = InsnsBuildingDone> {
+    insns: BK::BoxedSlice<Insn>,
+    small_stack_size: usize,
+    big_stack_size: usize,
+    small_state_debug_names: BK::BoxedSlice<Interned<str>>,
+    big_state_debug_names: BK::BoxedSlice<Interned<str>>,
+    insn_source_locations: BK::BoxedSlice<SourceLocation>,
+}
+
+struct InsnsDebug<'a> {
+    insns: &'a [Insn],
+    insn_source_locations: &'a [SourceLocation],
+}
+
+impl<'a> fmt::Debug for InsnsDebug<'a> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let mut debug_list = f.debug_list();
+        let mut last_source_location = None;
+        for (insn, source_location) in self.insns.iter().zip(self.insn_source_locations) {
+            if Some(source_location) != last_source_location {
+                debug_list.entry(&format_args!("// at: {source_location}\n{insn:?}"));
+            } else {
+                debug_list.entry(insn);
+            }
+            last_source_location = Some(source_location);
+        }
+        debug_list.finish()
+    }
+}
+
+impl<BK: InsnsBuildingKind> fmt::Debug for Insns<BK> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            insns,
+            small_stack_size,
+            big_stack_size,
+            small_state_debug_names,
+            big_state_debug_names,
+            insn_source_locations,
+        } = self;
+        f.debug_struct("Insns")
+            .field("small_stack_size", small_stack_size)
+            .field("big_stack_size", big_stack_size)
+            .field("small_state_debug_names", small_state_debug_names)
+            .field("big_state_debug_names", big_state_debug_names)
+            .field(
+                "insns",
+                &InsnsDebug {
+                    insns,
+                    insn_source_locations,
+                },
+            )
+            .finish_non_exhaustive()
+    }
+}
+
+impl Insns<InsnsBuilding> {
+    pub(crate) fn new() -> Self {
+        Self {
+            insns: Vec::new(),
+            small_stack_size: 0,
+            big_stack_size: 0,
+            small_state_debug_names: Vec::new(),
+            big_state_debug_names: Vec::new(),
+            insn_source_locations: Vec::new(),
+        }
+    }
+    pub(crate) fn last_insn_pc(&self) -> usize {
+        self.insns
+            .len()
+            .checked_sub(1)
+            .expect("no last instruction")
+    }
+    pub(crate) fn next_insn_pc(&self) -> usize {
+        self.insns.len()
+    }
+    pub(crate) fn push(&mut self, insn: Insn, source_location: SourceLocation) {
+        self.insns.push(insn);
+        self.insn_source_locations.push(source_location);
+    }
+}
+
+impl From<Insns<InsnsBuilding>> for Insns {
+    fn from(input: Insns<InsnsBuilding>) -> Self {
+        let Insns {
+            insns,
+            small_stack_size,
+            big_stack_size,
+            small_state_debug_names,
+            big_state_debug_names,
+            insn_source_locations,
+        } = input;
+        Insns {
+            insns: Intern::intern_owned(insns),
+            small_stack_size,
+            big_stack_size,
+            small_state_debug_names: Intern::intern_owned(small_state_debug_names),
+            big_state_debug_names: Intern::intern_owned(big_state_debug_names),
+            insn_source_locations: Intern::intern_owned(insn_source_locations),
+        }
+    }
+}
+
+#[derive(Debug)]
+pub(crate) struct State {
+    pub(crate) insns: Interned<Insns>,
+    pub(crate) pc: usize,
+    pub(crate) small_stack: Box<[SmallUInt]>,
+    pub(crate) small_stack_top: usize,
+    pub(crate) small_states: Box<[SmallUInt]>,
+    pub(crate) big_stack: Box<[BigInt]>,
+    pub(crate) big_stack_top: usize,
+    pub(crate) big_states: Box<[BigInt]>,
+}
+
+impl State {
+    pub(crate) fn setup_call(&mut self, entry_pc: usize) {
+        let Self {
+            insns: _,
+            pc,
+            small_stack: _,
+            small_stack_top,
+            small_states: _,
+            big_stack: _,
+            big_stack_top,
+            big_states: _,
+        } = self;
+        *pc = entry_pc;
+        *small_stack_top = 0;
+        *big_stack_top = 0;
+    }
+}
+
+impl_insns! {
+    #[next_macro = next, branch_macro = branch]
+    pub(crate) fn State::run(&mut self, insns: &[Insn]) -> () {
+        #[pc]
+        let mut pc: usize = self.pc;
+        setup! {
+            let small_states = &mut *self.small_states;
+            let small_stack = &mut *self.small_stack;
+            let mut small_stack_top = self.small_stack_top;
+            macro_rules! small_stack_push {
+                ($v:expr) => {
+                    {
+                        small_stack[small_stack_top] = $v;
+                        small_stack_top += 1;
+                    }
+                };
+            }
+            macro_rules! small_stack_pop {
+                () => {
+                    {
+                        small_stack_top -= 1;
+                        small_stack[small_stack_top]
+                    }
+                };
+            }
+            let big_states = &mut *self.big_states;
+            let big_stack = &mut *self.big_stack;
+            let mut big_stack_top = self.big_stack_top;
+            macro_rules! big_stack_push {
+                ($v:expr) => {
+                    {
+                        big_stack[big_stack_top] = $v;
+                        big_stack_top += 1;
+                    }
+                };
+            }
+            macro_rules! big_stack_pop {
+                () => {
+                    {
+                        big_stack_top -= 1;
+                        big_stack[big_stack_top]
+                    }
+                };
+            }
+        }
+        main_loop!();
+        cleanup! {
+            self.pc = pc;
+            self.small_stack_top = small_stack_top;
+        }
+    }
+    ReadSmall {
+        index: u32,
+    } => {
+        small_stack_push!(small_states[index as usize]);
+        next!();
+    }
+    SExtSmall {
+        /// number of bits in a [`SmallSInt`] that aren't used
+        unused_bit_count: u8,
+    } => {
+        let mut value = small_stack_pop!() as SmallSInt;
+        value <<= unused_bit_count;
+        value >>= unused_bit_count;
+        small_stack_push!(value as SmallUInt);
+        next!();
+    }
+    ZExtSmall {
+        /// number of bits in a [`SmallUInt`] that aren't used
+        unused_bit_count: u8,
+    } => {
+        let mut value = small_stack_pop!();
+        value <<= unused_bit_count;
+        value >>= unused_bit_count;
+        small_stack_push!(value);
+        next!();
+    }
+    AndSmall => {
+        let rhs = small_stack_pop!();
+        let lhs = small_stack_pop!();
+        let value = lhs & rhs;
+        small_stack_push!(value);
+        next!();
+    }
+    OrSmall => {
+        let rhs = small_stack_pop!();
+        let lhs = small_stack_pop!();
+        let value = lhs | rhs;
+        small_stack_push!(value);
+        next!();
+    }
+    XorSmall => {
+        let rhs = small_stack_pop!();
+        let lhs = small_stack_pop!();
+        let value = lhs ^ rhs;
+        small_stack_push!(value);
+        next!();
+    }
+    NotSmall => {
+        let value = small_stack_pop!();
+        small_stack_push!(!value);
+        next!();
+    }
+    CmpEqSmall => {
+        let rhs = small_stack_pop!();
+        let lhs = small_stack_pop!();
+        let value = (lhs == rhs) as SmallUInt;
+        small_stack_push!(value);
+        next!();
+    }
+    CmpNeSmall => {
+        let rhs = small_stack_pop!();
+        let lhs = small_stack_pop!();
+        let value = (lhs != rhs) as SmallUInt;
+        small_stack_push!(value);
+        next!();
+    }
+    CmpLTSmallUInt => {
+        let rhs = small_stack_pop!();
+        let lhs = small_stack_pop!();
+        let value = (lhs < rhs) as SmallUInt;
+        small_stack_push!(value);
+        next!();
+    }
+    CmpLESmallUInt => {
+        let rhs = small_stack_pop!();
+        let lhs = small_stack_pop!();
+        let value = (lhs <= rhs) as SmallUInt;
+        small_stack_push!(value);
+        next!();
+    }
+    CmpGTSmallUInt => {
+        let rhs = small_stack_pop!();
+        let lhs = small_stack_pop!();
+        let value = (lhs > rhs) as SmallUInt;
+        small_stack_push!(value);
+        next!();
+    }
+    CmpGESmallUInt => {
+        let rhs = small_stack_pop!();
+        let lhs = small_stack_pop!();
+        let value = (lhs >= rhs) as SmallUInt;
+        small_stack_push!(value);
+        next!();
+    }
+    CmpLTSmallSInt => {
+        let rhs = small_stack_pop!() as SmallSInt;
+        let lhs = small_stack_pop!() as SmallSInt;
+        let value = (lhs < rhs) as SmallUInt;
+        small_stack_push!(value);
+        next!();
+    }
+    CmpLESmallSInt => {
+        let rhs = small_stack_pop!() as SmallSInt;
+        let lhs = small_stack_pop!() as SmallSInt;
+        let value = (lhs <= rhs) as SmallUInt;
+        small_stack_push!(value);
+        next!();
+    }
+    CmpGTSmallSInt => {
+        let rhs = small_stack_pop!() as SmallSInt;
+        let lhs = small_stack_pop!() as SmallSInt;
+        let value = (lhs > rhs) as SmallUInt;
+        small_stack_push!(value);
+        next!();
+    }
+    CmpGESmallSInt => {
+        let rhs = small_stack_pop!() as SmallSInt;
+        let lhs = small_stack_pop!() as SmallSInt;
+        let value = (lhs >= rhs) as SmallUInt;
+        small_stack_push!(value);
+        next!();
+    }
+    AddSmall => {
+        let rhs = small_stack_pop!();
+        let lhs = small_stack_pop!();
+        let value = lhs.wrapping_add(rhs);
+        small_stack_push!(value);
+        next!();
+    }
+    SubSmall => {
+        let rhs = small_stack_pop!();
+        let lhs = small_stack_pop!();
+        let value = lhs.wrapping_sub(rhs);
+        small_stack_push!(value);
+        next!();
+    }
+    NegSmall => {
+        let value = small_stack_pop!();
+        let value = value.wrapping_neg();
+        small_stack_push!(value);
+        next!();
+    }
+    MulSmall => {
+        let rhs = small_stack_pop!();
+        let lhs = small_stack_pop!();
+        let value = lhs.wrapping_mul(rhs);
+        small_stack_push!(value);
+        next!();
+    }
+    ConstU32Small {
+        value: u32,
+    } => {
+        small_stack_push!(value as SmallUInt);
+        next!();
+    }
+    ConstS32Small {
+        value: i32,
+    } => {
+        small_stack_push!(value as SmallUInt);
+        next!();
+    }
+    WriteSmall {
+        index: u32,
+    } => {
+        small_states[index as usize] = small_stack_pop!();
+        next!();
+    }
+    Return => {
+        break;
+    }
+}

From 479d59b28722c79873e7c5fa1caf1230001b7ee1 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 7 Nov 2024 21:46:34 -0800
Subject: [PATCH 081/190] WIP implementing simulator

---
 crates/fayalite/src/expr/target.rs     |   2 +-
 crates/fayalite/src/sim.rs             | 389 ++++++++--
 crates/fayalite/src/sim/interpreter.rs | 961 ++++++++++++++++++++-----
 3 files changed, 1104 insertions(+), 248 deletions(-)

diff --git a/crates/fayalite/src/expr/target.rs b/crates/fayalite/src/expr/target.rs
index 0f85f62..e95ff84 100644
--- a/crates/fayalite/src/expr/target.rs
+++ b/crates/fayalite/src/expr/target.rs
@@ -313,7 +313,7 @@ impl TargetChild {
     }
 }
 
-#[derive(Clone, PartialEq, Eq, Hash)]
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
 pub enum Target {
     Base(Interned<TargetBase>),
     Child(TargetChild),
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 3aa69a6..3b55379 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -1,28 +1,32 @@
 //! Fayalite Simulation
 
 use crate::{
-    bundle::{Bundle, BundleType},
+    bundle::{Bundle, BundleField, BundleType},
     enum_::Enum,
-    expr::Expr,
-    int::Bool,
-    intern::{Intern, Interned},
-    module::{
-        Block, Module, ModuleBody, NormalModuleBody, Stmt, StmtConnect, StmtFormal, StmtIf,
-        StmtMatch,
+    expr::{
+        target::{
+            Target, TargetBase, TargetPathArrayElement, TargetPathBundleField, TargetPathElement,
+        },
+        Expr,
+    },
+    int::Bool,
+    intern::{Intern, Interned, Memoize},
+    module::{
+        AnnotatedModuleIO, Block, Instance, Module, ModuleBody, NormalModuleBody, Stmt,
+        StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch,
+    },
+    sim::interpreter::{
+        Insn, Insns, InsnsBuilding, InsnsBuildingDone, SlotDebugData, StatePartLayout, TypeIndex,
+        TypeIndexRange, TypeLayout,
     },
-    sim::interpreter::{Insn, Insns, InsnsBuilding},
     source_location::SourceLocation,
+    ty::CanonicalType,
 };
 use hashbrown::HashMap;
-use std::{cell::RefCell, rc::Rc};
+use std::fmt;
 
 mod interpreter;
 
-#[derive(Debug)]
-struct CompilingModule {
-    compiled_module: Option<CompiledModule>,
-}
-
 #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
 enum CondStack {
     Always,
@@ -44,32 +48,279 @@ enum CondStack {
     },
 }
 
+#[derive(PartialEq, Eq, Hash, Clone, Copy)]
+enum InstantiatedModule {
+    Base(Interned<Module<Bundle>>),
+    Child {
+        parent: Interned<InstantiatedModule>,
+        instance: Interned<Instance<Bundle>>,
+    },
+}
+
+impl InstantiatedModule {
+    fn leaf_module(self) -> Interned<Module<Bundle>> {
+        match self {
+            InstantiatedModule::Base(base) => base,
+            InstantiatedModule::Child { instance, .. } => instance.instantiated(),
+        }
+    }
+    fn write_path(self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self {
+            InstantiatedModule::Base(base) => fmt::Debug::fmt(&base.name_id(), f),
+            InstantiatedModule::Child { parent, instance } => {
+                parent.write_path(f)?;
+                write!(f, ".{}", instance.name_id())
+            }
+        }
+    }
+}
+
+impl fmt::Debug for InstantiatedModule {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "InstantiatedModule(")?;
+        self.write_path(f)?;
+        write!(f, ": {})", self.leaf_module().name_id())
+    }
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+struct TargetInInstantiatedModule {
+    instantiated_module: InstantiatedModule,
+    target: Target,
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+struct CompiledBundleField {
+    offset: TypeIndex,
+    ty: CompiledTypeLayout,
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+enum CompiledTypeLayoutBody {
+    Scalar,
+    Array {
+        /// debug names are ignored, use parent's layout instead
+        element: Interned<CompiledTypeLayout>,
+    },
+    Bundle {
+        /// debug names are ignored, use parent's layout instead
+        fields: Interned<[CompiledBundleField]>,
+    },
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+struct CompiledTypeLayout {
+    ty: CanonicalType,
+    layout: TypeLayout<InsnsBuildingDone>,
+    body: CompiledTypeLayoutBody,
+}
+
+impl CompiledTypeLayout {
+    fn with_prefixed_debug_names(self, prefix: &str) -> Self {
+        let Self { ty, layout, body } = self;
+        Self {
+            ty,
+            layout: layout.with_prefixed_debug_names(prefix),
+            body,
+        }
+    }
+    fn get(ty: CanonicalType) -> Self {
+        #[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)]
+        struct MyMemoize;
+        impl Memoize for MyMemoize {
+            type Input = CanonicalType;
+            type InputOwned = CanonicalType;
+            type Output = CompiledTypeLayout;
+
+            fn inner(self, input: &Self::Input) -> Self::Output {
+                match input {
+                    CanonicalType::UInt(_)
+                    | CanonicalType::SInt(_)
+                    | CanonicalType::Bool(_)
+                    | CanonicalType::Enum(_)
+                    | CanonicalType::AsyncReset(_)
+                    | CanonicalType::SyncReset(_)
+                    | CanonicalType::Reset(_)
+                    | CanonicalType::Clock(_) => {
+                        let mut layout = TypeLayout::empty();
+                        let debug_data = SlotDebugData { name: "".intern() };
+                        if input.bit_width() > interpreter::SmallUInt::BITS as usize {
+                            layout.big_slots = StatePartLayout::scalar(debug_data);
+                        } else {
+                            layout.small_slots = StatePartLayout::scalar(debug_data);
+                        };
+                        CompiledTypeLayout {
+                            ty: *input,
+                            layout: layout.into(),
+                            body: CompiledTypeLayoutBody::Scalar,
+                        }
+                    }
+                    CanonicalType::Array(array) => {
+                        let mut layout = TypeLayout::empty();
+                        let element = CompiledTypeLayout::get(array.element()).intern_sized();
+                        for index in 0..array.len() {
+                            layout.allocate(
+                                &element
+                                    .layout
+                                    .with_prefixed_debug_names(&format!("[{index}]")),
+                            );
+                        }
+                        CompiledTypeLayout {
+                            ty: *input,
+                            layout: layout.into(),
+                            body: CompiledTypeLayoutBody::Array { element },
+                        }
+                    }
+                    CanonicalType::Bundle(bundle) => {
+                        let mut layout = TypeLayout::empty();
+                        let fields = bundle
+                            .fields()
+                            .iter()
+                            .map(
+                                |BundleField {
+                                     name,
+                                     flipped: _,
+                                     ty,
+                                 }| {
+                                    let ty = CompiledTypeLayout::get(*ty);
+                                    let offset = layout
+                                        .allocate(
+                                            &ty.layout
+                                                .with_prefixed_debug_names(&format!(".{name}")),
+                                        )
+                                        .start();
+                                    CompiledBundleField { offset, ty }
+                                },
+                            )
+                            .collect();
+                        CompiledTypeLayout {
+                            ty: *input,
+                            layout: layout.into(),
+                            body: CompiledTypeLayoutBody::Bundle { fields },
+                        }
+                    }
+                }
+            }
+        }
+        MyMemoize.get_owned(ty)
+    }
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+struct CompiledValue {
+    layout: CompiledTypeLayout,
+    range: TypeIndexRange,
+    write: Option<(CompiledTypeLayout, TypeIndexRange)>,
+}
+
+impl CompiledValue {
+    fn map(
+        self,
+        mut f: impl FnMut(CompiledTypeLayout, TypeIndexRange) -> (CompiledTypeLayout, TypeIndexRange),
+    ) -> Self {
+        let (layout, range) = f(self.layout, self.range);
+        Self {
+            layout,
+            range,
+            write: self.write.map(|(layout, range)| f(layout, range)),
+        }
+    }
+}
+
 #[derive(Debug)]
 pub struct Compiler {
     insns: Insns<InsnsBuilding>,
-    modules: HashMap<Interned<Module<Bundle>>, Rc<RefCell<CompilingModule>>>,
-    module_queue: Vec<Interned<Module<Bundle>>>,
+    base_module: Interned<Module<Bundle>>,
+    modules: HashMap<InstantiatedModule, CompiledModule>,
+    compiled_values: HashMap<TargetInInstantiatedModule, CompiledValue>,
 }
 
 impl Compiler {
-    pub fn new() -> Self {
+    pub fn new(base_module: Interned<Module<Bundle>>) -> Self {
         Self {
             insns: Insns::new(),
+            base_module,
             modules: HashMap::new(),
-            module_queue: Vec::new(),
+            compiled_values: HashMap::new(),
         }
     }
-    pub fn add_module(&mut self, module: Interned<Module<Bundle>>) {
-        self.modules.entry(module).or_insert_with(|| {
-            self.module_queue.push(module);
-            Rc::new(RefCell::new(CompilingModule {
-                compiled_module: None,
-            }))
-        });
+    fn compile_value(&mut self, target: TargetInInstantiatedModule) -> CompiledValue {
+        if let Some(&retval) = self.compiled_values.get(&target) {
+            return retval;
+        }
+        match target.target {
+            Target::Base(base) => {
+                let unprefixed_layout = CompiledTypeLayout::get(base.canonical_ty());
+                let layout = unprefixed_layout.with_prefixed_debug_names(&format!(
+                    "{:?}.{:?}",
+                    target.instantiated_module,
+                    base.target_name()
+                ));
+                let range = self.insns.allocate_variable(&layout.layout);
+                let write = match *base {
+                    TargetBase::ModuleIO(_)
+                    | TargetBase::MemPort(_)
+                    | TargetBase::Wire(_)
+                    | TargetBase::Instance(_) => None,
+                    TargetBase::Reg(_) => {
+                        let write_layout = unprefixed_layout.with_prefixed_debug_names(&format!(
+                            "{:?}.{:?}$next",
+                            target.instantiated_module,
+                            base.target_name()
+                        ));
+                        Some((
+                            write_layout,
+                            self.insns.allocate_variable(&write_layout.layout),
+                        ))
+                    }
+                };
+                CompiledValue {
+                    range,
+                    layout,
+                    write,
+                }
+            }
+            Target::Child(target_child) => {
+                let parent = self.compile_value(TargetInInstantiatedModule {
+                    instantiated_module: target.instantiated_module,
+                    target: *target_child.parent(),
+                });
+                match *target_child.path_element() {
+                    TargetPathElement::BundleField(TargetPathBundleField { name }) => {
+                        parent.map(|layout, range| {
+                            let CompiledTypeLayout {
+                                ty: CanonicalType::Bundle(bundle),
+                                layout: _,
+                                body: CompiledTypeLayoutBody::Bundle { fields },
+                            } = layout
+                            else {
+                                unreachable!();
+                            };
+                            let field_index = bundle.name_indexes()[&name];
+                            (
+                                fields[field_index].ty,
+                                range.slice(TypeIndexRange::new(
+                                    fields[field_index].offset,
+                                    fields[field_index].ty.layout.len(),
+                                )),
+                            )
+                        })
+                    }
+                    TargetPathElement::ArrayElement(TargetPathArrayElement { index }) => parent
+                        .map(|layout, range| {
+                            let CompiledTypeLayoutBody::Array { element } = layout.body else {
+                                unreachable!();
+                            };
+                            (*element, range.index_array(element.layout.len(), index))
+                        }),
+                    TargetPathElement::DynArrayElement(_) => unreachable!(),
+                }
+            }
+        }
     }
     fn compile_block(
         &mut self,
-        module: Interned<Module<Bundle>>,
+        parent_module: Interned<InstantiatedModule>,
         block: Block,
         cond_stack: Interned<CondStack>,
     ) {
@@ -98,7 +349,7 @@ impl Compiler {
                     blocks: [then_block, else_block],
                 }) => {
                     self.compile_block(
-                        module,
+                        parent_module,
                         then_block,
                         CondStack::IfTrue {
                             parent: cond_stack,
@@ -108,7 +359,7 @@ impl Compiler {
                         .intern_sized(),
                     );
                     self.compile_block(
-                        module,
+                        parent_module,
                         else_block,
                         CondStack::IfFalse {
                             parent: cond_stack,
@@ -125,7 +376,7 @@ impl Compiler {
                 }) => {
                     for (variant_index, block) in blocks.into_iter().enumerate() {
                         self.compile_block(
-                            module,
+                            parent_module,
                             block,
                             CondStack::MatchArm {
                                 parent: cond_stack,
@@ -137,67 +388,79 @@ impl Compiler {
                         );
                     }
                 }
-                Stmt::Declaration(stmt_declaration) => todo!(),
+                Stmt::Declaration(declaration) => match declaration {
+                    StmtDeclaration::Wire(wire) => todo!(),
+                    StmtDeclaration::Reg(reg) => todo!(),
+                    StmtDeclaration::Instance(StmtInstance {
+                        annotations,
+                        instance,
+                    }) => {
+                        self.compile_module(
+                            InstantiatedModule::Child {
+                                parent: parent_module,
+                                instance: instance.intern_sized(),
+                            }
+                            .intern_sized(),
+                        );
+                        todo!()
+                    }
+                },
             }
         }
     }
-    fn compile_module(&mut self, module: Interned<Module<Bundle>>) -> CompiledModule {
-        let step_entry_pc = self.insns.next_insn_pc();
-        match module.body() {
+    fn compile_module(&mut self, module: Interned<InstantiatedModule>) -> &CompiledModule {
+        let module_io = module
+            .leaf_module()
+            .module_io()
+            .iter()
+            .map(
+                |&AnnotatedModuleIO {
+                     annotations: _,
+                     module_io,
+                 }| {
+                    self.compile_value(TargetInInstantiatedModule {
+                        instantiated_module: *module,
+                        target: Target::from(module_io),
+                    })
+                },
+            )
+            .collect();
+        match module.leaf_module().body() {
             ModuleBody::Normal(NormalModuleBody { body }) => {
                 self.compile_block(module, body, CondStack::Always.intern_sized())
             }
             ModuleBody::Extern(_extern_module_body) => {
-                todo!("simulating extern module: {}", module.name_id());
+                todo!("simulating extern module: {:?}", module);
             }
         }
-        self.insns.push(Insn::Return, module.source_location());
-        CompiledModule { step_entry_pc }
+        let hashbrown::hash_map::Entry::Vacant(entry) = self.modules.entry(*module) else {
+            unreachable!("compiled same instantiated module twice");
+        };
+        entry.insert(CompiledModule { module_io })
     }
     pub fn run(mut self) -> Compiled {
-        while let Some(module) = self.module_queue.pop() {
-            let compiling_module = self.modules[&module].clone();
-            let mut compiling_module = compiling_module.borrow_mut();
-            let CompilingModule { compiled_module } = &mut *compiling_module;
-            assert!(compiled_module.is_none());
-            *compiled_module = Some(self.compile_module(module));
-        }
+        self.compile_module(InstantiatedModule::Base(self.base_module).intern_sized());
         Compiled {
             insns: Insns::from(self.insns).intern_sized(),
-            modules: self
-                .modules
-                .into_iter()
-                .map(|(module, compiling_module)| {
-                    (
-                        module,
-                        Rc::into_inner(compiling_module)
-                            .expect("only reference is Compiler::modules")
-                            .into_inner()
-                            .compiled_module
-                            .expect("module is compiled by Compiler::run"),
-                    )
-                })
-                .collect(),
+            modules: self.modules,
         }
     }
 }
 
 #[derive(Debug)]
 struct CompiledModule {
-    step_entry_pc: usize,
+    module_io: Interned<[CompiledValue]>,
 }
 
 #[derive(Debug)]
 pub struct Compiled {
-    insns: Interned<Insns>,
-    modules: HashMap<Interned<Module<Bundle>>, CompiledModule>,
+    insns: Interned<Insns<InsnsBuildingDone>>,
+    modules: HashMap<InstantiatedModule, CompiledModule>,
 }
 
 impl Compiled {
     pub fn new<T: BundleType>(module: Module<T>) -> Self {
-        let mut compiler = Compiler::new();
-        compiler.add_module(module.canonical().intern());
-        compiler.run()
+        Compiler::new(module.canonical().intern()).run()
     }
 }
 
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index eed64e4..06d0025 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -3,21 +3,26 @@ use crate::{
     source_location::SourceLocation,
 };
 use num_bigint::BigInt;
-use std::{convert::Infallible, fmt, hash::Hash};
+use std::{
+    convert::Infallible,
+    fmt,
+    hash::Hash,
+    marker::PhantomData,
+    ops::{Deref, DerefMut, Index, IndexMut},
+};
 
 pub(crate) type SmallUInt = u64;
 pub(crate) type SmallSInt = i64;
 
 macro_rules! impl_insns {
     (
-        #[next_macro = $next_macro:ident, branch_macro = $branch_macro:ident]
-        $vis:vis fn $State:ident::$run:ident(&mut $self:ident, $insns:ident: &[$Insn:ident]) -> $run_ret_ty:ty {
-            #[pc]
-            let mut $pc:ident: usize = $pc_init:expr;
+        #[insn = $Insn:ident, next_macro = $next_macro:ident, branch_macro = $branch_macro:ident]
+        $vis:vis fn $State:ident::$run:ident(&mut $self:ident) -> $run_ret_ty:ty {
+            #[state]
+            let mut $state:ident = $state_init:expr;
             setup! {
                 $($setup:tt)*
             }
-            $(let mut $local:ident = $local_init:expr;)*
             main_loop!();
             cleanup! {
                 $($cleanup:tt)*
@@ -47,22 +52,22 @@ macro_rules! impl_insns {
         }
 
         impl $State {
-            $vis fn $run(&mut $self, $insns: &[$Insn]) -> $run_ret_ty {
-                let mut $pc: usize = $pc_init;
+            $vis fn $run(&mut $self) -> $run_ret_ty {
+                let mut $state = $state_init;
                 $($setup)*
-                let mut insn = $insns[$pc];
+                let mut insn = $state.insns[$state.pc];
                 let retval = 'main_loop: loop {
                     macro_rules! $next_macro {
                         () => {
-                            $pc += 1;
-                            insn = $insns[$pc];
+                            $state.pc += 1;
+                            insn = $state.insns[$state.pc];
                             continue 'main_loop;
                         };
                     }
                     macro_rules! $branch_macro {
                         ($next_pc:expr) => {
-                            $pc = $next_pc;
-                            insn = $insns[$pc];
+                            $state.pc = $next_pc;
+                            insn = $state.insns[$state.pc];
                             continue 'main_loop;
                         };
                     }
@@ -86,34 +91,37 @@ macro_rules! impl_insns {
 }
 
 pub(crate) trait InsnsBuildingKind: Copy + Eq + fmt::Debug + Hash + Default {
-    type BoxedSlice<T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static>: fmt::Debug
+    type Vec<T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static>: fmt::Debug
         + Clone
         + Eq
-        + std::ops::Deref<Target = [T]>;
+        + Hash
+        + Send
+        + Sync
+        + 'static
+        + Default
+        + Deref<Target = [T]>
+        + FromIterator<T>;
 }
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
 pub(crate) struct InsnsBuildingDone;
 
 impl InsnsBuildingKind for InsnsBuildingDone {
-    type BoxedSlice<T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static> = Interned<[T]>;
+    type Vec<T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static> = Interned<[T]>;
 }
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
 pub(crate) struct InsnsBuilding;
 
 impl InsnsBuildingKind for InsnsBuilding {
-    type BoxedSlice<T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static> = Vec<T>;
+    type Vec<T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static> = Vec<T>;
 }
 
 #[derive(Clone, PartialEq, Eq, Hash)]
-pub(crate) struct Insns<BK: InsnsBuildingKind = InsnsBuildingDone> {
-    insns: BK::BoxedSlice<Insn>,
-    small_stack_size: usize,
-    big_stack_size: usize,
-    small_state_debug_names: BK::BoxedSlice<Interned<str>>,
-    big_state_debug_names: BK::BoxedSlice<Interned<str>>,
-    insn_source_locations: BK::BoxedSlice<SourceLocation>,
+pub(crate) struct Insns<BK: InsnsBuildingKind> {
+    insns: BK::Vec<Insn>,
+    insn_source_locations: BK::Vec<SourceLocation>,
+    state_layout: StateLayout<BK>,
 }
 
 struct InsnsDebug<'a> {
@@ -141,17 +149,11 @@ impl<BK: InsnsBuildingKind> fmt::Debug for Insns<BK> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
             insns,
-            small_stack_size,
-            big_stack_size,
-            small_state_debug_names,
-            big_state_debug_names,
             insn_source_locations,
+            state_layout,
         } = self;
         f.debug_struct("Insns")
-            .field("small_stack_size", small_stack_size)
-            .field("big_stack_size", big_stack_size)
-            .field("small_state_debug_names", small_state_debug_names)
-            .field("big_state_debug_names", big_state_debug_names)
+            .field("state_layout", state_layout)
             .field(
                 "insns",
                 &InsnsDebug {
@@ -163,15 +165,662 @@ impl<BK: InsnsBuildingKind> fmt::Debug for Insns<BK> {
     }
 }
 
+pub(crate) trait StatePartKind:
+    Send + Sync + Ord + Hash + fmt::Debug + 'static + Copy + Default
+{
+    const NAME: &'static str;
+    type DebugData: Send + Sync + Eq + Hash + fmt::Debug + 'static + Copy;
+    type State: fmt::Debug + 'static + Clone;
+    type BorrowedState<'a>: 'a;
+    fn new_state(len: StatePartLen<Self>) -> Self::State;
+    fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a>;
+}
+
+macro_rules! make_state_part_kinds {
+    (
+        $(
+            #[state, field = $state_field:ident]
+            impl $StateStatePartKind:ident for $StateKind:ident $state_impl_body:tt
+        )+
+        $(
+            #[type, field = $type_field:ident]
+            impl $TypeStatePartKind:ident for $TypeKind:ident $type_impl_body:tt
+        )+
+    ) => {
+        $(
+            #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy, Default)]
+            pub(crate) struct $StateKind;
+
+            impl $StateStatePartKind for $StateKind $state_impl_body
+        )+
+
+        $(
+            #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy, Default)]
+            pub(crate) struct $TypeKind;
+
+            impl $TypeStatePartKind for $TypeKind $type_impl_body
+        )+
+
+        #[derive(Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct StateLayout<BK: InsnsBuildingKind> {
+            pub(crate) ty: TypeLayout<BK>,
+            $(pub(crate) $state_field: StatePartLayout<$StateKind, BK>,)+
+        }
+
+        impl Copy for StateLayout<InsnsBuildingDone> {}
+
+        impl<BK: InsnsBuildingKind> StateLayout<BK> {
+            pub(crate) fn len(self) -> StateLen {
+                StateLen {
+                    ty: self.ty.len(),
+                    $($state_field: self.$state_field.len(),)+
+                }
+            }
+            pub(crate) fn is_empty(self) -> bool {
+                self.ty.is_empty() $(&& self.$state_field.is_empty())+
+            }
+            pub(crate) fn empty() -> Self {
+                Self {
+                    ty: TypeLayout::empty(),
+                    $($state_field: StatePartLayout::empty(),)+
+                }
+            }
+        }
+
+        impl StateLayout<InsnsBuilding> {
+            pub(crate) fn next_index(&self) -> StateIndex {
+                StateIndex {
+                    ty: self.ty.next_index(),
+                    $($state_field: self.$state_field.next_index(),)+
+                }
+            }
+            pub(crate) fn allocate<BK: InsnsBuildingKind>(
+                &mut self,
+                layout: &StateLayout<BK>,
+            ) -> StateIndexRange {
+                StateIndexRange {
+                    ty: self.ty.allocate(&layout.ty),
+                    $($state_field: self.$state_field.allocate(&layout.$state_field),)+
+                }
+            }
+        }
+
+        impl From<StateLayout<InsnsBuilding>> for StateLayout<InsnsBuildingDone> {
+            fn from(v: StateLayout<InsnsBuilding>) -> Self {
+                Self {
+                    ty: v.ty.into(),
+                    $($state_field: v.$state_field.into(),)+
+                }
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct StateIndexRange {
+            pub(crate) ty: TypeIndexRange,
+            $(pub(crate) $state_field: StatePartIndexRange<$StateKind>,)+
+        }
+
+        impl StateIndexRange {
+            pub(crate) fn start(self) -> StateIndex {
+                StateIndex {
+                    ty: self.ty.start(),
+                    $($state_field: self.$state_field.start(),)+
+                }
+            }
+            pub(crate) fn len(self) -> StateLen {
+                StateLen {
+                    ty: self.ty.len(),
+                    $($state_field: self.$state_field.len(),)+
+                }
+            }
+            pub(crate) fn is_empty(self) -> bool {
+                self.ty.is_empty() $(&& self.$state_field.is_empty())+
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct StateLen {
+            pub(crate) ty: TypeLen,
+            $(pub(crate) $state_field: StatePartLen<$StateKind>,)+
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct StateIndex {
+            pub(crate) ty: TypeIndex,
+            $(pub(crate) $state_field: StatePartIndex<$StateKind>,)+
+        }
+
+        #[derive(Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct TypeLayout<BK: InsnsBuildingKind> {
+            $(pub(crate) $type_field: StatePartLayout<$TypeKind, BK>,)+
+        }
+
+        impl Copy for TypeLayout<InsnsBuildingDone> {}
+
+        impl<BK: InsnsBuildingKind> TypeLayout<BK> {
+            pub(crate) fn len(self) -> TypeLen {
+                TypeLen {
+                    $($type_field: self.$type_field.len(),)+
+                }
+            }
+            pub(crate) fn is_empty(self) -> bool {
+                $(self.$type_field.is_empty())&&+
+            }
+            pub(crate) fn empty() -> Self {
+                Self {
+                    $($type_field: StatePartLayout::empty(),)+
+                }
+            }
+        }
+
+        impl TypeLayout<InsnsBuilding> {
+            pub(crate) fn next_index(&self) -> TypeIndex {
+                TypeIndex {
+                    $($type_field: self.$type_field.next_index(),)+
+                }
+            }
+            pub(crate) fn allocate<BK: InsnsBuildingKind>(
+                &mut self,
+                layout: &TypeLayout<BK>,
+            ) -> TypeIndexRange {
+                TypeIndexRange {
+                    $($type_field: self.$type_field.allocate(&layout.$type_field),)+
+                }
+            }
+        }
+
+        impl From<TypeLayout<InsnsBuilding>> for TypeLayout<InsnsBuildingDone> {
+            fn from(v: TypeLayout<InsnsBuilding>) -> Self {
+                Self {
+                    $($type_field: v.$type_field.into(),)+
+                }
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct TypeIndexRange {
+            $(pub(crate) $type_field: StatePartIndexRange<$TypeKind>,)+
+        }
+
+        impl TypeIndexRange {
+            pub(crate) fn new(start: TypeIndex, len: TypeLen) -> Self {
+                Self {
+                    $($type_field: StatePartIndexRange {
+                        start: start.$type_field,
+                        len: len.$type_field,
+                    },)+
+                }
+            }
+            pub(crate) fn start(self) -> TypeIndex {
+                TypeIndex {
+                    $($type_field: self.$type_field.start(),)+
+                }
+            }
+            pub(crate) fn len(self) -> TypeLen {
+                TypeLen {
+                    $($type_field: self.$type_field.len(),)+
+                }
+            }
+            pub(crate) fn is_empty(self) -> bool {
+                $(self.$type_field.is_empty()) &&+
+            }
+            pub(crate) fn slice(self, index: TypeIndexRange) -> Self {
+                Self {
+                    $($type_field: self.$type_field.slice(index.$type_field),)+
+                }
+            }
+            pub(crate) fn index_array(self, element_size: TypeLen, index: usize) -> Self {
+                Self {
+                    $($type_field: self.$type_field.index_array(element_size.$type_field, index),)+
+                }
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct TypeLen {
+            $(pub(crate) $type_field: StatePartLen<$TypeKind>,)+
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct TypeIndex {
+            $(pub(crate) $type_field: StatePartIndex<$TypeKind>,)+
+        }
+
+        #[derive(Debug)]
+        pub(crate) struct State {
+            pub(crate) insns: Interned<Insns<InsnsBuildingDone>>,
+            pub(crate) pc: usize,
+            $(pub(crate) $state_field: StatePart<$StateKind>,)+
+            $(pub(crate) $type_field: StatePart<$TypeKind>,)+
+        }
+
+        impl State {
+            pub(crate) fn borrow(&mut self) -> BorrowedState<'_> {
+                BorrowedState {
+                    orig_insns: self.insns,
+                    insns: &self.insns.insns,
+                    pc: self.pc,
+                    orig_pc: &mut self.pc,
+                    $($state_field: self.$state_field.borrow(),)+
+                    $($type_field: self.$type_field.borrow(),)+
+                }
+            }
+        }
+
+        #[derive(Debug)]
+        pub(crate) struct BorrowedState<'a> {
+            pub(crate) orig_insns: Interned<Insns<InsnsBuildingDone>>,
+            pub(crate) insns: &'a [Insn],
+            pub(crate) orig_pc: &'a mut usize,
+            pub(crate) pc: usize,
+            $(pub(crate) $state_field: BorrowedStatePart<'a, $StateKind>,)+
+            $(pub(crate) $type_field: BorrowedStatePart<'a, $TypeKind>,)+
+        }
+
+        impl Drop for BorrowedState<'_> {
+            fn drop(&mut self) {
+                *self.orig_pc = self.pc;
+            }
+        }
+    };
+}
+
+make_state_part_kinds! {
+    #[state, field = small_stack]
+    impl StatePartKind for StatePartKindSmallStack {
+        const NAME: &'static str = "SmallStack";
+        type DebugData = ();
+        type State = Stack<SmallUInt>;
+        type BorrowedState<'a> = BorrowedStack<'a, SmallUInt>;
+        fn new_state(len: StatePartLen<Self>) -> Self::State {
+            Stack::new(len.value.try_into().expect("state is too big"))
+        }
+        fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
+            state.borrow()
+        }
+    }
+    #[state, field = big_stack]
+    impl StatePartKind for StatePartKindBigStack {
+        const NAME: &'static str = "BigStack";
+        type DebugData = ();
+        type State = Stack<BigInt>;
+        type BorrowedState<'a> = BorrowedStack<'a, BigInt>;
+        fn new_state(len: StatePartLen<Self>) -> Self::State {
+            Stack::new(len.value.try_into().expect("state is too big"))
+        }
+        fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
+            state.borrow()
+        }
+    }
+    #[type, field = small_slots]
+    impl StatePartKind for StatePartKindSmallSlots {
+        const NAME: &'static str = "SmallSlots";
+        type DebugData = SlotDebugData;
+        type State = Box<[SmallUInt]>;
+        type BorrowedState<'a> = &'a mut [SmallUInt];
+        fn new_state(len: StatePartLen<Self>) -> Self::State {
+            vec![0; len.value.try_into().expect("state is too big")].into_boxed_slice()
+        }
+        fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
+            state
+        }
+    }
+    #[type, field = big_slots]
+    impl StatePartKind for StatePartKindBigSlots {
+        const NAME: &'static str = "BigSlots";
+        type DebugData = SlotDebugData;
+        type State = Box<[BigInt]>;
+        type BorrowedState<'a> = &'a mut [BigInt];
+        fn new_state(len: StatePartLen<Self>) -> Self::State {
+            std::iter::repeat_with(BigInt::default).take(len.value.try_into().expect("state is too big")).collect()
+        }
+        fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
+            state
+        }
+    }
+}
+
+#[derive(Debug, Clone)]
+pub(crate) struct Stack<T> {
+    storage: Box<[T]>,
+    cur_len: usize,
+}
+
+impl<T> Stack<T> {
+    pub(crate) fn new(len: usize) -> Self
+    where
+        T: Default,
+    {
+        Self {
+            storage: std::iter::repeat_with(T::default).take(len).collect(),
+            cur_len: 0,
+        }
+    }
+    pub(crate) fn borrow(&mut self) -> BorrowedStack<'_, T> {
+        BorrowedStack {
+            storage: &mut self.storage,
+            cur_len: self.cur_len,
+            stack_cur_len: &mut self.cur_len,
+        }
+    }
+    pub(crate) fn clear(&mut self) {
+        self.cur_len = 0;
+    }
+}
+
+#[derive(Debug)]
+pub(crate) struct BorrowedStack<'a, T> {
+    storage: &'a mut [T],
+    cur_len: usize,
+    stack_cur_len: &'a mut usize,
+}
+
+impl<'a, T> BorrowedStack<'a, T> {
+    pub(crate) fn push(&mut self, value: T) {
+        self.storage[self.cur_len] = value;
+        self.cur_len += 1;
+    }
+    pub(crate) fn pop(&mut self) -> T
+    where
+        T: Default,
+    {
+        self.cur_len -= 1;
+        std::mem::take(&mut self.storage[self.cur_len])
+    }
+}
+
+impl<T> Drop for BorrowedStack<'_, T> {
+    fn drop(&mut self) {
+        *self.stack_cur_len = self.cur_len;
+    }
+}
+
+#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)]
+pub(crate) struct SlotDebugData {
+    pub(crate) name: Interned<str>,
+}
+
+impl SlotDebugData {
+    pub(crate) fn with_prefixed_debug_names(&self, prefix: &str) -> Self {
+        let mut name = String::with_capacity(self.name.len() + prefix.len());
+        name.push_str(prefix);
+        name.push_str(&self.name);
+        Self {
+            name: Intern::intern_owned(name),
+        }
+    }
+}
+
+impl<K: StatePartKind<DebugData = SlotDebugData>, BK: InsnsBuildingKind> StatePartLayout<K, BK> {
+    pub(crate) fn with_prefixed_debug_names(&self, prefix: &str) -> Self {
+        Self {
+            debug_data: self
+                .debug_data
+                .iter()
+                .map(|v| v.with_prefixed_debug_names(prefix))
+                .collect(),
+            _phantom: PhantomData,
+        }
+    }
+}
+
+impl<BK: InsnsBuildingKind> TypeLayout<BK> {
+    pub(crate) fn with_prefixed_debug_names(&self, prefix: &str) -> Self {
+        Self {
+            small_slots: self.small_slots.with_prefixed_debug_names(prefix),
+            big_slots: self.big_slots.with_prefixed_debug_names(prefix),
+        }
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
+pub(crate) struct StatePartIndex<K: StatePartKind> {
+    pub(crate) value: u32,
+    pub(crate) _phantom: PhantomData<K>,
+}
+
+impl<K: StatePartKind> fmt::Debug for StatePartIndex<K> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "StatePartIndex<{}>({})", K::NAME, self.value)
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
+pub(crate) struct StatePartLen<K: StatePartKind> {
+    pub(crate) value: u32,
+    pub(crate) _phantom: PhantomData<K>,
+}
+
+impl<K: StatePartKind> StatePartLen<K> {
+    pub(crate) const fn new(value: u32) -> Self {
+        Self {
+            value,
+            _phantom: PhantomData,
+        }
+    }
+}
+
+impl<K: StatePartKind> fmt::Debug for StatePartLen<K> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "StatePartLen<{}>({})", K::NAME, self.value)
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash)]
+pub(crate) struct StatePartLayout<K: StatePartKind, BK: InsnsBuildingKind> {
+    pub(crate) debug_data: BK::Vec<K::DebugData>,
+    pub(crate) _phantom: PhantomData<K>,
+}
+
+impl<K: StatePartKind> Copy for StatePartLayout<K, InsnsBuildingDone> {}
+
+impl<K: StatePartKind, BK: InsnsBuildingKind> StatePartLayout<K, BK> {
+    pub(crate) fn len(&self) -> StatePartLen<K> {
+        StatePartLen::new(
+            self.debug_data
+                .len()
+                .try_into()
+                .expect("state part allocation layout is too big"),
+        )
+    }
+    pub(crate) fn is_empty(&self) -> bool {
+        self.debug_data.is_empty()
+    }
+    pub(crate) fn empty() -> Self {
+        Self {
+            debug_data: Default::default(),
+            _phantom: PhantomData,
+        }
+    }
+}
+
+impl<K: StatePartKind> From<StatePartLayout<K, InsnsBuilding>>
+    for StatePartLayout<K, InsnsBuildingDone>
+{
+    fn from(value: StatePartLayout<K, InsnsBuilding>) -> Self {
+        Self {
+            debug_data: Intern::intern_owned(value.debug_data),
+            _phantom: PhantomData,
+        }
+    }
+}
+
+impl<K: StatePartKind> StatePartLayout<K, InsnsBuilding> {
+    pub(crate) fn scalar(debug_data: K::DebugData) -> Self {
+        Self {
+            debug_data: vec![debug_data],
+            _phantom: PhantomData,
+        }
+    }
+    pub(crate) fn next_index(&self) -> StatePartIndex<K> {
+        StatePartIndex {
+            value: self.len().value,
+            _phantom: PhantomData,
+        }
+    }
+    pub(crate) fn allocate<BK: InsnsBuildingKind>(
+        &mut self,
+        layout: &StatePartLayout<K, BK>,
+    ) -> StatePartIndexRange<K> {
+        let start = self.next_index();
+        let len = layout.len();
+        let Self {
+            debug_data,
+            _phantom: _,
+        } = self;
+        debug_data.extend_from_slice(&layout.debug_data);
+        StatePartIndexRange { start, len }
+    }
+}
+
+impl<K: StatePartKind, BK: InsnsBuildingKind> fmt::Debug for StatePartLayout<K, BK> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            debug_data,
+            _phantom: _,
+        } = self;
+        write!(f, "StatePartAllocationLayout<{}>", K::NAME)?;
+        f.debug_struct("")
+            .field("len", &debug_data.len())
+            .field("debug_data", debug_data)
+            .finish_non_exhaustive()
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+pub(crate) struct StatePartIndexRange<K: StatePartKind> {
+    pub(crate) start: StatePartIndex<K>,
+    pub(crate) len: StatePartLen<K>,
+}
+
+impl<K: StatePartKind> StatePartIndexRange<K> {
+    pub(crate) fn start(self) -> StatePartIndex<K> {
+        self.start
+    }
+    pub(crate) fn end(self) -> StatePartIndex<K> {
+        StatePartIndex {
+            value: self
+                .start
+                .value
+                .checked_add(self.len.value)
+                .expect("state part allocation layout is too big"),
+            _phantom: PhantomData,
+        }
+    }
+    pub(crate) fn len(self) -> StatePartLen<K> {
+        self.len
+    }
+    pub(crate) fn is_empty(self) -> bool {
+        self.len.value == 0
+    }
+    pub(crate) fn slice(self, index: StatePartIndexRange<K>) -> Self {
+        assert!(index.end().value <= self.len.value, "index out of range");
+        Self {
+            start: StatePartIndex {
+                value: self.start.value + index.start.value,
+                _phantom: PhantomData,
+            },
+            len: index.len,
+        }
+    }
+    pub(crate) fn index_array(self, element_size: StatePartLen<K>, index: usize) -> Self {
+        if element_size.value == 0 {
+            assert_eq!(
+                self.len.value, 0,
+                "array with zero-sized element must also be zero-sized",
+            );
+            return self;
+        }
+        assert!(
+            self.len.value % element_size.value == 0,
+            "array's size must be a multiple of its element size",
+        );
+        self.slice(StatePartIndexRange {
+            start: StatePartIndex {
+                value: index
+                    .try_into()
+                    .ok()
+                    .and_then(|index| element_size.value.checked_mul(index))
+                    .expect("index out of range"),
+                _phantom: PhantomData,
+            },
+            len: element_size,
+        })
+    }
+}
+
+impl<K: StatePartKind> fmt::Debug for StatePartIndexRange<K> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(
+            f,
+            "StatePartIndexRange<{}> {{ start: {}, len: {} }}",
+            K::NAME,
+            self.start.value,
+            self.len.value
+        )
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct StatePart<K: StatePartKind> {
+    pub(crate) value: K::State,
+}
+
+impl<K: StatePartKind> StatePart<K> {
+    pub(crate) fn new(len: StatePartLen<K>) -> Self {
+        Self {
+            value: K::new_state(len),
+        }
+    }
+    pub(crate) fn borrow<'a>(&'a mut self) -> BorrowedStatePart<'a, K> {
+        BorrowedStatePart {
+            value: K::borrow_state(&mut self.value),
+        }
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct BorrowedStatePart<'a, K: StatePartKind> {
+    pub(crate) value: K::BorrowedState<'a>,
+}
+
+impl<'a, K: StatePartKind<BorrowedState<'a>: Deref<Target: Index<usize, Output = T>>>, T>
+    Index<StatePartIndex<K>> for BorrowedStatePart<'a, K>
+{
+    type Output = T;
+    fn index(&self, index: StatePartIndex<K>) -> &Self::Output {
+        &self.value[index.value as usize]
+    }
+}
+
+impl<'a, K: StatePartKind<BorrowedState<'a>: DerefMut<Target: IndexMut<usize, Output = T>>>, T>
+    IndexMut<StatePartIndex<K>> for BorrowedStatePart<'a, K>
+{
+    fn index_mut(&mut self, index: StatePartIndex<K>) -> &mut Self::Output {
+        &mut self.value[index.value as usize]
+    }
+}
+
+impl<'a, K: StatePartKind<BorrowedState<'a> = BorrowedStack<'a, T>>, T: 'a>
+    BorrowedStatePart<'a, K>
+{
+    pub(crate) fn push(&mut self, value: T) {
+        self.value.push(value)
+    }
+    pub(crate) fn pop(&mut self) -> T
+    where
+        T: Default,
+    {
+        self.value.pop()
+    }
+}
+
 impl Insns<InsnsBuilding> {
     pub(crate) fn new() -> Self {
         Self {
             insns: Vec::new(),
-            small_stack_size: 0,
-            big_stack_size: 0,
-            small_state_debug_names: Vec::new(),
-            big_state_debug_names: Vec::new(),
             insn_source_locations: Vec::new(),
+            state_layout: StateLayout::empty(),
         }
     }
     pub(crate) fn last_insn_pc(&self) -> usize {
@@ -187,39 +836,27 @@ impl Insns<InsnsBuilding> {
         self.insns.push(insn);
         self.insn_source_locations.push(source_location);
     }
-}
-
-impl From<Insns<InsnsBuilding>> for Insns {
-    fn from(input: Insns<InsnsBuilding>) -> Self {
-        let Insns {
-            insns,
-            small_stack_size,
-            big_stack_size,
-            small_state_debug_names,
-            big_state_debug_names,
-            insn_source_locations,
-        } = input;
-        Insns {
-            insns: Intern::intern_owned(insns),
-            small_stack_size,
-            big_stack_size,
-            small_state_debug_names: Intern::intern_owned(small_state_debug_names),
-            big_state_debug_names: Intern::intern_owned(big_state_debug_names),
-            insn_source_locations: Intern::intern_owned(insn_source_locations),
-        }
+    pub(crate) fn allocate_variable<BK: InsnsBuildingKind>(
+        &mut self,
+        layout: &TypeLayout<BK>,
+    ) -> TypeIndexRange {
+        self.state_layout.ty.allocate(layout)
     }
 }
 
-#[derive(Debug)]
-pub(crate) struct State {
-    pub(crate) insns: Interned<Insns>,
-    pub(crate) pc: usize,
-    pub(crate) small_stack: Box<[SmallUInt]>,
-    pub(crate) small_stack_top: usize,
-    pub(crate) small_states: Box<[SmallUInt]>,
-    pub(crate) big_stack: Box<[BigInt]>,
-    pub(crate) big_stack_top: usize,
-    pub(crate) big_states: Box<[BigInt]>,
+impl From<Insns<InsnsBuilding>> for Insns<InsnsBuildingDone> {
+    fn from(input: Insns<InsnsBuilding>) -> Self {
+        let Insns {
+            insns,
+            insn_source_locations,
+            state_layout,
+        } = input;
+        Insns {
+            insns: Intern::intern_owned(insns),
+            insn_source_locations: Intern::intern_owned(insn_source_locations),
+            state_layout: state_layout.into(),
+        }
+    }
 }
 
 impl State {
@@ -227,235 +864,191 @@ impl State {
         let Self {
             insns: _,
             pc,
-            small_stack: _,
-            small_stack_top,
-            small_states: _,
-            big_stack: _,
-            big_stack_top,
-            big_states: _,
+            small_stack,
+            big_stack,
+            small_slots: _,
+            big_slots: _,
         } = self;
         *pc = entry_pc;
-        *small_stack_top = 0;
-        *big_stack_top = 0;
+        small_stack.value.clear();
+        big_stack.value.clear();
     }
 }
 
 impl_insns! {
-    #[next_macro = next, branch_macro = branch]
-    pub(crate) fn State::run(&mut self, insns: &[Insn]) -> () {
-        #[pc]
-        let mut pc: usize = self.pc;
-        setup! {
-            let small_states = &mut *self.small_states;
-            let small_stack = &mut *self.small_stack;
-            let mut small_stack_top = self.small_stack_top;
-            macro_rules! small_stack_push {
-                ($v:expr) => {
-                    {
-                        small_stack[small_stack_top] = $v;
-                        small_stack_top += 1;
-                    }
-                };
-            }
-            macro_rules! small_stack_pop {
-                () => {
-                    {
-                        small_stack_top -= 1;
-                        small_stack[small_stack_top]
-                    }
-                };
-            }
-            let big_states = &mut *self.big_states;
-            let big_stack = &mut *self.big_stack;
-            let mut big_stack_top = self.big_stack_top;
-            macro_rules! big_stack_push {
-                ($v:expr) => {
-                    {
-                        big_stack[big_stack_top] = $v;
-                        big_stack_top += 1;
-                    }
-                };
-            }
-            macro_rules! big_stack_pop {
-                () => {
-                    {
-                        big_stack_top -= 1;
-                        big_stack[big_stack_top]
-                    }
-                };
-            }
-        }
+    #[insn = Insn, next_macro = next, branch_macro = branch]
+    pub(crate) fn State::run(&mut self) -> () {
+        #[state]
+        let mut state = self.borrow();
+        setup! {}
         main_loop!();
-        cleanup! {
-            self.pc = pc;
-            self.small_stack_top = small_stack_top;
-        }
+        cleanup! {}
     }
     ReadSmall {
-        index: u32,
+        index: StatePartIndex<StatePartKindSmallSlots>,
     } => {
-        small_stack_push!(small_states[index as usize]);
+        state.small_stack.push(state.small_slots[index]);
         next!();
     }
     SExtSmall {
         /// number of bits in a [`SmallSInt`] that aren't used
         unused_bit_count: u8,
     } => {
-        let mut value = small_stack_pop!() as SmallSInt;
+        let mut value = state.small_stack.pop() as SmallSInt;
         value <<= unused_bit_count;
         value >>= unused_bit_count;
-        small_stack_push!(value as SmallUInt);
+        state.small_stack.push(value as SmallUInt);
         next!();
     }
     ZExtSmall {
         /// number of bits in a [`SmallUInt`] that aren't used
         unused_bit_count: u8,
     } => {
-        let mut value = small_stack_pop!();
+        let mut value = state.small_stack.pop();
         value <<= unused_bit_count;
         value >>= unused_bit_count;
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     AndSmall => {
-        let rhs = small_stack_pop!();
-        let lhs = small_stack_pop!();
+        let rhs = state.small_stack.pop();
+        let lhs = state.small_stack.pop();
         let value = lhs & rhs;
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     OrSmall => {
-        let rhs = small_stack_pop!();
-        let lhs = small_stack_pop!();
+        let rhs = state.small_stack.pop();
+        let lhs = state.small_stack.pop();
         let value = lhs | rhs;
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     XorSmall => {
-        let rhs = small_stack_pop!();
-        let lhs = small_stack_pop!();
+        let rhs = state.small_stack.pop();
+        let lhs = state.small_stack.pop();
         let value = lhs ^ rhs;
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     NotSmall => {
-        let value = small_stack_pop!();
-        small_stack_push!(!value);
+        let value = state.small_stack.pop();
+        state.small_stack.push(!value);
         next!();
     }
     CmpEqSmall => {
-        let rhs = small_stack_pop!();
-        let lhs = small_stack_pop!();
+        let rhs = state.small_stack.pop();
+        let lhs = state.small_stack.pop();
         let value = (lhs == rhs) as SmallUInt;
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     CmpNeSmall => {
-        let rhs = small_stack_pop!();
-        let lhs = small_stack_pop!();
+        let rhs = state.small_stack.pop();
+        let lhs = state.small_stack.pop();
         let value = (lhs != rhs) as SmallUInt;
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     CmpLTSmallUInt => {
-        let rhs = small_stack_pop!();
-        let lhs = small_stack_pop!();
+        let rhs = state.small_stack.pop();
+        let lhs = state.small_stack.pop();
         let value = (lhs < rhs) as SmallUInt;
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     CmpLESmallUInt => {
-        let rhs = small_stack_pop!();
-        let lhs = small_stack_pop!();
+        let rhs = state.small_stack.pop();
+        let lhs = state.small_stack.pop();
         let value = (lhs <= rhs) as SmallUInt;
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     CmpGTSmallUInt => {
-        let rhs = small_stack_pop!();
-        let lhs = small_stack_pop!();
+        let rhs = state.small_stack.pop();
+        let lhs = state.small_stack.pop();
         let value = (lhs > rhs) as SmallUInt;
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     CmpGESmallUInt => {
-        let rhs = small_stack_pop!();
-        let lhs = small_stack_pop!();
+        let rhs = state.small_stack.pop();
+        let lhs = state.small_stack.pop();
         let value = (lhs >= rhs) as SmallUInt;
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     CmpLTSmallSInt => {
-        let rhs = small_stack_pop!() as SmallSInt;
-        let lhs = small_stack_pop!() as SmallSInt;
+        let rhs = state.small_stack.pop() as SmallSInt;
+        let lhs = state.small_stack.pop() as SmallSInt;
         let value = (lhs < rhs) as SmallUInt;
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     CmpLESmallSInt => {
-        let rhs = small_stack_pop!() as SmallSInt;
-        let lhs = small_stack_pop!() as SmallSInt;
+        let rhs = state.small_stack.pop() as SmallSInt;
+        let lhs = state.small_stack.pop() as SmallSInt;
         let value = (lhs <= rhs) as SmallUInt;
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     CmpGTSmallSInt => {
-        let rhs = small_stack_pop!() as SmallSInt;
-        let lhs = small_stack_pop!() as SmallSInt;
+        let rhs = state.small_stack.pop() as SmallSInt;
+        let lhs = state.small_stack.pop() as SmallSInt;
         let value = (lhs > rhs) as SmallUInt;
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     CmpGESmallSInt => {
-        let rhs = small_stack_pop!() as SmallSInt;
-        let lhs = small_stack_pop!() as SmallSInt;
+        let rhs = state.small_stack.pop() as SmallSInt;
+        let lhs = state.small_stack.pop() as SmallSInt;
         let value = (lhs >= rhs) as SmallUInt;
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     AddSmall => {
-        let rhs = small_stack_pop!();
-        let lhs = small_stack_pop!();
+        let rhs = state.small_stack.pop();
+        let lhs = state.small_stack.pop();
         let value = lhs.wrapping_add(rhs);
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     SubSmall => {
-        let rhs = small_stack_pop!();
-        let lhs = small_stack_pop!();
+        let rhs = state.small_stack.pop();
+        let lhs = state.small_stack.pop();
         let value = lhs.wrapping_sub(rhs);
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     NegSmall => {
-        let value = small_stack_pop!();
+        let value = state.small_stack.pop();
         let value = value.wrapping_neg();
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     MulSmall => {
-        let rhs = small_stack_pop!();
-        let lhs = small_stack_pop!();
+        let rhs = state.small_stack.pop();
+        let lhs = state.small_stack.pop();
         let value = lhs.wrapping_mul(rhs);
-        small_stack_push!(value);
+        state.small_stack.push(value);
         next!();
     }
     ConstU32Small {
         value: u32,
     } => {
-        small_stack_push!(value as SmallUInt);
+        state.small_stack.push(value as SmallUInt);
         next!();
     }
     ConstS32Small {
         value: i32,
     } => {
-        small_stack_push!(value as SmallUInt);
+        state.small_stack.push(value as SmallUInt);
         next!();
     }
     WriteSmall {
-        index: u32,
+        index: StatePartIndex<StatePartKindSmallSlots>,
     } => {
-        small_states[index as usize] = small_stack_pop!();
+        state.small_slots[index] = state.small_stack.pop();
         next!();
     }
     Return => {

From b288d6f8f20d7bceee96375cb91ed8be336ee28b Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 7 Nov 2024 21:50:31 -0800
Subject: [PATCH 082/190] add missing copyright headers

---
 crates/fayalite/src/sim.rs             | 3 +++
 crates/fayalite/src/sim/interpreter.rs | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 3b55379..6114044 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -1,3 +1,6 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
 //! Fayalite Simulation
 
 use crate::{
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index 06d0025..f327510 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -1,3 +1,6 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
 use crate::{
     intern::{Intern, Interned},
     source_location::SourceLocation,

From 277d3e0d4d37a36eaba12fe684225dae38b0163d Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 10 Nov 2024 22:12:57 -0800
Subject: [PATCH 083/190] working on simulator

---
 Cargo.lock                             |   7 +
 Cargo.toml                             |   1 +
 crates/fayalite/Cargo.toml             |   1 +
 crates/fayalite/src/sim.rs             | 709 +++++++++++++++++++++++--
 crates/fayalite/src/sim/interpreter.rs | 665 +++++++++++++++++------
 crates/fayalite/src/util.rs            |   3 +-
 crates/fayalite/src/util/misc.rs       |  16 +
 7 files changed, 1212 insertions(+), 190 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 500bd34..2fca6fc 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -319,6 +319,7 @@ dependencies = [
  "serde_json",
  "tempfile",
  "trybuild",
+ "vec_map",
  "which",
 ]
 
@@ -720,6 +721,12 @@ version = "0.2.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "06abde3611657adf66d383f00b093d7faecc7fa57071cce2578660c9f1010821"
 
+[[package]]
+name = "vec_map"
+version = "0.8.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f1bddf1187be692e79c5ffeab891132dfb0f236ed36a43c7ed39f1165ee20191"
+
 [[package]]
 name = "version_check"
 version = "0.9.4"
diff --git a/Cargo.toml b/Cargo.toml
index b6b8616..44f5c5a 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -39,4 +39,5 @@ syn = { version = "2.0.66", features = ["full", "fold", "visit", "extra-traits"]
 tempfile = "3.10.1"
 thiserror = "1.0.61"
 trybuild = "1.0"
+vec_map = "0.8.2"
 which = "6.0.1"
diff --git a/crates/fayalite/Cargo.toml b/crates/fayalite/Cargo.toml
index 5724a80..8e90a74 100644
--- a/crates/fayalite/Cargo.toml
+++ b/crates/fayalite/Cargo.toml
@@ -28,6 +28,7 @@ os_pipe.workspace = true
 serde_json.workspace = true
 serde.workspace = true
 tempfile.workspace = true
+vec_map.workspace = true
 which.workspace = true
 
 [dev-dependencies]
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 6114044..9b40458 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -4,29 +4,28 @@
 //! Fayalite Simulation
 
 use crate::{
-    bundle::{Bundle, BundleField, BundleType},
-    enum_::Enum,
+    bundle::{BundleField, BundleType},
     expr::{
         target::{
             Target, TargetBase, TargetPathArrayElement, TargetPathBundleField, TargetPathElement,
         },
-        Expr,
+        ExprEnum,
     },
-    int::Bool,
     intern::{Intern, Interned, Memoize},
     module::{
-        AnnotatedModuleIO, Block, Instance, Module, ModuleBody, NormalModuleBody, Stmt,
-        StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch,
+        AnnotatedModuleIO, Block, ModuleBody, NormalModuleBody, Stmt, StmtConnect, StmtDeclaration,
+        StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire,
     },
+    prelude::*,
     sim::interpreter::{
-        Insn, Insns, InsnsBuilding, InsnsBuildingDone, SlotDebugData, StatePartLayout, TypeIndex,
-        TypeIndexRange, TypeLayout,
+        Insn, Insns, InsnsBuilding, InsnsBuildingDone, SlotDebugData, SmallUInt, StatePartIndex,
+        StatePartIndexMap, StatePartKind, StatePartKindBigSlots, StatePartKindSmallSlots,
+        StatePartLayout, StatePartLen, StatePartsValue, TypeIndex, TypeIndexRange, TypeLayout,
+        TypeLen, TypeParts, MIN_BITS_FOR_NEEDING_BIG,
     },
-    source_location::SourceLocation,
-    ty::CanonicalType,
 };
 use hashbrown::HashMap;
-use std::fmt;
+use std::{fmt, marker::PhantomData, mem};
 
 mod interpreter;
 
@@ -35,17 +34,17 @@ enum CondStack {
     Always,
     IfTrue {
         parent: Interned<CondStack>,
-        cond: Expr<Bool>,
+        cond: CompiledExpr<Bool>,
         source_location: SourceLocation,
     },
     IfFalse {
         parent: Interned<CondStack>,
-        cond: Expr<Bool>,
+        cond: CompiledExpr<Bool>,
         source_location: SourceLocation,
     },
     MatchArm {
         parent: Interned<CondStack>,
-        enum_expr: Expr<Enum>,
+        enum_expr: CompiledExpr<Enum>,
         variant_index: usize,
         source_location: SourceLocation,
     },
@@ -95,7 +94,7 @@ struct TargetInInstantiatedModule {
 #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
 struct CompiledBundleField {
     offset: TypeIndex,
-    ty: CompiledTypeLayout,
+    ty: CompiledTypeLayout<CanonicalType>,
 }
 
 #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
@@ -103,7 +102,7 @@ enum CompiledTypeLayoutBody {
     Scalar,
     Array {
         /// debug names are ignored, use parent's layout instead
-        element: Interned<CompiledTypeLayout>,
+        element: Interned<CompiledTypeLayout<CanonicalType>>,
     },
     Bundle {
         /// debug names are ignored, use parent's layout instead
@@ -112,13 +111,13 @@ enum CompiledTypeLayoutBody {
 }
 
 #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
-struct CompiledTypeLayout {
-    ty: CanonicalType,
+struct CompiledTypeLayout<T: Type> {
+    ty: T,
     layout: TypeLayout<InsnsBuildingDone>,
     body: CompiledTypeLayoutBody,
 }
 
-impl CompiledTypeLayout {
+impl<T: Type> CompiledTypeLayout<T> {
     fn with_prefixed_debug_names(self, prefix: &str) -> Self {
         let Self { ty, layout, body } = self;
         Self {
@@ -127,13 +126,13 @@ impl CompiledTypeLayout {
             body,
         }
     }
-    fn get(ty: CanonicalType) -> Self {
+    fn get(ty: T) -> Self {
         #[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)]
         struct MyMemoize;
         impl Memoize for MyMemoize {
             type Input = CanonicalType;
             type InputOwned = CanonicalType;
-            type Output = CompiledTypeLayout;
+            type Output = CompiledTypeLayout<CanonicalType>;
 
             fn inner(self, input: &Self::Input) -> Self::Output {
                 match input {
@@ -146,8 +145,10 @@ impl CompiledTypeLayout {
                     | CanonicalType::Reset(_)
                     | CanonicalType::Clock(_) => {
                         let mut layout = TypeLayout::empty();
-                        let debug_data = SlotDebugData { name: "".intern() };
-                        if input.bit_width() > interpreter::SmallUInt::BITS as usize {
+                        let debug_data = SlotDebugData {
+                            name: Interned::default(),
+                        };
+                        if input.bit_width() >= interpreter::MIN_BITS_FOR_NEEDING_BIG {
                             layout.big_slots = StatePartLayout::scalar(debug_data);
                         } else {
                             layout.small_slots = StatePartLayout::scalar(debug_data);
@@ -205,24 +206,32 @@ impl CompiledTypeLayout {
                 }
             }
         }
-        MyMemoize.get_owned(ty)
+        let CompiledTypeLayout {
+            ty: _,
+            layout,
+            body,
+        } = MyMemoize.get_owned(ty.canonical());
+        Self { ty, layout, body }
     }
 }
 
 #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
-struct CompiledValue {
-    layout: CompiledTypeLayout,
+struct CompiledValue<T: Type> {
+    layout: CompiledTypeLayout<T>,
     range: TypeIndexRange,
-    write: Option<(CompiledTypeLayout, TypeIndexRange)>,
+    write: Option<(CompiledTypeLayout<T>, TypeIndexRange)>,
 }
 
-impl CompiledValue {
-    fn map(
+impl<T: Type> CompiledValue<T> {
+    fn map<U: Type>(
         self,
-        mut f: impl FnMut(CompiledTypeLayout, TypeIndexRange) -> (CompiledTypeLayout, TypeIndexRange),
-    ) -> Self {
+        mut f: impl FnMut(
+            CompiledTypeLayout<T>,
+            TypeIndexRange,
+        ) -> (CompiledTypeLayout<U>, TypeIndexRange),
+    ) -> CompiledValue<U> {
         let (layout, range) = f(self.layout, self.range);
-        Self {
+        CompiledValue {
             layout,
             range,
             write: self.write.map(|(layout, range)| f(layout, range)),
@@ -230,12 +239,98 @@ impl CompiledValue {
     }
 }
 
+#[derive(Debug, PartialEq, Eq, Hash, Copy, Clone)]
+struct CompiledExprDynIndex {
+    index_slot: StatePartIndex<StatePartKindSmallSlots>,
+    len: TypeLen,
+    stride: TypeLen,
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Copy, Clone)]
+struct CompiledExpr<T: Type> {
+    static_part: CompiledValue<T>,
+    dyn_indexes: Interned<[CompiledExprDynIndex]>,
+}
+
+impl<T: Type> From<CompiledValue<T>> for CompiledExpr<T> {
+    fn from(static_part: CompiledValue<T>) -> Self {
+        Self {
+            static_part,
+            dyn_indexes: Interned::default(),
+        }
+    }
+}
+
+impl<T: Type> CompiledExpr<T> {
+    fn map_ty<U: Type>(self, mut f: impl FnMut(T) -> U) -> CompiledExpr<U> {
+        let Self {
+            static_part,
+            dyn_indexes,
+        } = self;
+        CompiledExpr {
+            static_part: static_part.map(|CompiledTypeLayout { ty, layout, body }, range| {
+                (
+                    CompiledTypeLayout {
+                        ty: f(ty),
+                        layout,
+                        body,
+                    },
+                    range,
+                )
+            }),
+            dyn_indexes,
+        }
+    }
+}
+
+#[derive(Clone, Debug, Default, PartialEq, Eq, Hash)]
+struct SlotSet(TypeParts<Self>);
+
+impl SlotSet {
+    fn is_empty(&self) -> bool {
+        let Self(TypeParts {
+            small_slots,
+            big_slots,
+        }) = self;
+        small_slots.is_empty() && big_slots.is_empty()
+    }
+}
+
+impl StatePartsValue for SlotSet {
+    type Value<K: StatePartKind> = Vec<StatePartIndex<K>>;
+}
+
+#[derive(Debug)]
+struct Assignment {
+    inputs: SlotSet,
+    insns: Vec<Insn>,
+}
+
+#[derive(Debug, Default)]
+struct StatePartAssignments<K: StatePartKind> {
+    written_slot_to_assignment_indexes_map: StatePartIndexMap<K, Vec<usize>>,
+}
+
+#[derive(Debug, Default)]
+struct SlotAssignments {
+    assignments: Vec<Assignment>,
+    parts: TypeParts<Self>,
+}
+
+impl StatePartsValue for SlotAssignments {
+    type Value<K: StatePartKind> = StatePartAssignments<K>;
+}
+
 #[derive(Debug)]
 pub struct Compiler {
     insns: Insns<InsnsBuilding>,
     base_module: Interned<Module<Bundle>>,
     modules: HashMap<InstantiatedModule, CompiledModule>,
-    compiled_values: HashMap<TargetInInstantiatedModule, CompiledValue>,
+    compiled_values: HashMap<TargetInInstantiatedModule, CompiledValue<CanonicalType>>,
+    compiled_exprs: HashMap<Expr<CanonicalType>, CompiledExpr<CanonicalType>>,
+    compiled_exprs_to_values: HashMap<CompiledExpr<CanonicalType>, CompiledValue<CanonicalType>>,
+    expanded_to_big: HashMap<Expr<CanonicalType>, CompiledValue<CanonicalType>>,
+    slots_assignments: SlotAssignments,
 }
 
 impl Compiler {
@@ -245,13 +340,20 @@ impl Compiler {
             base_module,
             modules: HashMap::new(),
             compiled_values: HashMap::new(),
+            compiled_exprs: HashMap::new(),
+            compiled_exprs_to_values: HashMap::new(),
+            expanded_to_big: HashMap::new(),
+            slots_assignments: SlotAssignments::default(),
         }
     }
-    fn compile_value(&mut self, target: TargetInInstantiatedModule) -> CompiledValue {
+    fn compile_value(
+        &mut self,
+        target: TargetInInstantiatedModule,
+    ) -> CompiledValue<CanonicalType> {
         if let Some(&retval) = self.compiled_values.get(&target) {
             return retval;
         }
-        match target.target {
+        let retval = match target.target {
             Target::Base(base) => {
                 let unprefixed_layout = CompiledTypeLayout::get(base.canonical_ty());
                 let layout = unprefixed_layout.with_prefixed_debug_names(&format!(
@@ -319,7 +421,494 @@ impl Compiler {
                     TargetPathElement::DynArrayElement(_) => unreachable!(),
                 }
             }
+        };
+        self.compiled_values.insert(target, retval);
+        retval
+    }
+    fn compiled_expr_to_value(
+        &mut self,
+        expr: CompiledExpr<CanonicalType>,
+    ) -> CompiledValue<CanonicalType> {
+        if let Some(&retval) = self.compiled_exprs_to_values.get(&expr) {
+            return retval;
         }
+        let CompiledExpr {
+            static_part: mut retval,
+            dyn_indexes,
+        } = expr;
+        for CompiledExprDynIndex {
+            index_slot,
+            len,
+            stride,
+        } in dyn_indexes
+        {
+            todo!();
+        }
+        self.compiled_exprs_to_values.insert(expr, retval);
+        retval
+    }
+    fn simple_nary_expr<const N: usize>(
+        &mut self,
+        dest_ty: CanonicalType,
+        inputs: [Expr<CanonicalType>; N],
+        make_insns: impl FnOnce(
+            &mut Self,
+            CompiledValue<CanonicalType>,
+            &mut [CompiledValue<CanonicalType>; N],
+        ) -> Vec<Insn>,
+    ) -> CompiledValue<CanonicalType> {
+        let mut inputs = inputs.map(|input| {
+            let input = self.compile_expr(input);
+            self.compiled_expr_to_value(input)
+        });
+        let layout = CompiledTypeLayout::get(dest_ty);
+        let range = self.insns.allocate_variable(&layout.layout);
+        let retval = CompiledValue {
+            layout,
+            range,
+            write: None,
+        };
+        let insns = make_insns(self, retval, &mut inputs);
+        let mut inputs_set = SlotSet::default();
+        for input in inputs {
+            let TypeIndexRange {
+                small_slots,
+                big_slots,
+            } = input.range;
+            inputs_set.0.small_slots.extend(small_slots.iter());
+            inputs_set.0.big_slots.extend(big_slots.iter());
+        }
+        let assignment_index = self.slots_assignments.assignments.len();
+        self.slots_assignments.assignments.push(Assignment {
+            inputs: inputs_set,
+            insns,
+        });
+        let TypeIndexRange {
+            small_slots,
+            big_slots,
+        } = range;
+        for i in small_slots.iter() {
+            self.slots_assignments
+                .parts
+                .small_slots
+                .written_slot_to_assignment_indexes_map
+                .entry(i)
+                .or_insert_with(Vec::new)
+                .push(assignment_index);
+        }
+        for i in big_slots.iter() {
+            self.slots_assignments
+                .parts
+                .big_slots
+                .written_slot_to_assignment_indexes_map
+                .entry(i)
+                .or_insert_with(Vec::new)
+                .push(assignment_index);
+        }
+        retval
+    }
+    fn expand_to_big(&mut self, expr: Expr<CanonicalType>) -> CompiledValue<CanonicalType> {
+        if let Some(&retval) = self.expanded_to_big.get(&expr) {
+            return retval;
+        }
+        let input = self.compile_expr(expr);
+        let input = self.compiled_expr_to_value(input);
+        let retval = match input.range.len() {
+            TypeLen {
+                small_slots:
+                    StatePartLen {
+                        value: 0,
+                        _phantom: _,
+                    },
+                big_slots: _,
+            } => input,
+            len => {
+                assert_eq!(
+                    Some(StatePartLen {
+                        value: 1,
+                        _phantom: PhantomData,
+                    }),
+                    len.only_small()
+                );
+                let signed = match Expr::ty(expr) {
+                    CanonicalType::UInt(_) => false,
+                    CanonicalType::SInt(_) => true,
+                    CanonicalType::Bool(_) => false,
+                    CanonicalType::Enum(_) => false,
+                    CanonicalType::Array(_) => unreachable!(),
+                    CanonicalType::Bundle(_) => unreachable!(),
+                    CanonicalType::AsyncReset(_) => false,
+                    CanonicalType::SyncReset(_) => false,
+                    CanonicalType::Reset(_) => false,
+                    CanonicalType::Clock(_) => false,
+                };
+                self.simple_nary_expr(
+                    if signed {
+                        SInt::new_dyn(MIN_BITS_FOR_NEEDING_BIG).canonical()
+                    } else {
+                        UInt::new_dyn(MIN_BITS_FOR_NEEDING_BIG).canonical()
+                    },
+                    [expr],
+                    |_this, dest, [input]| {
+                        let dest = dest.range.big_slots.start;
+                        let src = input.range.small_slots.start;
+                        let unused_bit_count =
+                            interpreter::SmallUInt::BITS as u8 - Expr::ty(expr).bit_width() as u8;
+                        if signed {
+                            vec![Insn::SExtSmallToBig {
+                                dest,
+                                src,
+                                unused_bit_count,
+                            }]
+                        } else {
+                            vec![Insn::ZExtSmallToBig {
+                                dest,
+                                src,
+                                unused_bit_count,
+                            }]
+                        }
+                    },
+                )
+            }
+        };
+        self.expanded_to_big.insert(expr, retval);
+        retval
+    }
+    fn simple_nary_small_or_big_expr<const N: usize>(
+        &mut self,
+        dest_ty: CanonicalType,
+        inputs: [Expr<CanonicalType>; N],
+        make_insns_small: impl FnOnce(
+            StatePartIndex<StatePartKindSmallSlots>,
+            [StatePartIndex<StatePartKindSmallSlots>; N],
+        ) -> Vec<Insn>,
+        make_insns_big: impl FnOnce(
+            StatePartIndex<StatePartKindBigSlots>,
+            [StatePartIndex<StatePartKindBigSlots>; N],
+        ) -> Vec<Insn>,
+        make_insns_big_to_small: impl FnOnce(
+            StatePartIndex<StatePartKindSmallSlots>,
+            [StatePartIndex<StatePartKindBigSlots>; N],
+        ) -> Vec<Insn>,
+    ) -> CompiledValue<CanonicalType> {
+        self.simple_nary_expr(dest_ty, inputs, |this, dest, compiled_inputs| {
+            let all_inputs_only_small = compiled_inputs
+                .iter()
+                .all(|input| input.range.len().only_small().is_some());
+            if all_inputs_only_small {
+                if dest.range.len().only_small().is_some() {
+                    // all small
+                    assert_eq!(dest.range.len().small_slots.value, 1);
+                    return make_insns_small(
+                        dest.range.small_slots.start,
+                        compiled_inputs.map(
+                            |CompiledValue {
+                                 layout,
+                                 range,
+                                 write: _,
+                             }| {
+                                assert_eq!(range.small_slots.len().value, 1);
+                                range.small_slots.start
+                            },
+                        ),
+                    );
+                } else {
+                    // inputs small, dest big -- expand inputs to big
+                    for (&input, compiled_input) in inputs.iter().zip(&mut *compiled_inputs) {
+                        *compiled_input = this.expand_to_big(input);
+                    }
+                }
+            }
+            let big_inputs = compiled_inputs.map(
+                |CompiledValue {
+                     layout,
+                     range:
+                         TypeIndexRange {
+                             small_slots,
+                             big_slots,
+                         },
+                     write: _,
+                 }| {
+                    assert_eq!(small_slots.len().value, 0);
+                    assert_eq!(big_slots.len().value, 1);
+                    big_slots.start
+                },
+            );
+            if dest.range.len().only_small().is_some() {
+                // inputs big, dest small
+                assert_eq!(dest.range.len().small_slots.value, 1);
+                return make_insns_big_to_small(dest.range.small_slots.start, big_inputs);
+            }
+            let TypeIndexRange {
+                small_slots,
+                big_slots,
+            } = dest.range;
+            assert_eq!(small_slots.len().value, 0);
+            assert_eq!(big_slots.len().value, 1);
+            make_insns_big(big_slots.start, big_inputs)
+        })
+    }
+    fn compile_expr(&mut self, expr: Expr<CanonicalType>) -> CompiledExpr<CanonicalType> {
+        if let Some(&retval) = self.compiled_exprs.get(&expr) {
+            return retval;
+        }
+        let retval: CompiledExpr<_> = match *Expr::expr_enum(expr) {
+            ExprEnum::UIntLiteral(expr) => self
+                .simple_nary_small_or_big_expr(
+                    Bool.canonical(),
+                    [],
+                    |dest, []| {
+                        vec![Insn::ConstSmall {
+                            dest,
+                            value: expr.to_bigint().try_into().expect("const too big"),
+                        }]
+                    },
+                    |dest, []| {
+                        vec![Insn::ConstBig {
+                            dest,
+                            value: expr.to_bigint().intern_sized(),
+                        }]
+                    },
+                    |_, _| unreachable!(),
+                )
+                .into(),
+            ExprEnum::SIntLiteral(expr) => self
+                .simple_nary_small_or_big_expr(
+                    Bool.canonical(),
+                    [],
+                    |dest, []| {
+                        vec![Insn::ConstSmall {
+                            dest,
+                            value: expr.to_bigint().try_into().expect("const too big"),
+                        }]
+                    },
+                    |dest, []| {
+                        vec![Insn::ConstBig {
+                            dest,
+                            value: expr.to_bigint().intern_sized(),
+                        }]
+                    },
+                    |_, _| unreachable!(),
+                )
+                .into(),
+            ExprEnum::BoolLiteral(expr) => self
+                .simple_nary_small_or_big_expr(
+                    Bool.canonical(),
+                    [],
+                    |dest, []| {
+                        vec![Insn::ConstSmall {
+                            dest,
+                            value: expr as SmallUInt,
+                        }]
+                    },
+                    |_, _| unreachable!(),
+                    |_, _| unreachable!(),
+                )
+                .into(),
+            ExprEnum::BundleLiteral(expr) => todo!(),
+            ExprEnum::ArrayLiteral(expr) => todo!(),
+            ExprEnum::EnumLiteral(expr) => todo!(),
+            ExprEnum::Uninit(expr) => todo!(),
+            ExprEnum::NotU(expr) => todo!(),
+            ExprEnum::NotS(expr) => todo!(),
+            ExprEnum::NotB(expr) => todo!(),
+            ExprEnum::Neg(expr) => self
+                .simple_nary_small_or_big_expr(
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| vec![Insn::NegSmall { dest, src }],
+                    |dest, [src]| vec![Insn::NegBig { dest, src }],
+                    |_, _| unreachable!(),
+                )
+                .into(),
+            ExprEnum::BitAndU(expr) => todo!(),
+            ExprEnum::BitAndS(expr) => todo!(),
+            ExprEnum::BitAndB(expr) => todo!(),
+            ExprEnum::BitOrU(expr) => todo!(),
+            ExprEnum::BitOrS(expr) => todo!(),
+            ExprEnum::BitOrB(expr) => todo!(),
+            ExprEnum::BitXorU(expr) => todo!(),
+            ExprEnum::BitXorS(expr) => todo!(),
+            ExprEnum::BitXorB(expr) => todo!(),
+            ExprEnum::AddU(expr) => todo!(),
+            ExprEnum::AddS(expr) => todo!(),
+            ExprEnum::SubU(expr) => todo!(),
+            ExprEnum::SubS(expr) => todo!(),
+            ExprEnum::MulU(expr) => todo!(),
+            ExprEnum::MulS(expr) => todo!(),
+            ExprEnum::DivU(expr) => todo!(),
+            ExprEnum::DivS(expr) => todo!(),
+            ExprEnum::RemU(expr) => todo!(),
+            ExprEnum::RemS(expr) => todo!(),
+            ExprEnum::DynShlU(expr) => todo!(),
+            ExprEnum::DynShlS(expr) => todo!(),
+            ExprEnum::DynShrU(expr) => todo!(),
+            ExprEnum::DynShrS(expr) => todo!(),
+            ExprEnum::FixedShlU(expr) => todo!(),
+            ExprEnum::FixedShlS(expr) => todo!(),
+            ExprEnum::FixedShrU(expr) => todo!(),
+            ExprEnum::FixedShrS(expr) => todo!(),
+            ExprEnum::CmpLtB(expr) => todo!(),
+            ExprEnum::CmpLeB(expr) => todo!(),
+            ExprEnum::CmpGtB(expr) => todo!(),
+            ExprEnum::CmpGeB(expr) => todo!(),
+            ExprEnum::CmpEqB(expr) => todo!(),
+            ExprEnum::CmpNeB(expr) => todo!(),
+            ExprEnum::CmpLtU(expr) => todo!(),
+            ExprEnum::CmpLeU(expr) => todo!(),
+            ExprEnum::CmpGtU(expr) => todo!(),
+            ExprEnum::CmpGeU(expr) => todo!(),
+            ExprEnum::CmpEqU(expr) => todo!(),
+            ExprEnum::CmpNeU(expr) => todo!(),
+            ExprEnum::CmpLtS(expr) => todo!(),
+            ExprEnum::CmpLeS(expr) => todo!(),
+            ExprEnum::CmpGtS(expr) => todo!(),
+            ExprEnum::CmpGeS(expr) => todo!(),
+            ExprEnum::CmpEqS(expr) => todo!(),
+            ExprEnum::CmpNeS(expr) => todo!(),
+            ExprEnum::CastUIntToUInt(expr) => todo!(),
+            ExprEnum::CastUIntToSInt(expr) => todo!(),
+            ExprEnum::CastSIntToUInt(expr) => todo!(),
+            ExprEnum::CastSIntToSInt(expr) => todo!(),
+            ExprEnum::CastBoolToUInt(expr) => todo!(),
+            ExprEnum::CastBoolToSInt(expr) => todo!(),
+            ExprEnum::CastUIntToBool(expr) => todo!(),
+            ExprEnum::CastSIntToBool(expr) => todo!(),
+            ExprEnum::CastBoolToSyncReset(expr) => todo!(),
+            ExprEnum::CastUIntToSyncReset(expr) => todo!(),
+            ExprEnum::CastSIntToSyncReset(expr) => todo!(),
+            ExprEnum::CastBoolToAsyncReset(expr) => todo!(),
+            ExprEnum::CastUIntToAsyncReset(expr) => todo!(),
+            ExprEnum::CastSIntToAsyncReset(expr) => todo!(),
+            ExprEnum::CastSyncResetToBool(expr) => todo!(),
+            ExprEnum::CastSyncResetToUInt(expr) => todo!(),
+            ExprEnum::CastSyncResetToSInt(expr) => todo!(),
+            ExprEnum::CastSyncResetToReset(expr) => todo!(),
+            ExprEnum::CastAsyncResetToBool(expr) => todo!(),
+            ExprEnum::CastAsyncResetToUInt(expr) => todo!(),
+            ExprEnum::CastAsyncResetToSInt(expr) => todo!(),
+            ExprEnum::CastAsyncResetToReset(expr) => todo!(),
+            ExprEnum::CastResetToBool(expr) => todo!(),
+            ExprEnum::CastResetToUInt(expr) => todo!(),
+            ExprEnum::CastResetToSInt(expr) => todo!(),
+            ExprEnum::CastBoolToClock(expr) => todo!(),
+            ExprEnum::CastUIntToClock(expr) => todo!(),
+            ExprEnum::CastSIntToClock(expr) => todo!(),
+            ExprEnum::CastClockToBool(expr) => todo!(),
+            ExprEnum::CastClockToUInt(expr) => todo!(),
+            ExprEnum::CastClockToSInt(expr) => todo!(),
+            ExprEnum::FieldAccess(expr) => todo!(),
+            ExprEnum::VariantAccess(expr) => todo!(),
+            ExprEnum::ArrayIndex(expr) => todo!(),
+            ExprEnum::DynArrayIndex(expr) => todo!(),
+            ExprEnum::ReduceBitAndU(expr) => todo!(),
+            ExprEnum::ReduceBitAndS(expr) => todo!(),
+            ExprEnum::ReduceBitOrU(expr) => todo!(),
+            ExprEnum::ReduceBitOrS(expr) => todo!(),
+            ExprEnum::ReduceBitXorU(expr) => todo!(),
+            ExprEnum::ReduceBitXorS(expr) => todo!(),
+            ExprEnum::SliceUInt(expr) => todo!(),
+            ExprEnum::SliceSInt(expr) => todo!(),
+            ExprEnum::CastToBits(expr) => todo!(),
+            ExprEnum::CastBitsTo(expr) => todo!(),
+            ExprEnum::ModuleIO(expr) => todo!(),
+            ExprEnum::Instance(expr) => todo!(),
+            ExprEnum::Wire(expr) => todo!(),
+            ExprEnum::Reg(expr) => todo!(),
+            ExprEnum::MemPort(expr) => todo!(),
+        };
+        self.compiled_exprs.insert(expr, retval);
+        retval
+    }
+    fn compile_connect(
+        &mut self,
+        parent_module: Interned<InstantiatedModule>,
+        cond_stack: Interned<CondStack>,
+        lhs: Expr<CanonicalType>,
+        mut rhs: Expr<CanonicalType>,
+        source_location: SourceLocation,
+    ) {
+        if Expr::ty(lhs) != Expr::ty(rhs) || !Expr::ty(lhs).is_passive() {
+            match Expr::ty(lhs) {
+                CanonicalType::UInt(lhs_ty) => {
+                    rhs = Expr::canonical(Expr::<UInt>::from_canonical(rhs).cast_to(lhs_ty));
+                }
+                CanonicalType::SInt(lhs_ty) => {
+                    rhs = Expr::canonical(Expr::<SInt>::from_canonical(rhs).cast_to(lhs_ty));
+                }
+                CanonicalType::Bool(_) => unreachable!(),
+                CanonicalType::Array(lhs_ty) => {
+                    let CanonicalType::Array(rhs_ty) = Expr::ty(rhs) else {
+                        unreachable!();
+                    };
+                    assert_eq!(lhs_ty.len(), rhs_ty.len());
+                    let lhs = Expr::<Array>::from_canonical(lhs);
+                    let rhs = Expr::<Array>::from_canonical(rhs);
+                    for index in 0..lhs_ty.len() {
+                        self.compile_connect(
+                            parent_module,
+                            cond_stack,
+                            lhs[index],
+                            rhs[index],
+                            source_location,
+                        );
+                    }
+                    return;
+                }
+                CanonicalType::Enum(lhs_ty) => {
+                    let CanonicalType::Enum(rhs_ty) = Expr::ty(rhs) else {
+                        unreachable!();
+                    };
+                    todo!("handle connect with different enum types");
+                }
+                CanonicalType::Bundle(lhs_ty) => {
+                    let CanonicalType::Bundle(rhs_ty) = Expr::ty(rhs) else {
+                        unreachable!();
+                    };
+                    assert_eq!(lhs_ty.fields().len(), rhs_ty.fields().len());
+                    let lhs = Expr::<Bundle>::from_canonical(lhs);
+                    let rhs = Expr::<Bundle>::from_canonical(rhs);
+                    for (
+                        field_index,
+                        (
+                            BundleField {
+                                name,
+                                flipped,
+                                ty: _,
+                            },
+                            rhs_field,
+                        ),
+                    ) in lhs_ty.fields().into_iter().zip(rhs_ty.fields()).enumerate()
+                    {
+                        assert_eq!(name, rhs_field.name);
+                        assert_eq!(flipped, rhs_field.flipped);
+                        let mut lhs_expr =
+                            crate::expr::ops::FieldAccess::new_by_index(lhs, field_index).to_expr();
+                        let mut rhs_expr =
+                            crate::expr::ops::FieldAccess::new_by_index(rhs, field_index).to_expr();
+                        if flipped {
+                            mem::swap(&mut lhs_expr, &mut rhs_expr);
+                        }
+                        self.compile_connect(
+                            parent_module,
+                            cond_stack,
+                            lhs_expr,
+                            rhs_expr,
+                            source_location,
+                        );
+                    }
+                    return;
+                }
+                CanonicalType::AsyncReset(_) => unreachable!(),
+                CanonicalType::SyncReset(_) => unreachable!(),
+                CanonicalType::Reset(_) => unreachable!(),
+                CanonicalType::Clock(_) => unreachable!(),
+            }
+        }
+        let lhs = self.compile_expr(lhs);
+        let rhs = self.compile_expr(rhs);
+        let rhs = self.compiled_expr_to_value(rhs);
+        todo!();
     }
     fn compile_block(
         &mut self,
@@ -337,7 +926,7 @@ impl Compiler {
                     lhs,
                     rhs,
                     source_location,
-                }) => todo!(),
+                }) => self.compile_connect(parent_module, cond_stack, lhs, rhs, source_location),
                 Stmt::Formal(StmtFormal {
                     kind,
                     clk,
@@ -351,6 +940,9 @@ impl Compiler {
                     source_location,
                     blocks: [then_block, else_block],
                 }) => {
+                    let cond = self
+                        .compile_expr(Expr::canonical(cond))
+                        .map_ty(Bool::from_canonical);
                     self.compile_block(
                         parent_module,
                         then_block,
@@ -377,13 +969,16 @@ impl Compiler {
                     source_location,
                     blocks,
                 }) => {
+                    let enum_expr = self
+                        .compile_expr(Expr::canonical(expr))
+                        .map_ty(Enum::from_canonical);
                     for (variant_index, block) in blocks.into_iter().enumerate() {
                         self.compile_block(
                             parent_module,
                             block,
                             CondStack::MatchArm {
                                 parent: cond_stack,
-                                enum_expr: expr,
+                                enum_expr,
                                 variant_index,
                                 source_location,
                             }
@@ -392,19 +987,51 @@ impl Compiler {
                     }
                 }
                 Stmt::Declaration(declaration) => match declaration {
-                    StmtDeclaration::Wire(wire) => todo!(),
-                    StmtDeclaration::Reg(reg) => todo!(),
+                    StmtDeclaration::Wire(StmtWire { annotations, wire }) => {
+                        self.compile_value(TargetInInstantiatedModule {
+                            instantiated_module: *parent_module,
+                            target: wire.into(),
+                        });
+                    }
+                    StmtDeclaration::Reg(StmtReg { annotations, reg }) => {
+                        self.compile_value(TargetInInstantiatedModule {
+                            instantiated_module: *parent_module,
+                            target: reg.into(),
+                        });
+                        todo!();
+                    }
                     StmtDeclaration::Instance(StmtInstance {
                         annotations,
                         instance,
                     }) => {
-                        self.compile_module(
+                        let CompiledValue {
+                            layout:
+                                CompiledTypeLayout {
+                                    ty: value_ty,
+                                    layout: ty_layout,
+                                    body: CompiledTypeLayoutBody::Bundle { fields },
+                                },
+                            range: value_range,
+                            write: None,
+                        } = self.compile_value(TargetInInstantiatedModule {
+                            instantiated_module: *parent_module,
+                            target: instance.into(),
+                        })
+                        else {
+                            unreachable!();
+                        };
+                        let CompiledModule { module_io } = *self.compile_module(
                             InstantiatedModule::Child {
                                 parent: parent_module,
                                 instance: instance.intern_sized(),
                             }
                             .intern_sized(),
                         );
+                        for (module_io, CompiledBundleField { offset, ty }) in
+                            module_io.into_iter().zip(fields)
+                        {
+                            todo!();
+                        }
                         todo!()
                     }
                 },
@@ -452,7 +1079,7 @@ impl Compiler {
 
 #[derive(Debug)]
 struct CompiledModule {
-    module_io: Interned<[CompiledValue]>,
+    module_io: Interned<[CompiledValue<CanonicalType>]>,
 }
 
 #[derive(Debug)]
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index f327510..82d3c11 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -4,18 +4,22 @@
 use crate::{
     intern::{Intern, Interned},
     source_location::SourceLocation,
+    util::get_many_mut,
 };
 use num_bigint::BigInt;
 use std::{
+    borrow::BorrowMut,
     convert::Infallible,
     fmt,
-    hash::Hash,
+    hash::{Hash, Hasher},
     marker::PhantomData,
     ops::{Deref, DerefMut, Index, IndexMut},
 };
+use vec_map::VecMap;
 
 pub(crate) type SmallUInt = u64;
 pub(crate) type SmallSInt = i64;
+pub(crate) const MIN_BITS_FOR_NEEDING_BIG: usize = SmallUInt::BITS as usize + 1;
 
 macro_rules! impl_insns {
     (
@@ -39,7 +43,7 @@ macro_rules! impl_insns {
                     $field_name:ident: $field_ty:ty,
                 )*
             })? => $block:block
-        )+
+        )*
     ) => {
         #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)]
         $vis enum $Insn {
@@ -51,7 +55,7 @@ macro_rules! impl_insns {
                         $field_name: $field_ty,
                     )*
                 })?,
-            )+
+            )*
         }
 
         impl $State {
@@ -83,7 +87,7 @@ macro_rules! impl_insns {
                             })? => {
                                 $block
                             }
-                        )+
+                        )*
                     };
                 };
                 $($cleanup)*
@@ -179,35 +183,151 @@ pub(crate) trait StatePartKind:
     fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a>;
 }
 
+pub(crate) trait StatePartsValue {
+    type Value<K: StatePartKind>;
+}
+
+macro_rules! impl_state_parts_traits {
+    (
+        struct $Struct:ident<$V:ident: $StatePartsValue:ident> {
+            $(#[flatten]
+            $flattened_field:ident: $flattened_field_ty:ty,
+            $(#[field_in_flattened]
+            $field_in_flattened:ident: $field_in_flattened_ty:ty,)*
+            )?
+            $($field:ident: $field_ty:ty,)*
+        }
+    ) => {
+        impl<$V: $StatePartsValue> Copy for $Struct<$V>
+        where
+            $($flattened_field_ty: Copy,)?
+            $($field_ty: Copy,)*
+        {
+        }
+
+        impl<$V: $StatePartsValue> Clone for $Struct<$V>
+        where
+            $($flattened_field_ty: Clone,)?
+            $($field_ty: Clone,)*
+        {
+            fn clone(&self) -> Self {
+                Self {
+                    $($flattened_field: self.$flattened_field.clone(),)?
+                    $($field: self.$field.clone(),)*
+                }
+            }
+        }
+
+        impl<$V: $StatePartsValue> fmt::Debug for $Struct<$V>
+        where
+            $($($field_in_flattened_ty: fmt::Debug,)*)?
+            $($field_ty: fmt::Debug,)*
+        {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                f.debug_struct(stringify!($Struct))
+                    $($(.field(stringify!($field_in_flattened), &self.$flattened_field.$field_in_flattened))*)?
+                    $(.field(stringify!($field), &self.$field))*
+                    .finish()
+            }
+        }
+
+        impl<$V: $StatePartsValue> PartialEq for $Struct<$V>
+        where
+            $($flattened_field_ty: PartialEq,)?
+            $($field_ty: PartialEq,)*
+        {
+            fn eq(&self, other: &Self) -> bool {
+                true $(&& self.$flattened_field == other.$flattened_field)? $(&& self.$field == other.$field)*
+            }
+        }
+
+        impl<$V: $StatePartsValue> Eq for $Struct<$V>
+        where
+            $($flattened_field_ty: Eq,)?
+            $($field_ty: Eq,)*
+        {
+        }
+
+        impl<$V: $StatePartsValue> Hash for $Struct<$V>
+        where
+            $($flattened_field_ty: Hash,)?
+            $($field_ty: Hash,)*
+        {
+            fn hash<H: Hasher>(&self, h: &mut H) {
+                $(self.$flattened_field.hash(h);)?
+                $(self.$field.hash(h);)*
+            }
+        }
+
+        impl<$V: $StatePartsValue> Default for $Struct<$V>
+        where
+            $($flattened_field_ty: Default,)?
+            $($field_ty: Default,)*
+        {
+            fn default() -> Self {
+                Self {
+                    $($flattened_field: Default::default(),)?
+                    $($field: Default::default(),)*
+                }
+            }
+        }
+    };
+}
+
 macro_rules! make_state_part_kinds {
     (
         $(
             #[state, field = $state_field:ident]
             impl $StateStatePartKind:ident for $StateKind:ident $state_impl_body:tt
-        )+
+        )*
         $(
             #[type, field = $type_field:ident]
             impl $TypeStatePartKind:ident for $TypeKind:ident $type_impl_body:tt
-        )+
+        )*
     ) => {
         $(
             #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy, Default)]
             pub(crate) struct $StateKind;
 
             impl $StateStatePartKind for $StateKind $state_impl_body
-        )+
+        )*
 
         $(
             #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy, Default)]
             pub(crate) struct $TypeKind;
 
             impl $TypeStatePartKind for $TypeKind $type_impl_body
-        )+
+        )*
+
+        pub(crate) struct StateParts<V: StatePartsValue> {
+            pub(crate) ty: TypeParts<V>,
+            $(pub(crate) $state_field: V::Value<$StateKind>,)*
+        }
+
+        impl_state_parts_traits! {
+            struct StateParts<V: StatePartsValue> {
+                #[flatten]
+                ty: TypeParts<V>,
+                $(#[field_in_flattened]
+                $type_field: V::Value<$TypeKind>,)*
+                $($state_field: V::Value<$StateKind>,)*
+            }
+        }
+
+        pub(crate) struct TypeParts<V: StatePartsValue> {
+            $(pub(crate) $type_field: V::Value<$TypeKind>,)*
+        }
+
+        impl_state_parts_traits! {
+            struct TypeParts<V: StatePartsValue> {
+                $($type_field: V::Value<$TypeKind>,)*
+            }
+        }
 
         #[derive(Clone, PartialEq, Eq, Hash, Debug)]
         pub(crate) struct StateLayout<BK: InsnsBuildingKind> {
             pub(crate) ty: TypeLayout<BK>,
-            $(pub(crate) $state_field: StatePartLayout<$StateKind, BK>,)+
+            $(pub(crate) $state_field: StatePartLayout<$StateKind, BK>,)*
         }
 
         impl Copy for StateLayout<InsnsBuildingDone> {}
@@ -216,16 +336,16 @@ macro_rules! make_state_part_kinds {
             pub(crate) fn len(self) -> StateLen {
                 StateLen {
                     ty: self.ty.len(),
-                    $($state_field: self.$state_field.len(),)+
+                    $($state_field: self.$state_field.len(),)*
                 }
             }
             pub(crate) fn is_empty(self) -> bool {
-                self.ty.is_empty() $(&& self.$state_field.is_empty())+
+                self.ty.is_empty() $(&& self.$state_field.is_empty())*
             }
             pub(crate) fn empty() -> Self {
                 Self {
                     ty: TypeLayout::empty(),
-                    $($state_field: StatePartLayout::empty(),)+
+                    $($state_field: StatePartLayout::empty(),)*
                 }
             }
         }
@@ -234,7 +354,7 @@ macro_rules! make_state_part_kinds {
             pub(crate) fn next_index(&self) -> StateIndex {
                 StateIndex {
                     ty: self.ty.next_index(),
-                    $($state_field: self.$state_field.next_index(),)+
+                    $($state_field: self.$state_field.next_index(),)*
                 }
             }
             pub(crate) fn allocate<BK: InsnsBuildingKind>(
@@ -243,7 +363,7 @@ macro_rules! make_state_part_kinds {
             ) -> StateIndexRange {
                 StateIndexRange {
                     ty: self.ty.allocate(&layout.ty),
-                    $($state_field: self.$state_field.allocate(&layout.$state_field),)+
+                    $($state_field: self.$state_field.allocate(&layout.$state_field),)*
                 }
             }
         }
@@ -252,7 +372,7 @@ macro_rules! make_state_part_kinds {
             fn from(v: StateLayout<InsnsBuilding>) -> Self {
                 Self {
                     ty: v.ty.into(),
-                    $($state_field: v.$state_field.into(),)+
+                    $($state_field: v.$state_field.into(),)*
                 }
             }
         }
@@ -260,42 +380,42 @@ macro_rules! make_state_part_kinds {
         #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
         pub(crate) struct StateIndexRange {
             pub(crate) ty: TypeIndexRange,
-            $(pub(crate) $state_field: StatePartIndexRange<$StateKind>,)+
+            $(pub(crate) $state_field: StatePartIndexRange<$StateKind>,)*
         }
 
         impl StateIndexRange {
             pub(crate) fn start(self) -> StateIndex {
                 StateIndex {
                     ty: self.ty.start(),
-                    $($state_field: self.$state_field.start(),)+
+                    $($state_field: self.$state_field.start(),)*
                 }
             }
             pub(crate) fn len(self) -> StateLen {
                 StateLen {
                     ty: self.ty.len(),
-                    $($state_field: self.$state_field.len(),)+
+                    $($state_field: self.$state_field.len(),)*
                 }
             }
             pub(crate) fn is_empty(self) -> bool {
-                self.ty.is_empty() $(&& self.$state_field.is_empty())+
+                self.ty.is_empty() $(&& self.$state_field.is_empty())*
             }
         }
 
         #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
         pub(crate) struct StateLen {
             pub(crate) ty: TypeLen,
-            $(pub(crate) $state_field: StatePartLen<$StateKind>,)+
+            $(pub(crate) $state_field: StatePartLen<$StateKind>,)*
         }
 
         #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
         pub(crate) struct StateIndex {
             pub(crate) ty: TypeIndex,
-            $(pub(crate) $state_field: StatePartIndex<$StateKind>,)+
+            $(pub(crate) $state_field: StatePartIndex<$StateKind>,)*
         }
 
         #[derive(Clone, PartialEq, Eq, Hash, Debug)]
         pub(crate) struct TypeLayout<BK: InsnsBuildingKind> {
-            $(pub(crate) $type_field: StatePartLayout<$TypeKind, BK>,)+
+            $(pub(crate) $type_field: StatePartLayout<$TypeKind, BK>,)*
         }
 
         impl Copy for TypeLayout<InsnsBuildingDone> {}
@@ -303,7 +423,7 @@ macro_rules! make_state_part_kinds {
         impl<BK: InsnsBuildingKind> TypeLayout<BK> {
             pub(crate) fn len(self) -> TypeLen {
                 TypeLen {
-                    $($type_field: self.$type_field.len(),)+
+                    $($type_field: self.$type_field.len(),)*
                 }
             }
             pub(crate) fn is_empty(self) -> bool {
@@ -311,7 +431,7 @@ macro_rules! make_state_part_kinds {
             }
             pub(crate) fn empty() -> Self {
                 Self {
-                    $($type_field: StatePartLayout::empty(),)+
+                    $($type_field: StatePartLayout::empty(),)*
                 }
             }
         }
@@ -319,7 +439,7 @@ macro_rules! make_state_part_kinds {
         impl TypeLayout<InsnsBuilding> {
             pub(crate) fn next_index(&self) -> TypeIndex {
                 TypeIndex {
-                    $($type_field: self.$type_field.next_index(),)+
+                    $($type_field: self.$type_field.next_index(),)*
                 }
             }
             pub(crate) fn allocate<BK: InsnsBuildingKind>(
@@ -327,7 +447,7 @@ macro_rules! make_state_part_kinds {
                 layout: &TypeLayout<BK>,
             ) -> TypeIndexRange {
                 TypeIndexRange {
-                    $($type_field: self.$type_field.allocate(&layout.$type_field),)+
+                    $($type_field: self.$type_field.allocate(&layout.$type_field),)*
                 }
             }
         }
@@ -335,14 +455,14 @@ macro_rules! make_state_part_kinds {
         impl From<TypeLayout<InsnsBuilding>> for TypeLayout<InsnsBuildingDone> {
             fn from(v: TypeLayout<InsnsBuilding>) -> Self {
                 Self {
-                    $($type_field: v.$type_field.into(),)+
+                    $($type_field: v.$type_field.into(),)*
                 }
             }
         }
 
         #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
         pub(crate) struct TypeIndexRange {
-            $(pub(crate) $type_field: StatePartIndexRange<$TypeKind>,)+
+            $(pub(crate) $type_field: StatePartIndexRange<$TypeKind>,)*
         }
 
         impl TypeIndexRange {
@@ -351,17 +471,17 @@ macro_rules! make_state_part_kinds {
                     $($type_field: StatePartIndexRange {
                         start: start.$type_field,
                         len: len.$type_field,
-                    },)+
+                    },)*
                 }
             }
             pub(crate) fn start(self) -> TypeIndex {
                 TypeIndex {
-                    $($type_field: self.$type_field.start(),)+
+                    $($type_field: self.$type_field.start(),)*
                 }
             }
             pub(crate) fn len(self) -> TypeLen {
                 TypeLen {
-                    $($type_field: self.$type_field.len(),)+
+                    $($type_field: self.$type_field.len(),)*
                 }
             }
             pub(crate) fn is_empty(self) -> bool {
@@ -369,32 +489,32 @@ macro_rules! make_state_part_kinds {
             }
             pub(crate) fn slice(self, index: TypeIndexRange) -> Self {
                 Self {
-                    $($type_field: self.$type_field.slice(index.$type_field),)+
+                    $($type_field: self.$type_field.slice(index.$type_field),)*
                 }
             }
             pub(crate) fn index_array(self, element_size: TypeLen, index: usize) -> Self {
                 Self {
-                    $($type_field: self.$type_field.index_array(element_size.$type_field, index),)+
+                    $($type_field: self.$type_field.index_array(element_size.$type_field, index),)*
                 }
             }
         }
 
         #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
         pub(crate) struct TypeLen {
-            $(pub(crate) $type_field: StatePartLen<$TypeKind>,)+
+            $(pub(crate) $type_field: StatePartLen<$TypeKind>,)*
         }
 
         #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
         pub(crate) struct TypeIndex {
-            $(pub(crate) $type_field: StatePartIndex<$TypeKind>,)+
+            $(pub(crate) $type_field: StatePartIndex<$TypeKind>,)*
         }
 
         #[derive(Debug)]
         pub(crate) struct State {
             pub(crate) insns: Interned<Insns<InsnsBuildingDone>>,
             pub(crate) pc: usize,
-            $(pub(crate) $state_field: StatePart<$StateKind>,)+
-            $(pub(crate) $type_field: StatePart<$TypeKind>,)+
+            $(pub(crate) $state_field: StatePart<$StateKind>,)*
+            $(pub(crate) $type_field: StatePart<$TypeKind>,)*
         }
 
         impl State {
@@ -404,8 +524,8 @@ macro_rules! make_state_part_kinds {
                     insns: &self.insns.insns,
                     pc: self.pc,
                     orig_pc: &mut self.pc,
-                    $($state_field: self.$state_field.borrow(),)+
-                    $($type_field: self.$type_field.borrow(),)+
+                    $($state_field: self.$state_field.borrow(),)*
+                    $($type_field: self.$type_field.borrow(),)*
                 }
             }
         }
@@ -416,8 +536,8 @@ macro_rules! make_state_part_kinds {
             pub(crate) insns: &'a [Insn],
             pub(crate) orig_pc: &'a mut usize,
             pub(crate) pc: usize,
-            $(pub(crate) $state_field: BorrowedStatePart<'a, $StateKind>,)+
-            $(pub(crate) $type_field: BorrowedStatePart<'a, $TypeKind>,)+
+            $(pub(crate) $state_field: BorrowedStatePart<'a, $StateKind>,)*
+            $(pub(crate) $type_field: BorrowedStatePart<'a, $TypeKind>,)*
         }
 
         impl Drop for BorrowedState<'_> {
@@ -429,7 +549,7 @@ macro_rules! make_state_part_kinds {
 }
 
 make_state_part_kinds! {
-    #[state, field = small_stack]
+    /*#[state, field = small_stack]
     impl StatePartKind for StatePartKindSmallStack {
         const NAME: &'static str = "SmallStack";
         type DebugData = ();
@@ -454,7 +574,7 @@ make_state_part_kinds! {
         fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
             state.borrow()
         }
-    }
+    }*/
     #[type, field = small_slots]
     impl StatePartKind for StatePartKindSmallSlots {
         const NAME: &'static str = "SmallSlots";
@@ -483,6 +603,23 @@ make_state_part_kinds! {
     }
 }
 
+impl TypeLen {
+    pub(crate) fn only_small(self) -> Option<StatePartLen<StatePartKindSmallSlots>> {
+        let Self {
+            small_slots,
+            big_slots:
+                StatePartLen {
+                    value: 0,
+                    _phantom: _,
+                },
+        } = self
+        else {
+            return None;
+        };
+        Some(small_slots)
+    }
+}
+
 #[derive(Debug, Clone)]
 pub(crate) struct Stack<T> {
     storage: Box<[T]>,
@@ -544,6 +681,11 @@ pub(crate) struct SlotDebugData {
 }
 
 impl SlotDebugData {
+    pub(crate) fn empty() -> Self {
+        Self {
+            name: Interned::default(),
+        }
+    }
     pub(crate) fn with_prefixed_debug_names(&self, prefix: &str) -> Self {
         let mut name = String::with_capacity(self.name.len() + prefix.len());
         name.push_str(prefix);
@@ -582,6 +724,12 @@ pub(crate) struct StatePartIndex<K: StatePartKind> {
     pub(crate) _phantom: PhantomData<K>,
 }
 
+impl<K: StatePartKind> StatePartIndex<K> {
+    pub(crate) fn as_usize(self) -> usize {
+        self.value.try_into().expect("index too big")
+    }
+}
+
 impl<K: StatePartKind> fmt::Debug for StatePartIndex<K> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         write!(f, "StatePartIndex<{}>({})", K::NAME, self.value)
@@ -716,6 +864,12 @@ impl<K: StatePartKind> StatePartIndexRange<K> {
     pub(crate) fn is_empty(self) -> bool {
         self.len.value == 0
     }
+    pub(crate) fn iter(self) -> impl Iterator<Item = StatePartIndex<K>> {
+        (self.start.value..self.end().value).map(|value| StatePartIndex {
+            value,
+            _phantom: PhantomData,
+        })
+    }
     pub(crate) fn slice(self, index: StatePartIndexRange<K>) -> Self {
         assert!(index.end().value <= self.len.value, "index out of range");
         Self {
@@ -787,6 +941,25 @@ pub(crate) struct BorrowedStatePart<'a, K: StatePartKind> {
     pub(crate) value: K::BorrowedState<'a>,
 }
 
+impl<
+        'a,
+        K: StatePartKind<
+            BorrowedState<'a>: DerefMut<Target: IndexMut<usize, Output = T> + BorrowMut<[T]>>,
+        >,
+        T,
+    > BorrowedStatePart<'a, K>
+{
+    pub(crate) fn get_many_mut<const N: usize>(
+        &mut self,
+        indexes: [StatePartIndex<K>; N],
+    ) -> [&mut T; N] {
+        get_many_mut(
+            (*self.value).borrow_mut(),
+            indexes.map(|v| v.value as usize),
+        )
+    }
+}
+
 impl<'a, K: StatePartKind<BorrowedState<'a>: Deref<Target: Index<usize, Output = T>>>, T>
     Index<StatePartIndex<K>> for BorrowedStatePart<'a, K>
 {
@@ -818,6 +991,139 @@ impl<'a, K: StatePartKind<BorrowedState<'a> = BorrowedStack<'a, T>>, T: 'a>
     }
 }
 
+#[derive(PartialEq, Eq, Hash, Clone)]
+pub(crate) struct StatePartIndexMap<K: StatePartKind, V> {
+    pub(crate) map: VecMap<V>,
+    _phantom: PhantomData<K>,
+}
+
+impl<K: StatePartKind, V: fmt::Debug> fmt::Debug for StatePartIndexMap<K, V> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_map().entries(self.iter()).finish()
+    }
+}
+
+impl<K: StatePartKind, V> StatePartIndexMap<K, V> {
+    pub(crate) fn new() -> Self {
+        Self {
+            map: VecMap::new(),
+            _phantom: PhantomData,
+        }
+    }
+    pub(crate) fn get(&self, key: StatePartIndex<K>) -> Option<&V> {
+        self.map.get(key.as_usize())
+    }
+    pub(crate) fn get_mut(&mut self, key: StatePartIndex<K>) -> Option<&mut V> {
+        self.map.get_mut(key.as_usize())
+    }
+    pub(crate) fn keys(&self) -> impl Iterator<Item = StatePartIndex<K>> + '_ {
+        self.map.keys().map(|k| StatePartIndex {
+            value: k as u32,
+            _phantom: PhantomData,
+        })
+    }
+    pub(crate) fn values(&self) -> vec_map::Values<'_, V> {
+        self.map.values()
+    }
+    pub(crate) fn values_mut(&mut self) -> vec_map::ValuesMut<'_, V> {
+        self.map.values_mut()
+    }
+    pub(crate) fn iter(&self) -> impl Iterator<Item = (StatePartIndex<K>, &V)> + '_ {
+        self.map.iter().map(|(k, v)| {
+            (
+                StatePartIndex {
+                    value: k as u32,
+                    _phantom: PhantomData,
+                },
+                v,
+            )
+        })
+    }
+    pub(crate) fn iter_mut(&mut self) -> impl Iterator<Item = (StatePartIndex<K>, &mut V)> + '_ {
+        self.map.iter_mut().map(|(k, v)| {
+            (
+                StatePartIndex {
+                    value: k as u32,
+                    _phantom: PhantomData,
+                },
+                v,
+            )
+        })
+    }
+    pub(crate) fn len(&self) -> usize {
+        self.map.len()
+    }
+    pub(crate) fn is_empty(&self) -> bool {
+        self.map.is_empty()
+    }
+    pub(crate) fn insert(&mut self, key: StatePartIndex<K>, value: V) -> Option<V> {
+        self.map.insert(key.as_usize(), value)
+    }
+    pub(crate) fn remove(&mut self, key: StatePartIndex<K>) -> Option<V> {
+        self.map.remove(key.as_usize())
+    }
+    pub(crate) fn entry(&mut self, key: StatePartIndex<K>) -> StatePartIndexMapEntry<'_, K, V> {
+        match self.map.entry(key.as_usize()) {
+            vec_map::Entry::Vacant(v) => {
+                StatePartIndexMapEntry::Vacant(StatePartIndexMapVacantEntry(v, PhantomData))
+            }
+            vec_map::Entry::Occupied(v) => {
+                StatePartIndexMapEntry::Occupied(StatePartIndexMapOccupiedEntry(v, PhantomData))
+            }
+        }
+    }
+}
+
+impl<K: StatePartKind, V> Default for StatePartIndexMap<K, V> {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+impl<K: StatePartKind, V> Index<StatePartIndex<K>> for StatePartIndexMap<K, V> {
+    type Output = V;
+
+    fn index(&self, index: StatePartIndex<K>) -> &Self::Output {
+        &self.map[index.as_usize()]
+    }
+}
+
+impl<K: StatePartKind, V> IndexMut<StatePartIndex<K>> for StatePartIndexMap<K, V> {
+    fn index_mut(&mut self, index: StatePartIndex<K>) -> &mut Self::Output {
+        &mut self.map[index.as_usize()]
+    }
+}
+
+pub(crate) struct StatePartIndexMapVacantEntry<'a, K: StatePartKind, V>(
+    vec_map::VacantEntry<'a, V>,
+    PhantomData<K>,
+);
+
+pub(crate) struct StatePartIndexMapOccupiedEntry<'a, K: StatePartKind, V>(
+    vec_map::OccupiedEntry<'a, V>,
+    PhantomData<K>,
+);
+
+pub(crate) enum StatePartIndexMapEntry<'a, K: StatePartKind, V> {
+    Vacant(StatePartIndexMapVacantEntry<'a, K, V>),
+    Occupied(StatePartIndexMapOccupiedEntry<'a, K, V>),
+}
+
+impl<'a, K: StatePartKind, V> StatePartIndexMapEntry<'a, K, V> {
+    pub(crate) fn or_insert(self, default: V) -> &'a mut V {
+        match self {
+            StatePartIndexMapEntry::Vacant(v) => v.0.insert(default),
+            StatePartIndexMapEntry::Occupied(v) => v.0.into_mut(),
+        }
+    }
+    pub(crate) fn or_insert_with(self, f: impl FnOnce() -> V) -> &'a mut V {
+        match self {
+            StatePartIndexMapEntry::Vacant(v) => v.0.insert(f()),
+            StatePartIndexMapEntry::Occupied(v) => v.0.into_mut(),
+        }
+    }
+}
+
 impl Insns<InsnsBuilding> {
     pub(crate) fn new() -> Self {
         Self {
@@ -867,14 +1173,10 @@ impl State {
         let Self {
             insns: _,
             pc,
-            small_stack,
-            big_stack,
             small_slots: _,
             big_slots: _,
         } = self;
         *pc = entry_pc;
-        small_stack.value.clear();
-        big_stack.value.clear();
     }
 }
 
@@ -887,171 +1189,238 @@ impl_insns! {
         main_loop!();
         cleanup! {}
     }
-    ReadSmall {
-        index: StatePartIndex<StatePartKindSmallSlots>,
+    CopySmall {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        src: StatePartIndex<StatePartKindSmallSlots>,
     } => {
-        state.small_stack.push(state.small_slots[index]);
+        state.small_slots[dest] = state.small_slots[src];
+        next!();
+    }
+    CopyBig {
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        src: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let [dest, src] = state.big_slots.get_many_mut([dest, src]);
+        dest.clone_from(src);
         next!();
     }
     SExtSmall {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        src: StatePartIndex<StatePartKindSmallSlots>,
         /// number of bits in a [`SmallSInt`] that aren't used
         unused_bit_count: u8,
     } => {
-        let mut value = state.small_stack.pop() as SmallSInt;
+        let mut value = state.small_slots[src] as SmallSInt;
         value <<= unused_bit_count;
         value >>= unused_bit_count;
-        state.small_stack.push(value as SmallUInt);
+        state.small_slots[dest] = value as SmallUInt;
         next!();
     }
     ZExtSmall {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        src: StatePartIndex<StatePartKindSmallSlots>,
         /// number of bits in a [`SmallUInt`] that aren't used
         unused_bit_count: u8,
     } => {
-        let mut value = state.small_stack.pop();
+        let mut value = state.small_slots[src];
         value <<= unused_bit_count;
         value >>= unused_bit_count;
-        state.small_stack.push(value);
+        state.small_slots[dest] = value;
         next!();
     }
-    AndSmall => {
-        let rhs = state.small_stack.pop();
-        let lhs = state.small_stack.pop();
+    SExtSmallToBig {
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        src: StatePartIndex<StatePartKindSmallSlots>,
+        /// number of bits in a [`SmallSInt`] that aren't used
+        unused_bit_count: u8,
+    } => {
+        let mut value = state.small_slots[src] as SmallSInt;
+        value <<= unused_bit_count;
+        value >>= unused_bit_count;
+        state.big_slots[dest] = value.into();
+        next!();
+    }
+    ZExtSmallToBig {
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        src: StatePartIndex<StatePartKindSmallSlots>,
+        /// number of bits in a [`SmallUInt`] that aren't used
+        unused_bit_count: u8,
+    } => {
+        let mut value = state.small_slots[src];
+        value <<= unused_bit_count;
+        value >>= unused_bit_count;
+        state.big_slots[dest] = value.into();
+        next!();
+    }
+    AndSmall {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        rhs: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let lhs = state.small_slots[lhs];
+        let rhs = state.small_slots[rhs];
         let value = lhs & rhs;
-        state.small_stack.push(value);
+        state.small_slots[dest] = value;
         next!();
     }
-    OrSmall => {
-        let rhs = state.small_stack.pop();
-        let lhs = state.small_stack.pop();
+    OrSmall {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        rhs: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let lhs = state.small_slots[lhs];
+        let rhs = state.small_slots[rhs];
         let value = lhs | rhs;
-        state.small_stack.push(value);
+        state.small_slots[dest] = value;
         next!();
     }
-    XorSmall => {
-        let rhs = state.small_stack.pop();
-        let lhs = state.small_stack.pop();
+    XorSmall {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        rhs: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let lhs = state.small_slots[lhs];
+        let rhs = state.small_slots[rhs];
         let value = lhs ^ rhs;
-        state.small_stack.push(value);
+        state.small_slots[dest] = value;
         next!();
     }
-    NotSmall => {
-        let value = state.small_stack.pop();
-        state.small_stack.push(!value);
+    NotSmall {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        src: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let value = state.small_slots[src];
+        state.small_slots[dest] = !value;
         next!();
     }
-    CmpEqSmall => {
-        let rhs = state.small_stack.pop();
-        let lhs = state.small_stack.pop();
+    CmpEqSmall {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        rhs: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let lhs = state.small_slots[lhs];
+        let rhs = state.small_slots[rhs];
         let value = (lhs == rhs) as SmallUInt;
-        state.small_stack.push(value);
+        state.small_slots[dest] = value;
         next!();
     }
-    CmpNeSmall => {
-        let rhs = state.small_stack.pop();
-        let lhs = state.small_stack.pop();
+    CmpNeSmall {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        rhs: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let lhs = state.small_slots[lhs];
+        let rhs = state.small_slots[rhs];
         let value = (lhs != rhs) as SmallUInt;
-        state.small_stack.push(value);
+        state.small_slots[dest] = value;
         next!();
     }
-    CmpLTSmallUInt => {
-        let rhs = state.small_stack.pop();
-        let lhs = state.small_stack.pop();
+    CmpLTSmallUInt {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        rhs: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let lhs = state.small_slots[lhs];
+        let rhs = state.small_slots[rhs];
         let value = (lhs < rhs) as SmallUInt;
-        state.small_stack.push(value);
+        state.small_slots[dest] = value;
         next!();
     }
-    CmpLESmallUInt => {
-        let rhs = state.small_stack.pop();
-        let lhs = state.small_stack.pop();
+    CmpLESmallUInt {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        rhs: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let lhs = state.small_slots[lhs];
+        let rhs = state.small_slots[rhs];
         let value = (lhs <= rhs) as SmallUInt;
-        state.small_stack.push(value);
+        state.small_slots[dest] = value;
         next!();
     }
-    CmpGTSmallUInt => {
-        let rhs = state.small_stack.pop();
-        let lhs = state.small_stack.pop();
-        let value = (lhs > rhs) as SmallUInt;
-        state.small_stack.push(value);
-        next!();
-    }
-    CmpGESmallUInt => {
-        let rhs = state.small_stack.pop();
-        let lhs = state.small_stack.pop();
-        let value = (lhs >= rhs) as SmallUInt;
-        state.small_stack.push(value);
-        next!();
-    }
-    CmpLTSmallSInt => {
-        let rhs = state.small_stack.pop() as SmallSInt;
-        let lhs = state.small_stack.pop() as SmallSInt;
+    CmpLTSmallSInt {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        rhs: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let lhs = state.small_slots[lhs] as SmallSInt;
+        let rhs = state.small_slots[rhs] as SmallSInt;
         let value = (lhs < rhs) as SmallUInt;
-        state.small_stack.push(value);
+        state.small_slots[dest] = value;
         next!();
     }
-    CmpLESmallSInt => {
-        let rhs = state.small_stack.pop() as SmallSInt;
-        let lhs = state.small_stack.pop() as SmallSInt;
+    CmpLESmallSInt {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        rhs: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let lhs = state.small_slots[lhs] as SmallSInt;
+        let rhs = state.small_slots[rhs] as SmallSInt;
         let value = (lhs <= rhs) as SmallUInt;
-        state.small_stack.push(value);
+        state.small_slots[dest] = value;
         next!();
     }
-    CmpGTSmallSInt => {
-        let rhs = state.small_stack.pop() as SmallSInt;
-        let lhs = state.small_stack.pop() as SmallSInt;
-        let value = (lhs > rhs) as SmallUInt;
-        state.small_stack.push(value);
-        next!();
-    }
-    CmpGESmallSInt => {
-        let rhs = state.small_stack.pop() as SmallSInt;
-        let lhs = state.small_stack.pop() as SmallSInt;
-        let value = (lhs >= rhs) as SmallUInt;
-        state.small_stack.push(value);
-        next!();
-    }
-    AddSmall => {
-        let rhs = state.small_stack.pop();
-        let lhs = state.small_stack.pop();
+    AddSmall {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        rhs: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let lhs = state.small_slots[lhs];
+        let rhs = state.small_slots[rhs];
         let value = lhs.wrapping_add(rhs);
-        state.small_stack.push(value);
+        state.small_slots[dest] = value;
         next!();
     }
-    SubSmall => {
-        let rhs = state.small_stack.pop();
-        let lhs = state.small_stack.pop();
+    SubSmall {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        rhs: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let lhs = state.small_slots[lhs];
+        let rhs = state.small_slots[rhs];
         let value = lhs.wrapping_sub(rhs);
-        state.small_stack.push(value);
+        state.small_slots[dest] = value;
         next!();
     }
-    NegSmall => {
-        let value = state.small_stack.pop();
+    NegSmall {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        src: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let value = state.small_slots[src];
         let value = value.wrapping_neg();
-        state.small_stack.push(value);
+        state.small_slots[dest] = value;
         next!();
     }
-    MulSmall => {
-        let rhs = state.small_stack.pop();
-        let lhs = state.small_stack.pop();
+    NegBig {
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        src: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = -&state.big_slots[src];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    MulSmall {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        rhs: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let lhs = state.small_slots[lhs];
+        let rhs = state.small_slots[rhs];
         let value = lhs.wrapping_mul(rhs);
-        state.small_stack.push(value);
+        state.small_slots[dest] = value;
         next!();
     }
-    ConstU32Small {
-        value: u32,
+    ConstSmall {
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        value: SmallUInt,
     } => {
-        state.small_stack.push(value as SmallUInt);
+        state.small_slots[dest] = value;
         next!();
     }
-    ConstS32Small {
-        value: i32,
+    ConstBig {
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        value: Interned<BigInt>,
     } => {
-        state.small_stack.push(value as SmallUInt);
-        next!();
-    }
-    WriteSmall {
-        index: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        state.small_slots[index] = state.small_stack.pop();
+        state.big_slots[dest].clone_from(&value);
         next!();
     }
     Return => {
diff --git a/crates/fayalite/src/util.rs b/crates/fayalite/src/util.rs
index f66654f..131c54c 100644
--- a/crates/fayalite/src/util.rs
+++ b/crates/fayalite/src/util.rs
@@ -24,7 +24,8 @@ pub use scoped_ref::ScopedRef;
 
 #[doc(inline)]
 pub use misc::{
-    interned_bit, iter_eq_by, BitSliceWriteWithBase, DebugAsDisplay, DebugAsRawString, MakeMutSlice,
+    get_many_mut, interned_bit, iter_eq_by, BitSliceWriteWithBase, DebugAsDisplay,
+    DebugAsRawString, MakeMutSlice,
 };
 
 pub mod job_server;
diff --git a/crates/fayalite/src/util/misc.rs b/crates/fayalite/src/util/misc.rs
index 884458f..85e376a 100644
--- a/crates/fayalite/src/util/misc.rs
+++ b/crates/fayalite/src/util/misc.rs
@@ -155,3 +155,19 @@ impl fmt::UpperHex for BitSliceWriteWithBase<'_> {
         self.fmt_with_base::<4, true>(f)
     }
 }
+
+#[inline]
+#[track_caller]
+pub fn get_many_mut<T, const N: usize>(slice: &mut [T], indexes: [usize; N]) -> [&mut T; N] {
+    for i in 0..N {
+        for j in 0..i {
+            assert!(indexes[i] != indexes[j], "duplicate index");
+        }
+        assert!(indexes[i] < slice.len(), "index out of bounds");
+    }
+    // Safety: checked that no indexes are duplicates and no indexes are out of bounds
+    unsafe {
+        let base = slice.as_mut_ptr(); // convert to a raw pointer before loop to avoid aliasing with &mut [T]
+        std::array::from_fn(|i| &mut *base.add(indexes[i]))
+    }
+}

From f338f37d3ef6cf1ec5a9c2d4db03c50863a9dd93 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 12 Nov 2024 01:08:32 -0800
Subject: [PATCH 084/190] working on simulator

---
 Cargo.lock                             |    5 +-
 Cargo.toml                             |    2 +-
 crates/fayalite/src/sim.rs             | 1230 +++++++++++++++++-------
 crates/fayalite/src/sim/interpreter.rs |  806 +++++++++++-----
 4 files changed, 1454 insertions(+), 589 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 2fca6fc..c280158 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -473,11 +473,10 @@ checksum = "01cda141df6706de531b6c46c3a33ecca755538219bd484262fa09410c13539c"
 
 [[package]]
 name = "num-bigint"
-version = "0.4.4"
+version = "0.4.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "608e7659b5c3d7cba262d894801b9ec9d00de989e8a82bd4bef91d08da45cdc0"
+checksum = "a5e44f723f1133c9deac646763579fdb3ac745e418f2a7af9cd0c431da1f20b9"
 dependencies = [
- "autocfg",
  "num-integer",
  "num-traits",
 ]
diff --git a/Cargo.toml b/Cargo.toml
index 44f5c5a..add4bfe 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -26,7 +26,7 @@ eyre = "0.6.12"
 hashbrown = "0.14.3"
 indexmap = { version = "2.2.6", features = ["serde"] }
 jobslot = "0.2.19"
-num-bigint = "0.4.4"
+num-bigint = "0.4.6"
 num-traits = "0.2.16"
 os_pipe = "1.2.1"
 prettyplease = "0.2.20"
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 9b40458..dbcb88a 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -18,38 +18,39 @@ use crate::{
     },
     prelude::*,
     sim::interpreter::{
-        Insn, Insns, InsnsBuilding, InsnsBuildingDone, SlotDebugData, SmallUInt, StatePartIndex,
-        StatePartIndexMap, StatePartKind, StatePartKindBigSlots, StatePartKindSmallSlots,
-        StatePartLayout, StatePartLen, StatePartsValue, TypeIndex, TypeIndexRange, TypeLayout,
-        TypeLen, TypeParts, MIN_BITS_FOR_NEEDING_BIG,
+        Insn, InsnField, InsnFieldKind, InsnFieldType, Insns, InsnsBuilding, InsnsBuildingDone,
+        SlotDebugData, SmallUInt, StatePartIndex, StatePartIndexMap, StatePartIndexRange,
+        StatePartKind, StatePartKindBigSlots, StatePartKindSmallSlots, StatePartLayout,
+        StatePartLen, StatePartsValue, TypeIndex, TypeIndexRange, TypeLayout, TypeLen, TypeParts,
+        MIN_BITS_FOR_NEEDING_BIG,
     },
 };
 use hashbrown::HashMap;
-use std::{fmt, marker::PhantomData, mem};
+use num_bigint::BigInt;
+use std::{collections::BTreeSet, fmt, marker::PhantomData, mem};
 
 mod interpreter;
 
 #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
-enum CondStack {
-    Always,
+enum CondBody {
     IfTrue {
-        parent: Interned<CondStack>,
         cond: CompiledExpr<Bool>,
-        source_location: SourceLocation,
     },
     IfFalse {
-        parent: Interned<CondStack>,
         cond: CompiledExpr<Bool>,
-        source_location: SourceLocation,
     },
     MatchArm {
-        parent: Interned<CondStack>,
         enum_expr: CompiledExpr<Enum>,
         variant_index: usize,
-        source_location: SourceLocation,
     },
 }
 
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+struct Cond {
+    body: CondBody,
+    source_location: SourceLocation,
+}
+
 #[derive(PartialEq, Eq, Hash, Clone, Copy)]
 enum InstantiatedModule {
     Base(Interned<Module<Bundle>>),
@@ -147,12 +148,9 @@ impl<T: Type> CompiledTypeLayout<T> {
                         let mut layout = TypeLayout::empty();
                         let debug_data = SlotDebugData {
                             name: Interned::default(),
+                            ty: *input,
                         };
-                        if input.bit_width() >= interpreter::MIN_BITS_FOR_NEEDING_BIG {
-                            layout.big_slots = StatePartLayout::scalar(debug_data);
-                        } else {
-                            layout.small_slots = StatePartLayout::scalar(debug_data);
-                        };
+                        layout.big_slots = StatePartLayout::scalar(debug_data);
                         CompiledTypeLayout {
                             ty: *input,
                             layout: layout.into(),
@@ -239,13 +237,94 @@ impl<T: Type> CompiledValue<T> {
     }
 }
 
+impl CompiledValue<Enum> {
+    fn add_discriminant_to_set(self, offset: TypeIndex, inputs: &mut SlotSet) {
+        inputs.extend([self.range.offset(offset)]);
+    }
+}
+
 #[derive(Debug, PartialEq, Eq, Hash, Copy, Clone)]
 struct CompiledExprDynIndex {
     index_slot: StatePartIndex<StatePartKindSmallSlots>,
-    len: TypeLen,
+    len: usize,
     stride: TypeLen,
 }
 
+impl CompiledExprDynIndex {
+    fn offsets(self) -> impl Iterator<Item = TypeIndex> {
+        (0..self.len.try_into().unwrap()).map(move |index| TypeIndex {
+            small_slots: StatePartIndex {
+                value: self
+                    .stride
+                    .small_slots
+                    .value
+                    .checked_mul(index)
+                    .expect("array too big"),
+                _phantom: PhantomData,
+            },
+            big_slots: StatePartIndex {
+                value: self
+                    .stride
+                    .big_slots
+                    .value
+                    .checked_mul(index)
+                    .expect("array too big"),
+                _phantom: PhantomData,
+            },
+        })
+    }
+    fn for_each_offset(dyn_indexes: &[CompiledExprDynIndex], mut f: impl FnMut(TypeIndex)) {
+        fn helper(
+            dyn_indexes: &[CompiledExprDynIndex],
+            offset: TypeIndex,
+            f: &mut impl FnMut(TypeIndex),
+        ) {
+            if let [next, rest @ ..] = dyn_indexes {
+                for next_offset in next.offsets() {
+                    helper(
+                        rest,
+                        TypeIndex {
+                            small_slots: StatePartIndex {
+                                value: next_offset
+                                    .small_slots
+                                    .value
+                                    .checked_add(offset.small_slots.value)
+                                    .expect("array too big"),
+                                _phantom: PhantomData,
+                            },
+                            big_slots: StatePartIndex {
+                                value: next_offset
+                                    .big_slots
+                                    .value
+                                    .checked_add(offset.big_slots.value)
+                                    .expect("array too big"),
+                                _phantom: PhantomData,
+                            },
+                        },
+                        f,
+                    );
+                }
+            } else {
+                f(offset);
+            }
+        }
+        helper(
+            dyn_indexes,
+            TypeIndex {
+                small_slots: StatePartIndex {
+                    value: 0,
+                    _phantom: PhantomData,
+                },
+                big_slots: StatePartIndex {
+                    value: 0,
+                    _phantom: PhantomData,
+                },
+            },
+            &mut f,
+        );
+    }
+}
+
 #[derive(Debug, PartialEq, Eq, Hash, Copy, Clone)]
 struct CompiledExpr<T: Type> {
     static_part: CompiledValue<T>,
@@ -281,6 +360,36 @@ impl<T: Type> CompiledExpr<T> {
             dyn_indexes,
         }
     }
+    fn add_target_without_indexes_to_set(self, inputs: &mut SlotSet) {
+        let Self {
+            static_part,
+            dyn_indexes,
+        } = self;
+        CompiledExprDynIndex::for_each_offset(&dyn_indexes, |offset| {
+            inputs.extend([static_part.range.offset(offset)]);
+        });
+    }
+    fn add_target_and_indexes_to_set(self, inputs: &mut SlotSet) {
+        let Self {
+            static_part: _,
+            dyn_indexes,
+        } = self;
+        self.add_target_without_indexes_to_set(inputs);
+        inputs.extend(dyn_indexes);
+    }
+}
+
+impl CompiledExpr<Enum> {
+    fn add_discriminant_and_indexes_to_set(self, inputs: &mut SlotSet) {
+        let Self {
+            static_part,
+            dyn_indexes,
+        } = self;
+        CompiledExprDynIndex::for_each_offset(&dyn_indexes, |offset| {
+            static_part.add_discriminant_to_set(offset, inputs);
+        });
+        inputs.extend(dyn_indexes);
+    }
 }
 
 #[derive(Clone, Debug, Default, PartialEq, Eq, Hash)]
@@ -297,12 +406,74 @@ impl SlotSet {
 }
 
 impl StatePartsValue for SlotSet {
-    type Value<K: StatePartKind> = Vec<StatePartIndex<K>>;
+    type Value<K: StatePartKind> = BTreeSet<StatePartIndex<K>>;
+}
+
+impl Extend<StatePartIndex<StatePartKindSmallSlots>> for SlotSet {
+    fn extend<T: IntoIterator<Item = StatePartIndex<StatePartKindSmallSlots>>>(&mut self, iter: T) {
+        self.0.small_slots.extend(iter);
+    }
+}
+
+impl Extend<StatePartIndex<StatePartKindBigSlots>> for SlotSet {
+    fn extend<T: IntoIterator<Item = StatePartIndex<StatePartKindBigSlots>>>(&mut self, iter: T) {
+        self.0.big_slots.extend(iter);
+    }
+}
+
+impl<K: StatePartKind> Extend<StatePartIndexRange<K>> for SlotSet
+where
+    Self: Extend<StatePartIndex<K>>,
+{
+    fn extend<T: IntoIterator<Item = StatePartIndexRange<K>>>(&mut self, iter: T) {
+        self.extend(iter.into_iter().flat_map(|v| v.iter()));
+    }
+}
+
+impl Extend<TypeIndexRange> for SlotSet {
+    fn extend<T: IntoIterator<Item = TypeIndexRange>>(&mut self, iter: T) {
+        iter.into_iter().for_each(
+            |TypeIndexRange {
+                 small_slots,
+                 big_slots,
+             }| {
+                self.extend(small_slots.iter());
+                self.extend(big_slots.iter());
+            },
+        )
+    }
+}
+
+impl Extend<CompiledExprDynIndex> for SlotSet {
+    fn extend<T: IntoIterator<Item = CompiledExprDynIndex>>(&mut self, iter: T) {
+        self.extend(iter.into_iter().map(|v| v.index_slot));
+    }
+}
+
+impl Extend<CondBody> for SlotSet {
+    fn extend<T: IntoIterator<Item = CondBody>>(&mut self, iter: T) {
+        iter.into_iter().for_each(|cond_body| match cond_body {
+            CondBody::IfTrue { cond } | CondBody::IfFalse { cond } => {
+                cond.add_target_and_indexes_to_set(self);
+            }
+            CondBody::MatchArm {
+                enum_expr,
+                variant_index,
+            } => enum_expr.add_discriminant_and_indexes_to_set(self),
+        })
+    }
+}
+
+impl Extend<Cond> for SlotSet {
+    fn extend<T: IntoIterator<Item = Cond>>(&mut self, iter: T) {
+        self.extend(iter.into_iter().map(|v| v.body))
+    }
 }
 
 #[derive(Debug)]
 struct Assignment {
     inputs: SlotSet,
+    conditions: Interned<[Cond]>,
     insns: Vec<Insn>,
 }
 
@@ -327,9 +498,9 @@ pub struct Compiler {
     base_module: Interned<Module<Bundle>>,
     modules: HashMap<InstantiatedModule, CompiledModule>,
     compiled_values: HashMap<TargetInInstantiatedModule, CompiledValue<CanonicalType>>,
-    compiled_exprs: HashMap<Expr<CanonicalType>, CompiledExpr<CanonicalType>>,
-    compiled_exprs_to_values: HashMap<CompiledExpr<CanonicalType>, CompiledValue<CanonicalType>>,
-    expanded_to_big: HashMap<Expr<CanonicalType>, CompiledValue<CanonicalType>>,
+    compiled_exprs: HashMap<(Interned<[Cond]>, Expr<CanonicalType>), CompiledExpr<CanonicalType>>,
+    compiled_exprs_to_values:
+        HashMap<(Interned<[Cond]>, CompiledExpr<CanonicalType>), CompiledValue<CanonicalType>>,
     slots_assignments: SlotAssignments,
 }
 
@@ -342,7 +513,6 @@ impl Compiler {
             compiled_values: HashMap::new(),
             compiled_exprs: HashMap::new(),
             compiled_exprs_to_values: HashMap::new(),
-            expanded_to_big: HashMap::new(),
             slots_assignments: SlotAssignments::default(),
         }
     }
@@ -427,9 +597,10 @@ impl Compiler {
     }
     fn compiled_expr_to_value(
         &mut self,
+        conditions: Interned<[Cond]>,
         expr: CompiledExpr<CanonicalType>,
     ) -> CompiledValue<CanonicalType> {
-        if let Some(&retval) = self.compiled_exprs_to_values.get(&expr) {
+        if let Some(&retval) = self.compiled_exprs_to_values.get(&(conditions, expr)) {
             return retval;
         }
         let CompiledExpr {
@@ -444,359 +615,678 @@ impl Compiler {
         {
             todo!();
         }
-        self.compiled_exprs_to_values.insert(expr, retval);
+        self.compiled_exprs_to_values
+            .insert((conditions, expr), retval);
         retval
     }
-    fn simple_nary_expr<const N: usize>(
+    fn add_assignment(
         &mut self,
+        conditions: Interned<[Cond]>,
+        insns: impl IntoIterator<Item = Insn>,
+    ) {
+        let insns = Vec::from_iter(insns);
+        let assignment_index = self.slots_assignments.assignments.len();
+        let mut inputs = SlotSet::default();
+        for insn in &insns {
+            for InsnField { ty, kind } in insn.fields() {
+                match (kind, ty) {
+                    (InsnFieldKind::Input, InsnFieldType::SmallSlot(&small_slot)) => {
+                        inputs.0.small_slots.insert(small_slot);
+                    }
+                    (InsnFieldKind::Input, InsnFieldType::BigSlot(&big_slot)) => {
+                        inputs.0.big_slots.insert(big_slot);
+                    }
+                    (InsnFieldKind::Output, InsnFieldType::SmallSlot(&small_slot)) => self
+                        .slots_assignments
+                        .parts
+                        .small_slots
+                        .written_slot_to_assignment_indexes_map
+                        .entry(small_slot)
+                        .or_insert_with(Vec::new)
+                        .push(assignment_index),
+                    (InsnFieldKind::Output, InsnFieldType::BigSlot(&big_slot)) => self
+                        .slots_assignments
+                        .parts
+                        .big_slots
+                        .written_slot_to_assignment_indexes_map
+                        .entry(big_slot)
+                        .or_insert_with(Vec::new)
+                        .push(assignment_index),
+                    (
+                        _,
+                        InsnFieldType::SmallUInt(_)
+                        | InsnFieldType::SmallSInt(_)
+                        | InsnFieldType::InternedBigInt(_)
+                        | InsnFieldType::U8(_)
+                        | InsnFieldType::USize(_)
+                        | InsnFieldType::Empty(_),
+                    )
+                    | (InsnFieldKind::Immediate | InsnFieldKind::BranchTarget, _) => {}
+                }
+            }
+        }
+        self.slots_assignments.assignments.push(Assignment {
+            inputs,
+            conditions,
+            insns,
+        });
+    }
+    fn simple_nary_big_expr<const N: usize>(
+        &mut self,
+        conditions: Interned<[Cond]>,
         dest_ty: CanonicalType,
         inputs: [Expr<CanonicalType>; N],
         make_insns: impl FnOnce(
-            &mut Self,
-            CompiledValue<CanonicalType>,
-            &mut [CompiledValue<CanonicalType>; N],
+            StatePartIndex<StatePartKindBigSlots>,
+            [StatePartIndex<StatePartKindBigSlots>; N],
         ) -> Vec<Insn>,
     ) -> CompiledValue<CanonicalType> {
-        let mut inputs = inputs.map(|input| {
-            let input = self.compile_expr(input);
-            self.compiled_expr_to_value(input)
+        let inputs = inputs.map(|input| {
+            let input = self.compile_expr(conditions, input);
+            let input = self.compiled_expr_to_value(conditions, input);
+            let TypeIndexRange {
+                small_slots,
+                big_slots,
+            } = input.range;
+            assert_eq!(small_slots.len.value, 0);
+            assert_eq!(big_slots.len.value, 1);
+            big_slots.start
         });
         let layout = CompiledTypeLayout::get(dest_ty);
         let range = self.insns.allocate_variable(&layout.layout);
+        let TypeIndexRange {
+            small_slots,
+            big_slots,
+        } = range;
+        assert_eq!(small_slots.len.value, 0);
+        assert_eq!(big_slots.len.value, 1);
         let retval = CompiledValue {
             layout,
             range,
             write: None,
         };
-        let insns = make_insns(self, retval, &mut inputs);
-        let mut inputs_set = SlotSet::default();
-        for input in inputs {
-            let TypeIndexRange {
-                small_slots,
-                big_slots,
-            } = input.range;
-            inputs_set.0.small_slots.extend(small_slots.iter());
-            inputs_set.0.big_slots.extend(big_slots.iter());
-        }
-        let assignment_index = self.slots_assignments.assignments.len();
-        self.slots_assignments.assignments.push(Assignment {
-            inputs: inputs_set,
-            insns,
-        });
-        let TypeIndexRange {
-            small_slots,
-            big_slots,
-        } = range;
-        for i in small_slots.iter() {
-            self.slots_assignments
-                .parts
-                .small_slots
-                .written_slot_to_assignment_indexes_map
-                .entry(i)
-                .or_insert_with(Vec::new)
-                .push(assignment_index);
-        }
-        for i in big_slots.iter() {
-            self.slots_assignments
-                .parts
-                .big_slots
-                .written_slot_to_assignment_indexes_map
-                .entry(i)
-                .or_insert_with(Vec::new)
-                .push(assignment_index);
-        }
+        self.add_assignment(conditions, make_insns(big_slots.start, inputs));
         retval
     }
-    fn expand_to_big(&mut self, expr: Expr<CanonicalType>) -> CompiledValue<CanonicalType> {
-        if let Some(&retval) = self.expanded_to_big.get(&expr) {
-            return retval;
-        }
-        let input = self.compile_expr(expr);
-        let input = self.compiled_expr_to_value(input);
-        let retval = match input.range.len() {
-            TypeLen {
-                small_slots:
-                    StatePartLen {
-                        value: 0,
-                        _phantom: _,
-                    },
-                big_slots: _,
-            } => input,
-            len => {
-                assert_eq!(
-                    Some(StatePartLen {
-                        value: 1,
-                        _phantom: PhantomData,
-                    }),
-                    len.only_small()
-                );
-                let signed = match Expr::ty(expr) {
-                    CanonicalType::UInt(_) => false,
-                    CanonicalType::SInt(_) => true,
-                    CanonicalType::Bool(_) => false,
-                    CanonicalType::Enum(_) => false,
-                    CanonicalType::Array(_) => unreachable!(),
-                    CanonicalType::Bundle(_) => unreachable!(),
-                    CanonicalType::AsyncReset(_) => false,
-                    CanonicalType::SyncReset(_) => false,
-                    CanonicalType::Reset(_) => false,
-                    CanonicalType::Clock(_) => false,
-                };
-                self.simple_nary_expr(
-                    if signed {
-                        SInt::new_dyn(MIN_BITS_FOR_NEEDING_BIG).canonical()
-                    } else {
-                        UInt::new_dyn(MIN_BITS_FOR_NEEDING_BIG).canonical()
-                    },
-                    [expr],
-                    |_this, dest, [input]| {
-                        let dest = dest.range.big_slots.start;
-                        let src = input.range.small_slots.start;
-                        let unused_bit_count =
-                            interpreter::SmallUInt::BITS as u8 - Expr::ty(expr).bit_width() as u8;
-                        if signed {
-                            vec![Insn::SExtSmallToBig {
-                                dest,
-                                src,
-                                unused_bit_count,
-                            }]
-                        } else {
-                            vec![Insn::ZExtSmallToBig {
-                                dest,
-                                src,
-                                unused_bit_count,
-                            }]
-                        }
-                    },
-                )
-            }
-        };
-        self.expanded_to_big.insert(expr, retval);
-        retval
-    }
-    fn simple_nary_small_or_big_expr<const N: usize>(
+    fn compile_expr(
         &mut self,
-        dest_ty: CanonicalType,
-        inputs: [Expr<CanonicalType>; N],
-        make_insns_small: impl FnOnce(
-            StatePartIndex<StatePartKindSmallSlots>,
-            [StatePartIndex<StatePartKindSmallSlots>; N],
-        ) -> Vec<Insn>,
-        make_insns_big: impl FnOnce(
-            StatePartIndex<StatePartKindBigSlots>,
-            [StatePartIndex<StatePartKindBigSlots>; N],
-        ) -> Vec<Insn>,
-        make_insns_big_to_small: impl FnOnce(
-            StatePartIndex<StatePartKindSmallSlots>,
-            [StatePartIndex<StatePartKindBigSlots>; N],
-        ) -> Vec<Insn>,
-    ) -> CompiledValue<CanonicalType> {
-        self.simple_nary_expr(dest_ty, inputs, |this, dest, compiled_inputs| {
-            let all_inputs_only_small = compiled_inputs
-                .iter()
-                .all(|input| input.range.len().only_small().is_some());
-            if all_inputs_only_small {
-                if dest.range.len().only_small().is_some() {
-                    // all small
-                    assert_eq!(dest.range.len().small_slots.value, 1);
-                    return make_insns_small(
-                        dest.range.small_slots.start,
-                        compiled_inputs.map(
-                            |CompiledValue {
-                                 layout,
-                                 range,
-                                 write: _,
-                             }| {
-                                assert_eq!(range.small_slots.len().value, 1);
-                                range.small_slots.start
-                            },
-                        ),
-                    );
-                } else {
-                    // inputs small, dest big -- expand inputs to big
-                    for (&input, compiled_input) in inputs.iter().zip(&mut *compiled_inputs) {
-                        *compiled_input = this.expand_to_big(input);
-                    }
-                }
-            }
-            let big_inputs = compiled_inputs.map(
-                |CompiledValue {
-                     layout,
-                     range:
-                         TypeIndexRange {
-                             small_slots,
-                             big_slots,
-                         },
-                     write: _,
-                 }| {
-                    assert_eq!(small_slots.len().value, 0);
-                    assert_eq!(big_slots.len().value, 1);
-                    big_slots.start
-                },
-            );
-            if dest.range.len().only_small().is_some() {
-                // inputs big, dest small
-                assert_eq!(dest.range.len().small_slots.value, 1);
-                return make_insns_big_to_small(dest.range.small_slots.start, big_inputs);
-            }
-            let TypeIndexRange {
-                small_slots,
-                big_slots,
-            } = dest.range;
-            assert_eq!(small_slots.len().value, 0);
-            assert_eq!(big_slots.len().value, 1);
-            make_insns_big(big_slots.start, big_inputs)
-        })
-    }
-    fn compile_expr(&mut self, expr: Expr<CanonicalType>) -> CompiledExpr<CanonicalType> {
-        if let Some(&retval) = self.compiled_exprs.get(&expr) {
+        conditions: Interned<[Cond]>,
+        expr: Expr<CanonicalType>,
+    ) -> CompiledExpr<CanonicalType> {
+        if let Some(&retval) = self.compiled_exprs.get(&(conditions, expr)) {
             return retval;
         }
+        let mut cast_bit = |arg: Expr<CanonicalType>| {
+            let src_signed = match Expr::ty(arg) {
+                CanonicalType::UInt(_) => false,
+                CanonicalType::SInt(_) => true,
+                CanonicalType::Bool(_) => false,
+                CanonicalType::Array(_) => unreachable!(),
+                CanonicalType::Enum(_) => unreachable!(),
+                CanonicalType::Bundle(_) => unreachable!(),
+                CanonicalType::AsyncReset(_) => false,
+                CanonicalType::SyncReset(_) => false,
+                CanonicalType::Reset(_) => false,
+                CanonicalType::Clock(_) => false,
+            };
+            let dest_signed = match Expr::ty(expr) {
+                CanonicalType::UInt(_) => false,
+                CanonicalType::SInt(_) => true,
+                CanonicalType::Bool(_) => false,
+                CanonicalType::Array(_) => unreachable!(),
+                CanonicalType::Enum(_) => unreachable!(),
+                CanonicalType::Bundle(_) => unreachable!(),
+                CanonicalType::AsyncReset(_) => false,
+                CanonicalType::SyncReset(_) => false,
+                CanonicalType::Reset(_) => false,
+                CanonicalType::Clock(_) => false,
+            };
+            self.simple_nary_big_expr(conditions, Expr::ty(expr), [arg], |dest, [src]| {
+                match (src_signed, dest_signed) {
+                    (false, false) | (true, true) => {
+                        vec![Insn::Copy { dest, src }]
+                    }
+                    (false, true) => vec![Insn::CastToSInt {
+                        dest,
+                        src,
+                        dest_width: 1,
+                    }],
+                    (true, false) => vec![Insn::CastToUInt {
+                        dest,
+                        src,
+                        dest_width: 1,
+                    }],
+                }
+            })
+            .into()
+        };
         let retval: CompiledExpr<_> = match *Expr::expr_enum(expr) {
             ExprEnum::UIntLiteral(expr) => self
-                .simple_nary_small_or_big_expr(
-                    Bool.canonical(),
-                    [],
-                    |dest, []| {
-                        vec![Insn::ConstSmall {
-                            dest,
-                            value: expr.to_bigint().try_into().expect("const too big"),
-                        }]
-                    },
-                    |dest, []| {
-                        vec![Insn::ConstBig {
-                            dest,
-                            value: expr.to_bigint().intern_sized(),
-                        }]
-                    },
-                    |_, _| unreachable!(),
-                )
+                .simple_nary_big_expr(conditions, expr.ty().canonical(), [], |dest, []| {
+                    vec![Insn::Const {
+                        dest,
+                        value: expr.to_bigint().intern_sized(),
+                    }]
+                })
                 .into(),
             ExprEnum::SIntLiteral(expr) => self
-                .simple_nary_small_or_big_expr(
-                    Bool.canonical(),
-                    [],
-                    |dest, []| {
-                        vec![Insn::ConstSmall {
-                            dest,
-                            value: expr.to_bigint().try_into().expect("const too big"),
-                        }]
-                    },
-                    |dest, []| {
-                        vec![Insn::ConstBig {
-                            dest,
-                            value: expr.to_bigint().intern_sized(),
-                        }]
-                    },
-                    |_, _| unreachable!(),
-                )
+                .simple_nary_big_expr(conditions, expr.ty().canonical(), [], |dest, []| {
+                    vec![Insn::Const {
+                        dest,
+                        value: expr.to_bigint().intern_sized(),
+                    }]
+                })
                 .into(),
             ExprEnum::BoolLiteral(expr) => self
-                .simple_nary_small_or_big_expr(
-                    Bool.canonical(),
-                    [],
-                    |dest, []| {
-                        vec![Insn::ConstSmall {
-                            dest,
-                            value: expr as SmallUInt,
-                        }]
-                    },
-                    |_, _| unreachable!(),
-                    |_, _| unreachable!(),
-                )
+                .simple_nary_big_expr(conditions, Bool.canonical(), [], |dest, []| {
+                    vec![Insn::Const {
+                        dest,
+                        value: BigInt::from(expr).intern_sized(),
+                    }]
+                })
                 .into(),
             ExprEnum::BundleLiteral(expr) => todo!(),
             ExprEnum::ArrayLiteral(expr) => todo!(),
             ExprEnum::EnumLiteral(expr) => todo!(),
             ExprEnum::Uninit(expr) => todo!(),
-            ExprEnum::NotU(expr) => todo!(),
-            ExprEnum::NotS(expr) => todo!(),
-            ExprEnum::NotB(expr) => todo!(),
-            ExprEnum::Neg(expr) => self
-                .simple_nary_small_or_big_expr(
-                    expr.ty().canonical(),
+            ExprEnum::NotU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Expr::ty(expr.arg()).canonical(),
                     [Expr::canonical(expr.arg())],
-                    |dest, [src]| vec![Insn::NegSmall { dest, src }],
-                    |dest, [src]| vec![Insn::NegBig { dest, src }],
-                    |_, _| unreachable!(),
+                    |dest, [src]| {
+                        vec![Insn::NotU {
+                            dest,
+                            src,
+                            width: Expr::ty(expr.arg()).width(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::NotS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Expr::ty(expr.arg()).canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| vec![Insn::NotS { dest, src }],
+                )
+                .into(),
+            ExprEnum::NotB(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Expr::ty(expr.arg()).canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| {
+                        vec![Insn::NotU {
+                            dest,
+                            src,
+                            width: 1,
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::Neg(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| vec![Insn::Neg { dest, src }],
+                )
+                .into(),
+            ExprEnum::BitAndU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::And { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitAndS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::And { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitAndB(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::And { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitOrU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Or { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitOrS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Or { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitOrB(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Or { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitXorU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Xor { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitXorS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Xor { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::BitXorB(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Xor { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::AddU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Add { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::AddS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Add { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::SubU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| {
+                        vec![Insn::SubU {
+                            dest,
+                            lhs,
+                            rhs,
+                            dest_width: expr.ty().width(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::SubS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::SubS { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::MulU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Mul { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::MulS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Mul { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::DivU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Div { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::DivS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Div { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::RemU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Rem { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::RemS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::Rem { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::DynShlU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::DynShl { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::DynShlS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::DynShl { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::DynShrU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::DynShr { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::DynShrS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::DynShr { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::FixedShlU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs())],
+                    |dest, [lhs]| {
+                        vec![Insn::Shl {
+                            dest,
+                            lhs,
+                            rhs: expr.rhs(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::FixedShlS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs())],
+                    |dest, [lhs]| {
+                        vec![Insn::Shl {
+                            dest,
+                            lhs,
+                            rhs: expr.rhs(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::FixedShrU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs())],
+                    |dest, [lhs]| {
+                        vec![Insn::Shr {
+                            dest,
+                            lhs,
+                            rhs: expr.rhs(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::FixedShrS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.lhs())],
+                    |dest, [lhs]| {
+                        vec![Insn::Shr {
+                            dest,
+                            lhs,
+                            rhs: expr.rhs(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::CmpLtB(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpLeB(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpGtB(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    // swap both comparison direction and lhs/rhs
+                    [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpGeB(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    // swap both comparison direction and lhs/rhs
+                    [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpEqB(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpEq { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpNeB(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpNe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpLtU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpLeU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpGtU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    // swap both comparison direction and lhs/rhs
+                    [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpGeU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    // swap both comparison direction and lhs/rhs
+                    [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpEqU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpEq { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpNeU(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpNe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpLtS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpLeS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpGtS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    // swap both comparison direction and lhs/rhs
+                    [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpGeS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    // swap both comparison direction and lhs/rhs
+                    [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpEqS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpEq { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CmpNeS(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    Bool.canonical(),
+                    [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
+                    |dest, [lhs, rhs]| vec![Insn::CmpNe { dest, lhs, rhs }],
+                )
+                .into(),
+            ExprEnum::CastUIntToUInt(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| {
+                        vec![Insn::CastToUInt {
+                            dest,
+                            src,
+                            dest_width: expr.ty().width(),
+                        }]
+                    },
                 )
                 .into(),
-            ExprEnum::BitAndU(expr) => todo!(),
-            ExprEnum::BitAndS(expr) => todo!(),
-            ExprEnum::BitAndB(expr) => todo!(),
-            ExprEnum::BitOrU(expr) => todo!(),
-            ExprEnum::BitOrS(expr) => todo!(),
-            ExprEnum::BitOrB(expr) => todo!(),
-            ExprEnum::BitXorU(expr) => todo!(),
-            ExprEnum::BitXorS(expr) => todo!(),
-            ExprEnum::BitXorB(expr) => todo!(),
-            ExprEnum::AddU(expr) => todo!(),
-            ExprEnum::AddS(expr) => todo!(),
-            ExprEnum::SubU(expr) => todo!(),
-            ExprEnum::SubS(expr) => todo!(),
-            ExprEnum::MulU(expr) => todo!(),
-            ExprEnum::MulS(expr) => todo!(),
-            ExprEnum::DivU(expr) => todo!(),
-            ExprEnum::DivS(expr) => todo!(),
-            ExprEnum::RemU(expr) => todo!(),
-            ExprEnum::RemS(expr) => todo!(),
-            ExprEnum::DynShlU(expr) => todo!(),
-            ExprEnum::DynShlS(expr) => todo!(),
-            ExprEnum::DynShrU(expr) => todo!(),
-            ExprEnum::DynShrS(expr) => todo!(),
-            ExprEnum::FixedShlU(expr) => todo!(),
-            ExprEnum::FixedShlS(expr) => todo!(),
-            ExprEnum::FixedShrU(expr) => todo!(),
-            ExprEnum::FixedShrS(expr) => todo!(),
-            ExprEnum::CmpLtB(expr) => todo!(),
-            ExprEnum::CmpLeB(expr) => todo!(),
-            ExprEnum::CmpGtB(expr) => todo!(),
-            ExprEnum::CmpGeB(expr) => todo!(),
-            ExprEnum::CmpEqB(expr) => todo!(),
-            ExprEnum::CmpNeB(expr) => todo!(),
-            ExprEnum::CmpLtU(expr) => todo!(),
-            ExprEnum::CmpLeU(expr) => todo!(),
-            ExprEnum::CmpGtU(expr) => todo!(),
-            ExprEnum::CmpGeU(expr) => todo!(),
-            ExprEnum::CmpEqU(expr) => todo!(),
-            ExprEnum::CmpNeU(expr) => todo!(),
-            ExprEnum::CmpLtS(expr) => todo!(),
-            ExprEnum::CmpLeS(expr) => todo!(),
-            ExprEnum::CmpGtS(expr) => todo!(),
-            ExprEnum::CmpGeS(expr) => todo!(),
-            ExprEnum::CmpEqS(expr) => todo!(),
-            ExprEnum::CmpNeS(expr) => todo!(),
-            ExprEnum::CastUIntToUInt(expr) => todo!(),
             ExprEnum::CastUIntToSInt(expr) => todo!(),
-            ExprEnum::CastSIntToUInt(expr) => todo!(),
+            ExprEnum::CastSIntToUInt(expr) => self
+                .simple_nary_big_expr(
+                    conditions,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| {
+                        vec![Insn::CastToUInt {
+                            dest,
+                            src,
+                            dest_width: expr.ty().width(),
+                        }]
+                    },
+                )
+                .into(),
             ExprEnum::CastSIntToSInt(expr) => todo!(),
-            ExprEnum::CastBoolToUInt(expr) => todo!(),
-            ExprEnum::CastBoolToSInt(expr) => todo!(),
-            ExprEnum::CastUIntToBool(expr) => todo!(),
-            ExprEnum::CastSIntToBool(expr) => todo!(),
-            ExprEnum::CastBoolToSyncReset(expr) => todo!(),
-            ExprEnum::CastUIntToSyncReset(expr) => todo!(),
-            ExprEnum::CastSIntToSyncReset(expr) => todo!(),
-            ExprEnum::CastBoolToAsyncReset(expr) => todo!(),
-            ExprEnum::CastUIntToAsyncReset(expr) => todo!(),
-            ExprEnum::CastSIntToAsyncReset(expr) => todo!(),
-            ExprEnum::CastSyncResetToBool(expr) => todo!(),
-            ExprEnum::CastSyncResetToUInt(expr) => todo!(),
-            ExprEnum::CastSyncResetToSInt(expr) => todo!(),
-            ExprEnum::CastSyncResetToReset(expr) => todo!(),
-            ExprEnum::CastAsyncResetToBool(expr) => todo!(),
-            ExprEnum::CastAsyncResetToUInt(expr) => todo!(),
-            ExprEnum::CastAsyncResetToSInt(expr) => todo!(),
-            ExprEnum::CastAsyncResetToReset(expr) => todo!(),
-            ExprEnum::CastResetToBool(expr) => todo!(),
-            ExprEnum::CastResetToUInt(expr) => todo!(),
-            ExprEnum::CastResetToSInt(expr) => todo!(),
-            ExprEnum::CastBoolToClock(expr) => todo!(),
-            ExprEnum::CastUIntToClock(expr) => todo!(),
-            ExprEnum::CastSIntToClock(expr) => todo!(),
-            ExprEnum::CastClockToBool(expr) => todo!(),
-            ExprEnum::CastClockToUInt(expr) => todo!(),
-            ExprEnum::CastClockToSInt(expr) => todo!(),
+            ExprEnum::CastBoolToUInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastBoolToSInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastUIntToBool(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSIntToBool(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastBoolToSyncReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastUIntToSyncReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSIntToSyncReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastBoolToAsyncReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastUIntToAsyncReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSIntToAsyncReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSyncResetToBool(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSyncResetToUInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSyncResetToSInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSyncResetToReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastAsyncResetToBool(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastAsyncResetToUInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastAsyncResetToSInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastAsyncResetToReset(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastResetToBool(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastResetToUInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastResetToSInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastBoolToClock(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastUIntToClock(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastSIntToClock(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastClockToBool(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastClockToUInt(expr) => cast_bit(Expr::canonical(expr.arg())),
+            ExprEnum::CastClockToSInt(expr) => cast_bit(Expr::canonical(expr.arg())),
             ExprEnum::FieldAccess(expr) => todo!(),
             ExprEnum::VariantAccess(expr) => todo!(),
             ExprEnum::ArrayIndex(expr) => todo!(),
@@ -817,13 +1307,13 @@ impl Compiler {
             ExprEnum::Reg(expr) => todo!(),
             ExprEnum::MemPort(expr) => todo!(),
         };
-        self.compiled_exprs.insert(expr, retval);
+        self.compiled_exprs.insert((conditions, expr), retval);
         retval
     }
     fn compile_connect(
         &mut self,
         parent_module: Interned<InstantiatedModule>,
-        cond_stack: Interned<CondStack>,
+        conditions: Interned<[Cond]>,
         lhs: Expr<CanonicalType>,
         mut rhs: Expr<CanonicalType>,
         source_location: SourceLocation,
@@ -847,7 +1337,7 @@ impl Compiler {
                     for index in 0..lhs_ty.len() {
                         self.compile_connect(
                             parent_module,
-                            cond_stack,
+                            conditions,
                             lhs[index],
                             rhs[index],
                             source_location,
@@ -891,7 +1381,7 @@ impl Compiler {
                         }
                         self.compile_connect(
                             parent_module,
-                            cond_stack,
+                            conditions,
                             lhs_expr,
                             rhs_expr,
                             source_location,
@@ -905,16 +1395,16 @@ impl Compiler {
                 CanonicalType::Clock(_) => unreachable!(),
             }
         }
-        let lhs = self.compile_expr(lhs);
-        let rhs = self.compile_expr(rhs);
-        let rhs = self.compiled_expr_to_value(rhs);
+        let lhs = self.compile_expr(conditions, lhs);
+        let rhs = self.compile_expr(conditions, rhs);
+        let rhs = self.compiled_expr_to_value(conditions, rhs);
         todo!();
     }
     fn compile_block(
         &mut self,
         parent_module: Interned<InstantiatedModule>,
         block: Block,
-        cond_stack: Interned<CondStack>,
+        conditions: Interned<[Cond]>,
     ) {
         let Block { memories, stmts } = block;
         for memory in memories {
@@ -926,7 +1416,7 @@ impl Compiler {
                     lhs,
                     rhs,
                     source_location,
-                }) => self.compile_connect(parent_module, cond_stack, lhs, rhs, source_location),
+                }) => self.compile_connect(parent_module, conditions, lhs, rhs, source_location),
                 Stmt::Formal(StmtFormal {
                     kind,
                     clk,
@@ -941,27 +1431,23 @@ impl Compiler {
                     blocks: [then_block, else_block],
                 }) => {
                     let cond = self
-                        .compile_expr(Expr::canonical(cond))
+                        .compile_expr(conditions, Expr::canonical(cond))
                         .map_ty(Bool::from_canonical);
                     self.compile_block(
                         parent_module,
                         then_block,
-                        CondStack::IfTrue {
-                            parent: cond_stack,
-                            cond,
+                        Interned::from_iter(conditions.iter().copied().chain([Cond {
+                            body: CondBody::IfTrue { cond },
                             source_location,
-                        }
-                        .intern_sized(),
+                        }])),
                     );
                     self.compile_block(
                         parent_module,
                         else_block,
-                        CondStack::IfFalse {
-                            parent: cond_stack,
-                            cond,
+                        Interned::from_iter(conditions.iter().copied().chain([Cond {
+                            body: CondBody::IfFalse { cond },
                             source_location,
-                        }
-                        .intern_sized(),
+                        }])),
                     );
                 }
                 Stmt::Match(StmtMatch {
@@ -970,19 +1456,19 @@ impl Compiler {
                     blocks,
                 }) => {
                     let enum_expr = self
-                        .compile_expr(Expr::canonical(expr))
+                        .compile_expr(conditions, Expr::canonical(expr))
                         .map_ty(Enum::from_canonical);
                     for (variant_index, block) in blocks.into_iter().enumerate() {
                         self.compile_block(
                             parent_module,
                             block,
-                            CondStack::MatchArm {
-                                parent: cond_stack,
-                                enum_expr,
-                                variant_index,
+                            Interned::from_iter(conditions.iter().copied().chain([Cond {
+                                body: CondBody::MatchArm {
+                                    enum_expr,
+                                    variant_index,
+                                },
                                 source_location,
-                            }
-                            .intern_sized(),
+                            }])),
                         );
                     }
                 }
@@ -1057,7 +1543,7 @@ impl Compiler {
             .collect();
         match module.leaf_module().body() {
             ModuleBody::Normal(NormalModuleBody { body }) => {
-                self.compile_block(module, body, CondStack::Always.intern_sized())
+                self.compile_block(module, body, Interned::default());
             }
             ModuleBody::Extern(_extern_module_body) => {
                 todo!("simulating extern module: {:?}", module);
@@ -1068,8 +1554,9 @@ impl Compiler {
         };
         entry.insert(CompiledModule { module_io })
     }
-    pub fn run(mut self) -> Compiled {
+    pub fn compile(mut self) -> Compiled {
         self.compile_module(InstantiatedModule::Base(self.base_module).intern_sized());
+
         Compiled {
             insns: Insns::from(self.insns).intern_sized(),
             modules: self.modules,
@@ -1090,10 +1577,11 @@ pub struct Compiled {
 
 impl Compiled {
     pub fn new<T: BundleType>(module: Module<T>) -> Self {
-        Compiler::new(module.canonical().intern()).run()
+        Compiler::new(module.canonical().intern()).compile()
     }
 }
 
+#[derive(Debug)]
 pub struct Simulation {
     state: interpreter::State,
 }
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index 82d3c11..8fc9038 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -2,11 +2,13 @@
 // See Notices.txt for copyright information
 
 use crate::{
-    intern::{Intern, Interned},
+    intern::{Intern, Interned, Memoize},
     source_location::SourceLocation,
+    ty::CanonicalType,
     util::get_many_mut,
 };
 use num_bigint::BigInt;
+use num_traits::{One, Signed, ToPrimitive, Zero};
 use std::{
     borrow::BorrowMut,
     convert::Infallible,
@@ -21,6 +23,147 @@ pub(crate) type SmallUInt = u64;
 pub(crate) type SmallSInt = i64;
 pub(crate) const MIN_BITS_FOR_NEEDING_BIG: usize = SmallUInt::BITS as usize + 1;
 
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) enum InsnFieldKind {
+    Input,
+    Output,
+    Immediate,
+    BranchTarget,
+}
+
+pub(crate) trait InsnFieldTypeTransform: Eq + Hash + fmt::Debug + Send + Sync {
+    type Type<FieldType: InsnFieldTrait>: Eq + Hash + fmt::Debug + Send + Sync;
+    fn empty_type() -> Self::Type<[(); 0]>;
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+pub(crate) struct InsnFieldTypeTransformUnit;
+
+impl InsnFieldTypeTransform for InsnFieldTypeTransformUnit {
+    type Type<FieldType: InsnFieldTrait> = ();
+    fn empty_type() -> Self::Type<[(); 0]> {
+        ()
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct InsnFieldTypeTransformRef<'a>(PhantomData<&'a ()>);
+
+impl<'a> InsnFieldTypeTransform for InsnFieldTypeTransformRef<'a> {
+    type Type<FieldType: InsnFieldTrait> = &'a FieldType;
+    fn empty_type() -> Self::Type<[(); 0]> {
+        &[]
+    }
+}
+
+#[derive(PartialEq, Eq, Hash, Debug)]
+pub(crate) struct InsnFieldTypeTransformRefMut<'a>(PhantomData<&'a mut ()>);
+
+impl<'a> InsnFieldTypeTransform for InsnFieldTypeTransformRefMut<'a> {
+    type Type<FieldType: InsnFieldTrait> = &'a mut FieldType;
+    fn empty_type() -> Self::Type<[(); 0]> {
+        &mut []
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct InsnFieldTypeTransformValue;
+
+impl InsnFieldTypeTransform for InsnFieldTypeTransformValue {
+    type Type<FieldType: InsnFieldTrait> = FieldType;
+    fn empty_type() -> Self::Type<[(); 0]> {
+        []
+    }
+}
+
+pub trait InsnFieldTrait: Send + Sync + 'static + Copy + Eq + Hash + fmt::Debug {
+    const UNIT: InsnFieldType<InsnFieldTypeTransformUnit>;
+    fn variant<Transform: InsnFieldTypeTransform>(
+        v: Transform::Type<Self>,
+    ) -> InsnFieldType<Transform>;
+}
+
+macro_rules! insn_field_enum {
+    (
+        $enum_vis:vis enum $InsnFieldType:ident<$Transform:ident: $InsnFieldTypeTransform:ident> {
+            $($Variant:ident($Transform2:ident::$Type:ident<$variant_ty:ty>),)*
+        }
+    ) => {
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        $enum_vis enum $InsnFieldType<$Transform: $InsnFieldTypeTransform> {
+            $($Variant($Transform2::$Type<$variant_ty>),)*
+        }
+
+        $(impl InsnFieldTrait for $variant_ty {
+            const UNIT: $InsnFieldType<InsnFieldTypeTransformUnit> = $InsnFieldType::$Variant(());
+            fn variant<$Transform2: $InsnFieldTypeTransform>(
+                v: $Transform2::$Type<Self>,
+            ) -> $InsnFieldType<$Transform2> {
+                $InsnFieldType::$Variant(v)
+            }
+        })*
+    };
+}
+
+insn_field_enum! {
+    pub(crate) enum InsnFieldType<Transform: InsnFieldTypeTransform> {
+        SmallSlot(Transform::Type<StatePartIndex<StatePartKindSmallSlots>>),
+        BigSlot(Transform::Type<StatePartIndex<StatePartKindBigSlots>>),
+        SmallUInt(Transform::Type<SmallUInt>),
+        SmallSInt(Transform::Type<SmallSInt>),
+        InternedBigInt(Transform::Type<Interned<BigInt>>),
+        U8(Transform::Type<u8>),
+        USize(Transform::Type<usize>),
+        Empty(Transform::Type<[(); 0]>),
+    }
+}
+
+impl<Transform: InsnFieldTypeTransform> InsnFieldType<Transform> {
+    pub(crate) fn empty() -> Self {
+        Self::Empty(Transform::empty_type())
+    }
+}
+
+#[derive(PartialEq, Eq, Hash, Debug)]
+pub(crate) struct InsnField<Transform: InsnFieldTypeTransform> {
+    pub(crate) ty: InsnFieldType<Transform>,
+    pub(crate) kind: InsnFieldKind,
+}
+
+impl<Transform: InsnFieldTypeTransform> Clone for InsnField<Transform>
+where
+    InsnFieldType<Transform>: Clone,
+{
+    fn clone(&self) -> Self {
+        Self {
+            ty: self.ty.clone(),
+            kind: self.kind.clone(),
+        }
+    }
+}
+
+impl<Transform: InsnFieldTypeTransform> Copy for InsnField<Transform> where
+    InsnFieldType<Transform>: Copy
+{
+}
+
+fn make_array_into_iter<T, const I: usize, const N: usize>(
+    input: [T; I],
+    mut default: impl FnMut() -> T,
+) -> std::array::IntoIter<T, N> {
+    const {
+        assert!(I <= N);
+    };
+    let mut input = input.into_iter();
+    let array = std::array::from_fn(|_| input.next().unwrap_or_else(&mut default));
+    let mut retval = array.into_iter();
+    // remove unneeded trailing elements
+    if I < N {
+        retval.nth_back(N - I - 1);
+    }
+    retval
+}
+
 macro_rules! impl_insns {
     (
         #[insn = $Insn:ident, next_macro = $next_macro:ident, branch_macro = $branch_macro:ident]
@@ -39,6 +182,7 @@ macro_rules! impl_insns {
             $(#[$insn_meta:meta])*
             $insn_name:ident $({
                 $(
+                    #[kind = $field_kind:ident]
                     $(#[$field_meta:meta])*
                     $field_name:ident: $field_ty:ty,
                 )*
@@ -58,6 +202,91 @@ macro_rules! impl_insns {
             )*
         }
 
+        impl $Insn {
+            $vis const MAX_FIELDS: usize = {
+                let mut retval = 0;
+                $($(
+                    let fields = [$(stringify!($field_name),)*].len();
+                    if retval < fields {
+                        retval = fields;
+                    }
+                )?)*
+                retval
+            };
+        }
+
+        impl $Insn {
+            $vis const fn fields_unit(&self) -> &'static [InsnField<InsnFieldTypeTransformUnit>] {
+                match self {
+                    $(
+                        $Insn::$insn_name {..} => &[
+                            $($(InsnField {
+                                ty: <$field_ty as InsnFieldTrait>::UNIT,
+                                kind: InsnFieldKind::$field_kind,
+                            },)*)?
+                        ],
+                    )*
+                }
+            }
+            $vis fn fields<'a>(&'a self) -> std::array::IntoIter<InsnField<InsnFieldTypeTransformRef<'a>>, { $Insn::MAX_FIELDS }> {
+                match self {
+                    $(
+                        $Insn::$insn_name $({
+                            $($field_name,)*
+                        })? => make_array_into_iter([
+                                $($(InsnField {
+                                    ty: <$field_ty as InsnFieldTrait>::variant($field_name),
+                                    kind: InsnFieldKind::$field_kind,
+                                },)*)?
+                            ],
+                            || InsnField {
+                                ty: InsnFieldType::empty(),
+                                kind: InsnFieldKind::Immediate,
+                            },
+                        ),
+                    )*
+                }
+            }
+            $vis fn fields_mut<'a>(&'a mut self) -> std::array::IntoIter<InsnField<InsnFieldTypeTransformRefMut<'a>>, { $Insn::MAX_FIELDS }> {
+                match self {
+                    $(
+                        $Insn::$insn_name $({
+                            $($field_name,)*
+                        })? => make_array_into_iter([
+                                $($(InsnField {
+                                    ty: <$field_ty as InsnFieldTrait>::variant($field_name),
+                                    kind: InsnFieldKind::$field_kind,
+                                },)*)?
+                            ],
+                            || InsnField {
+                                ty: InsnFieldType::empty(),
+                                kind: InsnFieldKind::Immediate,
+                            },
+                        ),
+                    )*
+                }
+            }
+            $vis fn into_fields(self) -> std::array::IntoIter<InsnField<InsnFieldTypeTransformValue>, { $Insn::MAX_FIELDS }> {
+                match self {
+                    $(
+                        $Insn::$insn_name $({
+                            $($field_name,)*
+                        })? => make_array_into_iter([
+                                $($(InsnField {
+                                    ty: <$field_ty as InsnFieldTrait>::variant($field_name),
+                                    kind: InsnFieldKind::$field_kind,
+                                },)*)?
+                            ],
+                            || InsnField {
+                                ty: InsnFieldType::empty(),
+                                kind: InsnFieldKind::Immediate,
+                            },
+                        ),
+                    )*
+                }
+            }
+        }
+
         impl $State {
             $vis fn $run(&mut $self) -> $run_ret_ty {
                 let mut $state = $state_init;
@@ -497,6 +726,11 @@ macro_rules! make_state_part_kinds {
                     $($type_field: self.$type_field.index_array(element_size.$type_field, index),)*
                 }
             }
+            pub(crate) fn offset(self, offset: TypeIndex) -> Self {
+                Self {
+                    $($type_field: self.$type_field.offset(offset.$type_field),)*
+                }
+            }
         }
 
         #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
@@ -509,6 +743,14 @@ macro_rules! make_state_part_kinds {
             $(pub(crate) $type_field: StatePartIndex<$TypeKind>,)*
         }
 
+        impl TypeIndex {
+            pub(crate) fn offset(self, offset: TypeIndex) -> Self {
+                Self {
+                    $($type_field: self.$type_field.offset(offset.$type_field),)*
+                }
+            }
+        }
+
         #[derive(Debug)]
         pub(crate) struct State {
             pub(crate) insns: Interned<Insns<InsnsBuildingDone>>,
@@ -678,20 +920,17 @@ impl<T> Drop for BorrowedStack<'_, T> {
 #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)]
 pub(crate) struct SlotDebugData {
     pub(crate) name: Interned<str>,
+    pub(crate) ty: CanonicalType,
 }
 
 impl SlotDebugData {
-    pub(crate) fn empty() -> Self {
-        Self {
-            name: Interned::default(),
-        }
-    }
     pub(crate) fn with_prefixed_debug_names(&self, prefix: &str) -> Self {
         let mut name = String::with_capacity(self.name.len() + prefix.len());
         name.push_str(prefix);
         name.push_str(&self.name);
         Self {
             name: Intern::intern_owned(name),
+            ty: self.ty,
         }
     }
 }
@@ -728,6 +967,15 @@ impl<K: StatePartKind> StatePartIndex<K> {
     pub(crate) fn as_usize(self) -> usize {
         self.value.try_into().expect("index too big")
     }
+    pub(crate) fn offset(self, offset: StatePartIndex<K>) -> Self {
+        Self {
+            value: self
+                .value
+                .checked_add(offset.value)
+                .expect("offset too big"),
+            _phantom: PhantomData,
+        }
+    }
 }
 
 impl<K: StatePartKind> fmt::Debug for StatePartIndex<K> {
@@ -870,6 +1118,13 @@ impl<K: StatePartKind> StatePartIndexRange<K> {
             _phantom: PhantomData,
         })
     }
+    pub(crate) fn offset(self, offset: StatePartIndex<K>) -> Self {
+        self.end().offset(offset); // check for overflow
+        Self {
+            start: self.start.offset(offset),
+            len: self.len,
+        }
+    }
     pub(crate) fn slice(self, index: StatePartIndexRange<K>) -> Self {
         assert!(index.end().value <= self.len.value, "index out of range");
         Self {
@@ -1180,6 +1435,65 @@ impl State {
     }
 }
 
+fn bigint_pow2(width: usize) -> Interned<BigInt> {
+    #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+    struct MyMemoize;
+    impl Memoize for MyMemoize {
+        type Input = usize;
+        type InputOwned = usize;
+        type Output = Interned<BigInt>;
+
+        fn inner(self, input: &Self::Input) -> Self::Output {
+            (BigInt::one() << *input).intern_sized()
+        }
+    }
+    MyMemoize.get(&width)
+}
+
+fn bigint_mask(width: usize) -> Interned<BigInt> {
+    #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+    struct MyMemoize;
+    impl Memoize for MyMemoize {
+        type Input = usize;
+        type InputOwned = usize;
+        type Output = Interned<BigInt>;
+
+        fn inner(self, input: &Self::Input) -> Self::Output {
+            ((BigInt::one() << *input) - BigInt::one()).intern_sized()
+        }
+    }
+    MyMemoize.get(&width)
+}
+
+fn bigint_not_mask(width: usize) -> Interned<BigInt> {
+    #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+    struct MyMemoize;
+    impl Memoize for MyMemoize {
+        type Input = usize;
+        type InputOwned = usize;
+        type Output = Interned<BigInt>;
+
+        fn inner(self, input: &Self::Input) -> Self::Output {
+            (-BigInt::one() << *input).intern_sized()
+        }
+    }
+    MyMemoize.get(&width)
+}
+
+fn cast_bigint_to_sint(src: &BigInt, dest_width: usize) -> BigInt {
+    if dest_width == 0 {
+        BigInt::ZERO
+    } else if src.bit((dest_width - 1) as u64) {
+        src | &*bigint_not_mask(dest_width)
+    } else {
+        src & &*bigint_mask(dest_width)
+    }
+}
+
+fn cast_bigint_to_uint(src: &BigInt, dest_width: usize) -> BigInt {
+    src & &*bigint_mask(dest_width)
+}
+
 impl_insns! {
     #[insn = Insn, next_macro = next, branch_macro = branch]
     pub(crate) fn State::run(&mut self) -> () {
@@ -1189,235 +1503,299 @@ impl_insns! {
         main_loop!();
         cleanup! {}
     }
-    CopySmall {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        src: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        state.small_slots[dest] = state.small_slots[src];
-        next!();
-    }
-    CopyBig {
+    Copy {
+        #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
         src: StatePartIndex<StatePartKindBigSlots>,
     } => {
-        let [dest, src] = state.big_slots.get_many_mut([dest, src]);
-        dest.clone_from(src);
+        if dest != src {
+            let [dest, src] = state.big_slots.get_many_mut([dest, src]);
+            dest.clone_from(src);
+        }
         next!();
     }
-    SExtSmall {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        src: StatePartIndex<StatePartKindSmallSlots>,
-        /// number of bits in a [`SmallSInt`] that aren't used
-        unused_bit_count: u8,
-    } => {
-        let mut value = state.small_slots[src] as SmallSInt;
-        value <<= unused_bit_count;
-        value >>= unused_bit_count;
-        state.small_slots[dest] = value as SmallUInt;
-        next!();
-    }
-    ZExtSmall {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        src: StatePartIndex<StatePartKindSmallSlots>,
-        /// number of bits in a [`SmallUInt`] that aren't used
-        unused_bit_count: u8,
-    } => {
-        let mut value = state.small_slots[src];
-        value <<= unused_bit_count;
-        value >>= unused_bit_count;
-        state.small_slots[dest] = value;
-        next!();
-    }
-    SExtSmallToBig {
+    CastToSInt {
+        #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,
-        src: StatePartIndex<StatePartKindSmallSlots>,
-        /// number of bits in a [`SmallSInt`] that aren't used
-        unused_bit_count: u8,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        dest_width: usize,
     } => {
-        let mut value = state.small_slots[src] as SmallSInt;
-        value <<= unused_bit_count;
-        value >>= unused_bit_count;
-        state.big_slots[dest] = value.into();
+        let value = cast_bigint_to_sint(&state.big_slots[src], dest_width);
+        state.big_slots[dest] = value;
         next!();
     }
-    ZExtSmallToBig {
+    CastToUInt {
+        #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,
-        src: StatePartIndex<StatePartKindSmallSlots>,
-        /// number of bits in a [`SmallUInt`] that aren't used
-        unused_bit_count: u8,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        dest_width: usize,
     } => {
-        let mut value = state.small_slots[src];
-        value <<= unused_bit_count;
-        value >>= unused_bit_count;
-        state.big_slots[dest] = value.into();
+        let value = cast_bigint_to_uint(&state.big_slots[src], dest_width);
+        state.big_slots[dest] = value;
         next!();
     }
-    AndSmall {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        lhs: StatePartIndex<StatePartKindSmallSlots>,
-        rhs: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        let lhs = state.small_slots[lhs];
-        let rhs = state.small_slots[rhs];
-        let value = lhs & rhs;
-        state.small_slots[dest] = value;
-        next!();
-    }
-    OrSmall {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        lhs: StatePartIndex<StatePartKindSmallSlots>,
-        rhs: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        let lhs = state.small_slots[lhs];
-        let rhs = state.small_slots[rhs];
-        let value = lhs | rhs;
-        state.small_slots[dest] = value;
-        next!();
-    }
-    XorSmall {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        lhs: StatePartIndex<StatePartKindSmallSlots>,
-        rhs: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        let lhs = state.small_slots[lhs];
-        let rhs = state.small_slots[rhs];
-        let value = lhs ^ rhs;
-        state.small_slots[dest] = value;
-        next!();
-    }
-    NotSmall {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        src: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        let value = state.small_slots[src];
-        state.small_slots[dest] = !value;
-        next!();
-    }
-    CmpEqSmall {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        lhs: StatePartIndex<StatePartKindSmallSlots>,
-        rhs: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        let lhs = state.small_slots[lhs];
-        let rhs = state.small_slots[rhs];
-        let value = (lhs == rhs) as SmallUInt;
-        state.small_slots[dest] = value;
-        next!();
-    }
-    CmpNeSmall {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        lhs: StatePartIndex<StatePartKindSmallSlots>,
-        rhs: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        let lhs = state.small_slots[lhs];
-        let rhs = state.small_slots[rhs];
-        let value = (lhs != rhs) as SmallUInt;
-        state.small_slots[dest] = value;
-        next!();
-    }
-    CmpLTSmallUInt {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        lhs: StatePartIndex<StatePartKindSmallSlots>,
-        rhs: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        let lhs = state.small_slots[lhs];
-        let rhs = state.small_slots[rhs];
-        let value = (lhs < rhs) as SmallUInt;
-        state.small_slots[dest] = value;
-        next!();
-    }
-    CmpLESmallUInt {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        lhs: StatePartIndex<StatePartKindSmallSlots>,
-        rhs: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        let lhs = state.small_slots[lhs];
-        let rhs = state.small_slots[rhs];
-        let value = (lhs <= rhs) as SmallUInt;
-        state.small_slots[dest] = value;
-        next!();
-    }
-    CmpLTSmallSInt {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        lhs: StatePartIndex<StatePartKindSmallSlots>,
-        rhs: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        let lhs = state.small_slots[lhs] as SmallSInt;
-        let rhs = state.small_slots[rhs] as SmallSInt;
-        let value = (lhs < rhs) as SmallUInt;
-        state.small_slots[dest] = value;
-        next!();
-    }
-    CmpLESmallSInt {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        lhs: StatePartIndex<StatePartKindSmallSlots>,
-        rhs: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        let lhs = state.small_slots[lhs] as SmallSInt;
-        let rhs = state.small_slots[rhs] as SmallSInt;
-        let value = (lhs <= rhs) as SmallUInt;
-        state.small_slots[dest] = value;
-        next!();
-    }
-    AddSmall {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        lhs: StatePartIndex<StatePartKindSmallSlots>,
-        rhs: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        let lhs = state.small_slots[lhs];
-        let rhs = state.small_slots[rhs];
-        let value = lhs.wrapping_add(rhs);
-        state.small_slots[dest] = value;
-        next!();
-    }
-    SubSmall {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        lhs: StatePartIndex<StatePartKindSmallSlots>,
-        rhs: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        let lhs = state.small_slots[lhs];
-        let rhs = state.small_slots[rhs];
-        let value = lhs.wrapping_sub(rhs);
-        state.small_slots[dest] = value;
-        next!();
-    }
-    NegSmall {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        src: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        let value = state.small_slots[src];
-        let value = value.wrapping_neg();
-        state.small_slots[dest] = value;
-        next!();
-    }
-    NegBig {
+    And {
+        #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = &state.big_slots[lhs] & &state.big_slots[rhs];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Or {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = &state.big_slots[lhs] | &state.big_slots[rhs];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Xor {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = &state.big_slots[lhs] ^ &state.big_slots[rhs];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    NotS {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = !&state.big_slots[src];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    NotU {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        width: usize,
+    } => {
+        let value = &state.big_slots[src] ^ &*bigint_mask(width);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Neg {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
         src: StatePartIndex<StatePartKindBigSlots>,
     } => {
         let value = -&state.big_slots[src];
         state.big_slots[dest] = value;
         next!();
     }
-    MulSmall {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        lhs: StatePartIndex<StatePartKindSmallSlots>,
-        rhs: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        let lhs = state.small_slots[lhs];
-        let rhs = state.small_slots[rhs];
-        let value = lhs.wrapping_mul(rhs);
-        state.small_slots[dest] = value;
-        next!();
-    }
-    ConstSmall {
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        value: SmallUInt,
-    } => {
-        state.small_slots[dest] = value;
-        next!();
-    }
-    ConstBig {
+    Add {
+        #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = &state.big_slots[lhs] + &state.big_slots[rhs];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    SubS {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = &state.big_slots[lhs] - &state.big_slots[rhs];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    SubU {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        dest_width: usize,
+    } => {
+        let mut value = &state.big_slots[lhs] - &state.big_slots[rhs];
+        value &= &*bigint_mask(dest_width);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Mul {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = &state.big_slots[lhs] * &state.big_slots[rhs];
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Div {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = state.big_slots[lhs].checked_div(&state.big_slots[rhs]).unwrap_or(BigInt::ZERO);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Rem {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        // no checked_rem?!
+        let value = if state.big_slots[rhs].is_zero() {
+            BigInt::ZERO
+        } else {
+            &state.big_slots[lhs] % &state.big_slots[rhs]
+        };
+        state.big_slots[dest] = value;
+        next!();
+    }
+    DynShl {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let value = &state.big_slots[lhs] << state.big_slots[rhs].to_usize().expect("shl by invalid value");
+        state.big_slots[dest] = value;
+        next!();
+    }
+    DynShr {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        assert!(!state.big_slots[rhs].is_negative(), "shr by invalid value");
+        let value = state.big_slots[rhs].to_usize().map_or(BigInt::ZERO, |rhs| &state.big_slots[lhs] >> rhs);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Shl {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        rhs: usize,
+    } => {
+        let value = &state.big_slots[lhs] << rhs;
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Shr {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        rhs: usize,
+    } => {
+        let value = &state.big_slots[lhs] >> rhs;
+        state.big_slots[dest] = value;
+        next!();
+    }
+    CmpEq {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let lhs = &state.big_slots[lhs];
+        let rhs = &state.big_slots[rhs];
+        let value = BigInt::from(lhs == rhs);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    CmpNe {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let lhs = &state.big_slots[lhs];
+        let rhs = &state.big_slots[rhs];
+        let value = BigInt::from(lhs != rhs);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    CmpLt {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let lhs = &state.big_slots[lhs];
+        let rhs = &state.big_slots[rhs];
+        let value = BigInt::from(lhs < rhs);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    CmpLe {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let lhs = &state.big_slots[lhs];
+        let rhs = &state.big_slots[rhs];
+        let value = BigInt::from(lhs <= rhs);
+        state.big_slots[dest] = value;
+        next!();
+    }
+    Const {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
         value: Interned<BigInt>,
     } => {
         state.big_slots[dest].clone_from(&value);

From 3106a6fff6db72ab44bfccc62383c305ab79e492 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 12 Nov 2024 22:11:12 -0800
Subject: [PATCH 085/190] working on simulator...

---
 crates/fayalite/src/sim.rs             | 1045 ++++++++++++++++--------
 crates/fayalite/src/sim/interpreter.rs |  335 ++++++++
 2 files changed, 1044 insertions(+), 336 deletions(-)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index dbcb88a..8dc087b 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -6,10 +6,12 @@
 use crate::{
     bundle::{BundleField, BundleType},
     expr::{
+        ops,
         target::{
-            Target, TargetBase, TargetPathArrayElement, TargetPathBundleField, TargetPathElement,
+            GetTarget, Target, TargetBase, TargetPathArrayElement, TargetPathBundleField,
+            TargetPathElement,
         },
-        ExprEnum,
+        ExprEnum, Flow,
     },
     intern::{Intern, Interned, Memoize},
     module::{
@@ -19,15 +21,16 @@ use crate::{
     prelude::*,
     sim::interpreter::{
         Insn, InsnField, InsnFieldKind, InsnFieldType, Insns, InsnsBuilding, InsnsBuildingDone,
-        SlotDebugData, SmallUInt, StatePartIndex, StatePartIndexMap, StatePartIndexRange,
-        StatePartKind, StatePartKindBigSlots, StatePartKindSmallSlots, StatePartLayout,
-        StatePartLen, StatePartsValue, TypeIndex, TypeIndexRange, TypeLayout, TypeLen, TypeParts,
-        MIN_BITS_FOR_NEEDING_BIG,
+        SlotDebugData, StatePartArrayIndex, StatePartArrayIndexed, StatePartIndex,
+        StatePartIndexMap, StatePartIndexRange, StatePartKind, StatePartKindBigSlots,
+        StatePartKindSmallSlots, StatePartLayout, StatePartsValue, TypeArrayIndex,
+        TypeArrayIndexes, TypeIndex, TypeIndexRange, TypeLayout, TypeParts,
     },
+    ty::StaticType,
 };
 use hashbrown::HashMap;
 use num_bigint::BigInt;
-use std::{collections::BTreeSet, fmt, marker::PhantomData, mem};
+use std::{collections::BTreeSet, fmt};
 
 mod interpreter;
 
@@ -127,6 +130,14 @@ impl<T: Type> CompiledTypeLayout<T> {
             body,
         }
     }
+    fn with_anonymized_debug_info(self) -> Self {
+        let Self { ty, layout, body } = self;
+        Self {
+            ty,
+            layout: layout.with_anonymized_debug_info(),
+            body,
+        }
+    }
     fn get(ty: T) -> Self {
         #[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)]
         struct MyMemoize;
@@ -221,6 +232,9 @@ struct CompiledValue<T: Type> {
 }
 
 impl<T: Type> CompiledValue<T> {
+    fn write(self) -> (CompiledTypeLayout<T>, TypeIndexRange) {
+        self.write.unwrap_or((self.layout, self.range))
+    }
     fn map<U: Type>(
         self,
         mut f: impl FnMut(
@@ -235,6 +249,18 @@ impl<T: Type> CompiledValue<T> {
             write: self.write.map(|(layout, range)| f(layout, range)),
         }
     }
+    fn map_ty<U: Type>(self, mut f: impl FnMut(T) -> U) -> CompiledValue<U> {
+        self.map(|CompiledTypeLayout { ty, layout, body }, range| {
+            (
+                CompiledTypeLayout {
+                    ty: f(ty),
+                    layout,
+                    body,
+                },
+                range,
+            )
+        })
+    }
 }
 
 impl CompiledValue<Enum> {
@@ -243,139 +269,90 @@ impl CompiledValue<Enum> {
     }
 }
 
-#[derive(Debug, PartialEq, Eq, Hash, Copy, Clone)]
-struct CompiledExprDynIndex {
-    index_slot: StatePartIndex<StatePartKindSmallSlots>,
-    len: usize,
-    stride: TypeLen,
-}
-
-impl CompiledExprDynIndex {
-    fn offsets(self) -> impl Iterator<Item = TypeIndex> {
-        (0..self.len.try_into().unwrap()).map(move |index| TypeIndex {
-            small_slots: StatePartIndex {
-                value: self
-                    .stride
-                    .small_slots
-                    .value
-                    .checked_mul(index)
-                    .expect("array too big"),
-                _phantom: PhantomData,
-            },
-            big_slots: StatePartIndex {
-                value: self
-                    .stride
-                    .big_slots
-                    .value
-                    .checked_mul(index)
-                    .expect("array too big"),
-                _phantom: PhantomData,
-            },
+impl CompiledValue<Bundle> {
+    fn field_by_index(self, field_index: usize) -> CompiledValue<CanonicalType> {
+        self.map(|layout, range| {
+            let CompiledTypeLayout {
+                ty: _,
+                layout: _,
+                body: CompiledTypeLayoutBody::Bundle { fields },
+            } = layout
+            else {
+                unreachable!();
+            };
+            (
+                fields[field_index].ty,
+                range.slice(TypeIndexRange::new(
+                    fields[field_index].offset,
+                    fields[field_index].ty.layout.len(),
+                )),
+            )
         })
     }
-    fn for_each_offset(dyn_indexes: &[CompiledExprDynIndex], mut f: impl FnMut(TypeIndex)) {
-        fn helper(
-            dyn_indexes: &[CompiledExprDynIndex],
-            offset: TypeIndex,
-            f: &mut impl FnMut(TypeIndex),
-        ) {
-            if let [next, rest @ ..] = dyn_indexes {
-                for next_offset in next.offsets() {
-                    helper(
-                        rest,
-                        TypeIndex {
-                            small_slots: StatePartIndex {
-                                value: next_offset
-                                    .small_slots
-                                    .value
-                                    .checked_add(offset.small_slots.value)
-                                    .expect("array too big"),
-                                _phantom: PhantomData,
-                            },
-                            big_slots: StatePartIndex {
-                                value: next_offset
-                                    .big_slots
-                                    .value
-                                    .checked_add(offset.big_slots.value)
-                                    .expect("array too big"),
-                                _phantom: PhantomData,
-                            },
-                        },
-                        f,
-                    );
-                }
-            } else {
-                f(offset);
-            }
-        }
-        helper(
-            dyn_indexes,
-            TypeIndex {
-                small_slots: StatePartIndex {
-                    value: 0,
-                    _phantom: PhantomData,
-                },
-                big_slots: StatePartIndex {
-                    value: 0,
-                    _phantom: PhantomData,
-                },
-            },
-            &mut f,
-        );
+    fn field_by_name(self, name: Interned<str>) -> CompiledValue<CanonicalType> {
+        self.field_by_index(self.layout.ty.name_indexes()[&name])
+    }
+}
+
+impl CompiledValue<Array> {
+    fn element(self, index: usize) -> CompiledValue<CanonicalType> {
+        self.map(|layout, range| {
+            let CompiledTypeLayoutBody::Array { element } = layout.body else {
+                unreachable!();
+            };
+            (*element, range.index_array(element.layout.len(), index))
+        })
+    }
+    fn element_dyn(
+        self,
+        index_slot: StatePartIndex<StatePartKindSmallSlots>,
+    ) -> CompiledExpr<CanonicalType> {
+        CompiledExpr::from(self).element_dyn(index_slot)
     }
 }
 
 #[derive(Debug, PartialEq, Eq, Hash, Copy, Clone)]
 struct CompiledExpr<T: Type> {
     static_part: CompiledValue<T>,
-    dyn_indexes: Interned<[CompiledExprDynIndex]>,
+    indexes: TypeArrayIndexes,
 }
 
 impl<T: Type> From<CompiledValue<T>> for CompiledExpr<T> {
     fn from(static_part: CompiledValue<T>) -> Self {
         Self {
             static_part,
-            dyn_indexes: Interned::default(),
+            indexes: TypeArrayIndexes::default(),
         }
     }
 }
 
 impl<T: Type> CompiledExpr<T> {
-    fn map_ty<U: Type>(self, mut f: impl FnMut(T) -> U) -> CompiledExpr<U> {
+    fn map_ty<U: Type>(self, f: impl FnMut(T) -> U) -> CompiledExpr<U> {
         let Self {
             static_part,
-            dyn_indexes,
+            indexes,
         } = self;
         CompiledExpr {
-            static_part: static_part.map(|CompiledTypeLayout { ty, layout, body }, range| {
-                (
-                    CompiledTypeLayout {
-                        ty: f(ty),
-                        layout,
-                        body,
-                    },
-                    range,
-                )
-            }),
-            dyn_indexes,
+            static_part: static_part.map_ty(f),
+            indexes,
         }
     }
     fn add_target_without_indexes_to_set(self, inputs: &mut SlotSet) {
         let Self {
             static_part,
-            dyn_indexes,
+            indexes,
         } = self;
-        CompiledExprDynIndex::for_each_offset(&dyn_indexes, |offset| {
+        indexes.as_ref().for_each_offset(|offset| {
             inputs.extend([static_part.range.offset(offset)]);
         });
     }
     fn add_target_and_indexes_to_set(self, inputs: &mut SlotSet) {
         let Self {
             static_part: _,
-            dyn_indexes,
+            indexes,
         } = self;
         self.add_target_without_indexes_to_set(inputs);
-        inputs.extend(dyn_indexes);
+        inputs.extend(indexes.as_ref().iter());
     }
 }
 
@@ -383,12 +360,59 @@ impl CompiledExpr<Enum> {
     fn add_discriminant_and_indexes_to_set(self, inputs: &mut SlotSet) {
         let Self {
             static_part,
-            dyn_indexes,
+            indexes,
         } = self;
-        CompiledExprDynIndex::for_each_offset(&dyn_indexes, |offset| {
+        indexes.as_ref().for_each_offset(|offset| {
             static_part.add_discriminant_to_set(offset, inputs);
         });
-        inputs.extend(dyn_indexes);
+        inputs.extend(indexes.as_ref().iter());
+    }
+}
+
+impl CompiledExpr<Bundle> {
+    fn field_by_index(self, field_index: usize) -> CompiledExpr<CanonicalType> {
+        CompiledExpr {
+            static_part: self.static_part.field_by_index(field_index),
+            indexes: self.indexes,
+        }
+    }
+    fn field_by_name(self, name: Interned<str>) -> CompiledExpr<CanonicalType> {
+        CompiledExpr {
+            static_part: self.static_part.field_by_name(name),
+            indexes: self.indexes,
+        }
+    }
+}
+
+impl CompiledExpr<Array> {
+    fn element(self, index: usize) -> CompiledExpr<CanonicalType> {
+        CompiledExpr {
+            static_part: self.static_part.element(index),
+            indexes: self.indexes,
+        }
+    }
+    fn element_dyn(
+        self,
+        index_slot: StatePartIndex<StatePartKindSmallSlots>,
+    ) -> CompiledExpr<CanonicalType> {
+        let CompiledTypeLayoutBody::Array { element } = self.static_part.layout.body else {
+            unreachable!();
+        };
+        let stride = element.layout.len();
+        let indexes = self.indexes.join(TypeArrayIndex::from_parts(
+            index_slot,
+            self.static_part.layout.ty.len(),
+            stride,
+        ));
+        CompiledExpr {
+            static_part: self.static_part.map(|layout, range| {
+                let CompiledTypeLayoutBody::Array { element } = layout.body else {
+                    unreachable!();
+                };
+                (*element, range.index_array(stride, 0))
+            }),
+            indexes,
+        }
     }
 }
 
@@ -444,9 +468,23 @@ impl Extend<TypeIndexRange> for SlotSet {
     }
 }
 
-impl Extend<CompiledExprDynIndex> for SlotSet {
-    fn extend<T: IntoIterator<Item = CompiledExprDynIndex>>(&mut self, iter: T) {
-        self.extend(iter.into_iter().map(|v| v.index_slot));
+impl Extend<TypeArrayIndex> for SlotSet {
+    fn extend<T: IntoIterator<Item = TypeArrayIndex>>(&mut self, iter: T) {
+        iter.into_iter().for_each(
+            |TypeArrayIndex {
+                 small_slots,
+                 big_slots,
+             }| {
+                self.extend([small_slots]);
+                self.extend([big_slots]);
+            },
+        )
+    }
+}
+
+impl<K: StatePartKind> Extend<StatePartArrayIndex<K>> for SlotSet {
+    fn extend<T: IntoIterator<Item = StatePartArrayIndex<K>>>(&mut self, iter: T) {
+        self.extend(iter.into_iter().map(|v| v.index));
     }
 }
 
@@ -475,6 +513,7 @@ struct Assignment {
     inputs: SlotSet,
     conditions: Interned<[Cond]>,
     insns: Vec<Insn>,
+    source_location: SourceLocation,
 }
 
 #[derive(Debug, Default)]
@@ -488,19 +527,59 @@ struct SlotAssignments {
     parts: TypeParts<Self>,
 }
 
+impl SlotAssignments {
+    fn for_assignment(&mut self, assignment_index: usize) -> SlotAssignmentsForAssignment<'_> {
+        SlotAssignmentsForAssignment {
+            parts: &mut self.parts,
+            assignment_index,
+        }
+    }
+}
+
 impl StatePartsValue for SlotAssignments {
     type Value<K: StatePartKind> = StatePartAssignments<K>;
 }
 
+struct SlotAssignmentsForAssignment<'a> {
+    parts: &'a mut TypeParts<SlotAssignments>,
+    assignment_index: usize,
+}
+
+impl Extend<StatePartIndex<StatePartKindSmallSlots>> for SlotAssignmentsForAssignment<'_> {
+    fn extend<T: IntoIterator<Item = StatePartIndex<StatePartKindSmallSlots>>>(&mut self, iter: T) {
+        iter.into_iter().for_each(|slot| {
+            self.parts
+                .small_slots
+                .written_slot_to_assignment_indexes_map
+                .entry(slot)
+                .or_insert_with(Vec::new)
+                .push(self.assignment_index)
+        });
+    }
+}
+
+impl Extend<StatePartIndex<StatePartKindBigSlots>> for SlotAssignmentsForAssignment<'_> {
+    fn extend<T: IntoIterator<Item = StatePartIndex<StatePartKindBigSlots>>>(&mut self, iter: T) {
+        iter.into_iter().for_each(|slot| {
+            self.parts
+                .big_slots
+                .written_slot_to_assignment_indexes_map
+                .entry(slot)
+                .or_insert_with(Vec::new)
+                .push(self.assignment_index)
+        });
+    }
+}
+
 #[derive(Debug)]
 pub struct Compiler {
     insns: Insns<InsnsBuilding>,
     base_module: Interned<Module<Bundle>>,
     modules: HashMap<InstantiatedModule, CompiledModule>,
     compiled_values: HashMap<TargetInInstantiatedModule, CompiledValue<CanonicalType>>,
-    compiled_exprs: HashMap<(Interned<[Cond]>, Expr<CanonicalType>), CompiledExpr<CanonicalType>>,
-    compiled_exprs_to_values:
-        HashMap<(Interned<[Cond]>, CompiledExpr<CanonicalType>), CompiledValue<CanonicalType>>,
+    compiled_exprs: HashMap<Expr<CanonicalType>, CompiledExpr<CanonicalType>>,
+    compiled_exprs_to_values: HashMap<CompiledExpr<CanonicalType>, CompiledValue<CanonicalType>>,
+    decl_conditions: HashMap<TargetInInstantiatedModule, Interned<[Cond]>>,
     slots_assignments: SlotAssignments,
 }
 
@@ -513,6 +592,7 @@ impl Compiler {
             compiled_values: HashMap::new(),
             compiled_exprs: HashMap::new(),
             compiled_exprs_to_values: HashMap::new(),
+            decl_conditions: HashMap::new(),
             slots_assignments: SlotAssignments::default(),
         }
     }
@@ -562,32 +642,11 @@ impl Compiler {
                 });
                 match *target_child.path_element() {
                     TargetPathElement::BundleField(TargetPathBundleField { name }) => {
-                        parent.map(|layout, range| {
-                            let CompiledTypeLayout {
-                                ty: CanonicalType::Bundle(bundle),
-                                layout: _,
-                                body: CompiledTypeLayoutBody::Bundle { fields },
-                            } = layout
-                            else {
-                                unreachable!();
-                            };
-                            let field_index = bundle.name_indexes()[&name];
-                            (
-                                fields[field_index].ty,
-                                range.slice(TypeIndexRange::new(
-                                    fields[field_index].offset,
-                                    fields[field_index].ty.layout.len(),
-                                )),
-                            )
-                        })
+                        parent.map_ty(Bundle::from_canonical).field_by_name(name)
+                    }
+                    TargetPathElement::ArrayElement(TargetPathArrayElement { index }) => {
+                        parent.map_ty(Array::from_canonical).element(index)
                     }
-                    TargetPathElement::ArrayElement(TargetPathArrayElement { index }) => parent
-                        .map(|layout, range| {
-                            let CompiledTypeLayoutBody::Array { element } = layout.body else {
-                                unreachable!();
-                            };
-                            (*element, range.index_array(element.layout.len(), index))
-                        }),
                     TargetPathElement::DynArrayElement(_) => unreachable!(),
                 }
             }
@@ -597,32 +656,76 @@ impl Compiler {
     }
     fn compiled_expr_to_value(
         &mut self,
-        conditions: Interned<[Cond]>,
         expr: CompiledExpr<CanonicalType>,
+        source_location: SourceLocation,
     ) -> CompiledValue<CanonicalType> {
-        if let Some(&retval) = self.compiled_exprs_to_values.get(&(conditions, expr)) {
+        if let Some(&retval) = self.compiled_exprs_to_values.get(&expr) {
             return retval;
         }
+        assert!(
+            expr.static_part.layout.ty.is_passive(),
+            "invalid expression passed to compiled_expr_to_value -- type must be passive",
+        );
         let CompiledExpr {
-            static_part: mut retval,
-            dyn_indexes,
+            static_part,
+            indexes,
         } = expr;
-        for CompiledExprDynIndex {
-            index_slot,
-            len,
-            stride,
-        } in dyn_indexes
-        {
-            todo!();
-        }
-        self.compiled_exprs_to_values
-            .insert((conditions, expr), retval);
+        let layout = static_part.layout.with_anonymized_debug_info();
+        let retval = CompiledValue {
+            layout,
+            range: self.insns.allocate_variable(&layout.layout),
+            write: None,
+        };
+        let TypeIndexRange {
+            small_slots,
+            big_slots,
+        } = retval.range;
+        self.add_assignment(
+            Interned::default(),
+            small_slots
+                .iter()
+                .zip(static_part.range.small_slots.iter())
+                .map(|(dest, base)| {
+                    if indexes.small_slots.is_empty() {
+                        Insn::CopySmall { dest, src: base }
+                    } else {
+                        Insn::ReadSmallIndexed {
+                            dest,
+                            src: StatePartArrayIndexed {
+                                base,
+                                indexes: indexes.small_slots,
+                            },
+                        }
+                    }
+                })
+                .chain(
+                    big_slots
+                        .iter()
+                        .zip(static_part.range.big_slots.iter())
+                        .map(|(dest, base)| {
+                            if indexes.big_slots.is_empty() {
+                                Insn::Copy { dest, src: base }
+                            } else {
+                                Insn::ReadIndexed {
+                                    dest,
+                                    src: StatePartArrayIndexed {
+                                        base,
+                                        indexes: indexes.big_slots,
+                                    },
+                                }
+                            }
+                        }),
+                ),
+            source_location,
+        );
+        self.compiled_exprs_to_values.insert(expr, retval);
         retval
     }
     fn add_assignment(
         &mut self,
         conditions: Interned<[Cond]>,
         insns: impl IntoIterator<Item = Insn>,
+        source_location: SourceLocation,
     ) {
         let insns = Vec::from_iter(insns);
         let assignment_index = self.slots_assignments.assignments.len();
@@ -630,28 +733,50 @@ impl Compiler {
         for insn in &insns {
             for InsnField { ty, kind } in insn.fields() {
                 match (kind, ty) {
-                    (InsnFieldKind::Input, InsnFieldType::SmallSlot(&small_slot)) => {
-                        inputs.0.small_slots.insert(small_slot);
+                    (InsnFieldKind::Input, InsnFieldType::SmallSlot(&slot)) => {
+                        inputs.extend([slot]);
                     }
-                    (InsnFieldKind::Input, InsnFieldType::BigSlot(&big_slot)) => {
-                        inputs.0.big_slots.insert(big_slot);
+                    (InsnFieldKind::Input, InsnFieldType::BigSlot(&slot)) => {
+                        inputs.extend([slot]);
                     }
-                    (InsnFieldKind::Output, InsnFieldType::SmallSlot(&small_slot)) => self
+                    (
+                        InsnFieldKind::Input,
+                        InsnFieldType::SmallSlotArrayIndexed(&array_indexed),
+                    ) => {
+                        array_indexed.for_each_target(|slot| inputs.extend([slot]));
+                        inputs.extend(array_indexed.indexes);
+                    }
+                    (InsnFieldKind::Input, InsnFieldType::BigSlotArrayIndexed(&array_indexed)) => {
+                        array_indexed.for_each_target(|slot| inputs.extend([slot]));
+                        inputs.extend(array_indexed.indexes);
+                    }
+                    (InsnFieldKind::Output, InsnFieldType::SmallSlot(&slot)) => self
                         .slots_assignments
-                        .parts
-                        .small_slots
-                        .written_slot_to_assignment_indexes_map
-                        .entry(small_slot)
-                        .or_insert_with(Vec::new)
-                        .push(assignment_index),
-                    (InsnFieldKind::Output, InsnFieldType::BigSlot(&big_slot)) => self
+                        .for_assignment(assignment_index)
+                        .extend([slot]),
+                    (InsnFieldKind::Output, InsnFieldType::BigSlot(&slot)) => self
                         .slots_assignments
-                        .parts
-                        .big_slots
-                        .written_slot_to_assignment_indexes_map
-                        .entry(big_slot)
-                        .or_insert_with(Vec::new)
-                        .push(assignment_index),
+                        .for_assignment(assignment_index)
+                        .extend([slot]),
+                    (
+                        InsnFieldKind::Output,
+                        InsnFieldType::SmallSlotArrayIndexed(&array_indexed),
+                    ) => {
+                        array_indexed.for_each_target(|slot| {
+                            self.slots_assignments
+                                .for_assignment(assignment_index)
+                                .extend([slot])
+                        });
+                        inputs.extend(array_indexed.indexes);
+                    }
+                    (InsnFieldKind::Output, InsnFieldType::BigSlotArrayIndexed(&array_indexed)) => {
+                        array_indexed.for_each_target(|slot| {
+                            self.slots_assignments
+                                .for_assignment(assignment_index)
+                                .extend([slot])
+                        });
+                        inputs.extend(array_indexed.indexes);
+                    }
                     (
                         _,
                         InsnFieldType::SmallUInt(_)
@@ -669,11 +794,12 @@ impl Compiler {
             inputs,
             conditions,
             insns,
+            source_location,
         });
     }
     fn simple_nary_big_expr<const N: usize>(
         &mut self,
-        conditions: Interned<[Cond]>,
+        instantiated_module: InstantiatedModule,
         dest_ty: CanonicalType,
         inputs: [Expr<CanonicalType>; N],
         make_insns: impl FnOnce(
@@ -682,8 +808,9 @@ impl Compiler {
         ) -> Vec<Insn>,
     ) -> CompiledValue<CanonicalType> {
         let inputs = inputs.map(|input| {
-            let input = self.compile_expr(conditions, input);
-            let input = self.compiled_expr_to_value(conditions, input);
+            let input = self.compile_expr(instantiated_module, input);
+            let input = self
+                .compiled_expr_to_value(input, instantiated_module.leaf_module().source_location());
             let TypeIndexRange {
                 small_slots,
                 big_slots,
@@ -705,15 +832,19 @@ impl Compiler {
             range,
             write: None,
         };
-        self.add_assignment(conditions, make_insns(big_slots.start, inputs));
+        self.add_assignment(
+            Interned::default(),
+            make_insns(big_slots.start, inputs),
+            instantiated_module.leaf_module().source_location(),
+        );
         retval
     }
     fn compile_expr(
         &mut self,
-        conditions: Interned<[Cond]>,
+        instantiated_module: InstantiatedModule,
         expr: Expr<CanonicalType>,
     ) -> CompiledExpr<CanonicalType> {
-        if let Some(&retval) = self.compiled_exprs.get(&(conditions, expr)) {
+        if let Some(&retval) = self.compiled_exprs.get(&expr) {
             return retval;
         }
         let mut cast_bit = |arg: Expr<CanonicalType>| {
@@ -741,7 +872,7 @@ impl Compiler {
                 CanonicalType::Reset(_) => false,
                 CanonicalType::Clock(_) => false,
             };
-            self.simple_nary_big_expr(conditions, Expr::ty(expr), [arg], |dest, [src]| {
+            self.simple_nary_big_expr(instantiated_module, Expr::ty(expr), [arg], |dest, [src]| {
                 match (src_signed, dest_signed) {
                     (false, false) | (true, true) => {
                         vec![Insn::Copy { dest, src }]
@@ -762,23 +893,33 @@ impl Compiler {
         };
         let retval: CompiledExpr<_> = match *Expr::expr_enum(expr) {
             ExprEnum::UIntLiteral(expr) => self
-                .simple_nary_big_expr(conditions, expr.ty().canonical(), [], |dest, []| {
-                    vec![Insn::Const {
-                        dest,
-                        value: expr.to_bigint().intern_sized(),
-                    }]
-                })
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [],
+                    |dest, []| {
+                        vec![Insn::Const {
+                            dest,
+                            value: expr.to_bigint().intern_sized(),
+                        }]
+                    },
+                )
                 .into(),
             ExprEnum::SIntLiteral(expr) => self
-                .simple_nary_big_expr(conditions, expr.ty().canonical(), [], |dest, []| {
-                    vec![Insn::Const {
-                        dest,
-                        value: expr.to_bigint().intern_sized(),
-                    }]
-                })
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [],
+                    |dest, []| {
+                        vec![Insn::Const {
+                            dest,
+                            value: expr.to_bigint().intern_sized(),
+                        }]
+                    },
+                )
                 .into(),
             ExprEnum::BoolLiteral(expr) => self
-                .simple_nary_big_expr(conditions, Bool.canonical(), [], |dest, []| {
+                .simple_nary_big_expr(instantiated_module, Bool.canonical(), [], |dest, []| {
                     vec![Insn::Const {
                         dest,
                         value: BigInt::from(expr).intern_sized(),
@@ -791,7 +932,7 @@ impl Compiler {
             ExprEnum::Uninit(expr) => todo!(),
             ExprEnum::NotU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Expr::ty(expr.arg()).canonical(),
                     [Expr::canonical(expr.arg())],
                     |dest, [src]| {
@@ -805,7 +946,7 @@ impl Compiler {
                 .into(),
             ExprEnum::NotS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Expr::ty(expr.arg()).canonical(),
                     [Expr::canonical(expr.arg())],
                     |dest, [src]| vec![Insn::NotS { dest, src }],
@@ -813,7 +954,7 @@ impl Compiler {
                 .into(),
             ExprEnum::NotB(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Expr::ty(expr.arg()).canonical(),
                     [Expr::canonical(expr.arg())],
                     |dest, [src]| {
@@ -827,7 +968,7 @@ impl Compiler {
                 .into(),
             ExprEnum::Neg(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.arg())],
                     |dest, [src]| vec![Insn::Neg { dest, src }],
@@ -835,7 +976,7 @@ impl Compiler {
                 .into(),
             ExprEnum::BitAndU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::And { dest, lhs, rhs }],
@@ -843,7 +984,7 @@ impl Compiler {
                 .into(),
             ExprEnum::BitAndS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::And { dest, lhs, rhs }],
@@ -851,7 +992,7 @@ impl Compiler {
                 .into(),
             ExprEnum::BitAndB(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::And { dest, lhs, rhs }],
@@ -859,7 +1000,7 @@ impl Compiler {
                 .into(),
             ExprEnum::BitOrU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::Or { dest, lhs, rhs }],
@@ -867,7 +1008,7 @@ impl Compiler {
                 .into(),
             ExprEnum::BitOrS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::Or { dest, lhs, rhs }],
@@ -875,7 +1016,7 @@ impl Compiler {
                 .into(),
             ExprEnum::BitOrB(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::Or { dest, lhs, rhs }],
@@ -883,7 +1024,7 @@ impl Compiler {
                 .into(),
             ExprEnum::BitXorU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::Xor { dest, lhs, rhs }],
@@ -891,7 +1032,7 @@ impl Compiler {
                 .into(),
             ExprEnum::BitXorS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::Xor { dest, lhs, rhs }],
@@ -899,7 +1040,7 @@ impl Compiler {
                 .into(),
             ExprEnum::BitXorB(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::Xor { dest, lhs, rhs }],
@@ -907,7 +1048,7 @@ impl Compiler {
                 .into(),
             ExprEnum::AddU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::Add { dest, lhs, rhs }],
@@ -915,7 +1056,7 @@ impl Compiler {
                 .into(),
             ExprEnum::AddS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::Add { dest, lhs, rhs }],
@@ -923,7 +1064,7 @@ impl Compiler {
                 .into(),
             ExprEnum::SubU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| {
@@ -938,7 +1079,7 @@ impl Compiler {
                 .into(),
             ExprEnum::SubS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::SubS { dest, lhs, rhs }],
@@ -946,7 +1087,7 @@ impl Compiler {
                 .into(),
             ExprEnum::MulU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::Mul { dest, lhs, rhs }],
@@ -954,7 +1095,7 @@ impl Compiler {
                 .into(),
             ExprEnum::MulS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::Mul { dest, lhs, rhs }],
@@ -962,7 +1103,7 @@ impl Compiler {
                 .into(),
             ExprEnum::DivU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::Div { dest, lhs, rhs }],
@@ -970,7 +1111,7 @@ impl Compiler {
                 .into(),
             ExprEnum::DivS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::Div { dest, lhs, rhs }],
@@ -978,7 +1119,7 @@ impl Compiler {
                 .into(),
             ExprEnum::RemU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::Rem { dest, lhs, rhs }],
@@ -986,7 +1127,7 @@ impl Compiler {
                 .into(),
             ExprEnum::RemS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::Rem { dest, lhs, rhs }],
@@ -994,7 +1135,7 @@ impl Compiler {
                 .into(),
             ExprEnum::DynShlU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::DynShl { dest, lhs, rhs }],
@@ -1002,7 +1143,7 @@ impl Compiler {
                 .into(),
             ExprEnum::DynShlS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::DynShl { dest, lhs, rhs }],
@@ -1010,7 +1151,7 @@ impl Compiler {
                 .into(),
             ExprEnum::DynShrU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::DynShr { dest, lhs, rhs }],
@@ -1018,7 +1159,7 @@ impl Compiler {
                 .into(),
             ExprEnum::DynShrS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::DynShr { dest, lhs, rhs }],
@@ -1026,7 +1167,7 @@ impl Compiler {
                 .into(),
             ExprEnum::FixedShlU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs())],
                     |dest, [lhs]| {
@@ -1040,7 +1181,7 @@ impl Compiler {
                 .into(),
             ExprEnum::FixedShlS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs())],
                     |dest, [lhs]| {
@@ -1054,7 +1195,7 @@ impl Compiler {
                 .into(),
             ExprEnum::FixedShrU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs())],
                     |dest, [lhs]| {
@@ -1068,7 +1209,7 @@ impl Compiler {
                 .into(),
             ExprEnum::FixedShrS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.lhs())],
                     |dest, [lhs]| {
@@ -1082,7 +1223,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpLtB(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }],
@@ -1090,7 +1231,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpLeB(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }],
@@ -1098,7 +1239,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpGtB(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     // swap both comparison direction and lhs/rhs
                     [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
@@ -1107,7 +1248,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpGeB(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     // swap both comparison direction and lhs/rhs
                     [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
@@ -1116,7 +1257,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpEqB(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::CmpEq { dest, lhs, rhs }],
@@ -1124,7 +1265,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpNeB(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::CmpNe { dest, lhs, rhs }],
@@ -1132,7 +1273,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpLtU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }],
@@ -1140,7 +1281,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpLeU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }],
@@ -1148,7 +1289,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpGtU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     // swap both comparison direction and lhs/rhs
                     [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
@@ -1157,7 +1298,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpGeU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     // swap both comparison direction and lhs/rhs
                     [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
@@ -1166,7 +1307,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpEqU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::CmpEq { dest, lhs, rhs }],
@@ -1174,7 +1315,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpNeU(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::CmpNe { dest, lhs, rhs }],
@@ -1182,7 +1323,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpLtS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::CmpLt { dest, lhs, rhs }],
@@ -1190,7 +1331,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpLeS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::CmpLe { dest, lhs, rhs }],
@@ -1198,7 +1339,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpGtS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     // swap both comparison direction and lhs/rhs
                     [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
@@ -1207,7 +1348,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpGeS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     // swap both comparison direction and lhs/rhs
                     [Expr::canonical(expr.rhs()), Expr::canonical(expr.lhs())],
@@ -1216,7 +1357,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpEqS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::CmpEq { dest, lhs, rhs }],
@@ -1224,7 +1365,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CmpNeS(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     Bool.canonical(),
                     [Expr::canonical(expr.lhs()), Expr::canonical(expr.rhs())],
                     |dest, [lhs, rhs]| vec![Insn::CmpNe { dest, lhs, rhs }],
@@ -1232,7 +1373,7 @@ impl Compiler {
                 .into(),
             ExprEnum::CastUIntToUInt(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.arg())],
                     |dest, [src]| {
@@ -1244,10 +1385,23 @@ impl Compiler {
                     },
                 )
                 .into(),
-            ExprEnum::CastUIntToSInt(expr) => todo!(),
+            ExprEnum::CastUIntToSInt(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| {
+                        vec![Insn::CastToSInt {
+                            dest,
+                            src,
+                            dest_width: expr.ty().width(),
+                        }]
+                    },
+                )
+                .into(),
             ExprEnum::CastSIntToUInt(expr) => self
                 .simple_nary_big_expr(
-                    conditions,
+                    instantiated_module,
                     expr.ty().canonical(),
                     [Expr::canonical(expr.arg())],
                     |dest, [src]| {
@@ -1259,7 +1413,20 @@ impl Compiler {
                     },
                 )
                 .into(),
-            ExprEnum::CastSIntToSInt(expr) => todo!(),
+            ExprEnum::CastSIntToSInt(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    expr.ty().canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| {
+                        vec![Insn::CastToSInt {
+                            dest,
+                            src,
+                            dest_width: expr.ty().width(),
+                        }]
+                    },
+                )
+                .into(),
             ExprEnum::CastBoolToUInt(expr) => cast_bit(Expr::canonical(expr.arg())),
             ExprEnum::CastBoolToSInt(expr) => cast_bit(Expr::canonical(expr.arg())),
             ExprEnum::CastUIntToBool(expr) => cast_bit(Expr::canonical(expr.arg())),
@@ -1287,34 +1454,190 @@ impl Compiler {
             ExprEnum::CastClockToBool(expr) => cast_bit(Expr::canonical(expr.arg())),
             ExprEnum::CastClockToUInt(expr) => cast_bit(Expr::canonical(expr.arg())),
             ExprEnum::CastClockToSInt(expr) => cast_bit(Expr::canonical(expr.arg())),
-            ExprEnum::FieldAccess(expr) => todo!(),
+            ExprEnum::FieldAccess(expr) => self
+                .compile_expr(instantiated_module, Expr::canonical(expr.base()))
+                .map_ty(Bundle::from_canonical)
+                .field_by_index(expr.field_index()),
             ExprEnum::VariantAccess(expr) => todo!(),
-            ExprEnum::ArrayIndex(expr) => todo!(),
+            ExprEnum::ArrayIndex(expr) => self
+                .compile_expr(instantiated_module, Expr::canonical(expr.base()))
+                .map_ty(Array::from_canonical)
+                .element(expr.element_index()),
             ExprEnum::DynArrayIndex(expr) => todo!(),
-            ExprEnum::ReduceBitAndU(expr) => todo!(),
-            ExprEnum::ReduceBitAndS(expr) => todo!(),
-            ExprEnum::ReduceBitOrU(expr) => todo!(),
-            ExprEnum::ReduceBitOrS(expr) => todo!(),
-            ExprEnum::ReduceBitXorU(expr) => todo!(),
-            ExprEnum::ReduceBitXorS(expr) => todo!(),
+            ExprEnum::ReduceBitAndU(expr) => if Expr::ty(expr.arg()).width() == 0 {
+                self.compile_expr(instantiated_module, Expr::canonical(true.to_expr()))
+            } else {
+                self.compile_expr(
+                    instantiated_module,
+                    Expr::canonical(
+                        expr.arg()
+                            .cmp_eq(Expr::ty(expr.arg()).from_int_wrapping(-1)),
+                    ),
+                )
+            }
+            .into(),
+            ExprEnum::ReduceBitAndS(expr) => if Expr::ty(expr.arg()).width() == 0 {
+                self.compile_expr(instantiated_module, Expr::canonical(true.to_expr()))
+            } else {
+                self.compile_expr(
+                    instantiated_module,
+                    Expr::canonical(
+                        expr.arg()
+                            .cmp_eq(Expr::ty(expr.arg()).from_int_wrapping(-1)),
+                    ),
+                )
+            }
+            .into(),
+            ExprEnum::ReduceBitOrU(expr) => if Expr::ty(expr.arg()).width() == 0 {
+                self.compile_expr(instantiated_module, Expr::canonical(false.to_expr()))
+            } else {
+                self.compile_expr(
+                    instantiated_module,
+                    Expr::canonical(expr.arg().cmp_ne(Expr::ty(expr.arg()).from_int_wrapping(0))),
+                )
+            }
+            .into(),
+            ExprEnum::ReduceBitOrS(expr) => if Expr::ty(expr.arg()).width() == 0 {
+                self.compile_expr(instantiated_module, Expr::canonical(false.to_expr()))
+            } else {
+                self.compile_expr(
+                    instantiated_module,
+                    Expr::canonical(expr.arg().cmp_ne(Expr::ty(expr.arg()).from_int_wrapping(0))),
+                )
+            }
+            .into(),
+            ExprEnum::ReduceBitXorU(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    UInt::<1>::TYPE.canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| {
+                        vec![Insn::ReduceBitXor {
+                            dest,
+                            src,
+                            input_width: Expr::ty(expr.arg()).width(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::ReduceBitXorS(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    UInt::<1>::TYPE.canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| {
+                        vec![Insn::ReduceBitXor {
+                            dest,
+                            src,
+                            input_width: Expr::ty(expr.arg()).width(),
+                        }]
+                    },
+                )
+                .into(),
             ExprEnum::SliceUInt(expr) => todo!(),
             ExprEnum::SliceSInt(expr) => todo!(),
             ExprEnum::CastToBits(expr) => todo!(),
             ExprEnum::CastBitsTo(expr) => todo!(),
-            ExprEnum::ModuleIO(expr) => todo!(),
-            ExprEnum::Instance(expr) => todo!(),
-            ExprEnum::Wire(expr) => todo!(),
-            ExprEnum::Reg(expr) => todo!(),
-            ExprEnum::MemPort(expr) => todo!(),
+            ExprEnum::ModuleIO(expr) => self
+                .compile_value(TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: expr.into(),
+                })
+                .into(),
+            ExprEnum::Instance(expr) => self
+                .compile_value(TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: expr.into(),
+                })
+                .into(),
+            ExprEnum::Wire(expr) => self
+                .compile_value(TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: expr.into(),
+                })
+                .into(),
+            ExprEnum::Reg(expr) => self
+                .compile_value(TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: expr.into(),
+                })
+                .into(),
+            ExprEnum::MemPort(expr) => self
+                .compile_value(TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: expr.into(),
+                })
+                .into(),
         };
-        self.compiled_exprs.insert((conditions, expr), retval);
+        self.compiled_exprs.insert(expr, retval);
         retval
     }
+    fn compile_simple_connect(
+        &mut self,
+        conditions: Interned<[Cond]>,
+        lhs: CompiledExpr<CanonicalType>,
+        rhs: CompiledValue<CanonicalType>,
+        source_location: SourceLocation,
+    ) {
+        let CompiledExpr {
+            static_part: lhs_static_part,
+            indexes,
+        } = lhs;
+        let (lhs_layout, lhs_range) = lhs_static_part.write();
+        assert!(
+            lhs_layout.ty.is_passive(),
+            "invalid expression passed to compile_simple_connect -- type must be passive",
+        );
+        let TypeIndexRange {
+            small_slots,
+            big_slots,
+        } = lhs_range;
+        self.add_assignment(
+            conditions,
+            small_slots
+                .iter()
+                .zip(rhs.range.small_slots.iter())
+                .map(|(base, src)| {
+                    if indexes.small_slots.is_empty() {
+                        Insn::CopySmall { dest: base, src }
+                    } else {
+                        Insn::WriteSmallIndexed {
+                            dest: StatePartArrayIndexed {
+                                base,
+                                indexes: indexes.small_slots,
+                            },
+                            src,
+                        }
+                    }
+                })
+                .chain(
+                    big_slots
+                        .iter()
+                        .zip(rhs.range.big_slots.iter())
+                        .map(|(base, src)| {
+                            if indexes.big_slots.is_empty() {
+                                Insn::Copy { dest: base, src }
+                            } else {
+                                Insn::WriteIndexed {
+                                    dest: StatePartArrayIndexed {
+                                        base,
+                                        indexes: indexes.big_slots,
+                                    },
+                                    src,
+                                }
+                            }
+                        }),
+                ),
+            source_location,
+        );
+    }
     fn compile_connect(
         &mut self,
-        parent_module: Interned<InstantiatedModule>,
-        conditions: Interned<[Cond]>,
+        lhs_instantiated_module: InstantiatedModule,
+        lhs_conditions: Interned<[Cond]>,
         lhs: Expr<CanonicalType>,
+        rhs_instantiated_module: InstantiatedModule,
+        rhs_conditions: Interned<[Cond]>,
         mut rhs: Expr<CanonicalType>,
         source_location: SourceLocation,
     ) {
@@ -1336,9 +1659,11 @@ impl Compiler {
                     let rhs = Expr::<Array>::from_canonical(rhs);
                     for index in 0..lhs_ty.len() {
                         self.compile_connect(
-                            parent_module,
-                            conditions,
+                            lhs_instantiated_module,
+                            lhs_conditions,
                             lhs[index],
+                            rhs_instantiated_module,
+                            rhs_conditions,
                             rhs[index],
                             source_location,
                         );
@@ -1372,20 +1697,30 @@ impl Compiler {
                     {
                         assert_eq!(name, rhs_field.name);
                         assert_eq!(flipped, rhs_field.flipped);
-                        let mut lhs_expr =
-                            crate::expr::ops::FieldAccess::new_by_index(lhs, field_index).to_expr();
-                        let mut rhs_expr =
-                            crate::expr::ops::FieldAccess::new_by_index(rhs, field_index).to_expr();
+                        let lhs_expr = ops::FieldAccess::new_by_index(lhs, field_index).to_expr();
+                        let rhs_expr = ops::FieldAccess::new_by_index(rhs, field_index).to_expr();
                         if flipped {
-                            mem::swap(&mut lhs_expr, &mut rhs_expr);
+                            // swap lhs/rhs
+                            self.compile_connect(
+                                rhs_instantiated_module,
+                                rhs_conditions,
+                                rhs_expr,
+                                lhs_instantiated_module,
+                                lhs_conditions,
+                                lhs_expr,
+                                source_location,
+                            );
+                        } else {
+                            self.compile_connect(
+                                lhs_instantiated_module,
+                                lhs_conditions,
+                                lhs_expr,
+                                rhs_instantiated_module,
+                                rhs_conditions,
+                                rhs_expr,
+                                source_location,
+                            );
                         }
-                        self.compile_connect(
-                            parent_module,
-                            conditions,
-                            lhs_expr,
-                            rhs_expr,
-                            source_location,
-                        );
                     }
                     return;
                 }
@@ -1395,10 +1730,93 @@ impl Compiler {
                 CanonicalType::Clock(_) => unreachable!(),
             }
         }
-        let lhs = self.compile_expr(conditions, lhs);
-        let rhs = self.compile_expr(conditions, rhs);
-        let rhs = self.compiled_expr_to_value(conditions, rhs);
-        todo!();
+        let Some(target) = lhs.target() else {
+            unreachable!("connect lhs must have target");
+        };
+        let lhs_decl_conditions = self.decl_conditions[&TargetInInstantiatedModule {
+            instantiated_module: lhs_instantiated_module,
+            target: target.base().into(),
+        }];
+        let lhs = self.compile_expr(lhs_instantiated_module, lhs);
+        let rhs = self.compile_expr(rhs_instantiated_module, rhs);
+        let rhs = self.compiled_expr_to_value(rhs, source_location);
+        self.compile_simple_connect(
+            lhs_conditions[lhs_decl_conditions.len()..].intern(),
+            lhs,
+            rhs,
+            source_location,
+        );
+    }
+    fn compile_declaration(
+        &mut self,
+        declaration: StmtDeclaration,
+        parent_module: Interned<InstantiatedModule>,
+        conditions: Interned<[Cond]>,
+    ) {
+        let target_base: TargetBase = match &declaration {
+            StmtDeclaration::Wire(v) => v.wire.into(),
+            StmtDeclaration::Reg(v) => v.reg.into(),
+            StmtDeclaration::Instance(v) => v.instance.into(),
+        };
+        let target = TargetInInstantiatedModule {
+            instantiated_module: *parent_module,
+            target: target_base.into(),
+        };
+        self.decl_conditions.insert(target, conditions);
+        self.compile_value(target);
+        match declaration {
+            StmtDeclaration::Wire(StmtWire { annotations, wire }) => {}
+            StmtDeclaration::Reg(StmtReg { annotations, reg }) => {
+                todo!();
+            }
+            StmtDeclaration::Instance(StmtInstance {
+                annotations,
+                instance,
+            }) => {
+                let inner_instantiated_module = InstantiatedModule::Child {
+                    parent: parent_module,
+                    instance: instance.intern_sized(),
+                }
+                .intern_sized();
+                let instance_expr = instance.to_expr();
+                self.compile_module(inner_instantiated_module);
+                for (field_index, module_io) in
+                    instance.instantiated().module_io().into_iter().enumerate()
+                {
+                    let instance_field =
+                        ops::FieldAccess::new_by_index(instance_expr, field_index).to_expr();
+                    match Expr::flow(instance_field) {
+                        Flow::Source => {
+                            // we need to supply the value to the instance since the
+                            // parent module expects to read from the instance
+                            self.compile_connect(
+                                *parent_module,
+                                conditions,
+                                instance_field,
+                                *inner_instantiated_module,
+                                Interned::default(),
+                                module_io.module_io.to_expr(),
+                                instance.source_location(),
+                            );
+                        }
+                        Flow::Sink => {
+                            // we need to take the value from the instance since the
+                            // parent module expects to write to the instance
+                            self.compile_connect(
+                                *inner_instantiated_module,
+                                Interned::default(),
+                                module_io.module_io.to_expr(),
+                                *parent_module,
+                                conditions,
+                                instance_field,
+                                instance.source_location(),
+                            );
+                        }
+                        Flow::Duplex => unreachable!(),
+                    }
+                }
+            }
+        }
     }
     fn compile_block(
         &mut self,
@@ -1416,22 +1834,23 @@ impl Compiler {
                     lhs,
                     rhs,
                     source_location,
-                }) => self.compile_connect(parent_module, conditions, lhs, rhs, source_location),
-                Stmt::Formal(StmtFormal {
-                    kind,
-                    clk,
-                    pred,
-                    en,
-                    text,
+                }) => self.compile_connect(
+                    *parent_module,
+                    conditions,
+                    lhs,
+                    *parent_module,
+                    conditions,
+                    rhs,
                     source_location,
-                }) => todo!("implement simulating formal statements"),
+                ),
+                Stmt::Formal(StmtFormal { .. }) => todo!("implement simulating formal statements"),
                 Stmt::If(StmtIf {
                     cond,
                     source_location,
                     blocks: [then_block, else_block],
                 }) => {
                     let cond = self
-                        .compile_expr(conditions, Expr::canonical(cond))
+                        .compile_expr(*parent_module, Expr::canonical(cond))
                         .map_ty(Bool::from_canonical);
                     self.compile_block(
                         parent_module,
@@ -1456,7 +1875,7 @@ impl Compiler {
                     blocks,
                 }) => {
                     let enum_expr = self
-                        .compile_expr(conditions, Expr::canonical(expr))
+                        .compile_expr(*parent_module, Expr::canonical(expr))
                         .map_ty(Enum::from_canonical);
                     for (variant_index, block) in blocks.into_iter().enumerate() {
                         self.compile_block(
@@ -1472,55 +1891,9 @@ impl Compiler {
                         );
                     }
                 }
-                Stmt::Declaration(declaration) => match declaration {
-                    StmtDeclaration::Wire(StmtWire { annotations, wire }) => {
-                        self.compile_value(TargetInInstantiatedModule {
-                            instantiated_module: *parent_module,
-                            target: wire.into(),
-                        });
-                    }
-                    StmtDeclaration::Reg(StmtReg { annotations, reg }) => {
-                        self.compile_value(TargetInInstantiatedModule {
-                            instantiated_module: *parent_module,
-                            target: reg.into(),
-                        });
-                        todo!();
-                    }
-                    StmtDeclaration::Instance(StmtInstance {
-                        annotations,
-                        instance,
-                    }) => {
-                        let CompiledValue {
-                            layout:
-                                CompiledTypeLayout {
-                                    ty: value_ty,
-                                    layout: ty_layout,
-                                    body: CompiledTypeLayoutBody::Bundle { fields },
-                                },
-                            range: value_range,
-                            write: None,
-                        } = self.compile_value(TargetInInstantiatedModule {
-                            instantiated_module: *parent_module,
-                            target: instance.into(),
-                        })
-                        else {
-                            unreachable!();
-                        };
-                        let CompiledModule { module_io } = *self.compile_module(
-                            InstantiatedModule::Child {
-                                parent: parent_module,
-                                instance: instance.intern_sized(),
-                            }
-                            .intern_sized(),
-                        );
-                        for (module_io, CompiledBundleField { offset, ty }) in
-                            module_io.into_iter().zip(fields)
-                        {
-                            todo!();
-                        }
-                        todo!()
-                    }
-                },
+                Stmt::Declaration(declaration) => {
+                    self.compile_declaration(declaration, parent_module, conditions);
+                }
             }
         }
     }
@@ -1556,7 +1929,7 @@ impl Compiler {
     }
     pub fn compile(mut self) -> Compiled {
         self.compile_module(InstantiatedModule::Base(self.base_module).intern_sized());
-
+        todo!("handle self.slots_assignments");
         Compiled {
             insns: Insns::from(self.insns).intern_sized(),
             modules: self.modules,
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index 8fc9038..e89628c 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -109,6 +109,8 @@ insn_field_enum! {
     pub(crate) enum InsnFieldType<Transform: InsnFieldTypeTransform> {
         SmallSlot(Transform::Type<StatePartIndex<StatePartKindSmallSlots>>),
         BigSlot(Transform::Type<StatePartIndex<StatePartKindBigSlots>>),
+        SmallSlotArrayIndexed(Transform::Type<StatePartArrayIndexed<StatePartKindSmallSlots>>),
+        BigSlotArrayIndexed(Transform::Type<StatePartArrayIndexed<StatePartKindBigSlots>>),
         SmallUInt(Transform::Type<SmallUInt>),
         SmallSInt(Transform::Type<SmallSInt>),
         InternedBigInt(Transform::Type<Interned<BigInt>>),
@@ -787,6 +789,167 @@ macro_rules! make_state_part_kinds {
                 *self.orig_pc = self.pc;
             }
         }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+        pub(crate) struct TypeArrayIndexes {
+            $(pub(crate) $type_field: Interned<[StatePartArrayIndex<$TypeKind>]>,)*
+        }
+
+        impl TypeArrayIndexes {
+            pub(crate) fn as_ref(&self) -> TypeArrayIndexesRef<'_> {
+                TypeArrayIndexesRef {
+                    $($type_field: &self.$type_field,)*
+                }
+            }
+            #[must_use]
+            pub(crate) fn join(self, next: TypeArrayIndex) -> TypeArrayIndexes {
+                TypeArrayIndexes {
+                    $($type_field: Interned::from_iter(self.$type_field.iter().copied().chain([next.$type_field])),)*
+                }
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct TypeArrayIndex {
+            $(pub(crate) $type_field: StatePartArrayIndex<$TypeKind>,)*
+        }
+
+        impl TypeArrayIndex {
+            pub(crate) fn from_parts(index: StatePartIndex<StatePartKindSmallSlots>, len: usize, stride: TypeLen) -> Self {
+                Self {
+                    $($type_field: StatePartArrayIndex {
+                        index,
+                        len,
+                        stride: stride.$type_field,
+                    },)*
+                }
+            }
+            pub(crate) fn len(self) -> usize {
+                let len = self.small_slots.len;
+                $(assert_eq!(self.$type_field.len, len, "array length mismatch");)*
+                len
+            }
+            pub(crate) fn index(self) -> StatePartIndex<StatePartKindSmallSlots> {
+                let index = self.small_slots.index;
+                $(assert_eq!(self.$type_field.index, index, "array index mismatch");)*
+                index
+            }
+            pub(crate) fn is_empty(self) -> bool {
+                self.len() == 0
+            }
+            pub(crate) fn stride(self) -> TypeLen {
+                TypeLen {
+                    $($type_field: self.$type_field.stride,)*
+                }
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+        pub(crate) struct TypeArrayIndexesRef<'a> {
+            $(pub(crate) $type_field: &'a [StatePartArrayIndex<$TypeKind>],)*
+        }
+
+        impl<'a> TypeArrayIndexesRef<'a> {
+            pub(crate) fn len(self) -> usize {
+                let len = self.small_slots.len();
+                $(assert_eq!(self.$type_field.len(), len, "indexes count mismatch");)*
+                len
+            }
+            pub(crate) fn is_empty(self) -> bool {
+                self.len() == 0
+            }
+            pub(crate) fn iter(self) -> impl Iterator<Item = TypeArrayIndex> + 'a {
+                (0..self.len()).map(move |i| TypeArrayIndex {
+                    $($type_field: self.$type_field[i],)*
+                })
+            }
+            pub(crate) fn for_each_offset(
+                self,
+                mut f: impl FnMut(TypeIndex),
+            ) {
+                self.for_each_offset2(TypeIndex {
+                    $($type_field: StatePartIndex {
+                        value: 0,
+                        _phantom: PhantomData,
+                    },)*
+                }, &mut f);
+            }
+            pub(crate) fn split_first(self) -> Option<(TypeArrayIndex, Self)> {
+                $(let $type_field = self.$type_field.split_first()?;)*
+                let next = TypeArrayIndex {
+                    $($type_field: *$type_field.0,)*
+                };
+                let rest = TypeArrayIndexesRef {
+                    $($type_field: $type_field.1,)*
+                };
+                Some((next, rest))
+            }
+            pub(crate) fn for_each_offset2(
+                self,
+                base_offset: TypeIndex,
+                f: &mut (impl FnMut(TypeIndex) + ?Sized),
+            ) {
+                if let Some((next, rest)) = self.split_first() {
+                    let stride = next.stride();
+                    for index in 0..next.len().try_into().expect("array too big") {
+                        let mut offset = TypeIndex {
+                            $($type_field: StatePartIndex {
+                                value: stride
+                                    .$type_field
+                                    .value
+                                    .checked_mul(index)
+                                    .expect("array too big"),
+                                _phantom: PhantomData,
+                            },)*
+                        };
+                        $(offset.$type_field.value =
+                            base_offset
+                                .$type_field
+                                .value
+                                .checked_add(offset.$type_field.value)
+                                .expect("array too big");)*
+                        rest.for_each_offset2(offset, f);
+                    }
+                } else {
+                    $(assert!(self.$type_field.is_empty(), "indexes count mismatch");)*
+                    f(base_offset);
+                }
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub(crate) struct TypeArrayIndexed {
+            $(pub(crate) $type_field: StatePartArrayIndexed<$TypeKind>,)*
+        }
+
+        impl TypeArrayIndexed {
+            pub(crate) fn from_parts(base: TypeIndex, indexes: TypeArrayIndexes) -> Self {
+                Self {
+                    $($type_field: StatePartArrayIndexed {
+                        base: base.$type_field,
+                        indexes: indexes.$type_field,
+                    },)*
+                }
+            }
+            pub(crate) fn base(self) -> TypeIndex {
+                TypeIndex {
+                    $($type_field: self.$type_field.base,)*
+                }
+            }
+            pub(crate) fn indexes(self) -> TypeArrayIndexes {
+                TypeArrayIndexes {
+                    $($type_field: self.$type_field.indexes,)*
+                }
+            }
+        }
+
+        impl From<TypeIndex> for TypeArrayIndexed {
+            fn from(value: TypeIndex) -> Self {
+                TypeArrayIndexed {
+                    $($type_field: value.$type_field.into(),)*
+                }
+            }
+        }
     };
 }
 
@@ -933,6 +1096,12 @@ impl SlotDebugData {
             ty: self.ty,
         }
     }
+    pub(crate) fn with_anonymized_debug_info(&self) -> Self {
+        Self {
+            name: Interned::default(),
+            ty: self.ty,
+        }
+    }
 }
 
 impl<K: StatePartKind<DebugData = SlotDebugData>, BK: InsnsBuildingKind> StatePartLayout<K, BK> {
@@ -946,6 +1115,16 @@ impl<K: StatePartKind<DebugData = SlotDebugData>, BK: InsnsBuildingKind> StatePa
             _phantom: PhantomData,
         }
     }
+    pub(crate) fn with_anonymized_debug_info(&self) -> Self {
+        Self {
+            debug_data: self
+                .debug_data
+                .iter()
+                .map(|v| v.with_anonymized_debug_info())
+                .collect(),
+            _phantom: PhantomData,
+        }
+    }
 }
 
 impl<BK: InsnsBuildingKind> TypeLayout<BK> {
@@ -955,6 +1134,63 @@ impl<BK: InsnsBuildingKind> TypeLayout<BK> {
             big_slots: self.big_slots.with_prefixed_debug_names(prefix),
         }
     }
+    pub(crate) fn with_anonymized_debug_info(&self) -> Self {
+        Self {
+            small_slots: self.small_slots.with_anonymized_debug_info(),
+            big_slots: self.big_slots.with_anonymized_debug_info(),
+        }
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct StatePartArrayIndex<K: StatePartKind> {
+    pub(crate) index: StatePartIndex<StatePartKindSmallSlots>,
+    pub(crate) len: usize,
+    pub(crate) stride: StatePartLen<K>,
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct StatePartArrayIndexed<K: StatePartKind> {
+    pub(crate) base: StatePartIndex<K>,
+    pub(crate) indexes: Interned<[StatePartArrayIndex<K>]>,
+}
+
+impl<K: StatePartKind> From<StatePartIndex<K>> for StatePartArrayIndexed<K> {
+    fn from(base: StatePartIndex<K>) -> Self {
+        Self {
+            base,
+            indexes: Interned::default(),
+        }
+    }
+}
+
+impl<K: StatePartKind> StatePartArrayIndexed<K> {
+    pub(crate) fn for_each_target2(
+        base: StatePartIndex<K>,
+        indexes: &[StatePartArrayIndex<K>],
+        f: &mut (impl FnMut(StatePartIndex<K>) + ?Sized),
+    ) {
+        if let [next, rest @ ..] = indexes {
+            for i in 0..next.len.try_into().expect("array too big") {
+                Self::for_each_target2(
+                    StatePartIndex {
+                        value: base
+                            .value
+                            .checked_add(next.stride.value.checked_mul(i).expect("array too big"))
+                            .expect("array too big"),
+                        _phantom: PhantomData,
+                    },
+                    rest,
+                    f,
+                );
+            }
+        } else {
+            f(base);
+        }
+    }
+    pub(crate) fn for_each_target(self, mut f: impl FnMut(StatePartIndex<K>)) {
+        Self::for_each_target2(self.base, &self.indexes, &mut f);
+    }
 }
 
 #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
@@ -1435,6 +1671,26 @@ impl State {
     }
 }
 
+impl BorrowedState<'_> {
+    fn eval_array_indexed<K: StatePartKind>(
+        &self,
+        array_indexed: StatePartArrayIndexed<K>,
+    ) -> Option<StatePartIndex<K>> {
+        let StatePartArrayIndexed {
+            base: mut retval,
+            indexes,
+        } = array_indexed;
+        for StatePartArrayIndex { index, len, stride } in indexes {
+            let index = self.small_slots[index];
+            if index >= len as SmallUInt {
+                return None;
+            }
+            retval.value += stride.value * index as u32;
+        }
+        Some(retval)
+    }
+}
+
 fn bigint_pow2(width: usize) -> Interned<BigInt> {
     #[derive(Copy, Clone, PartialEq, Eq, Hash)]
     struct MyMemoize;
@@ -1515,6 +1771,69 @@ impl_insns! {
         }
         next!();
     }
+    CopySmall {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        state.small_slots[dest] = state.small_slots[src];
+        next!();
+    }
+    ReadIndexed {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartArrayIndexed<StatePartKindBigSlots>,
+    } => {
+        if let Some(src) = state.eval_array_indexed(src) {
+            if dest != src {
+                let [dest, src] = state.big_slots.get_many_mut([dest, src]);
+                dest.clone_from(src);
+            }
+        } else {
+            state.big_slots[dest] = BigInt::ZERO;
+        }
+        next!();
+    }
+    ReadSmallIndexed {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        src: StatePartArrayIndexed<StatePartKindSmallSlots>,
+    } => {
+        if let Some(src) = state.eval_array_indexed(src) {
+            state.small_slots[dest] = state.small_slots[src];
+        } else {
+            state.small_slots[dest] = 0;
+        }
+        next!();
+    }
+    WriteIndexed {
+        #[kind = Output]
+        dest: StatePartArrayIndexed<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        if let Some(dest) = state.eval_array_indexed(dest) {
+            if dest != src {
+                let [dest, src] = state.big_slots.get_many_mut([dest, src]);
+                dest.clone_from(src);
+            }
+        }
+        next!();
+    }
+    WriteSmallIndexed {
+        #[kind = Output]
+        dest: StatePartArrayIndexed<StatePartKindSmallSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        if let Some(dest) = state.eval_array_indexed(dest) {
+            state.small_slots[dest] = state.small_slots[src];
+        }
+        next!();
+    }
     CastToSInt {
         #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,
@@ -1792,6 +2111,22 @@ impl_insns! {
         state.big_slots[dest] = value;
         next!();
     }
+    ReduceBitXor {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        input_width: usize,
+    } => {
+        let src = &state.big_slots[src];
+        let src = src & &*bigint_mask(input_width);
+        let value = BigInt::from(
+            src.to_biguint().expect("known to be non-negative").count_ones() % 2,
+        );
+        state.big_slots[dest] = value;
+        next!();
+    }
     Const {
         #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,

From a6e40839ac64d751e807b28e89ef11bd2f956b40 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 13 Nov 2024 04:14:04 -0800
Subject: [PATCH 086/190] simulator WIP: use petgraph for topological sort over
 assignments

---
 Cargo.lock                             |  17 +
 Cargo.toml                             |   1 +
 crates/fayalite/Cargo.toml             |   1 +
 crates/fayalite/src/sim.rs             | 959 +++++++++++++++++++++----
 crates/fayalite/src/sim/interpreter.rs |  54 +-
 5 files changed, 887 insertions(+), 145 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index c280158..c768882 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -315,6 +315,7 @@ dependencies = [
  "num-bigint",
  "num-traits",
  "os_pipe",
+ "petgraph",
  "serde",
  "serde_json",
  "tempfile",
@@ -358,6 +359,12 @@ dependencies = [
  "thiserror",
 ]
 
+[[package]]
+name = "fixedbitset"
+version = "0.4.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0ce7134b9999ecaf8bcd65542e436736ef32ddca1b3e06094cb6ec5755203b80"
+
 [[package]]
 name = "funty"
 version = "2.0.0"
@@ -515,6 +522,16 @@ dependencies = [
  "windows-sys 0.59.0",
 ]
 
+[[package]]
+name = "petgraph"
+version = "0.6.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b4c5cc86750666a3ed20bdaf5ca2a0344f9c67674cae0515bec2da16fbaa47db"
+dependencies = [
+ "fixedbitset",
+ "indexmap",
+]
+
 [[package]]
 name = "prettyplease"
 version = "0.2.20"
diff --git a/Cargo.toml b/Cargo.toml
index add4bfe..a9cc312 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -29,6 +29,7 @@ jobslot = "0.2.19"
 num-bigint = "0.4.6"
 num-traits = "0.2.16"
 os_pipe = "1.2.1"
+petgraph = "0.6.5"
 prettyplease = "0.2.20"
 proc-macro2 = "1.0.83"
 quote = "1.0.36"
diff --git a/crates/fayalite/Cargo.toml b/crates/fayalite/Cargo.toml
index 8e90a74..2652792 100644
--- a/crates/fayalite/Cargo.toml
+++ b/crates/fayalite/Cargo.toml
@@ -25,6 +25,7 @@ jobslot.workspace = true
 num-bigint.workspace = true
 num-traits.workspace = true
 os_pipe.workspace = true
+petgraph.workspace = true
 serde_json.workspace = true
 serde.workspace = true
 tempfile.workspace = true
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 8dc087b..b647302 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -21,16 +21,19 @@ use crate::{
     prelude::*,
     sim::interpreter::{
         Insn, InsnField, InsnFieldKind, InsnFieldType, Insns, InsnsBuilding, InsnsBuildingDone,
-        SlotDebugData, StatePartArrayIndex, StatePartArrayIndexed, StatePartIndex,
-        StatePartIndexMap, StatePartIndexRange, StatePartKind, StatePartKindBigSlots,
-        StatePartKindSmallSlots, StatePartLayout, StatePartsValue, TypeArrayIndex,
-        TypeArrayIndexes, TypeIndex, TypeIndexRange, TypeLayout, TypeParts,
+        SlotDebugData, SmallUInt, StatePartArrayIndex, StatePartArrayIndexed, StatePartIndex,
+        StatePartIndexRange, StatePartKind, StatePartKindBigSlots, StatePartKindSmallSlots,
+        StatePartLayout, StatePartLen, StatePartsValue, TypeArrayIndex, TypeArrayIndexes,
+        TypeIndex, TypeIndexRange, TypeLayout, TypeLen, TypeParts,
     },
     ty::StaticType,
 };
 use hashbrown::HashMap;
 use num_bigint::BigInt;
-use std::{collections::BTreeSet, fmt};
+use petgraph::visit::{
+    GraphBase, IntoNeighbors, IntoNeighborsDirected, IntoNodeIdentifiers, VisitMap, Visitable,
+};
+use std::{collections::BTreeSet, fmt, marker::PhantomData, mem, ops::IndexMut};
 
 mod interpreter;
 
@@ -416,6 +419,385 @@ impl CompiledExpr<Array> {
     }
 }
 
+#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
+enum AssignmentOrSlotIndex {
+    AssignmentIndex(usize),
+    SmallSlots(StatePartIndex<StatePartKindSmallSlots>),
+    BigSlots(StatePartIndex<StatePartKindBigSlots>),
+}
+
+#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
+enum AssignmentIO {
+    BigInput {
+        assignment_index: usize,
+        slot: StatePartIndex<StatePartKindBigSlots>,
+    },
+    SmallInput {
+        assignment_index: usize,
+        slot: StatePartIndex<StatePartKindSmallSlots>,
+    },
+    BigOutput {
+        assignment_index: usize,
+        slot: StatePartIndex<StatePartKindBigSlots>,
+    },
+    SmallOutput {
+        assignment_index: usize,
+        slot: StatePartIndex<StatePartKindSmallSlots>,
+    },
+}
+
+#[derive(Debug, Default)]
+struct Assignments {
+    assignments: Vec<Assignment>,
+    slot_readers: Option<SlotToAssignmentIndexFullMap>,
+    slot_writers: Option<SlotToAssignmentIndexFullMap>,
+}
+
+impl Assignments {
+    fn finalize(&mut self, slots_len: TypeLen) {
+        assert!(
+            self.slot_readers.is_none() && self.slot_writers.is_none(),
+            "already finalized"
+        );
+        let mut slot_readers = SlotToAssignmentIndexFullMap::new(slots_len);
+        let mut slot_writers = SlotToAssignmentIndexFullMap::new(slots_len);
+        for (assignment_index, assignment) in self.assignments.iter().enumerate() {
+            slot_readers
+                .keys_for_assignment(assignment_index)
+                .extend([&assignment.inputs]);
+            slot_writers
+                .keys_for_assignment(assignment_index)
+                .extend([&assignment.outputs]);
+        }
+        self.slot_readers = Some(slot_readers);
+        self.slot_writers = Some(slot_writers);
+    }
+    fn push(&mut self, v: Assignment) {
+        assert!(
+            self.slot_readers.is_none() && self.slot_writers.is_none(),
+            "already finalized"
+        );
+        self.assignments.push(v);
+    }
+    fn slot_readers(&self) -> &SlotToAssignmentIndexFullMap {
+        self.slot_readers
+            .as_ref()
+            .expect("Assignments::finalize should have been called")
+    }
+    fn slot_writers(&self) -> &SlotToAssignmentIndexFullMap {
+        self.slot_writers
+            .as_ref()
+            .expect("Assignments::finalize should have been called")
+    }
+}
+
+impl GraphBase for Assignments {
+    type EdgeId = AssignmentIO;
+    type NodeId = AssignmentOrSlotIndex;
+}
+
+struct AssignmentsNodeIdentifiers {
+    assignment_indexes: std::ops::Range<usize>,
+    small_slots: std::ops::Range<u32>,
+    big_slots: std::ops::Range<u32>,
+}
+
+impl Iterator for AssignmentsNodeIdentifiers {
+    type Item = AssignmentOrSlotIndex;
+    fn next(&mut self) -> Option<Self::Item> {
+        let Self {
+            assignment_indexes,
+            small_slots,
+            big_slots,
+        } = self;
+        assignment_indexes
+            .next()
+            .map(AssignmentOrSlotIndex::AssignmentIndex)
+            .or_else(|| {
+                small_slots.next().map(|value| {
+                    AssignmentOrSlotIndex::SmallSlots(StatePartIndex {
+                        value,
+                        _phantom: PhantomData,
+                    })
+                })
+            })
+            .or_else(|| {
+                big_slots.next().map(|value| {
+                    AssignmentOrSlotIndex::BigSlots(StatePartIndex {
+                        value,
+                        _phantom: PhantomData,
+                    })
+                })
+            })
+    }
+}
+
+impl<'a> IntoNodeIdentifiers for &'a Assignments {
+    type NodeIdentifiers = AssignmentsNodeIdentifiers;
+
+    fn node_identifiers(self) -> Self::NodeIdentifiers {
+        let TypeLen {
+            small_slots,
+            big_slots,
+        } = self.slot_readers().len();
+        AssignmentsNodeIdentifiers {
+            assignment_indexes: 0..self.assignments.len(),
+            small_slots: 0..small_slots.value,
+            big_slots: 0..big_slots.value,
+        }
+    }
+}
+
+enum AssignmentsNeighborsDirected<'a> {
+    AssignmentIndexes(std::slice::Iter<'a, usize>),
+    Slots {
+        small_slots: std::collections::btree_set::Iter<'a, StatePartIndex<StatePartKindSmallSlots>>,
+        big_slots: std::collections::btree_set::Iter<'a, StatePartIndex<StatePartKindBigSlots>>,
+    },
+}
+
+impl Iterator for AssignmentsNeighborsDirected<'_> {
+    type Item = AssignmentOrSlotIndex;
+    fn next(&mut self) -> Option<Self::Item> {
+        match self {
+            AssignmentsNeighborsDirected::AssignmentIndexes(iter) => iter
+                .next()
+                .copied()
+                .map(AssignmentOrSlotIndex::AssignmentIndex),
+            AssignmentsNeighborsDirected::Slots {
+                small_slots,
+                big_slots,
+            } => small_slots
+                .next()
+                .copied()
+                .map(AssignmentOrSlotIndex::SmallSlots)
+                .or_else(|| {
+                    big_slots
+                        .next()
+                        .copied()
+                        .map(AssignmentOrSlotIndex::BigSlots)
+                }),
+        }
+    }
+}
+
+impl<'a> IntoNeighbors for &'a Assignments {
+    type Neighbors = AssignmentsNeighborsDirected<'a>;
+
+    fn neighbors(self, n: Self::NodeId) -> Self::Neighbors {
+        self.neighbors_directed(n, petgraph::Direction::Outgoing)
+    }
+}
+
+impl<'a> IntoNeighborsDirected for &'a Assignments {
+    type NeighborsDirected = AssignmentsNeighborsDirected<'a>;
+
+    fn neighbors_directed(
+        self,
+        n: Self::NodeId,
+        d: petgraph::Direction,
+    ) -> Self::NeighborsDirected {
+        use petgraph::Direction::*;
+        let slot_map = match d {
+            Outgoing => self.slot_readers(),
+            Incoming => self.slot_writers(),
+        };
+        match n {
+            AssignmentOrSlotIndex::AssignmentIndex(assignment_index) => {
+                let assignment = &self.assignments[assignment_index];
+                let SlotSet(TypeParts {
+                    small_slots,
+                    big_slots,
+                }) = match d {
+                    Outgoing => &assignment.outputs,
+                    Incoming => &assignment.inputs,
+                };
+                AssignmentsNeighborsDirected::Slots {
+                    small_slots: small_slots.iter(),
+                    big_slots: big_slots.iter(),
+                }
+            }
+            AssignmentOrSlotIndex::SmallSlots(slot) => {
+                AssignmentsNeighborsDirected::AssignmentIndexes(slot_map[slot].iter())
+            }
+            AssignmentOrSlotIndex::BigSlots(slot) => {
+                AssignmentsNeighborsDirected::AssignmentIndexes(slot_map[slot].iter())
+            }
+        }
+    }
+}
+
+struct AssignmentsVisitMap {
+    assignments: Vec<bool>,
+    slots: DenseSlotSet,
+}
+
+impl VisitMap<AssignmentOrSlotIndex> for AssignmentsVisitMap {
+    fn visit(&mut self, n: AssignmentOrSlotIndex) -> bool {
+        match n {
+            AssignmentOrSlotIndex::AssignmentIndex(assignment_index) => {
+                !mem::replace(&mut self.assignments[assignment_index], true)
+            }
+            AssignmentOrSlotIndex::SmallSlots(slot) => self.slots.insert(slot),
+            AssignmentOrSlotIndex::BigSlots(slot) => self.slots.insert(slot),
+        }
+    }
+
+    fn is_visited(&self, n: &AssignmentOrSlotIndex) -> bool {
+        match *n {
+            AssignmentOrSlotIndex::AssignmentIndex(assignment_index) => {
+                self.assignments[assignment_index]
+            }
+            AssignmentOrSlotIndex::SmallSlots(slot) => self.slots.contains(slot),
+            AssignmentOrSlotIndex::BigSlots(slot) => self.slots.contains(slot),
+        }
+    }
+}
+
+impl Visitable for Assignments {
+    type Map = AssignmentsVisitMap;
+
+    fn visit_map(self: &Self) -> Self::Map {
+        AssignmentsVisitMap {
+            assignments: vec![false; self.assignments.len()],
+            slots: DenseSlotSet::new(self.slot_readers().len()),
+        }
+    }
+
+    fn reset_map(self: &Self, map: &mut Self::Map) {
+        let AssignmentsVisitMap { assignments, slots } = map;
+        assignments.clear();
+        assignments.resize(self.assignments.len(), false);
+        if slots.len() != self.slot_readers().len() {
+            *slots = DenseSlotSet::new(self.slot_readers().len());
+        } else {
+            slots.clear();
+        }
+    }
+}
+
+#[derive(Clone, Debug, PartialEq, Eq, Hash)]
+struct DenseSlotSet(TypeParts<Self>);
+
+impl DenseSlotSet {
+    fn new(len: TypeLen) -> Self {
+        let TypeLen {
+            small_slots,
+            big_slots,
+        } = len;
+        Self(TypeParts {
+            small_slots: vec![false; small_slots.value.try_into().expect("length too big")]
+                .into_boxed_slice(),
+            big_slots: vec![false; big_slots.value.try_into().expect("length too big")]
+                .into_boxed_slice(),
+        })
+    }
+    fn len(&self) -> TypeLen {
+        TypeLen {
+            small_slots: StatePartLen {
+                value: self.0.small_slots.len() as _,
+                _phantom: PhantomData,
+            },
+            big_slots: StatePartLen {
+                value: self.0.big_slots.len() as _,
+                _phantom: PhantomData,
+            },
+        }
+    }
+    fn clear(&mut self) {
+        let Self(TypeParts {
+            small_slots,
+            big_slots,
+        }) = self;
+        small_slots.fill(false);
+        big_slots.fill(false);
+    }
+}
+
+impl StatePartsValue for DenseSlotSet {
+    type Value<K: StatePartKind> = Box<[bool]>;
+}
+
+trait DenseSlotSetMethods<K: StatePartKind>: Extend<StatePartIndex<K>> {
+    fn contains(&self, k: StatePartIndex<K>) -> bool;
+    fn remove(&mut self, k: StatePartIndex<K>) -> bool {
+        self.take(k).is_some()
+    }
+    fn take(&mut self, k: StatePartIndex<K>) -> Option<StatePartIndex<K>>;
+    fn replace(&mut self, k: StatePartIndex<K>) -> Option<StatePartIndex<K>>;
+    fn insert(&mut self, k: StatePartIndex<K>) -> bool {
+        self.replace(k).is_none()
+    }
+}
+
+impl<K: StatePartKind> Extend<StatePartIndex<K>> for DenseSlotSet
+where
+    Self: DenseSlotSetMethods<K>,
+{
+    fn extend<T: IntoIterator<Item = StatePartIndex<K>>>(&mut self, iter: T) {
+        iter.into_iter().for_each(|v| {
+            self.insert(v);
+        });
+    }
+}
+
+impl DenseSlotSetMethods<StatePartKindSmallSlots> for DenseSlotSet {
+    fn contains(&self, k: StatePartIndex<StatePartKindSmallSlots>) -> bool {
+        self.0.small_slots[k.as_usize()]
+    }
+
+    fn take(
+        &mut self,
+        k: StatePartIndex<StatePartKindSmallSlots>,
+    ) -> Option<StatePartIndex<StatePartKindSmallSlots>> {
+        mem::replace(self.0.small_slots.get_mut(k.as_usize())?, false).then_some(k)
+    }
+
+    fn replace(
+        &mut self,
+        k: StatePartIndex<StatePartKindSmallSlots>,
+    ) -> Option<StatePartIndex<StatePartKindSmallSlots>> {
+        mem::replace(&mut self.0.small_slots[k.as_usize()], true).then_some(k)
+    }
+}
+
+impl DenseSlotSetMethods<StatePartKindBigSlots> for DenseSlotSet {
+    fn contains(&self, k: StatePartIndex<StatePartKindBigSlots>) -> bool {
+        self.0.big_slots[k.as_usize()]
+    }
+
+    fn take(
+        &mut self,
+        k: StatePartIndex<StatePartKindBigSlots>,
+    ) -> Option<StatePartIndex<StatePartKindBigSlots>> {
+        mem::replace(self.0.big_slots.get_mut(k.as_usize())?, false).then_some(k)
+    }
+
+    fn replace(
+        &mut self,
+        k: StatePartIndex<StatePartKindBigSlots>,
+    ) -> Option<StatePartIndex<StatePartKindBigSlots>> {
+        mem::replace(&mut self.0.big_slots[k.as_usize()], true).then_some(k)
+    }
+}
+
+#[derive(Clone, Debug, Default, PartialEq, Eq, Hash)]
+struct SlotVec(TypeParts<Self>);
+
+impl SlotVec {
+    fn is_empty(&self) -> bool {
+        let Self(TypeParts {
+            small_slots,
+            big_slots,
+        }) = self;
+        small_slots.is_empty() && big_slots.is_empty()
+    }
+}
+
+impl StatePartsValue for SlotVec {
+    type Value<K: StatePartKind> = Vec<StatePartIndex<K>>;
+}
+
 #[derive(Clone, Debug, Default, PartialEq, Eq, Hash)]
 struct SlotSet(TypeParts<Self>);
 
@@ -427,6 +809,30 @@ impl SlotSet {
         }) = self;
         small_slots.is_empty() && big_slots.is_empty()
     }
+    fn for_each(
+        &self,
+        small_slots_fn: impl FnMut(StatePartIndex<StatePartKindSmallSlots>),
+        big_slots_fn: impl FnMut(StatePartIndex<StatePartKindBigSlots>),
+    ) {
+        let Self(TypeParts {
+            small_slots,
+            big_slots,
+        }) = self;
+        small_slots.iter().copied().for_each(small_slots_fn);
+        big_slots.iter().copied().for_each(big_slots_fn);
+    }
+    fn all(
+        &self,
+        small_slots_fn: impl FnMut(StatePartIndex<StatePartKindSmallSlots>) -> bool,
+        big_slots_fn: impl FnMut(StatePartIndex<StatePartKindBigSlots>) -> bool,
+    ) -> bool {
+        let Self(TypeParts {
+            small_slots,
+            big_slots,
+        }) = self;
+        small_slots.iter().copied().all(small_slots_fn)
+            && big_slots.iter().copied().all(big_slots_fn)
+    }
 }
 
 impl StatePartsValue for SlotSet {
@@ -511,63 +917,221 @@ impl Extend<Cond> for SlotSet {
 #[derive(Debug)]
 struct Assignment {
     inputs: SlotSet,
+    outputs: SlotSet,
     conditions: Interned<[Cond]>,
     insns: Vec<Insn>,
     source_location: SourceLocation,
 }
 
-#[derive(Debug, Default)]
-struct StatePartAssignments<K: StatePartKind> {
-    written_slot_to_assignment_indexes_map: StatePartIndexMap<K, Vec<usize>>,
+#[derive(Debug)]
+struct SlotToAssignmentIndexFullMap(TypeParts<Self>);
+
+impl StatePartsValue for SlotToAssignmentIndexFullMap {
+    type Value<K: StatePartKind> = Box<[Vec<usize>]>;
 }
 
-#[derive(Debug, Default)]
-struct SlotAssignments {
-    assignments: Vec<Assignment>,
-    parts: TypeParts<Self>,
-}
-
-impl SlotAssignments {
-    fn for_assignment(&mut self, assignment_index: usize) -> SlotAssignmentsForAssignment<'_> {
-        SlotAssignmentsForAssignment {
-            parts: &mut self.parts,
+impl SlotToAssignmentIndexFullMap {
+    fn new(len: TypeLen) -> Self {
+        let TypeLen {
+            small_slots,
+            big_slots,
+        } = len;
+        const VEC_NEW: Vec<usize> = Vec::new();
+        Self(TypeParts {
+            small_slots: vec![VEC_NEW; small_slots.value.try_into().expect("length too big")]
+                .into_boxed_slice(),
+            big_slots: vec![VEC_NEW; big_slots.value.try_into().expect("length too big")]
+                .into_boxed_slice(),
+        })
+    }
+    fn len(&self) -> TypeLen {
+        TypeLen {
+            small_slots: StatePartLen {
+                value: self.0.small_slots.len() as _,
+                _phantom: PhantomData,
+            },
+            big_slots: StatePartLen {
+                value: self.0.big_slots.len() as _,
+                _phantom: PhantomData,
+            },
+        }
+    }
+    fn keys_for_assignment(
+        &mut self,
+        assignment_index: usize,
+    ) -> SlotToAssignmentIndexFullMapKeysForAssignment<'_> {
+        SlotToAssignmentIndexFullMapKeysForAssignment {
+            map: self,
             assignment_index,
         }
     }
-}
-
-impl StatePartsValue for SlotAssignments {
-    type Value<K: StatePartKind> = StatePartAssignments<K>;
-}
-
-struct SlotAssignmentsForAssignment<'a> {
-    parts: &'a mut TypeParts<SlotAssignments>,
-    assignment_index: usize,
-}
-
-impl Extend<StatePartIndex<StatePartKindSmallSlots>> for SlotAssignmentsForAssignment<'_> {
-    fn extend<T: IntoIterator<Item = StatePartIndex<StatePartKindSmallSlots>>>(&mut self, iter: T) {
-        iter.into_iter().for_each(|slot| {
-            self.parts
-                .small_slots
-                .written_slot_to_assignment_indexes_map
-                .entry(slot)
-                .or_insert_with(Vec::new)
-                .push(self.assignment_index)
+    fn for_each(
+        &self,
+        mut small_slots_fn: impl FnMut(StatePartIndex<StatePartKindSmallSlots>, &[usize]),
+        mut big_slots_fn: impl FnMut(StatePartIndex<StatePartKindBigSlots>, &[usize]),
+    ) {
+        let Self(TypeParts {
+            small_slots,
+            big_slots,
+        }) = self;
+        small_slots.iter().enumerate().for_each(|(k, v)| {
+            small_slots_fn(
+                StatePartIndex {
+                    value: k as _,
+                    _phantom: PhantomData,
+                },
+                v,
+            )
+        });
+        big_slots.iter().enumerate().for_each(|(k, v)| {
+            big_slots_fn(
+                StatePartIndex {
+                    value: k as _,
+                    _phantom: PhantomData,
+                },
+                v,
+            )
         });
     }
 }
 
-impl Extend<StatePartIndex<StatePartKindBigSlots>> for SlotAssignmentsForAssignment<'_> {
-    fn extend<T: IntoIterator<Item = StatePartIndex<StatePartKindBigSlots>>>(&mut self, iter: T) {
-        iter.into_iter().for_each(|slot| {
-            self.parts
-                .big_slots
-                .written_slot_to_assignment_indexes_map
-                .entry(slot)
-                .or_insert_with(Vec::new)
-                .push(self.assignment_index)
-        });
+impl std::ops::Index<StatePartIndex<StatePartKindSmallSlots>> for SlotToAssignmentIndexFullMap {
+    type Output = Vec<usize>;
+
+    fn index(&self, index: StatePartIndex<StatePartKindSmallSlots>) -> &Self::Output {
+        &self.0.small_slots[index.as_usize()]
+    }
+}
+
+impl std::ops::IndexMut<StatePartIndex<StatePartKindSmallSlots>> for SlotToAssignmentIndexFullMap {
+    fn index_mut(&mut self, index: StatePartIndex<StatePartKindSmallSlots>) -> &mut Self::Output {
+        &mut self.0.small_slots[index.as_usize()]
+    }
+}
+
+impl std::ops::Index<StatePartIndex<StatePartKindBigSlots>> for SlotToAssignmentIndexFullMap {
+    type Output = Vec<usize>;
+
+    fn index(&self, index: StatePartIndex<StatePartKindBigSlots>) -> &Self::Output {
+        &self.0.big_slots[index.as_usize()]
+    }
+}
+
+impl std::ops::IndexMut<StatePartIndex<StatePartKindBigSlots>> for SlotToAssignmentIndexFullMap {
+    fn index_mut(&mut self, index: StatePartIndex<StatePartKindBigSlots>) -> &mut Self::Output {
+        &mut self.0.big_slots[index.as_usize()]
+    }
+}
+
+struct SlotToAssignmentIndexFullMapKeysForAssignment<'a> {
+    map: &'a mut SlotToAssignmentIndexFullMap,
+    assignment_index: usize,
+}
+
+impl<'a, K: StatePartKind> Extend<&'a StatePartIndex<K>>
+    for SlotToAssignmentIndexFullMapKeysForAssignment<'_>
+where
+    Self: Extend<StatePartIndex<K>>,
+{
+    fn extend<T: IntoIterator<Item = &'a StatePartIndex<K>>>(&mut self, iter: T) {
+        self.extend(iter.into_iter().copied());
+    }
+}
+
+impl<K: StatePartKind> Extend<StatePartIndex<K>>
+    for SlotToAssignmentIndexFullMapKeysForAssignment<'_>
+where
+    SlotToAssignmentIndexFullMap: IndexMut<StatePartIndex<K>, Output = Vec<usize>>,
+{
+    fn extend<T: IntoIterator<Item = StatePartIndex<K>>>(&mut self, iter: T) {
+        iter.into_iter()
+            .for_each(|slot| self.map[slot].push(self.assignment_index));
+    }
+}
+
+impl<'a> Extend<&'a SlotSet> for SlotToAssignmentIndexFullMapKeysForAssignment<'_> {
+    fn extend<T: IntoIterator<Item = &'a SlotSet>>(&mut self, iter: T) {
+        iter.into_iter().for_each(
+            |SlotSet(TypeParts {
+                 small_slots,
+                 big_slots,
+             })| {
+                self.extend(small_slots);
+                self.extend(big_slots);
+            },
+        );
+    }
+}
+
+impl Assignment {
+    fn new(
+        conditions: Interned<[Cond]>,
+        insns: Vec<Insn>,
+        source_location: SourceLocation,
+    ) -> Self {
+        let mut inputs = SlotSet::default();
+        let mut outputs = SlotSet::default();
+        for insn in &insns {
+            for InsnField { ty, kind } in insn.fields() {
+                match (kind, ty) {
+                    (InsnFieldKind::Input, InsnFieldType::SmallSlot(&slot)) => {
+                        inputs.extend([slot]);
+                    }
+                    (InsnFieldKind::Input, InsnFieldType::BigSlot(&slot)) => {
+                        inputs.extend([slot]);
+                    }
+                    (
+                        InsnFieldKind::Input,
+                        InsnFieldType::SmallSlotArrayIndexed(&array_indexed),
+                    ) => {
+                        array_indexed.for_each_target(|slot| inputs.extend([slot]));
+                        inputs.extend(array_indexed.indexes);
+                    }
+                    (InsnFieldKind::Input, InsnFieldType::BigSlotArrayIndexed(&array_indexed)) => {
+                        array_indexed.for_each_target(|slot| inputs.extend([slot]));
+                        inputs.extend(array_indexed.indexes);
+                    }
+                    (InsnFieldKind::Output, InsnFieldType::SmallSlot(&slot)) => {
+                        outputs.extend([slot]);
+                    }
+                    (InsnFieldKind::Output, InsnFieldType::BigSlot(&slot)) => {
+                        outputs.extend([slot]);
+                    }
+                    (
+                        InsnFieldKind::Output,
+                        InsnFieldType::SmallSlotArrayIndexed(&array_indexed),
+                    ) => {
+                        array_indexed.for_each_target(|slot| {
+                            outputs.extend([slot]);
+                        });
+                        inputs.extend(array_indexed.indexes);
+                    }
+                    (InsnFieldKind::Output, InsnFieldType::BigSlotArrayIndexed(&array_indexed)) => {
+                        array_indexed.for_each_target(|slot| {
+                            outputs.extend([slot]);
+                        });
+                        inputs.extend(array_indexed.indexes);
+                    }
+                    (
+                        _,
+                        InsnFieldType::SmallUInt(_)
+                        | InsnFieldType::SmallSInt(_)
+                        | InsnFieldType::InternedBigInt(_)
+                        | InsnFieldType::U8(_)
+                        | InsnFieldType::USize(_)
+                        | InsnFieldType::Empty(_),
+                    )
+                    | (InsnFieldKind::Immediate | InsnFieldKind::BranchTarget, _) => {}
+                }
+            }
+        }
+        Self {
+            inputs,
+            outputs,
+            conditions,
+            insns,
+            source_location,
+        }
     }
 }
 
@@ -580,7 +1144,9 @@ pub struct Compiler {
     compiled_exprs: HashMap<Expr<CanonicalType>, CompiledExpr<CanonicalType>>,
     compiled_exprs_to_values: HashMap<CompiledExpr<CanonicalType>, CompiledValue<CanonicalType>>,
     decl_conditions: HashMap<TargetInInstantiatedModule, Interned<[Cond]>>,
-    slots_assignments: SlotAssignments,
+    compiled_values_to_dyn_array_indexes:
+        HashMap<CompiledValue<UInt>, StatePartIndex<StatePartKindSmallSlots>>,
+    assignments: Assignments,
 }
 
 impl Compiler {
@@ -593,7 +1159,8 @@ impl Compiler {
             compiled_exprs: HashMap::new(),
             compiled_exprs_to_values: HashMap::new(),
             decl_conditions: HashMap::new(),
-            slots_assignments: SlotAssignments::default(),
+            compiled_values_to_dyn_array_indexes: HashMap::new(),
+            assignments: Assignments::default(),
         }
     }
     fn compile_value(
@@ -728,74 +1295,8 @@ impl Compiler {
         source_location: SourceLocation,
     ) {
         let insns = Vec::from_iter(insns);
-        let assignment_index = self.slots_assignments.assignments.len();
-        let mut inputs = SlotSet::default();
-        for insn in &insns {
-            for InsnField { ty, kind } in insn.fields() {
-                match (kind, ty) {
-                    (InsnFieldKind::Input, InsnFieldType::SmallSlot(&slot)) => {
-                        inputs.extend([slot]);
-                    }
-                    (InsnFieldKind::Input, InsnFieldType::BigSlot(&slot)) => {
-                        inputs.extend([slot]);
-                    }
-                    (
-                        InsnFieldKind::Input,
-                        InsnFieldType::SmallSlotArrayIndexed(&array_indexed),
-                    ) => {
-                        array_indexed.for_each_target(|slot| inputs.extend([slot]));
-                        inputs.extend(array_indexed.indexes);
-                    }
-                    (InsnFieldKind::Input, InsnFieldType::BigSlotArrayIndexed(&array_indexed)) => {
-                        array_indexed.for_each_target(|slot| inputs.extend([slot]));
-                        inputs.extend(array_indexed.indexes);
-                    }
-                    (InsnFieldKind::Output, InsnFieldType::SmallSlot(&slot)) => self
-                        .slots_assignments
-                        .for_assignment(assignment_index)
-                        .extend([slot]),
-                    (InsnFieldKind::Output, InsnFieldType::BigSlot(&slot)) => self
-                        .slots_assignments
-                        .for_assignment(assignment_index)
-                        .extend([slot]),
-                    (
-                        InsnFieldKind::Output,
-                        InsnFieldType::SmallSlotArrayIndexed(&array_indexed),
-                    ) => {
-                        array_indexed.for_each_target(|slot| {
-                            self.slots_assignments
-                                .for_assignment(assignment_index)
-                                .extend([slot])
-                        });
-                        inputs.extend(array_indexed.indexes);
-                    }
-                    (InsnFieldKind::Output, InsnFieldType::BigSlotArrayIndexed(&array_indexed)) => {
-                        array_indexed.for_each_target(|slot| {
-                            self.slots_assignments
-                                .for_assignment(assignment_index)
-                                .extend([slot])
-                        });
-                        inputs.extend(array_indexed.indexes);
-                    }
-                    (
-                        _,
-                        InsnFieldType::SmallUInt(_)
-                        | InsnFieldType::SmallSInt(_)
-                        | InsnFieldType::InternedBigInt(_)
-                        | InsnFieldType::U8(_)
-                        | InsnFieldType::USize(_)
-                        | InsnFieldType::Empty(_),
-                    )
-                    | (InsnFieldKind::Immediate | InsnFieldKind::BranchTarget, _) => {}
-                }
-            }
-        }
-        self.slots_assignments.assignments.push(Assignment {
-            inputs,
-            conditions,
-            insns,
-            source_location,
-        });
+        self.assignments
+            .push(Assignment::new(conditions, insns, source_location));
     }
     fn simple_nary_big_expr<const N: usize>(
         &mut self,
@@ -839,6 +1340,70 @@ impl Compiler {
         );
         retval
     }
+    fn compiled_value_to_dyn_array_index(
+        &mut self,
+        compiled_value: CompiledValue<UInt>,
+        source_location: SourceLocation,
+    ) -> StatePartIndex<StatePartKindSmallSlots> {
+        if let Some(&retval) = self
+            .compiled_values_to_dyn_array_indexes
+            .get(&compiled_value)
+        {
+            return retval;
+        }
+        let retval = match compiled_value.range.len() {
+            TypeLen {
+                small_slots:
+                    StatePartLen {
+                        value: 1,
+                        _phantom: _,
+                    },
+                big_slots:
+                    StatePartLen {
+                        value: 0,
+                        _phantom: _,
+                    },
+            } => compiled_value.range.small_slots.start,
+            TypeLen {
+                small_slots:
+                    StatePartLen {
+                        value: 0,
+                        _phantom: _,
+                    },
+                big_slots:
+                    StatePartLen {
+                        value: 1,
+                        _phantom: _,
+                    },
+            } => {
+                let debug_data = SlotDebugData {
+                    name: Interned::default(),
+                    ty: UInt::<{ SmallUInt::BITS as usize }>::TYPE.canonical(),
+                };
+                let dest = self
+                    .insns
+                    .allocate_variable(&TypeLayout {
+                        small_slots: StatePartLayout::scalar(debug_data),
+                        big_slots: StatePartLayout::empty(),
+                    })
+                    .small_slots
+                    .start;
+                self.add_assignment(
+                    Interned::default(),
+                    vec![Insn::CastBigToArrayIndex {
+                        dest,
+                        src: compiled_value.range.big_slots.start,
+                    }],
+                    source_location,
+                );
+                dest
+            }
+            _ => unreachable!(),
+        };
+        self.compiled_values_to_dyn_array_indexes
+            .insert(compiled_value, retval);
+        retval
+    }
     fn compile_expr(
         &mut self,
         instantiated_module: InstantiatedModule,
@@ -1463,7 +2028,21 @@ impl Compiler {
                 .compile_expr(instantiated_module, Expr::canonical(expr.base()))
                 .map_ty(Array::from_canonical)
                 .element(expr.element_index()),
-            ExprEnum::DynArrayIndex(expr) => todo!(),
+            ExprEnum::DynArrayIndex(expr) => {
+                let element_index =
+                    self.compile_expr(instantiated_module, Expr::canonical(expr.element_index()));
+                let element_index = self.compiled_expr_to_value(
+                    element_index,
+                    instantiated_module.leaf_module().source_location(),
+                );
+                let index_slot = self.compiled_value_to_dyn_array_index(
+                    element_index.map_ty(UInt::from_canonical),
+                    instantiated_module.leaf_module().source_location(),
+                );
+                self.compile_expr(instantiated_module, Expr::canonical(expr.base()))
+                    .map_ty(Array::from_canonical)
+                    .element_dyn(index_slot)
+            }
             ExprEnum::ReduceBitAndU(expr) => if Expr::ty(expr.arg()).width() == 0 {
                 self.compile_expr(instantiated_module, Expr::canonical(true.to_expr()))
             } else {
@@ -1534,8 +2113,36 @@ impl Compiler {
                     },
                 )
                 .into(),
-            ExprEnum::SliceUInt(expr) => todo!(),
-            ExprEnum::SliceSInt(expr) => todo!(),
+            ExprEnum::SliceUInt(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    UInt::new_dyn(expr.range().len()).canonical(),
+                    [Expr::canonical(expr.base())],
+                    |dest, [src]| {
+                        vec![Insn::SliceInt {
+                            dest,
+                            src,
+                            start: expr.range().start,
+                            len: expr.range().len(),
+                        }]
+                    },
+                )
+                .into(),
+            ExprEnum::SliceSInt(expr) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    UInt::new_dyn(expr.range().len()).canonical(),
+                    [Expr::canonical(expr.base())],
+                    |dest, [src]| {
+                        vec![Insn::SliceInt {
+                            dest,
+                            src,
+                            start: expr.range().start,
+                            len: expr.range().len(),
+                        }]
+                    },
+                )
+                .into(),
             ExprEnum::CastToBits(expr) => todo!(),
             ExprEnum::CastBitsTo(expr) => todo!(),
             ExprEnum::ModuleIO(expr) => self
@@ -1927,34 +2534,104 @@ impl Compiler {
         };
         entry.insert(CompiledModule { module_io })
     }
-    pub fn compile(mut self) -> Compiled {
-        self.compile_module(InstantiatedModule::Base(self.base_module).intern_sized());
-        todo!("handle self.slots_assignments");
+    fn process_assignments(&mut self) {
+        self.assignments
+            .finalize(self.insns.state_layout().len().ty);
+        let assignments_queue: Vec<usize> = match petgraph::algo::toposort(&self.assignments, None)
+        {
+            Ok(nodes) => nodes
+                .into_iter()
+                .filter_map(|n| match n {
+                    AssignmentOrSlotIndex::AssignmentIndex(v) => Some(v),
+                    _ => None,
+                })
+                .collect(),
+            Err(e) => match e.node_id() {
+                AssignmentOrSlotIndex::AssignmentIndex(assignment_index) => panic!(
+                    "combinatorial logic cycle detected at: {}",
+                    self.assignments.assignments[assignment_index].source_location,
+                ),
+                AssignmentOrSlotIndex::SmallSlots(slot) => panic!(
+                    "combinatorial logic cycle detected through: {}",
+                    self.insns.state_layout().ty.small_slots.debug_data[slot.as_usize()].name,
+                ),
+                AssignmentOrSlotIndex::BigSlots(slot) => panic!(
+                    "combinatorial logic cycle detected through: {}",
+                    self.insns.state_layout().ty.big_slots.debug_data[slot.as_usize()].name,
+                ),
+            },
+        };
+        todo!();
+    }
+    pub fn compile(mut self) -> Compiled<Bundle> {
+        let base_module =
+            *self.compile_module(InstantiatedModule::Base(self.base_module).intern_sized());
+        self.process_assignments();
         Compiled {
             insns: Insns::from(self.insns).intern_sized(),
-            modules: self.modules,
+            base_module,
+            base_module_io_ty: self.base_module.io_ty(),
+        }
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+struct CompiledModule {
+    module_io: Interned<[CompiledValue<CanonicalType>]>,
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+pub struct Compiled<T: BundleType> {
+    insns: Interned<Insns<InsnsBuildingDone>>,
+    base_module: CompiledModule,
+    base_module_io_ty: T,
+}
+
+impl<T: BundleType> Compiled<T> {
+    pub fn new(module: Module<T>) -> Self {
+        Self::from_canonical(Compiler::new(module.canonical().intern()).compile())
+    }
+    pub fn canonical(self) -> Compiled<Bundle> {
+        let Self {
+            insns,
+            base_module,
+            base_module_io_ty,
+        } = self;
+        Compiled {
+            insns,
+            base_module,
+            base_module_io_ty: Bundle::from_canonical(base_module_io_ty.canonical()),
+        }
+    }
+    pub fn from_canonical(canonical: Compiled<Bundle>) -> Self {
+        let Compiled {
+            insns,
+            base_module,
+            base_module_io_ty,
+        } = canonical;
+        Self {
+            insns,
+            base_module,
+            base_module_io_ty: T::from_canonical(base_module_io_ty.canonical()),
         }
     }
 }
 
 #[derive(Debug)]
-struct CompiledModule {
-    module_io: Interned<[CompiledValue<CanonicalType>]>,
+pub struct Simulation<T: BundleType> {
+    state: interpreter::State,
+    compiled: Compiled<T>,
 }
 
-#[derive(Debug)]
-pub struct Compiled {
-    insns: Interned<Insns<InsnsBuildingDone>>,
-    modules: HashMap<InstantiatedModule, CompiledModule>,
-}
-
-impl Compiled {
-    pub fn new<T: BundleType>(module: Module<T>) -> Self {
-        Compiler::new(module.canonical().intern()).compile()
+impl<T: BundleType> Simulation<T> {
+    pub fn from_compiled(compiled: Compiled<T>) -> Self {
+        Self {
+            state: interpreter::State::new(compiled.insns),
+            compiled,
+        }
+    }
+    pub fn settle_step(&mut self) {
+        self.state.setup_call(0);
+        self.state.run();
     }
 }
-
-#[derive(Debug)]
-pub struct Simulation {
-    state: interpreter::State,
-}
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index e89628c..5269131 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -362,6 +362,12 @@ pub(crate) struct Insns<BK: InsnsBuildingKind> {
     state_layout: StateLayout<BK>,
 }
 
+impl<BK: InsnsBuildingKind> Insns<BK> {
+    pub(crate) fn state_layout(&self) -> &StateLayout<BK> {
+        &self.state_layout
+    }
+}
+
 struct InsnsDebug<'a> {
     insns: &'a [Insn],
     insn_source_locations: &'a [SourceLocation],
@@ -564,13 +570,13 @@ macro_rules! make_state_part_kinds {
         impl Copy for StateLayout<InsnsBuildingDone> {}
 
         impl<BK: InsnsBuildingKind> StateLayout<BK> {
-            pub(crate) fn len(self) -> StateLen {
+            pub(crate) fn len(&self) -> StateLen {
                 StateLen {
                     ty: self.ty.len(),
                     $($state_field: self.$state_field.len(),)*
                 }
             }
-            pub(crate) fn is_empty(self) -> bool {
+            pub(crate) fn is_empty(&self) -> bool {
                 self.ty.is_empty() $(&& self.$state_field.is_empty())*
             }
             pub(crate) fn empty() -> Self {
@@ -652,12 +658,12 @@ macro_rules! make_state_part_kinds {
         impl Copy for TypeLayout<InsnsBuildingDone> {}
 
         impl<BK: InsnsBuildingKind> TypeLayout<BK> {
-            pub(crate) fn len(self) -> TypeLen {
+            pub(crate) fn len(&self) -> TypeLen {
                 TypeLen {
                     $($type_field: self.$type_field.len(),)*
                 }
             }
-            pub(crate) fn is_empty(self) -> bool {
+            pub(crate) fn is_empty(&self) -> bool {
                 $(self.$type_field.is_empty())&&+
             }
             pub(crate) fn empty() -> Self {
@@ -762,6 +768,14 @@ macro_rules! make_state_part_kinds {
         }
 
         impl State {
+            pub(crate) fn new(insns: Interned<Insns<InsnsBuildingDone>>) -> Self {
+                Self {
+                    insns,
+                    pc: 0,
+                    $($state_field: StatePart::new(insns.state_layout.$state_field.len()),)*
+                    $($type_field: StatePart::new(insns.state_layout.ty.$type_field.len()),)*
+                }
+            }
             pub(crate) fn borrow(&mut self) -> BorrowedState<'_> {
                 BorrowedState {
                     orig_insns: self.insns,
@@ -1494,6 +1508,13 @@ impl<K: StatePartKind, V: fmt::Debug> fmt::Debug for StatePartIndexMap<K, V> {
     }
 }
 
+impl<K: StatePartKind, V> Extend<(StatePartIndex<K>, V)> for StatePartIndexMap<K, V> {
+    fn extend<T: IntoIterator<Item = (StatePartIndex<K>, V)>>(&mut self, iter: T) {
+        self.map
+            .extend(iter.into_iter().map(|(k, v)| (k.as_usize(), v)));
+    }
+}
+
 impl<K: StatePartKind, V> StatePartIndexMap<K, V> {
     pub(crate) fn new() -> Self {
         Self {
@@ -1834,6 +1855,17 @@ impl_insns! {
         }
         next!();
     }
+    CastBigToArrayIndex {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let src = &state.big_slots[src];
+        let value = src.try_into().unwrap_or(SmallUInt::MAX);
+        state.small_slots[dest] = value;
+        next!();
+    }
     CastToSInt {
         #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,
@@ -2055,6 +2087,20 @@ impl_insns! {
         state.big_slots[dest] = value;
         next!();
     }
+    SliceInt {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        start: usize,
+        #[kind = Immediate]
+        len: usize,
+    } => {
+        let value = &state.big_slots[src] >> start;
+        state.big_slots[dest] = value & &*bigint_mask(len);
+        next!();
+    }
     CmpEq {
         #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,

From f54e55a14330d1e10e2b6da13510d77e016850bc Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 13 Nov 2024 21:20:15 -0800
Subject: [PATCH 087/190] Simulation::settle_step() works for simple modules

---
 crates/fayalite/src/sim.rs             | 485 +++++++++++++++--------
 crates/fayalite/src/sim/interpreter.rs | 378 +++++++++++++++++-
 crates/fayalite/tests/sim.rs           | 524 +++++++++++++++++++++++++
 3 files changed, 1221 insertions(+), 166 deletions(-)
 create mode 100644 crates/fayalite/tests/sim.rs

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index b647302..7793dce 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -40,13 +40,13 @@ mod interpreter;
 #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
 enum CondBody {
     IfTrue {
-        cond: CompiledExpr<Bool>,
+        cond: CompiledValue<Bool>,
     },
     IfFalse {
-        cond: CompiledExpr<Bool>,
+        cond: CompiledValue<Bool>,
     },
     MatchArm {
-        enum_expr: CompiledExpr<Enum>,
+        enum_expr: CompiledValue<Enum>,
         variant_index: usize,
     },
 }
@@ -267,8 +267,8 @@ impl<T: Type> CompiledValue<T> {
 }
 
 impl CompiledValue<Enum> {
-    fn add_discriminant_to_set(self, offset: TypeIndex, inputs: &mut SlotSet) {
-        inputs.extend([self.range.offset(offset)]);
+    fn add_discriminant_to_set(self, inputs: &mut SlotSet) {
+        inputs.extend([self.range]);
     }
 }
 
@@ -359,19 +359,6 @@ impl<T: Type> CompiledExpr<T> {
     }
 }
 
-impl CompiledExpr<Enum> {
-    fn add_discriminant_and_indexes_to_set(self, inputs: &mut SlotSet) {
-        let Self {
-            static_part,
-            indexes,
-        } = self;
-        indexes.as_ref().for_each_offset(|offset| {
-            static_part.add_discriminant_to_set(offset, inputs);
-        });
-        inputs.extend(indexes.as_ref().iter());
-    }
-}
-
 impl CompiledExpr<Bundle> {
     fn field_by_index(self, field_index: usize) -> CompiledExpr<CanonicalType> {
         CompiledExpr {
@@ -446,48 +433,118 @@ enum AssignmentIO {
     },
 }
 
-#[derive(Debug, Default)]
-struct Assignments {
-    assignments: Vec<Assignment>,
-    slot_readers: Option<SlotToAssignmentIndexFullMap>,
-    slot_writers: Option<SlotToAssignmentIndexFullMap>,
+#[derive(Debug)]
+enum Assignments {
+    Accumulating {
+        assignments: Vec<Assignment>,
+    },
+    Finalized {
+        assignments: Box<[Assignment]>,
+        slot_readers: SlotToAssignmentIndexFullMap,
+        slot_writers: SlotToAssignmentIndexFullMap,
+        assignment_immediate_predecessors: Box<[Box<[usize]>]>,
+        assignment_immediate_successors: Box<[Box<[usize]>]>,
+    },
+}
+
+impl Default for Assignments {
+    fn default() -> Self {
+        Self::Accumulating {
+            assignments: Vec::new(),
+        }
+    }
 }
 
 impl Assignments {
     fn finalize(&mut self, slots_len: TypeLen) {
-        assert!(
-            self.slot_readers.is_none() && self.slot_writers.is_none(),
-            "already finalized"
-        );
+        let Self::Accumulating { assignments } = self else {
+            unreachable!("already finalized");
+        };
+        let assignments = mem::take(assignments).into_boxed_slice();
         let mut slot_readers = SlotToAssignmentIndexFullMap::new(slots_len);
         let mut slot_writers = SlotToAssignmentIndexFullMap::new(slots_len);
-        for (assignment_index, assignment) in self.assignments.iter().enumerate() {
+        let mut assignment_immediate_predecessors = vec![BTreeSet::new(); assignments.len()];
+        let mut assignment_immediate_successors = vec![BTreeSet::new(); assignments.len()];
+        for (assignment_index, assignment) in assignments.iter().enumerate() {
             slot_readers
                 .keys_for_assignment(assignment_index)
                 .extend([&assignment.inputs]);
-            slot_writers
-                .keys_for_assignment(assignment_index)
-                .extend([&assignment.outputs]);
+            let SlotSet(TypeParts {
+                small_slots,
+                big_slots,
+            }) = &assignment.outputs;
+            for &slot in small_slots {
+                if let Some(&pred) = slot_writers[slot].last() {
+                    assignment_immediate_predecessors[assignment_index].insert(pred);
+                    assignment_immediate_successors[pred].insert(assignment_index);
+                }
+                slot_writers[slot].push(assignment_index);
+            }
+            for &slot in big_slots {
+                if let Some(&pred) = slot_writers[slot].last() {
+                    assignment_immediate_predecessors[assignment_index].insert(pred);
+                    assignment_immediate_successors[pred].insert(assignment_index);
+                }
+                slot_writers[slot].push(assignment_index);
+            }
         }
-        self.slot_readers = Some(slot_readers);
-        self.slot_writers = Some(slot_writers);
+        *self = Self::Finalized {
+            assignments,
+            slot_readers,
+            slot_writers,
+            assignment_immediate_predecessors: assignment_immediate_predecessors
+                .into_iter()
+                .map(Box::from_iter)
+                .collect(),
+            assignment_immediate_successors: assignment_immediate_successors
+                .into_iter()
+                .map(Box::from_iter)
+                .collect(),
+        };
     }
     fn push(&mut self, v: Assignment) {
-        assert!(
-            self.slot_readers.is_none() && self.slot_writers.is_none(),
-            "already finalized"
-        );
-        self.assignments.push(v);
+        let Self::Accumulating { assignments } = self else {
+            unreachable!("already finalized");
+        };
+        assignments.push(v);
+    }
+    fn assignments(&self) -> &[Assignment] {
+        let Self::Finalized { assignments, .. } = self else {
+            unreachable!("Assignments::finalize should have been called");
+        };
+        assignments
     }
     fn slot_readers(&self) -> &SlotToAssignmentIndexFullMap {
-        self.slot_readers
-            .as_ref()
-            .expect("Assignments::finalize should have been called")
+        let Self::Finalized { slot_readers, .. } = self else {
+            unreachable!("Assignments::finalize should have been called");
+        };
+        slot_readers
     }
     fn slot_writers(&self) -> &SlotToAssignmentIndexFullMap {
-        self.slot_writers
-            .as_ref()
-            .expect("Assignments::finalize should have been called")
+        let Self::Finalized { slot_writers, .. } = self else {
+            unreachable!("Assignments::finalize should have been called");
+        };
+        slot_writers
+    }
+    fn assignment_immediate_predecessors(&self) -> &[Box<[usize]>] {
+        let Self::Finalized {
+            assignment_immediate_predecessors,
+            ..
+        } = self
+        else {
+            unreachable!("Assignments::finalize should have been called");
+        };
+        assignment_immediate_predecessors
+    }
+    fn assignment_immediate_successors(&self) -> &[Box<[usize]>] {
+        let Self::Finalized {
+            assignment_immediate_successors,
+            ..
+        } = self
+        else {
+            unreachable!("Assignments::finalize should have been called");
+        };
+        assignment_immediate_successors
     }
 }
 
@@ -541,42 +598,47 @@ impl<'a> IntoNodeIdentifiers for &'a Assignments {
             big_slots,
         } = self.slot_readers().len();
         AssignmentsNodeIdentifiers {
-            assignment_indexes: 0..self.assignments.len(),
+            assignment_indexes: 0..self.assignments().len(),
             small_slots: 0..small_slots.value,
             big_slots: 0..big_slots.value,
         }
     }
 }
 
-enum AssignmentsNeighborsDirected<'a> {
-    AssignmentIndexes(std::slice::Iter<'a, usize>),
-    Slots {
-        small_slots: std::collections::btree_set::Iter<'a, StatePartIndex<StatePartKindSmallSlots>>,
-        big_slots: std::collections::btree_set::Iter<'a, StatePartIndex<StatePartKindBigSlots>>,
-    },
+struct AssignmentsNeighborsDirected<'a> {
+    assignment_indexes: std::slice::Iter<'a, usize>,
+    small_slots: std::collections::btree_set::Iter<'a, StatePartIndex<StatePartKindSmallSlots>>,
+    big_slots: std::collections::btree_set::Iter<'a, StatePartIndex<StatePartKindBigSlots>>,
 }
 
 impl Iterator for AssignmentsNeighborsDirected<'_> {
     type Item = AssignmentOrSlotIndex;
     fn next(&mut self) -> Option<Self::Item> {
-        match self {
-            AssignmentsNeighborsDirected::AssignmentIndexes(iter) => iter
-                .next()
-                .copied()
-                .map(AssignmentOrSlotIndex::AssignmentIndex),
-            AssignmentsNeighborsDirected::Slots {
-                small_slots,
-                big_slots,
-            } => small_slots
-                .next()
-                .copied()
-                .map(AssignmentOrSlotIndex::SmallSlots)
-                .or_else(|| {
-                    big_slots
-                        .next()
-                        .copied()
-                        .map(AssignmentOrSlotIndex::BigSlots)
-                }),
+        let Self {
+            assignment_indexes,
+            small_slots,
+            big_slots,
+        } = self;
+        if let retval @ Some(_) = assignment_indexes
+            .next()
+            .copied()
+            .map(AssignmentOrSlotIndex::AssignmentIndex)
+        {
+            retval
+        } else if let retval @ Some(_) = small_slots
+            .next()
+            .copied()
+            .map(AssignmentOrSlotIndex::SmallSlots)
+        {
+            retval
+        } else if let retval @ Some(_) = big_slots
+            .next()
+            .copied()
+            .map(AssignmentOrSlotIndex::BigSlots)
+        {
+            retval
+        } else {
+            None
         }
     }
 }
@@ -604,25 +666,39 @@ impl<'a> IntoNeighborsDirected for &'a Assignments {
         };
         match n {
             AssignmentOrSlotIndex::AssignmentIndex(assignment_index) => {
-                let assignment = &self.assignments[assignment_index];
-                let SlotSet(TypeParts {
-                    small_slots,
-                    big_slots,
-                }) = match d {
-                    Outgoing => &assignment.outputs,
-                    Incoming => &assignment.inputs,
+                let assignment = &self.assignments()[assignment_index];
+                let (
+                    assignment_indexes,
+                    SlotSet(TypeParts {
+                        small_slots,
+                        big_slots,
+                    }),
+                ) = match d {
+                    Outgoing => (
+                        &self.assignment_immediate_successors()[assignment_index],
+                        &assignment.outputs,
+                    ),
+                    Incoming => (
+                        &self.assignment_immediate_predecessors()[assignment_index],
+                        &assignment.inputs,
+                    ),
                 };
-                AssignmentsNeighborsDirected::Slots {
+                AssignmentsNeighborsDirected {
+                    assignment_indexes: assignment_indexes.iter(),
                     small_slots: small_slots.iter(),
                     big_slots: big_slots.iter(),
                 }
             }
-            AssignmentOrSlotIndex::SmallSlots(slot) => {
-                AssignmentsNeighborsDirected::AssignmentIndexes(slot_map[slot].iter())
-            }
-            AssignmentOrSlotIndex::BigSlots(slot) => {
-                AssignmentsNeighborsDirected::AssignmentIndexes(slot_map[slot].iter())
-            }
+            AssignmentOrSlotIndex::SmallSlots(slot) => AssignmentsNeighborsDirected {
+                assignment_indexes: slot_map[slot].iter(),
+                small_slots: Default::default(),
+                big_slots: Default::default(),
+            },
+            AssignmentOrSlotIndex::BigSlots(slot) => AssignmentsNeighborsDirected {
+                assignment_indexes: slot_map[slot].iter(),
+                small_slots: Default::default(),
+                big_slots: Default::default(),
+            },
         }
     }
 }
@@ -659,7 +735,7 @@ impl Visitable for Assignments {
 
     fn visit_map(self: &Self) -> Self::Map {
         AssignmentsVisitMap {
-            assignments: vec![false; self.assignments.len()],
+            assignments: vec![false; self.assignments().len()],
             slots: DenseSlotSet::new(self.slot_readers().len()),
         }
     }
@@ -667,7 +743,7 @@ impl Visitable for Assignments {
     fn reset_map(self: &Self, map: &mut Self::Map) {
         let AssignmentsVisitMap { assignments, slots } = map;
         assignments.clear();
-        assignments.resize(self.assignments.len(), false);
+        assignments.resize(self.assignments().len(), false);
         if slots.len() != self.slot_readers().len() {
             *slots = DenseSlotSet::new(self.slot_readers().len());
         } else {
@@ -898,12 +974,12 @@ impl Extend<CondBody> for SlotSet {
     fn extend<T: IntoIterator<Item = CondBody>>(&mut self, iter: T) {
         iter.into_iter().for_each(|cond_body| match cond_body {
             CondBody::IfTrue { cond } | CondBody::IfFalse { cond } => {
-                cond.add_target_and_indexes_to_set(self);
+                self.extend([cond.range]);
             }
             CondBody::MatchArm {
                 enum_expr,
-                variant_index,
-            } => enum_expr.add_discriminant_and_indexes_to_set(self),
+                variant_index: _,
+            } => enum_expr.add_discriminant_to_set(self),
         })
     }
 }
@@ -936,11 +1012,10 @@ impl SlotToAssignmentIndexFullMap {
             small_slots,
             big_slots,
         } = len;
-        const VEC_NEW: Vec<usize> = Vec::new();
         Self(TypeParts {
-            small_slots: vec![VEC_NEW; small_slots.value.try_into().expect("length too big")]
+            small_slots: vec![Vec::new(); small_slots.value.try_into().expect("length too big")]
                 .into_boxed_slice(),
-            big_slots: vec![VEC_NEW; big_slots.value.try_into().expect("length too big")]
+            big_slots: vec![Vec::new(); big_slots.value.try_into().expect("length too big")]
                 .into_boxed_slice(),
         })
     }
@@ -1237,54 +1312,51 @@ impl Compiler {
             static_part,
             indexes,
         } = expr;
-        let layout = static_part.layout.with_anonymized_debug_info();
-        let retval = CompiledValue {
-            layout,
-            range: self.insns.allocate_variable(&layout.layout),
-            write: None,
+        let retval = if indexes.as_ref().is_empty() {
+            CompiledValue {
+                layout: static_part.layout,
+                range: static_part.range,
+                write: None,
+            }
+        } else {
+            let layout = static_part.layout.with_anonymized_debug_info();
+            let retval = CompiledValue {
+                layout,
+                range: self.insns.allocate_variable(&layout.layout),
+                write: None,
+            };
+            let TypeIndexRange {
+                small_slots,
+                big_slots,
+            } = retval.range;
+            self.add_assignment(
+                Interned::default(),
+                small_slots
+                    .iter()
+                    .zip(static_part.range.small_slots.iter())
+                    .map(|(dest, base)| Insn::ReadSmallIndexed {
+                        dest,
+                        src: StatePartArrayIndexed {
+                            base,
+                            indexes: indexes.small_slots,
+                        },
+                    })
+                    .chain(
+                        big_slots
+                            .iter()
+                            .zip(static_part.range.big_slots.iter())
+                            .map(|(dest, base)| Insn::ReadIndexed {
+                                dest,
+                                src: StatePartArrayIndexed {
+                                    base,
+                                    indexes: indexes.big_slots,
+                                },
+                            }),
+                    ),
+                source_location,
+            );
+            retval
         };
-        let TypeIndexRange {
-            small_slots,
-            big_slots,
-        } = retval.range;
-        self.add_assignment(
-            Interned::default(),
-            small_slots
-                .iter()
-                .zip(static_part.range.small_slots.iter())
-                .map(|(dest, base)| {
-                    if indexes.small_slots.is_empty() {
-                        Insn::CopySmall { dest, src: base }
-                    } else {
-                        Insn::ReadSmallIndexed {
-                            dest,
-                            src: StatePartArrayIndexed {
-                                base,
-                                indexes: indexes.small_slots,
-                            },
-                        }
-                    }
-                })
-                .chain(
-                    big_slots
-                        .iter()
-                        .zip(static_part.range.big_slots.iter())
-                        .map(|(dest, base)| {
-                            if indexes.big_slots.is_empty() {
-                                Insn::Copy { dest, src: base }
-                            } else {
-                                Insn::ReadIndexed {
-                                    dest,
-                                    src: StatePartArrayIndexed {
-                                        base,
-                                        indexes: indexes.big_slots,
-                                    },
-                                }
-                            }
-                        }),
-                ),
-            source_location,
-        );
         self.compiled_exprs_to_values.insert(expr, retval);
         retval
     }
@@ -2456,9 +2528,9 @@ impl Compiler {
                     source_location,
                     blocks: [then_block, else_block],
                 }) => {
-                    let cond = self
-                        .compile_expr(*parent_module, Expr::canonical(cond))
-                        .map_ty(Bool::from_canonical);
+                    let cond = self.compile_expr(*parent_module, Expr::canonical(cond));
+                    let cond = self.compiled_expr_to_value(cond, source_location);
+                    let cond = cond.map_ty(Bool::from_canonical);
                     self.compile_block(
                         parent_module,
                         then_block,
@@ -2481,9 +2553,9 @@ impl Compiler {
                     source_location,
                     blocks,
                 }) => {
-                    let enum_expr = self
-                        .compile_expr(*parent_module, Expr::canonical(expr))
-                        .map_ty(Enum::from_canonical);
+                    let enum_expr = self.compile_expr(*parent_module, Expr::canonical(expr));
+                    let enum_expr = self.compiled_expr_to_value(enum_expr, source_location);
+                    let enum_expr = enum_expr.map_ty(Enum::from_canonical);
                     for (variant_index, block) in blocks.into_iter().enumerate() {
                         self.compile_block(
                             parent_module,
@@ -2514,10 +2586,12 @@ impl Compiler {
                      annotations: _,
                      module_io,
                  }| {
-                    self.compile_value(TargetInInstantiatedModule {
+                    let target = TargetInInstantiatedModule {
                         instantiated_module: *module,
                         target: Target::from(module_io),
-                    })
+                    };
+                    self.decl_conditions.insert(target, Interned::default());
+                    self.compile_value(target)
                 },
             )
             .collect();
@@ -2537,8 +2611,7 @@ impl Compiler {
     fn process_assignments(&mut self) {
         self.assignments
             .finalize(self.insns.state_layout().len().ty);
-        let assignments_queue: Vec<usize> = match petgraph::algo::toposort(&self.assignments, None)
-        {
+        let assignments_order: Vec<_> = match petgraph::algo::toposort(&self.assignments, None) {
             Ok(nodes) => nodes
                 .into_iter()
                 .filter_map(|n| match n {
@@ -2549,7 +2622,7 @@ impl Compiler {
             Err(e) => match e.node_id() {
                 AssignmentOrSlotIndex::AssignmentIndex(assignment_index) => panic!(
                     "combinatorial logic cycle detected at: {}",
-                    self.assignments.assignments[assignment_index].source_location,
+                    self.assignments.assignments()[assignment_index].source_location,
                 ),
                 AssignmentOrSlotIndex::SmallSlots(slot) => panic!(
                     "combinatorial logic cycle detected through: {}",
@@ -2561,12 +2634,113 @@ impl Compiler {
                 ),
             },
         };
-        todo!();
+        struct CondStackEntry<'a> {
+            cond: &'a Cond,
+            end_label_index: usize,
+        }
+        let mut cond_stack = Vec::<CondStackEntry<'_>>::new();
+        for assignment_index in assignments_order {
+            let Assignment {
+                inputs: _,
+                outputs: _,
+                conditions,
+                insns,
+                source_location,
+            } = &self.assignments.assignments()[assignment_index];
+            let mut same_len = 0;
+            for (index, (entry, cond)) in cond_stack.iter().zip(conditions).enumerate() {
+                if entry.cond != cond {
+                    break;
+                }
+                same_len = index + 1;
+            }
+            while cond_stack.len() > same_len {
+                let CondStackEntry {
+                    cond: _,
+                    end_label_index,
+                } = cond_stack.pop().expect("just checked len");
+                self.insns.define_label_at_next_insn(end_label_index);
+            }
+            for cond in &conditions[cond_stack.len()..] {
+                let end_label_index = self.insns.new_label();
+                match cond.body {
+                    CondBody::IfTrue { cond: cond_value }
+                    | CondBody::IfFalse { cond: cond_value } => {
+                        let (branch_if_zero, branch_if_non_zero) = match cond_value.range.len() {
+                            TypeLen {
+                                small_slots:
+                                    StatePartLen {
+                                        value: 1,
+                                        _phantom: _,
+                                    },
+                                big_slots:
+                                    StatePartLen {
+                                        value: 0,
+                                        _phantom: _,
+                                    },
+                            } => (
+                                Insn::BranchIfSmallZero {
+                                    target: end_label_index,
+                                    value: cond_value.range.small_slots.start,
+                                },
+                                Insn::BranchIfSmallNonZero {
+                                    target: end_label_index,
+                                    value: cond_value.range.small_slots.start,
+                                },
+                            ),
+                            TypeLen {
+                                small_slots:
+                                    StatePartLen {
+                                        value: 0,
+                                        _phantom: _,
+                                    },
+                                big_slots:
+                                    StatePartLen {
+                                        value: 1,
+                                        _phantom: _,
+                                    },
+                            } => (
+                                Insn::BranchIfZero {
+                                    target: end_label_index,
+                                    value: cond_value.range.big_slots.start,
+                                },
+                                Insn::BranchIfNonZero {
+                                    target: end_label_index,
+                                    value: cond_value.range.big_slots.start,
+                                },
+                            ),
+                            _ => unreachable!(),
+                        };
+                        self.insns.push(
+                            if let CondBody::IfTrue { .. } = cond.body {
+                                branch_if_zero
+                            } else {
+                                branch_if_non_zero
+                            },
+                            cond.source_location,
+                        );
+                    }
+                    CondBody::MatchArm {
+                        enum_expr,
+                        variant_index,
+                    } => todo!(),
+                }
+                cond_stack.push(CondStackEntry {
+                    cond,
+                    end_label_index,
+                });
+            }
+            for insn in insns {
+                self.insns.push(*insn, *source_location);
+            }
+        }
     }
     pub fn compile(mut self) -> Compiled<Bundle> {
         let base_module =
             *self.compile_module(InstantiatedModule::Base(self.base_module).intern_sized());
         self.process_assignments();
+        self.insns
+            .push(Insn::Return, self.base_module.source_location());
         Compiled {
             insns: Insns::from(self.insns).intern_sized(),
             base_module,
@@ -2588,7 +2762,7 @@ pub struct Compiled<T: BundleType> {
 }
 
 impl<T: BundleType> Compiled<T> {
-    pub fn new(module: Module<T>) -> Self {
+    pub fn new(module: Interned<Module<T>>) -> Self {
         Self::from_canonical(Compiler::new(module.canonical().intern()).compile())
     }
     pub fn canonical(self) -> Compiled<Bundle> {
@@ -2620,14 +2794,19 @@ impl<T: BundleType> Compiled<T> {
 #[derive(Debug)]
 pub struct Simulation<T: BundleType> {
     state: interpreter::State,
-    compiled: Compiled<T>,
+    base_module: CompiledModule,
+    base_module_io_ty: T,
 }
 
 impl<T: BundleType> Simulation<T> {
+    pub fn new(module: Interned<Module<T>>) -> Self {
+        Self::from_compiled(Compiled::new(module))
+    }
     pub fn from_compiled(compiled: Compiled<T>) -> Self {
         Self {
             state: interpreter::State::new(compiled.insns),
-            compiled,
+            base_module: compiled.base_module,
+            base_module_io_ty: compiled.base_module_io_ty,
         }
     }
     pub fn settle_step(&mut self) {
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index 5269131..e713300 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -7,6 +7,7 @@ use crate::{
     ty::CanonicalType,
     util::get_many_mut,
 };
+use hashbrown::HashMap;
 use num_bigint::BigInt;
 use num_traits::{One, Signed, ToPrimitive, Zero};
 use std::{
@@ -166,6 +167,83 @@ fn make_array_into_iter<T, const I: usize, const N: usize>(
     retval
 }
 
+impl fmt::Debug for Insn {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.debug_fmt::<InsnsBuildingDone>(f, None, None)
+    }
+}
+
+impl Insn {
+    fn debug_fmt<BK: InsnsBuildingKind>(
+        &self,
+        f: &mut fmt::Formatter<'_>,
+        labels: Option<&Labels>,
+        state_layout: Option<&StateLayout<BK>>,
+    ) -> fmt::Result {
+        let (insn_name, fields) = self.fields_with_names();
+        write!(f, "{insn_name}")?;
+        if fields.len() == 0 {
+            return Ok(());
+        }
+        writeln!(f, " {{")?;
+        for (field_name, field) in fields {
+            write!(f, "    {field_name}: ")?;
+            match field.kind {
+                InsnFieldKind::BranchTarget => match field.ty {
+                    InsnFieldType::USize(&label_index) => {
+                        if let Some(labels) = labels {
+                            write!(f, "L{label_index}")?;
+                            if let Some(label) = labels.labels.get(label_index) {
+                                if let Some(address) = label.address {
+                                    write!(f, " (at {address})")?;
+                                } else {
+                                    write!(f, " (not yet defined)")?;
+                                }
+                            } else {
+                                write!(f, " (invalid)")?;
+                            }
+                            writeln!(f, ",")?;
+                            continue;
+                        }
+                    }
+                    InsnFieldType::SmallSlot(_)
+                    | InsnFieldType::BigSlot(_)
+                    | InsnFieldType::SmallSlotArrayIndexed(_)
+                    | InsnFieldType::BigSlotArrayIndexed(_)
+                    | InsnFieldType::SmallUInt(_)
+                    | InsnFieldType::SmallSInt(_)
+                    | InsnFieldType::InternedBigInt(_)
+                    | InsnFieldType::U8(_)
+                    | InsnFieldType::Empty(_) => {}
+                },
+                InsnFieldKind::Input | InsnFieldKind::Output | InsnFieldKind::Immediate => {}
+            }
+            match field.ty {
+                InsnFieldType::SmallSlot(v) => {
+                    v.debug_fmt(f, ",", " // ", "", state_layout)?;
+                }
+                InsnFieldType::BigSlot(v) => {
+                    v.debug_fmt(f, ",", " // ", "", state_layout)?;
+                }
+                InsnFieldType::SmallSlotArrayIndexed(v) => {
+                    v.debug_fmt(f, ",", " // ", "", state_layout)?;
+                }
+                InsnFieldType::BigSlotArrayIndexed(v) => {
+                    v.debug_fmt(f, ",", " // ", "", state_layout)?;
+                }
+                InsnFieldType::SmallUInt(v) => fmt::Debug::fmt(v, f)?,
+                InsnFieldType::SmallSInt(v) => fmt::Debug::fmt(v, f)?,
+                InsnFieldType::InternedBigInt(v) => fmt::Debug::fmt(v, f)?,
+                InsnFieldType::U8(v) => fmt::Debug::fmt(v, f)?,
+                InsnFieldType::USize(v) => fmt::Debug::fmt(v, f)?,
+                InsnFieldType::Empty(v) => fmt::Debug::fmt(v, f)?,
+            }
+            writeln!(f, ",")?;
+        }
+        write!(f, "}}")
+    }
+}
+
 macro_rules! impl_insns {
     (
         #[insn = $Insn:ident, next_macro = $next_macro:ident, branch_macro = $branch_macro:ident]
@@ -191,7 +269,7 @@ macro_rules! impl_insns {
             })? => $block:block
         )*
     ) => {
-        #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)]
+        #[derive(Copy, Clone, Eq, PartialEq, Hash)]
         $vis enum $Insn {
             $(
                 $(#[$insn_meta])*
@@ -249,6 +327,28 @@ macro_rules! impl_insns {
                     )*
                 }
             }
+            $vis fn fields_with_names<'a>(&'a self) -> (&'static str, std::array::IntoIter<(&'static str, InsnField<InsnFieldTypeTransformRef<'a>>), { $Insn::MAX_FIELDS }>) {
+                match self {
+                    $(
+                        $Insn::$insn_name $({
+                            $($field_name,)*
+                        })? => (
+                            stringify!($insn_name),
+                            make_array_into_iter([
+                                    $($((stringify!($field_name), InsnField {
+                                        ty: <$field_ty as InsnFieldTrait>::variant($field_name),
+                                        kind: InsnFieldKind::$field_kind,
+                                    }),)*)?
+                                ],
+                                || ("", InsnField {
+                                    ty: InsnFieldType::empty(),
+                                    kind: InsnFieldKind::Immediate,
+                                }),
+                            ),
+                        ),
+                    )*
+                }
+            }
             $vis fn fields_mut<'a>(&'a mut self) -> std::array::IntoIter<InsnField<InsnFieldTypeTransformRefMut<'a>>, { $Insn::MAX_FIELDS }> {
                 match self {
                     $(
@@ -339,6 +439,8 @@ pub(crate) trait InsnsBuildingKind: Copy + Eq + fmt::Debug + Hash + Default {
         + Default
         + Deref<Target = [T]>
         + FromIterator<T>;
+    type Labels: Default;
+    fn labels(labels: &Self::Labels) -> Option<&Labels>;
 }
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
@@ -346,6 +448,10 @@ pub(crate) struct InsnsBuildingDone;
 
 impl InsnsBuildingKind for InsnsBuildingDone {
     type Vec<T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static> = Interned<[T]>;
+    type Labels = ();
+    fn labels(_labels: &Self::Labels) -> Option<&Labels> {
+        None
+    }
 }
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
@@ -353,12 +459,27 @@ pub(crate) struct InsnsBuilding;
 
 impl InsnsBuildingKind for InsnsBuilding {
     type Vec<T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static> = Vec<T>;
+    type Labels = Labels;
+    fn labels(labels: &Self::Labels) -> Option<&Labels> {
+        Some(labels)
+    }
+}
+
+struct Label {
+    address: Option<usize>,
+}
+
+#[derive(Default)]
+pub(crate) struct Labels {
+    labels: Vec<Label>,
+    address_to_label_indexes_map: HashMap<usize, Vec<usize>>,
 }
 
 #[derive(Clone, PartialEq, Eq, Hash)]
 pub(crate) struct Insns<BK: InsnsBuildingKind> {
     insns: BK::Vec<Insn>,
     insn_source_locations: BK::Vec<SourceLocation>,
+    labels: BK::Labels,
     state_layout: StateLayout<BK>,
 }
 
@@ -368,21 +489,60 @@ impl<BK: InsnsBuildingKind> Insns<BK> {
     }
 }
 
-struct InsnsDebug<'a> {
+struct InsnsDebug<'a, BK: InsnsBuildingKind> {
     insns: &'a [Insn],
     insn_source_locations: &'a [SourceLocation],
+    labels: &'a BK::Labels,
+    state_layout: &'a StateLayout<BK>,
 }
 
-impl<'a> fmt::Debug for InsnsDebug<'a> {
+struct InsnDebug<'a, BK: InsnsBuildingKind> {
+    address: usize,
+    source_location: Option<SourceLocation>,
+    insn: &'a Insn,
+    labels: Option<&'a Labels>,
+    state_layout: &'a StateLayout<BK>,
+}
+
+impl<BK: InsnsBuildingKind> fmt::Debug for InsnDebug<'_, BK> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        if let Some(label_indexes) = self
+            .labels
+            .and_then(|labels| labels.address_to_label_indexes_map.get(&self.address))
+        {
+            for &label_index in label_indexes {
+                writeln!(f, "L{label_index}:")?;
+            }
+        }
+        if let Some(source_location) = self.source_location {
+            writeln!(f, "// at: {source_location}")?;
+        }
+        self.insn.debug_fmt(f, self.labels, Some(self.state_layout))
+    }
+}
+
+impl<'a, BK: InsnsBuildingKind> fmt::Debug for InsnsDebug<'a, BK> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let labels = BK::labels(&self.labels);
         let mut debug_list = f.debug_list();
         let mut last_source_location = None;
-        for (insn, source_location) in self.insns.iter().zip(self.insn_source_locations) {
-            if Some(source_location) != last_source_location {
-                debug_list.entry(&format_args!("// at: {source_location}\n{insn:?}"));
-            } else {
-                debug_list.entry(insn);
-            }
+        for (address, (insn, &source_location)) in self
+            .insns
+            .iter()
+            .zip(self.insn_source_locations)
+            .enumerate()
+        {
+            debug_list.entry(&InsnDebug {
+                address,
+                source_location: if Some(source_location) != last_source_location {
+                    Some(source_location)
+                } else {
+                    None
+                },
+                insn,
+                labels,
+                state_layout: self.state_layout,
+            });
             last_source_location = Some(source_location);
         }
         debug_list.finish()
@@ -394,15 +554,18 @@ impl<BK: InsnsBuildingKind> fmt::Debug for Insns<BK> {
         let Self {
             insns,
             insn_source_locations,
+            labels,
             state_layout,
         } = self;
         f.debug_struct("Insns")
             .field("state_layout", state_layout)
             .field(
                 "insns",
-                &InsnsDebug {
+                &InsnsDebug::<BK> {
                     insns,
                     insn_source_locations,
+                    labels,
+                    state_layout,
                 },
             )
             .finish_non_exhaustive()
@@ -418,6 +581,10 @@ pub(crate) trait StatePartKind:
     type BorrowedState<'a>: 'a;
     fn new_state(len: StatePartLen<Self>) -> Self::State;
     fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a>;
+    fn part_debug_data<BK: InsnsBuildingKind>(
+        state_layout: &StateLayout<BK>,
+        part_index: StatePartIndex<Self>,
+    ) -> Option<&Self::DebugData>;
 }
 
 pub(crate) trait StatePartsValue {
@@ -980,6 +1147,12 @@ make_state_part_kinds! {
         fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
             state.borrow()
         }
+        fn part_debug_data<BK: InsnsBuildingKind>(
+            state_layout: &StateLayout<BK>,
+            part_index: StatePartIndex<Self>,
+        ) -> Option<&Self::DebugData> {
+            state_layout.small_stack.debug_data.get(part_index.as_usize())
+        }
     }
     #[state, field = big_stack]
     impl StatePartKind for StatePartKindBigStack {
@@ -993,6 +1166,12 @@ make_state_part_kinds! {
         fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
             state.borrow()
         }
+        fn part_debug_data<BK: InsnsBuildingKind>(
+            state_layout: &StateLayout<BK>,
+            part_index: StatePartIndex<Self>,
+        ) -> Option<&Self::DebugData> {
+            state_layout.big_stack.debug_data.get(part_index.as_usize())
+        }
     }*/
     #[type, field = small_slots]
     impl StatePartKind for StatePartKindSmallSlots {
@@ -1006,6 +1185,12 @@ make_state_part_kinds! {
         fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
             state
         }
+        fn part_debug_data<BK: InsnsBuildingKind>(
+            state_layout: &StateLayout<BK>,
+            part_index: StatePartIndex<Self>,
+        ) -> Option<&Self::DebugData> {
+            state_layout.ty.small_slots.debug_data.get(part_index.as_usize())
+        }
     }
     #[type, field = big_slots]
     impl StatePartKind for StatePartKindBigSlots {
@@ -1019,6 +1204,12 @@ make_state_part_kinds! {
         fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
             state
         }
+        fn part_debug_data<BK: InsnsBuildingKind>(
+            state_layout: &StateLayout<BK>,
+            part_index: StatePartIndex<Self>,
+        ) -> Option<&Self::DebugData> {
+            state_layout.ty.big_slots.debug_data.get(part_index.as_usize())
+        }
     }
 }
 
@@ -1163,12 +1354,57 @@ pub(crate) struct StatePartArrayIndex<K: StatePartKind> {
     pub(crate) stride: StatePartLen<K>,
 }
 
-#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
 pub(crate) struct StatePartArrayIndexed<K: StatePartKind> {
     pub(crate) base: StatePartIndex<K>,
     pub(crate) indexes: Interned<[StatePartArrayIndex<K>]>,
 }
 
+impl<K: StatePartKind> StatePartArrayIndexed<K> {
+    pub(crate) fn debug_fmt<BK: InsnsBuildingKind>(
+        &self,
+        f: &mut fmt::Formatter<'_>,
+        before_debug_info_text: &str,
+        comment_start: &str,
+        comment_end: &str,
+        state_layout: Option<&StateLayout<BK>>,
+    ) -> fmt::Result {
+        if let Some(state_layout) = state_layout {
+            let Self { base, indexes } = *self;
+            if indexes.is_empty() {
+                base.debug_fmt(
+                    f,
+                    before_debug_info_text,
+                    comment_start,
+                    comment_end,
+                    Some(state_layout),
+                )
+            } else {
+                base.debug_fmt(f, "", " /* ", " */ ", Some(state_layout))?;
+                for StatePartArrayIndex { index, len, stride } in indexes {
+                    f.write_str("[")?;
+                    index.debug_fmt(f, "", " /* ", " */ ", Some(state_layout))?;
+                    write!(f, ", len={len}, stride={}]", stride.value)?;
+                }
+                f.write_str(before_debug_info_text)
+            }
+        } else {
+            let Self { base, indexes } = self;
+            f.debug_struct("StatePartArrayIndexed")
+                .field("base", base)
+                .field("indexes", indexes)
+                .finish()?;
+            f.write_str(before_debug_info_text)
+        }
+    }
+}
+
+impl<K: StatePartKind + fmt::Debug> fmt::Debug for StatePartArrayIndexed<K> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", None)
+    }
+}
+
 impl<K: StatePartKind> From<StatePartIndex<K>> for StatePartArrayIndexed<K> {
     fn from(base: StatePartIndex<K>) -> Self {
         Self {
@@ -1226,11 +1462,28 @@ impl<K: StatePartKind> StatePartIndex<K> {
             _phantom: PhantomData,
         }
     }
+    pub(crate) fn debug_fmt<BK: InsnsBuildingKind>(
+        &self,
+        f: &mut fmt::Formatter<'_>,
+        before_debug_info_text: &str,
+        comment_start: &str,
+        comment_end: &str,
+        state_layout: Option<&StateLayout<BK>>,
+    ) -> fmt::Result {
+        write!(f, "StatePartIndex<{}>({})", K::NAME, self.value)?;
+        f.write_str(before_debug_info_text)?;
+        if let Some(state_layout) = state_layout {
+            if let Some(debug_data) = K::part_debug_data(state_layout, *self) {
+                write!(f, "{comment_start}{debug_data:?}{comment_end}")?;
+            }
+        }
+        Ok(())
+    }
 }
 
 impl<K: StatePartKind> fmt::Debug for StatePartIndex<K> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        write!(f, "StatePartIndex<{}>({})", K::NAME, self.value)
+        self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", None)
     }
 }
 
@@ -1641,6 +1894,7 @@ impl Insns<InsnsBuilding> {
         Self {
             insns: Vec::new(),
             insn_source_locations: Vec::new(),
+            labels: Labels::default(),
             state_layout: StateLayout::empty(),
         }
     }
@@ -1663,18 +1917,62 @@ impl Insns<InsnsBuilding> {
     ) -> TypeIndexRange {
         self.state_layout.ty.allocate(layout)
     }
+    pub(crate) fn new_label(&mut self) -> usize {
+        let retval = self.labels.labels.len();
+        self.labels.labels.push(Label { address: None });
+        retval
+    }
+    #[track_caller]
+    pub(crate) fn define_label_at_next_insn(&mut self, label_index: usize) {
+        let address = self.next_insn_pc();
+        let label = &mut self.labels.labels[label_index];
+        assert!(label.address.is_none(), "label already defined");
+        label.address = Some(address);
+        self.labels
+            .address_to_label_indexes_map
+            .entry(address)
+            .or_default()
+            .push(label_index);
+    }
 }
 
 impl From<Insns<InsnsBuilding>> for Insns<InsnsBuildingDone> {
     fn from(input: Insns<InsnsBuilding>) -> Self {
         let Insns {
-            insns,
+            mut insns,
             insn_source_locations,
+            labels,
             state_layout,
         } = input;
+        for insn in &mut insns {
+            for field in insn.fields_mut() {
+                match field.kind {
+                    InsnFieldKind::BranchTarget => match field.ty {
+                        InsnFieldType::USize(value) => {
+                            *value = labels.labels[*value]
+                                .address
+                                .expect("label address not set");
+                        }
+                        InsnFieldType::SmallSlot(_)
+                        | InsnFieldType::BigSlot(_)
+                        | InsnFieldType::SmallSlotArrayIndexed(_)
+                        | InsnFieldType::BigSlotArrayIndexed(_)
+                        | InsnFieldType::SmallUInt(_)
+                        | InsnFieldType::SmallSInt(_)
+                        | InsnFieldType::InternedBigInt(_)
+                        | InsnFieldType::U8(_)
+                        | InsnFieldType::Empty(_) => {
+                            unreachable!()
+                        }
+                    },
+                    InsnFieldKind::Input | InsnFieldKind::Output | InsnFieldKind::Immediate => {}
+                }
+            }
+        }
         Insns {
             insns: Intern::intern_owned(insns),
             insn_source_locations: Intern::intern_owned(insn_source_locations),
+            labels: (),
             state_layout: state_layout.into(),
         }
     }
@@ -2182,6 +2480,60 @@ impl_insns! {
         state.big_slots[dest].clone_from(&value);
         next!();
     }
+    Branch {
+        #[kind = BranchTarget]
+        target: usize,
+    } => {
+        branch!(target);
+    }
+    BranchIfZero {
+        #[kind = BranchTarget]
+        target: usize,
+        #[kind = Input]
+        value: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        if state.big_slots[value].is_zero() {
+            branch!(target);
+        } else {
+            next!();
+        }
+    }
+    BranchIfNonZero {
+        #[kind = BranchTarget]
+        target: usize,
+        #[kind = Input]
+        value: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        if state.big_slots[value].is_zero() {
+            next!();
+        } else {
+            branch!(target);
+        }
+    }
+    BranchIfSmallZero {
+        #[kind = BranchTarget]
+        target: usize,
+        #[kind = Input]
+        value: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        if state.small_slots[value] == 0 {
+            branch!(target);
+        } else {
+            next!();
+        }
+    }
+    BranchIfSmallNonZero {
+        #[kind = BranchTarget]
+        target: usize,
+        #[kind = Input]
+        value: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        if state.small_slots[value] == 0 {
+            next!();
+        } else {
+            branch!(target);
+        }
+    }
     Return => {
         break;
     }
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
new file mode 100644
index 0000000..89302af
--- /dev/null
+++ b/crates/fayalite/tests/sim.rs
@@ -0,0 +1,524 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+use fayalite::{prelude::*, sim::Simulation};
+
+#[hdl_module(outline_generated)]
+pub fn connect_const() {
+    #[hdl]
+    let o: UInt<8> = m.output();
+    connect(o, 5u8);
+}
+
+#[test]
+fn test_connect_const() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(connect_const());
+    sim.settle_step();
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug
+        != r#"Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
+                    value: 5,
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Return,
+            ],
+            ..
+        },
+        pc: 2,
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                5,
+                5,
+            ],
+        },
+    },
+    base_module: CompiledModule {
+        module_io: [
+            CompiledValue {
+                layout: CompiledTypeLayout {
+                    ty: UInt<8>,
+                    layout: TypeLayout {
+                        small_slots: StatePartAllocationLayout<SmallSlots> {
+                            len: 0,
+                            debug_data: [],
+                            ..
+                        },
+                        big_slots: StatePartAllocationLayout<BigSlots> {
+                            len: 1,
+                            debug_data: [
+                                SlotDebugData {
+                                    name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
+                                    ty: UInt<8>,
+                                },
+                            ],
+                            ..
+                        },
+                    },
+                    body: Scalar,
+                },
+                range: TypeIndexRange {
+                    small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                    big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+                },
+                write: None,
+            },
+        ],
+    },
+    base_module_io_ty: connect_const {
+        o: UInt<8>,
+    },
+}"# {
+        panic!();
+    }
+}
+
+#[hdl_module(outline_generated)]
+pub fn mod1_child() {
+    #[hdl]
+    let i: UInt<4> = m.input();
+    #[hdl]
+    let o: SInt<2> = m.output();
+    #[hdl]
+    let i2: SInt<2> = m.input();
+    #[hdl]
+    let o2: UInt<4> = m.output();
+    connect(o, i.cast_to_static());
+    connect(o2, i2.cast_to_static());
+    #[hdl]
+    if i.cmp_gt(5_hdl_u4) {
+        connect(o2, 0xF_hdl_u4);
+    }
+}
+
+#[hdl_module(outline_generated)]
+pub fn mod1() {
+    #[hdl]
+    let child = instance(mod1_child());
+    #[hdl]
+    let o: mod1_child = m.output(Expr::ty(child));
+    connect(o, child);
+}
+
+#[test]
+fn test_mod1() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(mod1());
+    sim.settle_step();
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug
+        != r#"Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 17,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.i",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.o",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::child.i",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::child.o",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::child.i2",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::child.o2",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:4:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:2:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX-2.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
+                    value: 15,
+                },
+                Const {
+                    dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
+                    value: 5,
+                },
+                CmpLt {
+                    dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
+                },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
+                    dest_width: 4,
+                },
+                // at: module-XXXXXXXXXX-2.rs:7:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX-2.rs:8:1
+                BranchIfZero {
+                    target: 11,
+                    value: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX-2.rs:9:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:2:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX-2.rs:1:1
+                CastToSInt {
+                    dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
+                    dest_width: 2,
+                },
+                // at: module-XXXXXXXXXX-2.rs:6:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:2:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Return,
+            ],
+            ..
+        },
+        pc: 17,
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                5,
+                0,
+                15,
+            ],
+        },
+    },
+    base_module: CompiledModule {
+        module_io: [
+            CompiledValue {
+                layout: CompiledTypeLayout {
+                    ty: Bundle {
+                        #[hdl(flip)] /* offset = 0 */
+                        i: UInt<4>,
+                        /* offset = 4 */
+                        o: SInt<2>,
+                        #[hdl(flip)] /* offset = 6 */
+                        i2: SInt<2>,
+                        /* offset = 8 */
+                        o2: UInt<4>,
+                    },
+                    layout: TypeLayout {
+                        small_slots: StatePartAllocationLayout<SmallSlots> {
+                            len: 0,
+                            debug_data: [],
+                            ..
+                        },
+                        big_slots: StatePartAllocationLayout<BigSlots> {
+                            len: 4,
+                            debug_data: [
+                                SlotDebugData {
+                                    name: "InstantiatedModule(mod1: mod1).mod1::o.i",
+                                    ty: UInt<4>,
+                                },
+                                SlotDebugData {
+                                    name: "InstantiatedModule(mod1: mod1).mod1::o.o",
+                                    ty: SInt<2>,
+                                },
+                                SlotDebugData {
+                                    name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
+                                    ty: SInt<2>,
+                                },
+                                SlotDebugData {
+                                    name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
+                                    ty: UInt<4>,
+                                },
+                            ],
+                            ..
+                        },
+                    },
+                    body: Bundle {
+                        fields: [
+                            CompiledBundleField {
+                                offset: TypeIndex {
+                                    small_slots: StatePartIndex<SmallSlots>(0),
+                                    big_slots: StatePartIndex<BigSlots>(0),
+                                },
+                                ty: CompiledTypeLayout {
+                                    ty: UInt<4>,
+                                    layout: TypeLayout {
+                                        small_slots: StatePartAllocationLayout<SmallSlots> {
+                                            len: 0,
+                                            debug_data: [],
+                                            ..
+                                        },
+                                        big_slots: StatePartAllocationLayout<BigSlots> {
+                                            len: 1,
+                                            debug_data: [
+                                                SlotDebugData {
+                                                    name: "",
+                                                    ty: UInt<4>,
+                                                },
+                                            ],
+                                            ..
+                                        },
+                                    },
+                                    body: Scalar,
+                                },
+                            },
+                            CompiledBundleField {
+                                offset: TypeIndex {
+                                    small_slots: StatePartIndex<SmallSlots>(0),
+                                    big_slots: StatePartIndex<BigSlots>(1),
+                                },
+                                ty: CompiledTypeLayout {
+                                    ty: SInt<2>,
+                                    layout: TypeLayout {
+                                        small_slots: StatePartAllocationLayout<SmallSlots> {
+                                            len: 0,
+                                            debug_data: [],
+                                            ..
+                                        },
+                                        big_slots: StatePartAllocationLayout<BigSlots> {
+                                            len: 1,
+                                            debug_data: [
+                                                SlotDebugData {
+                                                    name: "",
+                                                    ty: SInt<2>,
+                                                },
+                                            ],
+                                            ..
+                                        },
+                                    },
+                                    body: Scalar,
+                                },
+                            },
+                            CompiledBundleField {
+                                offset: TypeIndex {
+                                    small_slots: StatePartIndex<SmallSlots>(0),
+                                    big_slots: StatePartIndex<BigSlots>(2),
+                                },
+                                ty: CompiledTypeLayout {
+                                    ty: SInt<2>,
+                                    layout: TypeLayout {
+                                        small_slots: StatePartAllocationLayout<SmallSlots> {
+                                            len: 0,
+                                            debug_data: [],
+                                            ..
+                                        },
+                                        big_slots: StatePartAllocationLayout<BigSlots> {
+                                            len: 1,
+                                            debug_data: [
+                                                SlotDebugData {
+                                                    name: "",
+                                                    ty: SInt<2>,
+                                                },
+                                            ],
+                                            ..
+                                        },
+                                    },
+                                    body: Scalar,
+                                },
+                            },
+                            CompiledBundleField {
+                                offset: TypeIndex {
+                                    small_slots: StatePartIndex<SmallSlots>(0),
+                                    big_slots: StatePartIndex<BigSlots>(3),
+                                },
+                                ty: CompiledTypeLayout {
+                                    ty: UInt<4>,
+                                    layout: TypeLayout {
+                                        small_slots: StatePartAllocationLayout<SmallSlots> {
+                                            len: 0,
+                                            debug_data: [],
+                                            ..
+                                        },
+                                        big_slots: StatePartAllocationLayout<BigSlots> {
+                                            len: 1,
+                                            debug_data: [
+                                                SlotDebugData {
+                                                    name: "",
+                                                    ty: UInt<4>,
+                                                },
+                                            ],
+                                            ..
+                                        },
+                                    },
+                                    body: Scalar,
+                                },
+                            },
+                        ],
+                    },
+                },
+                range: TypeIndexRange {
+                    small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                    big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 4 },
+                },
+                write: None,
+            },
+        ],
+    },
+    base_module_io_ty: mod1 {
+        o: mod1_child {
+            i: UInt<4>,
+            o: SInt<2>,
+            i2: SInt<2>,
+            o2: UInt<4>,
+        },
+    },
+}"# {
+        panic!();
+    }
+}

From 0095570f1911b5afe4d248cb3cbea2e96408d2dc Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 14 Nov 2024 20:28:43 -0800
Subject: [PATCH 088/190] simple combinatorial simulation works!

---
 crates/fayalite/src/int.rs             |  91 +++-
 crates/fayalite/src/module.rs          |  12 +
 crates/fayalite/src/sim.rs             | 353 +++++++++++++--
 crates/fayalite/src/sim/interpreter.rs |  17 +
 crates/fayalite/src/wire.rs            |  12 +
 crates/fayalite/tests/sim.rs           | 597 ++++++++++++++++---------
 6 files changed, 831 insertions(+), 251 deletions(-)

diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index 03b2c88..68f1cac 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -227,12 +227,29 @@ macro_rules! impl_int {
         impl<Width: Size> BoolOrIntType for $name<Width> {
             type Width = Width;
             type Signed = ConstBool<$SIGNED>;
+            type Value = $value<Width>;
             fn width(self) -> usize {
                 $name::width(self)
             }
             fn new(width: Width::SizeType) -> Self {
                 $name { width }
             }
+            fn value_from_bigint_wrapping(self, v: BigInt) -> Self::Value {
+                $value::<Width>::from_bigint_wrapping(self, v)
+            }
+            fn bits_to_value(bits: Cow<'_, BitSlice>) -> Self::Value {
+                #[derive(Copy, Clone, Eq, PartialEq, Hash)]
+                struct MemoizeBitsToValue;
+                impl Memoize for MemoizeBitsToValue {
+                    type Input = BitSlice;
+                    type InputOwned = BitVec;
+                    type Output = Arc<BitVec>;
+                    fn inner(self, input: &Self::Input) -> Self::Output {
+                        Arc::new(input.to_bitvec())
+                    }
+                }
+                $value::new(MemoizeBitsToValue.get_cow(bits))
+            }
             fn bits_to_expr(bits: Cow<'_, BitSlice>) -> Expr<Self> {
                 #[derive(Copy, Clone, Eq, PartialEq, Hash)]
                 struct MemoizeBitsToExpr;
@@ -334,6 +351,24 @@ macro_rules! impl_int {
             }
         }
 
+        impl<Width: Size> PartialOrd for $value<Width> {
+            fn partial_cmp(&self, other: &Self) -> Option<std::cmp::Ordering> {
+                Some(self.cmp(other))
+            }
+        }
+
+        impl<Width: Size> Ord for $value<Width> {
+            fn cmp(&self, other: &Self) -> std::cmp::Ordering {
+                self.to_bigint().cmp(&other.to_bigint())
+            }
+        }
+
+        impl<Width: Size> From<$value<Width>> for BigInt {
+            fn from(v: $value<Width>) -> BigInt {
+                v.to_bigint()
+            }
+        }
+
         impl<Width: Size> $value<Width> {
             pub fn width(&self) -> usize {
                 if let Some(retval) = Width::KNOWN_VALUE {
@@ -482,6 +517,19 @@ macro_rules! impl_prim_int {
         $(#[$meta:meta])*
         $prim_int:ident, $ty:ty
     ) => {
+        impl From<$prim_int> for <$ty as BoolOrIntType>::Value {
+            fn from(v: $prim_int) -> Self {
+                <$ty>::le_bytes_to_value_wrapping(
+                    &v.to_le_bytes(),
+                    <$ty as BoolOrIntType>::Width::VALUE,
+                )
+            }
+        }
+        impl From<NonZero<$prim_int>> for <$ty as BoolOrIntType>::Value {
+            fn from(v: NonZero<$prim_int>) -> Self {
+                v.get().into()
+            }
+        }
         $(#[$meta])*
         impl ToExpr for $prim_int {
             type Type = $ty;
@@ -498,10 +546,7 @@ macro_rules! impl_prim_int {
             type Type = $ty;
 
             fn to_expr(&self) -> Expr<Self::Type> {
-                <$ty>::le_bytes_to_expr_wrapping(
-                    &self.get().to_le_bytes(),
-                    <$ty as BoolOrIntType>::Width::VALUE,
-                )
+                self.get().to_expr()
             }
         }
     };
@@ -531,6 +576,15 @@ impl_prim_int!(
 pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
     type Width: Size;
     type Signed: GenericConstBool;
+    type Value: Clone
+        + Ord
+        + std::hash::Hash
+        + fmt::Debug
+        + Send
+        + Sync
+        + 'static
+        + ToExpr<Type = Self>
+        + Into<BigInt>;
     fn width(self) -> usize;
     fn new(width: <Self::Width as Size>::SizeType) -> Self;
     fn new_static() -> Self
@@ -545,6 +599,10 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
     fn as_same_width_uint(self) -> UIntType<Self::Width> {
         UIntType::new(Self::Width::from_usize(self.width()))
     }
+    fn value_from_int_wrapping(self, v: impl Into<BigInt>) -> Self::Value {
+        self.value_from_bigint_wrapping(v.into())
+    }
+    fn value_from_bigint_wrapping(self, v: BigInt) -> Self::Value;
     fn bits_from_bigint_wrapping(self, v: BigInt) -> BitVec {
         let width = self.width();
         let mut bytes = v.to_signed_bytes_le();
@@ -567,8 +625,9 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
         BitSlice::<u8, Lsb0>::from_slice_mut(&mut bytes)[..bits.len()].clone_from_bitslice(bits);
         BigInt::from_signed_bytes_le(&bytes)
     }
+    fn bits_to_value(bits: Cow<'_, BitSlice>) -> Self::Value;
     fn bits_to_expr(bits: Cow<'_, BitSlice>) -> Expr<Self>;
-    fn le_bytes_to_expr_wrapping(bytes: &[u8], bit_width: usize) -> Expr<Self> {
+    fn le_bytes_to_bits_wrapping(bytes: &[u8], bit_width: usize) -> BitVec {
         let bitslice = BitSlice::<u8, Lsb0>::from_slice(bytes);
         let bitslice = &bitslice[..bit_width.min(bitslice.len())];
         let mut bits = BitVec::new();
@@ -577,7 +636,17 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
             bit_width,
             Self::Signed::VALUE && bits.last().as_deref().copied().unwrap_or(false),
         );
-        Self::bits_to_expr(Cow::Owned(bits))
+        bits
+    }
+    fn le_bytes_to_expr_wrapping(bytes: &[u8], bit_width: usize) -> Expr<Self> {
+        Self::bits_to_expr(Cow::Owned(Self::le_bytes_to_bits_wrapping(
+            bytes, bit_width,
+        )))
+    }
+    fn le_bytes_to_value_wrapping(bytes: &[u8], bit_width: usize) -> Self::Value {
+        Self::bits_to_value(Cow::Owned(Self::le_bytes_to_bits_wrapping(
+            bytes, bit_width,
+        )))
     }
 }
 
@@ -629,6 +698,7 @@ impl sealed::BoolOrIntTypeSealed for Bool {}
 impl BoolOrIntType for Bool {
     type Width = ConstUsize<1>;
     type Signed = ConstBool<false>;
+    type Value = bool;
 
     fn width(self) -> usize {
         1
@@ -639,10 +709,19 @@ impl BoolOrIntType for Bool {
         Bool
     }
 
+    fn value_from_bigint_wrapping(self, v: BigInt) -> Self::Value {
+        v.bit(0)
+    }
+
     fn bits_to_expr(bits: Cow<'_, BitSlice>) -> Expr<Self> {
         assert_eq!(bits.len(), 1);
         bits[0].to_expr()
     }
+
+    fn bits_to_value(bits: Cow<'_, BitSlice>) -> Self::Value {
+        assert_eq!(bits.len(), 1);
+        bits[0]
+    }
 }
 
 impl Bool {
diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index 7387832..16010cf 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -714,6 +714,18 @@ impl<T: BundleType> Instance<T> {
             source_location,
         }
     }
+    pub fn from_canonical(v: Instance<Bundle>) -> Self {
+        let Instance {
+            scoped_name,
+            instantiated,
+            source_location,
+        } = v;
+        Self {
+            scoped_name,
+            instantiated: Module::from_canonical(*instantiated).intern_sized(),
+            source_location,
+        }
+    }
     pub fn containing_module_name(self) -> Interned<str> {
         self.containing_module_name_id().0
     }
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 7793dce..90991b4 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -11,29 +11,33 @@ use crate::{
             GetTarget, Target, TargetBase, TargetPathArrayElement, TargetPathBundleField,
             TargetPathElement,
         },
-        ExprEnum, Flow,
+        ExprEnum, Flow, ToLiteralBits,
     },
+    int::BoolOrIntType,
     intern::{Intern, Interned, Memoize},
     module::{
-        AnnotatedModuleIO, Block, ModuleBody, NormalModuleBody, Stmt, StmtConnect, StmtDeclaration,
-        StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire,
+        AnnotatedModuleIO, Block, Id, ModuleBody, NameId, NormalModuleBody, ScopedNameId, Stmt,
+        StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg,
+        StmtWire,
     },
     prelude::*,
     sim::interpreter::{
         Insn, InsnField, InsnFieldKind, InsnFieldType, Insns, InsnsBuilding, InsnsBuildingDone,
-        SlotDebugData, SmallUInt, StatePartArrayIndex, StatePartArrayIndexed, StatePartIndex,
-        StatePartIndexRange, StatePartKind, StatePartKindBigSlots, StatePartKindSmallSlots,
-        StatePartLayout, StatePartLen, StatePartsValue, TypeArrayIndex, TypeArrayIndexes,
-        TypeIndex, TypeIndexRange, TypeLayout, TypeLen, TypeParts,
+        SlotDebugData, SmallUInt, State, StatePartArrayIndex, StatePartArrayIndexed,
+        StatePartIndex, StatePartIndexRange, StatePartKind, StatePartKindBigSlots,
+        StatePartKindSmallSlots, StatePartLayout, StatePartLen, StatePartsValue, TypeArrayIndex,
+        TypeArrayIndexes, TypeIndex, TypeIndexRange, TypeLayout, TypeLen, TypeParts,
     },
     ty::StaticType,
+    util::DebugAsDisplay,
 };
-use hashbrown::HashMap;
+use hashbrown::{HashMap, HashSet};
 use num_bigint::BigInt;
+use num_traits::ToPrimitive;
 use petgraph::visit::{
     GraphBase, IntoNeighbors, IntoNeighborsDirected, IntoNodeIdentifiers, VisitMap, Visitable,
 };
-use std::{collections::BTreeSet, fmt, marker::PhantomData, mem, ops::IndexMut};
+use std::{borrow::Cow, collections::BTreeSet, fmt, marker::PhantomData, mem, ops::IndexMut};
 
 mod interpreter;
 
@@ -2744,7 +2748,14 @@ impl Compiler {
         Compiled {
             insns: Insns::from(self.insns).intern_sized(),
             base_module,
-            base_module_io_ty: self.base_module.io_ty(),
+            io: Instance::new_unchecked(
+                ScopedNameId(
+                    NameId("<simulator>".intern(), Id::new()),
+                    self.base_module.name_id(),
+                ),
+                self.base_module,
+                self.base_module.source_location(),
+            ),
         }
     }
 }
@@ -2758,7 +2769,7 @@ struct CompiledModule {
 pub struct Compiled<T: BundleType> {
     insns: Interned<Insns<InsnsBuildingDone>>,
     base_module: CompiledModule,
-    base_module_io_ty: T,
+    io: Instance<T>,
 }
 
 impl<T: BundleType> Compiled<T> {
@@ -2769,48 +2780,338 @@ impl<T: BundleType> Compiled<T> {
         let Self {
             insns,
             base_module,
-            base_module_io_ty,
+            io,
         } = self;
         Compiled {
             insns,
             base_module,
-            base_module_io_ty: Bundle::from_canonical(base_module_io_ty.canonical()),
+            io: Instance::from_canonical(io.canonical()),
         }
     }
     pub fn from_canonical(canonical: Compiled<Bundle>) -> Self {
         let Compiled {
             insns,
             base_module,
-            base_module_io_ty,
+            io,
         } = canonical;
         Self {
             insns,
             base_module,
-            base_module_io_ty: T::from_canonical(base_module_io_ty.canonical()),
+            io: Instance::from_canonical(io.canonical()),
         }
     }
 }
 
-#[derive(Debug)]
-pub struct Simulation<T: BundleType> {
+struct SimulationImpl {
     state: interpreter::State,
-    base_module: CompiledModule,
-    base_module_io_ty: T,
+    io: Expr<Bundle>,
+    uninitialized_inputs: HashSet<Target>,
+    io_targets: HashMap<Target, CompiledValue<CanonicalType>>,
+    made_initial_step: bool,
+}
+
+impl SimulationImpl {
+    fn parse_io(&mut self, target: Target, value: CompiledValue<CanonicalType>) {
+        self.io_targets.insert(target, value);
+        match value.layout.body {
+            CompiledTypeLayoutBody::Scalar => match target.flow() {
+                Flow::Source => {}
+                Flow::Sink => {
+                    self.uninitialized_inputs.insert(target);
+                }
+                Flow::Duplex => unreachable!(),
+            },
+            CompiledTypeLayoutBody::Array { .. } => {
+                let value = value.map_ty(Array::from_canonical);
+                for index in 0..value.layout.ty.len() {
+                    self.parse_io(
+                        target.join(
+                            TargetPathElement::from(TargetPathArrayElement { index })
+                                .intern_sized(),
+                        ),
+                        value.element(index),
+                    );
+                }
+            }
+            CompiledTypeLayoutBody::Bundle { .. } => {
+                let value = value.map_ty(Bundle::from_canonical);
+                for BundleField { name, .. } in value.layout.ty.fields() {
+                    self.parse_io(
+                        target.join(
+                            TargetPathElement::from(TargetPathBundleField { name }).intern_sized(),
+                        ),
+                        value.field_by_name(name),
+                    );
+                }
+            }
+        }
+    }
+    fn new(compiled: Compiled<Bundle>) -> Self {
+        let mut retval = Self {
+            state: State::new(compiled.insns),
+            io: compiled.io.to_expr(),
+            uninitialized_inputs: HashSet::new(),
+            io_targets: HashMap::new(),
+            made_initial_step: false,
+        };
+        let io_target = Target::from(compiled.io);
+        for (BundleField { name, .. }, value) in compiled
+            .io
+            .ty()
+            .fields()
+            .into_iter()
+            .zip(compiled.base_module.module_io)
+        {
+            retval.parse_io(
+                io_target
+                    .join(TargetPathElement::from(TargetPathBundleField { name }).intern_sized()),
+                value,
+            );
+        }
+        retval
+    }
+    #[track_caller]
+    fn settle_step(&mut self) {
+        assert!(
+            self.uninitialized_inputs.is_empty(),
+            "didn't initialize all inputs",
+        );
+        self.state.setup_call(0);
+        self.state.run();
+        self.made_initial_step = true;
+    }
+    #[track_caller]
+    fn get_io(&self, target: Target) -> CompiledValue<CanonicalType> {
+        if let Some(&retval) = self.io_targets.get(&target) {
+            return retval;
+        }
+        if Some(&target) == self.io.target().as_deref()
+            || Some(target.base()) != self.io.target().map(|v| v.base())
+        {
+            panic!("simulator read/write expression must be an array element/field of `Simulator::io()`");
+        };
+        panic!("simulator read/write expression must not have dynamic array indexes");
+    }
+    #[track_caller]
+    fn read_bool_or_int<I: BoolOrIntType>(&self, io: Expr<I>) -> I::Value {
+        let Some(target) = io.target() else {
+            panic!("can't read from expression that's not a field/element of `Simulation::io()`");
+        };
+        let compiled_value = self.get_io(*target);
+        if !self.made_initial_step {
+            match target.flow() {
+                Flow::Source => {
+                    panic!("can't read from an output before the simulation has made any steps");
+                }
+                Flow::Sink => {
+                    if self.uninitialized_inputs.contains(&*target) {
+                        panic!("can't read from an uninitialized input");
+                    }
+                }
+                Flow::Duplex => unreachable!(),
+            }
+        }
+        match compiled_value.range.len() {
+            TypeLen {
+                small_slots:
+                    StatePartLen {
+                        value: 1,
+                        _phantom: _,
+                    },
+                big_slots:
+                    StatePartLen {
+                        value: 0,
+                        _phantom: _,
+                    },
+            } => Expr::ty(io).value_from_int_wrapping(
+                self.state.small_slots[compiled_value.range.small_slots.start],
+            ),
+            TypeLen {
+                small_slots:
+                    StatePartLen {
+                        value: 0,
+                        _phantom: _,
+                    },
+                big_slots:
+                    StatePartLen {
+                        value: 1,
+                        _phantom: _,
+                    },
+            } => Expr::ty(io).value_from_int_wrapping(
+                self.state.big_slots[compiled_value.range.big_slots.start].clone(),
+            ),
+            _ => unreachable!(),
+        }
+    }
+    #[track_caller]
+    fn write_bool_or_int<I: BoolOrIntType>(&mut self, io: Expr<I>, value: I::Value) {
+        let Some(target) = io.target() else {
+            panic!("can't write to an expression that's not a field/element of `Simulation::io()`");
+        };
+        let compiled_value = self.get_io(*target);
+        match target.flow() {
+            Flow::Source => {
+                panic!("can't write to an output");
+            }
+            Flow::Sink => {}
+            Flow::Duplex => unreachable!(),
+        }
+        let value: BigInt = value.into();
+        if !self.made_initial_step {
+            self.uninitialized_inputs.remove(&*target);
+        }
+        match compiled_value.range.len() {
+            TypeLen {
+                small_slots:
+                    StatePartLen {
+                        value: 1,
+                        _phantom: _,
+                    },
+                big_slots:
+                    StatePartLen {
+                        value: 0,
+                        _phantom: _,
+                    },
+            } => {
+                self.state.small_slots[compiled_value.range.small_slots.start] =
+                    value.to_u64().expect("value out of range");
+            }
+            TypeLen {
+                small_slots:
+                    StatePartLen {
+                        value: 0,
+                        _phantom: _,
+                    },
+                big_slots:
+                    StatePartLen {
+                        value: 1,
+                        _phantom: _,
+                    },
+            } => self.state.big_slots[compiled_value.range.big_slots.start] = value,
+            _ => unreachable!(),
+        }
+    }
+}
+
+pub struct Simulation<T: BundleType> {
+    sim_impl: SimulationImpl,
+    io: Expr<T>,
+}
+
+struct SortedSetDebug<'a, T>(&'a HashSet<T>);
+
+impl<T: fmt::Debug> fmt::Debug for SortedSetDebug<'_, T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let mut entries = Vec::from_iter(self.0.iter().map(|v| {
+            if f.alternate() {
+                format!("{v:#?}")
+            } else {
+                format!("{v:?}")
+            }
+        }));
+        entries.sort();
+        f.debug_set()
+            .entries(entries.iter().map(DebugAsDisplay))
+            .finish()
+    }
+}
+
+struct SortedMapDebug<'a, K, V>(&'a HashMap<K, V>);
+
+impl<K: fmt::Debug, V: fmt::Debug> fmt::Debug for SortedMapDebug<'_, K, V> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let mut entries = Vec::from_iter(self.0.iter().map(|(k, v)| {
+            if f.alternate() {
+                (format!("{k:#?}"), format!("{v:#?}"))
+            } else {
+                (format!("{k:?}"), format!("{v:?}"))
+            }
+        }));
+        entries.sort();
+        f.debug_map()
+            .entries(
+                entries
+                    .iter()
+                    .map(|(k, v)| (DebugAsDisplay(k), DebugAsDisplay(v))),
+            )
+            .finish()
+    }
+}
+
+impl<T: BundleType> fmt::Debug for Simulation<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            sim_impl:
+                SimulationImpl {
+                    state,
+                    io: _,
+                    uninitialized_inputs,
+                    io_targets,
+                    made_initial_step,
+                },
+            io,
+        } = self;
+        f.debug_struct("Simulation")
+            .field("state", state)
+            .field("io", io)
+            .field(
+                "uninitialized_inputs",
+                &SortedSetDebug(uninitialized_inputs),
+            )
+            .field("io_targets", &SortedMapDebug(io_targets))
+            .field("made_initial_step", made_initial_step)
+            .finish()
+    }
 }
 
 impl<T: BundleType> Simulation<T> {
     pub fn new(module: Interned<Module<T>>) -> Self {
         Self::from_compiled(Compiled::new(module))
     }
-    pub fn from_compiled(compiled: Compiled<T>) -> Self {
-        Self {
-            state: interpreter::State::new(compiled.insns),
-            base_module: compiled.base_module,
-            base_module_io_ty: compiled.base_module_io_ty,
+    pub fn canonical(self) -> Simulation<Bundle> {
+        let Self { sim_impl, io } = self;
+        Simulation {
+            sim_impl,
+            io: Expr::as_bundle(io),
         }
     }
+    pub fn from_canonical(canonical: Simulation<Bundle>) -> Self {
+        let Simulation { sim_impl, io } = canonical;
+        Self {
+            sim_impl,
+            io: Expr::from_bundle(io),
+        }
+    }
+    pub fn io(&self) -> Expr<T> {
+        self.io.to_expr()
+    }
+    pub fn from_compiled(compiled: Compiled<T>) -> Self {
+        let sim_impl = SimulationImpl::new(compiled.canonical());
+        Self {
+            io: Expr::from_bundle(sim_impl.io),
+            sim_impl,
+        }
+    }
+    #[track_caller]
     pub fn settle_step(&mut self) {
-        self.state.setup_call(0);
-        self.state.run();
+        self.sim_impl.settle_step();
+    }
+    #[track_caller]
+    pub fn read_bool_or_int<I: BoolOrIntType>(&self, io: Expr<I>) -> I::Value {
+        self.sim_impl.read_bool_or_int(io)
+    }
+    #[track_caller]
+    pub fn write_bool_or_int<I: BoolOrIntType>(
+        &mut self,
+        io: Expr<I>,
+        value: impl ToExpr<Type = I>,
+    ) {
+        let value = value.to_expr();
+        assert_eq!(Expr::ty(io), Expr::ty(value), "type mismatch");
+        let value = value
+            .to_literal_bits()
+            .expect("the value that is being written to an input must be a literal");
+        self.sim_impl
+            .write_bool_or_int(io, I::bits_to_value(Cow::Borrowed(&value)));
     }
 }
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index e713300..930c933 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -1718,6 +1718,23 @@ impl<
     }
 }
 
+impl<K: StatePartKind<State: Deref<Target: Index<usize, Output = T>>>, T> Index<StatePartIndex<K>>
+    for StatePart<K>
+{
+    type Output = T;
+    fn index(&self, index: StatePartIndex<K>) -> &Self::Output {
+        &self.value[index.value as usize]
+    }
+}
+
+impl<K: StatePartKind<State: DerefMut<Target: IndexMut<usize, Output = T>>>, T>
+    IndexMut<StatePartIndex<K>> for StatePart<K>
+{
+    fn index_mut(&mut self, index: StatePartIndex<K>) -> &mut Self::Output {
+        &mut self.value[index.value as usize]
+    }
+}
+
 impl<'a, K: StatePartKind<BorrowedState<'a>: Deref<Target: Index<usize, Output = T>>>, T>
     Index<StatePartIndex<K>> for BorrowedStatePart<'a, K>
 {
diff --git a/crates/fayalite/src/wire.rs b/crates/fayalite/src/wire.rs
index 85ab342..51f8cf7 100644
--- a/crates/fayalite/src/wire.rs
+++ b/crates/fayalite/src/wire.rs
@@ -37,6 +37,18 @@ impl<T: Type> Wire<T> {
             ty: ty.canonical(),
         }
     }
+    pub fn from_canonical(v: Wire<CanonicalType>) -> Self {
+        let Wire {
+            name,
+            source_location,
+            ty,
+        } = v;
+        Self {
+            name,
+            source_location,
+            ty: T::from_canonical(ty),
+        }
+    }
     pub fn ty(&self) -> T {
         self.ty
     }
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 89302af..1696d6a 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-use fayalite::{prelude::*, sim::Simulation};
+use fayalite::{int::UIntValue, prelude::*, sim::Simulation};
 
 #[hdl_module(outline_generated)]
 pub fn connect_const() {
@@ -70,44 +70,55 @@ fn test_connect_const() {
             ],
         },
     },
-    base_module: CompiledModule {
-        module_io: [
-            CompiledValue {
-                layout: CompiledTypeLayout {
-                    ty: UInt<8>,
-                    layout: TypeLayout {
-                        small_slots: StatePartAllocationLayout<SmallSlots> {
-                            len: 0,
-                            debug_data: [],
-                            ..
-                        },
-                        big_slots: StatePartAllocationLayout<BigSlots> {
-                            len: 1,
-                            debug_data: [
-                                SlotDebugData {
-                                    name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
-                                    ty: UInt<8>,
-                                },
-                            ],
-                            ..
-                        },
-                    },
-                    body: Scalar,
-                },
-                range: TypeIndexRange {
-                    small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                    big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-                },
-                write: None,
+    io: Instance {
+        name: <simulator>::connect_const,
+        instantiated: Module {
+            name: connect_const,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::connect_const,
+            instantiated: Module {
+                name: connect_const,
+                ..
             },
-        ],
-    },
-    base_module_io_ty: connect_const {
-        o: UInt<8>,
+        }.o: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
     },
+    made_initial_step: true,
 }"# {
         panic!();
     }
+    assert_eq!(sim.read_bool_or_int(sim.io().o), UIntValue::from(5u8));
 }
 
 #[hdl_module(outline_generated)]
@@ -137,10 +148,13 @@ pub fn mod1() {
     connect(o, child);
 }
 
+#[hdl]
 #[test]
 fn test_mod1() {
     let _n = SourceLocation::normalize_files_for_tests();
     let mut sim = Simulation::new(mod1());
+    sim.write_bool_or_int(sim.io().o.i, 0xA_hdl_u4);
+    sim.write_bool_or_int(sim.io().o.i2, -2_hdl_i2);
     sim.settle_step();
     let sim_debug = format!("{sim:#?}");
     println!("#######\n{sim_debug}\n#######");
@@ -326,199 +340,344 @@ fn test_mod1() {
         },
         big_slots: StatePart {
             value: [
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
+                10,
+                -2,
+                -2,
+                15,
+                10,
+                -2,
+                -2,
+                15,
+                10,
+                -2,
+                -2,
+                15,
+                -2,
+                14,
                 5,
-                0,
+                1,
                 15,
             ],
         },
     },
-    base_module: CompiledModule {
-        module_io: [
-            CompiledValue {
-                layout: CompiledTypeLayout {
-                    ty: Bundle {
-                        #[hdl(flip)] /* offset = 0 */
-                        i: UInt<4>,
-                        /* offset = 4 */
-                        o: SInt<2>,
-                        #[hdl(flip)] /* offset = 6 */
-                        i2: SInt<2>,
-                        /* offset = 8 */
-                        o2: UInt<4>,
-                    },
-                    layout: TypeLayout {
-                        small_slots: StatePartAllocationLayout<SmallSlots> {
-                            len: 0,
-                            debug_data: [],
-                            ..
-                        },
-                        big_slots: StatePartAllocationLayout<BigSlots> {
-                            len: 4,
-                            debug_data: [
-                                SlotDebugData {
-                                    name: "InstantiatedModule(mod1: mod1).mod1::o.i",
-                                    ty: UInt<4>,
-                                },
-                                SlotDebugData {
-                                    name: "InstantiatedModule(mod1: mod1).mod1::o.o",
-                                    ty: SInt<2>,
-                                },
-                                SlotDebugData {
-                                    name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
-                                    ty: SInt<2>,
-                                },
-                                SlotDebugData {
-                                    name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
-                                    ty: UInt<4>,
-                                },
-                            ],
-                            ..
-                        },
-                    },
-                    body: Bundle {
-                        fields: [
-                            CompiledBundleField {
-                                offset: TypeIndex {
-                                    small_slots: StatePartIndex<SmallSlots>(0),
-                                    big_slots: StatePartIndex<BigSlots>(0),
-                                },
-                                ty: CompiledTypeLayout {
-                                    ty: UInt<4>,
-                                    layout: TypeLayout {
-                                        small_slots: StatePartAllocationLayout<SmallSlots> {
-                                            len: 0,
-                                            debug_data: [],
-                                            ..
-                                        },
-                                        big_slots: StatePartAllocationLayout<BigSlots> {
-                                            len: 1,
-                                            debug_data: [
-                                                SlotDebugData {
-                                                    name: "",
-                                                    ty: UInt<4>,
-                                                },
-                                            ],
-                                            ..
-                                        },
-                                    },
-                                    body: Scalar,
-                                },
-                            },
-                            CompiledBundleField {
-                                offset: TypeIndex {
-                                    small_slots: StatePartIndex<SmallSlots>(0),
-                                    big_slots: StatePartIndex<BigSlots>(1),
-                                },
-                                ty: CompiledTypeLayout {
-                                    ty: SInt<2>,
-                                    layout: TypeLayout {
-                                        small_slots: StatePartAllocationLayout<SmallSlots> {
-                                            len: 0,
-                                            debug_data: [],
-                                            ..
-                                        },
-                                        big_slots: StatePartAllocationLayout<BigSlots> {
-                                            len: 1,
-                                            debug_data: [
-                                                SlotDebugData {
-                                                    name: "",
-                                                    ty: SInt<2>,
-                                                },
-                                            ],
-                                            ..
-                                        },
-                                    },
-                                    body: Scalar,
-                                },
-                            },
-                            CompiledBundleField {
-                                offset: TypeIndex {
-                                    small_slots: StatePartIndex<SmallSlots>(0),
-                                    big_slots: StatePartIndex<BigSlots>(2),
-                                },
-                                ty: CompiledTypeLayout {
-                                    ty: SInt<2>,
-                                    layout: TypeLayout {
-                                        small_slots: StatePartAllocationLayout<SmallSlots> {
-                                            len: 0,
-                                            debug_data: [],
-                                            ..
-                                        },
-                                        big_slots: StatePartAllocationLayout<BigSlots> {
-                                            len: 1,
-                                            debug_data: [
-                                                SlotDebugData {
-                                                    name: "",
-                                                    ty: SInt<2>,
-                                                },
-                                            ],
-                                            ..
-                                        },
-                                    },
-                                    body: Scalar,
-                                },
-                            },
-                            CompiledBundleField {
-                                offset: TypeIndex {
-                                    small_slots: StatePartIndex<SmallSlots>(0),
-                                    big_slots: StatePartIndex<BigSlots>(3),
-                                },
-                                ty: CompiledTypeLayout {
-                                    ty: UInt<4>,
-                                    layout: TypeLayout {
-                                        small_slots: StatePartAllocationLayout<SmallSlots> {
-                                            len: 0,
-                                            debug_data: [],
-                                            ..
-                                        },
-                                        big_slots: StatePartAllocationLayout<BigSlots> {
-                                            len: 1,
-                                            debug_data: [
-                                                SlotDebugData {
-                                                    name: "",
-                                                    ty: UInt<4>,
-                                                },
-                                            ],
-                                            ..
-                                        },
-                                    },
-                                    body: Scalar,
-                                },
-                            },
-                        ],
-                    },
-                },
-                range: TypeIndexRange {
-                    small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                    big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 4 },
-                },
-                write: None,
-            },
-        ],
-    },
-    base_module_io_ty: mod1 {
-        o: mod1_child {
-            i: UInt<4>,
-            o: SInt<2>,
-            i2: SInt<2>,
-            o2: UInt<4>,
+    io: Instance {
+        name: <simulator>::mod1,
+        instantiated: Module {
+            name: mod1,
+            ..
         },
     },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::mod1,
+            instantiated: Module {
+                name: mod1,
+                ..
+            },
+        }.o: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    #[hdl(flip)] /* offset = 0 */
+                    i: UInt<4>,
+                    /* offset = 4 */
+                    o: SInt<2>,
+                    #[hdl(flip)] /* offset = 6 */
+                    i2: SInt<2>,
+                    /* offset = 8 */
+                    o2: UInt<4>,
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 4,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.i",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.o",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: UInt<4>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: UInt<4>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: SInt<2>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: SInt<2>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(2),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: SInt<2>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: SInt<2>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(3),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: UInt<4>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: UInt<4>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 4 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::mod1,
+            instantiated: Module {
+                name: mod1,
+                ..
+            },
+        }.o.i: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<4>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::mod1,
+            instantiated: Module {
+                name: mod1,
+                ..
+            },
+        }.o.i2: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: SInt<2>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: SInt<2>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::mod1,
+            instantiated: Module {
+                name: mod1,
+                ..
+            },
+        }.o.o: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: SInt<2>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: SInt<2>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::mod1,
+            instantiated: Module {
+                name: mod1,
+                ..
+            },
+        }.o.o2: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<4>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
 }"# {
         panic!();
     }
+    let expected = -2_hdl_i2;
+    assert_eq!(sim.read_bool_or_int(sim.io().o.o).to_expr(), expected);
+    let expected = 0xF_hdl_u4;
+    assert_eq!(sim.read_bool_or_int(sim.io().o.o2).to_expr(), expected);
 }

From 288a6b71b9c8f55051bf5cd0d5f968238bec4ecb Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 17 Nov 2024 01:02:00 -0800
Subject: [PATCH 089/190] WIP adding VCD output

---
 crates/fayalite/src/sim.rs      | 560 +++++++++++++++++++++++++++++++-
 crates/fayalite/src/sim/time.rs | 165 ++++++++++
 crates/fayalite/tests/sim.rs    |  12 +
 3 files changed, 731 insertions(+), 6 deletions(-)
 create mode 100644 crates/fayalite/src/sim/time.rs

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 90991b4..2eed11c 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -21,16 +21,21 @@ use crate::{
         StmtWire,
     },
     prelude::*,
-    sim::interpreter::{
-        Insn, InsnField, InsnFieldKind, InsnFieldType, Insns, InsnsBuilding, InsnsBuildingDone,
-        SlotDebugData, SmallUInt, State, StatePartArrayIndex, StatePartArrayIndexed,
-        StatePartIndex, StatePartIndexRange, StatePartKind, StatePartKindBigSlots,
-        StatePartKindSmallSlots, StatePartLayout, StatePartLen, StatePartsValue, TypeArrayIndex,
-        TypeArrayIndexes, TypeIndex, TypeIndexRange, TypeLayout, TypeLen, TypeParts,
+    sim::{
+        interpreter::{
+            Insn, InsnField, InsnFieldKind, InsnFieldType, Insns, InsnsBuilding, InsnsBuildingDone,
+            SlotDebugData, SmallUInt, State, StatePartArrayIndex, StatePartArrayIndexed,
+            StatePartIndex, StatePartIndexRange, StatePartKind, StatePartKindBigSlots,
+            StatePartKindSmallSlots, StatePartLayout, StatePartLen, StatePartsValue,
+            TypeArrayIndex, TypeArrayIndexes, TypeIndex, TypeIndexRange, TypeLayout, TypeLen,
+            TypeParts,
+        },
+        time::SimInstant,
     },
     ty::StaticType,
     util::DebugAsDisplay,
 };
+use bitvec::{bits, order::Lsb0, slice::BitSlice};
 use hashbrown::{HashMap, HashSet};
 use num_bigint::BigInt;
 use num_traits::ToPrimitive;
@@ -40,6 +45,7 @@ use petgraph::visit::{
 use std::{borrow::Cow, collections::BTreeSet, fmt, marker::PhantomData, mem, ops::IndexMut};
 
 mod interpreter;
+pub mod time;
 
 #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
 enum CondBody {
@@ -2756,6 +2762,11 @@ impl Compiler {
                 self.base_module,
                 self.base_module.source_location(),
             ),
+            trace_decls: TraceModule {
+                name: self.base_module.name(),
+                children: Interned::default(), // TODO: finish
+            },
+            traces: Interned::default(), // TODO: finish
         }
     }
 }
@@ -2770,6 +2781,8 @@ pub struct Compiled<T: BundleType> {
     insns: Interned<Insns<InsnsBuildingDone>>,
     base_module: CompiledModule,
     io: Instance<T>,
+    trace_decls: TraceModule,
+    traces: Interned<[SimTrace]>,
 }
 
 impl<T: BundleType> Compiled<T> {
@@ -2781,11 +2794,15 @@ impl<T: BundleType> Compiled<T> {
             insns,
             base_module,
             io,
+            trace_decls,
+            traces,
         } = self;
         Compiled {
             insns,
             base_module,
             io: Instance::from_canonical(io.canonical()),
+            trace_decls,
+            traces,
         }
     }
     pub fn from_canonical(canonical: Compiled<Bundle>) -> Self {
@@ -2793,21 +2810,471 @@ impl<T: BundleType> Compiled<T> {
             insns,
             base_module,
             io,
+            trace_decls,
+            traces,
         } = canonical;
         Self {
             insns,
             base_module,
             io: Instance::from_canonical(io.canonical()),
+            trace_decls,
+            traces,
         }
     }
 }
 
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
+pub struct TraceScalarId(usize);
+
+impl TraceScalarId {
+    pub fn as_usize(self) -> usize {
+        self.0
+    }
+}
+
+macro_rules! impl_trace_decl {
+    (
+        $(
+            #[kind = $category_kind:ident]
+            $(#[$category_meta:meta])*
+            $category_variant:ident($category_enum:ident {
+                fn $category_property_fn:ident(self) -> $category_property_fn_ret_ty:ty;
+                $(
+                    $(#[$meta:meta])*
+                    $variant:ident($struct:ident {
+                        fn $property_fn:ident($property_fn_self:ident) -> _ $property_fn_block:block
+                        $($(#[$field_meta:meta])*
+                        $field_name:ident: $field_ty:ty,)*
+                    }),
+                )*
+            }),
+        )*
+    ) => {
+        $(
+            #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
+            #[non_exhaustive]
+            $(#[$category_meta])*
+            pub enum $category_kind {
+                $($(#[$meta])*
+                $variant,)*
+            }
+
+            impl From<$category_kind> for TraceKind {
+                fn from(v: $category_kind) -> Self {
+                    TraceKind::$category_variant(v)
+                }
+            }
+
+            #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+            #[non_exhaustive]
+            $(#[$category_meta])*
+            pub enum $category_enum {
+                $($(#[$meta])*
+                $variant($struct),)*
+            }
+
+            impl $category_enum {
+                pub fn kind(self) -> $category_kind {
+                    match self {
+                        $(Self::$variant(_) => $category_kind::$variant,)*
+                    }
+                }
+                pub fn name(self) -> Interned<str> {
+                    match self {
+                        $(Self::$variant(v) => v.name,)*
+                    }
+                }
+                pub fn $category_property_fn(self) -> $category_property_fn_ret_ty {
+                    match self {
+                        $(Self::$variant(v) => v.$property_fn(),)*
+                    }
+                }
+            }
+
+            impl From<$category_enum> for TraceDecl {
+                fn from(v: $category_enum) -> Self {
+                    TraceDecl::$category_variant(v)
+                }
+            }
+
+            $(
+                #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+                #[non_exhaustive]
+                $(#[$meta])*
+                pub struct $struct {
+                    $($(#[$field_meta])*
+                    pub $field_name: $field_ty,)*
+                }
+
+                impl $struct {
+                    pub fn $property_fn($property_fn_self) -> $category_property_fn_ret_ty $property_fn_block
+                }
+
+                impl From<$struct> for $category_enum {
+                    fn from(v: $struct) -> Self {
+                        $category_enum::$variant(v)
+                    }
+                }
+
+                impl From<$struct> for TraceDecl {
+                    fn from(v: $struct) -> Self {
+                        TraceDecl::$category_variant($category_enum::$variant(v))
+                    }
+                }
+            )*
+        )*
+
+        #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
+        pub enum TraceKind {
+            $($(#[$category_meta])*
+            $category_variant($category_kind),)*
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub enum TraceDecl {
+            $($(#[$category_meta])*
+            $category_variant($category_enum),)*
+        }
+    };
+}
+
+impl_trace_decl! {
+    #[kind = TraceScopeKind]
+    Scope(TraceScope {
+        fn children(self) -> Interned<[TraceDecl]>;
+        Module(TraceModule {
+            fn children(self) -> _ {
+                self.children
+            }
+            name: Interned<str>,
+            children: Interned<[TraceDecl]>,
+        }),
+        Instance(TraceInstance {
+            fn children(self) -> _ {
+                self.children
+            }
+            name: Interned<str>,
+            children: Interned<[TraceDecl]>,
+            ty: Bundle,
+            flow: Flow,
+        }),
+        ModuleIO(TraceModuleIO {
+            fn children(self) -> _ {
+                self.children
+            }
+            name: Interned<str>,
+            children: Interned<[TraceDecl]>,
+            ty: Bundle,
+            flow: Flow,
+        }),
+        Bundle(TraceBundle {
+            fn children(self) -> _ {
+                self.children
+            }
+            name: Interned<str>,
+            children: Interned<[TraceDecl]>,
+            ty: Bundle,
+            flow: Flow,
+        }),
+        Array(TraceArray {
+            fn children(self) -> _ {
+                self.children
+            }
+            name: Interned<str>,
+            children: Interned<[TraceDecl]>,
+            ty: Array,
+            flow: Flow,
+        }),
+        EnumWithFields(TraceEnumWithFields {
+            fn children(self) -> _ {
+                self.children
+            }
+            name: Interned<str>,
+            children: Interned<[TraceDecl]>,
+            ty: Enum,
+            flow: Flow,
+        }),
+    }),
+    #[kind = TraceScalarKind]
+    Scalar(TraceScalar {
+        fn id(self) -> TraceScalarId;
+        UInt(TraceUInt {
+            fn id(self) -> _ {
+                self.id
+            }
+            id: TraceScalarId,
+            name: Interned<str>,
+            ty: UInt,
+            flow: Flow,
+        }),
+        SInt(TraceSInt {
+            fn id(self) -> _ {
+                self.id
+            }
+            id: TraceScalarId,
+            name: Interned<str>,
+            ty: SInt,
+            flow: Flow,
+        }),
+        Bool(TraceBool {
+            fn id(self) -> _ {
+                self.id
+            }
+            id: TraceScalarId,
+            name: Interned<str>,
+            ty: Bool,
+            flow: Flow,
+        }),
+        FieldlessEnum(TraceFieldlessEnum {
+            fn id(self) -> _ {
+                self.id
+            }
+            id: TraceScalarId,
+            name: Interned<str>,
+            ty: Enum,
+            flow: Flow,
+        }),
+        EnumDiscriminant(TraceEnumDiscriminant {
+            fn id(self) -> _ {
+                self.id
+            }
+            id: TraceScalarId,
+            name: Interned<str>,
+            ty: Enum,
+            flow: Flow,
+        }),
+        Clock(TraceClock {
+            fn id(self) -> _ {
+                self.id
+            }
+            id: TraceScalarId,
+            name: Interned<str>,
+            ty: Clock,
+            flow: Flow,
+        }),
+        SyncReset(TraceSyncReset {
+            fn id(self) -> _ {
+                self.id
+            }
+            id: TraceScalarId,
+            name: Interned<str>,
+            ty: SyncReset,
+            flow: Flow,
+        }),
+        AsyncReset(TraceAsyncReset {
+            fn id(self) -> _ {
+                self.id
+            }
+            id: TraceScalarId,
+            name: Interned<str>,
+            ty: AsyncReset,
+            flow: Flow,
+        }),
+    }),
+}
+
+pub trait TraceWriterDecls: fmt::Debug + 'static + Sized {
+    type Error: std::error::Error + Send + Sync + 'static;
+    type TraceWriter: TraceWriter<Error = Self::Error>;
+    fn write_decls(self, module: TraceModule) -> Result<Self::TraceWriter, Self::Error>;
+}
+
+trait TraceWriterDeclsDynTrait: fmt::Debug {
+    fn write_decls_dyn(self: Box<Self>, module: TraceModule) -> std::io::Result<DynTraceWriter>;
+}
+
+fn err_into_io<E: std::error::Error + Send + Sync + 'static>(e: E) -> std::io::Error {
+    match <dyn std::error::Error + Send + Sync>::downcast::<std::io::Error>(Box::new(e)) {
+        Ok(retval) => *retval,
+        Err(e) => std::io::Error::other(e),
+    }
+}
+
+impl<T: TraceWriterDecls> TraceWriterDeclsDynTrait for T {
+    fn write_decls_dyn(self: Box<Self>, module: TraceModule) -> std::io::Result<DynTraceWriter> {
+        Ok(DynTraceWriter(Box::new(
+            TraceWriterDecls::write_decls(*self, module).map_err(err_into_io)?,
+        )))
+    }
+}
+
+pub trait TraceWriter: fmt::Debug + 'static {
+    type Error: std::error::Error + Send + Sync + 'static;
+    fn finish_init(&mut self) -> Result<(), Self::Error> {
+        Ok(())
+    }
+    fn change_time_to(&mut self, instant: SimInstant) -> Result<(), Self::Error> {
+        let _ = instant;
+        Ok(())
+    }
+    fn flush(&mut self) -> Result<(), Self::Error> {
+        Ok(())
+    }
+    fn close(self) -> Result<(), Self::Error>
+    where
+        Self: Sized,
+    {
+        Ok(())
+    }
+    fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error>;
+    fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error>;
+    fn set_signal_bool(&mut self, id: TraceScalarId, value: bool) -> Result<(), Self::Error> {
+        if value {
+            self.set_signal_uint(id, bits![1])
+        } else {
+            self.set_signal_uint(id, bits![0])
+        }
+    }
+    fn set_signal_clock(&mut self, id: TraceScalarId, value: bool) -> Result<(), Self::Error> {
+        self.set_signal_bool(id, value)
+    }
+    fn set_signal_sync_reset(&mut self, id: TraceScalarId, value: bool) -> Result<(), Self::Error> {
+        self.set_signal_bool(id, value)
+    }
+    fn set_signal_async_reset(
+        &mut self,
+        id: TraceScalarId,
+        value: bool,
+    ) -> Result<(), Self::Error> {
+        self.set_signal_bool(id, value)
+    }
+}
+
+pub struct DynTraceWriterDecls(Box<dyn TraceWriterDeclsDynTrait>);
+
+impl fmt::Debug for DynTraceWriterDecls {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.0.fmt(f)
+    }
+}
+
+impl TraceWriterDecls for DynTraceWriterDecls {
+    type Error = std::io::Error;
+    type TraceWriter = DynTraceWriter;
+    fn write_decls(self, module: TraceModule) -> Result<Self::TraceWriter, Self::Error> {
+        self.0.write_decls_dyn(module)
+    }
+}
+
+trait TraceWriterDynTrait: fmt::Debug + 'static {
+    fn finish_init_dyn(&mut self) -> std::io::Result<()>;
+    fn change_time_to_dyn(&mut self, instant: SimInstant) -> std::io::Result<()>;
+    fn flush_dyn(&mut self) -> std::io::Result<()>;
+    fn close_dyn(self: Box<Self>) -> std::io::Result<()>;
+    fn set_signal_uint_dyn(&mut self, id: TraceScalarId, value: &BitSlice) -> std::io::Result<()>;
+    fn set_signal_sint_dyn(&mut self, id: TraceScalarId, value: &BitSlice) -> std::io::Result<()>;
+    fn set_signal_bool_dyn(&mut self, id: TraceScalarId, value: bool) -> std::io::Result<()>;
+    fn set_signal_clock_dyn(&mut self, id: TraceScalarId, value: bool) -> std::io::Result<()>;
+    fn set_signal_sync_reset_dyn(&mut self, id: TraceScalarId, value: bool) -> std::io::Result<()>;
+    fn set_signal_async_reset_dyn(&mut self, id: TraceScalarId, value: bool)
+        -> std::io::Result<()>;
+}
+
+impl<T: TraceWriter> TraceWriterDynTrait for T {
+    fn finish_init_dyn(&mut self) -> std::io::Result<()> {
+        Ok(TraceWriter::finish_init(self).map_err(err_into_io)?)
+    }
+    fn change_time_to_dyn(&mut self, instant: SimInstant) -> std::io::Result<()> {
+        Ok(TraceWriter::change_time_to(self, instant).map_err(err_into_io)?)
+    }
+    fn flush_dyn(&mut self) -> std::io::Result<()> {
+        Ok(TraceWriter::flush(self).map_err(err_into_io)?)
+    }
+    fn close_dyn(self: Box<Self>) -> std::io::Result<()> {
+        Ok(TraceWriter::close(*self).map_err(err_into_io)?)
+    }
+    fn set_signal_uint_dyn(&mut self, id: TraceScalarId, value: &BitSlice) -> std::io::Result<()> {
+        Ok(TraceWriter::set_signal_uint(self, id, value).map_err(err_into_io)?)
+    }
+    fn set_signal_sint_dyn(&mut self, id: TraceScalarId, value: &BitSlice) -> std::io::Result<()> {
+        Ok(TraceWriter::set_signal_sint(self, id, value).map_err(err_into_io)?)
+    }
+    fn set_signal_bool_dyn(&mut self, id: TraceScalarId, value: bool) -> std::io::Result<()> {
+        Ok(TraceWriter::set_signal_bool(self, id, value).map_err(err_into_io)?)
+    }
+    fn set_signal_clock_dyn(&mut self, id: TraceScalarId, value: bool) -> std::io::Result<()> {
+        Ok(TraceWriter::set_signal_clock(self, id, value).map_err(err_into_io)?)
+    }
+    fn set_signal_sync_reset_dyn(&mut self, id: TraceScalarId, value: bool) -> std::io::Result<()> {
+        Ok(TraceWriter::set_signal_sync_reset(self, id, value).map_err(err_into_io)?)
+    }
+    fn set_signal_async_reset_dyn(
+        &mut self,
+        id: TraceScalarId,
+        value: bool,
+    ) -> std::io::Result<()> {
+        Ok(TraceWriter::set_signal_async_reset(self, id, value).map_err(err_into_io)?)
+    }
+}
+
+pub struct DynTraceWriter(Box<dyn TraceWriterDynTrait>);
+
+impl fmt::Debug for DynTraceWriter {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.0.fmt(f)
+    }
+}
+
+impl TraceWriter for DynTraceWriter {
+    type Error = std::io::Error;
+    fn finish_init(&mut self) -> Result<(), Self::Error> {
+        self.0.finish_init_dyn()
+    }
+    fn flush(&mut self) -> Result<(), Self::Error> {
+        self.0.flush_dyn()
+    }
+    fn close(self) -> Result<(), Self::Error> {
+        self.0.close_dyn()
+    }
+    fn change_time_to(&mut self, instant: SimInstant) -> Result<(), Self::Error> {
+        self.0.change_time_to_dyn(instant)
+    }
+    fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
+        self.0.set_signal_uint_dyn(id, value)
+    }
+    fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
+        self.0.set_signal_sint_dyn(id, value)
+    }
+    fn set_signal_bool(&mut self, id: TraceScalarId, value: bool) -> Result<(), Self::Error> {
+        self.0.set_signal_bool_dyn(id, value)
+    }
+    fn set_signal_clock(&mut self, id: TraceScalarId, value: bool) -> Result<(), Self::Error> {
+        self.0.set_signal_clock_dyn(id, value)
+    }
+    fn set_signal_sync_reset(&mut self, id: TraceScalarId, value: bool) -> Result<(), Self::Error> {
+        self.0.set_signal_sync_reset_dyn(id, value)
+    }
+    fn set_signal_async_reset(
+        &mut self,
+        id: TraceScalarId,
+        value: bool,
+    ) -> Result<(), Self::Error> {
+        self.0.set_signal_async_reset_dyn(id, value)
+    }
+}
+
+#[derive(Debug)]
+enum TraceWriterState<T: TraceWriterDecls> {
+    Decls(T),
+    Init(T::TraceWriter),
+    Running(T::TraceWriter),
+    Errored(Option<T::Error>),
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+struct SimTrace {
+    id: TraceScalarId,
+}
+
 struct SimulationImpl {
     state: interpreter::State,
     io: Expr<Bundle>,
     uninitialized_inputs: HashSet<Target>,
     io_targets: HashMap<Target, CompiledValue<CanonicalType>>,
     made_initial_step: bool,
+    trace_decls: TraceModule,
+    traces: Interned<[SimTrace]>,
+    trace_writers: Vec<TraceWriterState<DynTraceWriterDecls>>,
 }
 
 impl SimulationImpl {
@@ -2853,6 +3320,9 @@ impl SimulationImpl {
             uninitialized_inputs: HashSet::new(),
             io_targets: HashMap::new(),
             made_initial_step: false,
+            trace_decls: compiled.trace_decls,
+            traces: compiled.traces,
+            trace_writers: vec![],
         };
         let io_target = Target::from(compiled.io);
         for (BundleField { name, .. }, value) in compiled
@@ -2991,6 +3461,72 @@ impl SimulationImpl {
             _ => unreachable!(),
         }
     }
+    fn close_all_trace_writers(&mut self) -> std::io::Result<()> {
+        let trace_writers = mem::take(&mut self.trace_writers);
+        let mut retval = Ok(());
+        let close_trace_writer =
+            |trace_writer: TraceWriterState<DynTraceWriterDecls>| match trace_writer {
+                TraceWriterState::Decls(v) => v.write_decls(self.trace_decls)?.close(),
+                TraceWriterState::Init(v) => v.close(),
+                TraceWriterState::Running(v) => v.close(),
+                TraceWriterState::Errored(Some(e)) => Err(e),
+                TraceWriterState::Errored(None) => Ok(()),
+            };
+        for trace_writer in trace_writers {
+            retval = retval.and(close_trace_writer(trace_writer));
+        }
+        retval
+    }
+    fn close(mut self) -> std::io::Result<()> {
+        self.close_all_trace_writers()
+    }
+    fn flush_traces(&mut self) -> std::io::Result<()> {
+        let flush_trace_writer = |trace_writer: TraceWriterState<DynTraceWriterDecls>| {
+            Ok(Some(match trace_writer {
+                TraceWriterState::Decls(v) => {
+                    let mut v = v.write_decls(self.trace_decls)?;
+                    v.flush()?;
+                    TraceWriterState::Init(v)
+                }
+                TraceWriterState::Init(mut v) => {
+                    v.flush()?;
+                    TraceWriterState::Init(v)
+                }
+                TraceWriterState::Running(mut v) => {
+                    v.flush()?;
+                    TraceWriterState::Running(v)
+                }
+                TraceWriterState::Errored(Some(e)) => return Err(e),
+                TraceWriterState::Errored(None) => return Ok(None),
+            }))
+        };
+        let mut retval = Ok(());
+        for trace_writer in &mut self.trace_writers {
+            *trace_writer = match flush_trace_writer(mem::replace(
+                trace_writer,
+                TraceWriterState::Errored(None),
+            )) {
+                Ok(Some(v)) => v,
+                Ok(None) => TraceWriterState::Errored(None),
+                Err(e) => {
+                    if retval.is_ok() {
+                        retval = Err(e);
+                        TraceWriterState::Errored(None)
+                    } else {
+                        TraceWriterState::Errored(Some(e))
+                    }
+                }
+            };
+        }
+        retval
+    }
+}
+
+impl Drop for SimulationImpl {
+    fn drop(&mut self) {
+        self.close_all_trace_writers()
+            .expect("error closing trace writers");
+    }
 }
 
 pub struct Simulation<T: BundleType> {
@@ -3048,6 +3584,9 @@ impl<T: BundleType> fmt::Debug for Simulation<T> {
                     uninitialized_inputs,
                     io_targets,
                     made_initial_step,
+                    trace_decls,
+                    traces,
+                    trace_writers,
                 },
             io,
         } = self;
@@ -3060,6 +3599,9 @@ impl<T: BundleType> fmt::Debug for Simulation<T> {
             )
             .field("io_targets", &SortedMapDebug(io_targets))
             .field("made_initial_step", made_initial_step)
+            .field("trace_decls", trace_decls)
+            .field("traces", traces)
+            .field("trace_writers", trace_writers)
             .finish()
     }
 }
@@ -3068,6 +3610,12 @@ impl<T: BundleType> Simulation<T> {
     pub fn new(module: Interned<Module<T>>) -> Self {
         Self::from_compiled(Compiled::new(module))
     }
+    pub fn flush_traces(&mut self) -> std::io::Result<()> {
+        self.sim_impl.flush_traces()
+    }
+    pub fn close(self) -> std::io::Result<()> {
+        self.sim_impl.close()
+    }
     pub fn canonical(self) -> Simulation<Bundle> {
         let Self { sim_impl, io } = self;
         Simulation {
diff --git a/crates/fayalite/src/sim/time.rs b/crates/fayalite/src/sim/time.rs
new file mode 100644
index 0000000..d548ab9
--- /dev/null
+++ b/crates/fayalite/src/sim/time.rs
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+use std::{fmt, time::Duration};
+
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Default)]
+pub struct SimInstant {
+    time_since_start: SimDuration,
+}
+
+impl fmt::Debug for SimInstant {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.time_since_start.fmt(f)
+    }
+}
+
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Default)]
+pub struct SimDuration {
+    attos: u128,
+}
+
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)]
+pub struct SimDurationParts {
+    pub attos: u16,
+    pub femtos: u16,
+    pub picos: u16,
+    pub nanos: u16,
+    pub micros: u16,
+    pub millis: u16,
+    pub secs: u128,
+}
+
+macro_rules! impl_duration_units {
+    (
+        $(
+            #[unit_const = $UNIT:ident, from_units = $from_units:ident, units = $units:ident, suffix = $suffix:literal]
+            const $log10_units_per_sec:ident: u32 = $log10_units_per_sec_value:expr;
+        )*
+    ) => {
+        impl SimDuration {
+            $(
+                const $log10_units_per_sec: u32 = $log10_units_per_sec_value;
+                pub const fn $from_units($units: u128) -> Self {
+                    Self::from_units_helper::<{ Self::$log10_units_per_sec }>($units)
+                }
+            )*
+            pub const fn into_parts(mut self) -> SimDurationParts {
+                $(
+                    let $units = self.attos / const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) };
+                    self.attos %= const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) };
+                )*
+                SimDurationParts {
+                    $($units: $units as _,)*
+                }
+            }
+            pub const fn from_parts_checked(parts: SimDurationParts) -> Option<Self> {
+                let attos = 0u128;
+                $(
+                    let Some(product) = const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) }.checked_mul(parts.$units as u128) else {
+                        return None;
+                    };
+                    let Some(attos) = attos.checked_add(product) else {
+                        return None;
+                    };
+                )*
+                Some(Self {
+                    attos,
+                })
+            }
+        }
+
+        impl fmt::Debug for SimDuration {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                let ilog10_attos = match self.attos.checked_ilog10() {
+                    Some(v) => v,
+                    None => Self::LOG10_ATTOS_PER_SEC,
+                };
+                let (suffix, int, fraction, fraction_digits) =
+                    match Self::LOG10_ATTOS_PER_SEC.saturating_sub(ilog10_attos) {
+                    $(
+                        ..=Self::$log10_units_per_sec => {
+                            let divisor = const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) };
+                            (
+                                $suffix,
+                                self.attos / divisor,
+                                self.attos % divisor,
+                                (Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) as usize,
+                            )
+                        },
+                    )*
+                    _ => unreachable!(),
+                };
+                write!(f, "{int}")?;
+                if fraction != 0 {
+                    write!(f, ".{fraction:0fraction_digits$}")?;
+                }
+                write!(f, " {suffix}")
+            }
+        }
+
+        #[cfg(test)]
+        #[test]
+        fn test_duration_debug() {
+            $(
+                assert_eq!(
+                    format!("{:?}", SimDuration::$from_units(123)),
+                    concat!("123 ", $suffix)
+                );
+                assert_eq!(
+                    format!("{:?}", SimDuration::$from_units(1)),
+                    concat!("1 ", $suffix),
+                );
+                let mut v = SimDuration::$from_units(1);
+                if v.attos < 1 << 53 {
+                    v.attos += 1;
+                    assert_eq!(
+                        format!("{v:?}"),
+                        format!("{} {}", v.attos as f64 / 10.0f64.powf((SimDuration::LOG10_ATTOS_PER_SEC - SimDuration::$log10_units_per_sec) as f64), $suffix),
+                        "1 {} + 1 as == {} as", $suffix, v.attos,
+                    );
+                }
+            )*
+        }
+    };
+}
+
+impl_duration_units! {
+    #[unit_const = SECOND, from_units = from_secs, units = secs, suffix = "s"]
+    const LOG10_SECS_PER_SEC: u32 = 0;
+    #[unit_const = MILLISECOND, from_units = from_millis, units = millis, suffix = "ms"]
+    const LOG10_MILLIS_PER_SEC: u32 = 3;
+    #[unit_const = MICROSECOND, from_units = from_micros, units = micros, suffix = "μs"]
+    const LOG10_MICROS_PER_SEC: u32 = 6;
+    #[unit_const = NANOSECOND, from_units = from_nanos, units = nanos, suffix = "ns"]
+    const LOG10_NANOS_PER_SEC: u32 = 9;
+    #[unit_const = PICOSECOND, from_units = from_picos, units = picos, suffix = "ps"]
+    const LOG10_PICOS_PER_SEC: u32 = 12;
+    #[unit_const = FEMTOSECOND, from_units = from_femtos, units = femtos, suffix = "fs"]
+    const LOG10_FEMTOS_PER_SEC: u32 = 15;
+    #[unit_const = ATTOSECOND, from_units = from_attos, units = attos, suffix = "as"]
+    const LOG10_ATTOS_PER_SEC: u32 = 18;
+}
+
+impl SimDuration {
+    const fn from_units_helper<const UNITS_PER_SEC: u32>(units: u128) -> Self {
+        let Some(attos) =
+            units.checked_mul(const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - UNITS_PER_SEC) })
+        else {
+            panic!("duration too big");
+        };
+        Self { attos }
+    }
+    pub const ZERO: SimDuration = SimDuration::from_secs(0);
+    pub const fn from_parts(parts: SimDurationParts) -> Self {
+        match Self::from_parts_checked(parts) {
+            Some(v) => v,
+            None => panic!("duration too big"),
+        }
+    }
+}
+
+impl From<Duration> for SimDuration {
+    fn from(duration: Duration) -> Self {
+        Self::from_nanos(duration.as_nanos())
+    }
+}
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 1696d6a..fef71e5 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -115,6 +115,12 @@ fn test_connect_const() {
         },
     },
     made_initial_step: true,
+    trace_decls: TraceModule {
+        name: "connect_const",
+        children: [],
+    },
+    traces: [],
+    trace_writers: [],
 }"# {
         panic!();
     }
@@ -673,6 +679,12 @@ fn test_mod1() {
         },
     },
     made_initial_step: true,
+    trace_decls: TraceModule {
+        name: "mod1",
+        children: [],
+    },
+    traces: [],
+    trace_writers: [],
 }"# {
         panic!();
     }

From 09aa9fbc786ee8205c90c5781a608bd9bdba3ee8 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 17 Nov 2024 21:02:44 -0800
Subject: [PATCH 090/190] wire up simulator trace writing interface

---
 crates/fayalite/src/expr/target.rs     |  10 +-
 crates/fayalite/src/sim.rs             | 832 ++++++++++++++++++++-----
 crates/fayalite/src/sim/interpreter.rs |  28 +-
 crates/fayalite/src/sim/time.rs        |  54 +-
 crates/fayalite/src/util/misc.rs       |   8 +-
 crates/fayalite/tests/sim.rs           | 298 ++++++++-
 6 files changed, 1046 insertions(+), 184 deletions(-)

diff --git a/crates/fayalite/src/expr/target.rs b/crates/fayalite/src/expr/target.rs
index e95ff84..849be00 100644
--- a/crates/fayalite/src/expr/target.rs
+++ b/crates/fayalite/src/expr/target.rs
@@ -14,7 +14,7 @@ use crate::{
 };
 use std::fmt;
 
-#[derive(Debug, Clone, PartialEq, Eq, Hash)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
 pub struct TargetPathBundleField {
     pub name: Interned<str>,
 }
@@ -25,7 +25,7 @@ impl fmt::Display for TargetPathBundleField {
     }
 }
 
-#[derive(Debug, Clone, PartialEq, Eq, Hash)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
 pub struct TargetPathArrayElement {
     pub index: usize,
 }
@@ -36,7 +36,7 @@ impl fmt::Display for TargetPathArrayElement {
     }
 }
 
-#[derive(Debug, Clone, PartialEq, Eq, Hash)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
 pub struct TargetPathDynArrayElement {}
 
 impl fmt::Display for TargetPathDynArrayElement {
@@ -45,7 +45,7 @@ impl fmt::Display for TargetPathDynArrayElement {
     }
 }
 
-#[derive(Debug, Clone, PartialEq, Eq, Hash)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
 pub enum TargetPathElement {
     BundleField(TargetPathBundleField),
     ArrayElement(TargetPathArrayElement),
@@ -197,7 +197,7 @@ macro_rules! impl_target_base {
 }
 
 impl_target_base! {
-    #[derive(Clone, PartialEq, Eq, Hash)]
+    #[derive(Copy, Clone, PartialEq, Eq, Hash)]
     pub enum TargetBase {
         #[is = is_module_io]
         #[to = module_io]
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 2eed11c..d33b0bb 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -30,15 +30,15 @@ use crate::{
             TypeArrayIndex, TypeArrayIndexes, TypeIndex, TypeIndexRange, TypeLayout, TypeLen,
             TypeParts,
         },
-        time::SimInstant,
+        time::{SimDuration, SimInstant},
     },
     ty::StaticType,
-    util::DebugAsDisplay,
+    util::{BitSliceWriteWithBase, DebugAsDisplay},
 };
-use bitvec::{bits, order::Lsb0, slice::BitSlice};
+use bitvec::{bits, order::Lsb0, slice::BitSlice, vec::BitVec};
 use hashbrown::{HashMap, HashSet};
 use num_bigint::BigInt;
-use num_traits::ToPrimitive;
+use num_traits::{Signed, ToPrimitive, Zero};
 use petgraph::visit::{
     GraphBase, IntoNeighbors, IntoNeighborsDirected, IntoNodeIdentifiers, VisitMap, Visitable,
 };
@@ -1232,6 +1232,7 @@ pub struct Compiler {
     compiled_values_to_dyn_array_indexes:
         HashMap<CompiledValue<UInt>, StatePartIndex<StatePartKindSmallSlots>>,
     assignments: Assignments,
+    traces: Vec<SimTrace<()>>,
 }
 
 impl Compiler {
@@ -1246,6 +1247,228 @@ impl Compiler {
             decl_conditions: HashMap::new(),
             compiled_values_to_dyn_array_indexes: HashMap::new(),
             assignments: Assignments::default(),
+            traces: Vec::new(),
+        }
+    }
+    fn new_sim_trace(&mut self, kind: SimTraceKind) -> TraceScalarId {
+        let id = TraceScalarId(self.traces.len());
+        self.traces.push(SimTrace {
+            id,
+            kind,
+            state: (),
+            last_state: (),
+        });
+        id
+    }
+    fn make_trace_scalar_helper(
+        &mut self,
+        target: TargetInInstantiatedModule,
+        small_kind: impl FnOnce(StatePartIndex<StatePartKindSmallSlots>) -> SimTraceKind,
+        big_kind: impl FnOnce(StatePartIndex<StatePartKindBigSlots>) -> SimTraceKind,
+    ) -> TraceScalarId {
+        let compiled_value = self.compile_value(target);
+        self.new_sim_trace(match compiled_value.range.len() {
+            TypeLen::A_SMALL_SLOT => small_kind(compiled_value.range.small_slots.start),
+            TypeLen::A_BIG_SLOT => big_kind(compiled_value.range.big_slots.start),
+            _ => unreachable!(),
+        })
+    }
+    fn make_trace_scalar(
+        &mut self,
+        target: TargetInInstantiatedModule,
+        name: Interned<str>,
+    ) -> TraceDecl {
+        let flow = target.target.flow();
+        match target.target.canonical_ty() {
+            CanonicalType::UInt(ty) => TraceUInt {
+                id: self.make_trace_scalar_helper(
+                    target,
+                    |index| SimTraceKind::SmallUInt { index, ty },
+                    |index| SimTraceKind::BigUInt { index, ty },
+                ),
+                name,
+                ty,
+                flow,
+            }
+            .into(),
+            CanonicalType::SInt(ty) => TraceSInt {
+                id: self.make_trace_scalar_helper(
+                    target,
+                    |index| SimTraceKind::SmallSInt { index, ty },
+                    |index| SimTraceKind::BigSInt { index, ty },
+                ),
+                name,
+                ty,
+                flow,
+            }
+            .into(),
+            CanonicalType::Bool(ty) => TraceBool {
+                id: self.make_trace_scalar_helper(
+                    target,
+                    |index| SimTraceKind::SmallBool { index },
+                    |index| SimTraceKind::BigBool { index },
+                ),
+                name,
+                flow,
+            }
+            .into(),
+            CanonicalType::Array(ty) => unreachable!(),
+            CanonicalType::Enum(ty) => todo!(),
+            CanonicalType::Bundle(ty) => unreachable!(),
+            CanonicalType::AsyncReset(ty) => TraceAsyncReset {
+                id: self.make_trace_scalar_helper(
+                    target,
+                    |index| SimTraceKind::SmallAsyncReset { index },
+                    |index| SimTraceKind::BigAsyncReset { index },
+                ),
+                name,
+                flow,
+            }
+            .into(),
+            CanonicalType::SyncReset(ty) => TraceSyncReset {
+                id: self.make_trace_scalar_helper(
+                    target,
+                    |index| SimTraceKind::SmallSyncReset { index },
+                    |index| SimTraceKind::BigSyncReset { index },
+                ),
+                name,
+                flow,
+            }
+            .into(),
+            CanonicalType::Reset(ty) => todo!(),
+            CanonicalType::Clock(ty) => TraceClock {
+                id: self.make_trace_scalar_helper(
+                    target,
+                    |index| SimTraceKind::SmallClock { index },
+                    |index| SimTraceKind::BigClock { index },
+                ),
+                name,
+                flow,
+            }
+            .into(),
+        }
+    }
+    fn make_trace_decl_child(
+        &mut self,
+        target: TargetInInstantiatedModule,
+        name: Interned<str>,
+    ) -> TraceDecl {
+        match target.target.canonical_ty() {
+            CanonicalType::Array(ty) => {
+                let elements = Interned::from_iter((0..ty.len()).map(|index| {
+                    self.make_trace_decl_child(
+                        TargetInInstantiatedModule {
+                            instantiated_module: target.instantiated_module,
+                            target: target.target.join(
+                                TargetPathElement::from(TargetPathArrayElement { index })
+                                    .intern_sized(),
+                            ),
+                        },
+                        Intern::intern_owned(format!("[{index}]")),
+                    )
+                }));
+                TraceArray {
+                    name,
+                    elements,
+                    ty,
+                    flow: target.target.flow(),
+                }
+                .into()
+            }
+            CanonicalType::Enum(ty) => todo!(),
+            CanonicalType::Bundle(ty) => {
+                let fields = Interned::from_iter(ty.fields().iter().map(|field| {
+                    self.make_trace_decl_child(
+                        TargetInInstantiatedModule {
+                            instantiated_module: target.instantiated_module,
+                            target: target.target.join(
+                                TargetPathElement::from(TargetPathBundleField { name: field.name })
+                                    .intern_sized(),
+                            ),
+                        },
+                        field.name,
+                    )
+                }));
+                TraceBundle {
+                    name,
+                    fields,
+                    ty,
+                    flow: target.target.flow(),
+                }
+                .into()
+            }
+            CanonicalType::UInt(_)
+            | CanonicalType::SInt(_)
+            | CanonicalType::Bool(_)
+            | CanonicalType::AsyncReset(_)
+            | CanonicalType::SyncReset(_)
+            | CanonicalType::Reset(_)
+            | CanonicalType::Clock(_) => self.make_trace_scalar(target, name),
+        }
+    }
+    fn make_trace_decl(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        target_base: TargetBase,
+    ) -> TraceDecl {
+        let target = TargetInInstantiatedModule {
+            instantiated_module,
+            target: target_base.into(),
+        };
+        match target_base {
+            TargetBase::ModuleIO(module_io) => TraceModuleIO {
+                name: module_io.name(),
+                child: self
+                    .make_trace_decl_child(target, module_io.name())
+                    .intern(),
+                ty: module_io.ty(),
+                flow: module_io.flow(),
+            }
+            .into(),
+            TargetBase::MemPort(mem_port) => {
+                let name = Intern::intern_owned(mem_port.port_name().to_string());
+                let TraceDecl::Scope(TraceScope::Bundle(bundle)) =
+                    self.make_trace_decl_child(target, name)
+                else {
+                    unreachable!()
+                };
+                TraceMemPort {
+                    name,
+                    bundle,
+                    ty: mem_port.ty(),
+                }
+                .into()
+            }
+            TargetBase::Reg(reg) => TraceReg {
+                name: reg.name(),
+                child: self.make_trace_decl_child(target, reg.name()).intern(),
+                ty: reg.ty(),
+            }
+            .into(),
+            TargetBase::Wire(wire) => TraceWire {
+                name: wire.name(),
+                child: self.make_trace_decl_child(target, wire.name()).intern(),
+                ty: wire.ty(),
+            }
+            .into(),
+            TargetBase::Instance(instance) => {
+                let TraceDecl::Scope(TraceScope::Bundle(instance_io)) =
+                    self.make_trace_decl_child(target, instance.name())
+                else {
+                    unreachable!()
+                };
+                let compiled_module = &self.modules[&InstantiatedModule::Child {
+                    parent: target.instantiated_module.intern(),
+                    instance: instance.intern(),
+                }];
+                TraceInstance {
+                    name: instance.name(),
+                    instance_io,
+                    module: compiled_module.trace_decls,
+                    ty: instance.ty(),
+                }
+                .into()
+            }
         }
     }
     fn compile_value(
@@ -1434,30 +1657,8 @@ impl Compiler {
             return retval;
         }
         let retval = match compiled_value.range.len() {
-            TypeLen {
-                small_slots:
-                    StatePartLen {
-                        value: 1,
-                        _phantom: _,
-                    },
-                big_slots:
-                    StatePartLen {
-                        value: 0,
-                        _phantom: _,
-                    },
-            } => compiled_value.range.small_slots.start,
-            TypeLen {
-                small_slots:
-                    StatePartLen {
-                        value: 0,
-                        _phantom: _,
-                    },
-                big_slots:
-                    StatePartLen {
-                        value: 1,
-                        _phantom: _,
-                    },
-            } => {
+            TypeLen::A_SMALL_SLOT => compiled_value.range.small_slots.start,
+            TypeLen::A_BIG_SLOT => {
                 let debug_data = SlotDebugData {
                     name: Interned::default(),
                     ty: UInt::<{ SmallUInt::BITS as usize }>::TYPE.canonical(),
@@ -2441,7 +2642,7 @@ impl Compiler {
         declaration: StmtDeclaration,
         parent_module: Interned<InstantiatedModule>,
         conditions: Interned<[Cond]>,
-    ) {
+    ) -> TraceDecl {
         let target_base: TargetBase = match &declaration {
             StmtDeclaration::Wire(v) => v.wire.into(),
             StmtDeclaration::Reg(v) => v.reg.into(),
@@ -2506,12 +2707,14 @@ impl Compiler {
                 }
             }
         }
+        self.make_trace_decl(*parent_module, target_base)
     }
     fn compile_block(
         &mut self,
         parent_module: Interned<InstantiatedModule>,
         block: Block,
         conditions: Interned<[Cond]>,
+        trace_decls: &mut Vec<TraceDecl>,
     ) {
         let Block { memories, stmts } = block;
         for memory in memories {
@@ -2548,6 +2751,7 @@ impl Compiler {
                             body: CondBody::IfTrue { cond },
                             source_location,
                         }])),
+                        trace_decls,
                     );
                     self.compile_block(
                         parent_module,
@@ -2556,6 +2760,7 @@ impl Compiler {
                             body: CondBody::IfFalse { cond },
                             source_location,
                         }])),
+                        trace_decls,
                     );
                 }
                 Stmt::Match(StmtMatch {
@@ -2577,16 +2782,22 @@ impl Compiler {
                                 },
                                 source_location,
                             }])),
+                            trace_decls,
                         );
                     }
                 }
                 Stmt::Declaration(declaration) => {
-                    self.compile_declaration(declaration, parent_module, conditions);
+                    trace_decls.push(self.compile_declaration(
+                        declaration,
+                        parent_module,
+                        conditions,
+                    ));
                 }
             }
         }
     }
     fn compile_module(&mut self, module: Interned<InstantiatedModule>) -> &CompiledModule {
+        let mut trace_decls = Vec::new();
         let module_io = module
             .leaf_module()
             .module_io()
@@ -2601,13 +2812,14 @@ impl Compiler {
                         target: Target::from(module_io),
                     };
                     self.decl_conditions.insert(target, Interned::default());
+                    trace_decls.push(self.make_trace_decl(*module, module_io.into()));
                     self.compile_value(target)
                 },
             )
             .collect();
         match module.leaf_module().body() {
             ModuleBody::Normal(NormalModuleBody { body }) => {
-                self.compile_block(module, body, Interned::default());
+                self.compile_block(module, body, Interned::default(), &mut trace_decls);
             }
             ModuleBody::Extern(_extern_module_body) => {
                 todo!("simulating extern module: {:?}", module);
@@ -2616,7 +2828,13 @@ impl Compiler {
         let hashbrown::hash_map::Entry::Vacant(entry) = self.modules.entry(*module) else {
             unreachable!("compiled same instantiated module twice");
         };
-        entry.insert(CompiledModule { module_io })
+        entry.insert(CompiledModule {
+            module_io,
+            trace_decls: TraceModule {
+                name: module.leaf_module().name(),
+                children: Intern::intern_owned(trace_decls),
+            },
+        })
     }
     fn process_assignments(&mut self) {
         self.assignments
@@ -2677,18 +2895,7 @@ impl Compiler {
                     CondBody::IfTrue { cond: cond_value }
                     | CondBody::IfFalse { cond: cond_value } => {
                         let (branch_if_zero, branch_if_non_zero) = match cond_value.range.len() {
-                            TypeLen {
-                                small_slots:
-                                    StatePartLen {
-                                        value: 1,
-                                        _phantom: _,
-                                    },
-                                big_slots:
-                                    StatePartLen {
-                                        value: 0,
-                                        _phantom: _,
-                                    },
-                            } => (
+                            TypeLen::A_SMALL_SLOT => (
                                 Insn::BranchIfSmallZero {
                                     target: end_label_index,
                                     value: cond_value.range.small_slots.start,
@@ -2698,18 +2905,7 @@ impl Compiler {
                                     value: cond_value.range.small_slots.start,
                                 },
                             ),
-                            TypeLen {
-                                small_slots:
-                                    StatePartLen {
-                                        value: 0,
-                                        _phantom: _,
-                                    },
-                                big_slots:
-                                    StatePartLen {
-                                        value: 1,
-                                        _phantom: _,
-                                    },
-                            } => (
+                            TypeLen::A_BIG_SLOT => (
                                 Insn::BranchIfZero {
                                     target: end_label_index,
                                     value: cond_value.range.big_slots.start,
@@ -2762,11 +2958,7 @@ impl Compiler {
                 self.base_module,
                 self.base_module.source_location(),
             ),
-            trace_decls: TraceModule {
-                name: self.base_module.name(),
-                children: Interned::default(), // TODO: finish
-            },
-            traces: Interned::default(), // TODO: finish
+            traces: Intern::intern_owned(self.traces),
         }
     }
 }
@@ -2774,6 +2966,7 @@ impl Compiler {
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
 struct CompiledModule {
     module_io: Interned<[CompiledValue<CanonicalType>]>,
+    trace_decls: TraceModule,
 }
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
@@ -2781,8 +2974,7 @@ pub struct Compiled<T: BundleType> {
     insns: Interned<Insns<InsnsBuildingDone>>,
     base_module: CompiledModule,
     io: Instance<T>,
-    trace_decls: TraceModule,
-    traces: Interned<[SimTrace]>,
+    traces: Interned<[SimTrace<()>]>,
 }
 
 impl<T: BundleType> Compiled<T> {
@@ -2794,14 +2986,12 @@ impl<T: BundleType> Compiled<T> {
             insns,
             base_module,
             io,
-            trace_decls,
             traces,
         } = self;
         Compiled {
             insns,
             base_module,
             io: Instance::from_canonical(io.canonical()),
-            trace_decls,
             traces,
         }
     }
@@ -2810,22 +3000,26 @@ impl<T: BundleType> Compiled<T> {
             insns,
             base_module,
             io,
-            trace_decls,
             traces,
         } = canonical;
         Self {
             insns,
             base_module,
             io: Instance::from_canonical(io.canonical()),
-            trace_decls,
             traces,
         }
     }
 }
 
-#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
 pub struct TraceScalarId(usize);
 
+impl fmt::Debug for TraceScalarId {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "TraceScalarId({})", self.0)
+    }
+}
+
 impl TraceScalarId {
     pub fn as_usize(self) -> usize {
         self.0
@@ -2865,7 +3059,7 @@ macro_rules! impl_trace_decl {
                 }
             }
 
-            #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+            #[derive(Copy, Clone, PartialEq, Eq, Hash)]
             #[non_exhaustive]
             $(#[$category_meta])*
             pub enum $category_enum {
@@ -2873,6 +3067,14 @@ macro_rules! impl_trace_decl {
                 $variant($struct),)*
             }
 
+            impl fmt::Debug for $category_enum {
+                fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                    match *self {
+                        $(Self::$variant(v) => v.fmt(f),)*
+                    }
+                }
+            }
+
             impl $category_enum {
                 pub fn kind(self) -> $category_kind {
                     match self {
@@ -2924,17 +3126,33 @@ macro_rules! impl_trace_decl {
             )*
         )*
 
-        #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
+        #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
         pub enum TraceKind {
             $($(#[$category_meta])*
             $category_variant($category_kind),)*
         }
 
-        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        impl fmt::Debug for TraceKind {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                match *self {
+                    $(Self::$category_variant(v) => v.fmt(f),)*
+                }
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash)]
         pub enum TraceDecl {
             $($(#[$category_meta])*
             $category_variant($category_enum),)*
         }
+
+        impl fmt::Debug for TraceDecl {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                match *self {
+                    $(Self::$category_variant(v) => v.fmt(f),)*
+                }
+            }
+        }
     };
 }
 
@@ -2951,46 +3169,71 @@ impl_trace_decl! {
         }),
         Instance(TraceInstance {
             fn children(self) -> _ {
-                self.children
+                [self.instance_io.into(), self.module.into()][..].intern()
             }
             name: Interned<str>,
-            children: Interned<[TraceDecl]>,
+            instance_io: TraceBundle,
+            module: TraceModule,
             ty: Bundle,
-            flow: Flow,
+        }),
+        MemPort(TraceMemPort {
+            fn children(self) -> _ {
+                [self.bundle.into()][..].intern()
+            }
+            name: Interned<str>,
+            bundle: TraceBundle,
+            ty: Bundle,
+        }),
+        Wire(TraceWire {
+            fn children(self) -> _ {
+                [*self.child][..].intern()
+            }
+            name: Interned<str>,
+            child: Interned<TraceDecl>,
+            ty: CanonicalType,
+        }),
+        Reg(TraceReg {
+            fn children(self) -> _ {
+                [*self.child][..].intern()
+            }
+            name: Interned<str>,
+            child: Interned<TraceDecl>,
+            ty: CanonicalType,
         }),
         ModuleIO(TraceModuleIO {
             fn children(self) -> _ {
-                self.children
+                [*self.child][..].intern()
             }
             name: Interned<str>,
-            children: Interned<[TraceDecl]>,
-            ty: Bundle,
+            child: Interned<TraceDecl>,
+            ty: CanonicalType,
             flow: Flow,
         }),
         Bundle(TraceBundle {
             fn children(self) -> _ {
-                self.children
+                self.fields
             }
             name: Interned<str>,
-            children: Interned<[TraceDecl]>,
+            fields: Interned<[TraceDecl]>,
             ty: Bundle,
             flow: Flow,
         }),
         Array(TraceArray {
             fn children(self) -> _ {
-                self.children
+                self.elements
             }
             name: Interned<str>,
-            children: Interned<[TraceDecl]>,
+            elements: Interned<[TraceDecl]>,
             ty: Array,
             flow: Flow,
         }),
         EnumWithFields(TraceEnumWithFields {
             fn children(self) -> _ {
-                self.children
+                Interned::from_iter([self.discriminant.into()].into_iter().chain(self.non_empty_fields))
             }
             name: Interned<str>,
-            children: Interned<[TraceDecl]>,
+            discriminant: TraceEnumDiscriminant,
+            non_empty_fields: Interned<[TraceDecl]>,
             ty: Enum,
             flow: Flow,
         }),
@@ -3022,7 +3265,6 @@ impl_trace_decl! {
             }
             id: TraceScalarId,
             name: Interned<str>,
-            ty: Bool,
             flow: Flow,
         }),
         FieldlessEnum(TraceFieldlessEnum {
@@ -3049,7 +3291,6 @@ impl_trace_decl! {
             }
             id: TraceScalarId,
             name: Interned<str>,
-            ty: Clock,
             flow: Flow,
         }),
         SyncReset(TraceSyncReset {
@@ -3058,7 +3299,6 @@ impl_trace_decl! {
             }
             id: TraceScalarId,
             name: Interned<str>,
-            ty: SyncReset,
             flow: Flow,
         }),
         AsyncReset(TraceAsyncReset {
@@ -3067,7 +3307,6 @@ impl_trace_decl! {
             }
             id: TraceScalarId,
             name: Interned<str>,
-            ty: AsyncReset,
             flow: Flow,
         }),
     }),
@@ -3142,6 +3381,12 @@ pub trait TraceWriter: fmt::Debug + 'static {
 
 pub struct DynTraceWriterDecls(Box<dyn TraceWriterDeclsDynTrait>);
 
+impl DynTraceWriterDecls {
+    pub fn new<W: TraceWriterDecls>(writer: W) -> Self {
+        Self(Box::new(writer))
+    }
+}
+
 impl fmt::Debug for DynTraceWriterDecls {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         self.0.fmt(f)
@@ -3261,9 +3506,111 @@ enum TraceWriterState<T: TraceWriterDecls> {
     Errored(Option<T::Error>),
 }
 
-#[derive(Clone, PartialEq, Eq, Hash, Debug)]
-struct SimTrace {
+#[derive(Clone, PartialEq, Eq, Hash)]
+struct SimTrace<S> {
     id: TraceScalarId,
+    kind: SimTraceKind,
+    state: S,
+    last_state: S,
+}
+
+impl fmt::Debug for SimTrace<()> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            id,
+            kind,
+            state,
+            last_state,
+        } = self;
+        f.debug_struct("SimTrace")
+            .field("id", id)
+            .field("kind", kind)
+            .field("state", state)
+            .field("last_state", last_state)
+            .finish()
+    }
+}
+
+impl fmt::Debug for SimTrace<BitVec> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            id,
+            kind,
+            state,
+            last_state,
+        } = self;
+        f.debug_struct("SimTrace")
+            .field("id", id)
+            .field("kind", kind)
+            .field("state", &BitSliceWriteWithBase(state))
+            .field("last_state", &BitSliceWriteWithBase(last_state))
+            .finish()
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+enum SimTraceKind {
+    BigUInt {
+        index: StatePartIndex<StatePartKindBigSlots>,
+        ty: UInt,
+    },
+    BigSInt {
+        index: StatePartIndex<StatePartKindBigSlots>,
+        ty: SInt,
+    },
+    BigBool {
+        index: StatePartIndex<StatePartKindBigSlots>,
+    },
+    BigAsyncReset {
+        index: StatePartIndex<StatePartKindBigSlots>,
+    },
+    BigSyncReset {
+        index: StatePartIndex<StatePartKindBigSlots>,
+    },
+    BigClock {
+        index: StatePartIndex<StatePartKindBigSlots>,
+    },
+    SmallUInt {
+        index: StatePartIndex<StatePartKindSmallSlots>,
+        ty: UInt,
+    },
+    SmallSInt {
+        index: StatePartIndex<StatePartKindSmallSlots>,
+        ty: SInt,
+    },
+    SmallBool {
+        index: StatePartIndex<StatePartKindSmallSlots>,
+    },
+    SmallAsyncReset {
+        index: StatePartIndex<StatePartKindSmallSlots>,
+    },
+    SmallSyncReset {
+        index: StatePartIndex<StatePartKindSmallSlots>,
+    },
+    SmallClock {
+        index: StatePartIndex<StatePartKindSmallSlots>,
+    },
+}
+
+impl SimTraceKind {
+    fn make_state(self) -> BitVec {
+        match self {
+            SimTraceKind::BigUInt { index: _, ty } | SimTraceKind::SmallUInt { index: _, ty } => {
+                BitVec::repeat(false, ty.width)
+            }
+            SimTraceKind::BigSInt { index: _, ty } | SimTraceKind::SmallSInt { index: _, ty } => {
+                BitVec::repeat(false, ty.width)
+            }
+            SimTraceKind::BigBool { index: _ }
+            | SimTraceKind::BigAsyncReset { index: _ }
+            | SimTraceKind::BigSyncReset { index: _ }
+            | SimTraceKind::BigClock { index: _ }
+            | SimTraceKind::SmallBool { index: _ }
+            | SimTraceKind::SmallAsyncReset { index: _ }
+            | SimTraceKind::SmallSyncReset { index: _ }
+            | SimTraceKind::SmallClock { index: _ } => BitVec::repeat(false, 1),
+        }
+    }
 }
 
 struct SimulationImpl {
@@ -3273,8 +3620,9 @@ struct SimulationImpl {
     io_targets: HashMap<Target, CompiledValue<CanonicalType>>,
     made_initial_step: bool,
     trace_decls: TraceModule,
-    traces: Interned<[SimTrace]>,
+    traces: Box<[SimTrace<BitVec>]>,
     trace_writers: Vec<TraceWriterState<DynTraceWriterDecls>>,
+    instant: SimInstant,
 }
 
 impl SimulationImpl {
@@ -3320,9 +3668,22 @@ impl SimulationImpl {
             uninitialized_inputs: HashSet::new(),
             io_targets: HashMap::new(),
             made_initial_step: false,
-            trace_decls: compiled.trace_decls,
-            traces: compiled.traces,
+            trace_decls: compiled.base_module.trace_decls,
+            traces: Box::from_iter(compiled.traces.iter().map(
+                |&SimTrace {
+                     id,
+                     kind,
+                     state: _,
+                     last_state: _,
+                 }| SimTrace {
+                    id,
+                    kind,
+                    state: kind.make_state(),
+                    last_state: kind.make_state(),
+                },
+            )),
             trace_writers: vec![],
+            instant: SimInstant::START,
         };
         let io_target = Target::from(compiled.io);
         for (BundleField { name, .. }, value) in compiled
@@ -3340,6 +3701,123 @@ impl SimulationImpl {
         }
         retval
     }
+    fn write_traces<const ONLY_IF_CHANGED: bool>(
+        &mut self,
+        mut trace_writer: DynTraceWriter,
+    ) -> std::io::Result<DynTraceWriter> {
+        for &SimTrace {
+            id,
+            kind,
+            ref state,
+            ref last_state,
+        } in &self.traces
+        {
+            if ONLY_IF_CHANGED && state == last_state {
+                continue;
+            }
+            match kind {
+                SimTraceKind::BigUInt { .. } | SimTraceKind::SmallUInt { .. } => {
+                    trace_writer.set_signal_uint(id, state)?;
+                }
+                SimTraceKind::BigSInt { .. } | SimTraceKind::SmallSInt { .. } => {
+                    trace_writer.set_signal_sint(id, state)?;
+                }
+                SimTraceKind::BigBool { .. } | SimTraceKind::SmallBool { .. } => {
+                    trace_writer.set_signal_bool(id, state[0])?;
+                }
+                SimTraceKind::BigAsyncReset { .. } | SimTraceKind::SmallAsyncReset { .. } => {
+                    trace_writer.set_signal_async_reset(id, state[0])?;
+                }
+                SimTraceKind::BigSyncReset { .. } | SimTraceKind::SmallSyncReset { .. } => {
+                    trace_writer.set_signal_sync_reset(id, state[0])?;
+                }
+                SimTraceKind::BigClock { .. } | SimTraceKind::SmallClock { .. } => {
+                    trace_writer.set_signal_clock(id, state[0])?;
+                }
+            }
+        }
+        Ok(trace_writer)
+    }
+    fn init_trace_writer(
+        &mut self,
+        trace_writer: DynTraceWriter,
+    ) -> std::io::Result<DynTraceWriter> {
+        let mut trace_writer = self.write_traces::<false>(trace_writer)?;
+        trace_writer.finish_init()?;
+        Ok(trace_writer)
+    }
+    fn update_trace_writer(
+        &mut self,
+        trace_writer: DynTraceWriter,
+    ) -> std::io::Result<DynTraceWriter> {
+        self.write_traces::<true>(trace_writer)
+    }
+    #[inline(never)]
+    fn read_traces<const IS_INITIAL_STEP: bool>(&mut self) {
+        for &mut SimTrace {
+            id: _,
+            kind,
+            ref mut state,
+            ref mut last_state,
+        } in &mut self.traces
+        {
+            if !IS_INITIAL_STEP {
+                mem::swap(state, last_state);
+            }
+            match kind {
+                SimTraceKind::BigUInt { index, ty: _ } | SimTraceKind::BigSInt { index, ty: _ } => {
+                    let bigint = &self.state.big_slots[index];
+                    let mut bytes = bigint.to_signed_bytes_le();
+                    bytes.resize(
+                        state.len().div_ceil(8),
+                        if bigint.is_negative() { 0xFF } else { 0 },
+                    );
+                    let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
+                    let bitslice = &bitslice[..state.len()];
+                    state.clone_from_bitslice(bitslice);
+                }
+                SimTraceKind::BigBool { index }
+                | SimTraceKind::BigAsyncReset { index }
+                | SimTraceKind::BigSyncReset { index }
+                | SimTraceKind::BigClock { index } => {
+                    state.set(0, !self.state.big_slots[index].is_zero());
+                }
+                SimTraceKind::SmallUInt { index, ty: _ }
+                | SimTraceKind::SmallSInt { index, ty: _ } => {
+                    let bytes = self.state.small_slots[index].to_le_bytes();
+                    let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
+                    let bitslice = &bitslice[..state.len()];
+                    state.clone_from_bitslice(bitslice);
+                }
+                SimTraceKind::SmallBool { index }
+                | SimTraceKind::SmallAsyncReset { index }
+                | SimTraceKind::SmallSyncReset { index }
+                | SimTraceKind::SmallClock { index } => {
+                    state.set(0, self.state.small_slots[index] != 0);
+                }
+            }
+            if IS_INITIAL_STEP {
+                last_state.copy_from_bitslice(state);
+            }
+        }
+    }
+    #[track_caller]
+    fn advance_time(&mut self, duration: SimDuration) {
+        if !self.made_initial_step {
+            self.settle_step();
+        }
+        self.instant += duration;
+        self.for_each_trace_writer_storing_error(|this, mut trace_writer_state| {
+            match &mut trace_writer_state {
+                TraceWriterState::Decls(_) | TraceWriterState::Init(_) => unreachable!(),
+                TraceWriterState::Running(trace_writer) => {
+                    trace_writer.change_time_to(this.instant)?;
+                }
+                TraceWriterState::Errored(_) => {}
+            }
+            Ok(trace_writer_state)
+        });
+    }
     #[track_caller]
     fn settle_step(&mut self) {
         assert!(
@@ -3348,7 +3826,26 @@ impl SimulationImpl {
         );
         self.state.setup_call(0);
         self.state.run();
+        if self.made_initial_step {
+            self.read_traces::<false>();
+        } else {
+            self.read_traces::<true>();
+        }
         self.made_initial_step = true;
+        self.for_each_trace_writer_storing_error(|this, trace_writer_state| {
+            Ok(match trace_writer_state {
+                TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running(
+                    this.init_trace_writer(trace_writer_decls.write_decls(this.trace_decls)?)?,
+                ),
+                TraceWriterState::Init(trace_writer) => {
+                    TraceWriterState::Running(this.init_trace_writer(trace_writer)?)
+                }
+                TraceWriterState::Running(trace_writer) => {
+                    TraceWriterState::Running(this.update_trace_writer(trace_writer)?)
+                }
+                TraceWriterState::Errored(e) => TraceWriterState::Errored(e),
+            })
+        });
     }
     #[track_caller]
     fn get_io(&self, target: Target) -> CompiledValue<CanonicalType> {
@@ -3382,32 +3879,10 @@ impl SimulationImpl {
             }
         }
         match compiled_value.range.len() {
-            TypeLen {
-                small_slots:
-                    StatePartLen {
-                        value: 1,
-                        _phantom: _,
-                    },
-                big_slots:
-                    StatePartLen {
-                        value: 0,
-                        _phantom: _,
-                    },
-            } => Expr::ty(io).value_from_int_wrapping(
+            TypeLen::A_SMALL_SLOT => Expr::ty(io).value_from_int_wrapping(
                 self.state.small_slots[compiled_value.range.small_slots.start],
             ),
-            TypeLen {
-                small_slots:
-                    StatePartLen {
-                        value: 0,
-                        _phantom: _,
-                    },
-                big_slots:
-                    StatePartLen {
-                        value: 1,
-                        _phantom: _,
-                    },
-            } => Expr::ty(io).value_from_int_wrapping(
+            TypeLen::A_BIG_SLOT => Expr::ty(io).value_from_int_wrapping(
                 self.state.big_slots[compiled_value.range.big_slots.start].clone(),
             ),
             _ => unreachable!(),
@@ -3431,33 +3906,13 @@ impl SimulationImpl {
             self.uninitialized_inputs.remove(&*target);
         }
         match compiled_value.range.len() {
-            TypeLen {
-                small_slots:
-                    StatePartLen {
-                        value: 1,
-                        _phantom: _,
-                    },
-                big_slots:
-                    StatePartLen {
-                        value: 0,
-                        _phantom: _,
-                    },
-            } => {
+            TypeLen::A_SMALL_SLOT => {
                 self.state.small_slots[compiled_value.range.small_slots.start] =
                     value.to_u64().expect("value out of range");
             }
-            TypeLen {
-                small_slots:
-                    StatePartLen {
-                        value: 0,
-                        _phantom: _,
-                    },
-                big_slots:
-                    StatePartLen {
-                        value: 1,
-                        _phantom: _,
-                    },
-            } => self.state.big_slots[compiled_value.range.big_slots.start] = value,
+            TypeLen::A_BIG_SLOT => {
+                self.state.big_slots[compiled_value.range.big_slots.start] = value
+            }
             _ => unreachable!(),
         }
     }
@@ -3477,37 +3932,40 @@ impl SimulationImpl {
         }
         retval
     }
-    fn close(mut self) -> std::io::Result<()> {
-        self.close_all_trace_writers()
+    fn for_each_trace_writer_storing_error(
+        &mut self,
+        mut f: impl FnMut(
+            &mut Self,
+            TraceWriterState<DynTraceWriterDecls>,
+        ) -> std::io::Result<TraceWriterState<DynTraceWriterDecls>>,
+    ) {
+        let mut trace_writers = mem::take(&mut self.trace_writers);
+        for trace_writer in &mut trace_writers {
+            *trace_writer = match f(
+                self,
+                mem::replace(trace_writer, TraceWriterState::Errored(None)),
+            ) {
+                Ok(v) => v,
+                Err(e) => TraceWriterState::Errored(Some(e)),
+            };
+        }
+        self.trace_writers = trace_writers;
     }
-    fn flush_traces(&mut self) -> std::io::Result<()> {
-        let flush_trace_writer = |trace_writer: TraceWriterState<DynTraceWriterDecls>| {
-            Ok(Some(match trace_writer {
-                TraceWriterState::Decls(v) => {
-                    let mut v = v.write_decls(self.trace_decls)?;
-                    v.flush()?;
-                    TraceWriterState::Init(v)
-                }
-                TraceWriterState::Init(mut v) => {
-                    v.flush()?;
-                    TraceWriterState::Init(v)
-                }
-                TraceWriterState::Running(mut v) => {
-                    v.flush()?;
-                    TraceWriterState::Running(v)
-                }
-                TraceWriterState::Errored(Some(e)) => return Err(e),
-                TraceWriterState::Errored(None) => return Ok(None),
-            }))
-        };
+    fn for_each_trace_writer_getting_error(
+        &mut self,
+        mut f: impl FnMut(
+            &mut Self,
+            TraceWriterState<DynTraceWriterDecls>,
+        ) -> std::io::Result<TraceWriterState<DynTraceWriterDecls>>,
+    ) -> std::io::Result<()> {
         let mut retval = Ok(());
-        for trace_writer in &mut self.trace_writers {
-            *trace_writer = match flush_trace_writer(mem::replace(
-                trace_writer,
-                TraceWriterState::Errored(None),
-            )) {
-                Ok(Some(v)) => v,
-                Ok(None) => TraceWriterState::Errored(None),
+        let mut trace_writers = mem::take(&mut self.trace_writers);
+        for trace_writer in &mut trace_writers {
+            *trace_writer = match f(
+                self,
+                mem::replace(trace_writer, TraceWriterState::Errored(None)),
+            ) {
+                Ok(v) => v,
                 Err(e) => {
                     if retval.is_ok() {
                         retval = Err(e);
@@ -3518,8 +3976,33 @@ impl SimulationImpl {
                 }
             };
         }
+        self.trace_writers = trace_writers;
         retval
     }
+    fn close(mut self) -> std::io::Result<()> {
+        self.close_all_trace_writers()
+    }
+    fn flush_traces(&mut self) -> std::io::Result<()> {
+        self.for_each_trace_writer_getting_error(
+            |this, trace_writer: TraceWriterState<DynTraceWriterDecls>| match trace_writer {
+                TraceWriterState::Decls(v) => {
+                    let mut v = v.write_decls(this.trace_decls)?;
+                    v.flush()?;
+                    Ok(TraceWriterState::Init(v))
+                }
+                TraceWriterState::Init(mut v) => {
+                    v.flush()?;
+                    Ok(TraceWriterState::Init(v))
+                }
+                TraceWriterState::Running(mut v) => {
+                    v.flush()?;
+                    Ok(TraceWriterState::Running(v))
+                }
+                TraceWriterState::Errored(Some(e)) => Err(e),
+                TraceWriterState::Errored(None) => Ok(TraceWriterState::Errored(None)),
+            },
+        )
+    }
 }
 
 impl Drop for SimulationImpl {
@@ -3587,6 +4070,7 @@ impl<T: BundleType> fmt::Debug for Simulation<T> {
                     trace_decls,
                     traces,
                     trace_writers,
+                    instant,
                 },
             io,
         } = self;
@@ -3602,6 +4086,7 @@ impl<T: BundleType> fmt::Debug for Simulation<T> {
             .field("trace_decls", trace_decls)
             .field("traces", traces)
             .field("trace_writers", trace_writers)
+            .field("instant", instant)
             .finish()
     }
 }
@@ -3610,6 +4095,11 @@ impl<T: BundleType> Simulation<T> {
     pub fn new(module: Interned<Module<T>>) -> Self {
         Self::from_compiled(Compiled::new(module))
     }
+    pub fn add_trace_writer<W: TraceWriterDecls>(&mut self, writer: W) {
+        self.sim_impl
+            .trace_writers
+            .push(TraceWriterState::Decls(DynTraceWriterDecls::new(writer)));
+    }
     pub fn flush_traces(&mut self) -> std::io::Result<()> {
         self.sim_impl.flush_traces()
     }
@@ -3645,6 +4135,10 @@ impl<T: BundleType> Simulation<T> {
         self.sim_impl.settle_step();
     }
     #[track_caller]
+    pub fn advance_time(&mut self, duration: SimDuration) {
+        self.sim_impl.advance_time(duration);
+    }
+    #[track_caller]
     pub fn read_bool_or_int<I: BoolOrIntType>(&self, io: Expr<I>) -> I::Value {
         self.sim_impl.read_bool_or_int(io)
     }
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index 930c933..5ef2fbc 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -477,10 +477,10 @@ pub(crate) struct Labels {
 
 #[derive(Clone, PartialEq, Eq, Hash)]
 pub(crate) struct Insns<BK: InsnsBuildingKind> {
-    insns: BK::Vec<Insn>,
-    insn_source_locations: BK::Vec<SourceLocation>,
-    labels: BK::Labels,
-    state_layout: StateLayout<BK>,
+    pub(crate) insns: BK::Vec<Insn>,
+    pub(crate) insn_source_locations: BK::Vec<SourceLocation>,
+    pub(crate) labels: BK::Labels,
+    pub(crate) state_layout: StateLayout<BK>,
 }
 
 impl<BK: InsnsBuildingKind> Insns<BK> {
@@ -1228,6 +1228,26 @@ impl TypeLen {
         };
         Some(small_slots)
     }
+    pub(crate) const A_SMALL_SLOT: Self = TypeLen {
+        small_slots: StatePartLen {
+            value: 1,
+            _phantom: PhantomData,
+        },
+        big_slots: StatePartLen {
+            value: 0,
+            _phantom: PhantomData,
+        },
+    };
+    pub(crate) const A_BIG_SLOT: Self = TypeLen {
+        small_slots: StatePartLen {
+            value: 0,
+            _phantom: PhantomData,
+        },
+        big_slots: StatePartLen {
+            value: 1,
+            _phantom: PhantomData,
+        },
+    };
 }
 
 #[derive(Debug, Clone)]
diff --git a/crates/fayalite/src/sim/time.rs b/crates/fayalite/src/sim/time.rs
index d548ab9..07e2b79 100644
--- a/crates/fayalite/src/sim/time.rs
+++ b/crates/fayalite/src/sim/time.rs
@@ -1,12 +1,45 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-use std::{fmt, time::Duration};
+use std::{
+    fmt,
+    ops::{Add, AddAssign},
+    time::Duration,
+};
 
 #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Default)]
 pub struct SimInstant {
     time_since_start: SimDuration,
 }
 
+impl Add<SimDuration> for SimInstant {
+    type Output = SimInstant;
+
+    fn add(mut self, rhs: SimDuration) -> Self::Output {
+        self += rhs;
+        self
+    }
+}
+
+impl AddAssign<SimDuration> for SimInstant {
+    fn add_assign(&mut self, rhs: SimDuration) {
+        self.time_since_start += rhs;
+    }
+}
+
+impl Add<SimInstant> for SimDuration {
+    type Output = SimInstant;
+
+    fn add(self, rhs: SimInstant) -> Self::Output {
+        rhs.add(self)
+    }
+}
+
+impl SimInstant {
+    pub const START: SimInstant = SimInstant {
+        time_since_start: SimDuration::ZERO,
+    };
+}
+
 impl fmt::Debug for SimInstant {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         self.time_since_start.fmt(f)
@@ -18,6 +51,25 @@ pub struct SimDuration {
     attos: u128,
 }
 
+impl AddAssign for SimDuration {
+    fn add_assign(&mut self, rhs: SimDuration) {
+        *self = *self + rhs;
+    }
+}
+
+impl Add for SimDuration {
+    type Output = SimDuration;
+
+    fn add(self, rhs: SimDuration) -> Self::Output {
+        SimDuration {
+            attos: self
+                .attos
+                .checked_add(rhs.attos)
+                .expect("overflow adding durations"),
+        }
+    }
+}
+
 #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)]
 pub struct SimDurationParts {
     pub attos: u16,
diff --git a/crates/fayalite/src/util/misc.rs b/crates/fayalite/src/util/misc.rs
index 85e376a..e1cc9f4 100644
--- a/crates/fayalite/src/util/misc.rs
+++ b/crates/fayalite/src/util/misc.rs
@@ -94,9 +94,15 @@ pub fn interned_bit(v: bool) -> Interned<BitSlice> {
     RETVAL.get_or_init(|| [bits![0; 1].intern(), bits![1; 1].intern()])[v as usize]
 }
 
-#[derive(Copy, Clone, Debug)]
+#[derive(Copy, Clone)]
 pub struct BitSliceWriteWithBase<'a>(pub &'a BitSlice);
 
+impl<'a> Debug for BitSliceWriteWithBase<'a> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "{self:#x}")
+    }
+}
+
 impl BitSliceWriteWithBase<'_> {
     fn fmt_with_base<const BITS_PER_DIGIT: usize, const UPPER_CASE: bool>(
         self,
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index fef71e5..3576b1e 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -117,10 +117,33 @@ fn test_connect_const() {
     made_initial_step: true,
     trace_decls: TraceModule {
         name: "connect_const",
-        children: [],
+        children: [
+            TraceModuleIO {
+                name: "o",
+                child: TraceUInt {
+                    id: TraceScalarId(0),
+                    name: "o",
+                    ty: UInt<8>,
+                    flow: Sink,
+                },
+                ty: UInt<8>,
+                flow: Sink,
+            },
+        ],
     },
-    traces: [],
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<8>,
+            },
+            state: 0x05,
+            last_state: 0x05,
+        },
+    ],
     trace_writers: [],
+    instant: 0 s,
 }"# {
         panic!();
     }
@@ -681,10 +704,277 @@ fn test_mod1() {
     made_initial_step: true,
     trace_decls: TraceModule {
         name: "mod1",
-        children: [],
+        children: [
+            TraceModuleIO {
+                name: "o",
+                child: TraceBundle {
+                    name: "o",
+                    fields: [
+                        TraceUInt {
+                            id: TraceScalarId(0),
+                            name: "i",
+                            ty: UInt<4>,
+                            flow: Source,
+                        },
+                        TraceSInt {
+                            id: TraceScalarId(1),
+                            name: "o",
+                            ty: SInt<2>,
+                            flow: Sink,
+                        },
+                        TraceSInt {
+                            id: TraceScalarId(2),
+                            name: "i2",
+                            ty: SInt<2>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            id: TraceScalarId(3),
+                            name: "o2",
+                            ty: UInt<4>,
+                            flow: Sink,
+                        },
+                    ],
+                    ty: Bundle {
+                        #[hdl(flip)] /* offset = 0 */
+                        i: UInt<4>,
+                        /* offset = 4 */
+                        o: SInt<2>,
+                        #[hdl(flip)] /* offset = 6 */
+                        i2: SInt<2>,
+                        /* offset = 8 */
+                        o2: UInt<4>,
+                    },
+                    flow: Sink,
+                },
+                ty: Bundle {
+                    #[hdl(flip)] /* offset = 0 */
+                    i: UInt<4>,
+                    /* offset = 4 */
+                    o: SInt<2>,
+                    #[hdl(flip)] /* offset = 6 */
+                    i2: SInt<2>,
+                    /* offset = 8 */
+                    o2: UInt<4>,
+                },
+                flow: Sink,
+            },
+            TraceInstance {
+                name: "child",
+                instance_io: TraceBundle {
+                    name: "child",
+                    fields: [
+                        TraceUInt {
+                            id: TraceScalarId(8),
+                            name: "i",
+                            ty: UInt<4>,
+                            flow: Sink,
+                        },
+                        TraceSInt {
+                            id: TraceScalarId(9),
+                            name: "o",
+                            ty: SInt<2>,
+                            flow: Source,
+                        },
+                        TraceSInt {
+                            id: TraceScalarId(10),
+                            name: "i2",
+                            ty: SInt<2>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            id: TraceScalarId(11),
+                            name: "o2",
+                            ty: UInt<4>,
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        #[hdl(flip)] /* offset = 0 */
+                        i: UInt<4>,
+                        /* offset = 4 */
+                        o: SInt<2>,
+                        #[hdl(flip)] /* offset = 6 */
+                        i2: SInt<2>,
+                        /* offset = 8 */
+                        o2: UInt<4>,
+                    },
+                    flow: Source,
+                },
+                module: TraceModule {
+                    name: "mod1_child",
+                    children: [
+                        TraceModuleIO {
+                            name: "i",
+                            child: TraceUInt {
+                                id: TraceScalarId(4),
+                                name: "i",
+                                ty: UInt<4>,
+                                flow: Source,
+                            },
+                            ty: UInt<4>,
+                            flow: Source,
+                        },
+                        TraceModuleIO {
+                            name: "o",
+                            child: TraceSInt {
+                                id: TraceScalarId(5),
+                                name: "o",
+                                ty: SInt<2>,
+                                flow: Sink,
+                            },
+                            ty: SInt<2>,
+                            flow: Sink,
+                        },
+                        TraceModuleIO {
+                            name: "i2",
+                            child: TraceSInt {
+                                id: TraceScalarId(6),
+                                name: "i2",
+                                ty: SInt<2>,
+                                flow: Source,
+                            },
+                            ty: SInt<2>,
+                            flow: Source,
+                        },
+                        TraceModuleIO {
+                            name: "o2",
+                            child: TraceUInt {
+                                id: TraceScalarId(7),
+                                name: "o2",
+                                ty: UInt<4>,
+                                flow: Sink,
+                            },
+                            ty: UInt<4>,
+                            flow: Sink,
+                        },
+                    ],
+                },
+                ty: Bundle {
+                    #[hdl(flip)] /* offset = 0 */
+                    i: UInt<4>,
+                    /* offset = 4 */
+                    o: SInt<2>,
+                    #[hdl(flip)] /* offset = 6 */
+                    i2: SInt<2>,
+                    /* offset = 8 */
+                    o2: UInt<4>,
+                },
+            },
+        ],
     },
-    traces: [],
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<4>,
+            },
+            state: 0xa,
+            last_state: 0xa,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(1),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(2),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<4>,
+            },
+            state: 0xf,
+            last_state: 0xf,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(8),
+                ty: UInt<4>,
+            },
+            state: 0xa,
+            last_state: 0xa,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(9),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(10),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(11),
+                ty: UInt<4>,
+            },
+            state: 0xf,
+            last_state: 0xf,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(4),
+                ty: UInt<4>,
+            },
+            state: 0xa,
+            last_state: 0xa,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(5),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(6),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(7),
+                ty: UInt<4>,
+            },
+            state: 0xf,
+            last_state: 0xf,
+        },
+    ],
     trace_writers: [],
+    instant: 0 s,
 }"# {
         panic!();
     }

From c4b5d004194dcaddba78f90598c3511d8f850471 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 18 Nov 2024 03:04:10 -0800
Subject: [PATCH 091/190] WIP adding VCD output

---
 crates/fayalite/src/sim.rs       |   1 +
 crates/fayalite/src/sim/time.rs  | 200 +++++++++++-
 crates/fayalite/src/sim/vcd.rs   | 542 +++++++++++++++++++++++++++++++
 crates/fayalite/src/util.rs      |   2 +-
 crates/fayalite/src/util/misc.rs |  48 +++
 crates/fayalite/tests/sim.rs     |  22 +-
 6 files changed, 801 insertions(+), 14 deletions(-)
 create mode 100644 crates/fayalite/src/sim/vcd.rs

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index d33b0bb..569cbcc 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -46,6 +46,7 @@ use std::{borrow::Cow, collections::BTreeSet, fmt, marker::PhantomData, mem, ops
 
 mod interpreter;
 pub mod time;
+pub mod vcd;
 
 #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
 enum CondBody {
diff --git a/crates/fayalite/src/sim/time.rs b/crates/fayalite/src/sim/time.rs
index 07e2b79..7c85d8f 100644
--- a/crates/fayalite/src/sim/time.rs
+++ b/crates/fayalite/src/sim/time.rs
@@ -2,7 +2,7 @@
 // See Notices.txt for copyright information
 use std::{
     fmt,
-    ops::{Add, AddAssign},
+    ops::{Add, AddAssign, Sub, SubAssign},
     time::Duration,
 };
 
@@ -11,9 +11,43 @@ pub struct SimInstant {
     time_since_start: SimDuration,
 }
 
+impl SimInstant {
+    pub const fn checked_add(self, duration: SimDuration) -> Option<Self> {
+        let Some(time_since_start) = self.time_since_start.checked_add(duration) else {
+            return None;
+        };
+        Some(SimInstant { time_since_start })
+    }
+    pub const fn checked_duration_since(self, earlier: Self) -> Option<SimDuration> {
+        self.time_since_start.checked_sub(earlier.time_since_start)
+    }
+    pub const fn checked_sub(self, duration: SimDuration) -> Option<Self> {
+        let Some(time_since_start) = self.time_since_start.checked_sub(duration) else {
+            return None;
+        };
+        Some(SimInstant { time_since_start })
+    }
+    #[track_caller]
+    pub const fn duration_since(self, earlier: Self) -> SimDuration {
+        let Some(retval) = self.checked_duration_since(earlier) else {
+            panic!(
+                "tried to compute the duration since a later time -- durations can't be negative"
+            );
+        };
+        retval
+    }
+    pub const fn saturating_duration_since(self, earlier: Self) -> SimDuration {
+        let Some(retval) = self.checked_duration_since(earlier) else {
+            return SimDuration::ZERO;
+        };
+        retval
+    }
+}
+
 impl Add<SimDuration> for SimInstant {
     type Output = SimInstant;
 
+    #[track_caller]
     fn add(mut self, rhs: SimDuration) -> Self::Output {
         self += rhs;
         self
@@ -21,6 +55,7 @@ impl Add<SimDuration> for SimInstant {
 }
 
 impl AddAssign<SimDuration> for SimInstant {
+    #[track_caller]
     fn add_assign(&mut self, rhs: SimDuration) {
         self.time_since_start += rhs;
     }
@@ -29,11 +64,40 @@ impl AddAssign<SimDuration> for SimInstant {
 impl Add<SimInstant> for SimDuration {
     type Output = SimInstant;
 
+    #[track_caller]
     fn add(self, rhs: SimInstant) -> Self::Output {
         rhs.add(self)
     }
 }
 
+impl Sub for SimInstant {
+    type Output = SimDuration;
+
+    #[track_caller]
+    fn sub(self, rhs: SimInstant) -> Self::Output {
+        self.duration_since(rhs)
+    }
+}
+
+impl Sub<SimDuration> for SimInstant {
+    type Output = SimInstant;
+
+    #[track_caller]
+    fn sub(self, rhs: SimDuration) -> Self::Output {
+        let Some(retval) = self.checked_sub(rhs) else {
+            panic!("SimInstant underflow");
+        };
+        retval
+    }
+}
+
+impl SubAssign<SimDuration> for SimInstant {
+    #[track_caller]
+    fn sub_assign(&mut self, rhs: SimDuration) {
+        *self = *self - rhs;
+    }
+}
+
 impl SimInstant {
     pub const START: SimInstant = SimInstant {
         time_since_start: SimDuration::ZERO,
@@ -52,6 +116,7 @@ pub struct SimDuration {
 }
 
 impl AddAssign for SimDuration {
+    #[track_caller]
     fn add_assign(&mut self, rhs: SimDuration) {
         *self = *self + rhs;
     }
@@ -60,6 +125,7 @@ impl AddAssign for SimDuration {
 impl Add for SimDuration {
     type Output = SimDuration;
 
+    #[track_caller]
     fn add(self, rhs: SimDuration) -> Self::Output {
         SimDuration {
             attos: self
@@ -70,6 +136,27 @@ impl Add for SimDuration {
     }
 }
 
+impl Sub for SimDuration {
+    type Output = Self;
+
+    #[track_caller]
+    fn sub(self, rhs: Self) -> Self::Output {
+        SimDuration {
+            attos: self
+                .attos
+                .checked_add(rhs.attos)
+                .expect("underflow subtracting durations -- durations can't be negative"),
+        }
+    }
+}
+
+impl SubAssign for SimDuration {
+    #[track_caller]
+    fn sub_assign(&mut self, rhs: Self) {
+        *self = *self - rhs;
+    }
+}
+
 #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)]
 pub struct SimDurationParts {
     pub attos: u16,
@@ -84,7 +171,7 @@ pub struct SimDurationParts {
 macro_rules! impl_duration_units {
     (
         $(
-            #[unit_const = $UNIT:ident, from_units = $from_units:ident, units = $units:ident, suffix = $suffix:literal]
+            #[unit_const = $UNIT:ident, from_units = $from_units:ident, as_units = $as_units:ident, units = $units:ident, suffix = $suffix:literal]
             const $log10_units_per_sec:ident: u32 = $log10_units_per_sec_value:expr;
         )*
     ) => {
@@ -94,8 +181,11 @@ macro_rules! impl_duration_units {
                 pub const fn $from_units($units: u128) -> Self {
                     Self::from_units_helper::<{ Self::$log10_units_per_sec }>($units)
                 }
+                pub const fn $as_units(self) -> u128 {
+                    self.attos / const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) }
+                }
             )*
-            pub const fn into_parts(mut self) -> SimDurationParts {
+            pub const fn to_parts(mut self) -> SimDurationParts {
                 $(
                     let $units = self.attos / const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) };
                     self.attos %= const { 10u128.pow(Self::LOG10_ATTOS_PER_SEC - Self::$log10_units_per_sec) };
@@ -176,19 +266,19 @@ macro_rules! impl_duration_units {
 }
 
 impl_duration_units! {
-    #[unit_const = SECOND, from_units = from_secs, units = secs, suffix = "s"]
+    #[unit_const = SECOND, from_units = from_secs, as_units = as_secs, units = secs, suffix = "s"]
     const LOG10_SECS_PER_SEC: u32 = 0;
-    #[unit_const = MILLISECOND, from_units = from_millis, units = millis, suffix = "ms"]
+    #[unit_const = MILLISECOND, from_units = from_millis, as_units = as_millis, units = millis, suffix = "ms"]
     const LOG10_MILLIS_PER_SEC: u32 = 3;
-    #[unit_const = MICROSECOND, from_units = from_micros, units = micros, suffix = "μs"]
+    #[unit_const = MICROSECOND, from_units = from_micros, as_units = as_micros, units = micros, suffix = "μs"]
     const LOG10_MICROS_PER_SEC: u32 = 6;
-    #[unit_const = NANOSECOND, from_units = from_nanos, units = nanos, suffix = "ns"]
+    #[unit_const = NANOSECOND, from_units = from_nanos, as_units = as_nanos, units = nanos, suffix = "ns"]
     const LOG10_NANOS_PER_SEC: u32 = 9;
-    #[unit_const = PICOSECOND, from_units = from_picos, units = picos, suffix = "ps"]
+    #[unit_const = PICOSECOND, from_units = from_picos, as_units = as_picos, units = picos, suffix = "ps"]
     const LOG10_PICOS_PER_SEC: u32 = 12;
-    #[unit_const = FEMTOSECOND, from_units = from_femtos, units = femtos, suffix = "fs"]
+    #[unit_const = FEMTOSECOND, from_units = from_femtos, as_units = as_femtos, units = femtos, suffix = "fs"]
     const LOG10_FEMTOS_PER_SEC: u32 = 15;
-    #[unit_const = ATTOSECOND, from_units = from_attos, units = attos, suffix = "as"]
+    #[unit_const = ATTOSECOND, from_units = from_attos, as_units = as_attos, units = attos, suffix = "as"]
     const LOG10_ATTOS_PER_SEC: u32 = 18;
 }
 
@@ -208,6 +298,96 @@ impl SimDuration {
             None => panic!("duration too big"),
         }
     }
+    pub const fn abs_diff(self, other: Self) -> Self {
+        Self {
+            attos: self.attos.abs_diff(other.attos),
+        }
+    }
+    pub const fn checked_add(self, rhs: Self) -> Option<Self> {
+        let Some(attos) = self.attos.checked_add(rhs.attos) else {
+            return None;
+        };
+        Some(Self { attos })
+    }
+    pub const fn checked_sub(self, rhs: Self) -> Option<Self> {
+        let Some(attos) = self.attos.checked_sub(rhs.attos) else {
+            return None;
+        };
+        Some(Self { attos })
+    }
+    pub const fn is_zero(self) -> bool {
+        self.attos == 0
+    }
+    pub const fn saturating_add(self, rhs: Self) -> Self {
+        Self {
+            attos: self.attos.saturating_add(rhs.attos),
+        }
+    }
+    pub const fn saturating_sub(self, rhs: Self) -> Self {
+        Self {
+            attos: self.attos.saturating_sub(rhs.attos),
+        }
+    }
+    pub const fn checked_ilog10(self) -> Option<i32> {
+        let Some(ilog10_attos) = self.attos.checked_ilog10() else {
+            return None;
+        };
+        Some(ilog10_attos as i32 - Self::LOG10_ATTOS_PER_SEC as i32)
+    }
+    #[track_caller]
+    pub const fn ilog10(self) -> i32 {
+        let Some(retval) = self.checked_ilog10() else {
+            panic!("tried to take the ilog10 of 0");
+        };
+        retval
+    }
+    pub const fn checked_pow10(log10: i32, underflow_is_zero: bool) -> Option<Self> {
+        let Some(log10) = Self::LOG10_ATTOS_PER_SEC.checked_add_signed(log10) else {
+            return if log10 < 0 && underflow_is_zero {
+                Some(Self::ZERO)
+            } else {
+                None
+            };
+        };
+        let Some(attos) = 10u128.checked_pow(log10) else {
+            return None;
+        };
+        Some(Self { attos })
+    }
+    #[track_caller]
+    pub const fn pow10(log10: i32) -> Self {
+        let Some(retval) = Self::checked_pow10(log10, true) else {
+            panic!("pow10 overflowed");
+        };
+        retval
+    }
+    pub const fn is_power_of_ten(self) -> bool {
+        const TEN: u128 = 10;
+        const NUMBER_OF_POWERS_OF_TEN: usize = {
+            let mut n = 0;
+            while let Some(_) = TEN.checked_pow(n as u32) {
+                n += 1;
+            }
+            n
+        };
+        const POWERS_OF_TEN: [u128; NUMBER_OF_POWERS_OF_TEN] = {
+            let mut retval = [0; NUMBER_OF_POWERS_OF_TEN];
+            let mut i = 0;
+            while i < NUMBER_OF_POWERS_OF_TEN {
+                retval[i] = TEN.pow(i as u32);
+                i += 1;
+            }
+            retval
+        };
+        let mut i = 0;
+        while i < NUMBER_OF_POWERS_OF_TEN {
+            if self.attos == POWERS_OF_TEN[i] {
+                return true;
+            }
+            i += 1;
+        }
+        false
+    }
 }
 
 impl From<Duration> for SimDuration {
diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs
new file mode 100644
index 0000000..cbb38b4
--- /dev/null
+++ b/crates/fayalite/src/sim/vcd.rs
@@ -0,0 +1,542 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::{
+    expr::Flow,
+    int::UInt,
+    sim::{
+        time::{SimDuration, SimInstant},
+        TraceArray, TraceAsyncReset, TraceBool, TraceBundle, TraceClock, TraceDecl,
+        TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceInstance,
+        TraceMemPort, TraceModule, TraceModuleIO, TraceReg, TraceSInt, TraceScalar, TraceScalarId,
+        TraceScope, TraceSyncReset, TraceUInt, TraceWire, TraceWriter, TraceWriterDecls,
+    },
+};
+use bitvec::slice::BitSlice;
+use std::{fmt, io, mem};
+
+pub struct VcdWriterDecls<W: io::Write + 'static> {
+    writer: W,
+    timescale: SimDuration,
+}
+
+impl<W: io::Write + 'static> VcdWriterDecls<W> {
+    pub fn new(writer: W) -> Self {
+        Self {
+            writer,
+            timescale: SimDuration::from_picos(1),
+        }
+    }
+    pub fn timescale(&self) -> SimDuration {
+        self.timescale
+    }
+    #[track_caller]
+    pub fn with_timescale(mut self, timescale: SimDuration) -> Self {
+        // check timescale validity
+        vcd_timescale(timescale);
+        self.timescale = timescale;
+        self
+    }
+}
+
+#[track_caller]
+const fn vcd_timescale(timescale: SimDuration) -> &'static str {
+    if !timescale.is_power_of_ten() {
+        panic!("VCD timescale must be a power of 10");
+    }
+    macro_rules! timescales {
+        ($($const_name:ident = ($dur:expr, $text:literal),)*) => {
+            $(const $const_name: SimDuration = $dur;)*
+            match timescale {
+                $($const_name => $text,)*
+                _ => panic!("VCD timescale is too big"),
+            }
+        };
+    }
+    timescales! {
+        TIMESCALE_1_AS = (SimDuration::from_attos(1), "1 as"),
+        TIMESCALE_10_AS = (SimDuration::from_attos(10), "10 as"),
+        TIMESCALE_100_AS = (SimDuration::from_attos(100), "100 as"),
+        TIMESCALE_1_FS = (SimDuration::from_femtos(1), "1 fs"),
+        TIMESCALE_10_FS = (SimDuration::from_femtos(10), "10 fs"),
+        TIMESCALE_100_FS = (SimDuration::from_femtos(100), "100 fs"),
+        TIMESCALE_1_PS = (SimDuration::from_picos(1), "1 ps"),
+        TIMESCALE_10_PS = (SimDuration::from_picos(10), "10 ps"),
+        TIMESCALE_100_PS = (SimDuration::from_picos(100), "100 ps"),
+        TIMESCALE_1_NS = (SimDuration::from_nanos(1), "1 ns"),
+        TIMESCALE_10_NS = (SimDuration::from_nanos(10), "10 ns"),
+        TIMESCALE_100_NS = (SimDuration::from_nanos(100), "100 ns"),
+        TIMESCALE_1_US = (SimDuration::from_micros(1), "1 us"),
+        TIMESCALE_10_US = (SimDuration::from_micros(10), "10 us"),
+        TIMESCALE_100_US = (SimDuration::from_micros(100), "100 us"),
+        TIMESCALE_1_MS = (SimDuration::from_millis(1), "1 ms"),
+        TIMESCALE_10_MS = (SimDuration::from_millis(10), "10 ms"),
+        TIMESCALE_100_MS = (SimDuration::from_millis(100), "100 ms"),
+        TIMESCALE_1_S = (SimDuration::from_secs(1), "1 s"),
+        TIMESCALE_10_S = (SimDuration::from_secs(10), "10 s"),
+        TIMESCALE_100_S = (SimDuration::from_secs(100), "100 s"),
+        TIMESCALE_1000_S = (SimDuration::from_secs(1000), "1000 s"),
+    }
+}
+
+impl<W: io::Write> fmt::Debug for VcdWriterDecls<W> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            writer: _,
+            timescale,
+        } = self;
+        f.debug_struct("VcdWriterDecls")
+            .field("timescale", timescale)
+            .finish_non_exhaustive()
+    }
+}
+
+fn write_vcd_scope<W: io::Write, R>(
+    writer: &mut W,
+    scope_type: &str,
+    scope_name: &str,
+    f: impl FnOnce(&mut W) -> io::Result<R>,
+) -> io::Result<R> {
+    writeln!(writer, "$scope {scope_type} {scope_name} $end")?;
+    let retval = f(writer)?;
+    writeln!(writer, "$upscope $end")?;
+    Ok(retval)
+}
+
+macro_rules! trait_arg {
+    (
+        trait $Arg:ident {
+            $(
+                fn $fn:ident(self) -> $ty:ty;
+            )*
+        }
+    ) => {
+        trait $Arg: Sized {
+            $(fn $fn(self) -> $ty {
+                unreachable!()
+            })*
+        }
+
+        $(
+            impl $Arg for $ty {
+                fn $fn(self) -> $ty {
+                    self
+                }
+            }
+        )*
+    };
+}
+
+trait_arg! {
+    trait Arg {
+        fn module(self) -> ArgModule;
+        fn module_body(self) -> ArgModuleBody;
+        fn in_type(self) -> ArgInType;
+    }
+}
+
+struct ArgModule {}
+
+struct ArgModuleBody {}
+
+#[derive(Clone, Copy)]
+struct ArgInType {
+    source_var_type: &'static str,
+    sink_var_type: &'static str,
+    duplex_var_type: &'static str,
+}
+
+trait WriteTrace: Copy {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()>;
+}
+
+impl WriteTrace for TraceDecl {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        match self {
+            Self::Scope(v) => v.write_trace(writer, arg),
+            Self::Scalar(v) => v.write_trace(writer, arg),
+        }
+    }
+}
+
+impl WriteTrace for TraceScalar {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        match self {
+            Self::UInt(v) => v.write_trace(writer, arg),
+            Self::SInt(v) => v.write_trace(writer, arg),
+            Self::Bool(v) => v.write_trace(writer, arg),
+            Self::FieldlessEnum(v) => v.write_trace(writer, arg),
+            Self::EnumDiscriminant(v) => v.write_trace(writer, arg),
+            Self::Clock(v) => v.write_trace(writer, arg),
+            Self::SyncReset(v) => v.write_trace(writer, arg),
+            Self::AsyncReset(v) => v.write_trace(writer, arg),
+        }
+    }
+}
+
+fn write_scalar_id<W: io::Write>(writer: &mut W, id: TraceScalarId) -> io::Result<()> {
+    let min_char = b'!';
+    let max_char = b'~';
+    let base = (max_char - min_char + 1) as usize;
+    let mut id = id.as_usize();
+    loop {
+        let digit = (id % base) as u8 + min_char;
+        id /= base;
+        writer.write_all(&[digit])?;
+        if id == 0 {
+            break;
+        }
+    }
+    Ok(())
+}
+
+fn write_vcd_var<W: io::Write>(
+    writer: &mut W,
+    var_type: &str,
+    size: usize,
+    id: TraceScalarId,
+    name: &str,
+) -> io::Result<()> {
+    write!(writer, "$var {var_type} {size} ")?;
+    write_scalar_id(writer, id)?;
+    writeln!(writer, " {name} $end")
+}
+
+impl WriteTrace for TraceUInt {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let ArgInType {
+            source_var_type,
+            sink_var_type,
+            duplex_var_type,
+        } = arg.in_type();
+        let Self { id, name, ty, flow } = self;
+        let var_type = match flow {
+            Flow::Source => source_var_type,
+            Flow::Sink => sink_var_type,
+            Flow::Duplex => duplex_var_type,
+        };
+        if ty.width() == 0 {
+            write_vcd_var(writer, "string", ty.width(), id, &name)
+        } else {
+            write_vcd_var(writer, var_type, ty.width(), id, &name)
+        }
+    }
+}
+
+impl WriteTrace for TraceSInt {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let Self { id, name, ty, flow } = self;
+        TraceUInt {
+            id,
+            name,
+            ty: UInt::new_dyn(ty.width()),
+            flow,
+        }
+        .write_trace(writer, arg)
+    }
+}
+
+impl WriteTrace for TraceBool {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let Self { id, name, flow } = self;
+        TraceUInt {
+            id,
+            name,
+            flow,
+            ty: UInt::new_dyn(1),
+        }
+        .write_trace(writer, arg)
+    }
+}
+
+impl WriteTrace for TraceFieldlessEnum {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        todo!()
+    }
+}
+
+impl WriteTrace for TraceEnumDiscriminant {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        todo!()
+    }
+}
+
+impl WriteTrace for TraceClock {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let Self { id, name, flow } = self;
+        TraceBool { id, name, flow }.write_trace(writer, arg)
+    }
+}
+
+impl WriteTrace for TraceSyncReset {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let Self { id, name, flow } = self;
+        TraceBool { id, name, flow }.write_trace(writer, arg)
+    }
+}
+
+impl WriteTrace for TraceAsyncReset {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let Self { id, name, flow } = self;
+        TraceBool { id, name, flow }.write_trace(writer, arg)
+    }
+}
+
+impl WriteTrace for TraceScope {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        match self {
+            Self::Module(v) => v.write_trace(writer, arg),
+            Self::Instance(v) => v.write_trace(writer, arg),
+            Self::MemPort(v) => v.write_trace(writer, arg),
+            Self::Wire(v) => v.write_trace(writer, arg),
+            Self::Reg(v) => v.write_trace(writer, arg),
+            Self::ModuleIO(v) => v.write_trace(writer, arg),
+            Self::Bundle(v) => v.write_trace(writer, arg),
+            Self::Array(v) => v.write_trace(writer, arg),
+            Self::EnumWithFields(v) => v.write_trace(writer, arg),
+        }
+    }
+}
+
+impl WriteTrace for TraceModule {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let ArgModule {} = arg.module();
+        let Self { name, children } = self;
+        write_vcd_scope(writer, "module", &name, |writer| {
+            for child in children {
+                child.write_trace(writer, ArgModuleBody {})?;
+            }
+            Ok(())
+        })
+    }
+}
+
+impl WriteTrace for TraceInstance {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let ArgModuleBody {} = arg.module_body();
+        let Self {
+            name: _,
+            instance_io,
+            module,
+            ty: _,
+        } = self;
+        instance_io.write_trace(
+            writer,
+            ArgInType {
+                source_var_type: "wire",
+                sink_var_type: "wire",
+                duplex_var_type: "wire",
+            },
+        )?;
+        module.write_trace(writer, ArgModule {})
+    }
+}
+
+impl WriteTrace for TraceMemPort {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        todo!()
+    }
+}
+
+impl WriteTrace for TraceWire {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let ArgModuleBody {} = arg.module_body();
+        let Self {
+            name: _,
+            child,
+            ty: _,
+        } = self;
+        child.write_trace(
+            writer,
+            ArgInType {
+                source_var_type: "wire",
+                sink_var_type: "wire",
+                duplex_var_type: "wire",
+            },
+        )
+    }
+}
+
+impl WriteTrace for TraceReg {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let ArgModuleBody {} = arg.module_body();
+        let Self {
+            name: _,
+            child,
+            ty: _,
+        } = self;
+        child.write_trace(
+            writer,
+            ArgInType {
+                source_var_type: "reg",
+                sink_var_type: "reg",
+                duplex_var_type: "reg",
+            },
+        )
+    }
+}
+
+impl WriteTrace for TraceModuleIO {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let ArgModuleBody {} = arg.module_body();
+        let Self {
+            name: _,
+            child,
+            ty: _,
+            flow: _,
+        } = self;
+        child.write_trace(
+            writer,
+            ArgInType {
+                source_var_type: "wire",
+                sink_var_type: "wire",
+                duplex_var_type: "wire",
+            },
+        )
+    }
+}
+
+impl WriteTrace for TraceBundle {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let arg = arg.in_type();
+        let Self {
+            name,
+            fields,
+            ty: _,
+            flow: _,
+        } = self;
+        write_vcd_scope(writer, "struct", &name, |writer| {
+            for field in fields {
+                field.write_trace(writer, arg)?;
+            }
+            Ok(())
+        })
+    }
+}
+
+impl WriteTrace for TraceArray {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let arg = arg.in_type();
+        let Self {
+            name,
+            elements,
+            ty: _,
+            flow: _,
+        } = self;
+        write_vcd_scope(writer, "struct", &name, |writer| {
+            for element in elements {
+                element.write_trace(writer, arg)?;
+            }
+            Ok(())
+        })
+    }
+}
+
+impl WriteTrace for TraceEnumWithFields {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        todo!()
+    }
+}
+
+impl<W: io::Write> TraceWriterDecls for VcdWriterDecls<W> {
+    type Error = io::Error;
+    type TraceWriter = VcdWriter<W>;
+
+    fn write_decls(self, module: TraceModule) -> Result<Self::TraceWriter, Self::Error> {
+        let Self {
+            mut writer,
+            timescale,
+        } = self;
+        writeln!(writer, "$timescale {} $end", vcd_timescale(timescale))?;
+        module.write_trace(&mut writer, ArgModule {})?;
+        writeln!(writer, "$enddefinitions $end")?;
+        writeln!(writer, "$dumpvars")?;
+        Ok(VcdWriter {
+            writer,
+            finished_init: false,
+            timescale,
+        })
+    }
+}
+
+pub struct VcdWriter<W: io::Write + 'static> {
+    writer: W,
+    finished_init: bool,
+    timescale: SimDuration,
+}
+
+impl<W: io::Write + 'static> VcdWriter<W> {
+    pub fn timescale(&self) -> SimDuration {
+        self.timescale
+    }
+}
+
+impl<W: io::Write> TraceWriter for VcdWriter<W> {
+    type Error = io::Error;
+
+    fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
+        match value.len() {
+            0 => self.writer.write_all(b"s0 ")?,
+            1 => write!(self.writer, "{} ", if value[0] { "1" } else { "0" })?,
+            _ => {
+                self.writer.write_all(b"b")?;
+                let mut any_ones = false;
+                for bit in value.iter().rev() {
+                    if *bit {
+                        any_ones = true;
+                        self.writer.write_all(b"1")?;
+                    } else if any_ones {
+                        self.writer.write_all(b"0")?;
+                    }
+                }
+                if !any_ones {
+                    self.writer.write_all(b"0")?;
+                }
+                self.writer.write_all(b" ")?;
+            }
+        }
+        write_scalar_id(&mut self.writer, id)?;
+        self.writer.write_all(b"\n")
+    }
+
+    fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
+        self.set_signal_uint(id, value)
+    }
+
+    fn finish_init(&mut self) -> Result<(), Self::Error> {
+        if mem::replace(&mut self.finished_init, true) {
+            return Ok(());
+        }
+        writeln!(self.writer, "$end")
+    }
+
+    fn change_time_to(&mut self, instant: SimInstant) -> Result<(), Self::Error> {
+        assert!(self.finished_init);
+        let mut instant_attos = (instant - SimInstant::START).as_attos();
+        instant_attos += self.timescale.as_attos() / 2;
+        let timestamp = instant_attos / self.timescale.as_attos();
+        writeln!(self.writer, "#{timestamp}")
+    }
+
+    fn flush(&mut self) -> Result<(), Self::Error> {
+        self.writer.flush()
+    }
+
+    fn close(mut self) -> Result<(), Self::Error> {
+        self.writer.flush()
+    }
+}
+
+impl<W: io::Write> fmt::Debug for VcdWriter<W> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            writer: _,
+            finished_init,
+            timescale,
+        } = self;
+        f.debug_struct("VcdWriter")
+            .field("finished_init", finished_init)
+            .field("timescale", timescale)
+            .finish_non_exhaustive()
+    }
+}
diff --git a/crates/fayalite/src/util.rs b/crates/fayalite/src/util.rs
index 131c54c..fadc7af 100644
--- a/crates/fayalite/src/util.rs
+++ b/crates/fayalite/src/util.rs
@@ -25,7 +25,7 @@ pub use scoped_ref::ScopedRef;
 #[doc(inline)]
 pub use misc::{
     get_many_mut, interned_bit, iter_eq_by, BitSliceWriteWithBase, DebugAsDisplay,
-    DebugAsRawString, MakeMutSlice,
+    DebugAsRawString, MakeMutSlice, RcWriter,
 };
 
 pub mod job_server;
diff --git a/crates/fayalite/src/util/misc.rs b/crates/fayalite/src/util/misc.rs
index e1cc9f4..f482eaa 100644
--- a/crates/fayalite/src/util/misc.rs
+++ b/crates/fayalite/src/util/misc.rs
@@ -3,6 +3,7 @@
 use crate::intern::{Intern, Interned};
 use bitvec::{bits, order::Lsb0, slice::BitSlice, view::BitView};
 use std::{
+    cell::Cell,
     fmt::{self, Debug, Write},
     rc::Rc,
     sync::{Arc, OnceLock},
@@ -177,3 +178,50 @@ pub fn get_many_mut<T, const N: usize>(slice: &mut [T], indexes: [usize; N]) ->
         std::array::from_fn(|i| &mut *base.add(indexes[i]))
     }
 }
+
+#[derive(Clone, Default)]
+pub struct RcWriter(Rc<Cell<Vec<u8>>>);
+
+impl Debug for RcWriter {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.borrow_impl(|buf| {
+            f.debug_tuple("RcWriter")
+                .field(&DebugAsDisplay(format_args!("b\"{}\"", buf.escape_ascii())))
+                .finish()
+        })
+    }
+}
+
+impl RcWriter {
+    fn borrow_impl<R>(&self, f: impl FnOnce(&mut Vec<u8>) -> R) -> R {
+        let buf = Cell::take(&self.0);
+        struct PutBackOnDrop<'a> {
+            buf: Vec<u8>,
+            this: &'a RcWriter,
+        }
+        impl Drop for PutBackOnDrop<'_> {
+            fn drop(&mut self) {
+                self.this.0.set(std::mem::take(&mut self.buf));
+            }
+        }
+        let mut buf = PutBackOnDrop { buf, this: self };
+        f(&mut buf.buf)
+    }
+    pub fn borrow<R>(&mut self, f: impl FnOnce(&mut Vec<u8>) -> R) -> R {
+        self.borrow_impl(f)
+    }
+    pub fn take(&mut self) -> Vec<u8> {
+        Cell::take(&self.0)
+    }
+}
+
+impl std::io::Write for RcWriter {
+    fn write(&mut self, buf: &[u8]) -> std::io::Result<usize> {
+        self.borrow(|v| v.extend_from_slice(buf));
+        Ok(buf.len())
+    }
+
+    fn flush(&mut self) -> std::io::Result<()> {
+        Ok(())
+    }
+}
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 3576b1e..b21b5c0 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -1,6 +1,11 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-use fayalite::{int::UIntValue, prelude::*, sim::Simulation};
+use fayalite::{
+    int::UIntValue,
+    prelude::*,
+    sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
+    util::RcWriter,
+};
 
 #[hdl_module(outline_generated)]
 pub fn connect_const() {
@@ -177,14 +182,25 @@ pub fn mod1() {
     connect(o, child);
 }
 
+#[cfg(todo)]
 #[hdl]
 #[test]
 fn test_mod1() {
     let _n = SourceLocation::normalize_files_for_tests();
     let mut sim = Simulation::new(mod1());
-    sim.write_bool_or_int(sim.io().o.i, 0xA_hdl_u4);
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_bool_or_int(sim.io().o.i, 0x3_hdl_u4);
     sim.write_bool_or_int(sim.io().o.i2, -2_hdl_i2);
-    sim.settle_step();
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.write_bool_or_int(sim.io().o.i, 0xA_hdl_u4);
+    sim.advance_time(SimDuration::from_micros(1));
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    todo!("generated vcd is incorrect");
+    if vcd != r#""# {
+        panic!();
+    }
     let sim_debug = format!("{sim:#?}");
     println!("#######\n{sim_debug}\n#######");
     if sim_debug

From 11ddbc43c7d18663f4a501b893c5b1cec8c3838d Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 20 Nov 2024 22:36:12 -0800
Subject: [PATCH 092/190] writing VCD for combinatorial circuits works!

---
 crates/fayalite/src/sim.rs   | 27 +++++++++---
 crates/fayalite/tests/sim.rs | 85 ++++++++++++++++++++++++++++++------
 2 files changed, 92 insertions(+), 20 deletions(-)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 569cbcc..fb5a1e0 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -3620,6 +3620,7 @@ struct SimulationImpl {
     uninitialized_inputs: HashSet<Target>,
     io_targets: HashMap<Target, CompiledValue<CanonicalType>>,
     made_initial_step: bool,
+    needs_settle: bool,
     trace_decls: TraceModule,
     traces: Box<[SimTrace<BitVec>]>,
     trace_writers: Vec<TraceWriterState<DynTraceWriterDecls>>,
@@ -3669,6 +3670,7 @@ impl SimulationImpl {
             uninitialized_inputs: HashSet::new(),
             io_targets: HashMap::new(),
             made_initial_step: false,
+            needs_settle: true,
             trace_decls: compiled.base_module.trace_decls,
             traces: Box::from_iter(compiled.traces.iter().map(
                 |&SimTrace {
@@ -3804,9 +3806,7 @@ impl SimulationImpl {
     }
     #[track_caller]
     fn advance_time(&mut self, duration: SimDuration) {
-        if !self.made_initial_step {
-            self.settle_step();
-        }
+        self.settle_step();
         self.instant += duration;
         self.for_each_trace_writer_storing_error(|this, mut trace_writer_state| {
             match &mut trace_writer_state {
@@ -3825,6 +3825,9 @@ impl SimulationImpl {
             self.uninitialized_inputs.is_empty(),
             "didn't initialize all inputs",
         );
+        if !self.needs_settle {
+            return;
+        }
         self.state.setup_call(0);
         self.state.run();
         if self.made_initial_step {
@@ -3833,6 +3836,7 @@ impl SimulationImpl {
             self.read_traces::<true>();
         }
         self.made_initial_step = true;
+        self.needs_settle = false;
         self.for_each_trace_writer_storing_error(|this, trace_writer_state| {
             Ok(match trace_writer_state {
                 TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running(
@@ -3861,12 +3865,14 @@ impl SimulationImpl {
         panic!("simulator read/write expression must not have dynamic array indexes");
     }
     #[track_caller]
-    fn read_bool_or_int<I: BoolOrIntType>(&self, io: Expr<I>) -> I::Value {
+    fn read_bool_or_int<I: BoolOrIntType>(&mut self, io: Expr<I>) -> I::Value {
         let Some(target) = io.target() else {
             panic!("can't read from expression that's not a field/element of `Simulation::io()`");
         };
         let compiled_value = self.get_io(*target);
-        if !self.made_initial_step {
+        if self.made_initial_step {
+            self.settle_step();
+        } else {
             match target.flow() {
                 Flow::Source => {
                     panic!("can't read from an output before the simulation has made any steps");
@@ -3906,6 +3912,7 @@ impl SimulationImpl {
         if !self.made_initial_step {
             self.uninitialized_inputs.remove(&*target);
         }
+        self.needs_settle = true;
         match compiled_value.range.len() {
             TypeLen::A_SMALL_SLOT => {
                 self.state.small_slots[compiled_value.range.small_slots.start] =
@@ -3981,9 +3988,15 @@ impl SimulationImpl {
         retval
     }
     fn close(mut self) -> std::io::Result<()> {
+        if self.made_initial_step {
+            self.settle_step();
+        }
         self.close_all_trace_writers()
     }
     fn flush_traces(&mut self) -> std::io::Result<()> {
+        if self.made_initial_step {
+            self.settle_step();
+        }
         self.for_each_trace_writer_getting_error(
             |this, trace_writer: TraceWriterState<DynTraceWriterDecls>| match trace_writer {
                 TraceWriterState::Decls(v) => {
@@ -4068,6 +4081,7 @@ impl<T: BundleType> fmt::Debug for Simulation<T> {
                     uninitialized_inputs,
                     io_targets,
                     made_initial_step,
+                    needs_settle,
                     trace_decls,
                     traces,
                     trace_writers,
@@ -4084,6 +4098,7 @@ impl<T: BundleType> fmt::Debug for Simulation<T> {
             )
             .field("io_targets", &SortedMapDebug(io_targets))
             .field("made_initial_step", made_initial_step)
+            .field("needs_settle", needs_settle)
             .field("trace_decls", trace_decls)
             .field("traces", traces)
             .field("trace_writers", trace_writers)
@@ -4140,7 +4155,7 @@ impl<T: BundleType> Simulation<T> {
         self.sim_impl.advance_time(duration);
     }
     #[track_caller]
-    pub fn read_bool_or_int<I: BoolOrIntType>(&self, io: Expr<I>) -> I::Value {
+    pub fn read_bool_or_int<I: BoolOrIntType>(&mut self, io: Expr<I>) -> I::Value {
         self.sim_impl.read_bool_or_int(io)
     }
     #[track_caller]
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index b21b5c0..78db49f 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -120,6 +120,7 @@ fn test_connect_const() {
         },
     },
     made_initial_step: true,
+    needs_settle: false,
     trace_decls: TraceModule {
         name: "connect_const",
         children: [
@@ -182,7 +183,6 @@ pub fn mod1() {
     connect(o, child);
 }
 
-#[cfg(todo)]
 #[hdl]
 #[test]
 fn test_mod1() {
@@ -195,10 +195,58 @@ fn test_mod1() {
     sim.advance_time(SimDuration::from_micros(1));
     sim.write_bool_or_int(sim.io().o.i, 0xA_hdl_u4);
     sim.advance_time(SimDuration::from_micros(1));
+    sim.flush_traces().unwrap();
     let vcd = String::from_utf8(writer.take()).unwrap();
     println!("####### VCD:\n{vcd}\n#######");
-    todo!("generated vcd is incorrect");
-    if vcd != r#""# {
+    if vcd
+        != r#"$timescale 1 ps $end
+$scope module mod1 $end
+$scope struct o $end
+$var wire 4 ! i $end
+$var wire 2 " o $end
+$var wire 2 # i2 $end
+$var wire 4 $ o2 $end
+$upscope $end
+$scope struct child $end
+$var wire 4 ) i $end
+$var wire 2 * o $end
+$var wire 2 + i2 $end
+$var wire 4 , o2 $end
+$upscope $end
+$scope module mod1_child $end
+$var wire 4 % i $end
+$var wire 2 & o $end
+$var wire 2 ' i2 $end
+$var wire 4 ( o2 $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+b11 !
+b11 "
+b10 #
+b1110 $
+b11 %
+b11 &
+b10 '
+b1110 (
+b11 )
+b11 *
+b10 +
+b1110 ,
+$end
+#1000000
+b1010 !
+b10 "
+b1111 $
+b1010 %
+b10 &
+b1111 (
+b1010 )
+b10 *
+b1111 ,
+#2000000
+"# {
         panic!();
     }
     let sim_debug = format!("{sim:#?}");
@@ -718,6 +766,7 @@ fn test_mod1() {
         },
     },
     made_initial_step: true,
+    needs_settle: false,
     trace_decls: TraceModule {
         name: "mod1",
         children: [
@@ -887,7 +936,7 @@ fn test_mod1() {
                 ty: UInt<4>,
             },
             state: 0xa,
-            last_state: 0xa,
+            last_state: 0x3,
         },
         SimTrace {
             id: TraceScalarId(1),
@@ -896,7 +945,7 @@ fn test_mod1() {
                 ty: SInt<2>,
             },
             state: 0x2,
-            last_state: 0x2,
+            last_state: 0x3,
         },
         SimTrace {
             id: TraceScalarId(2),
@@ -914,7 +963,7 @@ fn test_mod1() {
                 ty: UInt<4>,
             },
             state: 0xf,
-            last_state: 0xf,
+            last_state: 0xe,
         },
         SimTrace {
             id: TraceScalarId(4),
@@ -923,7 +972,7 @@ fn test_mod1() {
                 ty: UInt<4>,
             },
             state: 0xa,
-            last_state: 0xa,
+            last_state: 0x3,
         },
         SimTrace {
             id: TraceScalarId(5),
@@ -932,7 +981,7 @@ fn test_mod1() {
                 ty: SInt<2>,
             },
             state: 0x2,
-            last_state: 0x2,
+            last_state: 0x3,
         },
         SimTrace {
             id: TraceScalarId(6),
@@ -950,7 +999,7 @@ fn test_mod1() {
                 ty: UInt<4>,
             },
             state: 0xf,
-            last_state: 0xf,
+            last_state: 0xe,
         },
         SimTrace {
             id: TraceScalarId(8),
@@ -959,7 +1008,7 @@ fn test_mod1() {
                 ty: UInt<4>,
             },
             state: 0xa,
-            last_state: 0xa,
+            last_state: 0x3,
         },
         SimTrace {
             id: TraceScalarId(9),
@@ -968,7 +1017,7 @@ fn test_mod1() {
                 ty: SInt<2>,
             },
             state: 0x2,
-            last_state: 0x2,
+            last_state: 0x3,
         },
         SimTrace {
             id: TraceScalarId(10),
@@ -986,11 +1035,19 @@ fn test_mod1() {
                 ty: UInt<4>,
             },
             state: 0xf,
-            last_state: 0xf,
+            last_state: 0xe,
         },
     ],
-    trace_writers: [],
-    instant: 0 s,
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 2 μs,
 }"# {
         panic!();
     }

From 913baa37e90727089fc4d6710a17637d1a21d686 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 22 Nov 2024 16:07:18 -0800
Subject: [PATCH 093/190] WIP adding deduce_resets pass

---
 crates/fayalite/src/module.rs                 |  47 +++++
 crates/fayalite/src/module/transform.rs       |   1 +
 .../src/module/transform/deduce_resets.rs     | 191 ++++++++++++++++++
 crates/fayalite/src/sim.rs                    |  47 +----
 4 files changed, 242 insertions(+), 44 deletions(-)
 create mode 100644 crates/fayalite/src/module/transform/deduce_resets.rs

diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index 16010cf..b8610e7 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -2641,3 +2641,50 @@ impl<T: Type> ModuleIO<T> {
         self.ty
     }
 }
+
+#[derive(PartialEq, Eq, Hash, Clone, Copy)]
+pub enum InstantiatedModule {
+    Base(Interned<Module<Bundle>>),
+    Child {
+        parent: Interned<InstantiatedModule>,
+        instance: Interned<Instance<Bundle>>,
+    },
+}
+
+impl InstantiatedModule {
+    pub fn leaf_module(self) -> Interned<Module<Bundle>> {
+        match self {
+            InstantiatedModule::Base(base) => base,
+            InstantiatedModule::Child { instance, .. } => instance.instantiated(),
+        }
+    }
+    fn write_path(self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self {
+            InstantiatedModule::Base(base) => fmt::Debug::fmt(&base.name_id(), f),
+            InstantiatedModule::Child { parent, instance } => {
+                parent.write_path(f)?;
+                write!(f, ".{}", instance.name_id())
+            }
+        }
+    }
+}
+
+impl fmt::Debug for InstantiatedModule {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "InstantiatedModule(")?;
+        self.write_path(f)?;
+        write!(f, ": {})", self.leaf_module().name_id())
+    }
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+pub struct TargetInInstantiatedModule {
+    pub instantiated_module: InstantiatedModule,
+    pub target: Target,
+}
+
+#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
+pub struct ExprInInstantiatedModule<T: Type> {
+    pub instantiated_module: InstantiatedModule,
+    pub target: Expr<T>,
+}
diff --git a/crates/fayalite/src/module/transform.rs b/crates/fayalite/src/module/transform.rs
index 4117087..063a1a3 100644
--- a/crates/fayalite/src/module/transform.rs
+++ b/crates/fayalite/src/module/transform.rs
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
+pub mod deduce_resets;
 pub mod simplify_enums;
 pub mod simplify_memories;
 pub mod visit;
diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs
new file mode 100644
index 0000000..dc01b33
--- /dev/null
+++ b/crates/fayalite/src/module/transform/deduce_resets.rs
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use hashbrown::{hash_map::Entry, HashMap};
+use petgraph::graph::{NodeIndex, UnGraph};
+
+use crate::{
+    bundle::{BundleField, BundleType},
+    enum_::{EnumType, EnumVariant},
+    expr::target::{TargetPathArrayElement, TargetPathBundleField, TargetPathElement},
+    intern::{Intern, Interned, Memoize},
+    module::{
+        AnnotatedModuleIO, ExprInInstantiatedModule, ExternModuleBody, InstantiatedModule,
+        ModuleBody, NormalModuleBody, TargetInInstantiatedModule,
+    },
+    prelude::*,
+};
+use std::fmt;
+
+#[derive(Debug)]
+pub enum DeduceResetsError {
+    ResetIsNotDrivenByAsyncOrSync { target: TargetInInstantiatedModule },
+}
+
+impl fmt::Display for DeduceResetsError {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self {
+            DeduceResetsError::ResetIsNotDrivenByAsyncOrSync { target } => {
+                write!(f, "deduce_reset failed: Reset signal is not driven by any AsyncReset or SyncReset signals: {target:?}")
+            }
+        }
+    }
+}
+
+impl std::error::Error for DeduceResetsError {}
+
+impl From<DeduceResetsError> for std::io::Error {
+    fn from(value: DeduceResetsError) -> Self {
+        std::io::Error::new(std::io::ErrorKind::Other, value)
+    }
+}
+
+#[derive(Debug)]
+struct Node {
+    target: TargetInInstantiatedModule,
+    deduced_type: Option<CanonicalType>,
+}
+
+#[derive(Debug)]
+struct State {
+    base_module: Interned<Module<Bundle>>,
+    transformed_exprs:
+        HashMap<ExprInInstantiatedModule<CanonicalType>, ExprInInstantiatedModule<CanonicalType>>,
+    node_ids: HashMap<TargetInInstantiatedModule, NodeIndex<u32>>,
+    graph: UnGraph<Node, ()>,
+    fallback_to_sync_reset: bool,
+}
+
+fn type_contains_any_undeduced_resets(ty: CanonicalType) -> bool {
+    #[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)]
+    struct MyMemoize;
+    impl Memoize for MyMemoize {
+        type Input = CanonicalType;
+        type InputOwned = CanonicalType;
+        type Output = bool;
+
+        fn inner(self, input: &Self::Input) -> Self::Output {
+            match input {
+                CanonicalType::UInt(_) => false,
+                CanonicalType::SInt(_) => false,
+                CanonicalType::Bool(_) => false,
+                CanonicalType::Array(ty) => type_contains_any_undeduced_resets(ty.element()),
+                CanonicalType::Enum(ty) => {
+                    ty.variants().iter().any(|EnumVariant { ty, .. }| {
+                        ty.is_some_and(|ty| type_contains_any_undeduced_resets(ty))
+                    })
+                }
+                CanonicalType::Bundle(ty) => ty
+                    .fields()
+                    .iter()
+                    .any(|&BundleField { ty, .. }| type_contains_any_undeduced_resets(ty)),
+                CanonicalType::AsyncReset(_) => false,
+                CanonicalType::SyncReset(_) => false,
+                CanonicalType::Reset(_) => true,
+                CanonicalType::Clock(_) => false,
+            }
+        }
+    }
+    MyMemoize.get_owned(ty)
+}
+
+impl State {
+    fn add_target_to_graph_recursive(
+        &mut self,
+        target: TargetInInstantiatedModule,
+    ) -> NodeIndex<u32> {
+        let entry = match self.node_ids.entry(target) {
+            Entry::Vacant(entry) => entry,
+            Entry::Occupied(entry) => {
+                return *entry.get();
+            }
+        };
+        let ty = target.target.canonical_ty();
+        let node_id = self.graph.add_node(Node {
+            target,
+            deduced_type: type_contains_any_undeduced_resets(ty).then_some(ty),
+        });
+        entry.insert(node_id);
+        match target.target.canonical_ty() {
+            CanonicalType::UInt(_)
+            | CanonicalType::SInt(_)
+            | CanonicalType::Bool(_)
+            | CanonicalType::AsyncReset(_)
+            | CanonicalType::SyncReset(_)
+            | CanonicalType::Clock(_) => {}
+            CanonicalType::Array(ty) => {
+                for index in 0..ty.len() {
+                    self.add_target_to_graph_recursive(TargetInInstantiatedModule {
+                        instantiated_module: target.instantiated_module,
+                        target: target.target.join(
+                            TargetPathElement::from(TargetPathArrayElement { index })
+                                .intern_sized(),
+                        ),
+                    });
+                }
+            }
+            CanonicalType::Enum(_) => {}
+            CanonicalType::Bundle(ty) => {
+                for BundleField { name, .. } in ty.fields() {
+                    self.add_target_to_graph_recursive(TargetInInstantiatedModule {
+                        instantiated_module: target.instantiated_module,
+                        target: target.target.join(
+                            TargetPathElement::from(TargetPathBundleField { name }).intern_sized(),
+                        ),
+                    });
+                }
+            }
+            CanonicalType::Reset(_) => {}
+        }
+        node_id
+    }
+    fn build_graph_for_module(&mut self, instantiated_module: Interned<InstantiatedModule>) {
+        let Module {
+            name: _,
+            source_location: _,
+            body,
+            io_ty: _,
+            module_io,
+            module_annotations: _,
+        } = *instantiated_module.leaf_module();
+        for AnnotatedModuleIO {
+            annotations: _,
+            module_io,
+        } in module_io
+        {
+            self.add_target_to_graph_recursive(TargetInInstantiatedModule {
+                instantiated_module: *instantiated_module,
+                target: module_io.into(),
+            });
+        }
+        match body {
+            ModuleBody::Normal(NormalModuleBody { body }) => todo!(),
+            ModuleBody::Extern(ExternModuleBody {
+                verilog_name: _,
+                parameters: _,
+            }) => {}
+        }
+    }
+    fn deduce_types(&mut self) -> Result<(), DeduceResetsError> {
+        todo!()
+    }
+    fn transform_module(&mut self, module: Interned<Module<Bundle>>) -> Interned<Module<Bundle>> {
+        todo!()
+    }
+}
+
+pub fn deduce_resets(
+    module: Interned<Module<Bundle>>,
+    fallback_to_sync_reset: bool,
+) -> Result<Interned<Module<Bundle>>, DeduceResetsError> {
+    let mut state = State {
+        base_module: module,
+        transformed_exprs: HashMap::new(),
+        node_ids: HashMap::new(),
+        graph: UnGraph::new_undirected(),
+        fallback_to_sync_reset,
+    };
+    state.build_graph_for_module(InstantiatedModule::Base(module).intern_sized());
+    state.deduce_types()?;
+    Ok(state.transform_module(module))
+}
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index fb5a1e0..1bed47d 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -16,9 +16,9 @@ use crate::{
     int::BoolOrIntType,
     intern::{Intern, Interned, Memoize},
     module::{
-        AnnotatedModuleIO, Block, Id, ModuleBody, NameId, NormalModuleBody, ScopedNameId, Stmt,
-        StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg,
-        StmtWire,
+        AnnotatedModuleIO, Block, Id, InstantiatedModule, ModuleBody, NameId, NormalModuleBody,
+        ScopedNameId, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance,
+        StmtMatch, StmtReg, StmtWire, TargetInInstantiatedModule,
     },
     prelude::*,
     sim::{
@@ -68,47 +68,6 @@ struct Cond {
     source_location: SourceLocation,
 }
 
-#[derive(PartialEq, Eq, Hash, Clone, Copy)]
-enum InstantiatedModule {
-    Base(Interned<Module<Bundle>>),
-    Child {
-        parent: Interned<InstantiatedModule>,
-        instance: Interned<Instance<Bundle>>,
-    },
-}
-
-impl InstantiatedModule {
-    fn leaf_module(self) -> Interned<Module<Bundle>> {
-        match self {
-            InstantiatedModule::Base(base) => base,
-            InstantiatedModule::Child { instance, .. } => instance.instantiated(),
-        }
-    }
-    fn write_path(self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        match self {
-            InstantiatedModule::Base(base) => fmt::Debug::fmt(&base.name_id(), f),
-            InstantiatedModule::Child { parent, instance } => {
-                parent.write_path(f)?;
-                write!(f, ".{}", instance.name_id())
-            }
-        }
-    }
-}
-
-impl fmt::Debug for InstantiatedModule {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        write!(f, "InstantiatedModule(")?;
-        self.write_path(f)?;
-        write!(f, ": {})", self.leaf_module().name_id())
-    }
-}
-
-#[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
-struct TargetInInstantiatedModule {
-    instantiated_module: InstantiatedModule,
-    target: Target,
-}
-
 #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
 struct CompiledBundleField {
     offset: TypeIndex,

From 59be3bd645cdca9b6d4276b0e8141375075b6785 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 24 Nov 2024 03:44:31 -0800
Subject: [PATCH 094/190] WIP working on implementing deduce_resets pass

---
 crates/fayalite/src/module.rs                 |  16 +-
 .../src/module/transform/deduce_resets.rs     | 709 +++++++++++++++---
 2 files changed, 637 insertions(+), 88 deletions(-)

diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index b8610e7..915bf43 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -180,7 +180,7 @@ impl Block {
     }
 }
 
-#[derive(Clone, PartialEq, Eq, Hash)]
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
 pub struct StmtConnect {
     pub lhs: Expr<CanonicalType>,
     pub rhs: Expr<CanonicalType>,
@@ -235,7 +235,7 @@ impl fmt::Debug for StmtConnect {
     }
 }
 
-#[derive(Clone, PartialEq, Eq, Hash)]
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
 pub struct StmtFormal {
     pub kind: FormalKind,
     pub clk: Expr<Clock>,
@@ -284,6 +284,8 @@ pub struct StmtIf<S: ModuleBuildingStatus = ModuleBuilt> {
     pub blocks: [S::Block; 2],
 }
 
+impl Copy for StmtIf {}
+
 impl<S: ModuleBuildingStatus> StmtIf<S> {
     pub fn then_block(&self) -> S::Block {
         self.blocks[0]
@@ -315,6 +317,8 @@ pub struct StmtMatch<S: ModuleBuildingStatus = ModuleBuilt> {
     pub blocks: Interned<[S::Block]>,
 }
 
+impl Copy for StmtMatch {}
+
 impl StmtMatch {
     #[track_caller]
     fn assert_validity(&self) {
@@ -459,6 +463,8 @@ pub struct StmtWire<S: ModuleBuildingStatus = ModuleBuilt> {
     pub wire: Wire<CanonicalType>,
 }
 
+impl Copy for StmtWire {}
+
 #[derive(Hash, Clone, PartialEq, Eq, Debug)]
 pub struct StmtReg<S: ModuleBuildingStatus = ModuleBuilt> {
     pub annotations: S::StmtAnnotations,
@@ -473,6 +479,8 @@ pub struct StmtInstance<S: ModuleBuildingStatus = ModuleBuilt> {
     pub instance: Instance<Bundle>,
 }
 
+impl Copy for StmtInstance {}
+
 wrapper_enum! {
     #[impl(
         (<S: ModuleBuildingStatus>) self: StmtDeclaration<S> = self,
@@ -490,6 +498,8 @@ wrapper_enum! {
     }
 }
 
+impl Copy for StmtDeclaration {}
+
 impl<S: ModuleBuildingStatus> StmtDeclaration<S> {
     pub fn annotations(&self) -> S::StmtAnnotations {
         match self {
@@ -546,6 +556,8 @@ wrapper_enum! {
     }
 }
 
+impl Copy for Stmt {}
+
 impl<S: ModuleBuildingStatus> Stmt<S> {
     pub fn sub_stmt_blocks(&self) -> &[S::Block] {
         match self {
diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs
index dc01b33..9b5cee3 100644
--- a/crates/fayalite/src/module/transform/deduce_resets.rs
+++ b/crates/fayalite/src/module/transform/deduce_resets.rs
@@ -2,20 +2,28 @@
 // See Notices.txt for copyright information
 
 use hashbrown::{hash_map::Entry, HashMap};
-use petgraph::graph::{NodeIndex, UnGraph};
+use petgraph::{
+    graph::{NodeIndex, UnGraph},
+    unionfind::UnionFind,
+};
 
 use crate::{
     bundle::{BundleField, BundleType},
     enum_::{EnumType, EnumVariant},
-    expr::target::{TargetPathArrayElement, TargetPathBundleField, TargetPathElement},
+    expr::{
+        ops,
+        target::{TargetBase, TargetPathArrayElement, TargetPathBundleField, TargetPathElement},
+        Flow,
+    },
     intern::{Intern, Interned, Memoize},
     module::{
-        AnnotatedModuleIO, ExprInInstantiatedModule, ExternModuleBody, InstantiatedModule,
-        ModuleBody, NormalModuleBody, TargetInInstantiatedModule,
+        AnnotatedModuleIO, Block, ExprInInstantiatedModule, ExternModuleBody, InstantiatedModule,
+        ModuleBody, ModuleIO, NormalModuleBody, Stmt, StmtConnect, StmtDeclaration, StmtFormal,
+        StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire, TargetInInstantiatedModule,
     },
     prelude::*,
 };
-use std::fmt;
+use std::{convert::Infallible, fmt};
 
 #[derive(Debug)]
 pub enum DeduceResetsError {
@@ -40,18 +48,132 @@ impl From<DeduceResetsError> for std::io::Error {
     }
 }
 
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+enum ResetTarget {
+    Base {
+        base: Interned<TargetBase>,
+    },
+    BundleField {
+        parent: Interned<ResetTarget>,
+        field_ty: CanonicalType,
+        field_index: usize,
+    },
+    EnumVariant {
+        parent: Interned<ResetTarget>,
+        variant_ty: CanonicalType,
+        variant_index: usize,
+    },
+    /// Array's Elements:
+    /// deduce_resets requires all array elements to deduce to the same pattern of async/sync resets,
+    /// so we don't track individual array elements but instead track all of an array's elements together.
+    ArraysElements {
+        parent: Interned<ResetTarget>,
+        element_ty: CanonicalType,
+    },
+}
+
+impl ResetTarget {
+    fn canonical_ty(self) -> CanonicalType {
+        match self {
+            ResetTarget::Base { base } => base.canonical_ty(),
+            ResetTarget::BundleField { field_ty, .. } => field_ty,
+            ResetTarget::EnumVariant { variant_ty, .. } => variant_ty,
+            ResetTarget::ArraysElements { element_ty, .. } => element_ty,
+        }
+    }
+    fn parent(self) -> Option<Interned<ResetTarget>> {
+        match self {
+            ResetTarget::Base { .. } => None,
+            ResetTarget::BundleField { parent, .. }
+            | ResetTarget::EnumVariant { parent, .. }
+            | ResetTarget::ArraysElements { parent, .. } => Some(parent),
+        }
+    }
+    fn base(mut self) -> Interned<TargetBase> {
+        loop {
+            match self {
+                ResetTarget::Base { base } => break base,
+                ResetTarget::BundleField { parent, .. }
+                | ResetTarget::EnumVariant { parent, .. }
+                | ResetTarget::ArraysElements { parent, .. } => self = *parent,
+            }
+        }
+    }
+    fn bundle_field(self, field_index: usize) -> Self {
+        let field_ty = Bundle::from_canonical(self.canonical_ty()).fields()[field_index].ty;
+        Self::BundleField {
+            parent: self.intern_sized(),
+            field_ty,
+            field_index,
+        }
+    }
+    fn enum_variant(self, variant_index: usize) -> Self {
+        let variant_ty = Enum::from_canonical(self.canonical_ty()).variants()[variant_index]
+            .ty
+            .expect("known to have a variant field");
+        Self::EnumVariant {
+            parent: self.intern_sized(),
+            variant_ty,
+            variant_index,
+        }
+    }
+    fn arrays_elements(self) -> Self {
+        let element_ty = <Array>::from_canonical(self.canonical_ty()).element();
+        Self::ArraysElements {
+            parent: self.intern_sized(),
+            element_ty,
+        }
+    }
+    fn for_each_child<E>(self, mut f: impl FnMut(ResetTarget) -> Result<(), E>) -> Result<(), E> {
+        match self.canonical_ty() {
+            CanonicalType::UInt(_)
+            | CanonicalType::SInt(_)
+            | CanonicalType::Bool(_)
+            | CanonicalType::AsyncReset(_)
+            | CanonicalType::SyncReset(_)
+            | CanonicalType::Reset(_)
+            | CanonicalType::Clock(_) => Ok(()),
+            CanonicalType::Array(_) => f(self.arrays_elements()),
+            CanonicalType::Enum(ty) => {
+                for variant_index in 0..ty.variants().len() {
+                    f(self.enum_variant(variant_index))?;
+                }
+                Ok(())
+            }
+            CanonicalType::Bundle(ty) => {
+                for field_index in 0..ty.fields().len() {
+                    f(self.bundle_field(field_index))?;
+                }
+                Ok(())
+            }
+        }
+    }
+}
+
+impl<T: Into<TargetBase>> From<T> for ResetTarget {
+    fn from(base: T) -> Self {
+        ResetTarget::Base {
+            base: TargetBase::intern_sized(base.into()),
+        }
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+struct ResetTargetInInstantiatedModule {
+    instantiated_module: InstantiatedModule,
+    target: ResetTarget,
+}
+
 #[derive(Debug)]
 struct Node {
-    target: TargetInInstantiatedModule,
+    target: ResetTargetInInstantiatedModule,
     deduced_type: Option<CanonicalType>,
 }
 
 #[derive(Debug)]
 struct State {
     base_module: Interned<Module<Bundle>>,
-    transformed_exprs:
-        HashMap<ExprInInstantiatedModule<CanonicalType>, ExprInInstantiatedModule<CanonicalType>>,
-    node_ids: HashMap<TargetInInstantiatedModule, NodeIndex<u32>>,
+    node_ids: HashMap<ResetTargetInInstantiatedModule, NodeIndex<u32>>,
     graph: UnGraph<Node, ()>,
     fallback_to_sync_reset: bool,
 }
@@ -89,88 +211,499 @@ fn type_contains_any_undeduced_resets(ty: CanonicalType) -> bool {
     MyMemoize.get_owned(ty)
 }
 
-impl State {
-    fn add_target_to_graph_recursive(
-        &mut self,
-        target: TargetInInstantiatedModule,
-    ) -> NodeIndex<u32> {
-        let entry = match self.node_ids.entry(target) {
-            Entry::Vacant(entry) => entry,
-            Entry::Occupied(entry) => {
-                return *entry.get();
-            }
+trait ProcessStep {
+    type Error;
+    type Processed<T>;
+    fn processed_as_ref<T>(v: &Self::Processed<T>) -> Self::Processed<&T>;
+    fn processed_as_mut<T>(v: &mut Self::Processed<T>) -> Self::Processed<&mut T>;
+    fn processed_zip<T, U>(t: Self::Processed<T>, u: Self::Processed<U>)
+        -> Self::Processed<(T, U)>;
+    fn processed_map<T, U>(v: Self::Processed<T>, f: impl FnOnce(T) -> U) -> Self::Processed<U>;
+    fn processed_make<T>(t: T) -> Self::Processed<T>;
+    fn processed_from_iter<T, O: FromIterator<T>>(
+        iter: impl IntoIterator<Item = Self::Processed<T>>,
+    ) -> Self::Processed<O>;
+}
+
+macro_rules! impl_process_step_with_empty_processed {
+    () => {
+        type Processed<T> = ();
+        fn processed_as_ref<T>(v: &Self::Processed<T>) -> Self::Processed<&T> {
+            *v
+        }
+        fn processed_as_mut<T>(v: &mut Self::Processed<T>) -> Self::Processed<&mut T> {
+            *v
+        }
+        fn processed_zip<T, U>(
+            t: Self::Processed<T>,
+            u: Self::Processed<U>,
+        ) -> Self::Processed<(T, U)> {
+            let _ = t;
+            let _ = u;
+            ()
+        }
+        fn processed_map<T, U>(
+            v: Self::Processed<T>,
+            f: impl FnOnce(T) -> U,
+        ) -> Self::Processed<U> {
+            let _ = f;
+            v
+        }
+        fn processed_make<T>(t: T) -> Self::Processed<T> {
+            let _ = t;
+            ()
+        }
+        fn processed_from_iter<T, O: FromIterator<T>>(
+            iter: impl IntoIterator<Item = Self::Processed<T>>,
+        ) -> Self::Processed<O> {
+            FromIterator::from_iter(iter)
+        }
+    };
+}
+
+struct Processed<T, Step: ProcessStep>(Step::Processed<T>);
+
+impl<T, Step: ProcessStep> Processed<T, Step> {
+    fn as_ref(&self) -> Processed<&T, Step> {
+        Processed(Step::processed_as_ref(&self.0))
+    }
+    fn as_mut(&mut self) -> Processed<&mut T, Step> {
+        Processed(Step::processed_as_mut(&mut self.0))
+    }
+    fn zip<U>(self, u: Processed<U, Step>) -> Processed<(T, U), Step> {
+        Processed(Step::processed_zip(self.0, u.0))
+    }
+    fn new(v: T) -> Self {
+        Processed(Step::processed_make(v))
+    }
+    fn map<U>(self, f: impl FnOnce(T) -> U) -> Processed<U, Step> {
+        Processed(Step::processed_map(self.0, f))
+    }
+}
+
+impl<C: FromIterator<A>, A, Step: ProcessStep> FromIterator<Processed<A, Step>>
+    for Processed<C, Step>
+{
+    fn from_iter<T: IntoIterator<Item = Processed<A, Step>>>(iter: T) -> Self {
+        Processed(Step::processed_from_iter(iter.into_iter().map(|v| v.0)))
+    }
+}
+
+struct AddNodesToGraphStep;
+
+impl ProcessStep for AddNodesToGraphStep {
+    type Error = Infallible;
+    impl_process_step_with_empty_processed!();
+}
+
+struct AddEdgesToGraphStep {
+    union_find: UnionFind<u32>,
+}
+
+impl ProcessStep for AddEdgesToGraphStep {
+    type Error = Infallible;
+    impl_process_step_with_empty_processed!();
+}
+
+trait RunProcessStep<Step: ProcessStep>: Sized {
+    fn run_process_step(
+        self,
+        instantiated_module: InstantiatedModule,
+        state: &mut State,
+        step: &mut Step,
+    ) -> Result<Processed<Self, Step>, Step::Error>;
+}
+
+impl RunProcessStep<AddNodesToGraphStep> for ResetTarget {
+    fn run_process_step(
+        self,
+        instantiated_module: InstantiatedModule,
+        state: &mut State,
+        step: &mut AddNodesToGraphStep,
+    ) -> Result<Processed<Self, AddNodesToGraphStep>, Infallible> {
+        let target = ResetTargetInInstantiatedModule {
+            instantiated_module,
+            target: self,
         };
-        let ty = target.target.canonical_ty();
-        let node_id = self.graph.add_node(Node {
+        let Entry::Vacant(entry) = state.node_ids.entry(target) else {
+            return Ok(Processed(()));
+        };
+        let ty = self.canonical_ty();
+        let node_id = state.graph.add_node(Node {
             target,
             deduced_type: type_contains_any_undeduced_resets(ty).then_some(ty),
         });
         entry.insert(node_id);
-        match target.target.canonical_ty() {
-            CanonicalType::UInt(_)
-            | CanonicalType::SInt(_)
-            | CanonicalType::Bool(_)
-            | CanonicalType::AsyncReset(_)
-            | CanonicalType::SyncReset(_)
-            | CanonicalType::Clock(_) => {}
-            CanonicalType::Array(ty) => {
-                for index in 0..ty.len() {
-                    self.add_target_to_graph_recursive(TargetInInstantiatedModule {
-                        instantiated_module: target.instantiated_module,
-                        target: target.target.join(
-                            TargetPathElement::from(TargetPathArrayElement { index })
-                                .intern_sized(),
-                        ),
-                    });
-                }
-            }
-            CanonicalType::Enum(_) => {}
-            CanonicalType::Bundle(ty) => {
-                for BundleField { name, .. } in ty.fields() {
-                    self.add_target_to_graph_recursive(TargetInInstantiatedModule {
-                        instantiated_module: target.instantiated_module,
-                        target: target.target.join(
-                            TargetPathElement::from(TargetPathBundleField { name }).intern_sized(),
-                        ),
-                    });
-                }
-            }
-            CanonicalType::Reset(_) => {}
-        }
-        node_id
+        self.for_each_child(|target| -> Result<(), Infallible> {
+            target.run_process_step(instantiated_module, state, step)?;
+            Ok(())
+        })?;
+        Ok(Processed(()))
     }
-    fn build_graph_for_module(&mut self, instantiated_module: Interned<InstantiatedModule>) {
-        let Module {
-            name: _,
-            source_location: _,
-            body,
-            io_ty: _,
-            module_io,
-            module_annotations: _,
-        } = *instantiated_module.leaf_module();
-        for AnnotatedModuleIO {
-            annotations: _,
-            module_io,
-        } in module_io
-        {
-            self.add_target_to_graph_recursive(TargetInInstantiatedModule {
-                instantiated_module: *instantiated_module,
-                target: module_io.into(),
-            });
+}
+
+struct ConnectAndLhsInstantiatedModule {
+    lhs_instantiated_module: InstantiatedModule,
+    lhs: Expr<CanonicalType>,
+    rhs: Expr<CanonicalType>,
+    source_location: SourceLocation,
+}
+
+impl<Step: ProcessStep> RunProcessStep<Step> for ConnectAndLhsInstantiatedModule {
+    fn run_process_step(
+        self,
+        rhs_instantiated_module: InstantiatedModule,
+        state: &mut State,
+        step: &mut Step,
+    ) -> Result<Processed<Self, Step>, Step::Error> {
+        let Self {
+            lhs_instantiated_module,
+            lhs,
+            rhs,
+            source_location,
+        } = self;
+        todo!();
+    }
+}
+
+impl<Step: ProcessStep> RunProcessStep<Step> for StmtConnect {
+    fn run_process_step(
+        self,
+        instantiated_module: InstantiatedModule,
+        state: &mut State,
+        step: &mut Step,
+    ) -> Result<Processed<Self, Step>, Step::Error> {
+        let StmtConnect {
+            lhs,
+            rhs,
+            source_location,
+        } = self;
+        Ok(ConnectAndLhsInstantiatedModule {
+            lhs_instantiated_module: instantiated_module,
+            lhs,
+            rhs,
+            source_location,
         }
-        match body {
-            ModuleBody::Normal(NormalModuleBody { body }) => todo!(),
-            ModuleBody::Extern(ExternModuleBody {
+        .run_process_step(instantiated_module, state, step)?
+        .map(
+            |ConnectAndLhsInstantiatedModule {
+                 lhs_instantiated_module: _,
+                 lhs,
+                 rhs,
+                 source_location,
+             }| StmtConnect {
+                lhs,
+                rhs,
+                source_location,
+            },
+        ))
+    }
+}
+
+impl<Step: ProcessStep> RunProcessStep<Step> for StmtFormal {
+    fn run_process_step(
+        self,
+        _instantiated_module: InstantiatedModule,
+        _state: &mut State,
+        _step: &mut Step,
+    ) -> Result<Processed<Self, Step>, Step::Error> {
+        // no inputs are Reset
+        Ok(Processed::new(self))
+    }
+}
+
+impl<Step: ProcessStep> RunProcessStep<Step> for StmtIf {
+    fn run_process_step(
+        self,
+        instantiated_module: InstantiatedModule,
+        state: &mut State,
+        step: &mut Step,
+    ) -> Result<Processed<Self, Step>, Step::Error> {
+        todo!()
+    }
+}
+
+impl<Step: ProcessStep> RunProcessStep<Step> for StmtMatch {
+    fn run_process_step(
+        self,
+        instantiated_module: InstantiatedModule,
+        state: &mut State,
+        step: &mut Step,
+    ) -> Result<Processed<Self, Step>, Step::Error> {
+        todo!()
+    }
+}
+
+impl<Step: ProcessStep> RunProcessStep<Step> for ModuleIO<CanonicalType>
+where
+    ResetTarget: RunProcessStep<Step>,
+{
+    fn run_process_step(
+        self,
+        instantiated_module: InstantiatedModule,
+        state: &mut State,
+        step: &mut Step,
+    ) -> Result<Processed<Self, Step>, Step::Error> {
+        Ok(ResetTarget::from(self)
+            .run_process_step(instantiated_module, state, step)?
+            .map(|target| {
+                let ResetTarget::Base { base } = target else {
+                    unreachable!();
+                };
+                let TargetBase::ModuleIO(module_io) = *base else {
+                    unreachable!();
+                };
+                module_io
+            }))
+    }
+}
+
+impl<Step: ProcessStep> RunProcessStep<Step> for StmtWire
+where
+    ResetTarget: RunProcessStep<Step>,
+{
+    fn run_process_step(
+        self,
+        instantiated_module: InstantiatedModule,
+        state: &mut State,
+        step: &mut Step,
+    ) -> Result<Processed<Self, Step>, Step::Error> {
+        let Self { annotations, wire } = self;
+        Ok(ResetTarget::from(wire)
+            .run_process_step(instantiated_module, state, step)?
+            .map(|target| {
+                let ResetTarget::Base { base } = target else {
+                    unreachable!();
+                };
+                let TargetBase::Wire(wire) = *base else {
+                    unreachable!();
+                };
+                Self { annotations, wire }
+            }))
+    }
+}
+
+impl<Step: ProcessStep> RunProcessStep<Step> for StmtReg
+where
+    ResetTarget: RunProcessStep<Step>,
+{
+    fn run_process_step(
+        self,
+        instantiated_module: InstantiatedModule,
+        state: &mut State,
+        step: &mut Step,
+    ) -> Result<Processed<Self, Step>, Step::Error> {
+        let Self { annotations, reg } = self;
+        Ok(ResetTarget::from(reg)
+            .run_process_step(instantiated_module, state, step)?
+            .map(|target| {
+                let ResetTarget::Base { base } = target else {
+                    unreachable!();
+                };
+                let TargetBase::Reg(reg) = *base else {
+                    unreachable!();
+                };
+                Self { annotations, reg }
+            }))
+    }
+}
+
+impl<Step: ProcessStep> RunProcessStep<Step> for StmtInstance
+where
+    ResetTarget: RunProcessStep<Step>,
+{
+    fn run_process_step(
+        self,
+        instantiated_module: InstantiatedModule,
+        state: &mut State,
+        step: &mut Step,
+    ) -> Result<Processed<Self, Step>, Step::Error> {
+        let Self {
+            annotations,
+            instance,
+        } = self;
+        let child_instantiated_module = InstantiatedModule::Child {
+            parent: instantiated_module.intern_sized(),
+            instance: instance.intern_sized(),
+        };
+        instance
+            .instantiated()
+            .run_process_step(child_instantiated_module, state, step)?;
+        for (field_index, AnnotatedModuleIO { module_io, .. }) in
+            instance.instantiated().module_io().into_iter().enumerate()
+        {
+            let (lhs_instantiated_module, lhs, rhs_instantiated_module, rhs) = match module_io
+                .flow()
+            {
+                Flow::Source => {
+                    // connect to submodule's input from instance input
+                    (
+                        child_instantiated_module,
+                        module_io.to_expr(),
+                        instantiated_module,
+                        ops::FieldAccess::new_by_index(instance.to_expr(), field_index).to_expr(),
+                    )
+                }
+                Flow::Sink => {
+                    // connect to instance output from submodule's output
+                    (
+                        instantiated_module,
+                        ops::FieldAccess::new_by_index(instance.to_expr(), field_index).to_expr(),
+                        child_instantiated_module,
+                        module_io.to_expr(),
+                    )
+                }
+                Flow::Duplex => unreachable!(),
+            };
+            ConnectAndLhsInstantiatedModule {
+                lhs_instantiated_module,
+                lhs,
+                rhs,
+                source_location: instance.source_location(),
+            }
+            .run_process_step(rhs_instantiated_module, state, step)?;
+        }
+        Ok(ResetTarget::from(instance)
+            .run_process_step(instantiated_module, state, step)?
+            .map(|target| {
+                let ResetTarget::Base { base } = target else {
+                    unreachable!();
+                };
+                let TargetBase::Instance(instance) = *base else {
+                    unreachable!();
+                };
+                Self {
+                    annotations,
+                    instance,
+                }
+            }))
+    }
+}
+
+impl<Step: ProcessStep> RunProcessStep<Step> for StmtDeclaration
+where
+    ResetTarget: RunProcessStep<Step>,
+{
+    fn run_process_step(
+        self,
+        instantiated_module: InstantiatedModule,
+        state: &mut State,
+        step: &mut Step,
+    ) -> Result<Processed<Self, Step>, Step::Error> {
+        Ok(match self {
+            StmtDeclaration::Wire(decl) => decl
+                .run_process_step(instantiated_module, state, step)?
+                .map(StmtDeclaration::from),
+            StmtDeclaration::Reg(decl) => decl
+                .run_process_step(instantiated_module, state, step)?
+                .map(StmtDeclaration::from),
+            StmtDeclaration::Instance(decl) => decl
+                .run_process_step(instantiated_module, state, step)?
+                .map(StmtDeclaration::from),
+        })
+    }
+}
+
+impl<Step: ProcessStep> RunProcessStep<Step> for Stmt
+where
+    ResetTarget: RunProcessStep<Step>,
+{
+    fn run_process_step(
+        self,
+        instantiated_module: InstantiatedModule,
+        state: &mut State,
+        step: &mut Step,
+    ) -> Result<Processed<Self, Step>, Step::Error> {
+        Ok(match self {
+            Stmt::Connect(stmt) => stmt
+                .run_process_step(instantiated_module, state, step)?
+                .map(Stmt::from),
+            Stmt::Formal(stmt) => stmt
+                .run_process_step(instantiated_module, state, step)?
+                .map(Stmt::from),
+            Stmt::If(stmt) => stmt
+                .run_process_step(instantiated_module, state, step)?
+                .map(Stmt::from),
+            Stmt::Match(stmt) => stmt
+                .run_process_step(instantiated_module, state, step)?
+                .map(Stmt::from),
+            Stmt::Declaration(stmt) => stmt
+                .run_process_step(instantiated_module, state, step)?
+                .map(Stmt::from),
+        })
+    }
+}
+
+impl<Step: ProcessStep> RunProcessStep<Step> for Block
+where
+    ResetTarget: RunProcessStep<Step>,
+{
+    fn run_process_step(
+        self,
+        instantiated_module: InstantiatedModule,
+        state: &mut State,
+        step: &mut Step,
+    ) -> Result<Processed<Self, Step>, Step::Error> {
+        let Block { memories, stmts } = self;
+        // memories and memory ports won't ever contain any Reset values,
+        // so always just use the old `memories` value. we add the ports to the graph anyway to make the other logic easier.
+        for memory in memories {
+            for port in memory.ports() {
+                ResetTarget::from(port).run_process_step(instantiated_module, state, step)?;
+            }
+        }
+        let stmts = Result::<Processed<_, _>, _>::from_iter(
+            stmts
+                .iter()
+                .map(|stmt| stmt.run_process_step(instantiated_module, state, step)),
+        )?;
+        Ok(stmts.map(|stmts| Block { memories, stmts }))
+    }
+}
+
+impl<Step: ProcessStep> RunProcessStep<Step> for Module<Bundle>
+where
+    ResetTarget: RunProcessStep<Step>,
+{
+    fn run_process_step(
+        self,
+        instantiated_module: InstantiatedModule,
+        state: &mut State,
+        step: &mut Step,
+    ) -> Result<Processed<Self, Step>, Step::Error> {
+        let module = *instantiated_module.leaf_module();
+        let module_io =
+            Result::<Processed<Interned<[_]>, _>, _>::from_iter(module.module_io().iter().map(
+                |&AnnotatedModuleIO {
+                     annotations,
+                     module_io,
+                 }| {
+                    Ok(module_io
+                        .run_process_step(instantiated_module, state, step)?
+                        .map(|module_io| AnnotatedModuleIO {
+                            annotations,
+                            module_io,
+                        }))
+                },
+            ))?;
+        let body = match module.body() {
+            ModuleBody::Normal(NormalModuleBody { body }) => body
+                .run_process_step(instantiated_module, state, step)?
+                .map(|body| ModuleBody::Normal(NormalModuleBody { body })),
+            body @ ModuleBody::Extern(ExternModuleBody {
                 verilog_name: _,
                 parameters: _,
-            }) => {}
-        }
-    }
-    fn deduce_types(&mut self) -> Result<(), DeduceResetsError> {
-        todo!()
-    }
-    fn transform_module(&mut self, module: Interned<Module<Bundle>>) -> Interned<Module<Bundle>> {
-        todo!()
+            }) => Processed::new(body),
+        };
+        Ok(module_io.zip(body).map(|(module_io, body)| {
+            Module::new_unchecked(
+                module.name_id(),
+                module.source_location(),
+                body,
+                module_io,
+                module.module_annotations(),
+            )
+        }))
     }
 }
 
@@ -180,12 +713,16 @@ pub fn deduce_resets(
 ) -> Result<Interned<Module<Bundle>>, DeduceResetsError> {
     let mut state = State {
         base_module: module,
-        transformed_exprs: HashMap::new(),
         node_ids: HashMap::new(),
         graph: UnGraph::new_undirected(),
         fallback_to_sync_reset,
     };
-    state.build_graph_for_module(InstantiatedModule::Base(module).intern_sized());
-    state.deduce_types()?;
-    Ok(state.transform_module(module))
+    let Ok(Processed(())) = module.run_process_step(
+        InstantiatedModule::Base(module),
+        &mut state,
+        &mut AddNodesToGraphStep,
+    );
+    todo!("add edges");
+    todo!("deduce types");
+    Ok(todo!("transform module"))
 }

From 698b8adc23fc3e9ff60ada4f3e87007e791aeca1 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 24 Nov 2024 14:39:32 -0800
Subject: [PATCH 095/190] working on deduce_resets pass

---
 .../src/module/transform/deduce_resets.rs     | 189 ++++++++++++------
 1 file changed, 126 insertions(+), 63 deletions(-)

diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs
index 9b5cee3..ecc2c43 100644
--- a/crates/fayalite/src/module/transform/deduce_resets.rs
+++ b/crates/fayalite/src/module/transform/deduce_resets.rs
@@ -10,16 +10,13 @@ use petgraph::{
 use crate::{
     bundle::{BundleField, BundleType},
     enum_::{EnumType, EnumVariant},
-    expr::{
-        ops,
-        target::{TargetBase, TargetPathArrayElement, TargetPathBundleField, TargetPathElement},
-        Flow,
-    },
+    expr::{ops, ExprEnum, Flow},
     intern::{Intern, Interned, Memoize},
     module::{
-        AnnotatedModuleIO, Block, ExprInInstantiatedModule, ExternModuleBody, InstantiatedModule,
-        ModuleBody, ModuleIO, NormalModuleBody, Stmt, StmtConnect, StmtDeclaration, StmtFormal,
-        StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire, TargetInInstantiatedModule,
+        transform::visit::{Visit, Visitor},
+        AnnotatedModuleIO, Block, ExternModuleBody, InstantiatedModule, ModuleBody, ModuleIO,
+        NormalModuleBody, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance,
+        StmtMatch, StmtReg, StmtWire, TargetInInstantiatedModule,
     },
     prelude::*,
 };
@@ -51,7 +48,7 @@ impl From<DeduceResetsError> for std::io::Error {
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
 enum ResetTarget {
     Base {
-        base: Interned<TargetBase>,
+        base: Expr<CanonicalType>,
     },
     BundleField {
         parent: Interned<ResetTarget>,
@@ -75,7 +72,7 @@ enum ResetTarget {
 impl ResetTarget {
     fn canonical_ty(self) -> CanonicalType {
         match self {
-            ResetTarget::Base { base } => base.canonical_ty(),
+            ResetTarget::Base { base } => Expr::ty(base),
             ResetTarget::BundleField { field_ty, .. } => field_ty,
             ResetTarget::EnumVariant { variant_ty, .. } => variant_ty,
             ResetTarget::ArraysElements { element_ty, .. } => element_ty,
@@ -89,7 +86,7 @@ impl ResetTarget {
             | ResetTarget::ArraysElements { parent, .. } => Some(parent),
         }
     }
-    fn base(mut self) -> Interned<TargetBase> {
+    fn base(mut self) -> Expr<CanonicalType> {
         loop {
             match self {
                 ResetTarget::Base { base } => break base,
@@ -150,14 +147,6 @@ impl ResetTarget {
     }
 }
 
-impl<T: Into<TargetBase>> From<T> for ResetTarget {
-    fn from(base: T) -> Self {
-        ResetTarget::Base {
-            base: TargetBase::intern_sized(base.into()),
-        }
-    }
-}
-
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
 struct ResetTargetInInstantiatedModule {
     instantiated_module: InstantiatedModule,
@@ -289,6 +278,23 @@ impl<C: FromIterator<A>, A, Step: ProcessStep> FromIterator<Processed<A, Step>>
     }
 }
 
+fn for_each_subexpr_exclusive<E>(
+    expr: Expr<CanonicalType>,
+    f: impl FnMut(Expr<CanonicalType>) -> Result<(), E>,
+) -> Result<(), E> {
+    struct MyVisitor<F> {
+        f: F,
+    }
+    impl<F: FnMut(Expr<CanonicalType>) -> Result<(), E>, E> Visitor for MyVisitor<F> {
+        type Error = E;
+        fn visit_expr_enum(&mut self, v: &ExprEnum) -> Result<(), Self::Error> {
+            (self.f)(v.to_expr())?;
+            v.default_visit(self)
+        }
+    }
+    Expr::expr_enum(expr).default_visit(&mut MyVisitor { f })
+}
+
 struct AddNodesToGraphStep;
 
 impl ProcessStep for AddNodesToGraphStep {
@@ -342,6 +348,41 @@ impl RunProcessStep<AddNodesToGraphStep> for ResetTarget {
     }
 }
 
+impl RunProcessStep<AddEdgesToGraphStep> for ResetTarget {
+    fn run_process_step(
+        self,
+        _instantiated_module: InstantiatedModule,
+        _state: &mut State,
+        _step: &mut AddEdgesToGraphStep,
+    ) -> Result<Processed<Self, AddEdgesToGraphStep>, Infallible> {
+        Ok(Processed(()))
+    }
+}
+
+impl<Step: ProcessStep> RunProcessStep<Step> for Expr<CanonicalType>
+where
+    ResetTarget: RunProcessStep<Step>,
+{
+    fn run_process_step(
+        self,
+        instantiated_module: InstantiatedModule,
+        state: &mut State,
+        step: &mut Step,
+    ) -> Result<Processed<Self, Step>, Step::Error> {
+        let retval = ResetTarget::Base { base: self }
+            .run_process_step(instantiated_module, state, step)?
+            .map(|target| match target {
+                ResetTarget::Base { base } => base,
+                _ => unreachable!(),
+            });
+        for_each_subexpr_exclusive(self, |base| {
+            ResetTarget::Base { base }.run_process_step(instantiated_module, state, step)?;
+            Ok(())
+        })?;
+        Ok(retval)
+    }
+}
+
 struct ConnectAndLhsInstantiatedModule {
     lhs_instantiated_module: InstantiatedModule,
     lhs: Expr<CanonicalType>,
@@ -349,24 +390,49 @@ struct ConnectAndLhsInstantiatedModule {
     source_location: SourceLocation,
 }
 
-impl<Step: ProcessStep> RunProcessStep<Step> for ConnectAndLhsInstantiatedModule {
+impl RunProcessStep<AddNodesToGraphStep> for ConnectAndLhsInstantiatedModule {
+    fn run_process_step(
+        self,
+        _instantiated_module: InstantiatedModule,
+        _state: &mut State,
+        _step: &mut AddNodesToGraphStep,
+    ) -> Result<Processed<Self, AddNodesToGraphStep>, Infallible> {
+        Ok(Processed(()))
+    }
+}
+
+impl RunProcessStep<AddEdgesToGraphStep> for ConnectAndLhsInstantiatedModule {
     fn run_process_step(
         self,
         rhs_instantiated_module: InstantiatedModule,
         state: &mut State,
-        step: &mut Step,
-    ) -> Result<Processed<Self, Step>, Step::Error> {
+        step: &mut AddEdgesToGraphStep,
+    ) -> Result<Processed<Self, AddEdgesToGraphStep>, Infallible> {
         let Self {
             lhs_instantiated_module,
             lhs,
             rhs,
             source_location,
         } = self;
-        todo!();
+        match Expr::ty(lhs) {
+            CanonicalType::UInt(ty) => todo!(),
+            CanonicalType::SInt(ty) => todo!(),
+            CanonicalType::Bool(ty) => todo!(),
+            CanonicalType::AsyncReset(ty) => todo!(),
+            CanonicalType::SyncReset(ty) => todo!(),
+            CanonicalType::Reset(ty) => todo!(),
+            CanonicalType::Clock(ty) => todo!(),
+            CanonicalType::Array(ty) => todo!(),
+            CanonicalType::Enum(ty) => todo!(),
+            CanonicalType::Bundle(ty) => todo!(),
+        }
     }
 }
 
-impl<Step: ProcessStep> RunProcessStep<Step> for StmtConnect {
+impl<Step: ProcessStep> RunProcessStep<Step> for StmtConnect
+where
+    ConnectAndLhsInstantiatedModule: RunProcessStep<Step>,
+{
     fn run_process_step(
         self,
         instantiated_module: InstantiatedModule,
@@ -444,16 +510,12 @@ where
         state: &mut State,
         step: &mut Step,
     ) -> Result<Processed<Self, Step>, Step::Error> {
-        Ok(ResetTarget::from(self)
+        Ok(self
+            .to_expr()
             .run_process_step(instantiated_module, state, step)?
-            .map(|target| {
-                let ResetTarget::Base { base } = target else {
-                    unreachable!();
-                };
-                let TargetBase::ModuleIO(module_io) = *base else {
-                    unreachable!();
-                };
-                module_io
+            .map(|expr| match *Expr::expr_enum(expr) {
+                ExprEnum::ModuleIO(module_io) => module_io,
+                _ => unreachable!(),
             }))
     }
 }
@@ -469,16 +531,12 @@ where
         step: &mut Step,
     ) -> Result<Processed<Self, Step>, Step::Error> {
         let Self { annotations, wire } = self;
-        Ok(ResetTarget::from(wire)
+        Ok(wire
+            .to_expr()
             .run_process_step(instantiated_module, state, step)?
-            .map(|target| {
-                let ResetTarget::Base { base } = target else {
-                    unreachable!();
-                };
-                let TargetBase::Wire(wire) = *base else {
-                    unreachable!();
-                };
-                Self { annotations, wire }
+            .map(|expr| match *Expr::expr_enum(expr) {
+                ExprEnum::Wire(wire) => Self { annotations, wire },
+                _ => unreachable!(),
             }))
     }
 }
@@ -494,16 +552,12 @@ where
         step: &mut Step,
     ) -> Result<Processed<Self, Step>, Step::Error> {
         let Self { annotations, reg } = self;
-        Ok(ResetTarget::from(reg)
+        Ok(reg
+            .to_expr()
             .run_process_step(instantiated_module, state, step)?
-            .map(|target| {
-                let ResetTarget::Base { base } = target else {
-                    unreachable!();
-                };
-                let TargetBase::Reg(reg) = *base else {
-                    unreachable!();
-                };
-                Self { annotations, reg }
+            .map(|expr| match *Expr::expr_enum(expr) {
+                ExprEnum::Reg(reg) => Self { annotations, reg },
+                _ => unreachable!(),
             }))
     }
 }
@@ -511,6 +565,7 @@ where
 impl<Step: ProcessStep> RunProcessStep<Step> for StmtInstance
 where
     ResetTarget: RunProcessStep<Step>,
+    ConnectAndLhsInstantiatedModule: RunProcessStep<Step>,
 {
     fn run_process_step(
         self,
@@ -563,19 +618,14 @@ where
             }
             .run_process_step(rhs_instantiated_module, state, step)?;
         }
-        Ok(ResetTarget::from(instance)
+        Ok(Expr::canonical(instance.to_expr())
             .run_process_step(instantiated_module, state, step)?
-            .map(|target| {
-                let ResetTarget::Base { base } = target else {
-                    unreachable!();
-                };
-                let TargetBase::Instance(instance) = *base else {
-                    unreachable!();
-                };
-                Self {
+            .map(|expr| match *Expr::expr_enum(expr) {
+                ExprEnum::Instance(instance) => Self {
                     annotations,
                     instance,
-                }
+                },
+                _ => unreachable!(),
             }))
     }
 }
@@ -583,6 +633,7 @@ where
 impl<Step: ProcessStep> RunProcessStep<Step> for StmtDeclaration
 where
     ResetTarget: RunProcessStep<Step>,
+    ConnectAndLhsInstantiatedModule: RunProcessStep<Step>,
 {
     fn run_process_step(
         self,
@@ -607,6 +658,7 @@ where
 impl<Step: ProcessStep> RunProcessStep<Step> for Stmt
 where
     ResetTarget: RunProcessStep<Step>,
+    ConnectAndLhsInstantiatedModule: RunProcessStep<Step>,
 {
     fn run_process_step(
         self,
@@ -637,6 +689,7 @@ where
 impl<Step: ProcessStep> RunProcessStep<Step> for Block
 where
     ResetTarget: RunProcessStep<Step>,
+    ConnectAndLhsInstantiatedModule: RunProcessStep<Step>,
 {
     fn run_process_step(
         self,
@@ -649,7 +702,11 @@ where
         // so always just use the old `memories` value. we add the ports to the graph anyway to make the other logic easier.
         for memory in memories {
             for port in memory.ports() {
-                ResetTarget::from(port).run_process_step(instantiated_module, state, step)?;
+                Expr::canonical(port.to_expr()).run_process_step(
+                    instantiated_module,
+                    state,
+                    step,
+                )?;
             }
         }
         let stmts = Result::<Processed<_, _>, _>::from_iter(
@@ -664,6 +721,7 @@ where
 impl<Step: ProcessStep> RunProcessStep<Step> for Module<Bundle>
 where
     ResetTarget: RunProcessStep<Step>,
+    ConnectAndLhsInstantiatedModule: RunProcessStep<Step>,
 {
     fn run_process_step(
         self,
@@ -722,7 +780,12 @@ pub fn deduce_resets(
         &mut state,
         &mut AddNodesToGraphStep,
     );
-    todo!("add edges");
+    let mut step = AddEdgesToGraphStep {
+        union_find: UnionFind::new(state.graph.node_count()),
+    };
+    let Ok(Processed(())) =
+        module.run_process_step(InstantiatedModule::Base(module), &mut state, &mut step);
+    let AddEdgesToGraphStep { union_find } = step;
     todo!("deduce types");
     Ok(todo!("transform module"))
 }

From 52ab134673b17d26028b7d92e9cd0ff5c91db0b4 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 24 Nov 2024 14:41:39 -0800
Subject: [PATCH 096/190] increase rust version to support omitting match arms
 with uninhabited types

---
 Cargo.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Cargo.toml b/Cargo.toml
index a9cc312..b5325ad 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -11,7 +11,7 @@ edition = "2021"
 repository = "https://git.libre-chip.org/libre-chip/fayalite"
 keywords = ["hdl", "hardware", "semiconductors", "firrtl", "fpga"]
 categories = ["simulation", "development-tools", "compilers"]
-rust-version = "1.80.1"
+rust-version = "1.82.0"
 
 [workspace.dependencies]
 fayalite-proc-macros = { version = "=0.2.1", path = "crates/fayalite-proc-macros" }

From 9516fe03a1ca7cb44724e0d50e621aa91807a276 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 24 Nov 2024 14:46:25 -0800
Subject: [PATCH 097/190] increase rust version in CI too

---
 .forgejo/workflows/test.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index 969d691..fd7be6f 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -38,7 +38,7 @@ jobs:
             z3 \
             zlib1g-dev
       - run: |
-          curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.80.1
+          curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.82.0
           source "$HOME/.cargo/env"
           echo "$PATH" >> "$GITHUB_PATH"
       - uses: https://code.forgejo.org/actions/cache/restore@v3

From fa50930ff81137dcc0c34929e1e915c647cca211 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 25 Nov 2024 00:00:26 -0800
Subject: [PATCH 098/190] update petgraph dependency to include
 `UnionFind::new_set()`

---
 Cargo.lock | 11 +++++------
 Cargo.toml |  5 +++--
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index c768882..1c54aeb 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -361,9 +361,9 @@ dependencies = [
 
 [[package]]
 name = "fixedbitset"
-version = "0.4.2"
+version = "0.5.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0ce7134b9999ecaf8bcd65542e436736ef32ddca1b3e06094cb6ec5755203b80"
+checksum = "1d674e81391d1e1ab681a28d99df07927c6d4aa5b027d7da16ba32d1d21ecd99"
 
 [[package]]
 name = "funty"
@@ -431,9 +431,9 @@ checksum = "ce23b50ad8242c51a442f3ff322d56b02f08852c77e4c0b4d3fd684abc89c683"
 
 [[package]]
 name = "indexmap"
-version = "2.2.6"
+version = "2.5.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "168fb715dda47215e360912c096649d23d58bf392ac62f73919e831745e40f26"
+checksum = "68b900aa2f7301e21c36462b170ee99994de34dff39a4a6a528e80e7376d07e5"
 dependencies = [
  "equivalent",
  "hashbrown",
@@ -525,8 +525,7 @@ dependencies = [
 [[package]]
 name = "petgraph"
 version = "0.6.5"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b4c5cc86750666a3ed20bdaf5ca2a0344f9c67674cae0515bec2da16fbaa47db"
+source = "git+https://github.com/programmerjake/petgraph.git?rev=258ea8071209a924b73fe96f9f87a3b7b45cbc9f#258ea8071209a924b73fe96f9f87a3b7b45cbc9f"
 dependencies = [
  "fixedbitset",
  "indexmap",
diff --git a/Cargo.toml b/Cargo.toml
index b5325ad..50a4fb8 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -24,12 +24,13 @@ clap = { version = "4.5.9", features = ["derive", "env", "string"] }
 ctor = "0.2.8"
 eyre = "0.6.12"
 hashbrown = "0.14.3"
-indexmap = { version = "2.2.6", features = ["serde"] }
+indexmap = { version = "2.5.0", features = ["serde"] }
 jobslot = "0.2.19"
 num-bigint = "0.4.6"
 num-traits = "0.2.16"
 os_pipe = "1.2.1"
-petgraph = "0.6.5"
+# TODO: switch back to crates.io once petgraph accepts PR #684 and releases a new version
+petgraph = { git = "https://github.com/programmerjake/petgraph.git", rev = "258ea8071209a924b73fe96f9f87a3b7b45cbc9f" }
 prettyplease = "0.2.20"
 proc-macro2 = "1.0.83"
 quote = "1.0.36"

From 3e3da53bd2655b30de83592181a55a9a3022c8ca Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 25 Nov 2024 00:01:02 -0800
Subject: [PATCH 099/190] working on deduce_resets

---
 .../src/module/transform/deduce_resets.rs     | 59 ++++++++++++++++---
 1 file changed, 52 insertions(+), 7 deletions(-)

diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs
index ecc2c43..4308efa 100644
--- a/crates/fayalite/src/module/transform/deduce_resets.rs
+++ b/crates/fayalite/src/module/transform/deduce_resets.rs
@@ -20,7 +20,7 @@ use crate::{
     },
     prelude::*,
 };
-use std::{convert::Infallible, fmt};
+use std::{convert::Infallible, fmt, mem};
 
 #[derive(Debug)]
 pub enum DeduceResetsError {
@@ -415,17 +415,62 @@ impl RunProcessStep<AddEdgesToGraphStep> for ConnectAndLhsInstantiatedModule {
             source_location,
         } = self;
         match Expr::ty(lhs) {
-            CanonicalType::UInt(ty) => todo!(),
-            CanonicalType::SInt(ty) => todo!(),
-            CanonicalType::Bool(ty) => todo!(),
+            CanonicalType::UInt(_) => {}
+            CanonicalType::SInt(_) => {}
+            CanonicalType::Bool(_) => {}
             CanonicalType::AsyncReset(ty) => todo!(),
             CanonicalType::SyncReset(ty) => todo!(),
             CanonicalType::Reset(ty) => todo!(),
-            CanonicalType::Clock(ty) => todo!(),
+            CanonicalType::Clock(_) => {}
             CanonicalType::Array(ty) => todo!(),
-            CanonicalType::Enum(ty) => todo!(),
-            CanonicalType::Bundle(ty) => todo!(),
+            CanonicalType::Enum(ty) => {
+                for (variant_index, EnumVariant { ty, .. }) in ty.variants().into_iter().enumerate()
+                {
+                    if ty.is_none() {
+                        continue;
+                    }
+                    let lhs =
+                        ops::VariantAccess::new_by_index(Expr::from_canonical(lhs), variant_index)
+                            .to_expr();
+                    let rhs =
+                        ops::VariantAccess::new_by_index(Expr::from_canonical(rhs), variant_index)
+                            .to_expr();
+                    ConnectAndLhsInstantiatedModule {
+                        lhs_instantiated_module,
+                        lhs,
+                        rhs,
+                        source_location,
+                    }
+                    .run_process_step(rhs_instantiated_module, state, step)?;
+                }
+            }
+            CanonicalType::Bundle(ty) => {
+                for (field_index, BundleField { flipped, .. }) in
+                    ty.fields().into_iter().enumerate()
+                {
+                    let mut lhs =
+                        ops::FieldAccess::new_by_index(Expr::from_canonical(lhs), field_index)
+                            .to_expr();
+                    let mut rhs =
+                        ops::FieldAccess::new_by_index(Expr::from_canonical(rhs), field_index)
+                            .to_expr();
+                    let mut lhs_instantiated_module = lhs_instantiated_module;
+                    let mut rhs_instantiated_module = rhs_instantiated_module;
+                    if flipped {
+                        mem::swap(&mut lhs, &mut rhs);
+                        mem::swap(&mut lhs_instantiated_module, &mut rhs_instantiated_module);
+                    }
+                    ConnectAndLhsInstantiatedModule {
+                        lhs_instantiated_module,
+                        lhs,
+                        rhs,
+                        source_location,
+                    }
+                    .run_process_step(rhs_instantiated_module, state, step)?;
+                }
+            }
         }
+        Ok(Processed(()))
     }
 }
 

From 7851bf545cb33fd26b05fc72a2ebd009677d992e Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 26 Nov 2024 00:07:11 -0800
Subject: [PATCH 100/190] working on deduce_resets.rs

---
 .../src/module/transform/deduce_resets.rs     | 1413 +++++++++--------
 1 file changed, 707 insertions(+), 706 deletions(-)

diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs
index 4308efa..e6b5987 100644
--- a/crates/fayalite/src/module/transform/deduce_resets.rs
+++ b/crates/fayalite/src/module/transform/deduce_resets.rs
@@ -1,37 +1,62 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 
+#![cfg(todo)]
+
 use hashbrown::{hash_map::Entry, HashMap};
+use num_bigint::BigInt;
 use petgraph::{
     graph::{NodeIndex, UnGraph},
     unionfind::UnionFind,
 };
 
 use crate::{
+    annotations::{Annotation, TargetedAnnotation},
     bundle::{BundleField, BundleType},
     enum_::{EnumType, EnumVariant},
-    expr::{ops, ExprEnum, Flow},
+    expr::{
+        ops,
+        target::{
+            Target, TargetBase, TargetChild, TargetPathArrayElement, TargetPathBundleField,
+            TargetPathDynArrayElement, TargetPathElement,
+        },
+        ExprEnum, Flow,
+    },
     intern::{Intern, Interned, Memoize},
+    memory::{DynPortType, MemPort},
     module::{
-        transform::visit::{Visit, Visitor},
-        AnnotatedModuleIO, Block, ExternModuleBody, InstantiatedModule, ModuleBody, ModuleIO,
-        NormalModuleBody, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance,
-        StmtMatch, StmtReg, StmtWire, TargetInInstantiatedModule,
+        transform::visit::{Folder, Visit, Visitor},
+        AnnotatedModuleIO, Block, ExprInInstantiatedModule, ExternModuleBody,
+        ExternModuleParameter, ExternModuleParameterValue, InstantiatedModule, ModuleBody,
+        ModuleIO, NameId, NormalModuleBody, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtIf,
+        StmtInstance, StmtMatch, StmtReg, StmtWire,
     },
     prelude::*,
+    source_location,
+};
+use std::{
+    borrow::Borrow,
+    convert::Infallible,
+    fmt,
+    hash::{Hash, Hasher},
+    marker::PhantomData,
+    mem,
 };
-use std::{convert::Infallible, fmt, mem};
 
 #[derive(Debug)]
 pub enum DeduceResetsError {
-    ResetIsNotDrivenByAsyncOrSync { target: TargetInInstantiatedModule },
+    ResetIsNotDrivenByAsyncOrSync { source_location: SourceLocation },
+    ResetIsDrivenByBothAsyncAndSync { source_location: SourceLocation },
 }
 
 impl fmt::Display for DeduceResetsError {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         match self {
-            DeduceResetsError::ResetIsNotDrivenByAsyncOrSync { target } => {
-                write!(f, "deduce_reset failed: Reset signal is not driven by any AsyncReset or SyncReset signals: {target:?}")
+            DeduceResetsError::ResetIsNotDrivenByAsyncOrSync { source_location } => {
+                write!(f, "deduce_reset failed: Reset signal is not driven by any AsyncReset or SyncReset signals: {source_location}")
+            }
+            DeduceResetsError::ResetIsDrivenByBothAsyncAndSync { source_location } => {
+                write!(f, "deduce_reset failed: Reset signal is driven by both AsyncReset and SyncReset signals: {source_location}")
             }
         }
     }
@@ -46,767 +71,736 @@ impl From<DeduceResetsError> for std::io::Error {
 }
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
-enum ResetTarget {
-    Base {
-        base: Expr<CanonicalType>,
+enum ResetsLayout {
+    NoResets,
+    Reset,
+    SyncReset,
+    AsyncReset,
+    Bundle {
+        fields: Interned<[ResetsLayout]>,
+        reset_count: usize,
     },
-    BundleField {
-        parent: Interned<ResetTarget>,
-        field_ty: CanonicalType,
-        field_index: usize,
+    Enum {
+        variants: Interned<[ResetsLayout]>,
+        reset_count: usize,
     },
-    EnumVariant {
-        parent: Interned<ResetTarget>,
-        variant_ty: CanonicalType,
-        variant_index: usize,
-    },
-    /// Array's Elements:
-    /// deduce_resets requires all array elements to deduce to the same pattern of async/sync resets,
-    /// so we don't track individual array elements but instead track all of an array's elements together.
-    ArraysElements {
-        parent: Interned<ResetTarget>,
-        element_ty: CanonicalType,
+    Array {
+        element: Interned<ResetsLayout>,
+        reset_count: usize,
     },
 }
 
-impl ResetTarget {
-    fn canonical_ty(self) -> CanonicalType {
+impl ResetsLayout {
+    fn reset_count(self) -> usize {
         match self {
-            ResetTarget::Base { base } => Expr::ty(base),
-            ResetTarget::BundleField { field_ty, .. } => field_ty,
-            ResetTarget::EnumVariant { variant_ty, .. } => variant_ty,
-            ResetTarget::ArraysElements { element_ty, .. } => element_ty,
+            ResetsLayout::NoResets => 0,
+            ResetsLayout::Reset | ResetsLayout::SyncReset | ResetsLayout::AsyncReset => 1,
+            ResetsLayout::Bundle { reset_count, .. }
+            | ResetsLayout::Enum { reset_count, .. }
+            | ResetsLayout::Array { reset_count, .. } => reset_count,
         }
     }
-    fn parent(self) -> Option<Interned<ResetTarget>> {
+    fn new(ty: CanonicalType) -> Self {
+        #[derive(Clone, Copy, PartialEq, Eq, Hash)]
+        struct MyMemoize;
+        impl Memoize for MyMemoize {
+            type Input = CanonicalType;
+            type InputOwned = CanonicalType;
+            type Output = ResetsLayout;
+
+            fn inner(self, ty: &Self::Input) -> Self::Output {
+                match *ty {
+                    CanonicalType::UInt(_) => ResetsLayout::NoResets,
+                    CanonicalType::SInt(_) => ResetsLayout::NoResets,
+                    CanonicalType::Bool(_) => ResetsLayout::NoResets,
+                    CanonicalType::Array(ty) => {
+                        let element = ResetsLayout::new(ty.element()).intern_sized();
+                        ResetsLayout::Array {
+                            element,
+                            reset_count: element.reset_count(),
+                        }
+                    }
+                    CanonicalType::Enum(ty) => {
+                        let mut reset_count = 0;
+                        let variants = Interned::from_iter(ty.variants().iter().map(|variant| {
+                            let resets_layout =
+                                variant.ty.map_or(ResetsLayout::NoResets, ResetsLayout::new);
+                            reset_count += resets_layout.reset_count();
+                            resets_layout
+                        }));
+                        ResetsLayout::Enum {
+                            variants,
+                            reset_count,
+                        }
+                    }
+                    CanonicalType::Bundle(ty) => {
+                        let mut reset_count = 0;
+                        let fields = Interned::from_iter(ty.fields().iter().map(|field| {
+                            let resets_layout = ResetsLayout::new(field.ty);
+                            reset_count += resets_layout.reset_count();
+                            resets_layout
+                        }));
+                        ResetsLayout::Bundle {
+                            fields,
+                            reset_count,
+                        }
+                    }
+                    CanonicalType::AsyncReset(_) => ResetsLayout::AsyncReset,
+                    CanonicalType::SyncReset(_) => ResetsLayout::SyncReset,
+                    CanonicalType::Reset(_) => ResetsLayout::Reset,
+                    CanonicalType::Clock(_) => ResetsLayout::NoResets,
+                }
+            }
+        }
+        MyMemoize.get_owned(ty)
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+struct ResetNodeIndex(usize);
+
+#[derive(Copy, Clone, Debug)]
+struct ResetNode {
+    is_async: Option<bool>,
+    source_location: Option<SourceLocation>,
+}
+
+impl ResetNode {
+    fn union(
+        self,
+        other: Self,
+        fallback_error_source_location: SourceLocation,
+    ) -> Result<Self, DeduceResetsError> {
+        match (self.is_async, other.is_async) {
+            (None, None) => Ok(Self {
+                is_async: None,
+                source_location: self.source_location.or(other.source_location),
+            }),
+            (None, is_async @ Some(_)) => Ok(Self {
+                is_async,
+                // prioritize `other`
+                source_location: other.source_location.or(self.source_location),
+            }),
+            (is_async @ Some(_), None) => Ok(Self {
+                is_async,
+                // prioritize `self`
+                source_location: self.source_location.or(other.source_location),
+            }),
+            (Some(self_is_async), Some(other_is_async)) => {
+                if self_is_async == other_is_async {
+                    Ok(Self {
+                        is_async: Some(self_is_async),
+                        source_location: self.source_location.or(other.source_location),
+                    })
+                } else {
+                    Err(DeduceResetsError::ResetIsDrivenByBothAsyncAndSync {
+                        source_location: self
+                            .source_location
+                            .or(other.source_location)
+                            .unwrap_or(fallback_error_source_location),
+                    })
+                }
+            }
+        }
+    }
+}
+
+#[derive(Debug, Default)]
+struct ResetGraph {
+    union_find: UnionFind<usize>,
+    nodes: Vec<ResetNode>,
+}
+
+impl ResetGraph {
+    fn new_node(
+        &mut self,
+        is_async: Option<bool>,
+        source_location: Option<SourceLocation>,
+    ) -> ResetNodeIndex {
+        let index = self.union_find.new_set();
+        assert_eq!(index, self.nodes.len());
+        self.nodes.push(ResetNode {
+            is_async,
+            source_location,
+        });
+        ResetNodeIndex(index)
+    }
+    fn union(
+        &mut self,
+        a: ResetNodeIndex,
+        b: ResetNodeIndex,
+        fallback_error_source_location: SourceLocation,
+    ) -> Result<(), DeduceResetsError> {
+        let a = self.union_find.find_mut(a.0);
+        let b = self.union_find.find_mut(b.0);
+        if a != b {
+            self.union_find.union(a, b);
+            let merged = self.union_find.find_mut(a);
+            self.nodes[merged] =
+                self.nodes[a].union(self.nodes[b], fallback_error_source_location)?;
+        }
+        Ok(())
+    }
+    fn is_async(
+        &mut self,
+        node: ResetNodeIndex,
+        fallback_to_sync_reset: bool,
+        fallback_error_source_location: SourceLocation,
+    ) -> Result<bool, DeduceResetsError> {
+        let ResetNode {
+            is_async,
+            source_location,
+        } = self.nodes[self.union_find.find_mut(node.0)];
+        if let Some(is_async) = is_async {
+            Ok(is_async)
+        } else if fallback_to_sync_reset {
+            Ok(false)
+        } else {
+            Err(DeduceResetsError::ResetIsNotDrivenByAsyncOrSync {
+                source_location: source_location.unwrap_or(fallback_error_source_location),
+            })
+        }
+    }
+}
+
+#[derive(Debug)]
+enum MaybeInterned<'a, T: ?Sized + Intern> {
+    Interned(Interned<T>),
+    Borrowed(&'a T),
+}
+
+impl<'a, T: ?Sized + Intern> Borrow<T> for MaybeInterned<'a, T> {
+    fn borrow(&self) -> &T {
+        &**self
+    }
+}
+
+impl<'a, T: ?Sized + Intern + PartialEq> PartialEq for MaybeInterned<'a, T> {
+    fn eq(&self, other: &Self) -> bool {
+        **self == **other
+    }
+}
+
+impl<'a, T: ?Sized + Intern + Eq> Eq for MaybeInterned<'a, T> {}
+
+impl<'a, T: ?Sized + Intern + Hash> Hash for MaybeInterned<'a, T> {
+    fn hash<H: Hasher>(&self, state: &mut H) {
+        (**self).hash(state);
+    }
+}
+
+impl<'a, T: ?Sized + Intern> Copy for MaybeInterned<'a, T> {}
+
+impl<'a, T: ?Sized + Intern> Clone for MaybeInterned<'a, T> {
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+impl<'a, T: ?Sized + Intern> std::ops::Deref for MaybeInterned<'a, T> {
+    type Target = T;
+
+    fn deref(&self) -> &Self::Target {
         match self {
-            ResetTarget::Base { .. } => None,
-            ResetTarget::BundleField { parent, .. }
-            | ResetTarget::EnumVariant { parent, .. }
-            | ResetTarget::ArraysElements { parent, .. } => Some(parent),
+            MaybeInterned::Interned(v) => v,
+            MaybeInterned::Borrowed(v) => v,
         }
     }
-    fn base(mut self) -> Expr<CanonicalType> {
-        loop {
-            match self {
-                ResetTarget::Base { base } => break base,
-                ResetTarget::BundleField { parent, .. }
-                | ResetTarget::EnumVariant { parent, .. }
-                | ResetTarget::ArraysElements { parent, .. } => self = *parent,
-            }
-        }
-    }
-    fn bundle_field(self, field_index: usize) -> Self {
-        let field_ty = Bundle::from_canonical(self.canonical_ty()).fields()[field_index].ty;
-        Self::BundleField {
-            parent: self.intern_sized(),
-            field_ty,
-            field_index,
-        }
-    }
-    fn enum_variant(self, variant_index: usize) -> Self {
-        let variant_ty = Enum::from_canonical(self.canonical_ty()).variants()[variant_index]
-            .ty
-            .expect("known to have a variant field");
-        Self::EnumVariant {
-            parent: self.intern_sized(),
-            variant_ty,
-            variant_index,
-        }
-    }
-    fn arrays_elements(self) -> Self {
-        let element_ty = <Array>::from_canonical(self.canonical_ty()).element();
-        Self::ArraysElements {
-            parent: self.intern_sized(),
-            element_ty,
-        }
-    }
-    fn for_each_child<E>(self, mut f: impl FnMut(ResetTarget) -> Result<(), E>) -> Result<(), E> {
-        match self.canonical_ty() {
-            CanonicalType::UInt(_)
-            | CanonicalType::SInt(_)
-            | CanonicalType::Bool(_)
-            | CanonicalType::AsyncReset(_)
-            | CanonicalType::SyncReset(_)
-            | CanonicalType::Reset(_)
-            | CanonicalType::Clock(_) => Ok(()),
-            CanonicalType::Array(_) => f(self.arrays_elements()),
-            CanonicalType::Enum(ty) => {
-                for variant_index in 0..ty.variants().len() {
-                    f(self.enum_variant(variant_index))?;
-                }
-                Ok(())
-            }
-            CanonicalType::Bundle(ty) => {
-                for field_index in 0..ty.fields().len() {
-                    f(self.bundle_field(field_index))?;
-                }
-                Ok(())
-            }
+}
+
+impl<'a, T: ?Sized + Intern> MaybeInterned<'a, T> {
+    fn to_interned(self) -> Interned<T> {
+        match self {
+            MaybeInterned::Interned(v) => v,
+            MaybeInterned::Borrowed(v) => v.intern(),
         }
     }
 }
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
-struct ResetTargetInInstantiatedModule {
-    instantiated_module: InstantiatedModule,
-    target: ResetTarget,
+struct Resets<'a> {
+    ty: CanonicalType,
+    layout: ResetsLayout,
+    node_indexes: MaybeInterned<'a, [ResetNodeIndex]>,
 }
 
-#[derive(Debug)]
-struct Node {
-    target: ResetTargetInInstantiatedModule,
-    deduced_type: Option<CanonicalType>,
+impl<'a> Resets<'a> {
+    fn into_interned(self) -> Resets<'static> {
+        let Self {
+            ty,
+            layout,
+            node_indexes,
+        } = self;
+        Resets {
+            ty,
+            layout,
+            node_indexes: MaybeInterned::Interned(node_indexes.to_interned()),
+        }
+    }
 }
 
 #[derive(Debug)]
 struct State {
     base_module: Interned<Module<Bundle>>,
-    node_ids: HashMap<ResetTargetInInstantiatedModule, NodeIndex<u32>>,
-    graph: UnGraph<Node, ()>,
+    expr_resets: HashMap<ExprInInstantiatedModule<CanonicalType>, Resets<'static>>,
+    reset_graph: ResetGraph,
     fallback_to_sync_reset: bool,
 }
 
-fn type_contains_any_undeduced_resets(ty: CanonicalType) -> bool {
-    #[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)]
-    struct MyMemoize;
-    impl Memoize for MyMemoize {
-        type Input = CanonicalType;
-        type InputOwned = CanonicalType;
-        type Output = bool;
+struct PassOutput<T, P: Pass>(P::Output<T>);
 
-        fn inner(self, input: &Self::Input) -> Self::Output {
-            match input {
-                CanonicalType::UInt(_) => false,
-                CanonicalType::SInt(_) => false,
-                CanonicalType::Bool(_) => false,
-                CanonicalType::Array(ty) => type_contains_any_undeduced_resets(ty.element()),
-                CanonicalType::Enum(ty) => {
-                    ty.variants().iter().any(|EnumVariant { ty, .. }| {
-                        ty.is_some_and(|ty| type_contains_any_undeduced_resets(ty))
-                    })
-                }
-                CanonicalType::Bundle(ty) => ty
-                    .fields()
-                    .iter()
-                    .any(|&BundleField { ty, .. }| type_contains_any_undeduced_resets(ty)),
-                CanonicalType::AsyncReset(_) => false,
-                CanonicalType::SyncReset(_) => false,
-                CanonicalType::Reset(_) => true,
-                CanonicalType::Clock(_) => false,
+impl<T, P: Pass> PassOutput<T, P> {
+    fn new(v: T) -> Self {
+        P::output_new(v)
+    }
+    fn from_fn(f: impl FnOnce() -> T) -> Self {
+        PassOutput::new(()).map(|()| f())
+    }
+    fn as_ref(&self) -> PassOutput<&T, P> {
+        P::output_as_ref(self)
+    }
+    fn as_mut(&mut self) -> PassOutput<&mut T, P> {
+        P::output_as_mut(self)
+    }
+    fn map<U>(self, f: impl FnOnce(T) -> U) -> PassOutput<U, P> {
+        P::map(self, f)
+    }
+}
+
+trait PassOutputZip<P: Pass>: Sized {
+    type Zipped;
+    fn zip(self) -> PassOutput<Self::Zipped, P>;
+    fn call<U>(self, f: impl FnOnce(Self::Zipped) -> U) -> PassOutput<U, P> {
+        self.zip().map(f)
+    }
+}
+
+impl<P: Pass> PassOutputZip<P> for () {
+    type Zipped = ();
+    fn zip(self) -> PassOutput<Self::Zipped, P> {
+        PassOutput::new(())
+    }
+}
+
+impl<T, P: Pass> PassOutputZip<P> for (PassOutput<T, P>,) {
+    type Zipped = (T,);
+    fn zip(self) -> PassOutput<Self::Zipped, P> {
+        self.0.map(|v| (v,))
+    }
+}
+
+macro_rules! impl_zip {
+    ($first_arg:ident: $first_T:ident, $($arg:ident: $T:ident),* $(,)?) => {
+        impl_zip!(@step [], [($first_arg: $first_T) $(($arg: $T))*], (),);
+    };
+    (
+        @impl($first_arg:tt,),
+        $tuple_pat:tt,
+    ) => {};
+    (
+        @impl(($first_arg:ident: $first_T:ident),
+            $(($arg:ident: $T:ident),)*),
+        $tuple_pat:tt,
+    ) => {
+        impl<$first_T, $($T,)* P: Pass> PassOutputZip<P> for (PassOutput<$first_T, P>, $(PassOutput<$T, P>),*) {
+            type Zipped = ($first_T, $($T),*);
+            fn zip(self) -> PassOutput<($first_T, $($T),*), P> {
+                let (tuples, $($arg),*) = self;
+                $(let tuples = P::zip(tuples, $arg);)*
+                tuples.map(|$tuple_pat| ($first_arg, $($arg),*))
             }
         }
+    };
+    (
+        @step [$($cur:tt)*],
+        [],
+        $tuple_pat:tt,
+    ) => {};
+    (
+        @step [$($cur:tt)*],
+        [($next_arg:ident: $next_T:ident) $($rest:tt)*],
+        (),
+    ) => {
+        impl_zip!(@impl($($cur,)* ($next_arg: $next_T),), $next_arg,);
+        impl_zip!(@step [$($cur)* ($next_arg: $next_T)], [$($rest)*], $next_arg,);
+    };
+    (
+        @step [$($cur:tt)*],
+        [($next_arg:ident: $next_T:ident) $($rest:tt)*],
+        $tuple_pat:tt,
+    ) => {
+        impl_zip!(@impl($($cur,)* ($next_arg: $next_T),), ($tuple_pat, $next_arg),);
+        impl_zip!(@step [$($cur)* ($next_arg: $next_T)], [$($rest)*], ($tuple_pat, $next_arg),);
+    };
+}
+
+impl_zip!(t0: T0, t1: T1, t2: T2, t3: T3, t4: T4, t5: T5, t6: T6, t7: T7, t8: T8, t9: T9, t10: T10, t11: T11);
+
+impl<T: FromIterator<A>, P: Pass, A> FromIterator<PassOutput<A, P>> for PassOutput<T, P> {
+    fn from_iter<I: IntoIterator<Item = PassOutput<A, P>>>(iter: I) -> Self {
+        P::output_from_iter(iter)
     }
-    MyMemoize.get_owned(ty)
 }
 
-trait ProcessStep {
-    type Error;
-    type Processed<T>;
-    fn processed_as_ref<T>(v: &Self::Processed<T>) -> Self::Processed<&T>;
-    fn processed_as_mut<T>(v: &mut Self::Processed<T>) -> Self::Processed<&mut T>;
-    fn processed_zip<T, U>(t: Self::Processed<T>, u: Self::Processed<U>)
-        -> Self::Processed<(T, U)>;
-    fn processed_map<T, U>(v: Self::Processed<T>, f: impl FnOnce(T) -> U) -> Self::Processed<U>;
-    fn processed_make<T>(t: T) -> Self::Processed<T>;
-    fn processed_from_iter<T, O: FromIterator<T>>(
-        iter: impl IntoIterator<Item = Self::Processed<T>>,
-    ) -> Self::Processed<O>;
+trait Pass: Sized {
+    type Output<T>;
+    fn output_new<T>(v: T) -> PassOutput<T, Self>;
+    fn output_as_ref<T>(v: &PassOutput<T, Self>) -> PassOutput<&T, Self>;
+    fn output_as_mut<T>(v: &mut PassOutput<T, Self>) -> PassOutput<&mut T, Self>;
+    fn output_from_iter<T: FromIterator<A>, A>(
+        iter: impl IntoIterator<Item = PassOutput<A, Self>>,
+    ) -> PassOutput<T, Self>;
+    fn map<T, U>(v: PassOutput<T, Self>, f: impl FnOnce(T) -> U) -> PassOutput<U, Self>;
+    fn zip<T, U>(t: PassOutput<T, Self>, u: PassOutput<U, Self>) -> PassOutput<(T, U), Self>;
 }
 
-macro_rules! impl_process_step_with_empty_processed {
-    () => {
-        type Processed<T> = ();
-        fn processed_as_ref<T>(v: &Self::Processed<T>) -> Self::Processed<&T> {
-            *v
+struct BuildResetGraph;
+
+impl Pass for BuildResetGraph {
+    type Output<T> = ();
+
+    fn output_new<T>(_v: T) -> PassOutput<T, Self> {
+        PassOutput(())
+    }
+
+    fn output_as_ref<T>(_v: &PassOutput<T, Self>) -> PassOutput<&T, Self> {
+        PassOutput(())
+    }
+
+    fn output_as_mut<T>(_v: &mut PassOutput<T, Self>) -> PassOutput<&mut T, Self> {
+        PassOutput(())
+    }
+
+    fn output_from_iter<T: FromIterator<A>, A>(
+        iter: impl IntoIterator<Item = PassOutput<A, Self>>,
+    ) -> PassOutput<T, Self> {
+        iter.into_iter().for_each(|_| {});
+        PassOutput(())
+    }
+
+    fn map<T, U>(_v: PassOutput<T, Self>, _f: impl FnOnce(T) -> U) -> PassOutput<U, Self> {
+        PassOutput(())
+    }
+
+    fn zip<T, U>(_t: PassOutput<T, Self>, _u: PassOutput<U, Self>) -> PassOutput<(T, U), Self> {
+        PassOutput(())
+    }
+}
+
+struct SubstituteResets;
+
+impl Pass for SubstituteResets {
+    type Output<T> = T;
+
+    fn output_new<T>(v: T) -> PassOutput<T, Self> {
+        PassOutput(v)
+    }
+
+    fn output_as_ref<T>(v: &PassOutput<T, Self>) -> PassOutput<&T, Self> {
+        PassOutput(&v.0)
+    }
+
+    fn output_as_mut<T>(v: &mut PassOutput<T, Self>) -> PassOutput<&mut T, Self> {
+        PassOutput(&mut v.0)
+    }
+
+    fn output_from_iter<T: FromIterator<A>, A>(
+        iter: impl IntoIterator<Item = PassOutput<A, Self>>,
+    ) -> PassOutput<T, Self> {
+        PassOutput(T::from_iter(iter.into_iter().map(|PassOutput(v)| v)))
+    }
+
+    fn map<T, U>(v: PassOutput<T, Self>, f: impl FnOnce(T) -> U) -> PassOutput<U, Self> {
+        PassOutput(f(v.0))
+    }
+
+    fn zip<T, U>(t: PassOutput<T, Self>, u: PassOutput<U, Self>) -> PassOutput<(T, U), Self> {
+        PassOutput((t.0, u.0))
+    }
+}
+
+struct PassArgs<'a, P: Pass> {
+    state: &'a mut State,
+    instantiated_module: InstantiatedModule,
+    fallback_error_source_location: SourceLocation,
+    _phantom: PhantomData<P>,
+}
+
+impl<'a, P: Pass> fmt::Debug for PassArgs<'a, P> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            state,
+            instantiated_module,
+            fallback_error_source_location,
+            _phantom: _,
+        } = self;
+        f.debug_struct("PassArgs")
+            .field("state", state)
+            .field("instantiated_module", instantiated_module)
+            .field(
+                "fallback_error_source_location",
+                fallback_error_source_location,
+            )
+            .finish()
+    }
+}
+
+impl<'a, P: Pass> PassArgs<'a, P> {
+    fn as_mut(&mut self) -> PassArgs<'_, P> {
+        let PassArgs {
+            ref mut state,
+            instantiated_module,
+            fallback_error_source_location,
+            _phantom: _,
+        } = *self;
+        PassArgs {
+            state: &mut **state,
+            instantiated_module,
+            fallback_error_source_location,
+            _phantom: PhantomData,
         }
-        fn processed_as_mut<T>(v: &mut Self::Processed<T>) -> Self::Processed<&mut T> {
-            *v
-        }
-        fn processed_zip<T, U>(
-            t: Self::Processed<T>,
-            u: Self::Processed<U>,
-        ) -> Self::Processed<(T, U)> {
-            let _ = t;
-            let _ = u;
-            ()
-        }
-        fn processed_map<T, U>(
-            v: Self::Processed<T>,
-            f: impl FnOnce(T) -> U,
-        ) -> Self::Processed<U> {
-            let _ = f;
-            v
-        }
-        fn processed_make<T>(t: T) -> Self::Processed<T> {
-            let _ = t;
-            ()
-        }
-        fn processed_from_iter<T, O: FromIterator<T>>(
-            iter: impl IntoIterator<Item = Self::Processed<T>>,
-        ) -> Self::Processed<O> {
-            FromIterator::from_iter(iter)
+    }
+}
+
+trait RunPass<P: Pass>: Sized {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError>;
+}
+
+impl<T: RunPass<P> + Intern + Clone, P: Pass> RunPass<P> for Interned<T> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Ok(T::run_pass(self, pass_args)?.map(Intern::intern_sized))
+    }
+}
+
+impl<T: RunPass<P> + Clone, P: Pass> RunPass<P> for Interned<[T]>
+where
+    [T]: Intern,
+{
+    fn run_pass(
+        &self,
+        mut pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Result::from_iter(self.iter().map(|v| v.run_pass(pass_args.as_mut())))
+    }
+}
+
+macro_rules! impl_run_pass_copy {
+    ([$($generics:tt)*] $ty:ty) => {
+        impl<P: Pass, $($generics)*> RunPass<P> for $ty {
+            fn run_pass(
+                &self,
+                _pass_args: PassArgs<'_, P>,
+            ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+                Ok(PassOutput::new(*self))
+            }
         }
     };
 }
 
-struct Processed<T, Step: ProcessStep>(Step::Processed<T>);
-
-impl<T, Step: ProcessStep> Processed<T, Step> {
-    fn as_ref(&self) -> Processed<&T, Step> {
-        Processed(Step::processed_as_ref(&self.0))
-    }
-    fn as_mut(&mut self) -> Processed<&mut T, Step> {
-        Processed(Step::processed_as_mut(&mut self.0))
-    }
-    fn zip<U>(self, u: Processed<U, Step>) -> Processed<(T, U), Step> {
-        Processed(Step::processed_zip(self.0, u.0))
-    }
-    fn new(v: T) -> Self {
-        Processed(Step::processed_make(v))
-    }
-    fn map<U>(self, f: impl FnOnce(T) -> U) -> Processed<U, Step> {
-        Processed(Step::processed_map(self.0, f))
-    }
-}
-
-impl<C: FromIterator<A>, A, Step: ProcessStep> FromIterator<Processed<A, Step>>
-    for Processed<C, Step>
-{
-    fn from_iter<T: IntoIterator<Item = Processed<A, Step>>>(iter: T) -> Self {
-        Processed(Step::processed_from_iter(iter.into_iter().map(|v| v.0)))
-    }
-}
-
-fn for_each_subexpr_exclusive<E>(
-    expr: Expr<CanonicalType>,
-    f: impl FnMut(Expr<CanonicalType>) -> Result<(), E>,
-) -> Result<(), E> {
-    struct MyVisitor<F> {
-        f: F,
-    }
-    impl<F: FnMut(Expr<CanonicalType>) -> Result<(), E>, E> Visitor for MyVisitor<F> {
-        type Error = E;
-        fn visit_expr_enum(&mut self, v: &ExprEnum) -> Result<(), Self::Error> {
-            (self.f)(v.to_expr())?;
-            v.default_visit(self)
-        }
-    }
-    Expr::expr_enum(expr).default_visit(&mut MyVisitor { f })
-}
-
-struct AddNodesToGraphStep;
-
-impl ProcessStep for AddNodesToGraphStep {
-    type Error = Infallible;
-    impl_process_step_with_empty_processed!();
-}
-
-struct AddEdgesToGraphStep {
-    union_find: UnionFind<u32>,
-}
-
-impl ProcessStep for AddEdgesToGraphStep {
-    type Error = Infallible;
-    impl_process_step_with_empty_processed!();
-}
-
-trait RunProcessStep<Step: ProcessStep>: Sized {
-    fn run_process_step(
-        self,
-        instantiated_module: InstantiatedModule,
-        state: &mut State,
-        step: &mut Step,
-    ) -> Result<Processed<Self, Step>, Step::Error>;
-}
-
-impl RunProcessStep<AddNodesToGraphStep> for ResetTarget {
-    fn run_process_step(
-        self,
-        instantiated_module: InstantiatedModule,
-        state: &mut State,
-        step: &mut AddNodesToGraphStep,
-    ) -> Result<Processed<Self, AddNodesToGraphStep>, Infallible> {
-        let target = ResetTargetInInstantiatedModule {
-            instantiated_module,
-            target: self,
-        };
-        let Entry::Vacant(entry) = state.node_ids.entry(target) else {
-            return Ok(Processed(()));
-        };
-        let ty = self.canonical_ty();
-        let node_id = state.graph.add_node(Node {
-            target,
-            deduced_type: type_contains_any_undeduced_resets(ty).then_some(ty),
-        });
-        entry.insert(node_id);
-        self.for_each_child(|target| -> Result<(), Infallible> {
-            target.run_process_step(instantiated_module, state, step)?;
-            Ok(())
-        })?;
-        Ok(Processed(()))
-    }
-}
-
-impl RunProcessStep<AddEdgesToGraphStep> for ResetTarget {
-    fn run_process_step(
-        self,
-        _instantiated_module: InstantiatedModule,
-        _state: &mut State,
-        _step: &mut AddEdgesToGraphStep,
-    ) -> Result<Processed<Self, AddEdgesToGraphStep>, Infallible> {
-        Ok(Processed(()))
-    }
-}
-
-impl<Step: ProcessStep> RunProcessStep<Step> for Expr<CanonicalType>
-where
-    ResetTarget: RunProcessStep<Step>,
-{
-    fn run_process_step(
-        self,
-        instantiated_module: InstantiatedModule,
-        state: &mut State,
-        step: &mut Step,
-    ) -> Result<Processed<Self, Step>, Step::Error> {
-        let retval = ResetTarget::Base { base: self }
-            .run_process_step(instantiated_module, state, step)?
-            .map(|target| match target {
-                ResetTarget::Base { base } => base,
-                _ => unreachable!(),
-            });
-        for_each_subexpr_exclusive(self, |base| {
-            ResetTarget::Base { base }.run_process_step(instantiated_module, state, step)?;
-            Ok(())
-        })?;
-        Ok(retval)
-    }
-}
-
-struct ConnectAndLhsInstantiatedModule {
-    lhs_instantiated_module: InstantiatedModule,
-    lhs: Expr<CanonicalType>,
-    rhs: Expr<CanonicalType>,
-    source_location: SourceLocation,
-}
-
-impl RunProcessStep<AddNodesToGraphStep> for ConnectAndLhsInstantiatedModule {
-    fn run_process_step(
-        self,
-        _instantiated_module: InstantiatedModule,
-        _state: &mut State,
-        _step: &mut AddNodesToGraphStep,
-    ) -> Result<Processed<Self, AddNodesToGraphStep>, Infallible> {
-        Ok(Processed(()))
-    }
-}
-
-impl RunProcessStep<AddEdgesToGraphStep> for ConnectAndLhsInstantiatedModule {
-    fn run_process_step(
-        self,
-        rhs_instantiated_module: InstantiatedModule,
-        state: &mut State,
-        step: &mut AddEdgesToGraphStep,
-    ) -> Result<Processed<Self, AddEdgesToGraphStep>, Infallible> {
-        let Self {
-            lhs_instantiated_module,
-            lhs,
-            rhs,
-            source_location,
-        } = self;
-        match Expr::ty(lhs) {
-            CanonicalType::UInt(_) => {}
-            CanonicalType::SInt(_) => {}
-            CanonicalType::Bool(_) => {}
-            CanonicalType::AsyncReset(ty) => todo!(),
-            CanonicalType::SyncReset(ty) => todo!(),
-            CanonicalType::Reset(ty) => todo!(),
-            CanonicalType::Clock(_) => {}
-            CanonicalType::Array(ty) => todo!(),
-            CanonicalType::Enum(ty) => {
-                for (variant_index, EnumVariant { ty, .. }) in ty.variants().into_iter().enumerate()
-                {
-                    if ty.is_none() {
-                        continue;
-                    }
-                    let lhs =
-                        ops::VariantAccess::new_by_index(Expr::from_canonical(lhs), variant_index)
-                            .to_expr();
-                    let rhs =
-                        ops::VariantAccess::new_by_index(Expr::from_canonical(rhs), variant_index)
-                            .to_expr();
-                    ConnectAndLhsInstantiatedModule {
-                        lhs_instantiated_module,
-                        lhs,
-                        rhs,
-                        source_location,
-                    }
-                    .run_process_step(rhs_instantiated_module, state, step)?;
-                }
+macro_rules! impl_run_pass_clone {
+    ([$($generics:tt)*] $ty:ty) => {
+        impl<P: Pass, $($generics)*> RunPass<P> for $ty {
+            fn run_pass(
+                &self,
+                _pass_args: PassArgs<'_, P>,
+            ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+                Ok(PassOutput::from_fn(|| self.clone()))
             }
-            CanonicalType::Bundle(ty) => {
-                for (field_index, BundleField { flipped, .. }) in
-                    ty.fields().into_iter().enumerate()
-                {
-                    let mut lhs =
-                        ops::FieldAccess::new_by_index(Expr::from_canonical(lhs), field_index)
-                            .to_expr();
-                    let mut rhs =
-                        ops::FieldAccess::new_by_index(Expr::from_canonical(rhs), field_index)
-                            .to_expr();
-                    let mut lhs_instantiated_module = lhs_instantiated_module;
-                    let mut rhs_instantiated_module = rhs_instantiated_module;
-                    if flipped {
-                        mem::swap(&mut lhs, &mut rhs);
-                        mem::swap(&mut lhs_instantiated_module, &mut rhs_instantiated_module);
-                    }
-                    ConnectAndLhsInstantiatedModule {
-                        lhs_instantiated_module,
-                        lhs,
-                        rhs,
-                        source_location,
-                    }
-                    .run_process_step(rhs_instantiated_module, state, step)?;
+        }
+    };
+}
+
+impl_run_pass_copy!([] Interned<str>);
+impl_run_pass_copy!([] usize);
+impl_run_pass_copy!([] bool);
+impl_run_pass_clone!([] BigInt);
+
+macro_rules! impl_run_pass_for_struct {
+    (
+        $(#[adjust_pass_args = $adjust_pass_args:expr])?
+        #[constructor = $constructor:expr]
+        impl[$($generics:tt)*] $RunPass:ident for $ty:ty {
+            $($field:ident $(($($args:tt)*))?: _,)*
+        }
+    ) => {
+        impl<P: Pass, $($generics)*> $RunPass<P> for $ty {
+            #[allow(unused_mut, unused_variables)]
+            fn run_pass(
+                &self,
+                mut pass_args: PassArgs<'_, P>,
+            ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+                $($adjust_pass_args(self, &mut pass_args);)?
+                Ok(($(self.$field$(($($args)*))?.run_pass(pass_args.as_mut())?,)*).call(|($($field,)*)| $constructor))
+            }
+        }
+    };
+    (
+        $(#[adjust_pass_args = $adjust_pass_args:expr])?
+        impl[$($generics:tt)*] $RunPass:ident for $ty:ty {
+            $($field:ident: _,)*
+        }
+    ) => {
+        impl_run_pass_for_struct! {
+            $(#[adjust_pass_args = $adjust_pass_args])?
+            #[constructor = {
+                type Ty<T> = T;
+                Ty::<$ty> { $($field,)* }
+            }]
+            impl[$($generics)*] $RunPass for $ty {
+                $($field: _,)*
+            }
+        }
+    };
+}
+
+macro_rules! impl_run_pass_for_enum {
+    (impl[$($generics:tt)*] $RunPass:ident for $ty:ty {
+        $($variant:ident($arg:ident),)*
+    }) => {
+        impl<P: Pass, $($generics)*> $RunPass<P> for $ty {
+            fn run_pass(
+                &self,
+                pass_args: PassArgs<'_, P>,
+            ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+                type Ty<T> = T;
+                match self {
+                    $(Ty::<$ty>::$variant($arg) => Ok($arg.run_pass(pass_args)?.map(<$ty>::$variant)),)*
                 }
             }
         }
-        Ok(Processed(()))
+    };
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for Block {
+        memories: _,
+        stmts: _,
     }
 }
 
-impl<Step: ProcessStep> RunProcessStep<Step> for StmtConnect
-where
-    ConnectAndLhsInstantiatedModule: RunProcessStep<Step>,
-{
-    fn run_process_step(
-        self,
-        instantiated_module: InstantiatedModule,
-        state: &mut State,
-        step: &mut Step,
-    ) -> Result<Processed<Self, Step>, Step::Error> {
-        let StmtConnect {
-            lhs,
-            rhs,
-            source_location,
-        } = self;
-        Ok(ConnectAndLhsInstantiatedModule {
-            lhs_instantiated_module: instantiated_module,
-            lhs,
-            rhs,
-            source_location,
-        }
-        .run_process_step(instantiated_module, state, step)?
-        .map(
-            |ConnectAndLhsInstantiatedModule {
-                 lhs_instantiated_module: _,
-                 lhs,
-                 rhs,
-                 source_location,
-             }| StmtConnect {
-                lhs,
-                rhs,
-                source_location,
-            },
-        ))
+impl_run_pass_for_struct! {
+    impl[] RunPass for NormalModuleBody {
+        body: _,
     }
 }
 
-impl<Step: ProcessStep> RunProcessStep<Step> for StmtFormal {
-    fn run_process_step(
-        self,
-        _instantiated_module: InstantiatedModule,
-        _state: &mut State,
-        _step: &mut Step,
-    ) -> Result<Processed<Self, Step>, Step::Error> {
-        // no inputs are Reset
-        Ok(Processed::new(self))
+impl_run_pass_copy!([] ExternModuleBody);
+impl_run_pass_copy!([] NameId);
+impl_run_pass_copy!([] SourceLocation);
+impl_run_pass_copy!([] DontTouchAnnotation);
+impl_run_pass_copy!([] SVAttributeAnnotation);
+impl_run_pass_copy!([] BlackBoxInlineAnnotation);
+impl_run_pass_copy!([] BlackBoxPathAnnotation);
+impl_run_pass_copy!([] DocStringAnnotation);
+impl_run_pass_copy!([] CustomFirrtlAnnotation);
+impl_run_pass_copy!([] MemPort<DynPortType>); // Mem can't contain any `Reset` types
+impl_run_pass_copy!([] Mem); // Mem can't contain any `Reset` types
+
+impl_run_pass_for_enum! {
+    impl[] RunPass for TargetBase {
+        ModuleIO(v),
+        MemPort(v),
+        Reg(v),
+        Wire(v),
+        Instance(v),
     }
 }
 
-impl<Step: ProcessStep> RunProcessStep<Step> for StmtIf {
-    fn run_process_step(
-        self,
-        instantiated_module: InstantiatedModule,
-        state: &mut State,
-        step: &mut Step,
-    ) -> Result<Processed<Self, Step>, Step::Error> {
-        todo!()
+impl_run_pass_for_struct! {
+    impl[] RunPass for TargetPathBundleField {
+        name: _,
     }
 }
 
-impl<Step: ProcessStep> RunProcessStep<Step> for StmtMatch {
-    fn run_process_step(
-        self,
-        instantiated_module: InstantiatedModule,
-        state: &mut State,
-        step: &mut Step,
-    ) -> Result<Processed<Self, Step>, Step::Error> {
-        todo!()
+impl_run_pass_for_struct! {
+    impl[] RunPass for TargetPathArrayElement {
+        index: _,
     }
 }
 
-impl<Step: ProcessStep> RunProcessStep<Step> for ModuleIO<CanonicalType>
-where
-    ResetTarget: RunProcessStep<Step>,
-{
-    fn run_process_step(
-        self,
-        instantiated_module: InstantiatedModule,
-        state: &mut State,
-        step: &mut Step,
-    ) -> Result<Processed<Self, Step>, Step::Error> {
-        Ok(self
-            .to_expr()
-            .run_process_step(instantiated_module, state, step)?
-            .map(|expr| match *Expr::expr_enum(expr) {
-                ExprEnum::ModuleIO(module_io) => module_io,
-                _ => unreachable!(),
-            }))
+impl_run_pass_for_struct! {
+    impl[] RunPass for TargetPathDynArrayElement {}
+}
+
+impl_run_pass_for_enum! {
+    impl[] RunPass for TargetPathElement {
+        BundleField(v),
+        ArrayElement(v),
+        DynArrayElement(v),
     }
 }
 
-impl<Step: ProcessStep> RunProcessStep<Step> for StmtWire
-where
-    ResetTarget: RunProcessStep<Step>,
-{
-    fn run_process_step(
-        self,
-        instantiated_module: InstantiatedModule,
-        state: &mut State,
-        step: &mut Step,
-    ) -> Result<Processed<Self, Step>, Step::Error> {
-        let Self { annotations, wire } = self;
-        Ok(wire
-            .to_expr()
-            .run_process_step(instantiated_module, state, step)?
-            .map(|expr| match *Expr::expr_enum(expr) {
-                ExprEnum::Wire(wire) => Self { annotations, wire },
-                _ => unreachable!(),
-            }))
+impl_run_pass_for_enum! {
+    impl[] RunPass for Target {
+        Base(v),
+        Child(v),
     }
 }
 
-impl<Step: ProcessStep> RunProcessStep<Step> for StmtReg
-where
-    ResetTarget: RunProcessStep<Step>,
-{
-    fn run_process_step(
-        self,
-        instantiated_module: InstantiatedModule,
-        state: &mut State,
-        step: &mut Step,
-    ) -> Result<Processed<Self, Step>, Step::Error> {
-        let Self { annotations, reg } = self;
-        Ok(reg
-            .to_expr()
-            .run_process_step(instantiated_module, state, step)?
-            .map(|expr| match *Expr::expr_enum(expr) {
-                ExprEnum::Reg(reg) => Self { annotations, reg },
-                _ => unreachable!(),
-            }))
+impl_run_pass_for_struct! {
+    #[constructor = TargetChild::new(parent, path_element)]
+    impl[] RunPass for TargetChild {
+        parent(): _,
+        path_element(): _,
     }
 }
 
-impl<Step: ProcessStep> RunProcessStep<Step> for StmtInstance
-where
-    ResetTarget: RunProcessStep<Step>,
-    ConnectAndLhsInstantiatedModule: RunProcessStep<Step>,
-{
-    fn run_process_step(
-        self,
-        instantiated_module: InstantiatedModule,
-        state: &mut State,
-        step: &mut Step,
-    ) -> Result<Processed<Self, Step>, Step::Error> {
-        let Self {
-            annotations,
-            instance,
-        } = self;
-        let child_instantiated_module = InstantiatedModule::Child {
-            parent: instantiated_module.intern_sized(),
-            instance: instance.intern_sized(),
-        };
-        instance
-            .instantiated()
-            .run_process_step(child_instantiated_module, state, step)?;
-        for (field_index, AnnotatedModuleIO { module_io, .. }) in
-            instance.instantiated().module_io().into_iter().enumerate()
-        {
-            let (lhs_instantiated_module, lhs, rhs_instantiated_module, rhs) = match module_io
-                .flow()
-            {
-                Flow::Source => {
-                    // connect to submodule's input from instance input
-                    (
-                        child_instantiated_module,
-                        module_io.to_expr(),
-                        instantiated_module,
-                        ops::FieldAccess::new_by_index(instance.to_expr(), field_index).to_expr(),
-                    )
-                }
-                Flow::Sink => {
-                    // connect to instance output from submodule's output
-                    (
-                        instantiated_module,
-                        ops::FieldAccess::new_by_index(instance.to_expr(), field_index).to_expr(),
-                        child_instantiated_module,
-                        module_io.to_expr(),
-                    )
-                }
-                Flow::Duplex => unreachable!(),
-            };
-            ConnectAndLhsInstantiatedModule {
-                lhs_instantiated_module,
-                lhs,
-                rhs,
-                source_location: instance.source_location(),
-            }
-            .run_process_step(rhs_instantiated_module, state, step)?;
-        }
-        Ok(Expr::canonical(instance.to_expr())
-            .run_process_step(instantiated_module, state, step)?
-            .map(|expr| match *Expr::expr_enum(expr) {
-                ExprEnum::Instance(instance) => Self {
-                    annotations,
-                    instance,
-                },
-                _ => unreachable!(),
-            }))
+impl_run_pass_for_enum! {
+    impl[] RunPass for Annotation {
+        DontTouch(v),
+        SVAttribute(v),
+        BlackBoxInline(v),
+        BlackBoxPath(v),
+        DocString(v),
+        CustomFirrtl(v),
     }
 }
 
-impl<Step: ProcessStep> RunProcessStep<Step> for StmtDeclaration
-where
-    ResetTarget: RunProcessStep<Step>,
-    ConnectAndLhsInstantiatedModule: RunProcessStep<Step>,
-{
-    fn run_process_step(
-        self,
-        instantiated_module: InstantiatedModule,
-        state: &mut State,
-        step: &mut Step,
-    ) -> Result<Processed<Self, Step>, Step::Error> {
-        Ok(match self {
-            StmtDeclaration::Wire(decl) => decl
-                .run_process_step(instantiated_module, state, step)?
-                .map(StmtDeclaration::from),
-            StmtDeclaration::Reg(decl) => decl
-                .run_process_step(instantiated_module, state, step)?
-                .map(StmtDeclaration::from),
-            StmtDeclaration::Instance(decl) => decl
-                .run_process_step(instantiated_module, state, step)?
-                .map(StmtDeclaration::from),
-        })
+impl_run_pass_for_enum! {
+    impl[] RunPass for ModuleBody {
+        Normal(v),
+        Extern(v),
     }
 }
 
-impl<Step: ProcessStep> RunProcessStep<Step> for Stmt
-where
-    ResetTarget: RunProcessStep<Step>,
-    ConnectAndLhsInstantiatedModule: RunProcessStep<Step>,
-{
-    fn run_process_step(
-        self,
-        instantiated_module: InstantiatedModule,
-        state: &mut State,
-        step: &mut Step,
-    ) -> Result<Processed<Self, Step>, Step::Error> {
-        Ok(match self {
-            Stmt::Connect(stmt) => stmt
-                .run_process_step(instantiated_module, state, step)?
-                .map(Stmt::from),
-            Stmt::Formal(stmt) => stmt
-                .run_process_step(instantiated_module, state, step)?
-                .map(Stmt::from),
-            Stmt::If(stmt) => stmt
-                .run_process_step(instantiated_module, state, step)?
-                .map(Stmt::from),
-            Stmt::Match(stmt) => stmt
-                .run_process_step(instantiated_module, state, step)?
-                .map(Stmt::from),
-            Stmt::Declaration(stmt) => stmt
-                .run_process_step(instantiated_module, state, step)?
-                .map(Stmt::from),
-        })
+impl_run_pass_for_struct! {
+    #[constructor = TargetedAnnotation::new(target, annotation)]
+    impl[] RunPass for TargetedAnnotation {
+        target(): _,
+        annotation(): _,
     }
 }
 
-impl<Step: ProcessStep> RunProcessStep<Step> for Block
-where
-    ResetTarget: RunProcessStep<Step>,
-    ConnectAndLhsInstantiatedModule: RunProcessStep<Step>,
-{
-    fn run_process_step(
-        self,
-        instantiated_module: InstantiatedModule,
-        state: &mut State,
-        step: &mut Step,
-    ) -> Result<Processed<Self, Step>, Step::Error> {
-        let Block { memories, stmts } = self;
-        // memories and memory ports won't ever contain any Reset values,
-        // so always just use the old `memories` value. we add the ports to the graph anyway to make the other logic easier.
-        for memory in memories {
-            for port in memory.ports() {
-                Expr::canonical(port.to_expr()).run_process_step(
-                    instantiated_module,
-                    state,
-                    step,
-                )?;
-            }
-        }
-        let stmts = Result::<Processed<_, _>, _>::from_iter(
-            stmts
-                .iter()
-                .map(|stmt| stmt.run_process_step(instantiated_module, state, step)),
-        )?;
-        Ok(stmts.map(|stmts| Block { memories, stmts }))
+impl_run_pass_for_struct! {
+    impl[] RunPass for AnnotatedModuleIO {
+        annotations: _,
+        module_io: _,
     }
 }
 
-impl<Step: ProcessStep> RunProcessStep<Step> for Module<Bundle>
-where
-    ResetTarget: RunProcessStep<Step>,
-    ConnectAndLhsInstantiatedModule: RunProcessStep<Step>,
-{
-    fn run_process_step(
-        self,
-        instantiated_module: InstantiatedModule,
-        state: &mut State,
-        step: &mut Step,
-    ) -> Result<Processed<Self, Step>, Step::Error> {
-        let module = *instantiated_module.leaf_module();
-        let module_io =
-            Result::<Processed<Interned<[_]>, _>, _>::from_iter(module.module_io().iter().map(
-                |&AnnotatedModuleIO {
-                     annotations,
-                     module_io,
-                 }| {
-                    Ok(module_io
-                        .run_process_step(instantiated_module, state, step)?
-                        .map(|module_io| AnnotatedModuleIO {
-                            annotations,
-                            module_io,
-                        }))
-                },
-            ))?;
-        let body = match module.body() {
-            ModuleBody::Normal(NormalModuleBody { body }) => body
-                .run_process_step(instantiated_module, state, step)?
-                .map(|body| ModuleBody::Normal(NormalModuleBody { body })),
-            body @ ModuleBody::Extern(ExternModuleBody {
-                verilog_name: _,
-                parameters: _,
-            }) => Processed::new(body),
-        };
-        Ok(module_io.zip(body).map(|(module_io, body)| {
-            Module::new_unchecked(
-                module.name_id(),
-                module.source_location(),
-                body,
-                module_io,
-                module.module_annotations(),
-            )
-        }))
+impl_run_pass_for_struct! {
+    #[adjust_pass_args = |module: &Module<_>, pass_args: &mut PassArgs<'_, _>| {
+        pass_args.fallback_error_source_location = module.source_location();
+    }]
+    #[constructor = Module::new_unchecked(
+        name_id,
+        source_location,
+        body,
+        module_io,
+        module_annotations,
+    )]
+    impl[] RunPass for Module<Bundle> {
+        name_id(): _,
+        source_location(): _,
+        body(): _,
+        module_io(): _,
+        module_annotations(): _,
     }
 }
 
@@ -816,21 +810,28 @@ pub fn deduce_resets(
 ) -> Result<Interned<Module<Bundle>>, DeduceResetsError> {
     let mut state = State {
         base_module: module,
-        node_ids: HashMap::new(),
-        graph: UnGraph::new_undirected(),
+        expr_resets: HashMap::new(),
+        reset_graph: ResetGraph::default(),
         fallback_to_sync_reset,
     };
-    let Ok(Processed(())) = module.run_process_step(
-        InstantiatedModule::Base(module),
-        &mut state,
-        &mut AddNodesToGraphStep,
-    );
-    let mut step = AddEdgesToGraphStep {
-        union_find: UnionFind::new(state.graph.node_count()),
-    };
-    let Ok(Processed(())) =
-        module.run_process_step(InstantiatedModule::Base(module), &mut state, &mut step);
-    let AddEdgesToGraphStep { union_find } = step;
-    todo!("deduce types");
-    Ok(todo!("transform module"))
+    RunPass::<BuildResetGraph>::run_pass(
+        &*module,
+        PassArgs {
+            state: &mut state,
+            instantiated_module: InstantiatedModule::Base(module),
+            fallback_error_source_location: module.source_location(),
+            _phantom: PhantomData,
+        },
+    )?;
+    Ok(RunPass::<SubstituteResets>::run_pass(
+        &*module,
+        PassArgs {
+            state: &mut state,
+            instantiated_module: InstantiatedModule::Base(module),
+            fallback_error_source_location: module.source_location(),
+            _phantom: PhantomData,
+        },
+    )?
+    .0
+    .intern_sized())
 }

From c45624e3c29de5bbcfb8e24a525073f5ee67a287 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 26 Nov 2024 16:26:29 -0800
Subject: [PATCH 101/190] Fix SInt::for_value not accounting for sign bit for
 positive values

Fixes: #4
---
 crates/fayalite/src/int.rs | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index 03b2c88..4dd7696 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -453,7 +453,10 @@ impl SInt {
                     v.not().bits().checked_add(1).expect("too big")
                 }
                 Sign::NoSign => 0,
-                Sign::Plus => v.bits(),
+                Sign::Plus => {
+                    // account for sign bit
+                    v.bits().checked_add(1).expect("too big")
+                }
             }
             .try_into()
             .expect("too big"),
@@ -693,3 +696,31 @@ impl ToLiteralBits for bool {
         Ok(interned_bit(*self))
     }
 }
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_uint_for_value() {
+        assert_eq!(UInt::for_value(0u8).width, 0);
+        assert_eq!(UInt::for_value(1u8).width, 1);
+        assert_eq!(UInt::for_value(2u8).width, 2);
+        assert_eq!(UInt::for_value(3u8).width, 2);
+        assert_eq!(UInt::for_value(4u8).width, 3);
+    }
+
+    #[test]
+    fn test_sint_for_value() {
+        assert_eq!(SInt::for_value(-5).width, 4);
+        assert_eq!(SInt::for_value(-4).width, 3);
+        assert_eq!(SInt::for_value(-3).width, 3);
+        assert_eq!(SInt::for_value(-2).width, 2);
+        assert_eq!(SInt::for_value(-1).width, 1);
+        assert_eq!(SInt::for_value(0).width, 0);
+        assert_eq!(SInt::for_value(1).width, 2);
+        assert_eq!(SInt::for_value(2).width, 3);
+        assert_eq!(SInt::for_value(3).width, 3);
+        assert_eq!(SInt::for_value(4).width, 4);
+    }
+}

From 89d84551f82929ab02fd698fd31554c027eb2a06 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 26 Nov 2024 18:52:03 -0800
Subject: [PATCH 102/190] add ResetType to the list of recognized type bounds

---
 .../src/hdl_type_common.rs                       | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
index 3f3f817..6193dc3 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
@@ -2044,6 +2044,7 @@ pub(crate) mod known_items {
     impl_known_item!(::fayalite::int::Size);
     impl_known_item!(::fayalite::int::UInt);
     impl_known_item!(::fayalite::int::UIntType);
+    impl_known_item!(::fayalite::reset::ResetType);
     impl_known_item!(::fayalite::ty::CanonicalType);
     impl_known_item!(::fayalite::ty::StaticType);
     impl_known_item!(::fayalite::ty::Type);
@@ -2239,6 +2240,7 @@ impl_bounds! {
         EnumType,
         IntType,
         KnownSize,
+        ResetType,
         Size,
         StaticType,
         Type,
@@ -2252,6 +2254,7 @@ impl_bounds! {
         BundleType,
         EnumType,
         IntType,
+        ResetType,
         StaticType,
         Type,
     }
@@ -2264,6 +2267,7 @@ impl From<ParsedTypeBound> for ParsedBound {
             ParsedTypeBound::BundleType(v) => ParsedBound::BundleType(v),
             ParsedTypeBound::EnumType(v) => ParsedBound::EnumType(v),
             ParsedTypeBound::IntType(v) => ParsedBound::IntType(v),
+            ParsedTypeBound::ResetType(v) => ParsedBound::ResetType(v),
             ParsedTypeBound::StaticType(v) => ParsedBound::StaticType(v),
             ParsedTypeBound::Type(v) => ParsedBound::Type(v),
         }
@@ -2277,6 +2281,7 @@ impl From<ParsedTypeBounds> for ParsedBounds {
             BundleType,
             EnumType,
             IntType,
+            ResetType,
             StaticType,
             Type,
         } = value;
@@ -2286,6 +2291,7 @@ impl From<ParsedTypeBounds> for ParsedBounds {
             EnumType,
             IntType,
             KnownSize: None,
+            ResetType,
             Size: None,
             StaticType,
             Type,
@@ -2314,6 +2320,11 @@ impl ParsedTypeBound {
                 ParsedTypeBound::BoolOrIntType(known_items::BoolOrIntType(span)),
                 ParsedTypeBound::Type(known_items::Type(span)),
             ]),
+            Self::ResetType(v) => ParsedTypeBounds::from_iter([
+                ParsedTypeBound::from(v),
+                ParsedTypeBound::StaticType(known_items::StaticType(span)),
+                ParsedTypeBound::Type(known_items::Type(span)),
+            ]),
             Self::StaticType(v) => ParsedTypeBounds::from_iter([
                 ParsedTypeBound::from(v),
                 ParsedTypeBound::Type(known_items::Type(span)),
@@ -2349,6 +2360,7 @@ impl From<ParsedSizeTypeBounds> for ParsedBounds {
             EnumType: None,
             IntType: None,
             KnownSize,
+            ResetType: None,
             Size,
             StaticType: None,
             Type: None,
@@ -2425,6 +2437,7 @@ impl ParsedBound {
             Self::EnumType(v) => ParsedBoundCategory::Type(ParsedTypeBound::EnumType(v)),
             Self::IntType(v) => ParsedBoundCategory::Type(ParsedTypeBound::IntType(v)),
             Self::KnownSize(v) => ParsedBoundCategory::SizeType(ParsedSizeTypeBound::KnownSize(v)),
+            Self::ResetType(v) => ParsedBoundCategory::Type(ParsedTypeBound::ResetType(v)),
             Self::Size(v) => ParsedBoundCategory::SizeType(ParsedSizeTypeBound::Size(v)),
             Self::StaticType(v) => ParsedBoundCategory::Type(ParsedTypeBound::StaticType(v)),
             Self::Type(v) => ParsedBoundCategory::Type(ParsedTypeBound::Type(v)),
@@ -3310,7 +3323,8 @@ impl ParsedGenerics {
                                 ParsedTypeBound::BoolOrIntType(_)
                                 | ParsedTypeBound::BundleType(_)
                                 | ParsedTypeBound::EnumType(_)
-                                | ParsedTypeBound::IntType(_) => {
+                                | ParsedTypeBound::IntType(_)
+                                | ParsedTypeBound::ResetType(_) => {
                                     errors.error(bound, "bound on mask type not implemented");
                                 }
                                 ParsedTypeBound::StaticType(bound) => {

From 9b5f1218fda1137eb5c840c2c9ff7ff9e12f9f50 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 26 Nov 2024 20:47:03 -0800
Subject: [PATCH 103/190] make ClockDomain and Reg generic over reset type

---
 crates/fayalite/src/clock.rs                  |   6 +-
 crates/fayalite/src/expr.rs                   |  30 ++++-
 crates/fayalite/src/expr/target.rs            |  55 +++++++-
 crates/fayalite/src/firrtl.rs                 |  75 +++++++----
 crates/fayalite/src/module.rs                 | 124 ++++++++++++++----
 .../src/module/transform/simplify_enums.rs    |   4 +-
 crates/fayalite/src/module/transform/visit.rs |   2 +-
 crates/fayalite/src/reg.rs                    |  15 ++-
 crates/fayalite/src/reset.rs                  |  31 ++++-
 crates/fayalite/src/sim.rs                    |  34 ++++-
 crates/fayalite/visit_types.json              |  15 ++-
 11 files changed, 306 insertions(+), 85 deletions(-)

diff --git a/crates/fayalite/src/clock.rs b/crates/fayalite/src/clock.rs
index fe99653..711432b 100644
--- a/crates/fayalite/src/clock.rs
+++ b/crates/fayalite/src/clock.rs
@@ -4,7 +4,7 @@ use crate::{
     expr::{Expr, ToExpr},
     hdl,
     int::Bool,
-    reset::Reset,
+    reset::{Reset, ResetType},
     source_location::SourceLocation,
     ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
 };
@@ -88,9 +88,9 @@ impl ToClock for Expr<Clock> {
 }
 
 #[hdl]
-pub struct ClockDomain {
+pub struct ClockDomain<R: ResetType = Reset> {
     pub clk: Clock,
-    pub rst: Reset,
+    pub rst: R,
 }
 
 impl ToClock for bool {
diff --git a/crates/fayalite/src/expr.rs b/crates/fayalite/src/expr.rs
index fa50852..f0008f4 100644
--- a/crates/fayalite/src/expr.rs
+++ b/crates/fayalite/src/expr.rs
@@ -17,6 +17,7 @@ use crate::{
         Instance, ModuleIO,
     },
     reg::Reg,
+    reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
     ty::{CanonicalType, StaticType, Type, TypeWithDeref},
     wire::Wire,
 };
@@ -209,7 +210,9 @@ expr_enum! {
         ModuleIO(ModuleIO<CanonicalType>),
         Instance(Instance<Bundle>),
         Wire(Wire<CanonicalType>),
-        Reg(Reg<CanonicalType>),
+        Reg(Reg<CanonicalType, Reset>),
+        RegSync(Reg<CanonicalType, SyncReset>),
+        RegAsync(Reg<CanonicalType, AsyncReset>),
         MemPort(MemPort<DynPortType>),
     }
 }
@@ -593,25 +596,42 @@ impl<T: Type> GetTarget for Wire<T> {
     }
 }
 
-impl<T: Type> ToExpr for Reg<T> {
+impl<T: Type, R: ResetType> ToExpr for Reg<T, R> {
     type Type = T;
 
     fn to_expr(&self) -> Expr<Self::Type> {
+        struct Dispatch;
+        impl ResetTypeDispatch for Dispatch {
+            type Input<T: ResetType> = Reg<CanonicalType, T>;
+            type Output<T: ResetType> = ExprEnum;
+
+            fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset> {
+                ExprEnum::Reg(input)
+            }
+
+            fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
+                ExprEnum::RegSync(input)
+            }
+
+            fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
+                ExprEnum::RegAsync(input)
+            }
+        }
         Expr {
-            __enum: ExprEnum::Reg(self.canonical()).intern_sized(),
+            __enum: R::dispatch(self.canonical(), Dispatch).intern_sized(),
             __ty: self.ty(),
             __flow: self.flow(),
         }
     }
 }
 
-impl<T: Type> ToLiteralBits for Reg<T> {
+impl<T: Type, R: ResetType> ToLiteralBits for Reg<T, R> {
     fn to_literal_bits(&self) -> Result<Interned<BitSlice>, NotALiteralExpr> {
         Err(NotALiteralExpr)
     }
 }
 
-impl<T: Type> GetTarget for Reg<T> {
+impl<T: Type, R: ResetType> GetTarget for Reg<T, R> {
     fn target(&self) -> Option<Interned<Target>> {
         Some(Intern::intern_sized(self.canonical().into()))
     }
diff --git a/crates/fayalite/src/expr/target.rs b/crates/fayalite/src/expr/target.rs
index 849be00..8f39e13 100644
--- a/crates/fayalite/src/expr/target.rs
+++ b/crates/fayalite/src/expr/target.rs
@@ -8,6 +8,7 @@ use crate::{
     memory::{DynPortType, MemPort},
     module::{Instance, ModuleIO, TargetName},
     reg::Reg,
+    reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
     wire::Wire,
@@ -127,6 +128,7 @@ macro_rules! impl_target_base {
         $(#[$enum_meta:meta])*
         $enum_vis:vis enum $TargetBase:ident {
             $(
+                $(#[from = $from:ident])?
                 #[is = $is_fn:ident]
                 #[to = $to_fn:ident]
                 $(#[$variant_meta:meta])*
@@ -150,19 +152,19 @@ macro_rules! impl_target_base {
             }
         }
 
-        $(
+        $($(
         impl From<$VariantTy> for $TargetBase {
-            fn from(value: $VariantTy) -> Self {
+            fn $from(value: $VariantTy) -> Self {
                 Self::$Variant(value)
             }
         }
 
         impl From<$VariantTy> for Target {
-            fn from(value: $VariantTy) -> Self {
+            fn $from(value: $VariantTy) -> Self {
                 $TargetBase::$Variant(value).into()
             }
         }
-        )*
+        )*)?
 
         impl $TargetBase {
             $(
@@ -199,24 +201,63 @@ macro_rules! impl_target_base {
 impl_target_base! {
     #[derive(Copy, Clone, PartialEq, Eq, Hash)]
     pub enum TargetBase {
+        #[from = from]
         #[is = is_module_io]
         #[to = module_io]
         ModuleIO(ModuleIO<CanonicalType>),
+        #[from = from]
         #[is = is_mem_port]
         #[to = mem_port]
         MemPort(MemPort<DynPortType>),
         #[is = is_reg]
         #[to = reg]
-        Reg(Reg<CanonicalType>),
+        Reg(Reg<CanonicalType, Reset>),
+        #[is = is_reg_sync]
+        #[to = reg_sync]
+        RegSync(Reg<CanonicalType, SyncReset>),
+        #[is = is_reg_async]
+        #[to = reg_async]
+        RegAsync(Reg<CanonicalType, AsyncReset>),
+        #[from = from]
         #[is = is_wire]
         #[to = wire]
         Wire(Wire<CanonicalType>),
+        #[from = from]
         #[is = is_instance]
         #[to = instance]
         Instance(Instance<Bundle>),
     }
 }
 
+impl<R: ResetType> From<Reg<CanonicalType, R>> for TargetBase {
+    fn from(value: Reg<CanonicalType, R>) -> Self {
+        struct Dispatch;
+        impl ResetTypeDispatch for Dispatch {
+            type Input<T: ResetType> = Reg<CanonicalType, T>;
+            type Output<T: ResetType> = TargetBase;
+
+            fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset> {
+                TargetBase::Reg(input)
+            }
+
+            fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
+                TargetBase::RegSync(input)
+            }
+
+            fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
+                TargetBase::RegAsync(input)
+            }
+        }
+        R::dispatch(value, Dispatch)
+    }
+}
+
+impl<R: ResetType> From<Reg<CanonicalType, R>> for Target {
+    fn from(value: Reg<CanonicalType, R>) -> Self {
+        TargetBase::from(value).into()
+    }
+}
+
 impl fmt::Display for TargetBase {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         write!(f, "{:?}", self.target_name())
@@ -229,6 +270,8 @@ impl TargetBase {
             TargetBase::ModuleIO(v) => TargetName(v.scoped_name(), None),
             TargetBase::MemPort(v) => TargetName(v.mem_name(), Some(v.port_name())),
             TargetBase::Reg(v) => TargetName(v.scoped_name(), None),
+            TargetBase::RegSync(v) => TargetName(v.scoped_name(), None),
+            TargetBase::RegAsync(v) => TargetName(v.scoped_name(), None),
             TargetBase::Wire(v) => TargetName(v.scoped_name(), None),
             TargetBase::Instance(v) => TargetName(v.scoped_name(), None),
         }
@@ -238,6 +281,8 @@ impl TargetBase {
             TargetBase::ModuleIO(v) => v.ty(),
             TargetBase::MemPort(v) => v.ty().canonical(),
             TargetBase::Reg(v) => v.ty(),
+            TargetBase::RegSync(v) => v.ty(),
+            TargetBase::RegAsync(v) => v.ty(),
             TargetBase::Wire(v) => v.ty(),
             TargetBase::Instance(v) => v.ty().canonical(),
         }
diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index bc75ccc..ea76cf8 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -31,7 +31,7 @@ use crate::{
         StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg,
         StmtWire,
     },
-    reset::{AsyncReset, Reset, SyncReset},
+    reset::{AsyncReset, Reset, ResetType, SyncReset},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
     util::{
@@ -1739,6 +1739,14 @@ impl<'a> Exporter<'a> {
                 assert!(!const_ty, "not a constant");
                 self.module.ns.get(expr.scoped_name().1).to_string()
             }
+            ExprEnum::RegSync(expr) => {
+                assert!(!const_ty, "not a constant");
+                self.module.ns.get(expr.scoped_name().1).to_string()
+            }
+            ExprEnum::RegAsync(expr) => {
+                assert!(!const_ty, "not a constant");
+                self.module.ns.get(expr.scoped_name().1).to_string()
+            }
             ExprEnum::MemPort(expr) => {
                 assert!(!const_ty, "not a constant");
                 let mem_name = self.module.ns.get(expr.mem_name().1);
@@ -1848,6 +1856,8 @@ impl<'a> Exporter<'a> {
                         self.module.ns.get(v.mem_name().1)
                     }
                     TargetBase::Reg(v) => self.module.ns.get(v.name_id()),
+                    TargetBase::RegSync(v) => self.module.ns.get(v.name_id()),
+                    TargetBase::RegAsync(v) => self.module.ns.get(v.name_id()),
                     TargetBase::Wire(v) => self.module.ns.get(v.name_id()),
                     TargetBase::Instance(v) => self.module.ns.get(v.name_id()),
                 };
@@ -1956,6 +1966,37 @@ impl<'a> Exporter<'a> {
         drop(memory_indent);
         Ok(body)
     }
+    fn stmt_reg<R: ResetType>(
+        &mut self,
+        stmt_reg: StmtReg<R>,
+        module_name: Ident,
+        definitions: &RcDefinitions,
+        body: &mut String,
+    ) {
+        let StmtReg { annotations, reg } = stmt_reg;
+        let indent = self.indent;
+        self.targeted_annotations(module_name, vec![], &annotations);
+        let name = self.module.ns.get(reg.name_id());
+        let ty = self.type_state.ty(reg.ty());
+        let clk = self.expr(Expr::canonical(reg.clock_domain().clk), definitions, false);
+        if let Some(init) = reg.init() {
+            let rst = self.expr(Expr::canonical(reg.clock_domain().rst), definitions, false);
+            let init = self.expr(init, definitions, false);
+            writeln!(
+                body,
+                "{indent}regreset {name}: {ty}, {clk}, {rst}, {init}{}",
+                FileInfo::new(reg.source_location()),
+            )
+            .unwrap();
+        } else {
+            writeln!(
+                body,
+                "{indent}reg {name}: {ty}, {clk}{}",
+                FileInfo::new(reg.source_location()),
+            )
+            .unwrap();
+        }
+    }
     fn block(
         &mut self,
         module: Interned<Module<Bundle>>,
@@ -2126,30 +2167,14 @@ impl<'a> Exporter<'a> {
                     )
                     .unwrap();
                 }
-                Stmt::Declaration(StmtDeclaration::Reg(StmtReg { annotations, reg })) => {
-                    self.targeted_annotations(module_name, vec![], &annotations);
-                    let name = self.module.ns.get(reg.name_id());
-                    let ty = self.type_state.ty(reg.ty());
-                    let clk =
-                        self.expr(Expr::canonical(reg.clock_domain().clk), &definitions, false);
-                    if let Some(init) = reg.init() {
-                        let rst =
-                            self.expr(Expr::canonical(reg.clock_domain().rst), &definitions, false);
-                        let init = self.expr(init, &definitions, false);
-                        writeln!(
-                            body,
-                            "{indent}regreset {name}: {ty}, {clk}, {rst}, {init}{}",
-                            FileInfo::new(reg.source_location()),
-                        )
-                        .unwrap();
-                    } else {
-                        writeln!(
-                            body,
-                            "{indent}reg {name}: {ty}, {clk}{}",
-                            FileInfo::new(reg.source_location()),
-                        )
-                        .unwrap();
-                    }
+                Stmt::Declaration(StmtDeclaration::Reg(stmt_reg)) => {
+                    self.stmt_reg(stmt_reg, module_name, &definitions, &mut body);
+                }
+                Stmt::Declaration(StmtDeclaration::RegSync(stmt_reg)) => {
+                    self.stmt_reg(stmt_reg, module_name, &definitions, &mut body);
+                }
+                Stmt::Declaration(StmtDeclaration::RegAsync(stmt_reg)) => {
+                    self.stmt_reg(stmt_reg, module_name, &definitions, &mut body);
                 }
                 Stmt::Declaration(StmtDeclaration::Instance(StmtInstance {
                     annotations,
diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index 915bf43..5a18ac9 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -20,6 +20,7 @@ use crate::{
     intern::{Intern, Interned},
     memory::{Mem, MemBuilder, MemBuilderTarget, PortName},
     reg::Reg,
+    reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
     util::ScopedRef,
@@ -350,7 +351,7 @@ macro_rules! wrapper_enum {
         $(#[$enum_meta:meta])*
         $vis:vis enum $enum_name:ident<$T_enum:ident: $T_bound:ident = $T_enum_default:ident> {
             $(
-                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident]
+                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident $(, from = $from:ident)?]
                 $(#[$variant_meta:meta])*
                 $Variant:ident($VariantTy:ty),
             )*
@@ -362,7 +363,7 @@ macro_rules! wrapper_enum {
             $(#[$enum_meta])*
             $vis enum $enum_name<$T_enum: $T_bound = $T_enum_default> {
                 $(
-                    #[is = $is_fn, as_ref = $as_ref_fn]
+                    #[is = $is_fn, as_ref = $as_ref_fn $(, from = $from)?]
                     $(#[$variant_meta])*
                     $Variant($VariantTy),
                 )*
@@ -389,7 +390,7 @@ macro_rules! wrapper_enum {
         $(#[$enum_meta:meta])*
         $vis:vis enum $enum_name:ident<$T_enum:ident: $T_bound:ident = $T_enum_default:ident> {
             $(
-                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident]
+                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident $(, from = $from:ident)?]
                 $(#[$variant_meta:meta])*
                 $Variant:ident($VariantTy:ty),
             )*
@@ -401,22 +402,22 @@ macro_rules! wrapper_enum {
             $(#[$enum_meta])*
             $vis enum $enum_name<$T_enum: $T_bound = $T_enum_default> {
                 $(
-                    #[is = $is_fn, as_ref = $as_ref_fn]
+                    #[is = $is_fn, as_ref = $as_ref_fn $(, from = $from)?]
                     $(#[$variant_meta])*
                     $Variant($VariantTy),
                 )*
             }
         }
 
-        $(
+        $($(
             wrapper_enum! {
                 impl $T_to From<$VariantTy> for $to_type {
-                    fn from(value: $VariantTy) -> Self {
+                    fn $from(value: $VariantTy) -> Self {
                         $enum_name::$Variant(value).into()
                     }
                 }
             }
-        )*
+        )?)*
     };
     (
         #[impl()]
@@ -424,7 +425,7 @@ macro_rules! wrapper_enum {
         $(#[$enum_meta:meta])*
         $vis:vis enum $enum_name:ident<$T_enum:ident: $T_bound:ident = $T_enum_default:ident> {
             $(
-                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident]
+                #[is = $is_fn:ident, as_ref = $as_ref_fn:ident $(, from = $from:ident)?]
                 $(#[$variant_meta:meta])*
                 $Variant:ident($VariantTy:ty),
             )*
@@ -466,12 +467,12 @@ pub struct StmtWire<S: ModuleBuildingStatus = ModuleBuilt> {
 impl Copy for StmtWire {}
 
 #[derive(Hash, Clone, PartialEq, Eq, Debug)]
-pub struct StmtReg<S: ModuleBuildingStatus = ModuleBuilt> {
+pub struct StmtReg<R: ResetType, S: ModuleBuildingStatus = ModuleBuilt> {
     pub annotations: S::StmtAnnotations,
-    pub reg: Reg<CanonicalType>,
+    pub reg: Reg<CanonicalType, R>,
 }
 
-impl Copy for StmtReg {}
+impl<R: ResetType> Copy for StmtReg<R> {}
 
 #[derive(Clone, PartialEq, Eq, Hash, Debug)]
 pub struct StmtInstance<S: ModuleBuildingStatus = ModuleBuilt> {
@@ -489,22 +490,57 @@ wrapper_enum! {
     #[to((<S: ModuleBuildingStatus>) StmtDeclaration<S>, (<S: ModuleBuildingStatus>) Stmt<S>)]
     #[derive(Clone, PartialEq, Eq, Hash)]
     pub enum StmtDeclaration<S: ModuleBuildingStatus = ModuleBuilt> {
-        #[is = is_wire, as_ref = wire]
+        #[is = is_wire, as_ref = wire, from = from]
         Wire(StmtWire<S>),
         #[is = is_reg, as_ref = reg]
-        Reg(StmtReg<S>),
-        #[is = is_instance, as_ref = instance]
+        Reg(StmtReg<Reset, S>),
+        #[is = is_reg_sync, as_ref = reg_sync]
+        RegSync(StmtReg<SyncReset, S>),
+        #[is = is_reg_async, as_ref = reg_async]
+        RegAsync(StmtReg<AsyncReset, S>),
+        #[is = is_instance, as_ref = instance, from = from]
         Instance(StmtInstance<S>),
     }
 }
 
 impl Copy for StmtDeclaration {}
 
+impl<S: ModuleBuildingStatus, R: ResetType> From<StmtReg<R, S>> for Stmt<S> {
+    fn from(value: StmtReg<R, S>) -> Self {
+        StmtDeclaration::from(value).into()
+    }
+}
+
+impl<S: ModuleBuildingStatus, R: ResetType> From<StmtReg<R, S>> for StmtDeclaration<S> {
+    fn from(value: StmtReg<R, S>) -> Self {
+        struct Dispatch<S>(PhantomData<S>);
+        impl<S: ModuleBuildingStatus> ResetTypeDispatch for Dispatch<S> {
+            type Input<T: ResetType> = StmtReg<T, S>;
+            type Output<T: ResetType> = StmtDeclaration<S>;
+
+            fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset> {
+                StmtDeclaration::Reg(input)
+            }
+
+            fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
+                StmtDeclaration::RegSync(input)
+            }
+
+            fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
+                StmtDeclaration::RegAsync(input)
+            }
+        }
+        R::dispatch(value, Dispatch(PhantomData))
+    }
+}
+
 impl<S: ModuleBuildingStatus> StmtDeclaration<S> {
     pub fn annotations(&self) -> S::StmtAnnotations {
         match self {
             StmtDeclaration::Wire(v) => v.annotations,
             StmtDeclaration::Reg(v) => v.annotations,
+            StmtDeclaration::RegSync(v) => v.annotations,
+            StmtDeclaration::RegAsync(v) => v.annotations,
             StmtDeclaration::Instance(v) => v.annotations,
         }
     }
@@ -512,6 +548,8 @@ impl<S: ModuleBuildingStatus> StmtDeclaration<S> {
         match self {
             StmtDeclaration::Wire(v) => v.wire.source_location(),
             StmtDeclaration::Reg(v) => v.reg.source_location(),
+            StmtDeclaration::RegSync(v) => v.reg.source_location(),
+            StmtDeclaration::RegAsync(v) => v.reg.source_location(),
             StmtDeclaration::Instance(v) => v.instance.source_location(),
         }
     }
@@ -519,20 +557,26 @@ impl<S: ModuleBuildingStatus> StmtDeclaration<S> {
         match self {
             StmtDeclaration::Wire(v) => v.wire.scoped_name(),
             StmtDeclaration::Reg(v) => v.reg.scoped_name(),
+            StmtDeclaration::RegSync(v) => v.reg.scoped_name(),
+            StmtDeclaration::RegAsync(v) => v.reg.scoped_name(),
             StmtDeclaration::Instance(v) => v.instance.scoped_name(),
         }
     }
     pub fn sub_stmt_blocks(&self) -> &[S::Block] {
         match self {
-            StmtDeclaration::Wire(_) | StmtDeclaration::Reg(_) | StmtDeclaration::Instance(_) => {
-                &[]
-            }
+            StmtDeclaration::Wire(_)
+            | StmtDeclaration::Reg(_)
+            | StmtDeclaration::RegSync(_)
+            | StmtDeclaration::RegAsync(_)
+            | StmtDeclaration::Instance(_) => &[],
         }
     }
     pub fn canonical_ty(&self) -> CanonicalType {
         match self {
             StmtDeclaration::Wire(v) => v.wire.ty(),
             StmtDeclaration::Reg(v) => v.reg.ty(),
+            StmtDeclaration::RegSync(v) => v.reg.ty(),
+            StmtDeclaration::RegAsync(v) => v.reg.ty(),
             StmtDeclaration::Instance(v) => CanonicalType::Bundle(v.instance.ty()),
         }
     }
@@ -543,15 +587,15 @@ wrapper_enum! {
     #[to((<S: ModuleBuildingStatus>) Stmt<S>)]
     #[derive(Clone, PartialEq, Eq, Hash)]
     pub enum Stmt<S: ModuleBuildingStatus = ModuleBuilt> {
-        #[is = is_connect, as_ref = connect]
+        #[is = is_connect, as_ref = connect, from = from]
         Connect(StmtConnect),
-        #[is = is_formal, as_ref = formal]
+        #[is = is_formal, as_ref = formal, from = from]
         Formal(StmtFormal),
-        #[is = is_if, as_ref = if_]
+        #[is = is_if, as_ref = if_, from = from]
         If(StmtIf<S>),
-        #[is = is_match, as_ref = match_]
+        #[is = is_match, as_ref = match_, from = from]
         Match(StmtMatch<S>),
-        #[is = is_declaration, as_ref = declaration]
+        #[is = is_declaration, as_ref = declaration, from = from]
         Declaration(StmtDeclaration<S>),
     }
 }
@@ -982,6 +1026,14 @@ impl From<NormalModuleBody<ModuleBuilding>> for NormalModuleBody {
                                 annotations: (),
                                 reg,
                             }) => StmtReg { annotations, reg }.into(),
+                            StmtDeclaration::RegSync(StmtReg {
+                                annotations: (),
+                                reg,
+                            }) => StmtReg { annotations, reg }.into(),
+                            StmtDeclaration::RegAsync(StmtReg {
+                                annotations: (),
+                                reg,
+                            }) => StmtReg { annotations, reg }.into(),
                             StmtDeclaration::Instance(StmtInstance {
                                 annotations: (),
                                 instance,
@@ -1685,6 +1737,14 @@ impl AssertValidityState {
                     annotations: _,
                     reg,
                 })) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block),
+                Stmt::Declaration(StmtDeclaration::RegSync(StmtReg {
+                    annotations: _,
+                    reg,
+                })) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block),
+                Stmt::Declaration(StmtDeclaration::RegAsync(StmtReg {
+                    annotations: _,
+                    reg,
+                })) => self.insert_new_base(TargetBase::intern_sized(reg.into()), block),
                 Stmt::Declaration(StmtDeclaration::Instance(StmtInstance {
                     annotations: _,
                     instance,
@@ -1866,10 +1926,10 @@ impl<CD> RegBuilder<CD, (), ()> {
 }
 
 impl<I, T: Type> RegBuilder<(), I, T> {
-    pub fn clock_domain(
+    pub fn clock_domain<R: ResetType>(
         self,
-        clock_domain: impl ToExpr<Type = ClockDomain>,
-    ) -> RegBuilder<Expr<ClockDomain>, I, T> {
+        clock_domain: impl ToExpr<Type = ClockDomain<R>>,
+    ) -> RegBuilder<Expr<ClockDomain<R>>, I, T> {
         let Self {
             name,
             source_location,
@@ -1887,7 +1947,7 @@ impl<I, T: Type> RegBuilder<(), I, T> {
     }
 }
 
-impl<T: Type> RegBuilder<Expr<ClockDomain>, Option<Expr<T>>, T> {
+impl<T: Type, R: ResetType> RegBuilder<Expr<ClockDomain<R>>, Option<Expr<T>>, T> {
     #[track_caller]
     pub fn build(self) -> Expr<T> {
         let Self {
@@ -2212,6 +2272,16 @@ pub fn annotate<T: Type>(target: Expr<T>, annotations: impl IntoAnnotations) {
             reg,
         }
         .into(),
+        TargetBase::RegSync(reg) => StmtReg {
+            annotations: (),
+            reg,
+        }
+        .into(),
+        TargetBase::RegAsync(reg) => StmtReg {
+            annotations: (),
+            reg,
+        }
+        .into(),
         TargetBase::Wire(wire) => StmtWire {
             annotations: (),
             wire,
@@ -2698,5 +2768,5 @@ pub struct TargetInInstantiatedModule {
 #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
 pub struct ExprInInstantiatedModule<T: Type> {
     pub instantiated_module: InstantiatedModule,
-    pub target: Expr<T>,
+    pub expr: Expr<T>,
 }
diff --git a/crates/fayalite/src/module/transform/simplify_enums.rs b/crates/fayalite/src/module/transform/simplify_enums.rs
index bb57cf0..4eb0d0c 100644
--- a/crates/fayalite/src/module/transform/simplify_enums.rs
+++ b/crates/fayalite/src/module/transform/simplify_enums.rs
@@ -764,7 +764,9 @@ impl Folder for State {
             | ExprEnum::ModuleIO(_)
             | ExprEnum::Instance(_)
             | ExprEnum::Wire(_)
-            | ExprEnum::Reg(_) => op.default_fold(self),
+            | ExprEnum::Reg(_)
+            | ExprEnum::RegSync(_)
+            | ExprEnum::RegAsync(_) => op.default_fold(self),
         }
     }
 
diff --git a/crates/fayalite/src/module/transform/visit.rs b/crates/fayalite/src/module/transform/visit.rs
index 2e1e48f..97de4fc 100644
--- a/crates/fayalite/src/module/transform/visit.rs
+++ b/crates/fayalite/src/module/transform/visit.rs
@@ -29,7 +29,7 @@ use crate::{
         StmtInstance, StmtMatch, StmtReg, StmtWire,
     },
     reg::Reg,
-    reset::{AsyncReset, Reset, SyncReset},
+    reset::{AsyncReset, Reset, ResetType, SyncReset},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
     wire::Wire,
diff --git a/crates/fayalite/src/reg.rs b/crates/fayalite/src/reg.rs
index 8f757f2..20e0b94 100644
--- a/crates/fayalite/src/reg.rs
+++ b/crates/fayalite/src/reg.rs
@@ -5,21 +5,22 @@ use crate::{
     expr::{Expr, Flow},
     intern::Interned,
     module::{NameId, ScopedNameId},
+    reset::{Reset, ResetType},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
 };
 use std::fmt;
 
 #[derive(Copy, Clone, Eq, PartialEq, Hash)]
-pub struct Reg<T: Type> {
+pub struct Reg<T: Type, R: ResetType = Reset> {
     name: ScopedNameId,
     source_location: SourceLocation,
     ty: T,
-    clock_domain: Expr<ClockDomain>,
+    clock_domain: Expr<ClockDomain<R>>,
     init: Option<Expr<T>>,
 }
 
-impl<T: Type + fmt::Debug> fmt::Debug for Reg<T> {
+impl<T: Type + fmt::Debug, R: ResetType> fmt::Debug for Reg<T, R> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
             name,
@@ -37,8 +38,8 @@ impl<T: Type + fmt::Debug> fmt::Debug for Reg<T> {
     }
 }
 
-impl<T: Type> Reg<T> {
-    pub fn canonical(&self) -> Reg<CanonicalType> {
+impl<T: Type, R: ResetType> Reg<T, R> {
+    pub fn canonical(&self) -> Reg<CanonicalType, R> {
         let Self {
             name,
             source_location,
@@ -59,7 +60,7 @@ impl<T: Type> Reg<T> {
         scoped_name: ScopedNameId,
         source_location: SourceLocation,
         ty: T,
-        clock_domain: Expr<ClockDomain>,
+        clock_domain: Expr<ClockDomain<R>>,
         init: Option<Expr<T>>,
     ) -> Self {
         assert!(
@@ -98,7 +99,7 @@ impl<T: Type> Reg<T> {
     pub fn scoped_name(&self) -> ScopedNameId {
         self.name
     }
-    pub fn clock_domain(&self) -> Expr<ClockDomain> {
+    pub fn clock_domain(&self) -> Expr<ClockDomain<R>> {
         self.clock_domain
     }
     pub fn init(&self) -> Option<Expr<T>> {
diff --git a/crates/fayalite/src/reset.rs b/crates/fayalite/src/reset.rs
index 70d5f02..0dd6df8 100644
--- a/crates/fayalite/src/reset.rs
+++ b/crates/fayalite/src/reset.rs
@@ -11,10 +11,21 @@ mod sealed {
     pub trait ResetTypeSealed {}
 }
 
-pub trait ResetType: StaticType<MaskType = Bool> + sealed::ResetTypeSealed {}
+pub trait ResetType: StaticType<MaskType = Bool> + sealed::ResetTypeSealed {
+    fn dispatch<D: ResetTypeDispatch>(input: D::Input<Self>, dispatch: D) -> D::Output<Self>;
+}
+
+pub trait ResetTypeDispatch: Sized {
+    type Input<T: ResetType>;
+    type Output<T: ResetType>;
+
+    fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset>;
+    fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset>;
+    fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset>;
+}
 
 macro_rules! reset_type {
-    ($name:ident, $Trait:ident::$trait_fn:ident, $is_castable_from_bits:literal) => {
+    ($name:ident, $Trait:ident::$trait_fn:ident, $is_castable_from_bits:literal, $dispatch_fn:ident) => {
         #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Default)]
         pub struct $name;
 
@@ -67,7 +78,14 @@ macro_rules! reset_type {
 
         impl sealed::ResetTypeSealed for $name {}
 
-        impl ResetType for $name {}
+        impl ResetType for $name {
+            fn dispatch<D: ResetTypeDispatch>(
+                input: D::Input<Self>,
+                dispatch: D,
+            ) -> D::Output<Self> {
+                dispatch.$dispatch_fn(input)
+            }
+        }
 
         pub trait $Trait {
             fn $trait_fn(&self) -> Expr<$name>;
@@ -99,12 +117,13 @@ macro_rules! reset_type {
     };
 }
 
-reset_type!(AsyncReset, ToAsyncReset::to_async_reset, true);
-reset_type!(SyncReset, ToSyncReset::to_sync_reset, true);
+reset_type!(AsyncReset, ToAsyncReset::to_async_reset, true, async_reset);
+reset_type!(SyncReset, ToSyncReset::to_sync_reset, true, sync_reset);
 reset_type!(
     Reset,
     ToReset::to_reset,
-    false // Reset is not castable from bits because we don't know if it's async or sync
+    false, // Reset is not castable from bits because we don't know if it's async or sync
+    reset
 );
 
 impl ToSyncReset for bool {
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 1bed47d..4780ea2 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -1405,6 +1405,18 @@ impl Compiler {
                 ty: reg.ty(),
             }
             .into(),
+            TargetBase::RegSync(reg) => TraceReg {
+                name: reg.name(),
+                child: self.make_trace_decl_child(target, reg.name()).intern(),
+                ty: reg.ty(),
+            }
+            .into(),
+            TargetBase::RegAsync(reg) => TraceReg {
+                name: reg.name(),
+                child: self.make_trace_decl_child(target, reg.name()).intern(),
+                ty: reg.ty(),
+            }
+            .into(),
             TargetBase::Wire(wire) => TraceWire {
                 name: wire.name(),
                 child: self.make_trace_decl_child(target, wire.name()).intern(),
@@ -1452,7 +1464,7 @@ impl Compiler {
                     | TargetBase::MemPort(_)
                     | TargetBase::Wire(_)
                     | TargetBase::Instance(_) => None,
-                    TargetBase::Reg(_) => {
+                    TargetBase::Reg(_) | TargetBase::RegSync(_) | TargetBase::RegAsync(_) => {
                         let write_layout = unprefixed_layout.with_prefixed_debug_names(&format!(
                             "{:?}.{:?}$next",
                             target.instantiated_module,
@@ -2412,6 +2424,18 @@ impl Compiler {
                     target: expr.into(),
                 })
                 .into(),
+            ExprEnum::RegSync(expr) => self
+                .compile_value(TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: expr.into(),
+                })
+                .into(),
+            ExprEnum::RegAsync(expr) => self
+                .compile_value(TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: expr.into(),
+                })
+                .into(),
             ExprEnum::MemPort(expr) => self
                 .compile_value(TargetInInstantiatedModule {
                     instantiated_module,
@@ -2606,6 +2630,8 @@ impl Compiler {
         let target_base: TargetBase = match &declaration {
             StmtDeclaration::Wire(v) => v.wire.into(),
             StmtDeclaration::Reg(v) => v.reg.into(),
+            StmtDeclaration::RegSync(v) => v.reg.into(),
+            StmtDeclaration::RegAsync(v) => v.reg.into(),
             StmtDeclaration::Instance(v) => v.instance.into(),
         };
         let target = TargetInInstantiatedModule {
@@ -2619,6 +2645,12 @@ impl Compiler {
             StmtDeclaration::Reg(StmtReg { annotations, reg }) => {
                 todo!();
             }
+            StmtDeclaration::RegSync(StmtReg { annotations, reg }) => {
+                todo!();
+            }
+            StmtDeclaration::RegAsync(StmtReg { annotations, reg }) => {
+                todo!();
+            }
             StmtDeclaration::Instance(StmtInstance {
                 annotations,
                 instance,
diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json
index 182efd9..3eff1f5 100644
--- a/crates/fayalite/visit_types.json
+++ b/crates/fayalite/visit_types.json
@@ -1047,9 +1047,9 @@
                 "clock_domain()": "Visible",
                 "init()": "Visible"
             },
-            "generics": "<T: Type>",
-            "fold_where": "T: Fold<State>",
-            "visit_where": "T: Visit<State>"
+            "generics": "<T: Type, R: ResetType>",
+            "fold_where": "T: Fold<State>, R: Fold<State>",
+            "visit_where": "T: Visit<State>, R: Visit<State>"
         },
         "Wire": {
             "data": {
@@ -1078,6 +1078,8 @@
                 "$kind": "Enum",
                 "Wire": "Visible",
                 "Reg": "Visible",
+                "RegSync": "Visible",
+                "RegAsync": "Visible",
                 "Instance": "Visible"
             }
         },
@@ -1136,7 +1138,10 @@
                 "$kind": "Struct",
                 "annotations": "Visible",
                 "reg": "Visible"
-            }
+            },
+            "generics": "<R: ResetType>",
+            "fold_where": "R: Fold<State>",
+            "visit_where": "R: Visit<State>"
         },
         "StmtWire": {
             "data": {
@@ -1219,6 +1224,8 @@
                 "ModuleIO": "Visible",
                 "MemPort": "Visible",
                 "Reg": "Visible",
+                "RegSync": "Visible",
+                "RegAsync": "Visible",
                 "Wire": "Visible",
                 "Instance": "Visible"
             }

From 546010739a187e0343e46edda3fd5b59d8c27341 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 26 Nov 2024 21:26:56 -0800
Subject: [PATCH 104/190] working on deduce_resets

---
 .../src/module/transform/deduce_resets.rs     | 744 ++++++++++++++++--
 1 file changed, 697 insertions(+), 47 deletions(-)

diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs
index e6b5987..d9009f8 100644
--- a/crates/fayalite/src/module/transform/deduce_resets.rs
+++ b/crates/fayalite/src/module/transform/deduce_resets.rs
@@ -3,44 +3,41 @@
 
 #![cfg(todo)]
 
-use hashbrown::{hash_map::Entry, HashMap};
-use num_bigint::BigInt;
-use petgraph::{
-    graph::{NodeIndex, UnGraph},
-    unionfind::UnionFind,
-};
-
 use crate::{
     annotations::{Annotation, TargetedAnnotation},
     bundle::{BundleField, BundleType},
     enum_::{EnumType, EnumVariant},
     expr::{
-        ops,
         target::{
             Target, TargetBase, TargetChild, TargetPathArrayElement, TargetPathBundleField,
             TargetPathDynArrayElement, TargetPathElement,
         },
-        ExprEnum, Flow,
+        ExprEnum,
     },
+    int::{SIntValue, UIntValue},
     intern::{Intern, Interned, Memoize},
     memory::{DynPortType, MemPort},
     module::{
-        transform::visit::{Folder, Visit, Visitor},
-        AnnotatedModuleIO, Block, ExprInInstantiatedModule, ExternModuleBody,
-        ExternModuleParameter, ExternModuleParameterValue, InstantiatedModule, ModuleBody,
-        ModuleIO, NameId, NormalModuleBody, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtIf,
-        StmtInstance, StmtMatch, StmtReg, StmtWire,
+        AnnotatedModuleIO, Block, ExprInInstantiatedModule, ExternModuleBody, InstantiatedModule,
+        ModuleBody, ModuleIO, NameId, NormalModuleBody,
     },
     prelude::*,
-    source_location,
+    reset::{ResetType, ResetTypeDispatch},
+};
+use hashbrown::{hash_map::Entry, HashMap};
+use hashbrown::{hash_map::Entry, HashMap};
+use num_bigint::BigInt;
+use num_bigint::BigInt;
+use petgraph::unionfind::UnionFind;
+use petgraph::{
+    graph::{NodeIndex, UnGraph},
+    unionfind::UnionFind,
 };
 use std::{
     borrow::Borrow,
-    convert::Infallible,
     fmt,
     hash::{Hash, Hasher},
     marker::PhantomData,
-    mem,
 };
 
 #[derive(Debug)]
@@ -70,6 +67,25 @@ impl From<DeduceResetsError> for std::io::Error {
     }
 }
 
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+enum AnyReg {
+    Reg(Reg<CanonicalType, Reset>),
+    RegSync(Reg<CanonicalType, SyncReset>),
+    RegAsync(Reg<CanonicalType, AsyncReset>),
+}
+
+macro_rules! match_any_reg {
+    (
+        $match_expr:expr, $fn:expr
+    ) => {
+        match $match_expr {
+            AnyReg::Reg(reg) => $fn(reg),
+            AnyReg::RegSync(reg) => $fn(reg),
+            AnyReg::RegAsync(reg) => $fn(reg),
+        }
+    };
+}
+
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
 enum ResetsLayout {
     NoResets,
@@ -261,6 +277,45 @@ impl ResetGraph {
             })
         }
     }
+    fn append_new_nodes_for_layout(
+        &mut self,
+        layout: ResetsLayout,
+        node_indexes: &mut Vec<ResetNodeIndex>,
+        source_location: Option<SourceLocation>,
+    ) {
+        match layout {
+            ResetsLayout::NoResets => {}
+            ResetsLayout::Reset => node_indexes.push(self.new_node(None, source_location)),
+            ResetsLayout::SyncReset => {
+                node_indexes.push(self.new_node(Some(false), source_location))
+            }
+            ResetsLayout::AsyncReset => {
+                node_indexes.push(self.new_node(Some(true), source_location))
+            }
+            ResetsLayout::Bundle {
+                fields,
+                reset_count: _,
+            } => {
+                for field in fields {
+                    self.append_new_nodes_for_layout(field, node_indexes, source_location);
+                }
+            }
+            ResetsLayout::Enum {
+                variants,
+                reset_count: _,
+            } => {
+                for variant in variants {
+                    self.append_new_nodes_for_layout(variant, node_indexes, source_location);
+                }
+            }
+            ResetsLayout::Array {
+                element,
+                reset_count: _,
+            } => {
+                self.append_new_nodes_for_layout(*element, node_indexes, source_location);
+            }
+        }
+    }
 }
 
 #[derive(Debug)]
@@ -318,23 +373,164 @@ impl<'a, T: ?Sized + Intern> MaybeInterned<'a, T> {
 }
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
-struct Resets<'a> {
+struct Resets {
     ty: CanonicalType,
     layout: ResetsLayout,
-    node_indexes: MaybeInterned<'a, [ResetNodeIndex]>,
+    node_indexes: Interned<[ResetNodeIndex]>,
 }
 
-impl<'a> Resets<'a> {
-    fn into_interned(self) -> Resets<'static> {
-        let Self {
+impl Resets {
+    fn with_new_nodes(
+        reset_graph: &mut ResetGraph,
+        ty: CanonicalType,
+        source_location: Option<SourceLocation>,
+    ) -> Self {
+        let layout = ResetsLayout::new(ty);
+        let mut node_indexes = Vec::with_capacity(layout.reset_count());
+        reset_graph.append_new_nodes_for_layout(layout, &mut node_indexes, source_location);
+        let node_indexes = Intern::intern_owned(node_indexes);
+        Self {
             ty,
             layout,
             node_indexes,
-        } = self;
-        Resets {
-            ty,
-            layout,
-            node_indexes: MaybeInterned::Interned(node_indexes.to_interned()),
+        }
+    }
+    fn array_elements(self) -> Self {
+        let array = <Array>::from_canonical(self.ty);
+        let ResetsLayout::Array {
+            element,
+            reset_count: _,
+        } = self.layout
+        else {
+            unreachable!();
+        };
+        Self {
+            ty: array.element(),
+            layout: *element,
+            node_indexes: self.node_indexes,
+        }
+    }
+    fn bundle_fields(self) -> impl Iterator<Item = Self> {
+        let bundle = Bundle::from_canonical(self.ty);
+        let ResetsLayout::Bundle {
+            fields,
+            reset_count: _,
+        } = self.layout
+        else {
+            unreachable!();
+        };
+        bundle.fields().into_iter().zip(fields).scan(
+            0,
+            move |start_index, (BundleField { ty, .. }, layout)| {
+                let end_index = *start_index + layout.reset_count();
+                let node_indexes = self.node_indexes[*start_index..end_index].intern();
+                *start_index = end_index;
+                Some(Self {
+                    ty,
+                    layout,
+                    node_indexes,
+                })
+            },
+        )
+    }
+    fn enum_variants(self) -> impl Iterator<Item = Option<Self>> {
+        let enum_ = Enum::from_canonical(self.ty);
+        let ResetsLayout::Enum {
+            variants,
+            reset_count: _,
+        } = self.layout
+        else {
+            unreachable!();
+        };
+        enum_.variants().into_iter().zip(variants).scan(
+            0,
+            move |start_index, (EnumVariant { ty, .. }, layout)| {
+                let end_index = *start_index + layout.reset_count();
+                let node_indexes = self.node_indexes[*start_index..end_index].intern();
+                *start_index = end_index;
+                Some(ty.map(|ty| Self {
+                    ty,
+                    layout,
+                    node_indexes,
+                }))
+            },
+        )
+    }
+    fn substituted_type(
+        self,
+        reset_graph: &mut ResetGraph,
+        fallback_to_sync_reset: bool,
+        fallback_error_source_location: SourceLocation,
+    ) -> Result<CanonicalType, DeduceResetsError> {
+        if self.layout.reset_count() == 0 {
+            return Ok(self.ty);
+        }
+        match self.ty {
+            CanonicalType::UInt(_)
+            | CanonicalType::SInt(_)
+            | CanonicalType::Bool(_)
+            | CanonicalType::AsyncReset(_)
+            | CanonicalType::SyncReset(_)
+            | CanonicalType::Clock(_) => Ok(self.ty),
+            CanonicalType::Array(ty) => Ok(CanonicalType::Array(Array::new_dyn(
+                self.array_elements().substituted_type(
+                    reset_graph,
+                    fallback_to_sync_reset,
+                    fallback_error_source_location,
+                )?,
+                ty.len(),
+            ))),
+            CanonicalType::Enum(ty) => Ok(CanonicalType::Enum(Enum::new(Result::from_iter(
+                self.enum_variants().zip(ty.variants()).map(
+                    |(resets, EnumVariant { name, ty: _ })| {
+                        Ok(EnumVariant {
+                            name,
+                            ty: resets
+                                .map(|resets| {
+                                    resets.substituted_type(
+                                        reset_graph,
+                                        fallback_to_sync_reset,
+                                        fallback_error_source_location,
+                                    )
+                                })
+                                .transpose()?,
+                        })
+                    },
+                ),
+            )?))),
+            CanonicalType::Bundle(ty) => Ok(CanonicalType::Bundle(Bundle::new(Result::from_iter(
+                self.bundle_fields().zip(ty.fields()).map(
+                    |(
+                        resets,
+                        BundleField {
+                            name,
+                            flipped,
+                            ty: _,
+                        },
+                    )| {
+                        Ok(BundleField {
+                            name,
+                            flipped,
+                            ty: resets.substituted_type(
+                                reset_graph,
+                                fallback_to_sync_reset,
+                                fallback_error_source_location,
+                            )?,
+                        })
+                    },
+                ),
+            )?))),
+            CanonicalType::Reset(_) => Ok(
+                if reset_graph.is_async(
+                    self.node_indexes[0],
+                    fallback_to_sync_reset,
+                    fallback_error_source_location,
+                )? {
+                    CanonicalType::AsyncReset(AsyncReset)
+                } else {
+                    CanonicalType::SyncReset(SyncReset)
+                },
+            ),
         }
     }
 }
@@ -342,11 +538,48 @@ impl<'a> Resets<'a> {
 #[derive(Debug)]
 struct State {
     base_module: Interned<Module<Bundle>>,
-    expr_resets: HashMap<ExprInInstantiatedModule<CanonicalType>, Resets<'static>>,
+    expr_resets: HashMap<ExprInInstantiatedModule<CanonicalType>, Resets>,
     reset_graph: ResetGraph,
     fallback_to_sync_reset: bool,
 }
 
+impl State {
+    fn get_resets(
+        &self,
+        instantiated_module: InstantiatedModule,
+        expr: impl ToExpr,
+    ) -> Option<Resets> {
+        self.expr_resets
+            .get(&ExprInInstantiatedModule {
+                instantiated_module,
+                expr: Expr::canonical(expr.to_expr()),
+            })
+            .copied()
+    }
+    fn get_or_make_resets(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        expr: impl ToExpr,
+        source_location: Option<SourceLocation>,
+    ) -> (Resets, bool) {
+        let expr = Expr::canonical(expr.to_expr());
+        match self.expr_resets.entry(ExprInInstantiatedModule {
+            instantiated_module,
+            expr,
+        }) {
+            Entry::Occupied(entry) => (*entry.get(), false),
+            Entry::Vacant(entry) => (
+                *entry.insert(Resets::with_new_nodes(
+                    &mut self.reset_graph,
+                    Expr::ty(expr),
+                    source_location,
+                )),
+                true,
+            ),
+        }
+    }
+}
+
 struct PassOutput<T, P: Pass>(P::Output<T>);
 
 impl<T, P: Pass> PassOutput<T, P> {
@@ -442,6 +675,19 @@ impl<T: FromIterator<A>, P: Pass, A> FromIterator<PassOutput<A, P>> for PassOutp
     }
 }
 
+trait PassDispatch: Sized {
+    type Input<P: Pass>;
+    type Output<P: Pass>;
+    fn build_reset_graph(
+        self,
+        input: Self::Input<BuildResetGraph>,
+    ) -> Self::Output<BuildResetGraph>;
+    fn substitute_resets(
+        self,
+        input: Self::Input<SubstituteResets>,
+    ) -> Self::Output<SubstituteResets>;
+}
+
 trait Pass: Sized {
     type Output<T>;
     fn output_new<T>(v: T) -> PassOutput<T, Self>;
@@ -452,6 +698,7 @@ trait Pass: Sized {
     ) -> PassOutput<T, Self>;
     fn map<T, U>(v: PassOutput<T, Self>, f: impl FnOnce(T) -> U) -> PassOutput<U, Self>;
     fn zip<T, U>(t: PassOutput<T, Self>, u: PassOutput<U, Self>) -> PassOutput<(T, U), Self>;
+    fn dispatch<D: PassDispatch>(dispatch: D, input: D::Input<Self>) -> D::Output<Self>;
 }
 
 struct BuildResetGraph;
@@ -485,6 +732,10 @@ impl Pass for BuildResetGraph {
     fn zip<T, U>(_t: PassOutput<T, Self>, _u: PassOutput<U, Self>) -> PassOutput<(T, U), Self> {
         PassOutput(())
     }
+
+    fn dispatch<D: PassDispatch>(dispatch: D, input: D::Input<Self>) -> D::Output<Self> {
+        dispatch.build_reset_graph(input)
+    }
 }
 
 struct SubstituteResets;
@@ -517,6 +768,10 @@ impl Pass for SubstituteResets {
     fn zip<T, U>(t: PassOutput<T, Self>, u: PassOutput<U, Self>) -> PassOutput<(T, U), Self> {
         PassOutput((t.0, u.0))
     }
+
+    fn dispatch<D: PassDispatch>(dispatch: D, input: D::Input<Self>) -> D::Output<Self> {
+        dispatch.substitute_resets(input)
+    }
 }
 
 struct PassArgs<'a, P: Pass> {
@@ -560,6 +815,17 @@ impl<'a, P: Pass> PassArgs<'a, P> {
             _phantom: PhantomData,
         }
     }
+    fn get_resets(&self, expr: impl ToExpr) -> Option<Resets> {
+        self.state.get_resets(self.instantiated_module, expr)
+    }
+    fn get_or_make_resets(
+        &mut self,
+        expr: impl ToExpr,
+        source_location: Option<SourceLocation>,
+    ) -> (Resets, bool) {
+        self.state
+            .get_or_make_resets(self.instantiated_module, expr, source_location)
+    }
 }
 
 trait RunPass<P: Pass>: Sized {
@@ -569,6 +835,50 @@ trait RunPass<P: Pass>: Sized {
     ) -> Result<PassOutput<Self, P>, DeduceResetsError>;
 }
 
+trait RunPassDispatch: Sized {
+    fn build_reset_graph(
+        &self,
+        pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError>;
+    fn substitute_resets(
+        &self,
+        pass_args: PassArgs<'_, SubstituteResets>,
+    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError>;
+    fn dispatch<P: Pass>(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        struct Dispatch<'a, T>(T, PhantomData<&'a mut ()>);
+        impl<'a, T: RunPassDispatch> PassDispatch for Dispatch<'a, &'_ T> {
+            type Input<P: Pass> = PassArgs<'a, P>;
+            type Output<P: Pass> = Result<PassOutput<T, P>, DeduceResetsError>;
+
+            fn build_reset_graph(
+                self,
+                input: Self::Input<BuildResetGraph>,
+            ) -> Self::Output<BuildResetGraph> {
+                self.0.build_reset_graph(input)
+            }
+            fn substitute_resets(
+                self,
+                input: Self::Input<SubstituteResets>,
+            ) -> Self::Output<SubstituteResets> {
+                self.0.substitute_resets(input)
+            }
+        }
+        P::dispatch(Dispatch(self, PhantomData), pass_args)
+    }
+}
+
+impl<T: RunPassDispatch, P: Pass> RunPass<P> for T {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        T::dispatch(self, pass_args)
+    }
+}
+
 impl<T: RunPass<P> + Intern + Clone, P: Pass> RunPass<P> for Interned<T> {
     fn run_pass(
         &self,
@@ -590,6 +900,332 @@ where
     }
 }
 
+impl<T: RunPass<P>, P: Pass> RunPass<P> for Option<T> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        match self {
+            Some(v) => Ok(v.run_pass(pass_args)?.map(Some)),
+            None => Ok(PassOutput::new(None)),
+        }
+    }
+}
+
+fn reg_expr_run_pass<P: Pass, R: ResetType>(
+    reg: &Reg<CanonicalType, R>,
+    pass_args: PassArgs<'_, P>,
+) -> Result<PassOutput<ExprEnum, P>, DeduceResetsError> {
+    Ok(AnyReg::from(*reg)
+        .run_pass(pass_args)?
+        .map(|reg| match_any_reg!(reg, ExprEnum::from)))
+}
+
+impl<P: Pass> RunPass<P> for ExprEnum {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        match self {
+            ExprEnum::UIntLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::SIntLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BoolLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BundleLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ArrayLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::EnumLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::Uninit(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::NotU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::NotS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::NotB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::Neg(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitAndU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitAndS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitAndB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitOrU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitOrS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitOrB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitXorU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitXorS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::BitXorB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::AddU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::AddS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::SubU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::SubS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::MulU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::MulS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::DivU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::DivS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::RemU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::RemS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::DynShlU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::DynShlS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::DynShrU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::DynShrS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::FixedShlU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::FixedShlS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::FixedShrU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::FixedShrS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpLtB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpLeB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpGtB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpGeB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpEqB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpNeB(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpLtU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpLeU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpGtU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpGeU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpEqU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpNeU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpLtS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpLeS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpGtS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpGeS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpEqS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CmpNeS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastUIntToUInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastUIntToSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastSIntToUInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastSIntToSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastBoolToUInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastBoolToSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastUIntToBool(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastSIntToBool(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastBoolToSyncReset(expr) => {
+                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
+            }
+            ExprEnum::CastUIntToSyncReset(expr) => {
+                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
+            }
+            ExprEnum::CastSIntToSyncReset(expr) => {
+                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
+            }
+            ExprEnum::CastBoolToAsyncReset(expr) => {
+                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
+            }
+            ExprEnum::CastUIntToAsyncReset(expr) => {
+                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
+            }
+            ExprEnum::CastSIntToAsyncReset(expr) => {
+                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
+            }
+            ExprEnum::CastSyncResetToBool(expr) => {
+                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
+            }
+            ExprEnum::CastSyncResetToUInt(expr) => {
+                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
+            }
+            ExprEnum::CastSyncResetToSInt(expr) => {
+                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
+            }
+            ExprEnum::CastSyncResetToReset(expr) => {
+                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
+            }
+            ExprEnum::CastAsyncResetToBool(expr) => {
+                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
+            }
+            ExprEnum::CastAsyncResetToUInt(expr) => {
+                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
+            }
+            ExprEnum::CastAsyncResetToSInt(expr) => {
+                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
+            }
+            ExprEnum::CastAsyncResetToReset(expr) => {
+                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
+            }
+            ExprEnum::CastResetToBool(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastResetToUInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastResetToSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastBoolToClock(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastUIntToClock(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastSIntToClock(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastClockToBool(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastClockToUInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastClockToSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::FieldAccess(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::VariantAccess(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ArrayIndex(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::DynArrayIndex(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ReduceBitAndU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ReduceBitAndS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ReduceBitOrU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ReduceBitOrS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ReduceBitXorU(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ReduceBitXorS(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::SliceUInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::SliceSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastToBits(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastBitsTo(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::ModuleIO(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::Instance(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::Wire(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::Reg(expr) => reg_expr_run_pass(expr, pass_args),
+            ExprEnum::RegSync(expr) => reg_expr_run_pass(expr, pass_args),
+            ExprEnum::RegAsync(expr) => reg_expr_run_pass(expr, pass_args),
+            ExprEnum::MemPort(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+        }
+    }
+}
+
+impl<P: Pass> RunPass<P> for Expr<CanonicalType> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Ok(Expr::expr_enum(*self)
+            .run_pass(pass_args)?
+            .map(|expr_enum| expr_enum.to_expr()))
+    }
+}
+
+impl RunPassDispatch for ModuleIO<CanonicalType> {
+    fn build_reset_graph(
+        &self,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError> {
+        pass_args.get_or_make_resets(self, Some(self.source_location()));
+        Ok(PassOutput(()))
+    }
+
+    fn substitute_resets(
+        &self,
+        pass_args: PassArgs<'_, SubstituteResets>,
+    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError> {
+        let resets = pass_args
+            .get_resets(self)
+            .expect("added resets in build_reset_graph");
+        Ok(PassOutput(Self::new_unchecked(
+            self.containing_module_name_id(),
+            self.name_id(),
+            self.source_location(),
+            self.is_input(),
+            resets.substituted_type(
+                &mut pass_args.state.reset_graph,
+                pass_args.state.fallback_to_sync_reset,
+                self.source_location(),
+            )?,
+        )))
+    }
+}
+
+impl RunPassDispatch for Wire<CanonicalType> {
+    fn build_reset_graph(
+        &self,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError> {
+        pass_args.get_or_make_resets(self, Some(self.source_location()));
+        Ok(PassOutput(()))
+    }
+
+    fn substitute_resets(
+        &self,
+        pass_args: PassArgs<'_, SubstituteResets>,
+    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError> {
+        let resets = pass_args
+            .get_resets(self)
+            .expect("added resets in build_reset_graph");
+        Ok(PassOutput(Self::new_unchecked(
+            self.scoped_name(),
+            self.source_location(),
+            resets.substituted_type(
+                &mut pass_args.state.reset_graph,
+                pass_args.state.fallback_to_sync_reset,
+                self.source_location(),
+            )?,
+        )))
+    }
+}
+
+impl<T: ResetType> From<Reg<CanonicalType, T>> for AnyReg {
+    fn from(value: Reg<CanonicalType, T>) -> Self {
+        struct Dispatch;
+        impl ResetTypeDispatch for Dispatch {
+            type Input<T: ResetType> = Reg<CanonicalType, T>;
+            type Output<T: ResetType> = AnyReg;
+
+            fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset> {
+                AnyReg::Reg(input)
+            }
+
+            fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
+                AnyReg::RegSync(input)
+            }
+
+            fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
+                AnyReg::RegAsync(input)
+            }
+        }
+        T::dispatch(value, Dispatch)
+    }
+}
+
+impl RunPassDispatch for AnyReg {
+    fn build_reset_graph(
+        &self,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError> {
+        match_any_reg!(self, |reg: &Reg<CanonicalType, _>| {
+            pass_args
+                .get_or_make_resets(Expr::canonical(reg.to_expr()), Some(reg.source_location()));
+            reg.init().run_pass(pass_args.as_mut())?;
+            Expr::canonical(reg.clock_domain()).run_pass(pass_args)?;
+            Ok(PassOutput(()))
+        })
+    }
+
+    fn substitute_resets(
+        &self,
+        mut pass_args: PassArgs<'_, SubstituteResets>,
+    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError> {
+        match_any_reg!(self, |reg: &Reg<CanonicalType, _>| {
+            let scoped_name = reg.scoped_name();
+            let source_location = reg.source_location();
+            let resets = pass_args
+                .get_resets(Expr::canonical(reg.to_expr()))
+                .expect("added resets in build_reset_graph");
+            let ty = resets.substituted_type(
+                &mut pass_args.state.reset_graph,
+                pass_args.state.fallback_to_sync_reset,
+                source_location,
+            )?;
+            let init = reg.init().run_pass(pass_args.as_mut())?.0;
+            let clock_domain = Expr::<Bundle>::from_canonical(
+                Expr::canonical(reg.clock_domain()).run_pass(pass_args)?.0,
+            );
+            match Expr::ty(clock_domain)
+                .field_by_name("rst".intern())
+                .expect("ClockDomain has rst field")
+                .ty
+            {
+                CanonicalType::AsyncReset(_) => {
+                    Ok(PassOutput(AnyReg::RegAsync(Reg::new_unchecked(
+                        scoped_name,
+                        source_location,
+                        ty,
+                        Expr::from_bundle(clock_domain),
+                        init,
+                    ))))
+                }
+                CanonicalType::SyncReset(_) => Ok(PassOutput(AnyReg::RegSync(Reg::new_unchecked(
+                    scoped_name,
+                    source_location,
+                    ty,
+                    Expr::from_bundle(clock_domain),
+                    init,
+                )))),
+                CanonicalType::UInt(_)
+                | CanonicalType::SInt(_)
+                | CanonicalType::Bool(_)
+                | CanonicalType::Array(_)
+                | CanonicalType::Enum(_)
+                | CanonicalType::Bundle(_)
+                | CanonicalType::Reset(_)
+                | CanonicalType::Clock(_) => unreachable!(),
+            }
+        })
+    }
+}
+
 macro_rules! impl_run_pass_copy {
     ([$($generics:tt)*] $ty:ty) => {
         impl<P: Pass, $($generics)*> RunPass<P> for $ty {
@@ -616,10 +1252,21 @@ macro_rules! impl_run_pass_clone {
     };
 }
 
-impl_run_pass_copy!([] Interned<str>);
-impl_run_pass_copy!([] usize);
-impl_run_pass_copy!([] bool);
 impl_run_pass_clone!([] BigInt);
+impl_run_pass_clone!([] UIntValue);
+impl_run_pass_clone!([] SIntValue);
+impl_run_pass_copy!([] BlackBoxInlineAnnotation);
+impl_run_pass_copy!([] BlackBoxPathAnnotation);
+impl_run_pass_copy!([] bool);
+impl_run_pass_copy!([] CustomFirrtlAnnotation);
+impl_run_pass_copy!([] DocStringAnnotation);
+impl_run_pass_copy!([] DontTouchAnnotation);
+impl_run_pass_copy!([] ExternModuleBody);
+impl_run_pass_copy!([] Interned<str>);
+impl_run_pass_copy!([] NameId);
+impl_run_pass_copy!([] SourceLocation);
+impl_run_pass_copy!([] SVAttributeAnnotation);
+impl_run_pass_copy!([] usize);
 
 macro_rules! impl_run_pass_for_struct {
     (
@@ -690,25 +1337,28 @@ impl_run_pass_for_struct! {
     }
 }
 
-impl_run_pass_copy!([] ExternModuleBody);
-impl_run_pass_copy!([] NameId);
-impl_run_pass_copy!([] SourceLocation);
-impl_run_pass_copy!([] DontTouchAnnotation);
-impl_run_pass_copy!([] SVAttributeAnnotation);
-impl_run_pass_copy!([] BlackBoxInlineAnnotation);
-impl_run_pass_copy!([] BlackBoxPathAnnotation);
-impl_run_pass_copy!([] DocStringAnnotation);
-impl_run_pass_copy!([] CustomFirrtlAnnotation);
 impl_run_pass_copy!([] MemPort<DynPortType>); // Mem can't contain any `Reset` types
 impl_run_pass_copy!([] Mem); // Mem can't contain any `Reset` types
 
-impl_run_pass_for_enum! {
-    impl[] RunPass for TargetBase {
-        ModuleIO(v),
-        MemPort(v),
-        Reg(v),
-        Wire(v),
-        Instance(v),
+impl<P: Pass> RunPass<P> for TargetBase {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        let reg = match self {
+            TargetBase::ModuleIO(v) => return Ok(v.run_pass(pass_args)?.map(TargetBase::ModuleIO)),
+            TargetBase::MemPort(v) => return Ok(v.run_pass(pass_args)?.map(TargetBase::MemPort)),
+            &TargetBase::Reg(v) => v.into(),
+            &TargetBase::RegSync(v) => v.into(),
+            &TargetBase::RegAsync(v) => v.into(),
+            TargetBase::Wire(v) => return Ok(v.run_pass(pass_args)?.map(TargetBase::Wire)),
+            TargetBase::Instance(v) => return Ok(v.run_pass(pass_args)?.map(TargetBase::Instance)),
+        };
+        Ok(reg.run_pass(pass_args)?.map(|reg| match reg {
+            AnyReg::Reg(reg) => TargetBase::Reg(reg),
+            AnyReg::RegSync(reg) => TargetBase::RegSync(reg),
+            AnyReg::RegAsync(reg) => TargetBase::RegAsync(reg),
+        }))
     }
 }
 

From 358cdd10c80925b2bbe3f956289702ef3d5a137d Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 27 Nov 2024 01:30:28 -0800
Subject: [PATCH 105/190] add more expr casts

---
 crates/fayalite/src/expr/ops.rs | 78 +++++++++++++++++++++++++++++++++
 1 file changed, 78 insertions(+)

diff --git a/crates/fayalite/src/expr/ops.rs b/crates/fayalite/src/expr/ops.rs
index 3579641..51aa7d2 100644
--- a/crates/fayalite/src/expr/ops.rs
+++ b/crates/fayalite/src/expr/ops.rs
@@ -1788,6 +1788,84 @@ impl_cast_bit_op!(CastClockToBool, Clock, Bool);
 impl_cast_bit_op!(CastClockToUInt, Clock, UInt<1>, #[dyn] UInt);
 impl_cast_bit_op!(CastClockToSInt, Clock, SInt<1>, #[dyn] SInt);
 
+impl ExprCastTo<AsyncReset> for AsyncReset {
+    fn cast_to(src: Expr<Self>, _to_type: AsyncReset) -> Expr<AsyncReset> {
+        src
+    }
+}
+
+impl ExprCastTo<SyncReset> for AsyncReset {
+    fn cast_to(src: Expr<Self>, to_type: SyncReset) -> Expr<SyncReset> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<Clock> for AsyncReset {
+    fn cast_to(src: Expr<Self>, to_type: Clock) -> Expr<Clock> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<AsyncReset> for SyncReset {
+    fn cast_to(src: Expr<Self>, to_type: AsyncReset) -> Expr<AsyncReset> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<SyncReset> for SyncReset {
+    fn cast_to(src: Expr<Self>, _to_type: SyncReset) -> Expr<SyncReset> {
+        src
+    }
+}
+
+impl ExprCastTo<Clock> for SyncReset {
+    fn cast_to(src: Expr<Self>, to_type: Clock) -> Expr<Clock> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<AsyncReset> for Reset {
+    fn cast_to(src: Expr<Self>, to_type: AsyncReset) -> Expr<AsyncReset> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<SyncReset> for Reset {
+    fn cast_to(src: Expr<Self>, to_type: SyncReset) -> Expr<SyncReset> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<Reset> for Reset {
+    fn cast_to(src: Expr<Self>, _to_type: Reset) -> Expr<Reset> {
+        src
+    }
+}
+
+impl ExprCastTo<Clock> for Reset {
+    fn cast_to(src: Expr<Self>, to_type: Clock) -> Expr<Clock> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<AsyncReset> for Clock {
+    fn cast_to(src: Expr<Self>, to_type: AsyncReset) -> Expr<AsyncReset> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<SyncReset> for Clock {
+    fn cast_to(src: Expr<Self>, to_type: SyncReset) -> Expr<SyncReset> {
+        src.cast_to(Bool).cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<Clock> for Clock {
+    fn cast_to(src: Expr<Self>, _to_type: Clock) -> Expr<Clock> {
+        src
+    }
+}
+
 #[derive(Copy, Clone, PartialEq, Eq, Hash)]
 pub struct FieldAccess<FieldType: Type = CanonicalType> {
     base: Expr<Bundle>,

From d744d85c66593e9c5599be8d843eb09771076316 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 27 Nov 2024 01:31:18 -0800
Subject: [PATCH 106/190] working on deduce_resets

---
 .../src/module/transform/deduce_resets.rs     | 308 +++++++++++++++---
 1 file changed, 257 insertions(+), 51 deletions(-)

diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs
index d9009f8..ad943ae 100644
--- a/crates/fayalite/src/module/transform/deduce_resets.rs
+++ b/crates/fayalite/src/module/transform/deduce_resets.rs
@@ -8,6 +8,7 @@ use crate::{
     bundle::{BundleField, BundleType},
     enum_::{EnumType, EnumVariant},
     expr::{
+        ops,
         target::{
             Target, TargetBase, TargetChild, TargetPathArrayElement, TargetPathBundleField,
             TargetPathDynArrayElement, TargetPathElement,
@@ -25,14 +26,8 @@ use crate::{
     reset::{ResetType, ResetTypeDispatch},
 };
 use hashbrown::{hash_map::Entry, HashMap};
-use hashbrown::{hash_map::Entry, HashMap};
-use num_bigint::BigInt;
 use num_bigint::BigInt;
 use petgraph::unionfind::UnionFind;
-use petgraph::{
-    graph::{NodeIndex, UnGraph},
-    unionfind::UnionFind,
-};
 use std::{
     borrow::Borrow,
     fmt,
@@ -921,6 +916,94 @@ fn reg_expr_run_pass<P: Pass, R: ResetType>(
         .map(|reg| match_any_reg!(reg, ExprEnum::from)))
 }
 
+fn cast_bit_op<P: Pass, T: Type, A: Type>(
+    expr: impl ToExpr<Type = T>,
+    arg: Expr<A>,
+    pass_args: PassArgs<'_, P>,
+) -> Result<PassOutput<ExprEnum, P>, DeduceResetsError> {
+    struct Dispatch<'a, T: Type, A: Type> {
+        expr: Expr<T>,
+        arg: Expr<A>,
+        _phantom: PhantomData<&'a mut ()>,
+    }
+    impl<'a, T: Type, A: Type> PassDispatch for Dispatch<'a, T, A> {
+        type Input<P: Pass> = PassArgs<'a, P>;
+        type Output<P: Pass> = Result<PassOutput<ExprEnum, P>, DeduceResetsError>;
+
+        fn build_reset_graph(
+            self,
+            mut pass_args: Self::Input<BuildResetGraph>,
+        ) -> Self::Output<BuildResetGraph> {
+            Expr::canonical(self.arg).run_pass(pass_args.as_mut())?;
+            let (expr_resets, _) = pass_args.get_or_make_resets(self.expr, None);
+            let (arg_resets, _) = pass_args.get_or_make_resets(self.arg, None);
+            for (expr_node_index, arg_node_index) in expr_resets
+                .node_indexes
+                .into_iter()
+                .zip(arg_resets.node_indexes)
+            {
+                pass_args.state.reset_graph.union(
+                    expr_node_index,
+                    arg_node_index,
+                    pass_args.fallback_error_source_location,
+                )?;
+            }
+            Ok(PassOutput(()))
+        }
+
+        fn substitute_resets(
+            self,
+            mut pass_args: Self::Input<SubstituteResets>,
+        ) -> Self::Output<SubstituteResets> {
+            let resets = pass_args
+                .get_resets(self.expr)
+                .expect("added resets in build_reset_graph");
+            let arg = Expr::canonical(self.arg).run_pass(pass_args.as_mut())?;
+            let ty = resets.substituted_type(
+                &mut pass_args.state.reset_graph,
+                pass_args.state.fallback_to_sync_reset,
+                pass_args.fallback_error_source_location,
+            )?;
+            Ok(arg.map(|arg| {
+                macro_rules! match_expr_ty {
+                    ($arg:ident, $($Variant:ident),*) => {
+                        match ty {
+                            CanonicalType::Array(_)
+                            | CanonicalType::Enum(_)
+                            | CanonicalType::Bundle(_)
+                            | CanonicalType::Reset(_) => unreachable!(),
+                            $(CanonicalType::$Variant(ty) => Expr::expr_enum($arg.cast_to(ty)),)*
+                        }
+                    };
+                }
+                macro_rules! match_arg_ty {
+                    ($($Variant:ident),*) => {
+                        *match Expr::ty(arg) {
+                            CanonicalType::Array(_)
+                            | CanonicalType::Enum(_)
+                            | CanonicalType::Bundle(_)
+                            | CanonicalType::Reset(_) => unreachable!(),
+                            $(CanonicalType::$Variant(_) => {
+                                let arg = Expr::<$Variant>::from_canonical(arg);
+                                match_expr_ty!(arg, UInt, SInt, Bool, AsyncReset, SyncReset, Clock)
+                            })*
+                        }
+                    };
+                }
+                match_arg_ty!(UInt, SInt, Bool, AsyncReset, SyncReset, Clock)
+            }))
+        }
+    }
+    P::dispatch(
+        Dispatch {
+            expr: expr.to_expr(),
+            arg,
+            _phantom: PhantomData,
+        },
+        pass_args,
+    )
+}
+
 impl<P: Pass> RunPass<P> for ExprEnum {
     fn run_pass(
         &self,
@@ -991,51 +1074,23 @@ impl<P: Pass> RunPass<P> for ExprEnum {
             ExprEnum::CastBoolToSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
             ExprEnum::CastUIntToBool(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
             ExprEnum::CastSIntToBool(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
-            ExprEnum::CastBoolToSyncReset(expr) => {
-                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
-            }
-            ExprEnum::CastUIntToSyncReset(expr) => {
-                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
-            }
-            ExprEnum::CastSIntToSyncReset(expr) => {
-                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
-            }
-            ExprEnum::CastBoolToAsyncReset(expr) => {
-                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
-            }
-            ExprEnum::CastUIntToAsyncReset(expr) => {
-                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
-            }
-            ExprEnum::CastSIntToAsyncReset(expr) => {
-                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
-            }
-            ExprEnum::CastSyncResetToBool(expr) => {
-                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
-            }
-            ExprEnum::CastSyncResetToUInt(expr) => {
-                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
-            }
-            ExprEnum::CastSyncResetToSInt(expr) => {
-                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
-            }
-            ExprEnum::CastSyncResetToReset(expr) => {
-                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
-            }
-            ExprEnum::CastAsyncResetToBool(expr) => {
-                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
-            }
-            ExprEnum::CastAsyncResetToUInt(expr) => {
-                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
-            }
-            ExprEnum::CastAsyncResetToSInt(expr) => {
-                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
-            }
-            ExprEnum::CastAsyncResetToReset(expr) => {
-                Ok(expr.run_pass(pass_args)?.map(ExprEnum::from))
-            }
-            ExprEnum::CastResetToBool(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
-            ExprEnum::CastResetToUInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
-            ExprEnum::CastResetToSInt(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::CastBoolToSyncReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastUIntToSyncReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastSIntToSyncReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastBoolToAsyncReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastUIntToAsyncReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastSIntToAsyncReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastSyncResetToBool(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastSyncResetToUInt(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastSyncResetToSInt(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastSyncResetToReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastAsyncResetToBool(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastAsyncResetToUInt(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastAsyncResetToSInt(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastAsyncResetToReset(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastResetToBool(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastResetToUInt(expr) => cast_bit_op(expr, expr.arg(), pass_args),
+            ExprEnum::CastResetToSInt(expr) => cast_bit_op(expr, expr.arg(), pass_args),
             ExprEnum::CastBoolToClock(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
             ExprEnum::CastUIntToClock(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
             ExprEnum::CastSIntToClock(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
@@ -1078,6 +1133,50 @@ impl<P: Pass> RunPass<P> for Expr<CanonicalType> {
     }
 }
 
+impl<P: Pass, Width: Size> RunPass<P> for Expr<UIntType<Width>> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Ok(Expr::canonical(*self)
+            .run_pass(pass_args)?
+            .map(Expr::from_canonical))
+    }
+}
+
+impl<P: Pass, Width: Size> RunPass<P> for Expr<SIntType<Width>> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Ok(Expr::canonical(*self)
+            .run_pass(pass_args)?
+            .map(Expr::from_canonical))
+    }
+}
+
+impl<P: Pass> RunPass<P> for Expr<Bool> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Ok(Expr::canonical(*self)
+            .run_pass(pass_args)?
+            .map(Expr::from_canonical))
+    }
+}
+
+impl<P: Pass> RunPass<P> for Expr<Clock> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Ok(Expr::canonical(*self)
+            .run_pass(pass_args)?
+            .map(Expr::from_canonical))
+    }
+}
+
 impl RunPassDispatch for ModuleIO<CanonicalType> {
     fn build_reset_graph(
         &self,
@@ -1324,6 +1423,113 @@ macro_rules! impl_run_pass_for_enum {
     };
 }
 
+macro_rules! impl_run_pass_for_unary_op {
+    ($path:path) => {
+        impl_run_pass_for_struct! {
+            #[constructor = <$path>::new(arg)]
+            impl[] RunPass for $path {
+                arg(): _,
+            }
+        }
+    };
+}
+
+impl_run_pass_for_unary_op!(ops::NotU);
+impl_run_pass_for_unary_op!(ops::NotS);
+impl_run_pass_for_unary_op!(ops::NotB);
+impl_run_pass_for_unary_op!(ops::Neg);
+impl_run_pass_for_unary_op!(ops::CastBoolToUInt);
+impl_run_pass_for_unary_op!(ops::CastBoolToSInt);
+impl_run_pass_for_unary_op!(ops::CastUIntToBool);
+impl_run_pass_for_unary_op!(ops::CastSIntToBool);
+impl_run_pass_for_unary_op!(ops::CastBoolToClock);
+impl_run_pass_for_unary_op!(ops::CastUIntToClock);
+impl_run_pass_for_unary_op!(ops::CastSIntToClock);
+impl_run_pass_for_unary_op!(ops::CastClockToBool);
+impl_run_pass_for_unary_op!(ops::CastClockToUInt);
+impl_run_pass_for_unary_op!(ops::CastClockToSInt);
+impl_run_pass_for_unary_op!(ops::ReduceBitAndU);
+impl_run_pass_for_unary_op!(ops::ReduceBitAndS);
+impl_run_pass_for_unary_op!(ops::ReduceBitOrU);
+impl_run_pass_for_unary_op!(ops::ReduceBitOrS);
+impl_run_pass_for_unary_op!(ops::ReduceBitXorU);
+impl_run_pass_for_unary_op!(ops::ReduceBitXorS);
+
+macro_rules! impl_run_pass_for_binary_op {
+    ($path:path) => {
+        impl_run_pass_for_struct! {
+            #[constructor = <$path>::new(lhs, rhs)]
+            impl[] RunPass for $path {
+                lhs(): _,
+                rhs(): _,
+            }
+        }
+    };
+}
+
+impl_run_pass_for_binary_op!(ops::BitAndU);
+impl_run_pass_for_binary_op!(ops::BitAndS);
+impl_run_pass_for_binary_op!(ops::BitAndB);
+impl_run_pass_for_binary_op!(ops::BitOrU);
+impl_run_pass_for_binary_op!(ops::BitOrS);
+impl_run_pass_for_binary_op!(ops::BitOrB);
+impl_run_pass_for_binary_op!(ops::BitXorU);
+impl_run_pass_for_binary_op!(ops::BitXorS);
+impl_run_pass_for_binary_op!(ops::BitXorB);
+impl_run_pass_for_binary_op!(ops::AddU);
+impl_run_pass_for_binary_op!(ops::AddS);
+impl_run_pass_for_binary_op!(ops::SubU);
+impl_run_pass_for_binary_op!(ops::SubS);
+impl_run_pass_for_binary_op!(ops::MulU);
+impl_run_pass_for_binary_op!(ops::MulS);
+impl_run_pass_for_binary_op!(ops::DivU);
+impl_run_pass_for_binary_op!(ops::DivS);
+impl_run_pass_for_binary_op!(ops::RemU);
+impl_run_pass_for_binary_op!(ops::RemS);
+impl_run_pass_for_binary_op!(ops::DynShlU);
+impl_run_pass_for_binary_op!(ops::DynShlS);
+impl_run_pass_for_binary_op!(ops::DynShrU);
+impl_run_pass_for_binary_op!(ops::DynShrS);
+impl_run_pass_for_binary_op!(ops::FixedShlU);
+impl_run_pass_for_binary_op!(ops::FixedShlS);
+impl_run_pass_for_binary_op!(ops::FixedShrU);
+impl_run_pass_for_binary_op!(ops::FixedShrS);
+impl_run_pass_for_binary_op!(ops::CmpLtB);
+impl_run_pass_for_binary_op!(ops::CmpLeB);
+impl_run_pass_for_binary_op!(ops::CmpGtB);
+impl_run_pass_for_binary_op!(ops::CmpGeB);
+impl_run_pass_for_binary_op!(ops::CmpEqB);
+impl_run_pass_for_binary_op!(ops::CmpNeB);
+impl_run_pass_for_binary_op!(ops::CmpLtU);
+impl_run_pass_for_binary_op!(ops::CmpLeU);
+impl_run_pass_for_binary_op!(ops::CmpGtU);
+impl_run_pass_for_binary_op!(ops::CmpGeU);
+impl_run_pass_for_binary_op!(ops::CmpEqU);
+impl_run_pass_for_binary_op!(ops::CmpNeU);
+impl_run_pass_for_binary_op!(ops::CmpLtS);
+impl_run_pass_for_binary_op!(ops::CmpLeS);
+impl_run_pass_for_binary_op!(ops::CmpGtS);
+impl_run_pass_for_binary_op!(ops::CmpGeS);
+impl_run_pass_for_binary_op!(ops::CmpEqS);
+impl_run_pass_for_binary_op!(ops::CmpNeS);
+
+macro_rules! impl_run_pass_for_int_cast_op {
+    ($path:path) => {
+        impl_run_pass_for_struct! {
+            #[constructor = <$path>::new(arg, ty)]
+            impl[] RunPass for $path {
+                arg(): _,
+                ty(): _,
+            }
+        }
+    };
+}
+
+impl_run_pass_for_int_cast_op!(ops::CastUIntToUInt);
+impl_run_pass_for_int_cast_op!(ops::CastUIntToSInt);
+impl_run_pass_for_int_cast_op!(ops::CastSIntToUInt);
+impl_run_pass_for_int_cast_op!(ops::CastSIntToSInt);
+
 impl_run_pass_for_struct! {
     impl[] RunPass for Block {
         memories: _,

From d36cf92d7f9fa31463c1ef9a7484a6dc3e07e4c8 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 27 Nov 2024 23:19:55 -0800
Subject: [PATCH 107/190] make ToReset generic over the reset type

---
 crates/fayalite/src/expr/ops.rs | 32 +++++++++++++++++++++++++++++---
 crates/fayalite/src/reset.rs    | 10 +++++-----
 2 files changed, 34 insertions(+), 8 deletions(-)

diff --git a/crates/fayalite/src/expr/ops.rs b/crates/fayalite/src/expr/ops.rs
index 51aa7d2..0c8c4fa 100644
--- a/crates/fayalite/src/expr/ops.rs
+++ b/crates/fayalite/src/expr/ops.rs
@@ -19,7 +19,10 @@ use crate::{
         UIntType, UIntValue,
     },
     intern::{Intern, Interned},
-    reset::{AsyncReset, Reset, SyncReset, ToAsyncReset, ToReset, ToSyncReset},
+    reset::{
+        AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset, ToAsyncReset, ToReset,
+        ToSyncReset,
+    },
     ty::{CanonicalType, StaticType, Type},
     util::ConstUsize,
 };
@@ -1773,11 +1776,11 @@ impl_cast_bit_op!(CastSIntToAsyncReset, SInt<1>, #[dyn] SInt, AsyncReset, #[trai
 impl_cast_bit_op!(CastSyncResetToBool, SyncReset, Bool);
 impl_cast_bit_op!(CastSyncResetToUInt, SyncReset, UInt<1>, #[dyn] UInt);
 impl_cast_bit_op!(CastSyncResetToSInt, SyncReset, SInt<1>, #[dyn] SInt);
-impl_cast_bit_op!(CastSyncResetToReset, SyncReset, Reset, #[trait] ToReset::to_reset);
+impl_cast_bit_op!(CastSyncResetToReset, SyncReset, Reset);
 impl_cast_bit_op!(CastAsyncResetToBool, AsyncReset, Bool);
 impl_cast_bit_op!(CastAsyncResetToUInt, AsyncReset, UInt<1>, #[dyn] UInt);
 impl_cast_bit_op!(CastAsyncResetToSInt, AsyncReset, SInt<1>, #[dyn] SInt);
-impl_cast_bit_op!(CastAsyncResetToReset, AsyncReset, Reset, #[trait] ToReset::to_reset);
+impl_cast_bit_op!(CastAsyncResetToReset, AsyncReset, Reset);
 impl_cast_bit_op!(CastResetToBool, Reset, Bool);
 impl_cast_bit_op!(CastResetToUInt, Reset, UInt<1>, #[dyn] UInt);
 impl_cast_bit_op!(CastResetToSInt, Reset, SInt<1>, #[dyn] SInt);
@@ -1788,6 +1791,29 @@ impl_cast_bit_op!(CastClockToBool, Clock, Bool);
 impl_cast_bit_op!(CastClockToUInt, Clock, UInt<1>, #[dyn] UInt);
 impl_cast_bit_op!(CastClockToSInt, Clock, SInt<1>, #[dyn] SInt);
 
+impl<T: ResetType> ToReset for Expr<T> {
+    fn to_reset(&self) -> Expr<Reset> {
+        struct Dispatch;
+        impl ResetTypeDispatch for Dispatch {
+            type Input<T: ResetType> = Expr<T>;
+            type Output<T: ResetType> = Expr<Reset>;
+
+            fn reset(self, input: Self::Input<Reset>) -> Self::Output<Reset> {
+                input
+            }
+
+            fn sync_reset(self, input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
+                input.cast_to_static()
+            }
+
+            fn async_reset(self, input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
+                input.cast_to_static()
+            }
+        }
+        T::dispatch(*self, Dispatch)
+    }
+}
+
 impl ExprCastTo<AsyncReset> for AsyncReset {
     fn cast_to(src: Expr<Self>, _to_type: AsyncReset) -> Expr<AsyncReset> {
         src
diff --git a/crates/fayalite/src/reset.rs b/crates/fayalite/src/reset.rs
index 0dd6df8..b90d40e 100644
--- a/crates/fayalite/src/reset.rs
+++ b/crates/fayalite/src/reset.rs
@@ -25,7 +25,7 @@ pub trait ResetTypeDispatch: Sized {
 }
 
 macro_rules! reset_type {
-    ($name:ident, $Trait:ident::$trait_fn:ident, $is_castable_from_bits:literal, $dispatch_fn:ident) => {
+    ($name:ident, $(#[$impl_trait:ident])? $Trait:ident::$trait_fn:ident, $is_castable_from_bits:literal, $dispatch_fn:ident) => {
         #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Default)]
         pub struct $name;
 
@@ -109,16 +109,16 @@ macro_rules! reset_type {
             }
         }
 
-        impl $Trait for Expr<$name> {
+        $($impl_trait $Trait for Expr<$name> {
             fn $trait_fn(&self) -> Expr<$name> {
                 *self
             }
-        }
+        })?
     };
 }
 
-reset_type!(AsyncReset, ToAsyncReset::to_async_reset, true, async_reset);
-reset_type!(SyncReset, ToSyncReset::to_sync_reset, true, sync_reset);
+reset_type!(AsyncReset, #[impl] ToAsyncReset::to_async_reset, true, async_reset);
+reset_type!(SyncReset, #[impl] ToSyncReset::to_sync_reset, true, sync_reset);
 reset_type!(
     Reset,
     ToReset::to_reset,

From 6446b71afd245e6372a9ce3df97c646445d15336 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 27 Nov 2024 23:20:22 -0800
Subject: [PATCH 108/190] deduce_resets works!

---
 .../src/module/transform/deduce_resets.rs     | 877 +++++++++++++++---
 crates/fayalite/tests/module.rs               | 263 +++++-
 2 files changed, 989 insertions(+), 151 deletions(-)

diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs
index ad943ae..b2d2cb5 100644
--- a/crates/fayalite/src/module/transform/deduce_resets.rs
+++ b/crates/fayalite/src/module/transform/deduce_resets.rs
@@ -1,39 +1,34 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 
-#![cfg(todo)]
-
 use crate::{
     annotations::{Annotation, TargetedAnnotation},
     bundle::{BundleField, BundleType},
     enum_::{EnumType, EnumVariant},
     expr::{
-        ops,
+        ops::{self, ArrayLiteral},
         target::{
             Target, TargetBase, TargetChild, TargetPathArrayElement, TargetPathBundleField,
             TargetPathDynArrayElement, TargetPathElement,
         },
         ExprEnum,
     },
+    formal::FormalKind,
     int::{SIntValue, UIntValue},
     intern::{Intern, Interned, Memoize},
     memory::{DynPortType, MemPort},
     module::{
         AnnotatedModuleIO, Block, ExprInInstantiatedModule, ExternModuleBody, InstantiatedModule,
-        ModuleBody, ModuleIO, NameId, NormalModuleBody,
+        ModuleBody, ModuleIO, NameId, NormalModuleBody, Stmt, StmtConnect, StmtDeclaration,
+        StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire,
     },
     prelude::*,
     reset::{ResetType, ResetTypeDispatch},
 };
-use hashbrown::{hash_map::Entry, HashMap};
+use hashbrown::{hash_map::Entry, HashMap, HashSet};
 use num_bigint::BigInt;
 use petgraph::unionfind::UnionFind;
-use std::{
-    borrow::Borrow,
-    fmt,
-    hash::{Hash, Hasher},
-    marker::PhantomData,
-};
+use std::{fmt, marker::PhantomData};
 
 #[derive(Debug)]
 pub enum DeduceResetsError {
@@ -313,60 +308,6 @@ impl ResetGraph {
     }
 }
 
-#[derive(Debug)]
-enum MaybeInterned<'a, T: ?Sized + Intern> {
-    Interned(Interned<T>),
-    Borrowed(&'a T),
-}
-
-impl<'a, T: ?Sized + Intern> Borrow<T> for MaybeInterned<'a, T> {
-    fn borrow(&self) -> &T {
-        &**self
-    }
-}
-
-impl<'a, T: ?Sized + Intern + PartialEq> PartialEq for MaybeInterned<'a, T> {
-    fn eq(&self, other: &Self) -> bool {
-        **self == **other
-    }
-}
-
-impl<'a, T: ?Sized + Intern + Eq> Eq for MaybeInterned<'a, T> {}
-
-impl<'a, T: ?Sized + Intern + Hash> Hash for MaybeInterned<'a, T> {
-    fn hash<H: Hasher>(&self, state: &mut H) {
-        (**self).hash(state);
-    }
-}
-
-impl<'a, T: ?Sized + Intern> Copy for MaybeInterned<'a, T> {}
-
-impl<'a, T: ?Sized + Intern> Clone for MaybeInterned<'a, T> {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-
-impl<'a, T: ?Sized + Intern> std::ops::Deref for MaybeInterned<'a, T> {
-    type Target = T;
-
-    fn deref(&self) -> &Self::Target {
-        match self {
-            MaybeInterned::Interned(v) => v,
-            MaybeInterned::Borrowed(v) => v,
-        }
-    }
-}
-
-impl<'a, T: ?Sized + Intern> MaybeInterned<'a, T> {
-    fn to_interned(self) -> Interned<T> {
-        match self {
-            MaybeInterned::Interned(v) => v,
-            MaybeInterned::Borrowed(v) => v.intern(),
-        }
-    }
-}
-
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
 struct Resets {
     ty: CanonicalType,
@@ -532,7 +473,8 @@ impl Resets {
 
 #[derive(Debug)]
 struct State {
-    base_module: Interned<Module<Bundle>>,
+    modules_added_to_graph: HashSet<InstantiatedModule>,
+    substituted_modules: HashMap<InstantiatedModule, Module<Bundle>>,
     expr_resets: HashMap<ExprInInstantiatedModule<CanonicalType>, Resets>,
     reset_graph: ResetGraph,
     fallback_to_sync_reset: bool,
@@ -584,12 +526,6 @@ impl<T, P: Pass> PassOutput<T, P> {
     fn from_fn(f: impl FnOnce() -> T) -> Self {
         PassOutput::new(()).map(|()| f())
     }
-    fn as_ref(&self) -> PassOutput<&T, P> {
-        P::output_as_ref(self)
-    }
-    fn as_mut(&mut self) -> PassOutput<&mut T, P> {
-        P::output_as_mut(self)
-    }
     fn map<U>(self, f: impl FnOnce(T) -> U) -> PassOutput<U, P> {
         P::map(self, f)
     }
@@ -686,11 +622,12 @@ trait PassDispatch: Sized {
 trait Pass: Sized {
     type Output<T>;
     fn output_new<T>(v: T) -> PassOutput<T, Self>;
-    fn output_as_ref<T>(v: &PassOutput<T, Self>) -> PassOutput<&T, Self>;
-    fn output_as_mut<T>(v: &mut PassOutput<T, Self>) -> PassOutput<&mut T, Self>;
     fn output_from_iter<T: FromIterator<A>, A>(
         iter: impl IntoIterator<Item = PassOutput<A, Self>>,
     ) -> PassOutput<T, Self>;
+    fn try_array_from_fn<T, const N: usize, E>(
+        f: impl FnMut(usize) -> Result<PassOutput<T, Self>, E>,
+    ) -> Result<PassOutput<[T; N], Self>, E>;
     fn map<T, U>(v: PassOutput<T, Self>, f: impl FnOnce(T) -> U) -> PassOutput<U, Self>;
     fn zip<T, U>(t: PassOutput<T, Self>, u: PassOutput<U, Self>) -> PassOutput<(T, U), Self>;
     fn dispatch<D: PassDispatch>(dispatch: D, input: D::Input<Self>) -> D::Output<Self>;
@@ -705,14 +642,6 @@ impl Pass for BuildResetGraph {
         PassOutput(())
     }
 
-    fn output_as_ref<T>(_v: &PassOutput<T, Self>) -> PassOutput<&T, Self> {
-        PassOutput(())
-    }
-
-    fn output_as_mut<T>(_v: &mut PassOutput<T, Self>) -> PassOutput<&mut T, Self> {
-        PassOutput(())
-    }
-
     fn output_from_iter<T: FromIterator<A>, A>(
         iter: impl IntoIterator<Item = PassOutput<A, Self>>,
     ) -> PassOutput<T, Self> {
@@ -720,6 +649,15 @@ impl Pass for BuildResetGraph {
         PassOutput(())
     }
 
+    fn try_array_from_fn<T, const N: usize, E>(
+        mut f: impl FnMut(usize) -> Result<PassOutput<T, Self>, E>,
+    ) -> Result<PassOutput<[T; N], Self>, E> {
+        for i in 0..N {
+            f(i)?;
+        }
+        Ok(PassOutput(()))
+    }
+
     fn map<T, U>(_v: PassOutput<T, Self>, _f: impl FnOnce(T) -> U) -> PassOutput<U, Self> {
         PassOutput(())
     }
@@ -742,20 +680,24 @@ impl Pass for SubstituteResets {
         PassOutput(v)
     }
 
-    fn output_as_ref<T>(v: &PassOutput<T, Self>) -> PassOutput<&T, Self> {
-        PassOutput(&v.0)
-    }
-
-    fn output_as_mut<T>(v: &mut PassOutput<T, Self>) -> PassOutput<&mut T, Self> {
-        PassOutput(&mut v.0)
-    }
-
     fn output_from_iter<T: FromIterator<A>, A>(
         iter: impl IntoIterator<Item = PassOutput<A, Self>>,
     ) -> PassOutput<T, Self> {
         PassOutput(T::from_iter(iter.into_iter().map(|PassOutput(v)| v)))
     }
 
+    fn try_array_from_fn<T, const N: usize, E>(
+        mut f: impl FnMut(usize) -> Result<PassOutput<T, Self>, E>,
+    ) -> Result<PassOutput<[T; N], Self>, E> {
+        let mut retval = [const { None }; N];
+        for i in 0..N {
+            retval[i] = Some(f(i)?.0);
+        }
+        Ok(PassOutput(
+            retval.map(|v| v.expect("just wrote Some to all elements")),
+        ))
+    }
+
     fn map<T, U>(v: PassOutput<T, Self>, f: impl FnOnce(T) -> U) -> PassOutput<U, Self> {
         PassOutput(f(v.0))
     }
@@ -821,6 +763,23 @@ impl<'a, P: Pass> PassArgs<'a, P> {
         self.state
             .get_or_make_resets(self.instantiated_module, expr, source_location)
     }
+    fn union(
+        &mut self,
+        a: Resets,
+        b: Resets,
+        fallback_error_source_location: Option<SourceLocation>,
+    ) -> Result<(), DeduceResetsError> {
+        assert_eq!(a.layout, b.layout);
+        assert_eq!(a.ty, b.ty);
+        for (a_node_index, b_node_index) in a.node_indexes.into_iter().zip(b.node_indexes) {
+            self.state.reset_graph.union(
+                a_node_index,
+                b_node_index,
+                fallback_error_source_location.unwrap_or(self.fallback_error_source_location),
+            )?;
+        }
+        Ok(())
+    }
 }
 
 trait RunPass<P: Pass>: Sized {
@@ -874,6 +833,61 @@ impl<T: RunPassDispatch, P: Pass> RunPass<P> for T {
     }
 }
 
+trait RunPassExpr: ToExpr + Sized {
+    type Args<'a>: IntoIterator<Item = Expr<CanonicalType>> + 'a
+    where
+        Self: 'a;
+    fn args<'a>(&'a self) -> Self::Args<'a>;
+    fn source_location(&self) -> Option<SourceLocation>;
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError>;
+    fn new(
+        &self,
+        ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError>;
+}
+
+impl<T: RunPassExpr> RunPassDispatch for T {
+    fn build_reset_graph(
+        &self,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError> {
+        let source_location = self.source_location();
+        let (resets, _) = pass_args.get_or_make_resets(self, source_location);
+        let args_resets = Result::from_iter(self.args().into_iter().map(|arg| {
+            arg.run_pass(pass_args.as_mut())?;
+            let (resets, _) = pass_args.get_or_make_resets(arg, source_location);
+            Ok(resets)
+        }))?;
+        self.union_parts(resets, args_resets, pass_args)?;
+        Ok(PassOutput(()))
+    }
+
+    fn substitute_resets(
+        &self,
+        mut pass_args: PassArgs<'_, SubstituteResets>,
+    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError> {
+        let source_location = self.source_location();
+        let (resets, _) = pass_args.get_or_make_resets(self, source_location);
+        let ty = resets.substituted_type(
+            &mut pass_args.state.reset_graph,
+            pass_args.state.fallback_to_sync_reset,
+            pass_args.fallback_error_source_location,
+        )?;
+        let new_args = Result::from_iter(
+            self.args()
+                .into_iter()
+                .map(|arg| Ok(arg.run_pass(pass_args.as_mut())?.0)),
+        )?;
+        Ok(PassOutput(self.new(ty, new_args)?))
+    }
+}
+
 impl<T: RunPass<P> + Intern + Clone, P: Pass> RunPass<P> for Interned<T> {
     fn run_pass(
         &self,
@@ -895,6 +909,15 @@ where
     }
 }
 
+impl<T: RunPass<P>, P: Pass, const N: usize> RunPass<P> for [T; N] {
+    fn run_pass(
+        &self,
+        mut pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        P::try_array_from_fn(|i| self[i].run_pass(pass_args.as_mut()))
+    }
+}
+
 impl<T: RunPass<P>, P: Pass> RunPass<P> for Option<T> {
     fn run_pass(
         &self,
@@ -937,6 +960,7 @@ fn cast_bit_op<P: Pass, T: Type, A: Type>(
             Expr::canonical(self.arg).run_pass(pass_args.as_mut())?;
             let (expr_resets, _) = pass_args.get_or_make_resets(self.expr, None);
             let (arg_resets, _) = pass_args.get_or_make_resets(self.arg, None);
+            // don't use PassArgs::union since types don't match and we want to just union resets if they exist
             for (expr_node_index, arg_node_index) in expr_resets
                 .node_indexes
                 .into_iter()
@@ -1166,6 +1190,17 @@ impl<P: Pass> RunPass<P> for Expr<Bool> {
     }
 }
 
+impl<P: Pass> RunPass<P> for Expr<Enum> {
+    fn run_pass(
+        &self,
+        pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        Ok(Expr::canonical(*self)
+            .run_pass(pass_args)?
+            .map(Expr::from_canonical))
+    }
+}
+
 impl<P: Pass> RunPass<P> for Expr<Clock> {
     fn run_pass(
         &self,
@@ -1177,61 +1212,374 @@ impl<P: Pass> RunPass<P> for Expr<Clock> {
     }
 }
 
-impl RunPassDispatch for ModuleIO<CanonicalType> {
-    fn build_reset_graph(
-        &self,
-        mut pass_args: PassArgs<'_, BuildResetGraph>,
-    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError> {
-        pass_args.get_or_make_resets(self, Some(self.source_location()));
-        Ok(PassOutput(()))
+impl RunPassExpr for ops::Uninit {
+    type Args<'a> = [Expr<CanonicalType>; 0];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        []
     }
 
-    fn substitute_resets(
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
         &self,
-        pass_args: PassArgs<'_, SubstituteResets>,
-    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError> {
-        let resets = pass_args
-            .get_resets(self)
-            .expect("added resets in build_reset_graph");
-        Ok(PassOutput(Self::new_unchecked(
+        _resets: Resets,
+        _args_resets: Vec<Resets>,
+        _pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        ty: CanonicalType,
+        _new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(ops::Uninit::new(ty))
+    }
+}
+
+impl RunPassExpr for ops::BundleLiteral {
+    type Args<'a> = Interned<[Expr<CanonicalType>]>;
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        self.field_values()
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        for (resets_field, field_expr_resets) in resets.bundle_fields().zip(args_resets) {
+            pass_args.union(resets_field, field_expr_resets, None)?;
+        }
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(ops::BundleLiteral::new(
+            Bundle::from_canonical(ty),
+            Intern::intern_owned(new_args),
+        ))
+    }
+}
+
+impl RunPassExpr for ArrayLiteral<CanonicalType, DynSize> {
+    type Args<'a> = Interned<[Expr<CanonicalType>]>;
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        self.element_values()
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        let resets_elements = resets.array_elements();
+        for arg_resets in args_resets {
+            pass_args.union(resets_elements, arg_resets, None)?;
+        }
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new(
+            <Array>::from_canonical(ty).element(),
+            Intern::intern_owned(new_args),
+        ))
+    }
+}
+
+impl RunPassExpr for ops::EnumLiteral {
+    type Args<'a> = Option<Expr<CanonicalType>>;
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        self.variant_value()
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        if let Some(Some(variant_resets)) = resets.enum_variants().nth(self.variant_index()) {
+            pass_args.union(variant_resets, args_resets[0], None)?;
+        }
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new_by_index(
+            Enum::from_canonical(ty),
+            self.variant_index(),
+            new_args.get(0).copied(),
+        ))
+    }
+}
+
+impl RunPassExpr for ops::FieldAccess {
+    type Args<'a> = [Expr<CanonicalType>; 1];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        [Expr::canonical(self.base())]
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        let Some(field_resets) = args_resets[0].bundle_fields().nth(self.field_index()) else {
+            unreachable!();
+        };
+        pass_args.union(resets, field_resets, None)
+    }
+
+    fn new(
+        &self,
+        _ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new_by_index(
+            Expr::from_canonical(new_args[0]),
+            self.field_index(),
+        ))
+    }
+}
+
+impl RunPassExpr for ops::VariantAccess {
+    type Args<'a> = [Expr<CanonicalType>; 1];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        [Expr::canonical(self.base())]
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        if let Some(Some(variant_resets)) = args_resets[0].enum_variants().nth(self.variant_index())
+        {
+            pass_args.union(resets, variant_resets, None)?;
+        }
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        _ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new_by_index(
+            Expr::from_canonical(new_args[0]),
+            self.variant_index(),
+        ))
+    }
+}
+
+impl RunPassExpr for ops::ArrayIndex {
+    type Args<'a> = [Expr<CanonicalType>; 1];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        [Expr::canonical(self.base())]
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        pass_args.union(resets, args_resets[0].array_elements(), None)
+    }
+
+    fn new(
+        &self,
+        _ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new(
+            Expr::from_canonical(new_args[0]),
+            self.element_index(),
+        ))
+    }
+}
+
+impl RunPassExpr for ops::DynArrayIndex {
+    type Args<'a> = [Expr<CanonicalType>; 2];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        [
+            Expr::canonical(self.base()),
+            Expr::canonical(self.element_index()),
+        ]
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        resets: Resets,
+        args_resets: Vec<Resets>,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        pass_args.union(resets, args_resets[0].array_elements(), None)
+    }
+
+    fn new(
+        &self,
+        _ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new(
+            Expr::from_canonical(new_args[0]),
+            Expr::from_canonical(new_args[1]),
+        ))
+    }
+}
+
+impl RunPassExpr for ops::CastBitsTo {
+    type Args<'a> = [Expr<CanonicalType>; 1];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        [Expr::canonical(self.arg())]
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        None
+    }
+
+    fn union_parts(
+        &self,
+        _resets: Resets,
+        _args_resets: Vec<Resets>,
+        _pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        ty: CanonicalType,
+        new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new(Expr::from_canonical(new_args[0]), ty))
+    }
+}
+
+impl RunPassExpr for ModuleIO<CanonicalType> {
+    type Args<'a> = [Expr<CanonicalType>; 0];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        []
+    }
+
+    fn source_location(&self) -> Option<SourceLocation> {
+        Some(self.source_location())
+    }
+
+    fn union_parts(
+        &self,
+        _resets: Resets,
+        _args_resets: Vec<Resets>,
+        _pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        ty: CanonicalType,
+        _new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new_unchecked(
             self.containing_module_name_id(),
             self.name_id(),
             self.source_location(),
             self.is_input(),
-            resets.substituted_type(
-                &mut pass_args.state.reset_graph,
-                pass_args.state.fallback_to_sync_reset,
-                self.source_location(),
-            )?,
-        )))
+            ty,
+        ))
     }
 }
 
-impl RunPassDispatch for Wire<CanonicalType> {
-    fn build_reset_graph(
-        &self,
-        mut pass_args: PassArgs<'_, BuildResetGraph>,
-    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError> {
-        pass_args.get_or_make_resets(self, Some(self.source_location()));
-        Ok(PassOutput(()))
+impl RunPassExpr for Wire<CanonicalType> {
+    type Args<'a> = [Expr<CanonicalType>; 0];
+
+    fn args<'a>(&'a self) -> Self::Args<'a> {
+        []
     }
 
-    fn substitute_resets(
+    fn source_location(&self) -> Option<SourceLocation> {
+        Some(self.source_location())
+    }
+
+    fn union_parts(
         &self,
-        pass_args: PassArgs<'_, SubstituteResets>,
-    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError> {
-        let resets = pass_args
-            .get_resets(self)
-            .expect("added resets in build_reset_graph");
-        Ok(PassOutput(Self::new_unchecked(
+        _resets: Resets,
+        _args_resets: Vec<Resets>,
+        _pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<(), DeduceResetsError> {
+        Ok(())
+    }
+
+    fn new(
+        &self,
+        ty: CanonicalType,
+        _new_args: Vec<Expr<CanonicalType>>,
+    ) -> Result<Self, DeduceResetsError> {
+        Ok(Self::new_unchecked(
             self.scoped_name(),
             self.source_location(),
-            resets.substituted_type(
-                &mut pass_args.state.reset_graph,
-                pass_args.state.fallback_to_sync_reset,
-                self.source_location(),
-            )?,
-        )))
+            ty,
+        ))
     }
 }
 
@@ -1325,6 +1673,54 @@ impl RunPassDispatch for AnyReg {
     }
 }
 
+impl RunPassDispatch for Instance<Bundle> {
+    fn build_reset_graph(
+        &self,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError> {
+        self.instantiated().run_pass(PassArgs::<BuildResetGraph> {
+            state: pass_args.state,
+            instantiated_module: InstantiatedModule::Child {
+                parent: pass_args.instantiated_module.intern_sized(),
+                instance: self.intern(),
+            },
+            fallback_error_source_location: self.instantiated().source_location(),
+            _phantom: PhantomData,
+        })?;
+        let (resets, _) = pass_args.get_or_make_resets(self, Some(self.source_location()));
+        for (resets_field, module_io) in resets.bundle_fields().zip(self.instantiated().module_io())
+        {
+            let (module_io_resets, _) = pass_args.get_or_make_resets(
+                module_io.module_io,
+                Some(self.instantiated().source_location()),
+            );
+            pass_args.union(resets_field, module_io_resets, Some(self.source_location()))?;
+        }
+        Ok(PassOutput(()))
+    }
+
+    fn substitute_resets(
+        &self,
+        pass_args: PassArgs<'_, SubstituteResets>,
+    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError> {
+        let PassOutput(instantiated) =
+            self.instantiated().run_pass(PassArgs::<SubstituteResets> {
+                state: pass_args.state,
+                instantiated_module: InstantiatedModule::Child {
+                    parent: pass_args.instantiated_module.intern_sized(),
+                    instance: self.intern(),
+                },
+                fallback_error_source_location: self.instantiated().source_location(),
+                _phantom: PhantomData,
+            })?;
+        Ok(PassOutput(Self::new_unchecked(
+            self.scoped_name(),
+            instantiated,
+            self.source_location(),
+        )))
+    }
+}
+
 macro_rules! impl_run_pass_copy {
     ([$($generics:tt)*] $ty:ty) => {
         impl<P: Pass, $($generics)*> RunPass<P> for $ty {
@@ -1352,8 +1748,9 @@ macro_rules! impl_run_pass_clone {
 }
 
 impl_run_pass_clone!([] BigInt);
-impl_run_pass_clone!([] UIntValue);
 impl_run_pass_clone!([] SIntValue);
+impl_run_pass_clone!([] std::ops::Range<usize>);
+impl_run_pass_clone!([] UIntValue);
 impl_run_pass_copy!([] BlackBoxInlineAnnotation);
 impl_run_pass_copy!([] BlackBoxPathAnnotation);
 impl_run_pass_copy!([] bool);
@@ -1363,9 +1760,12 @@ impl_run_pass_copy!([] DontTouchAnnotation);
 impl_run_pass_copy!([] ExternModuleBody);
 impl_run_pass_copy!([] Interned<str>);
 impl_run_pass_copy!([] NameId);
+impl_run_pass_copy!([] SInt);
 impl_run_pass_copy!([] SourceLocation);
 impl_run_pass_copy!([] SVAttributeAnnotation);
+impl_run_pass_copy!([] UInt);
 impl_run_pass_copy!([] usize);
+impl_run_pass_copy!([] FormalKind);
 
 macro_rules! impl_run_pass_for_struct {
     (
@@ -1530,6 +1930,80 @@ impl_run_pass_for_int_cast_op!(ops::CastUIntToSInt);
 impl_run_pass_for_int_cast_op!(ops::CastSIntToUInt);
 impl_run_pass_for_int_cast_op!(ops::CastSIntToSInt);
 
+impl_run_pass_for_struct! {
+    #[constructor = ops::SliceUInt::new(base, range)]
+    impl[] RunPass for ops::SliceUInt {
+        base(): _,
+        range(): _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    #[constructor = ops::SliceSInt::new(base, range)]
+    impl[] RunPass for ops::SliceSInt {
+        base(): _,
+        range(): _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    #[constructor = ops::CastToBits::new(arg)]
+    impl[] RunPass for ops::CastToBits {
+        arg(): _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for StmtFormal {
+        kind: _,
+        clk: _,
+        pred: _,
+        en: _,
+        text: _,
+        source_location: _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for StmtIf {
+        cond: _,
+        source_location: _,
+        blocks: _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for StmtMatch {
+        expr: _,
+        source_location: _,
+        blocks: _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for StmtWire {
+        annotations: _,
+        wire: _,
+    }
+}
+
+impl_run_pass_for_struct! {
+    impl[] RunPass for StmtInstance {
+        annotations: _,
+        instance: _,
+    }
+}
+
+impl_run_pass_for_enum! {
+    impl[] RunPass for Stmt {
+        Connect(v),
+        Formal(v),
+        If(v),
+        Match(v),
+        Declaration(v),
+    }
+}
+
 impl_run_pass_for_struct! {
     impl[] RunPass for Block {
         memories: _,
@@ -1546,12 +2020,51 @@ impl_run_pass_for_struct! {
 impl_run_pass_copy!([] MemPort<DynPortType>); // Mem can't contain any `Reset` types
 impl_run_pass_copy!([] Mem); // Mem can't contain any `Reset` types
 
+impl RunPassDispatch for StmtConnect {
+    fn build_reset_graph(
+        &self,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError> {
+        let Self {
+            lhs,
+            rhs,
+            source_location,
+        } = *self;
+        pass_args.fallback_error_source_location = source_location;
+        lhs.run_pass(pass_args.as_mut())?;
+        rhs.run_pass(pass_args.as_mut())?;
+        let (lhs_resets, _) = pass_args.get_or_make_resets(lhs, Some(source_location));
+        let (rhs_resets, _) = pass_args.get_or_make_resets(rhs, Some(source_location));
+        pass_args.union(lhs_resets, rhs_resets, Some(source_location))?;
+        Ok(PassOutput(()))
+    }
+
+    fn substitute_resets(
+        &self,
+        mut pass_args: PassArgs<'_, SubstituteResets>,
+    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError> {
+        let StmtConnect {
+            lhs,
+            rhs,
+            source_location,
+        } = *self;
+        pass_args.fallback_error_source_location = source_location;
+        let lhs = lhs.run_pass(pass_args.as_mut())?.0;
+        let rhs = rhs.run_pass(pass_args)?.0;
+        Ok(PassOutput(StmtConnect {
+            lhs,
+            rhs,
+            source_location,
+        }))
+    }
+}
+
 impl<P: Pass> RunPass<P> for TargetBase {
     fn run_pass(
         &self,
         pass_args: PassArgs<'_, P>,
     ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
-        let reg = match self {
+        let reg: AnyReg = match self {
             TargetBase::ModuleIO(v) => return Ok(v.run_pass(pass_args)?.map(TargetBase::ModuleIO)),
             TargetBase::MemPort(v) => return Ok(v.run_pass(pass_args)?.map(TargetBase::MemPort)),
             &TargetBase::Reg(v) => v.into(),
@@ -1568,6 +2081,36 @@ impl<P: Pass> RunPass<P> for TargetBase {
     }
 }
 
+impl<P: Pass> RunPass<P> for StmtDeclaration {
+    fn run_pass(
+        &self,
+        mut pass_args: PassArgs<'_, P>,
+    ) -> Result<PassOutput<Self, P>, DeduceResetsError> {
+        let (annotations, reg) = match self {
+            StmtDeclaration::Wire(v) => {
+                return Ok(v.run_pass(pass_args)?.map(StmtDeclaration::Wire))
+            }
+            &StmtDeclaration::Reg(StmtReg { annotations, reg }) => (annotations, AnyReg::from(reg)),
+            &StmtDeclaration::RegSync(StmtReg { annotations, reg }) => {
+                (annotations, AnyReg::from(reg))
+            }
+            &StmtDeclaration::RegAsync(StmtReg { annotations, reg }) => {
+                (annotations, AnyReg::from(reg))
+            }
+            StmtDeclaration::Instance(v) => {
+                return Ok(v.run_pass(pass_args)?.map(StmtDeclaration::Instance))
+            }
+        };
+        let annotations = annotations.run_pass(pass_args.as_mut())?;
+        let reg = reg.run_pass(pass_args)?;
+        Ok((annotations, reg).call(|(annotations, reg)| match reg {
+            AnyReg::Reg(reg) => StmtReg { annotations, reg }.into(),
+            AnyReg::RegSync(reg) => StmtReg { annotations, reg }.into(),
+            AnyReg::RegAsync(reg) => StmtReg { annotations, reg }.into(),
+        }))
+    }
+}
+
 impl_run_pass_for_struct! {
     impl[] RunPass for TargetPathBundleField {
         name: _,
@@ -1640,23 +2183,56 @@ impl_run_pass_for_struct! {
     }
 }
 
-impl_run_pass_for_struct! {
-    #[adjust_pass_args = |module: &Module<_>, pass_args: &mut PassArgs<'_, _>| {
-        pass_args.fallback_error_source_location = module.source_location();
-    }]
-    #[constructor = Module::new_unchecked(
-        name_id,
-        source_location,
-        body,
-        module_io,
-        module_annotations,
-    )]
-    impl[] RunPass for Module<Bundle> {
-        name_id(): _,
-        source_location(): _,
-        body(): _,
-        module_io(): _,
-        module_annotations(): _,
+impl RunPassDispatch for Module<Bundle> {
+    fn build_reset_graph(
+        &self,
+        mut pass_args: PassArgs<'_, BuildResetGraph>,
+    ) -> Result<PassOutput<Self, BuildResetGraph>, DeduceResetsError> {
+        pass_args.fallback_error_source_location = self.source_location();
+        if pass_args
+            .state
+            .modules_added_to_graph
+            .insert(pass_args.instantiated_module)
+        {
+            self.name_id().run_pass(pass_args.as_mut())?;
+            self.source_location().run_pass(pass_args.as_mut())?;
+            self.module_io().run_pass(pass_args.as_mut())?;
+            self.body().run_pass(pass_args.as_mut())?;
+            self.module_annotations().run_pass(pass_args.as_mut())?;
+        }
+        Ok(PassOutput(()))
+    }
+
+    fn substitute_resets(
+        &self,
+        mut pass_args: PassArgs<'_, SubstituteResets>,
+    ) -> Result<PassOutput<Self, SubstituteResets>, DeduceResetsError> {
+        pass_args.fallback_error_source_location = self.source_location();
+        if let Some(&retval) = pass_args
+            .state
+            .substituted_modules
+            .get(&pass_args.instantiated_module)
+        {
+            return Ok(PassOutput(retval));
+        }
+        let PassOutput(name_id) = self.name_id().run_pass(pass_args.as_mut())?;
+        let PassOutput(source_location) = self.source_location().run_pass(pass_args.as_mut())?;
+        let PassOutput(module_io) = self.module_io().run_pass(pass_args.as_mut())?;
+        let PassOutput(body) = self.body().run_pass(pass_args.as_mut())?;
+        let PassOutput(module_annotations) =
+            self.module_annotations().run_pass(pass_args.as_mut())?;
+        let retval = Module::new_unchecked(
+            name_id,
+            source_location,
+            body,
+            module_io,
+            module_annotations,
+        );
+        pass_args
+            .state
+            .substituted_modules
+            .insert(pass_args.instantiated_module, retval);
+        Ok(PassOutput(retval))
     }
 }
 
@@ -1665,7 +2241,8 @@ pub fn deduce_resets(
     fallback_to_sync_reset: bool,
 ) -> Result<Interned<Module<Bundle>>, DeduceResetsError> {
     let mut state = State {
-        base_module: module,
+        modules_added_to_graph: HashSet::new(),
+        substituted_modules: HashMap::new(),
         expr_resets: HashMap::new(),
         reset_graph: ResetGraph::default(),
         fallback_to_sync_reset,
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 222f7ba..4cb3057 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -2,7 +2,8 @@
 // See Notices.txt for copyright information
 use fayalite::{
     assert_export_firrtl, firrtl::ExportOptions, intern::Intern,
-    module::transform::simplify_enums::SimplifyEnumsKind, prelude::*, ty::StaticType,
+    module::transform::simplify_enums::SimplifyEnumsKind, prelude::*, reset::ResetType,
+    ty::StaticType,
 };
 use serde_json::json;
 
@@ -4026,3 +4027,263 @@ circuit check_enum_connect_any:
 ",
     };
 }
+
+#[hdl_module(outline_generated)]
+pub fn check_deduce_resets<T: ResetType>(ty: T) {
+    #[hdl]
+    let cd: ClockDomain<T> = m.input(ClockDomain[ty]);
+    #[hdl]
+    let my_reg = reg_builder().reset(0u8).clock_domain(cd);
+    #[hdl]
+    let u8_in: UInt<8> = m.input();
+    connect(my_reg, u8_in);
+    #[hdl]
+    let u8_out: UInt<8> = m.output();
+    connect(u8_out, my_reg);
+    #[hdl]
+    let enum_in: OneOfThree<Reset, AsyncReset, SyncReset> = m.input();
+    #[hdl]
+    let enum_out: OneOfThree<Reset, AsyncReset, SyncReset> = m.output();
+    #[hdl]
+    let reset_out: Reset = m.output();
+    connect(reset_out, cd.rst.to_reset());
+    #[hdl]
+    match enum_in {
+        OneOfThree::<_, _, _>::A(v) => {
+            connect(
+                enum_out,
+                OneOfThree[Reset][AsyncReset][SyncReset].A(cd.rst.to_reset()),
+            );
+            connect(reset_out, v);
+        }
+        OneOfThree::<_, _, _>::B(v) => {
+            connect(enum_out, OneOfThree[Reset][AsyncReset][SyncReset].B(v))
+        }
+        OneOfThree::<_, _, _>::C(v) => {
+            connect(enum_out, OneOfThree[Reset][AsyncReset][SyncReset].C(v))
+        }
+    }
+}
+
+#[test]
+fn test_deduce_resets() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_deduce_resets(Reset);
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
+        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
+circuit check_deduce_resets:
+    type Ty0 = {clk: Clock, rst: Reset}
+    type Ty1 = {|A: Reset, B: AsyncReset, C: UInt<1>|}
+    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
+        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
+        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
+        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
+        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
+        output reset_out: Reset @[module-XXXXXXXXXX.rs 10:1]
+        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
+        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
+        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
+        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
+        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
+            A(_match_arm_value):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
+                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
+            B(_match_arm_value_1):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
+            C(_match_arm_value_2):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+    fayalite::module::transform::deduce_resets::deduce_resets(m.canonical().intern_sized(), false)
+        .unwrap_err();
+    let m = fayalite::module::transform::deduce_resets::deduce_resets(
+        m.canonical().intern_sized(),
+        true,
+    )
+    .unwrap();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
+        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
+circuit check_deduce_resets:
+    type Ty0 = {clk: Clock, rst: UInt<1>}
+    type Ty1 = {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}
+    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
+        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
+        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
+        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
+        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
+        output reset_out: UInt<1> @[module-XXXXXXXXXX.rs 10:1]
+        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
+        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
+        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
+        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
+        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
+            A(_match_arm_value):
+                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
+                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
+            B(_match_arm_value_1):
+                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
+            C(_match_arm_value_2):
+                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+    let m = check_deduce_resets(SyncReset);
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
+        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
+circuit check_deduce_resets:
+    type Ty0 = {clk: Clock, rst: UInt<1>}
+    type Ty1 = {|A: Reset, B: AsyncReset, C: UInt<1>|}
+    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
+        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
+        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
+        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
+        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
+        output reset_out: Reset @[module-XXXXXXXXXX.rs 10:1]
+        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
+        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
+        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
+        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
+        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
+            A(_match_arm_value):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
+                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
+            B(_match_arm_value_1):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
+            C(_match_arm_value_2):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+    let m = fayalite::module::transform::deduce_resets::deduce_resets(
+        m.canonical().intern_sized(),
+        false,
+    )
+    .unwrap();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
+        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
+circuit check_deduce_resets:
+    type Ty0 = {clk: Clock, rst: UInt<1>}
+    type Ty1 = {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}
+    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
+        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
+        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
+        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
+        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
+        output reset_out: UInt<1> @[module-XXXXXXXXXX.rs 10:1]
+        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
+        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
+        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
+        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
+        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
+            A(_match_arm_value):
+                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
+                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
+            B(_match_arm_value_1):
+                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
+            C(_match_arm_value_2):
+                connect enum_out, {|A: UInt<1>, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+    let m = check_deduce_resets(AsyncReset);
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
+        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
+circuit check_deduce_resets:
+    type Ty0 = {clk: Clock, rst: AsyncReset}
+    type Ty1 = {|A: Reset, B: AsyncReset, C: UInt<1>|}
+    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
+        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
+        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
+        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
+        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
+        output reset_out: Reset @[module-XXXXXXXXXX.rs 10:1]
+        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
+        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
+        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
+        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
+        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
+            A(_match_arm_value):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
+                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
+            B(_match_arm_value_1):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
+            C(_match_arm_value_2):
+                connect enum_out, {|A: Reset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+    let m = fayalite::module::transform::deduce_resets::deduce_resets(
+        m.canonical().intern_sized(),
+        false,
+    )
+    .unwrap();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        options: ExportOptions {
+            simplify_enums: None,
+            ..ExportOptions::default()
+        },
+        "/test/check_deduce_resets.fir": r"FIRRTL version 3.2.0
+circuit check_deduce_resets:
+    type Ty0 = {clk: Clock, rst: AsyncReset}
+    type Ty1 = {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}
+    module check_deduce_resets: @[module-XXXXXXXXXX.rs 1:1]
+        input cd: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input u8_in: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
+        output u8_out: UInt<8> @[module-XXXXXXXXXX.rs 6:1]
+        input enum_in: Ty1 @[module-XXXXXXXXXX.rs 8:1]
+        output enum_out: Ty1 @[module-XXXXXXXXXX.rs 9:1]
+        output reset_out: AsyncReset @[module-XXXXXXXXXX.rs 10:1]
+        regreset my_reg: UInt<8>, cd.clk, cd.rst, UInt<8>(0h0) @[module-XXXXXXXXXX.rs 3:1]
+        connect my_reg, u8_in @[module-XXXXXXXXXX.rs 5:1]
+        connect u8_out, my_reg @[module-XXXXXXXXXX.rs 7:1]
+        connect reset_out, cd.rst @[module-XXXXXXXXXX.rs 11:1]
+        match enum_in: @[module-XXXXXXXXXX.rs 12:1]
+            A(_match_arm_value):
+                connect enum_out, {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}(A, cd.rst) @[module-XXXXXXXXXX.rs 13:1]
+                connect reset_out, _match_arm_value @[module-XXXXXXXXXX.rs 14:1]
+            B(_match_arm_value_1):
+                connect enum_out, {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}(B, _match_arm_value_1) @[module-XXXXXXXXXX.rs 15:1]
+            C(_match_arm_value_2):
+                connect enum_out, {|A: AsyncReset, B: AsyncReset, C: UInt<1>|}(C, _match_arm_value_2) @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+}

From 3abba7f9eb89bf4175d17f7923362f2e15b352f4 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 27 Nov 2024 23:52:07 -0800
Subject: [PATCH 109/190] simulating circuits with deduced resets works

---
 crates/fayalite/src/sim.rs   |  19 ++-
 crates/fayalite/tests/sim.rs | 260 +++++++++++++++++++++++++++++++++++
 2 files changed, 272 insertions(+), 7 deletions(-)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 4780ea2..857ced9 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -16,9 +16,9 @@ use crate::{
     int::BoolOrIntType,
     intern::{Intern, Interned, Memoize},
     module::{
-        AnnotatedModuleIO, Block, Id, InstantiatedModule, ModuleBody, NameId, NormalModuleBody,
-        ScopedNameId, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance,
-        StmtMatch, StmtReg, StmtWire, TargetInInstantiatedModule,
+        transform::deduce_resets::deduce_resets, AnnotatedModuleIO, Block, Id, InstantiatedModule,
+        ModuleBody, NameId, NormalModuleBody, ScopedNameId, Stmt, StmtConnect, StmtDeclaration,
+        StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire, TargetInInstantiatedModule,
     },
     prelude::*,
     sim::{
@@ -1183,6 +1183,7 @@ impl Assignment {
 #[derive(Debug)]
 pub struct Compiler {
     insns: Insns<InsnsBuilding>,
+    original_base_module: Interned<Module<Bundle>>,
     base_module: Interned<Module<Bundle>>,
     modules: HashMap<InstantiatedModule, CompiledModule>,
     compiled_values: HashMap<TargetInInstantiatedModule, CompiledValue<CanonicalType>>,
@@ -1197,8 +1198,12 @@ pub struct Compiler {
 
 impl Compiler {
     pub fn new(base_module: Interned<Module<Bundle>>) -> Self {
+        let original_base_module = base_module;
+        let base_module = deduce_resets(base_module, true)
+            .unwrap_or_else(|e| panic!("failed to deduce reset types: {e}"));
         Self {
             insns: Insns::new(),
+            original_base_module,
             base_module,
             modules: HashMap::new(),
             compiled_values: HashMap::new(),
@@ -1295,7 +1300,7 @@ impl Compiler {
                 flow,
             }
             .into(),
-            CanonicalType::Reset(ty) => todo!(),
+            CanonicalType::Reset(_) => unreachable!(),
             CanonicalType::Clock(ty) => TraceClock {
                 id: self.make_trace_scalar_helper(
                     target,
@@ -2945,10 +2950,10 @@ impl Compiler {
             io: Instance::new_unchecked(
                 ScopedNameId(
                     NameId("<simulator>".intern(), Id::new()),
-                    self.base_module.name_id(),
+                    self.original_base_module.name_id(),
                 ),
-                self.base_module,
-                self.base_module.source_location(),
+                self.original_base_module,
+                self.original_base_module.source_location(),
             ),
             traces: Intern::intern_owned(self.traces),
         }
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 78db49f..606d92b 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -156,6 +156,266 @@ fn test_connect_const() {
     assert_eq!(sim.read_bool_or_int(sim.io().o), UIntValue::from(5u8));
 }
 
+#[hdl_module(outline_generated)]
+pub fn connect_const_reset() {
+    #[hdl]
+    let reset_out: Reset = m.output();
+    #[hdl]
+    let bit_out: Bool = m.output();
+    connect(reset_out, true.to_async_reset().to_reset());
+    connect(bit_out, reset_out.cast_to_static());
+}
+
+#[test]
+fn test_connect_const_reset() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(connect_const_reset());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.settle_step();
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd
+        != r#"$timescale 1 ps $end
+$scope module connect_const_reset $end
+$var wire 1 ! reset_out $end
+$var wire 1 " bit_out $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+1 !
+1 "
+$end
+#1000000
+"# {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug
+        != r#"Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 5,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
+                                ty: AsyncReset,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: AsyncReset,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    value: 1,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
+                    src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
+                    src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Return,
+            ],
+            ..
+        },
+        pc: 5,
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                1,
+                1,
+                1,
+                1,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::connect_const_reset,
+        instantiated: Module {
+            name: connect_const_reset,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::connect_const_reset,
+            instantiated: Module {
+                name: connect_const_reset,
+                ..
+            },
+        }.bit_out: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::connect_const_reset,
+            instantiated: Module {
+                name: connect_const_reset,
+                ..
+            },
+        }.reset_out: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: AsyncReset,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
+                                ty: AsyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "connect_const_reset",
+        children: [
+            TraceModuleIO {
+                name: "reset_out",
+                child: TraceAsyncReset {
+                    id: TraceScalarId(0),
+                    name: "reset_out",
+                    flow: Sink,
+                },
+                ty: AsyncReset,
+                flow: Sink,
+            },
+            TraceModuleIO {
+                name: "bit_out",
+                child: TraceBool {
+                    id: TraceScalarId(1),
+                    name: "bit_out",
+                    flow: Sink,
+                },
+                ty: Bool,
+                flow: Sink,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigAsyncReset {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+    ],
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 1 μs,
+}"# {
+        panic!();
+    }
+    assert_eq!(sim.read_bool_or_int(sim.io().bit_out), true);
+}
+
 #[hdl_module(outline_generated)]
 pub fn mod1_child() {
     #[hdl]

From 965fe530778161b2cfb0d0a27ee4e0768ca57c0c Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 1 Dec 2024 20:08:43 -0800
Subject: [PATCH 110/190] deduce_resets: show more debugging info on assertion
 failure

---
 crates/fayalite/src/module/transform/deduce_resets.rs | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs
index b2d2cb5..fe518a5 100644
--- a/crates/fayalite/src/module/transform/deduce_resets.rs
+++ b/crates/fayalite/src/module/transform/deduce_resets.rs
@@ -770,7 +770,10 @@ impl<'a, P: Pass> PassArgs<'a, P> {
         fallback_error_source_location: Option<SourceLocation>,
     ) -> Result<(), DeduceResetsError> {
         assert_eq!(a.layout, b.layout);
-        assert_eq!(a.ty, b.ty);
+        assert!(
+            a.ty.can_connect(b.ty),
+            "can't connect types! a:\n{a:?}\nb:\n{b:?}"
+        );
         for (a_node_index, b_node_index) in a.node_indexes.into_iter().zip(b.node_indexes) {
             self.state.reset_graph.union(
                 a_node_index,

From 12b3ba57f1b9d53f8cda6c04b91bbebdb49ab637 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 1 Dec 2024 20:10:25 -0800
Subject: [PATCH 111/190] add some ExprCastTo supertraits to ResetType to make
 generic code easier

---
 crates/fayalite/src/reset.rs | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/crates/fayalite/src/reset.rs b/crates/fayalite/src/reset.rs
index b90d40e..9328365 100644
--- a/crates/fayalite/src/reset.rs
+++ b/crates/fayalite/src/reset.rs
@@ -1,8 +1,9 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use crate::{
-    expr::{Expr, ToExpr},
-    int::Bool,
+    clock::Clock,
+    expr::{ops, Expr, ToExpr},
+    int::{Bool, SInt, UInt},
     source_location::SourceLocation,
     ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
 };
@@ -11,7 +12,19 @@ mod sealed {
     pub trait ResetTypeSealed {}
 }
 
-pub trait ResetType: StaticType<MaskType = Bool> + sealed::ResetTypeSealed {
+pub trait ResetType:
+    StaticType<MaskType = Bool>
+    + sealed::ResetTypeSealed
+    + ops::ExprCastTo<Bool>
+    + ops::ExprCastTo<Reset>
+    + ops::ExprCastTo<SyncReset>
+    + ops::ExprCastTo<AsyncReset>
+    + ops::ExprCastTo<Clock>
+    + ops::ExprCastTo<UInt<1>>
+    + ops::ExprCastTo<SInt<1>>
+    + ops::ExprCastTo<UInt>
+    + ops::ExprCastTo<SInt>
+{
     fn dispatch<D: ResetTypeDispatch>(input: D::Input<Self>, dispatch: D) -> D::Output<Self>;
 }
 

From 5e0548db269ddd7a6caed7e0a077478d915905cc Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 1 Dec 2024 20:12:43 -0800
Subject: [PATCH 112/190] vcd: single bit signals have no spaces in their value
 changes

---
 crates/fayalite/src/sim/vcd.rs | 2 +-
 crates/fayalite/tests/sim.rs   | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs
index cbb38b4..b17d839 100644
--- a/crates/fayalite/src/sim/vcd.rs
+++ b/crates/fayalite/src/sim/vcd.rs
@@ -477,7 +477,7 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
     fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
         match value.len() {
             0 => self.writer.write_all(b"s0 ")?,
-            1 => write!(self.writer, "{} ", if value[0] { "1" } else { "0" })?,
+            1 => self.writer.write_all(if value[0] { b"1" } else { b"0" })?,
             _ => {
                 self.writer.write_all(b"b")?;
                 let mut any_ones = false;
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 606d92b..b329603 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -185,8 +185,8 @@ $var wire 1 " bit_out $end
 $upscope $end
 $enddefinitions $end
 $dumpvars
-1 !
-1 "
+1!
+1"
 $end
 #1000000
 "# {

From fd45465d357e0e94ddfdd0e28fbda2c673f6d9bc Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 1 Dec 2024 20:14:13 -0800
Subject: [PATCH 113/190] sim: add support for registers

---
 crates/fayalite/src/sim.rs             |  487 ++++-
 crates/fayalite/src/sim/interpreter.rs |   33 +
 crates/fayalite/tests/sim.rs           | 2481 +++++++++++++++++++++++-
 3 files changed, 2944 insertions(+), 57 deletions(-)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 857ced9..6a18355 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -21,6 +21,7 @@ use crate::{
         StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire, TargetInInstantiatedModule,
     },
     prelude::*,
+    reset::{ResetType, ResetTypeDispatch},
     sim::{
         interpreter::{
             Insn, InsnField, InsnFieldKind, InsnFieldType, Insns, InsnsBuilding, InsnsBuildingDone,
@@ -208,6 +209,14 @@ impl<T: Type> CompiledValue<T> {
     fn write(self) -> (CompiledTypeLayout<T>, TypeIndexRange) {
         self.write.unwrap_or((self.layout, self.range))
     }
+    fn write_value(self) -> Self {
+        let (layout, range) = self.write();
+        Self {
+            layout,
+            range,
+            write: None,
+        }
+    }
     fn map<U: Type>(
         self,
         mut f: impl FnMut(
@@ -1180,6 +1189,29 @@ impl Assignment {
     }
 }
 
+#[derive(Debug)]
+struct RegisterReset {
+    is_async: bool,
+    init: CompiledValue<CanonicalType>,
+    rst: StatePartIndex<StatePartKindSmallSlots>,
+}
+
+#[derive(Debug, Clone, Copy)]
+struct ClockTrigger {
+    last_clk_was_low: StatePartIndex<StatePartKindSmallSlots>,
+    clk: StatePartIndex<StatePartKindSmallSlots>,
+    clk_triggered: StatePartIndex<StatePartKindSmallSlots>,
+    source_location: SourceLocation,
+}
+
+#[derive(Debug)]
+struct Register {
+    value: CompiledValue<CanonicalType>,
+    clk_triggered: StatePartIndex<StatePartKindSmallSlots>,
+    reset: Option<RegisterReset>,
+    source_location: SourceLocation,
+}
+
 #[derive(Debug)]
 pub struct Compiler {
     insns: Insns<InsnsBuilding>,
@@ -1192,7 +1224,12 @@ pub struct Compiler {
     decl_conditions: HashMap<TargetInInstantiatedModule, Interned<[Cond]>>,
     compiled_values_to_dyn_array_indexes:
         HashMap<CompiledValue<UInt>, StatePartIndex<StatePartKindSmallSlots>>,
+    compiled_value_bool_dest_is_small_map:
+        HashMap<CompiledValue<CanonicalType>, StatePartIndex<StatePartKindSmallSlots>>,
     assignments: Assignments,
+    clock_triggers: Vec<ClockTrigger>,
+    compiled_value_to_clock_trigger_map: HashMap<CompiledValue<Clock>, ClockTrigger>,
+    registers: Vec<Register>,
     traces: Vec<SimTrace<()>>,
 }
 
@@ -1211,7 +1248,11 @@ impl Compiler {
             compiled_exprs_to_values: HashMap::new(),
             decl_conditions: HashMap::new(),
             compiled_values_to_dyn_array_indexes: HashMap::new(),
+            compiled_value_bool_dest_is_small_map: HashMap::new(),
             assignments: Assignments::default(),
+            clock_triggers: Vec::new(),
+            compiled_value_to_clock_trigger_map: HashMap::new(),
+            registers: Vec::new(),
             traces: Vec::new(),
         }
     }
@@ -1664,6 +1705,48 @@ impl Compiler {
             .insert(compiled_value, retval);
         retval
     }
+    fn compiled_value_bool_dest_is_small(
+        &mut self,
+        compiled_value: CompiledValue<CanonicalType>,
+        source_location: SourceLocation,
+    ) -> StatePartIndex<StatePartKindSmallSlots> {
+        if let Some(&retval) = self
+            .compiled_value_bool_dest_is_small_map
+            .get(&compiled_value)
+        {
+            return retval;
+        }
+        let retval = match compiled_value.range.len() {
+            TypeLen::A_SMALL_SLOT => compiled_value.range.small_slots.start,
+            TypeLen::A_BIG_SLOT => {
+                let debug_data = SlotDebugData {
+                    name: Interned::default(),
+                    ty: Bool.canonical(),
+                };
+                let dest = self
+                    .insns
+                    .allocate_variable(&TypeLayout {
+                        small_slots: StatePartLayout::scalar(debug_data),
+                        big_slots: StatePartLayout::empty(),
+                    })
+                    .small_slots
+                    .start;
+                self.add_assignment(
+                    Interned::default(),
+                    vec![Insn::IsNonZeroDestIsSmall {
+                        dest,
+                        src: compiled_value.range.big_slots.start,
+                    }],
+                    source_location,
+                );
+                dest
+            }
+            _ => unreachable!(),
+        };
+        self.compiled_value_bool_dest_is_small_map
+            .insert(compiled_value, retval);
+        retval
+    }
     fn compile_expr(
         &mut self,
         instantiated_module: InstantiatedModule,
@@ -2626,6 +2709,125 @@ impl Compiler {
             source_location,
         );
     }
+    fn compile_clock(
+        &mut self,
+        clk: CompiledValue<Clock>,
+        source_location: SourceLocation,
+    ) -> ClockTrigger {
+        if let Some(&retval) = self.compiled_value_to_clock_trigger_map.get(&clk) {
+            return retval;
+        }
+        let mut alloc_small_slot = |part_name: &str| {
+            self.insns
+                .state_layout
+                .ty
+                .small_slots
+                .allocate(&StatePartLayout::scalar(SlotDebugData {
+                    name: Interned::default(),
+                    ty: Bool.canonical(),
+                }))
+                .start
+        };
+        let last_clk_was_low = alloc_small_slot("last_clk_was_low");
+        let clk_triggered = alloc_small_slot("clk_triggered");
+        let retval = ClockTrigger {
+            last_clk_was_low,
+            clk: self.compiled_value_bool_dest_is_small(
+                clk.map_ty(CanonicalType::Clock),
+                source_location,
+            ),
+            clk_triggered,
+            source_location,
+        };
+        self.add_assignment(
+            Interned::default(),
+            [Insn::AndSmall {
+                dest: clk_triggered,
+                lhs: retval.clk,
+                rhs: last_clk_was_low,
+            }],
+            source_location,
+        );
+        self.clock_triggers.push(retval);
+        self.compiled_value_to_clock_trigger_map.insert(clk, retval);
+        retval
+    }
+    fn compile_stmt_reg<R: ResetType>(
+        &mut self,
+        stmt_reg: StmtReg<R>,
+        instantiated_module: InstantiatedModule,
+        value: CompiledValue<CanonicalType>,
+    ) {
+        let StmtReg { annotations, reg } = stmt_reg;
+        let clk = self.compile_expr(instantiated_module, Expr::canonical(reg.clock_domain().clk));
+        let clk = self
+            .compiled_expr_to_value(clk, reg.source_location())
+            .map_ty(Clock::from_canonical);
+        let clk = self.compile_clock(clk, reg.source_location());
+        struct Dispatch;
+        impl ResetTypeDispatch for Dispatch {
+            type Input<T: ResetType> = ();
+
+            type Output<T: ResetType> = bool;
+
+            fn reset(self, _input: Self::Input<Reset>) -> Self::Output<Reset> {
+                unreachable!()
+            }
+
+            fn sync_reset(self, _input: Self::Input<SyncReset>) -> Self::Output<SyncReset> {
+                false
+            }
+
+            fn async_reset(self, _input: Self::Input<AsyncReset>) -> Self::Output<AsyncReset> {
+                true
+            }
+        }
+        let reset = if let Some(init) = reg.init() {
+            let init = self.compile_expr(instantiated_module, init);
+            let init = self.compiled_expr_to_value(init, reg.source_location());
+            let rst =
+                self.compile_expr(instantiated_module, Expr::canonical(reg.clock_domain().rst));
+            let rst = self.compiled_expr_to_value(rst, reg.source_location());
+            let rst = self.compiled_value_bool_dest_is_small(rst, reg.source_location());
+            let is_async = R::dispatch((), Dispatch);
+            if is_async {
+                let cond = Expr::canonical(reg.clock_domain().rst.cast_to(Bool));
+                let cond = self.compile_expr(instantiated_module, cond);
+                let cond = self.compiled_expr_to_value(cond, reg.source_location());
+                let cond = cond.map_ty(Bool::from_canonical);
+                // write to the register's current value since asynchronous reset is combinational
+                let lhs = CompiledValue {
+                    layout: value.layout,
+                    range: value.range,
+                    write: None,
+                }
+                .into();
+                self.compile_simple_connect(
+                    [Cond {
+                        body: CondBody::IfTrue { cond },
+                        source_location: reg.source_location(),
+                    }][..]
+                        .intern(),
+                    lhs,
+                    init,
+                    reg.source_location(),
+                );
+            }
+            Some(RegisterReset {
+                is_async,
+                init,
+                rst,
+            })
+        } else {
+            None
+        };
+        self.registers.push(Register {
+            value,
+            clk_triggered: clk.clk_triggered,
+            reset,
+            source_location: reg.source_location(),
+        });
+    }
     fn compile_declaration(
         &mut self,
         declaration: StmtDeclaration,
@@ -2644,17 +2846,17 @@ impl Compiler {
             target: target_base.into(),
         };
         self.decl_conditions.insert(target, conditions);
-        self.compile_value(target);
+        let compiled_value = self.compile_value(target);
         match declaration {
             StmtDeclaration::Wire(StmtWire { annotations, wire }) => {}
-            StmtDeclaration::Reg(StmtReg { annotations, reg }) => {
-                todo!();
+            StmtDeclaration::Reg(_) => {
+                unreachable!("Reset types were already replaced by SyncReset or AsyncReset");
             }
-            StmtDeclaration::RegSync(StmtReg { annotations, reg }) => {
-                todo!();
+            StmtDeclaration::RegSync(stmt_reg) => {
+                self.compile_stmt_reg(stmt_reg, *parent_module, compiled_value)
             }
-            StmtDeclaration::RegAsync(StmtReg { annotations, reg }) => {
-                todo!();
+            StmtDeclaration::RegAsync(stmt_reg) => {
+                self.compile_stmt_reg(stmt_reg, *parent_module, compiled_value)
             }
             StmtDeclaration::Instance(StmtInstance {
                 annotations,
@@ -2938,10 +3140,109 @@ impl Compiler {
             }
         }
     }
+    fn process_clocks(&mut self) -> Interned<[StatePartIndex<StatePartKindSmallSlots>]> {
+        mem::take(&mut self.clock_triggers)
+            .into_iter()
+            .map(
+                |ClockTrigger {
+                     last_clk_was_low,
+                     clk,
+                     clk_triggered,
+                     source_location,
+                 }| {
+                    self.insns.push(
+                        Insn::NotSmall {
+                            dest: last_clk_was_low,
+                            src: clk,
+                        },
+                        source_location,
+                    );
+                    clk_triggered
+                },
+            )
+            .collect()
+    }
+    fn process_registers(&mut self) {
+        for Register {
+            value,
+            clk_triggered,
+            reset,
+            source_location,
+        } in mem::take(&mut self.registers)
+        {
+            let write_to_current_value = |value_to_write: CompiledValue<CanonicalType>| {
+                let TypeIndexRange {
+                    small_slots,
+                    big_slots,
+                } = value.range;
+                small_slots
+                    .iter()
+                    .zip(value_to_write.range.small_slots.iter())
+                    .map(|(base, src)| Insn::CopySmall { dest: base, src })
+                    .chain(
+                        big_slots
+                            .iter()
+                            .zip(value_to_write.range.big_slots.iter())
+                            .map(|(base, src)| Insn::Copy { dest: base, src }),
+                    )
+            };
+            match reset {
+                Some(RegisterReset {
+                    is_async,
+                    init,
+                    rst,
+                }) => {
+                    let reg_end = self.insns.new_label();
+                    let reg_reset = self.insns.new_label();
+                    let branch_if_reset = Insn::BranchIfSmallNonZero {
+                        target: reg_reset,
+                        value: rst,
+                    };
+                    let branch_if_not_triggered = Insn::BranchIfSmallZero {
+                        target: reg_end,
+                        value: clk_triggered,
+                    };
+                    if is_async {
+                        self.insns.push(branch_if_reset, source_location);
+                        self.insns.push(branch_if_not_triggered, source_location);
+                    } else {
+                        self.insns.push(branch_if_not_triggered, source_location);
+                        self.insns.push(branch_if_reset, source_location);
+                    }
+                    for insn in write_to_current_value(value.write_value()) {
+                        self.insns.push(insn, source_location);
+                    }
+                    self.insns
+                        .push(Insn::Branch { target: reg_end }, source_location);
+                    self.insns.define_label_at_next_insn(reg_reset);
+                    for insn in write_to_current_value(init) {
+                        self.insns.push(insn, source_location);
+                    }
+                    self.insns.define_label_at_next_insn(reg_end);
+                }
+                None => {
+                    let reg_end = self.insns.new_label();
+                    self.insns.push(
+                        Insn::BranchIfSmallZero {
+                            target: reg_end,
+                            value: clk_triggered,
+                        },
+                        source_location,
+                    );
+                    for insn in write_to_current_value(value.write_value()) {
+                        self.insns.push(insn, source_location);
+                    }
+                    self.insns.define_label_at_next_insn(reg_end);
+                }
+            }
+        }
+    }
     pub fn compile(mut self) -> Compiled<Bundle> {
         let base_module =
             *self.compile_module(InstantiatedModule::Base(self.base_module).intern_sized());
         self.process_assignments();
+        self.process_registers();
+        let clocks_triggered = self.process_clocks();
         self.insns
             .push(Insn::Return, self.base_module.source_location());
         Compiled {
@@ -2956,6 +3257,7 @@ impl Compiler {
                 self.original_base_module.source_location(),
             ),
             traces: Intern::intern_owned(self.traces),
+            clocks_triggered,
         }
     }
 }
@@ -2972,6 +3274,7 @@ pub struct Compiled<T: BundleType> {
     base_module: CompiledModule,
     io: Instance<T>,
     traces: Interned<[SimTrace<()>]>,
+    clocks_triggered: Interned<[StatePartIndex<StatePartKindSmallSlots>]>,
 }
 
 impl<T: BundleType> Compiled<T> {
@@ -2984,12 +3287,14 @@ impl<T: BundleType> Compiled<T> {
             base_module,
             io,
             traces,
+            clocks_triggered,
         } = self;
         Compiled {
             insns,
             base_module,
             io: Instance::from_canonical(io.canonical()),
             traces,
+            clocks_triggered,
         }
     }
     pub fn from_canonical(canonical: Compiled<Bundle>) -> Self {
@@ -2998,12 +3303,14 @@ impl<T: BundleType> Compiled<T> {
             base_module,
             io,
             traces,
+            clocks_triggered,
         } = canonical;
         Self {
             insns,
             base_module,
             io: Instance::from_canonical(io.canonical()),
             traces,
+            clocks_triggered,
         }
     }
 }
@@ -3621,6 +3928,7 @@ struct SimulationImpl {
     traces: Box<[SimTrace<BitVec>]>,
     trace_writers: Vec<TraceWriterState<DynTraceWriterDecls>>,
     instant: SimInstant,
+    clocks_triggered: Interned<[StatePartIndex<StatePartKindSmallSlots>]>,
 }
 
 impl SimulationImpl {
@@ -3683,6 +3991,7 @@ impl SimulationImpl {
             )),
             trace_writers: vec![],
             instant: SimInstant::START,
+            clocks_triggered: compiled.clocks_triggered,
         };
         let io_target = Target::from(compiled.io);
         for (BundleField { name, .. }, value) in compiled
@@ -3802,7 +4111,7 @@ impl SimulationImpl {
     }
     #[track_caller]
     fn advance_time(&mut self, duration: SimDuration) {
-        self.settle_step();
+        self.settle();
         self.instant += duration;
         self.for_each_trace_writer_storing_error(|this, mut trace_writer_state| {
             match &mut trace_writer_state {
@@ -3816,37 +4125,43 @@ impl SimulationImpl {
         });
     }
     #[track_caller]
-    fn settle_step(&mut self) {
+    fn settle(&mut self) {
         assert!(
             self.uninitialized_inputs.is_empty(),
             "didn't initialize all inputs",
         );
-        if !self.needs_settle {
-            return;
+        for _ in 0..100000 {
+            if !self.needs_settle {
+                return;
+            }
+            self.state.setup_call(0);
+            self.state.run();
+            if self.made_initial_step {
+                self.read_traces::<false>();
+            } else {
+                self.read_traces::<true>();
+            }
+            self.made_initial_step = true;
+            self.needs_settle = self
+                .clocks_triggered
+                .iter()
+                .any(|i| self.state.small_slots[*i] != 0);
+            self.for_each_trace_writer_storing_error(|this, trace_writer_state| {
+                Ok(match trace_writer_state {
+                    TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running(
+                        this.init_trace_writer(trace_writer_decls.write_decls(this.trace_decls)?)?,
+                    ),
+                    TraceWriterState::Init(trace_writer) => {
+                        TraceWriterState::Running(this.init_trace_writer(trace_writer)?)
+                    }
+                    TraceWriterState::Running(trace_writer) => {
+                        TraceWriterState::Running(this.update_trace_writer(trace_writer)?)
+                    }
+                    TraceWriterState::Errored(e) => TraceWriterState::Errored(e),
+                })
+            });
         }
-        self.state.setup_call(0);
-        self.state.run();
-        if self.made_initial_step {
-            self.read_traces::<false>();
-        } else {
-            self.read_traces::<true>();
-        }
-        self.made_initial_step = true;
-        self.needs_settle = false;
-        self.for_each_trace_writer_storing_error(|this, trace_writer_state| {
-            Ok(match trace_writer_state {
-                TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running(
-                    this.init_trace_writer(trace_writer_decls.write_decls(this.trace_decls)?)?,
-                ),
-                TraceWriterState::Init(trace_writer) => {
-                    TraceWriterState::Running(this.init_trace_writer(trace_writer)?)
-                }
-                TraceWriterState::Running(trace_writer) => {
-                    TraceWriterState::Running(this.update_trace_writer(trace_writer)?)
-                }
-                TraceWriterState::Errored(e) => TraceWriterState::Errored(e),
-            })
-        });
+        panic!("settle(): took too many steps");
     }
     #[track_caller]
     fn get_io(&self, target: Target) -> CompiledValue<CanonicalType> {
@@ -3861,13 +4176,13 @@ impl SimulationImpl {
         panic!("simulator read/write expression must not have dynamic array indexes");
     }
     #[track_caller]
-    fn read_bool_or_int<I: BoolOrIntType>(&mut self, io: Expr<I>) -> I::Value {
+    fn read_helper(&mut self, io: Expr<CanonicalType>) -> CompiledValue<CanonicalType> {
         let Some(target) = io.target() else {
             panic!("can't read from expression that's not a field/element of `Simulation::io()`");
         };
         let compiled_value = self.get_io(*target);
         if self.made_initial_step {
-            self.settle_step();
+            self.settle();
         } else {
             match target.flow() {
                 Flow::Source => {
@@ -3881,6 +4196,56 @@ impl SimulationImpl {
                 Flow::Duplex => unreachable!(),
             }
         }
+        compiled_value
+    }
+    #[track_caller]
+    fn write_helper(&mut self, io: Expr<CanonicalType>) -> CompiledValue<CanonicalType> {
+        let Some(target) = io.target() else {
+            panic!("can't write to an expression that's not a field/element of `Simulation::io()`");
+        };
+        let compiled_value = self.get_io(*target);
+        match target.flow() {
+            Flow::Source => {
+                panic!("can't write to an output");
+            }
+            Flow::Sink => {}
+            Flow::Duplex => unreachable!(),
+        }
+        if !self.made_initial_step {
+            self.uninitialized_inputs.remove(&*target);
+        }
+        self.needs_settle = true;
+        compiled_value
+    }
+    #[track_caller]
+    fn read_bit(&mut self, io: Expr<CanonicalType>) -> bool {
+        let compiled_value = self.read_helper(Expr::canonical(io));
+        match compiled_value.range.len() {
+            TypeLen::A_SMALL_SLOT => {
+                self.state.small_slots[compiled_value.range.small_slots.start] != 0
+            }
+            TypeLen::A_BIG_SLOT => !self.state.big_slots[compiled_value.range.big_slots.start]
+                .clone()
+                .is_zero(),
+            _ => unreachable!(),
+        }
+    }
+    #[track_caller]
+    fn write_bit(&mut self, io: Expr<CanonicalType>, value: bool) {
+        let compiled_value = self.write_helper(io);
+        match compiled_value.range.len() {
+            TypeLen::A_SMALL_SLOT => {
+                self.state.small_slots[compiled_value.range.small_slots.start] = value as _;
+            }
+            TypeLen::A_BIG_SLOT => {
+                self.state.big_slots[compiled_value.range.big_slots.start] = value.into()
+            }
+            _ => unreachable!(),
+        }
+    }
+    #[track_caller]
+    fn read_bool_or_int<I: BoolOrIntType>(&mut self, io: Expr<I>) -> I::Value {
+        let compiled_value = self.read_helper(Expr::canonical(io));
         match compiled_value.range.len() {
             TypeLen::A_SMALL_SLOT => Expr::ty(io).value_from_int_wrapping(
                 self.state.small_slots[compiled_value.range.small_slots.start],
@@ -3893,22 +4258,8 @@ impl SimulationImpl {
     }
     #[track_caller]
     fn write_bool_or_int<I: BoolOrIntType>(&mut self, io: Expr<I>, value: I::Value) {
-        let Some(target) = io.target() else {
-            panic!("can't write to an expression that's not a field/element of `Simulation::io()`");
-        };
-        let compiled_value = self.get_io(*target);
-        match target.flow() {
-            Flow::Source => {
-                panic!("can't write to an output");
-            }
-            Flow::Sink => {}
-            Flow::Duplex => unreachable!(),
-        }
+        let compiled_value = self.write_helper(Expr::canonical(io));
         let value: BigInt = value.into();
-        if !self.made_initial_step {
-            self.uninitialized_inputs.remove(&*target);
-        }
-        self.needs_settle = true;
         match compiled_value.range.len() {
             TypeLen::A_SMALL_SLOT => {
                 self.state.small_slots[compiled_value.range.small_slots.start] =
@@ -3985,13 +4336,13 @@ impl SimulationImpl {
     }
     fn close(mut self) -> std::io::Result<()> {
         if self.made_initial_step {
-            self.settle_step();
+            self.settle();
         }
         self.close_all_trace_writers()
     }
     fn flush_traces(&mut self) -> std::io::Result<()> {
         if self.made_initial_step {
-            self.settle_step();
+            self.settle();
         }
         self.for_each_trace_writer_getting_error(
             |this, trace_writer: TraceWriterState<DynTraceWriterDecls>| match trace_writer {
@@ -4082,6 +4433,7 @@ impl<T: BundleType> fmt::Debug for Simulation<T> {
                     traces,
                     trace_writers,
                     instant,
+                    clocks_triggered,
                 },
             io,
         } = self;
@@ -4099,6 +4451,7 @@ impl<T: BundleType> fmt::Debug for Simulation<T> {
             .field("traces", traces)
             .field("trace_writers", trace_writers)
             .field("instant", instant)
+            .field("clocks_triggered", clocks_triggered)
             .finish()
     }
 }
@@ -4143,8 +4496,8 @@ impl<T: BundleType> Simulation<T> {
         }
     }
     #[track_caller]
-    pub fn settle_step(&mut self) {
-        self.sim_impl.settle_step();
+    pub fn settle(&mut self) {
+        self.sim_impl.settle();
     }
     #[track_caller]
     pub fn advance_time(&mut self, duration: SimDuration) {
@@ -4168,4 +4521,28 @@ impl<T: BundleType> Simulation<T> {
         self.sim_impl
             .write_bool_or_int(io, I::bits_to_value(Cow::Borrowed(&value)));
     }
+    #[track_caller]
+    pub fn write_clock(&mut self, io: Expr<Clock>, value: bool) {
+        self.sim_impl.write_bit(Expr::canonical(io), value);
+    }
+    #[track_caller]
+    pub fn read_clock(&mut self, io: Expr<Clock>) -> bool {
+        self.sim_impl.read_bit(Expr::canonical(io))
+    }
+    #[track_caller]
+    pub fn write_bool(&mut self, io: Expr<Bool>, value: bool) {
+        self.sim_impl.write_bit(Expr::canonical(io), value);
+    }
+    #[track_caller]
+    pub fn read_bool(&mut self, io: Expr<Bool>) -> bool {
+        self.sim_impl.read_bit(Expr::canonical(io))
+    }
+    #[track_caller]
+    pub fn write_reset<R: ResetType>(&mut self, io: Expr<R>, value: bool) {
+        self.sim_impl.write_bit(Expr::canonical(io), value);
+    }
+    #[track_caller]
+    pub fn read_reset<R: ResetType>(&mut self, io: Expr<R>) -> bool {
+        self.sim_impl.read_bit(Expr::canonical(io))
+    }
 }
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index 5ef2fbc..643b604 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -2201,6 +2201,17 @@ impl_insns! {
         state.small_slots[dest] = value;
         next!();
     }
+    IsNonZeroDestIsSmall {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindBigSlots>,
+    } => {
+        let src = &state.big_slots[src];
+        let value = !src.is_zero();
+        state.small_slots[dest] = value as SmallUInt;
+        next!();
+    }
     CastToSInt {
         #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,
@@ -2237,6 +2248,18 @@ impl_insns! {
         state.big_slots[dest] = value;
         next!();
     }
+    AndSmall {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        rhs: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let value = state.small_slots[lhs] & state.small_slots[rhs];
+        state.small_slots[dest] = value;
+        next!();
+    }
     Or {
         #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,
@@ -2283,6 +2306,16 @@ impl_insns! {
         state.big_slots[dest] = value;
         next!();
     }
+    NotSmall {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let value = !state.small_slots[src];
+        state.small_slots[dest] = value;
+        next!();
+    }
     Neg {
         #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index b329603..f34bb89 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -3,6 +3,7 @@
 use fayalite::{
     int::UIntValue,
     prelude::*,
+    reset::ResetType,
     sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
     util::RcWriter,
 };
@@ -18,7 +19,7 @@ pub fn connect_const() {
 fn test_connect_const() {
     let _n = SourceLocation::normalize_files_for_tests();
     let mut sim = Simulation::new(connect_const());
-    sim.settle_step();
+    sim.settle();
     let sim_debug = format!("{sim:#?}");
     println!("#######\n{sim_debug}\n#######");
     if sim_debug
@@ -150,6 +151,7 @@ fn test_connect_const() {
     ],
     trace_writers: [],
     instant: 0 s,
+    clocks_triggered: [],
 }"# {
         panic!();
     }
@@ -172,7 +174,7 @@ fn test_connect_const_reset() {
     let mut sim = Simulation::new(connect_const_reset());
     let mut writer = RcWriter::default();
     sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
-    sim.settle_step();
+    sim.settle();
     sim.advance_time(SimDuration::from_micros(1));
     sim.flush_traces().unwrap();
     let vcd = String::from_utf8(writer.take()).unwrap();
@@ -410,6 +412,7 @@ $end
         ),
     ],
     instant: 1 μs,
+    clocks_triggered: [],
 }"# {
         panic!();
     }
@@ -1308,6 +1311,7 @@ b1111 ,
         ),
     ],
     instant: 2 μs,
+    clocks_triggered: [],
 }"# {
         panic!();
     }
@@ -1316,3 +1320,2476 @@ b1111 ,
     let expected = 0xF_hdl_u4;
     assert_eq!(sim.read_bool_or_int(sim.io().o.o2).to_expr(), expected);
 }
+
+#[hdl_module(outline_generated)]
+pub fn counter<R: ResetType>() {
+    #[hdl]
+    let cd: ClockDomain<R> = m.input();
+    #[hdl]
+    let count_reg: UInt<4> = reg_builder().clock_domain(cd).reset(3_hdl_u4);
+    connect_any(count_reg, count_reg + 1_hdl_u1);
+    #[hdl]
+    let count: UInt<4> = m.output();
+    connect(count, count_reg);
+}
+
+#[hdl]
+#[test]
+fn test_counter_sync() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(counter::<SyncReset>());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.write_clock(sim.io().cd.clk, true);
+    sim.settle();
+    let reset_value = 3_hdl_u4;
+    assert_eq!(
+        reset_value,
+        sim.read_bool_or_int(sim.io().count).to_expr(),
+        "vcd:\n{}",
+        String::from_utf8(writer.take()).unwrap(),
+    );
+    sim.write_reset(sim.io().cd.rst, false);
+    sim.advance_time(SimDuration::from_micros(1));
+    for i in 0..32u32 {
+        assert_eq!(
+            UInt::<4>::new_static().from_int_wrapping(i + 3),
+            sim.read_bool_or_int(sim.io().count),
+            "vcd:\n{}",
+            String::from_utf8(writer.take()).unwrap(),
+        );
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(SimDuration::from_micros(1));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd
+        != r#"$timescale 1 ps $end
+$scope module counter $end
+$scope struct cd $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$upscope $end
+$var wire 4 # count $end
+$var reg 4 $ count_reg $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+1"
+b0 #
+b0 $
+$end
+#1000000
+1!
+b11 $
+b11 #
+0"
+#2000000
+0!
+#3000000
+1!
+b100 $
+b100 #
+#4000000
+0!
+#5000000
+1!
+b101 $
+b101 #
+#6000000
+0!
+#7000000
+1!
+b110 $
+b110 #
+#8000000
+0!
+#9000000
+1!
+b111 $
+b111 #
+#10000000
+0!
+#11000000
+1!
+b1000 $
+b1000 #
+#12000000
+0!
+#13000000
+1!
+b1001 $
+b1001 #
+#14000000
+0!
+#15000000
+1!
+b1010 $
+b1010 #
+#16000000
+0!
+#17000000
+1!
+b1011 $
+b1011 #
+#18000000
+0!
+#19000000
+1!
+b1100 $
+b1100 #
+#20000000
+0!
+#21000000
+1!
+b1101 $
+b1101 #
+#22000000
+0!
+#23000000
+1!
+b1110 $
+b1110 #
+#24000000
+0!
+#25000000
+1!
+b1111 $
+b1111 #
+#26000000
+0!
+#27000000
+1!
+b0 $
+b0 #
+#28000000
+0!
+#29000000
+1!
+b1 $
+b1 #
+#30000000
+0!
+#31000000
+1!
+b10 $
+b10 #
+#32000000
+0!
+#33000000
+1!
+b11 $
+b11 #
+#34000000
+0!
+#35000000
+1!
+b100 $
+b100 #
+#36000000
+0!
+#37000000
+1!
+b101 $
+b101 #
+#38000000
+0!
+#39000000
+1!
+b110 $
+b110 #
+#40000000
+0!
+#41000000
+1!
+b111 $
+b111 #
+#42000000
+0!
+#43000000
+1!
+b1000 $
+b1000 #
+#44000000
+0!
+#45000000
+1!
+b1001 $
+b1001 #
+#46000000
+0!
+#47000000
+1!
+b1010 $
+b1010 #
+#48000000
+0!
+#49000000
+1!
+b1011 $
+b1011 #
+#50000000
+0!
+#51000000
+1!
+b1100 $
+b1100 #
+#52000000
+0!
+#53000000
+1!
+b1101 $
+b1101 #
+#54000000
+0!
+#55000000
+1!
+b1110 $
+b1110 #
+#56000000
+0!
+#57000000
+1!
+b1111 $
+b1111 #
+#58000000
+0!
+#59000000
+1!
+b0 $
+b0 #
+#60000000
+0!
+#61000000
+1!
+b1 $
+b1 #
+#62000000
+0!
+#63000000
+1!
+b10 $
+b10 #
+#64000000
+0!
+#65000000
+1!
+b11 $
+b11 #
+#66000000
+"# {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug
+        != r#"Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 4,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 9,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count_reg",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count_reg$next",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<5>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:6:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
+                    value: 1,
+                },
+                Add {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
+                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
+                },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
+                    dest_width: 4,
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
+                    value: 3,
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
+                },
+                AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallZero {
+                    target: 14,
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallNonZero {
+                    target: 13,
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                },
+                Branch {
+                    target: 14,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                NotSmall {
+                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Return,
+            ],
+            ..
+        },
+        pc: 15,
+        small_slots: StatePart {
+            value: [
+                18446744073709551614,
+                0,
+                1,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                0,
+                3,
+                3,
+                4,
+                3,
+                1,
+                4,
+                4,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::counter,
+        instantiated: Module {
+            name: counter,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.cd: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: SyncReset,
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
+                                ty: SyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Clock,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Clock,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: SyncReset,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: SyncReset,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.cd.clk: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.cd.rst: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: SyncReset,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: SyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.count: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<4>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "counter",
+        children: [
+            TraceModuleIO {
+                name: "cd",
+                child: TraceBundle {
+                    name: "cd",
+                    fields: [
+                        TraceClock {
+                            id: TraceScalarId(0),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceSyncReset {
+                            id: TraceScalarId(1),
+                            name: "rst",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        rst: SyncReset,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: SyncReset,
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "count",
+                child: TraceUInt {
+                    id: TraceScalarId(2),
+                    name: "count",
+                    ty: UInt<4>,
+                    flow: Sink,
+                },
+                ty: UInt<4>,
+                flow: Sink,
+            },
+            TraceReg {
+                name: "count_reg",
+                child: TraceUInt {
+                    id: TraceScalarId(3),
+                    name: "count_reg",
+                    ty: UInt<4>,
+                    flow: Duplex,
+                },
+                ty: UInt<4>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigSyncReset {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(2),
+                ty: UInt<4>,
+            },
+            state: 0x3,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<4>,
+            },
+            state: 0x3,
+            last_state: 0x3,
+        },
+    ],
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 66 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+    ],
+}"# {
+        panic!();
+    }
+}
+
+#[hdl]
+#[test]
+fn test_counter_async() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(counter::<AsyncReset>());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, false);
+    sim.advance_time(SimDuration::from_nanos(500));
+    sim.write_reset(sim.io().cd.rst, true);
+    let reset_value = 3_hdl_u4;
+    assert_eq!(
+        reset_value,
+        sim.read_bool_or_int(sim.io().count).to_expr(),
+        "vcd:\n{}",
+        String::from_utf8(writer.take()).unwrap(),
+    );
+    sim.advance_time(SimDuration::from_nanos(500));
+    sim.write_clock(sim.io().cd.clk, true);
+    sim.advance_time(SimDuration::from_nanos(500));
+    sim.write_reset(sim.io().cd.rst, false);
+    sim.advance_time(SimDuration::from_nanos(500));
+    for i in 0..32u32 {
+        assert_eq!(
+            UInt::<4>::new_static().from_int_wrapping(i + 3),
+            sim.read_bool_or_int(sim.io().count),
+            "vcd:\n{}",
+            String::from_utf8(writer.take()).unwrap(),
+        );
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(SimDuration::from_micros(1));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd
+        != r#"$timescale 1 ps $end
+$scope module counter $end
+$scope struct cd $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$upscope $end
+$var wire 4 # count $end
+$var reg 4 $ count_reg $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+0"
+b0 #
+b0 $
+$end
+#500000
+1"
+b11 #
+b11 $
+#1000000
+1!
+#1500000
+0"
+#2000000
+0!
+#3000000
+1!
+b100 $
+b100 #
+#4000000
+0!
+#5000000
+1!
+b101 $
+b101 #
+#6000000
+0!
+#7000000
+1!
+b110 $
+b110 #
+#8000000
+0!
+#9000000
+1!
+b111 $
+b111 #
+#10000000
+0!
+#11000000
+1!
+b1000 $
+b1000 #
+#12000000
+0!
+#13000000
+1!
+b1001 $
+b1001 #
+#14000000
+0!
+#15000000
+1!
+b1010 $
+b1010 #
+#16000000
+0!
+#17000000
+1!
+b1011 $
+b1011 #
+#18000000
+0!
+#19000000
+1!
+b1100 $
+b1100 #
+#20000000
+0!
+#21000000
+1!
+b1101 $
+b1101 #
+#22000000
+0!
+#23000000
+1!
+b1110 $
+b1110 #
+#24000000
+0!
+#25000000
+1!
+b1111 $
+b1111 #
+#26000000
+0!
+#27000000
+1!
+b0 $
+b0 #
+#28000000
+0!
+#29000000
+1!
+b1 $
+b1 #
+#30000000
+0!
+#31000000
+1!
+b10 $
+b10 #
+#32000000
+0!
+#33000000
+1!
+b11 $
+b11 #
+#34000000
+0!
+#35000000
+1!
+b100 $
+b100 #
+#36000000
+0!
+#37000000
+1!
+b101 $
+b101 #
+#38000000
+0!
+#39000000
+1!
+b110 $
+b110 #
+#40000000
+0!
+#41000000
+1!
+b111 $
+b111 #
+#42000000
+0!
+#43000000
+1!
+b1000 $
+b1000 #
+#44000000
+0!
+#45000000
+1!
+b1001 $
+b1001 #
+#46000000
+0!
+#47000000
+1!
+b1010 $
+b1010 #
+#48000000
+0!
+#49000000
+1!
+b1011 $
+b1011 #
+#50000000
+0!
+#51000000
+1!
+b1100 $
+b1100 #
+#52000000
+0!
+#53000000
+1!
+b1101 $
+b1101 #
+#54000000
+0!
+#55000000
+1!
+b1110 $
+b1110 #
+#56000000
+0!
+#57000000
+1!
+b1111 $
+b1111 #
+#58000000
+0!
+#59000000
+1!
+b0 $
+b0 #
+#60000000
+0!
+#61000000
+1!
+b1 $
+b1 #
+#62000000
+0!
+#63000000
+1!
+b10 $
+b10 #
+#64000000
+0!
+#65000000
+1!
+b11 $
+b11 #
+#66000000
+"# {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug
+        != r#"Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 4,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 10,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
+                                ty: AsyncReset,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count_reg",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count_reg$next",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<5>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
+                    value: 1,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
+                    value: 3,
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                BranchIfZero {
+                    target: 6,
+                    value: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Add {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
+                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
+                },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
+                    dest_width: 4,
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
+                },
+                AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallNonZero {
+                    target: 16,
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallZero {
+                    target: 17,
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                },
+                Branch {
+                    target: 17,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                NotSmall {
+                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Return,
+            ],
+            ..
+        },
+        pc: 18,
+        small_slots: StatePart {
+            value: [
+                18446744073709551614,
+                0,
+                1,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                0,
+                3,
+                3,
+                4,
+                3,
+                0,
+                1,
+                4,
+                4,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::counter,
+        instantiated: Module {
+            name: counter,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.cd: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: AsyncReset,
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
+                                ty: AsyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Clock,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Clock,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: AsyncReset,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: AsyncReset,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.cd.clk: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.cd.rst: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: AsyncReset,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: AsyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.count: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<4>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "counter",
+        children: [
+            TraceModuleIO {
+                name: "cd",
+                child: TraceBundle {
+                    name: "cd",
+                    fields: [
+                        TraceClock {
+                            id: TraceScalarId(0),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceAsyncReset {
+                            id: TraceScalarId(1),
+                            name: "rst",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        rst: AsyncReset,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: AsyncReset,
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "count",
+                child: TraceUInt {
+                    id: TraceScalarId(2),
+                    name: "count",
+                    ty: UInt<4>,
+                    flow: Sink,
+                },
+                ty: UInt<4>,
+                flow: Sink,
+            },
+            TraceReg {
+                name: "count_reg",
+                child: TraceUInt {
+                    id: TraceScalarId(3),
+                    name: "count_reg",
+                    ty: UInt<4>,
+                    flow: Duplex,
+                },
+                ty: UInt<4>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigAsyncReset {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(2),
+                ty: UInt<4>,
+            },
+            state: 0x3,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<4>,
+            },
+            state: 0x3,
+            last_state: 0x3,
+        },
+    ],
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 66 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+    ],
+}"# {
+        panic!();
+    }
+}
+
+#[hdl_module(outline_generated)]
+pub fn shift_register() {
+    #[hdl]
+    let cd: ClockDomain<SyncReset> = m.input();
+    #[hdl]
+    let d: Bool = m.input();
+    #[hdl]
+    let q: Bool = m.output();
+    #[hdl]
+    let reg0: Bool = reg_builder().clock_domain(cd).reset(false);
+    connect(reg0, d);
+    #[hdl]
+    let reg1: Bool = reg_builder().clock_domain(cd).reset(false);
+    connect(reg1, reg0);
+    #[hdl]
+    let reg2: Bool = reg_builder().clock_domain(cd).reset(false);
+    connect(reg2, reg1);
+    #[hdl]
+    let reg3: Bool = reg_builder().clock_domain(cd).reset(false);
+    connect(reg3, reg2);
+    connect(q, reg3);
+}
+
+#[hdl]
+#[test]
+fn test_shift_register() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(shift_register());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
+    sim.write_bool(sim.io().d, false);
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.write_clock(sim.io().cd.clk, true);
+    sim.advance_time(SimDuration::from_nanos(100));
+    sim.write_reset(sim.io().cd.rst, false);
+    sim.advance_time(SimDuration::from_nanos(900));
+    let data = [
+        false, true, true, false, false, true, false, true, true, true, true,
+    ];
+    for cycle in 0..32usize {
+        if let Some(out_cycle) = cycle.checked_sub(4) {
+            if let Some(expected) = data.get(out_cycle) {
+                assert_eq!(
+                    *expected,
+                    sim.read_bool(sim.io().q),
+                    "cycle: {cycle}\nvcd:\n{}",
+                    String::from_utf8(writer.take()).unwrap(),
+                );
+            }
+        }
+        sim.write_bool(sim.io().d, data.get(cycle).copied().unwrap_or(false));
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(SimDuration::from_micros(1));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd
+        != r#"$timescale 1 ps $end
+$scope module shift_register $end
+$scope struct cd $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$upscope $end
+$var wire 1 # d $end
+$var wire 1 $ q $end
+$var reg 1 % reg0 $end
+$var reg 1 & reg1 $end
+$var reg 1 ' reg2 $end
+$var reg 1 ( reg3 $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+1"
+0#
+0$
+0%
+0&
+0'
+0(
+$end
+#1000000
+1!
+#1100000
+0"
+#2000000
+0!
+#3000000
+1!
+#4000000
+0!
+1#
+#5000000
+1!
+1%
+#6000000
+0!
+#7000000
+1!
+1&
+#8000000
+0!
+0#
+#9000000
+1!
+0%
+1'
+#10000000
+0!
+#11000000
+1!
+0&
+1(
+1$
+#12000000
+0!
+1#
+#13000000
+1!
+1%
+0'
+#14000000
+0!
+0#
+#15000000
+1!
+0%
+1&
+0(
+0$
+#16000000
+0!
+1#
+#17000000
+1!
+1%
+0&
+1'
+#18000000
+0!
+#19000000
+1!
+1&
+0'
+1(
+1$
+#20000000
+0!
+#21000000
+1!
+1'
+0(
+0$
+#22000000
+0!
+#23000000
+1!
+1(
+1$
+#24000000
+0!
+0#
+#25000000
+1!
+0%
+#26000000
+0!
+#27000000
+1!
+0&
+#28000000
+0!
+#29000000
+1!
+0'
+#30000000
+0!
+#31000000
+1!
+0(
+0$
+#32000000
+0!
+#33000000
+1!
+#34000000
+0!
+#35000000
+1!
+#36000000
+0!
+#37000000
+1!
+#38000000
+0!
+#39000000
+1!
+#40000000
+0!
+#41000000
+1!
+#42000000
+0!
+#43000000
+1!
+#44000000
+0!
+#45000000
+1!
+#46000000
+0!
+#47000000
+1!
+#48000000
+0!
+#49000000
+1!
+#50000000
+0!
+#51000000
+1!
+#52000000
+0!
+#53000000
+1!
+#54000000
+0!
+#55000000
+1!
+#56000000
+0!
+#57000000
+1!
+#58000000
+0!
+#59000000
+1!
+#60000000
+0!
+#61000000
+1!
+#62000000
+0!
+#63000000
+1!
+#64000000
+0!
+#65000000
+1!
+#66000000
+"# {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug
+        != r#"Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 4,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 13,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:13:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
+                    src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:12:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                    value: 0,
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
+                },
+                AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallZero {
+                    target: 14,
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallNonZero {
+                    target: 13,
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
+                },
+                Branch {
+                    target: 14,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:7:1
+                BranchIfSmallZero {
+                    target: 19,
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallNonZero {
+                    target: 18,
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
+                },
+                Branch {
+                    target: 19,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                BranchIfSmallZero {
+                    target: 24,
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallNonZero {
+                    target: 23,
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
+                },
+                Branch {
+                    target: 24,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                BranchIfSmallZero {
+                    target: 29,
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallNonZero {
+                    target: 28,
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                    src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
+                },
+                Branch {
+                    target: 29,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                NotSmall {
+                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Return,
+            ],
+            ..
+        },
+        pc: 30,
+        small_slots: StatePart {
+            value: [
+                18446744073709551614,
+                0,
+                1,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::shift_register,
+        instantiated: Module {
+            name: shift_register,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::shift_register,
+            instantiated: Module {
+                name: shift_register,
+                ..
+            },
+        }.cd: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: SyncReset,
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
+                                ty: SyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Clock,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Clock,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: SyncReset,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: SyncReset,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::shift_register,
+            instantiated: Module {
+                name: shift_register,
+                ..
+            },
+        }.cd.clk: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::shift_register,
+            instantiated: Module {
+                name: shift_register,
+                ..
+            },
+        }.cd.rst: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: SyncReset,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: SyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::shift_register,
+            instantiated: Module {
+                name: shift_register,
+                ..
+            },
+        }.d: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::shift_register,
+            instantiated: Module {
+                name: shift_register,
+                ..
+            },
+        }.q: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "shift_register",
+        children: [
+            TraceModuleIO {
+                name: "cd",
+                child: TraceBundle {
+                    name: "cd",
+                    fields: [
+                        TraceClock {
+                            id: TraceScalarId(0),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceSyncReset {
+                            id: TraceScalarId(1),
+                            name: "rst",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        rst: SyncReset,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: SyncReset,
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "d",
+                child: TraceBool {
+                    id: TraceScalarId(2),
+                    name: "d",
+                    flow: Source,
+                },
+                ty: Bool,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "q",
+                child: TraceBool {
+                    id: TraceScalarId(3),
+                    name: "q",
+                    flow: Sink,
+                },
+                ty: Bool,
+                flow: Sink,
+            },
+            TraceReg {
+                name: "reg0",
+                child: TraceBool {
+                    id: TraceScalarId(4),
+                    name: "reg0",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+            TraceReg {
+                name: "reg1",
+                child: TraceBool {
+                    id: TraceScalarId(5),
+                    name: "reg1",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+            TraceReg {
+                name: "reg2",
+                child: TraceBool {
+                    id: TraceScalarId(6),
+                    name: "reg2",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+            TraceReg {
+                name: "reg3",
+                child: TraceBool {
+                    id: TraceScalarId(7),
+                    name: "reg3",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigSyncReset {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(3),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(4),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(7),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(9),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(11),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+    ],
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 66 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+    ],
+}"# {
+        panic!();
+    }
+}

From d3f52292a1e0faf86666f877464cf39f085432f3 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 1 Dec 2024 20:21:26 -0800
Subject: [PATCH 114/190] test doc tests in CI

---
 .forgejo/workflows/test.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index fd7be6f..e83c668 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -57,4 +57,5 @@ jobs:
           save-if: ${{ github.ref == 'refs/heads/master' }}
       - run: cargo test
       - run: cargo build --tests --features=unstable-doc
+      - run: cargo test --doc --features=unstable-doc
       - run: cargo doc --features=unstable-doc

From 4422157db8ebab00d0a607deb996c9cd3b577a64 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 2 Dec 2024 21:06:23 -0800
Subject: [PATCH 115/190] WIP adding enums to simulator

---
 crates/fayalite/src/sim.rs             | 161 +++++++++++++++++++++++--
 crates/fayalite/src/sim/interpreter.rs |  29 +++++
 crates/fayalite/src/sim/vcd.rs         |  92 +++++++++++++-
 3 files changed, 269 insertions(+), 13 deletions(-)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 6a18355..3751241 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -5,6 +5,7 @@
 
 use crate::{
     bundle::{BundleField, BundleType},
+    enum_::{EnumType, EnumVariant},
     expr::{
         ops,
         target::{
@@ -36,7 +37,7 @@ use crate::{
     ty::StaticType,
     util::{BitSliceWriteWithBase, DebugAsDisplay},
 };
-use bitvec::{bits, order::Lsb0, slice::BitSlice, vec::BitVec};
+use bitvec::{bits, order::Lsb0, slice::BitSlice, vec::BitVec, view::BitView};
 use hashbrown::{HashMap, HashSet};
 use num_bigint::BigInt;
 use num_traits::{Signed, ToPrimitive, Zero};
@@ -1229,6 +1230,7 @@ pub struct Compiler {
     assignments: Assignments,
     clock_triggers: Vec<ClockTrigger>,
     compiled_value_to_clock_trigger_map: HashMap<CompiledValue<Clock>, ClockTrigger>,
+    enum_discriminants: HashMap<CompiledValue<Enum>, StatePartIndex<StatePartKindSmallSlots>>,
     registers: Vec<Register>,
     traces: Vec<SimTrace<()>>,
 }
@@ -1252,6 +1254,7 @@ impl Compiler {
             assignments: Assignments::default(),
             clock_triggers: Vec::new(),
             compiled_value_to_clock_trigger_map: HashMap::new(),
+            enum_discriminants: HashMap::new(),
             registers: Vec::new(),
             traces: Vec::new(),
         }
@@ -1308,7 +1311,7 @@ impl Compiler {
                 flow,
             }
             .into(),
-            CanonicalType::Bool(ty) => TraceBool {
+            CanonicalType::Bool(_) => TraceBool {
                 id: self.make_trace_scalar_helper(
                     target,
                     |index| SimTraceKind::SmallBool { index },
@@ -1318,10 +1321,27 @@ impl Compiler {
                 flow,
             }
             .into(),
-            CanonicalType::Array(ty) => unreachable!(),
-            CanonicalType::Enum(ty) => todo!(),
-            CanonicalType::Bundle(ty) => unreachable!(),
-            CanonicalType::AsyncReset(ty) => TraceAsyncReset {
+            CanonicalType::Array(_) => unreachable!(),
+            CanonicalType::Enum(ty) => {
+                assert_eq!(ty.discriminant_bit_width(), ty.type_properties().bit_width);
+                let compiled_value = self.compile_value(target);
+                let discriminant = self.compile_enum_discriminant(
+                    compiled_value.map_ty(Enum::from_canonical),
+                    target.target.base().source_location(),
+                );
+                TraceFieldlessEnum {
+                    id: self.new_sim_trace(SimTraceKind::EnumDiscriminant {
+                        index: discriminant,
+                        ty,
+                    }),
+                    name,
+                    ty,
+                    flow,
+                }
+                .into()
+            }
+            CanonicalType::Bundle(_) => unreachable!(),
+            CanonicalType::AsyncReset(_) => TraceAsyncReset {
                 id: self.make_trace_scalar_helper(
                     target,
                     |index| SimTraceKind::SmallAsyncReset { index },
@@ -1331,7 +1351,7 @@ impl Compiler {
                 flow,
             }
             .into(),
-            CanonicalType::SyncReset(ty) => TraceSyncReset {
+            CanonicalType::SyncReset(_) => TraceSyncReset {
                 id: self.make_trace_scalar_helper(
                     target,
                     |index| SimTraceKind::SmallSyncReset { index },
@@ -1342,7 +1362,7 @@ impl Compiler {
             }
             .into(),
             CanonicalType::Reset(_) => unreachable!(),
-            CanonicalType::Clock(ty) => TraceClock {
+            CanonicalType::Clock(_) => TraceClock {
                 id: self.make_trace_scalar_helper(
                     target,
                     |index| SimTraceKind::SmallClock { index },
@@ -1381,7 +1401,13 @@ impl Compiler {
                 }
                 .into()
             }
-            CanonicalType::Enum(ty) => todo!(),
+            CanonicalType::Enum(ty) => {
+                if ty.variants().iter().all(|v| v.ty.is_none()) {
+                    self.make_trace_scalar(target, name)
+                } else {
+                    todo!()
+                }
+            }
             CanonicalType::Bundle(ty) => {
                 let fields = Interned::from_iter(ty.fields().iter().map(|field| {
                     self.make_trace_decl_child(
@@ -2752,6 +2778,71 @@ impl Compiler {
         self.compiled_value_to_clock_trigger_map.insert(clk, retval);
         retval
     }
+    fn compile_enum_discriminant(
+        &mut self,
+        enum_value: CompiledValue<Enum>,
+        source_location: SourceLocation,
+    ) -> StatePartIndex<StatePartKindSmallSlots> {
+        if let Some(&retval) = self.enum_discriminants.get(&enum_value) {
+            return retval;
+        }
+        let retval_ty = Enum::new(
+            enum_value
+                .layout
+                .ty
+                .variants()
+                .iter()
+                .map(|variant| EnumVariant {
+                    name: variant.name,
+                    ty: None,
+                })
+                .collect(),
+        );
+        let retval = if retval_ty == enum_value.layout.ty
+            && enum_value.range.len() == TypeLen::A_SMALL_SLOT
+        {
+            enum_value.range.small_slots.start
+        } else {
+            let retval = self
+                .insns
+                .state_layout
+                .ty
+                .small_slots
+                .allocate(&StatePartLayout::scalar(SlotDebugData {
+                    name: Interned::default(),
+                    ty: retval_ty.canonical(),
+                }))
+                .start;
+            let discriminant_bit_width = enum_value.layout.ty.discriminant_bit_width();
+            let discriminant_mask = !(!0u64 << discriminant_bit_width);
+            let insn = match enum_value.range.len() {
+                TypeLen::A_BIG_SLOT => Insn::AndBigWithSmallImmediate {
+                    dest: retval,
+                    lhs: enum_value.range.big_slots.start,
+                    rhs: discriminant_mask,
+                },
+                TypeLen::A_SMALL_SLOT => {
+                    if discriminant_bit_width == enum_value.layout.ty.type_properties().bit_width {
+                        Insn::CopySmall {
+                            dest: retval,
+                            src: enum_value.range.small_slots.start,
+                        }
+                    } else {
+                        Insn::AndSmallImmediate {
+                            dest: retval,
+                            lhs: enum_value.range.small_slots.start,
+                            rhs: discriminant_mask,
+                        }
+                    }
+                }
+                _ => unreachable!(),
+            };
+            self.add_assignment(Interned::default(), [insn], source_location);
+            retval
+        };
+        self.enum_discriminants.insert(enum_value, retval);
+        retval
+    }
     fn compile_stmt_reg<R: ResetType>(
         &mut self,
         stmt_reg: StmtReg<R>,
@@ -3681,6 +3772,12 @@ pub trait TraceWriter: fmt::Debug + 'static {
     ) -> Result<(), Self::Error> {
         self.set_signal_bool(id, value)
     }
+    fn set_signal_enum_discriminant(
+        &mut self,
+        id: TraceScalarId,
+        variant_index: usize,
+        ty: Enum,
+    ) -> Result<(), Self::Error>;
 }
 
 pub struct DynTraceWriterDecls(Box<dyn TraceWriterDeclsDynTrait>);
@@ -3717,6 +3814,12 @@ trait TraceWriterDynTrait: fmt::Debug + 'static {
     fn set_signal_sync_reset_dyn(&mut self, id: TraceScalarId, value: bool) -> std::io::Result<()>;
     fn set_signal_async_reset_dyn(&mut self, id: TraceScalarId, value: bool)
         -> std::io::Result<()>;
+    fn set_signal_enum_discriminant_dyn(
+        &mut self,
+        id: TraceScalarId,
+        variant_index: usize,
+        ty: Enum,
+    ) -> std::io::Result<()>;
 }
 
 impl<T: TraceWriter> TraceWriterDynTrait for T {
@@ -3754,6 +3857,17 @@ impl<T: TraceWriter> TraceWriterDynTrait for T {
     ) -> std::io::Result<()> {
         Ok(TraceWriter::set_signal_async_reset(self, id, value).map_err(err_into_io)?)
     }
+    fn set_signal_enum_discriminant_dyn(
+        &mut self,
+        id: TraceScalarId,
+        variant_index: usize,
+        ty: Enum,
+    ) -> std::io::Result<()> {
+        Ok(
+            TraceWriter::set_signal_enum_discriminant(self, id, variant_index, ty)
+                .map_err(err_into_io)?,
+        )
+    }
 }
 
 pub struct DynTraceWriter(Box<dyn TraceWriterDynTrait>);
@@ -3800,6 +3914,15 @@ impl TraceWriter for DynTraceWriter {
     ) -> Result<(), Self::Error> {
         self.0.set_signal_async_reset_dyn(id, value)
     }
+    fn set_signal_enum_discriminant(
+        &mut self,
+        id: TraceScalarId,
+        variant_index: usize,
+        ty: Enum,
+    ) -> Result<(), Self::Error> {
+        self.0
+            .set_signal_enum_discriminant_dyn(id, variant_index, ty)
+    }
 }
 
 #[derive(Debug)]
@@ -3894,6 +4017,10 @@ enum SimTraceKind {
     SmallClock {
         index: StatePartIndex<StatePartKindSmallSlots>,
     },
+    EnumDiscriminant {
+        index: StatePartIndex<StatePartKindSmallSlots>,
+        ty: Enum,
+    },
 }
 
 impl SimTraceKind {
@@ -3913,6 +4040,9 @@ impl SimTraceKind {
             | SimTraceKind::SmallAsyncReset { index: _ }
             | SimTraceKind::SmallSyncReset { index: _ }
             | SimTraceKind::SmallClock { index: _ } => BitVec::repeat(false, 1),
+            SimTraceKind::EnumDiscriminant { index: _, ty } => {
+                BitVec::repeat(false, ty.discriminant_bit_width())
+            }
         }
     }
 }
@@ -4042,6 +4172,16 @@ impl SimulationImpl {
                 SimTraceKind::BigClock { .. } | SimTraceKind::SmallClock { .. } => {
                     trace_writer.set_signal_clock(id, state[0])?;
                 }
+                SimTraceKind::EnumDiscriminant { ty, .. } => {
+                    let mut variant_index = [0; mem::size_of::<usize>()];
+                    variant_index.view_bits_mut::<Lsb0>()[0..state.len()]
+                        .clone_from_bitslice(state);
+                    trace_writer.set_signal_enum_discriminant(
+                        id,
+                        usize::from_le_bytes(variant_index),
+                        ty,
+                    )?;
+                }
             }
         }
         Ok(trace_writer)
@@ -4091,7 +4231,8 @@ impl SimulationImpl {
                     state.set(0, !self.state.big_slots[index].is_zero());
                 }
                 SimTraceKind::SmallUInt { index, ty: _ }
-                | SimTraceKind::SmallSInt { index, ty: _ } => {
+                | SimTraceKind::SmallSInt { index, ty: _ }
+                | SimTraceKind::EnumDiscriminant { index, ty: _ } => {
                     let bytes = self.state.small_slots[index].to_le_bytes();
                     let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
                     let bitslice = &bitslice[..state.len()];
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index 643b604..ceaa359 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -2260,6 +2260,35 @@ impl_insns! {
         state.small_slots[dest] = value;
         next!();
     }
+    AndSmallImmediate {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        rhs: SmallUInt,
+    } => {
+        let value = state.small_slots[lhs] & rhs;
+        state.small_slots[dest] = value;
+        next!();
+    }
+    AndBigWithSmallImmediate {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Immediate]
+        rhs: SmallUInt,
+    } => {
+        let lhs = &state.big_slots[lhs];
+        let mut lhs_lsb64 = lhs.iter_u64_digits().next().unwrap_or(0);
+        if lhs.is_negative() {
+            lhs_lsb64 = lhs_lsb64.wrapping_neg();
+        }
+        let value = lhs_lsb64 & rhs;
+        state.small_slots[dest] = value;
+        next!();
+    }
     Or {
         #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,
diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs
index b17d839..1ec2aeb 100644
--- a/crates/fayalite/src/sim/vcd.rs
+++ b/crates/fayalite/src/sim/vcd.rs
@@ -2,6 +2,7 @@
 // See Notices.txt for copyright information
 
 use crate::{
+    enum_::{Enum, EnumType},
     expr::Flow,
     int::UInt,
     sim::{
@@ -13,7 +14,11 @@ use crate::{
     },
 };
 use bitvec::slice::BitSlice;
-use std::{fmt, io, mem};
+use std::{
+    fmt::{self, Display},
+    io::{self, Write},
+    mem,
+};
 
 pub struct VcdWriterDecls<W: io::Write + 'static> {
     writer: W,
@@ -190,6 +195,46 @@ fn write_scalar_id<W: io::Write>(writer: &mut W, id: TraceScalarId) -> io::Resul
     Ok(())
 }
 
+fn write_escaped<W: io::Write>(writer: &mut W, value: impl Display) -> io::Result<()> {
+    // escaping rules from function GTKWave uses to decode VCD strings:
+    // https://github.com/gtkwave/gtkwave/blob/491f24d7e8619cfc1fcc65704ee5c967d1083c18/lib/libfst/fstapi.c#L7090
+    struct Wrapper<W>(W);
+    impl<W: io::Write> io::Write for Wrapper<W> {
+        fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
+            if buf.is_empty() {
+                return self.0.write(buf);
+            }
+            let mut retval = 0;
+            for &byte in buf {
+                match byte {
+                    b'\\' | b'\'' | b'"' | b'?' => self.0.write_all(&[b'\\', byte])?,
+                    b'\n' => self.0.write_all(br"\n")?,
+                    b'\r' => self.0.write_all(br"\r")?,
+                    b'\t' => self.0.write_all(br"\t")?,
+                    0x7 => self.0.write_all(br"\a")?,
+                    0x8 => self.0.write_all(br"\b")?,
+                    0xC => self.0.write_all(br"\f")?,
+                    0xB => self.0.write_all(br"\v")?,
+                    _ => {
+                        if byte.is_ascii_graphic() {
+                            self.0.write_all(&[byte])?;
+                        } else {
+                            write!(self.0, r"\x{byte:02x}")?;
+                        }
+                    }
+                }
+                retval += 1;
+            }
+            Ok(retval)
+        }
+
+        fn flush(&mut self) -> io::Result<()> {
+            self.0.flush()
+        }
+    }
+    write!(Wrapper(writer), "{value}")
+}
+
 fn write_vcd_var<W: io::Write>(
     writer: &mut W,
     var_type: &str,
@@ -251,13 +296,25 @@ impl WriteTrace for TraceBool {
 
 impl WriteTrace for TraceFieldlessEnum {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        todo!()
+        let Self { id, name, ty, flow } = self;
+        TraceEnumDiscriminant { id, name, ty, flow }.write_trace(writer, arg)
     }
 }
 
 impl WriteTrace for TraceEnumDiscriminant {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        todo!()
+        let ArgInType {
+            source_var_type: _,
+            sink_var_type: _,
+            duplex_var_type: _,
+        } = arg.in_type();
+        let Self {
+            id,
+            name,
+            ty: _,
+            flow: _,
+        } = self;
+        write_vcd_var(writer, "string", 1, id, &name)
     }
 }
 
@@ -469,6 +526,17 @@ impl<W: io::Write + 'static> VcdWriter<W> {
     pub fn timescale(&self) -> SimDuration {
         self.timescale
     }
+    fn write_string_value_change(
+        &mut self,
+        value: impl Display,
+        id: TraceScalarId,
+    ) -> io::Result<()> {
+        self.writer.write_all(b"s")?;
+        write_escaped(&mut self.writer, value)?;
+        self.writer.write_all(b" ")?;
+        write_scalar_id(&mut self.writer, id)?;
+        self.writer.write_all(b"\n")
+    }
 }
 
 impl<W: io::Write> TraceWriter for VcdWriter<W> {
@@ -525,6 +593,24 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
     fn close(mut self) -> Result<(), Self::Error> {
         self.writer.flush()
     }
+
+    fn set_signal_enum_discriminant(
+        &mut self,
+        id: TraceScalarId,
+        variant_index: usize,
+        ty: Enum,
+    ) -> Result<(), Self::Error> {
+        self.write_string_value_change(
+            format_args!(
+                "{} ({variant_index})",
+                ty.variants()
+                    .get(variant_index)
+                    .map(|v| &*v.name)
+                    .unwrap_or("<invalid>"),
+            ),
+            id,
+        )
+    }
 }
 
 impl<W: io::Write> fmt::Debug for VcdWriter<W> {

From 15bc304bb69aff5581515433f2340c56990087d5 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 4 Dec 2024 20:57:44 -0800
Subject: [PATCH 116/190] impl ToExpr for TargetBase

---
 crates/fayalite/src/expr/target.rs | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite/src/expr/target.rs b/crates/fayalite/src/expr/target.rs
index 8f39e13..c8c55e9 100644
--- a/crates/fayalite/src/expr/target.rs
+++ b/crates/fayalite/src/expr/target.rs
@@ -3,7 +3,7 @@
 use crate::{
     array::Array,
     bundle::{Bundle, BundleField},
-    expr::Flow,
+    expr::{Expr, Flow, ToExpr},
     intern::{Intern, Interned},
     memory::{DynPortType, MemPort},
     module::{Instance, ModuleIO, TargetName},
@@ -195,6 +195,16 @@ macro_rules! impl_target_base {
                 }
             }
         }
+
+        impl ToExpr for $TargetBase {
+            type Type = CanonicalType;
+
+            fn to_expr(&self) -> Expr<Self::Type> {
+                match self {
+                    $(Self::$Variant(v) => Expr::canonical(v.to_expr()),)*
+                }
+            }
+        }
     };
 }
 

From 42afd2da0e9c507232b8ed1d010208eceeadcdc7 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 4 Dec 2024 20:58:39 -0800
Subject: [PATCH 117/190] sim: implement enums (except for connecting unequal
 enum types)

---
 crates/fayalite/src/sim.rs             | 523 +++++++++++++++++++------
 crates/fayalite/src/sim/interpreter.rs |  69 ++++
 crates/fayalite/tests/sim.rs           |   2 +
 3 files changed, 475 insertions(+), 119 deletions(-)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 3751241..ea09e83 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -59,7 +59,7 @@ enum CondBody {
         cond: CompiledValue<Bool>,
     },
     MatchArm {
-        enum_expr: CompiledValue<Enum>,
+        discriminant: StatePartIndex<StatePartKindSmallSlots>,
         variant_index: usize,
     },
 }
@@ -246,12 +246,6 @@ impl<T: Type> CompiledValue<T> {
     }
 }
 
-impl CompiledValue<Enum> {
-    fn add_discriminant_to_set(self, inputs: &mut SlotSet) {
-        inputs.extend([self.range]);
-    }
-}
-
 impl CompiledValue<Bundle> {
     fn field_by_index(self, field_index: usize) -> CompiledValue<CanonicalType> {
         self.map(|layout, range| {
@@ -957,9 +951,9 @@ impl Extend<CondBody> for SlotSet {
                 self.extend([cond.range]);
             }
             CondBody::MatchArm {
-                enum_expr,
+                discriminant,
                 variant_index: _,
-            } => enum_expr.add_discriminant_to_set(self),
+            } => self.extend([discriminant]),
         })
     }
 }
@@ -1271,11 +1265,14 @@ impl Compiler {
     }
     fn make_trace_scalar_helper(
         &mut self,
-        target: TargetInInstantiatedModule,
+        instantiated_module: InstantiatedModule,
+        target: Expr<CanonicalType>,
+        source_location: SourceLocation,
         small_kind: impl FnOnce(StatePartIndex<StatePartKindSmallSlots>) -> SimTraceKind,
         big_kind: impl FnOnce(StatePartIndex<StatePartKindBigSlots>) -> SimTraceKind,
     ) -> TraceScalarId {
-        let compiled_value = self.compile_value(target);
+        let compiled_value = self.compile_expr(instantiated_module, target);
+        let compiled_value = self.compiled_expr_to_value(compiled_value, source_location);
         self.new_sim_trace(match compiled_value.range.len() {
             TypeLen::A_SMALL_SLOT => small_kind(compiled_value.range.small_slots.start),
             TypeLen::A_BIG_SLOT => big_kind(compiled_value.range.big_slots.start),
@@ -1284,14 +1281,18 @@ impl Compiler {
     }
     fn make_trace_scalar(
         &mut self,
-        target: TargetInInstantiatedModule,
+        instantiated_module: InstantiatedModule,
+        target: Expr<CanonicalType>,
         name: Interned<str>,
+        source_location: SourceLocation,
     ) -> TraceDecl {
-        let flow = target.target.flow();
-        match target.target.canonical_ty() {
+        let flow = Expr::flow(target);
+        match Expr::ty(target) {
             CanonicalType::UInt(ty) => TraceUInt {
                 id: self.make_trace_scalar_helper(
+                    instantiated_module,
                     target,
+                    source_location,
                     |index| SimTraceKind::SmallUInt { index, ty },
                     |index| SimTraceKind::BigUInt { index, ty },
                 ),
@@ -1302,7 +1303,9 @@ impl Compiler {
             .into(),
             CanonicalType::SInt(ty) => TraceSInt {
                 id: self.make_trace_scalar_helper(
+                    instantiated_module,
                     target,
+                    source_location,
                     |index| SimTraceKind::SmallSInt { index, ty },
                     |index| SimTraceKind::BigSInt { index, ty },
                 ),
@@ -1313,7 +1316,9 @@ impl Compiler {
             .into(),
             CanonicalType::Bool(_) => TraceBool {
                 id: self.make_trace_scalar_helper(
+                    instantiated_module,
                     target,
+                    source_location,
                     |index| SimTraceKind::SmallBool { index },
                     |index| SimTraceKind::BigBool { index },
                 ),
@@ -1324,10 +1329,11 @@ impl Compiler {
             CanonicalType::Array(_) => unreachable!(),
             CanonicalType::Enum(ty) => {
                 assert_eq!(ty.discriminant_bit_width(), ty.type_properties().bit_width);
-                let compiled_value = self.compile_value(target);
+                let compiled_value = self.compile_expr(instantiated_module, target);
+                let compiled_value = self.compiled_expr_to_value(compiled_value, source_location);
                 let discriminant = self.compile_enum_discriminant(
                     compiled_value.map_ty(Enum::from_canonical),
-                    target.target.base().source_location(),
+                    source_location,
                 );
                 TraceFieldlessEnum {
                     id: self.new_sim_trace(SimTraceKind::EnumDiscriminant {
@@ -1343,7 +1349,9 @@ impl Compiler {
             CanonicalType::Bundle(_) => unreachable!(),
             CanonicalType::AsyncReset(_) => TraceAsyncReset {
                 id: self.make_trace_scalar_helper(
+                    instantiated_module,
                     target,
+                    source_location,
                     |index| SimTraceKind::SmallAsyncReset { index },
                     |index| SimTraceKind::BigAsyncReset { index },
                 ),
@@ -1353,7 +1361,9 @@ impl Compiler {
             .into(),
             CanonicalType::SyncReset(_) => TraceSyncReset {
                 id: self.make_trace_scalar_helper(
+                    instantiated_module,
                     target,
+                    source_location,
                     |index| SimTraceKind::SmallSyncReset { index },
                     |index| SimTraceKind::BigSyncReset { index },
                 ),
@@ -1364,7 +1374,9 @@ impl Compiler {
             CanonicalType::Reset(_) => unreachable!(),
             CanonicalType::Clock(_) => TraceClock {
                 id: self.make_trace_scalar_helper(
+                    instantiated_module,
                     target,
+                    source_location,
                     |index| SimTraceKind::SmallClock { index },
                     |index| SimTraceKind::BigClock { index },
                 ),
@@ -1376,56 +1388,89 @@ impl Compiler {
     }
     fn make_trace_decl_child(
         &mut self,
-        target: TargetInInstantiatedModule,
+        instantiated_module: InstantiatedModule,
+        target: Expr<CanonicalType>,
         name: Interned<str>,
+        source_location: SourceLocation,
     ) -> TraceDecl {
-        match target.target.canonical_ty() {
+        match Expr::ty(target) {
             CanonicalType::Array(ty) => {
                 let elements = Interned::from_iter((0..ty.len()).map(|index| {
                     self.make_trace_decl_child(
-                        TargetInInstantiatedModule {
-                            instantiated_module: target.instantiated_module,
-                            target: target.target.join(
-                                TargetPathElement::from(TargetPathArrayElement { index })
-                                    .intern_sized(),
-                            ),
-                        },
+                        instantiated_module,
+                        Expr::<Array>::from_canonical(target)[index],
                         Intern::intern_owned(format!("[{index}]")),
+                        source_location,
                     )
                 }));
                 TraceArray {
                     name,
                     elements,
                     ty,
-                    flow: target.target.flow(),
+                    flow: Expr::flow(target),
                 }
                 .into()
             }
             CanonicalType::Enum(ty) => {
                 if ty.variants().iter().all(|v| v.ty.is_none()) {
-                    self.make_trace_scalar(target, name)
+                    self.make_trace_scalar(instantiated_module, target, name, source_location)
                 } else {
-                    todo!()
+                    let flow = Expr::flow(target);
+                    let compiled_value = self.compile_expr(instantiated_module, target);
+                    let compiled_value =
+                        self.compiled_expr_to_value(compiled_value, source_location);
+                    let discriminant = self.compile_enum_discriminant(
+                        compiled_value.map_ty(Enum::from_canonical),
+                        source_location,
+                    );
+                    let discriminant = TraceEnumDiscriminant {
+                        id: self.new_sim_trace(SimTraceKind::EnumDiscriminant {
+                            index: discriminant,
+                            ty,
+                        }),
+                        name,
+                        ty,
+                        flow,
+                    };
+                    let base = Expr::<Enum>::from_canonical(target);
+                    let non_empty_fields =
+                        Interned::from_iter(ty.variants().into_iter().enumerate().flat_map(
+                            |(variant_index, variant)| {
+                                variant.ty.map(|_| {
+                                    self.make_trace_decl_child(
+                                        instantiated_module,
+                                        ops::VariantAccess::new_by_index(base, variant_index)
+                                            .to_expr(),
+                                        variant.name,
+                                        source_location,
+                                    )
+                                })
+                            },
+                        ));
+                    TraceEnumWithFields {
+                        name,
+                        discriminant,
+                        non_empty_fields,
+                        ty,
+                        flow,
+                    }
+                    .into()
                 }
             }
             CanonicalType::Bundle(ty) => {
                 let fields = Interned::from_iter(ty.fields().iter().map(|field| {
                     self.make_trace_decl_child(
-                        TargetInInstantiatedModule {
-                            instantiated_module: target.instantiated_module,
-                            target: target.target.join(
-                                TargetPathElement::from(TargetPathBundleField { name: field.name })
-                                    .intern_sized(),
-                            ),
-                        },
+                        instantiated_module,
+                        Expr::field(Expr::<Bundle>::from_canonical(target), &field.name),
                         field.name,
+                        source_location,
                     )
                 }));
                 TraceBundle {
                     name,
                     fields,
                     ty,
-                    flow: target.target.flow(),
+                    flow: Expr::flow(target),
                 }
                 .into()
             }
@@ -1435,7 +1480,9 @@ impl Compiler {
             | CanonicalType::AsyncReset(_)
             | CanonicalType::SyncReset(_)
             | CanonicalType::Reset(_)
-            | CanonicalType::Clock(_) => self.make_trace_scalar(target, name),
+            | CanonicalType::Clock(_) => {
+                self.make_trace_scalar(instantiated_module, target, name, source_location)
+            }
         }
     }
     fn make_trace_decl(
@@ -1443,15 +1490,17 @@ impl Compiler {
         instantiated_module: InstantiatedModule,
         target_base: TargetBase,
     ) -> TraceDecl {
-        let target = TargetInInstantiatedModule {
-            instantiated_module,
-            target: target_base.into(),
-        };
+        let target = target_base.to_expr();
         match target_base {
             TargetBase::ModuleIO(module_io) => TraceModuleIO {
                 name: module_io.name(),
                 child: self
-                    .make_trace_decl_child(target, module_io.name())
+                    .make_trace_decl_child(
+                        instantiated_module,
+                        target,
+                        module_io.name(),
+                        module_io.source_location(),
+                    )
                     .intern(),
                 ty: module_io.ty(),
                 flow: module_io.flow(),
@@ -1459,9 +1508,12 @@ impl Compiler {
             .into(),
             TargetBase::MemPort(mem_port) => {
                 let name = Intern::intern_owned(mem_port.port_name().to_string());
-                let TraceDecl::Scope(TraceScope::Bundle(bundle)) =
-                    self.make_trace_decl_child(target, name)
-                else {
+                let TraceDecl::Scope(TraceScope::Bundle(bundle)) = self.make_trace_decl_child(
+                    instantiated_module,
+                    target,
+                    name,
+                    mem_port.source_location(),
+                ) else {
                     unreachable!()
                 };
                 TraceMemPort {
@@ -1473,36 +1525,67 @@ impl Compiler {
             }
             TargetBase::Reg(reg) => TraceReg {
                 name: reg.name(),
-                child: self.make_trace_decl_child(target, reg.name()).intern(),
+                child: self
+                    .make_trace_decl_child(
+                        instantiated_module,
+                        target,
+                        reg.name(),
+                        reg.source_location(),
+                    )
+                    .intern(),
                 ty: reg.ty(),
             }
             .into(),
             TargetBase::RegSync(reg) => TraceReg {
                 name: reg.name(),
-                child: self.make_trace_decl_child(target, reg.name()).intern(),
+                child: self
+                    .make_trace_decl_child(
+                        instantiated_module,
+                        target,
+                        reg.name(),
+                        reg.source_location(),
+                    )
+                    .intern(),
                 ty: reg.ty(),
             }
             .into(),
             TargetBase::RegAsync(reg) => TraceReg {
                 name: reg.name(),
-                child: self.make_trace_decl_child(target, reg.name()).intern(),
+                child: self
+                    .make_trace_decl_child(
+                        instantiated_module,
+                        target,
+                        reg.name(),
+                        reg.source_location(),
+                    )
+                    .intern(),
                 ty: reg.ty(),
             }
             .into(),
             TargetBase::Wire(wire) => TraceWire {
                 name: wire.name(),
-                child: self.make_trace_decl_child(target, wire.name()).intern(),
+                child: self
+                    .make_trace_decl_child(
+                        instantiated_module,
+                        target,
+                        wire.name(),
+                        wire.source_location(),
+                    )
+                    .intern(),
                 ty: wire.ty(),
             }
             .into(),
             TargetBase::Instance(instance) => {
-                let TraceDecl::Scope(TraceScope::Bundle(instance_io)) =
-                    self.make_trace_decl_child(target, instance.name())
-                else {
+                let TraceDecl::Scope(TraceScope::Bundle(instance_io)) = self.make_trace_decl_child(
+                    instantiated_module,
+                    target,
+                    instance.name(),
+                    instance.source_location(),
+                ) else {
                     unreachable!()
                 };
                 let compiled_module = &self.modules[&InstantiatedModule::Child {
-                    parent: target.instantiated_module.intern(),
+                    parent: instantiated_module.intern(),
                     instance: instance.intern(),
                 }];
                 TraceInstance {
@@ -1647,6 +1730,49 @@ impl Compiler {
         self.assignments
             .push(Assignment::new(conditions, insns, source_location));
     }
+    fn simple_big_expr_input(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        input: Expr<CanonicalType>,
+    ) -> StatePartIndex<StatePartKindBigSlots> {
+        let input = self.compile_expr(instantiated_module, input);
+        let input =
+            self.compiled_expr_to_value(input, instantiated_module.leaf_module().source_location());
+        assert_eq!(input.range.len(), TypeLen::A_BIG_SLOT);
+        input.range.big_slots.start
+    }
+    fn compile_expr_helper(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        dest_ty: CanonicalType,
+        make_insns: impl FnOnce(&mut Self, TypeIndexRange) -> Vec<Insn>,
+    ) -> CompiledValue<CanonicalType> {
+        let layout = CompiledTypeLayout::get(dest_ty);
+        let range = self.insns.allocate_variable(&layout.layout);
+        let retval = CompiledValue {
+            layout,
+            range,
+            write: None,
+        };
+        let insns = make_insns(self, range);
+        self.add_assignment(
+            Interned::default(),
+            insns,
+            instantiated_module.leaf_module().source_location(),
+        );
+        retval
+    }
+    fn simple_nary_big_expr_helper(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        dest_ty: CanonicalType,
+        make_insns: impl FnOnce(StatePartIndex<StatePartKindBigSlots>) -> Vec<Insn>,
+    ) -> CompiledValue<CanonicalType> {
+        self.compile_expr_helper(instantiated_module, dest_ty, |_, dest| {
+            assert_eq!(dest.len(), TypeLen::A_BIG_SLOT);
+            make_insns(dest.big_slots.start)
+        })
+    }
     fn simple_nary_big_expr<const N: usize>(
         &mut self,
         instantiated_module: InstantiatedModule,
@@ -1657,37 +1783,10 @@ impl Compiler {
             [StatePartIndex<StatePartKindBigSlots>; N],
         ) -> Vec<Insn>,
     ) -> CompiledValue<CanonicalType> {
-        let inputs = inputs.map(|input| {
-            let input = self.compile_expr(instantiated_module, input);
-            let input = self
-                .compiled_expr_to_value(input, instantiated_module.leaf_module().source_location());
-            let TypeIndexRange {
-                small_slots,
-                big_slots,
-            } = input.range;
-            assert_eq!(small_slots.len.value, 0);
-            assert_eq!(big_slots.len.value, 1);
-            big_slots.start
-        });
-        let layout = CompiledTypeLayout::get(dest_ty);
-        let range = self.insns.allocate_variable(&layout.layout);
-        let TypeIndexRange {
-            small_slots,
-            big_slots,
-        } = range;
-        assert_eq!(small_slots.len.value, 0);
-        assert_eq!(big_slots.len.value, 1);
-        let retval = CompiledValue {
-            layout,
-            range,
-            write: None,
-        };
-        self.add_assignment(
-            Interned::default(),
-            make_insns(big_slots.start, inputs),
-            instantiated_module.leaf_module().source_location(),
-        );
-        retval
+        let inputs = inputs.map(|input| self.simple_big_expr_input(instantiated_module, input));
+        self.simple_nary_big_expr_helper(instantiated_module, dest_ty, |dest| {
+            make_insns(dest, inputs)
+        })
     }
     fn compiled_value_to_dyn_array_index(
         &mut self,
@@ -1773,6 +1872,153 @@ impl Compiler {
             .insert(compiled_value, retval);
         retval
     }
+    fn compile_cast_scalar_to_bits<T: Type>(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        arg: Expr<CanonicalType>,
+        cast_fn: impl FnOnce(Expr<T>) -> Expr<UInt>,
+    ) -> CompiledValue<UInt> {
+        let arg = Expr::<T>::from_canonical(arg);
+        let retval = cast_fn(arg);
+        let retval = self.compile_expr(instantiated_module, Expr::canonical(retval));
+        let retval = self
+            .compiled_expr_to_value(retval, instantiated_module.leaf_module().source_location());
+        retval.map_ty(UInt::from_canonical)
+    }
+    fn compile_cast_aggregate_to_bits(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        parts: impl IntoIterator<Item = Expr<CanonicalType>>,
+    ) -> CompiledValue<UInt> {
+        let retval = parts
+            .into_iter()
+            .map(|part| part.cast_to_bits())
+            .reduce(|accumulator, part| accumulator | (part << Expr::ty(accumulator).width))
+            .unwrap_or_else(|| UInt[0].zero().to_expr());
+        let retval = self.compile_expr(instantiated_module, Expr::canonical(retval));
+        let retval = self
+            .compiled_expr_to_value(retval, instantiated_module.leaf_module().source_location());
+        retval.map_ty(UInt::from_canonical)
+    }
+    fn compile_cast_to_bits(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        expr: ops::CastToBits,
+    ) -> CompiledValue<UInt> {
+        match Expr::ty(expr.arg()) {
+            CanonicalType::UInt(_) => {
+                self.compile_cast_scalar_to_bits(instantiated_module, expr.arg(), |arg| arg)
+            }
+            CanonicalType::SInt(ty) => self.compile_cast_scalar_to_bits(
+                instantiated_module,
+                expr.arg(),
+                |arg: Expr<SInt>| arg.cast_to(ty.as_same_width_uint()),
+            ),
+            CanonicalType::Bool(_)
+            | CanonicalType::AsyncReset(_)
+            | CanonicalType::SyncReset(_)
+            | CanonicalType::Reset(_)
+            | CanonicalType::Clock(_) => self.compile_cast_scalar_to_bits(
+                instantiated_module,
+                expr.arg(),
+                |arg: Expr<Bool>| arg.cast_to(UInt[1]),
+            ),
+            CanonicalType::Array(ty) => self.compile_cast_aggregate_to_bits(
+                instantiated_module,
+                (0..ty.len()).map(|index| Expr::<Array>::from_canonical(expr.arg())[index]),
+            ),
+            CanonicalType::Enum(ty) => self
+                .simple_nary_big_expr(
+                    instantiated_module,
+                    UInt[ty.type_properties().bit_width].canonical(),
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| vec![Insn::Copy { dest, src }],
+                )
+                .map_ty(UInt::from_canonical),
+            CanonicalType::Bundle(ty) => self.compile_cast_aggregate_to_bits(
+                instantiated_module,
+                ty.fields().iter().map(|field| {
+                    Expr::field(Expr::<Bundle>::from_canonical(expr.arg()), &field.name)
+                }),
+            ),
+        }
+    }
+    fn compile_cast_bits_to(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        expr: ops::CastBitsTo,
+    ) -> CompiledValue<CanonicalType> {
+        let retval = match expr.ty() {
+            CanonicalType::UInt(_) => Expr::canonical(expr.arg()),
+            CanonicalType::SInt(ty) => Expr::canonical(expr.arg().cast_to(ty)),
+            CanonicalType::Bool(ty) => Expr::canonical(expr.arg().cast_to(ty)),
+            CanonicalType::Array(ty) => {
+                let stride = ty.element().bit_width();
+                Expr::<Array>::canonical(
+                    ops::ArrayLiteral::new(
+                        ty.element(),
+                        Interned::from_iter((0..ty.len()).map(|index| {
+                            let start = stride * index;
+                            let end = start + stride;
+                            expr.arg()[start..end].cast_bits_to(ty.element())
+                        })),
+                    )
+                    .to_expr(),
+                )
+            }
+            ty @ CanonicalType::Enum(_) => {
+                return self.simple_nary_big_expr(
+                    instantiated_module,
+                    ty,
+                    [Expr::canonical(expr.arg())],
+                    |dest, [src]| vec![Insn::Copy { dest, src }],
+                );
+            }
+            CanonicalType::Bundle(ty) => Expr::canonical(
+                ops::BundleLiteral::new(
+                    ty,
+                    Interned::from_iter(ty.field_offsets().iter().zip(&ty.fields()).map(
+                        |(&offset, &field)| {
+                            let end = offset + field.ty.bit_width();
+                            expr.arg()[offset..end].cast_bits_to(field.ty)
+                        },
+                    )),
+                )
+                .to_expr(),
+            ),
+            CanonicalType::AsyncReset(ty) => Expr::canonical(expr.arg().cast_to(ty)),
+            CanonicalType::SyncReset(ty) => Expr::canonical(expr.arg().cast_to(ty)),
+            CanonicalType::Reset(_) => unreachable!(),
+            CanonicalType::Clock(ty) => Expr::canonical(expr.arg().cast_to(ty)),
+        };
+        let retval = self.compile_expr(instantiated_module, Expr::canonical(retval));
+        self.compiled_expr_to_value(retval, instantiated_module.leaf_module().source_location())
+    }
+    fn compile_aggregate_literal(
+        &mut self,
+        instantiated_module: InstantiatedModule,
+        dest_ty: CanonicalType,
+        inputs: Interned<[Expr<CanonicalType>]>,
+    ) -> CompiledValue<CanonicalType> {
+        self.compile_expr_helper(instantiated_module, dest_ty, |this, dest| {
+            let mut insns = Vec::new();
+            let mut offset = TypeIndex::ZERO;
+            for input in inputs {
+                let input = this.compile_expr(instantiated_module, input);
+                let input = this
+                    .compiled_expr_to_value(
+                        input,
+                        instantiated_module.leaf_module().source_location(),
+                    )
+                    .range;
+                insns.extend(
+                    input.insns_for_copy_to(dest.slice(TypeIndexRange::new(offset, input.len()))),
+                );
+                offset = offset.offset(input.len().as_index());
+            }
+            insns
+        })
+    }
     fn compile_expr(
         &mut self,
         instantiated_module: InstantiatedModule,
@@ -1860,10 +2106,44 @@ impl Compiler {
                     }]
                 })
                 .into(),
-            ExprEnum::BundleLiteral(expr) => todo!(),
-            ExprEnum::ArrayLiteral(expr) => todo!(),
-            ExprEnum::EnumLiteral(expr) => todo!(),
-            ExprEnum::Uninit(expr) => todo!(),
+            ExprEnum::BundleLiteral(literal) => self
+                .compile_aggregate_literal(
+                    instantiated_module,
+                    Expr::ty(expr),
+                    literal.field_values(),
+                )
+                .into(),
+            ExprEnum::ArrayLiteral(literal) => self
+                .compile_aggregate_literal(
+                    instantiated_module,
+                    Expr::ty(expr),
+                    literal.element_values(),
+                )
+                .into(),
+            ExprEnum::EnumLiteral(expr) => {
+                let enum_bits_ty = UInt[expr.ty().type_properties().bit_width];
+                let enum_bits = if let Some(variant_value) = expr.variant_value() {
+                    (
+                        UInt[expr.ty().discriminant_bit_width()]
+                            .from_int_wrapping(expr.variant_index()),
+                        variant_value,
+                    )
+                        .cast_to_bits()
+                        .cast_to(enum_bits_ty)
+                } else {
+                    enum_bits_ty
+                        .from_int_wrapping(expr.variant_index())
+                        .to_expr()
+                };
+                self.compile_expr(
+                    instantiated_module,
+                    enum_bits.cast_bits_to(expr.ty().canonical()),
+                )
+            }
+            ExprEnum::Uninit(expr) => self.compile_expr(
+                instantiated_module,
+                UInt[expr.ty().bit_width()].zero().cast_bits_to(expr.ty()),
+            ),
             ExprEnum::NotU(expr) => self
                 .simple_nary_big_expr(
                     instantiated_module,
@@ -2392,7 +2672,12 @@ impl Compiler {
                 .compile_expr(instantiated_module, Expr::canonical(expr.base()))
                 .map_ty(Bundle::from_canonical)
                 .field_by_index(expr.field_index()),
-            ExprEnum::VariantAccess(expr) => todo!(),
+            ExprEnum::VariantAccess(variant_access) => self.compile_expr(
+                instantiated_module,
+                variant_access.base().cast_to_bits()
+                    [Expr::ty(variant_access.base()).discriminant_bit_width()..]
+                    .cast_bits_to(Expr::ty(expr)),
+            ),
             ExprEnum::ArrayIndex(expr) => self
                 .compile_expr(instantiated_module, Expr::canonical(expr.base()))
                 .map_ty(Array::from_canonical)
@@ -2512,8 +2797,13 @@ impl Compiler {
                     },
                 )
                 .into(),
-            ExprEnum::CastToBits(expr) => todo!(),
-            ExprEnum::CastBitsTo(expr) => todo!(),
+            ExprEnum::CastToBits(expr) => self
+                .compile_cast_to_bits(instantiated_module, expr)
+                .map_ty(CanonicalType::UInt)
+                .into(),
+            ExprEnum::CastBitsTo(expr) => {
+                self.compile_cast_bits_to(instantiated_module, expr).into()
+            }
             ExprEnum::ModuleIO(expr) => self
                 .compile_value(TargetInInstantiatedModule {
                     instantiated_module,
@@ -3061,13 +3351,14 @@ impl Compiler {
                     let enum_expr = self.compile_expr(*parent_module, Expr::canonical(expr));
                     let enum_expr = self.compiled_expr_to_value(enum_expr, source_location);
                     let enum_expr = enum_expr.map_ty(Enum::from_canonical);
+                    let discriminant = self.compile_enum_discriminant(enum_expr, source_location);
                     for (variant_index, block) in blocks.into_iter().enumerate() {
                         self.compile_block(
                             parent_module,
                             block,
                             Interned::from_iter(conditions.iter().copied().chain([Cond {
                                 body: CondBody::MatchArm {
-                                    enum_expr,
+                                    discriminant,
                                     variant_index,
                                 },
                                 source_location,
@@ -3217,9 +3508,18 @@ impl Compiler {
                         );
                     }
                     CondBody::MatchArm {
-                        enum_expr,
+                        discriminant,
                         variant_index,
-                    } => todo!(),
+                    } => {
+                        self.insns.push(
+                            Insn::BranchIfSmallNeImmediate {
+                                target: end_label_index,
+                                lhs: discriminant,
+                                rhs: variant_index as _,
+                            },
+                            cond.source_location,
+                        );
+                    }
                 }
                 cond_stack.push(CondStackEntry {
                     cond,
@@ -3261,22 +3561,6 @@ impl Compiler {
             source_location,
         } in mem::take(&mut self.registers)
         {
-            let write_to_current_value = |value_to_write: CompiledValue<CanonicalType>| {
-                let TypeIndexRange {
-                    small_slots,
-                    big_slots,
-                } = value.range;
-                small_slots
-                    .iter()
-                    .zip(value_to_write.range.small_slots.iter())
-                    .map(|(base, src)| Insn::CopySmall { dest: base, src })
-                    .chain(
-                        big_slots
-                            .iter()
-                            .zip(value_to_write.range.big_slots.iter())
-                            .map(|(base, src)| Insn::Copy { dest: base, src }),
-                    )
-            };
             match reset {
                 Some(RegisterReset {
                     is_async,
@@ -3300,15 +3584,15 @@ impl Compiler {
                         self.insns.push(branch_if_not_triggered, source_location);
                         self.insns.push(branch_if_reset, source_location);
                     }
-                    for insn in write_to_current_value(value.write_value()) {
-                        self.insns.push(insn, source_location);
-                    }
+                    self.insns.extend(
+                        value.range.insns_for_copy_from(value.write_value().range),
+                        source_location,
+                    );
                     self.insns
                         .push(Insn::Branch { target: reg_end }, source_location);
                     self.insns.define_label_at_next_insn(reg_reset);
-                    for insn in write_to_current_value(init) {
-                        self.insns.push(insn, source_location);
-                    }
+                    self.insns
+                        .extend(value.range.insns_for_copy_from(init.range), source_location);
                     self.insns.define_label_at_next_insn(reg_end);
                 }
                 None => {
@@ -3320,9 +3604,10 @@ impl Compiler {
                         },
                         source_location,
                     );
-                    for insn in write_to_current_value(value.write_value()) {
-                        self.insns.push(insn, source_location);
-                    }
+                    self.insns.extend(
+                        value.range.insns_for_copy_from(value.write_value().range),
+                        source_location,
+                    );
                     self.insns.define_label_at_next_insn(reg_end);
                 }
             }
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index ceaa359..cb1f29b 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -913,12 +913,23 @@ macro_rules! make_state_part_kinds {
             $(pub(crate) $type_field: StatePartLen<$TypeKind>,)*
         }
 
+        impl TypeLen {
+            pub(crate) const fn as_index(self) -> TypeIndex {
+                TypeIndex {
+                    $($type_field: self.$type_field.as_index(),)*
+                }
+            }
+        }
+
         #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
         pub(crate) struct TypeIndex {
             $(pub(crate) $type_field: StatePartIndex<$TypeKind>,)*
         }
 
         impl TypeIndex {
+            pub(crate) const ZERO: Self = Self {
+                $($type_field: StatePartIndex::ZERO,)*
+            };
             pub(crate) fn offset(self, offset: TypeIndex) -> Self {
                 Self {
                     $($type_field: self.$type_field.offset(offset.$type_field),)*
@@ -1470,6 +1481,10 @@ pub(crate) struct StatePartIndex<K: StatePartKind> {
 }
 
 impl<K: StatePartKind> StatePartIndex<K> {
+    pub(crate) const ZERO: Self = Self {
+        value: 0,
+        _phantom: PhantomData,
+    };
     pub(crate) fn as_usize(self) -> usize {
         self.value.try_into().expect("index too big")
     }
@@ -1520,6 +1535,12 @@ impl<K: StatePartKind> StatePartLen<K> {
             _phantom: PhantomData,
         }
     }
+    pub(crate) const fn as_index(self) -> StatePartIndex<K> {
+        StatePartIndex {
+            value: self.value,
+            _phantom: PhantomData,
+        }
+    }
 }
 
 impl<K: StatePartKind> fmt::Debug for StatePartLen<K> {
@@ -1948,6 +1969,15 @@ impl Insns<InsnsBuilding> {
         self.insns.push(insn);
         self.insn_source_locations.push(source_location);
     }
+    pub(crate) fn extend(
+        &mut self,
+        insns: impl IntoIterator<Item = Insn>,
+        source_location: SourceLocation,
+    ) {
+        self.insns.extend(insns);
+        self.insn_source_locations
+            .resize(self.insns.len(), source_location);
+    }
     pub(crate) fn allocate_variable<BK: InsnsBuildingKind>(
         &mut self,
         layout: &TypeLayout<BK>,
@@ -2047,6 +2077,31 @@ impl BorrowedState<'_> {
     }
 }
 
+impl TypeIndexRange {
+    #[must_use]
+    pub(crate) fn insns_for_copy_to(self, dest: TypeIndexRange) -> impl Iterator<Item = Insn> {
+        assert_eq!(self.len(), dest.len());
+        let Self {
+            small_slots,
+            big_slots,
+        } = self;
+        small_slots
+            .iter()
+            .zip(dest.small_slots.iter())
+            .map(|(src, dest)| Insn::CopySmall { dest, src })
+            .chain(
+                big_slots
+                    .iter()
+                    .zip(dest.big_slots.iter())
+                    .map(|(src, dest)| Insn::Copy { dest, src }),
+            )
+    }
+    #[must_use]
+    pub(crate) fn insns_for_copy_from(self, src: TypeIndexRange) -> impl Iterator<Item = Insn> {
+        src.insns_for_copy_to(self)
+    }
+}
+
 fn bigint_pow2(width: usize) -> Interned<BigInt> {
     #[derive(Copy, Clone, PartialEq, Eq, Hash)]
     struct MyMemoize;
@@ -2633,6 +2688,20 @@ impl_insns! {
             branch!(target);
         }
     }
+    BranchIfSmallNeImmediate {
+        #[kind = BranchTarget]
+        target: usize,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        rhs: SmallUInt,
+    } => {
+        if state.small_slots[lhs] != rhs {
+            branch!(target);
+        } else {
+            next!();
+        }
+    }
     Return => {
         break;
     }
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index f34bb89..c837927 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -3793,3 +3793,5 @@ $end
         panic!();
     }
 }
+
+// TODO: add tests for enums

From 643816d5b5c17ac82efae7b2f6afab531c922390 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 4 Dec 2024 21:03:29 -0800
Subject: [PATCH 118/190] vcd: handle enums with fields

---
 crates/fayalite/src/sim.rs     |  2 +-
 crates/fayalite/src/sim/vcd.rs | 16 +++++++++++++++-
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index ea09e83..009e599 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -1428,7 +1428,7 @@ impl Compiler {
                             index: discriminant,
                             ty,
                         }),
-                        name,
+                        name: "$tag".intern(),
                         ty,
                         flow,
                     };
diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs
index 1ec2aeb..8b5a58c 100644
--- a/crates/fayalite/src/sim/vcd.rs
+++ b/crates/fayalite/src/sim/vcd.rs
@@ -491,7 +491,21 @@ impl WriteTrace for TraceArray {
 
 impl WriteTrace for TraceEnumWithFields {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        todo!()
+        let arg = arg.in_type();
+        let Self {
+            name,
+            discriminant,
+            non_empty_fields,
+            ty: _,
+            flow: _,
+        } = self;
+        write_vcd_scope(writer, "struct", &name, |writer| {
+            discriminant.write_trace(writer, arg)?;
+            for field in non_empty_fields {
+                field.write_trace(writer, arg)?;
+            }
+            Ok(())
+        })
     }
 }
 

From 259bee39c226bdcdbfd5cb0d5456272062b1b21d Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 5 Dec 2024 18:15:38 -0800
Subject: [PATCH 119/190] tests/sim: split expected output text into separate
 files

---
 crates/fayalite/tests/sim.rs                  | 3523 +----------------
 .../tests/sim/expected/connect_const.txt      |  130 +
 .../sim/expected/connect_const_reset.txt      |  217 +
 .../sim/expected/connect_const_reset.vcd      |   11 +
 .../tests/sim/expected/counter_async.txt      |  509 +++
 .../tests/sim/expected/counter_async.vcd      |  217 +
 .../tests/sim/expected/counter_sync.txt       |  490 +++
 .../tests/sim/expected/counter_sync.vcd       |  214 +
 crates/fayalite/tests/sim/expected/mod1.txt   |  798 ++++
 crates/fayalite/tests/sim/expected/mod1.vcd   |   47 +
 .../tests/sim/expected/shift_register.txt     |  670 ++++
 .../tests/sim/expected/shift_register.vcd     |  193 +
 scripts/check-copyright.sh                    |    2 +-
 13 files changed, 3508 insertions(+), 3513 deletions(-)
 create mode 100644 crates/fayalite/tests/sim/expected/connect_const.txt
 create mode 100644 crates/fayalite/tests/sim/expected/connect_const_reset.txt
 create mode 100644 crates/fayalite/tests/sim/expected/connect_const_reset.vcd
 create mode 100644 crates/fayalite/tests/sim/expected/counter_async.txt
 create mode 100644 crates/fayalite/tests/sim/expected/counter_async.vcd
 create mode 100644 crates/fayalite/tests/sim/expected/counter_sync.txt
 create mode 100644 crates/fayalite/tests/sim/expected/counter_sync.vcd
 create mode 100644 crates/fayalite/tests/sim/expected/mod1.txt
 create mode 100644 crates/fayalite/tests/sim/expected/mod1.vcd
 create mode 100644 crates/fayalite/tests/sim/expected/shift_register.txt
 create mode 100644 crates/fayalite/tests/sim/expected/shift_register.vcd

diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index c837927..e65064d 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -22,137 +22,7 @@ fn test_connect_const() {
     sim.settle();
     let sim_debug = format!("{sim:#?}");
     println!("#######\n{sim_debug}\n#######");
-    if sim_debug
-        != r#"Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:1:1
-                Const {
-                    dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
-                    value: 5,
-                },
-                // at: module-XXXXXXXXXX.rs:3:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                Return,
-            ],
-            ..
-        },
-        pc: 2,
-        small_slots: StatePart {
-            value: [],
-        },
-        big_slots: StatePart {
-            value: [
-                5,
-                5,
-            ],
-        },
-    },
-    io: Instance {
-        name: <simulator>::connect_const,
-        instantiated: Module {
-            name: connect_const,
-            ..
-        },
-    },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::connect_const,
-            instantiated: Module {
-                name: connect_const,
-                ..
-            },
-        }.o: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-    },
-    made_initial_step: true,
-    needs_settle: false,
-    trace_decls: TraceModule {
-        name: "connect_const",
-        children: [
-            TraceModuleIO {
-                name: "o",
-                child: TraceUInt {
-                    id: TraceScalarId(0),
-                    name: "o",
-                    ty: UInt<8>,
-                    flow: Sink,
-                },
-                ty: UInt<8>,
-                flow: Sink,
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(0),
-                ty: UInt<8>,
-            },
-            state: 0x05,
-            last_state: 0x05,
-        },
-    ],
-    trace_writers: [],
-    instant: 0 s,
-    clocks_triggered: [],
-}"# {
+    if sim_debug != include_str!("sim/expected/connect_const.txt") {
         panic!();
     }
     assert_eq!(sim.read_bool_or_int(sim.io().o), UIntValue::from(5u8));
@@ -179,241 +49,12 @@ fn test_connect_const_reset() {
     sim.flush_traces().unwrap();
     let vcd = String::from_utf8(writer.take()).unwrap();
     println!("####### VCD:\n{vcd}\n#######");
-    if vcd
-        != r#"$timescale 1 ps $end
-$scope module connect_const_reset $end
-$var wire 1 ! reset_out $end
-$var wire 1 " bit_out $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-1!
-1"
-$end
-#1000000
-"# {
+    if vcd != include_str!("sim/expected/connect_const_reset.vcd") {
         panic!();
     }
     let sim_debug = format!("{sim:#?}");
     println!("#######\n{sim_debug}\n#######");
-    if sim_debug
-        != r#"Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 5,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
-                                ty: AsyncReset,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: AsyncReset,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:1:1
-                Const {
-                    dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    value: 1,
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
-                    src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
-                    src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
-                },
-                // at: module-XXXXXXXXXX.rs:5:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
-                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                Return,
-            ],
-            ..
-        },
-        pc: 5,
-        small_slots: StatePart {
-            value: [],
-        },
-        big_slots: StatePart {
-            value: [
-                1,
-                1,
-                1,
-                1,
-                1,
-            ],
-        },
-    },
-    io: Instance {
-        name: <simulator>::connect_const_reset,
-        instantiated: Module {
-            name: connect_const_reset,
-            ..
-        },
-    },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::connect_const_reset,
-            instantiated: Module {
-                name: connect_const_reset,
-                ..
-            },
-        }.bit_out: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::connect_const_reset,
-            instantiated: Module {
-                name: connect_const_reset,
-                ..
-            },
-        }.reset_out: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: AsyncReset,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
-                                ty: AsyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-    },
-    made_initial_step: true,
-    needs_settle: false,
-    trace_decls: TraceModule {
-        name: "connect_const_reset",
-        children: [
-            TraceModuleIO {
-                name: "reset_out",
-                child: TraceAsyncReset {
-                    id: TraceScalarId(0),
-                    name: "reset_out",
-                    flow: Sink,
-                },
-                ty: AsyncReset,
-                flow: Sink,
-            },
-            TraceModuleIO {
-                name: "bit_out",
-                child: TraceBool {
-                    id: TraceScalarId(1),
-                    name: "bit_out",
-                    flow: Sink,
-                },
-                ty: Bool,
-                flow: Sink,
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigAsyncReset {
-                index: StatePartIndex<BigSlots>(0),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(1),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(1),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-    ],
-    trace_writers: [
-        Running(
-            VcdWriter {
-                finished_init: true,
-                timescale: 1 ps,
-                ..
-            },
-        ),
-    ],
-    instant: 1 μs,
-    clocks_triggered: [],
-}"# {
+    if sim_debug != include_str!("sim/expected/connect_const_reset.txt") {
         panic!();
     }
     assert_eq!(sim.read_bool_or_int(sim.io().bit_out), true);
@@ -461,858 +102,12 @@ fn test_mod1() {
     sim.flush_traces().unwrap();
     let vcd = String::from_utf8(writer.take()).unwrap();
     println!("####### VCD:\n{vcd}\n#######");
-    if vcd
-        != r#"$timescale 1 ps $end
-$scope module mod1 $end
-$scope struct o $end
-$var wire 4 ! i $end
-$var wire 2 " o $end
-$var wire 2 # i2 $end
-$var wire 4 $ o2 $end
-$upscope $end
-$scope struct child $end
-$var wire 4 ) i $end
-$var wire 2 * o $end
-$var wire 2 + i2 $end
-$var wire 4 , o2 $end
-$upscope $end
-$scope module mod1_child $end
-$var wire 4 % i $end
-$var wire 2 & o $end
-$var wire 2 ' i2 $end
-$var wire 4 ( o2 $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-b11 !
-b11 "
-b10 #
-b1110 $
-b11 %
-b11 &
-b10 '
-b1110 (
-b11 )
-b11 *
-b10 +
-b1110 ,
-$end
-#1000000
-b1010 !
-b10 "
-b1111 $
-b1010 %
-b10 &
-b1111 (
-b1010 )
-b10 *
-b1111 ,
-#2000000
-"# {
+    if vcd != include_str!("sim/expected/mod1.vcd") {
         panic!();
     }
     let sim_debug = format!("{sim:#?}");
     println!("#######\n{sim_debug}\n#######");
-    if sim_debug
-        != r#"Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 17,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.i",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.o",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::child.i",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::child.o",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::child.i2",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::child.o2",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:4:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:2:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX-2.rs:1:1
-                Const {
-                    dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
-                    value: 15,
-                },
-                Const {
-                    dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
-                    value: 5,
-                },
-                CmpLt {
-                    dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
-                    rhs: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
-                },
-                CastToUInt {
-                    dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
-                    dest_width: 4,
-                },
-                // at: module-XXXXXXXXXX-2.rs:7:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX-2.rs:8:1
-                BranchIfZero {
-                    target: 11,
-                    value: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX-2.rs:9:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:2:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX-2.rs:1:1
-                CastToSInt {
-                    dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
-                    dest_width: 2,
-                },
-                // at: module-XXXXXXXXXX-2.rs:6:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
-                },
-                // at: module-XXXXXXXXXX.rs:2:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                Return,
-            ],
-            ..
-        },
-        pc: 17,
-        small_slots: StatePart {
-            value: [],
-        },
-        big_slots: StatePart {
-            value: [
-                10,
-                -2,
-                -2,
-                15,
-                10,
-                -2,
-                -2,
-                15,
-                10,
-                -2,
-                -2,
-                15,
-                -2,
-                14,
-                5,
-                1,
-                15,
-            ],
-        },
-    },
-    io: Instance {
-        name: <simulator>::mod1,
-        instantiated: Module {
-            name: mod1,
-            ..
-        },
-    },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::mod1,
-            instantiated: Module {
-                name: mod1,
-                ..
-            },
-        }.o: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    #[hdl(flip)] /* offset = 0 */
-                    i: UInt<4>,
-                    /* offset = 4 */
-                    o: SInt<2>,
-                    #[hdl(flip)] /* offset = 6 */
-                    i2: SInt<2>,
-                    /* offset = 8 */
-                    o2: UInt<4>,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 4,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.i",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.o",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<4>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<4>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SInt<2>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SInt<2>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(2),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SInt<2>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SInt<2>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(3),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<4>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<4>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 4 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::mod1,
-            instantiated: Module {
-                name: mod1,
-                ..
-            },
-        }.o.i: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::mod1,
-            instantiated: Module {
-                name: mod1,
-                ..
-            },
-        }.o.i2: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SInt<2>,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SInt<2>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::mod1,
-            instantiated: Module {
-                name: mod1,
-                ..
-            },
-        }.o.o: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SInt<2>,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SInt<2>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::mod1,
-            instantiated: Module {
-                name: mod1,
-                ..
-            },
-        }.o.o2: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
-            },
-            write: None,
-        },
-    },
-    made_initial_step: true,
-    needs_settle: false,
-    trace_decls: TraceModule {
-        name: "mod1",
-        children: [
-            TraceModuleIO {
-                name: "o",
-                child: TraceBundle {
-                    name: "o",
-                    fields: [
-                        TraceUInt {
-                            id: TraceScalarId(0),
-                            name: "i",
-                            ty: UInt<4>,
-                            flow: Source,
-                        },
-                        TraceSInt {
-                            id: TraceScalarId(1),
-                            name: "o",
-                            ty: SInt<2>,
-                            flow: Sink,
-                        },
-                        TraceSInt {
-                            id: TraceScalarId(2),
-                            name: "i2",
-                            ty: SInt<2>,
-                            flow: Source,
-                        },
-                        TraceUInt {
-                            id: TraceScalarId(3),
-                            name: "o2",
-                            ty: UInt<4>,
-                            flow: Sink,
-                        },
-                    ],
-                    ty: Bundle {
-                        #[hdl(flip)] /* offset = 0 */
-                        i: UInt<4>,
-                        /* offset = 4 */
-                        o: SInt<2>,
-                        #[hdl(flip)] /* offset = 6 */
-                        i2: SInt<2>,
-                        /* offset = 8 */
-                        o2: UInt<4>,
-                    },
-                    flow: Sink,
-                },
-                ty: Bundle {
-                    #[hdl(flip)] /* offset = 0 */
-                    i: UInt<4>,
-                    /* offset = 4 */
-                    o: SInt<2>,
-                    #[hdl(flip)] /* offset = 6 */
-                    i2: SInt<2>,
-                    /* offset = 8 */
-                    o2: UInt<4>,
-                },
-                flow: Sink,
-            },
-            TraceInstance {
-                name: "child",
-                instance_io: TraceBundle {
-                    name: "child",
-                    fields: [
-                        TraceUInt {
-                            id: TraceScalarId(8),
-                            name: "i",
-                            ty: UInt<4>,
-                            flow: Sink,
-                        },
-                        TraceSInt {
-                            id: TraceScalarId(9),
-                            name: "o",
-                            ty: SInt<2>,
-                            flow: Source,
-                        },
-                        TraceSInt {
-                            id: TraceScalarId(10),
-                            name: "i2",
-                            ty: SInt<2>,
-                            flow: Sink,
-                        },
-                        TraceUInt {
-                            id: TraceScalarId(11),
-                            name: "o2",
-                            ty: UInt<4>,
-                            flow: Source,
-                        },
-                    ],
-                    ty: Bundle {
-                        #[hdl(flip)] /* offset = 0 */
-                        i: UInt<4>,
-                        /* offset = 4 */
-                        o: SInt<2>,
-                        #[hdl(flip)] /* offset = 6 */
-                        i2: SInt<2>,
-                        /* offset = 8 */
-                        o2: UInt<4>,
-                    },
-                    flow: Source,
-                },
-                module: TraceModule {
-                    name: "mod1_child",
-                    children: [
-                        TraceModuleIO {
-                            name: "i",
-                            child: TraceUInt {
-                                id: TraceScalarId(4),
-                                name: "i",
-                                ty: UInt<4>,
-                                flow: Source,
-                            },
-                            ty: UInt<4>,
-                            flow: Source,
-                        },
-                        TraceModuleIO {
-                            name: "o",
-                            child: TraceSInt {
-                                id: TraceScalarId(5),
-                                name: "o",
-                                ty: SInt<2>,
-                                flow: Sink,
-                            },
-                            ty: SInt<2>,
-                            flow: Sink,
-                        },
-                        TraceModuleIO {
-                            name: "i2",
-                            child: TraceSInt {
-                                id: TraceScalarId(6),
-                                name: "i2",
-                                ty: SInt<2>,
-                                flow: Source,
-                            },
-                            ty: SInt<2>,
-                            flow: Source,
-                        },
-                        TraceModuleIO {
-                            name: "o2",
-                            child: TraceUInt {
-                                id: TraceScalarId(7),
-                                name: "o2",
-                                ty: UInt<4>,
-                                flow: Sink,
-                            },
-                            ty: UInt<4>,
-                            flow: Sink,
-                        },
-                    ],
-                },
-                ty: Bundle {
-                    #[hdl(flip)] /* offset = 0 */
-                    i: UInt<4>,
-                    /* offset = 4 */
-                    o: SInt<2>,
-                    #[hdl(flip)] /* offset = 6 */
-                    i2: SInt<2>,
-                    /* offset = 8 */
-                    o2: UInt<4>,
-                },
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(0),
-                ty: UInt<4>,
-            },
-            state: 0xa,
-            last_state: 0x3,
-        },
-        SimTrace {
-            id: TraceScalarId(1),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(1),
-                ty: SInt<2>,
-            },
-            state: 0x2,
-            last_state: 0x3,
-        },
-        SimTrace {
-            id: TraceScalarId(2),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(2),
-                ty: SInt<2>,
-            },
-            state: 0x2,
-            last_state: 0x2,
-        },
-        SimTrace {
-            id: TraceScalarId(3),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(3),
-                ty: UInt<4>,
-            },
-            state: 0xf,
-            last_state: 0xe,
-        },
-        SimTrace {
-            id: TraceScalarId(4),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(8),
-                ty: UInt<4>,
-            },
-            state: 0xa,
-            last_state: 0x3,
-        },
-        SimTrace {
-            id: TraceScalarId(5),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(9),
-                ty: SInt<2>,
-            },
-            state: 0x2,
-            last_state: 0x3,
-        },
-        SimTrace {
-            id: TraceScalarId(6),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(10),
-                ty: SInt<2>,
-            },
-            state: 0x2,
-            last_state: 0x2,
-        },
-        SimTrace {
-            id: TraceScalarId(7),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(11),
-                ty: UInt<4>,
-            },
-            state: 0xf,
-            last_state: 0xe,
-        },
-        SimTrace {
-            id: TraceScalarId(8),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(4),
-                ty: UInt<4>,
-            },
-            state: 0xa,
-            last_state: 0x3,
-        },
-        SimTrace {
-            id: TraceScalarId(9),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(5),
-                ty: SInt<2>,
-            },
-            state: 0x2,
-            last_state: 0x3,
-        },
-        SimTrace {
-            id: TraceScalarId(10),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(6),
-                ty: SInt<2>,
-            },
-            state: 0x2,
-            last_state: 0x2,
-        },
-        SimTrace {
-            id: TraceScalarId(11),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(7),
-                ty: UInt<4>,
-            },
-            state: 0xf,
-            last_state: 0xe,
-        },
-    ],
-    trace_writers: [
-        Running(
-            VcdWriter {
-                finished_init: true,
-                timescale: 1 ps,
-                ..
-            },
-        ),
-    ],
-    instant: 2 μs,
-    clocks_triggered: [],
-}"# {
+    if sim_debug != include_str!("sim/expected/mod1.txt") {
         panic!();
     }
     let expected = -2_hdl_i2;
@@ -1369,717 +164,12 @@ fn test_counter_sync() {
     sim.flush_traces().unwrap();
     let vcd = String::from_utf8(writer.take()).unwrap();
     println!("####### VCD:\n{vcd}\n#######");
-    if vcd
-        != r#"$timescale 1 ps $end
-$scope module counter $end
-$scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
-$upscope $end
-$var wire 4 # count $end
-$var reg 4 $ count_reg $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-0!
-1"
-b0 #
-b0 $
-$end
-#1000000
-1!
-b11 $
-b11 #
-0"
-#2000000
-0!
-#3000000
-1!
-b100 $
-b100 #
-#4000000
-0!
-#5000000
-1!
-b101 $
-b101 #
-#6000000
-0!
-#7000000
-1!
-b110 $
-b110 #
-#8000000
-0!
-#9000000
-1!
-b111 $
-b111 #
-#10000000
-0!
-#11000000
-1!
-b1000 $
-b1000 #
-#12000000
-0!
-#13000000
-1!
-b1001 $
-b1001 #
-#14000000
-0!
-#15000000
-1!
-b1010 $
-b1010 #
-#16000000
-0!
-#17000000
-1!
-b1011 $
-b1011 #
-#18000000
-0!
-#19000000
-1!
-b1100 $
-b1100 #
-#20000000
-0!
-#21000000
-1!
-b1101 $
-b1101 #
-#22000000
-0!
-#23000000
-1!
-b1110 $
-b1110 #
-#24000000
-0!
-#25000000
-1!
-b1111 $
-b1111 #
-#26000000
-0!
-#27000000
-1!
-b0 $
-b0 #
-#28000000
-0!
-#29000000
-1!
-b1 $
-b1 #
-#30000000
-0!
-#31000000
-1!
-b10 $
-b10 #
-#32000000
-0!
-#33000000
-1!
-b11 $
-b11 #
-#34000000
-0!
-#35000000
-1!
-b100 $
-b100 #
-#36000000
-0!
-#37000000
-1!
-b101 $
-b101 #
-#38000000
-0!
-#39000000
-1!
-b110 $
-b110 #
-#40000000
-0!
-#41000000
-1!
-b111 $
-b111 #
-#42000000
-0!
-#43000000
-1!
-b1000 $
-b1000 #
-#44000000
-0!
-#45000000
-1!
-b1001 $
-b1001 #
-#46000000
-0!
-#47000000
-1!
-b1010 $
-b1010 #
-#48000000
-0!
-#49000000
-1!
-b1011 $
-b1011 #
-#50000000
-0!
-#51000000
-1!
-b1100 $
-b1100 #
-#52000000
-0!
-#53000000
-1!
-b1101 $
-b1101 #
-#54000000
-0!
-#55000000
-1!
-b1110 $
-b1110 #
-#56000000
-0!
-#57000000
-1!
-b1111 $
-b1111 #
-#58000000
-0!
-#59000000
-1!
-b0 $
-b0 #
-#60000000
-0!
-#61000000
-1!
-b1 $
-b1 #
-#62000000
-0!
-#63000000
-1!
-b10 $
-b10 #
-#64000000
-0!
-#65000000
-1!
-b11 $
-b11 #
-#66000000
-"# {
+    if vcd != include_str!("sim/expected/counter_sync.vcd") {
         panic!();
     }
     let sim_debug = format!("{sim:#?}");
     println!("#######\n{sim_debug}\n#######");
-    if sim_debug
-        != r#"Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 4,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 9,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
-                                ty: SyncReset,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count_reg",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count_reg$next",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<5>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:6:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                Const {
-                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
-                    value: 1,
-                },
-                Add {
-                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
-                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    rhs: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
-                },
-                CastToUInt {
-                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
-                    dest_width: 4,
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:3:1
-                IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                Const {
-                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
-                    value: 3,
-                },
-                // at: module-XXXXXXXXXX.rs:3:1
-                IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
-                },
-                AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
-                },
-                BranchIfSmallZero {
-                    target: 14,
-                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
-                },
-                BranchIfSmallNonZero {
-                    target: 13,
-                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
-                },
-                Branch {
-                    target: 14,
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
-                },
-                NotSmall {
-                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                Return,
-            ],
-            ..
-        },
-        pc: 15,
-        small_slots: StatePart {
-            value: [
-                18446744073709551614,
-                0,
-                1,
-                0,
-            ],
-        },
-        big_slots: StatePart {
-            value: [
-                1,
-                0,
-                3,
-                3,
-                4,
-                3,
-                1,
-                4,
-                4,
-            ],
-        },
-    },
-    io: Instance {
-        name: <simulator>::counter,
-        instantiated: Module {
-            name: counter,
-            ..
-        },
-    },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: SyncReset,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
-                                ty: SyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SyncReset,
-                                layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SyncReset,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd.rst: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SyncReset,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.count: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-    },
-    made_initial_step: true,
-    needs_settle: false,
-    trace_decls: TraceModule {
-        name: "counter",
-        children: [
-            TraceModuleIO {
-                name: "cd",
-                child: TraceBundle {
-                    name: "cd",
-                    fields: [
-                        TraceClock {
-                            id: TraceScalarId(0),
-                            name: "clk",
-                            flow: Source,
-                        },
-                        TraceSyncReset {
-                            id: TraceScalarId(1),
-                            name: "rst",
-                            flow: Source,
-                        },
-                    ],
-                    ty: Bundle {
-                        /* offset = 0 */
-                        clk: Clock,
-                        /* offset = 1 */
-                        rst: SyncReset,
-                    },
-                    flow: Source,
-                },
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: SyncReset,
-                },
-                flow: Source,
-            },
-            TraceModuleIO {
-                name: "count",
-                child: TraceUInt {
-                    id: TraceScalarId(2),
-                    name: "count",
-                    ty: UInt<4>,
-                    flow: Sink,
-                },
-                ty: UInt<4>,
-                flow: Sink,
-            },
-            TraceReg {
-                name: "count_reg",
-                child: TraceUInt {
-                    id: TraceScalarId(3),
-                    name: "count_reg",
-                    ty: UInt<4>,
-                    flow: Duplex,
-                },
-                ty: UInt<4>,
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(0),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(1),
-            kind: BigSyncReset {
-                index: StatePartIndex<BigSlots>(1),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(2),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(2),
-                ty: UInt<4>,
-            },
-            state: 0x3,
-            last_state: 0x2,
-        },
-        SimTrace {
-            id: TraceScalarId(3),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(3),
-                ty: UInt<4>,
-            },
-            state: 0x3,
-            last_state: 0x3,
-        },
-    ],
-    trace_writers: [
-        Running(
-            VcdWriter {
-                finished_init: true,
-                timescale: 1 ps,
-                ..
-            },
-        ),
-    ],
-    instant: 66 μs,
-    clocks_triggered: [
-        StatePartIndex<SmallSlots>(1),
-    ],
-}"# {
+    if sim_debug != include_str!("sim/expected/counter_sync.txt") {
         panic!();
     }
 }
@@ -2122,739 +212,12 @@ fn test_counter_async() {
     sim.flush_traces().unwrap();
     let vcd = String::from_utf8(writer.take()).unwrap();
     println!("####### VCD:\n{vcd}\n#######");
-    if vcd
-        != r#"$timescale 1 ps $end
-$scope module counter $end
-$scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
-$upscope $end
-$var wire 4 # count $end
-$var reg 4 $ count_reg $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-0!
-0"
-b0 #
-b0 $
-$end
-#500000
-1"
-b11 #
-b11 $
-#1000000
-1!
-#1500000
-0"
-#2000000
-0!
-#3000000
-1!
-b100 $
-b100 #
-#4000000
-0!
-#5000000
-1!
-b101 $
-b101 #
-#6000000
-0!
-#7000000
-1!
-b110 $
-b110 #
-#8000000
-0!
-#9000000
-1!
-b111 $
-b111 #
-#10000000
-0!
-#11000000
-1!
-b1000 $
-b1000 #
-#12000000
-0!
-#13000000
-1!
-b1001 $
-b1001 #
-#14000000
-0!
-#15000000
-1!
-b1010 $
-b1010 #
-#16000000
-0!
-#17000000
-1!
-b1011 $
-b1011 #
-#18000000
-0!
-#19000000
-1!
-b1100 $
-b1100 #
-#20000000
-0!
-#21000000
-1!
-b1101 $
-b1101 #
-#22000000
-0!
-#23000000
-1!
-b1110 $
-b1110 #
-#24000000
-0!
-#25000000
-1!
-b1111 $
-b1111 #
-#26000000
-0!
-#27000000
-1!
-b0 $
-b0 #
-#28000000
-0!
-#29000000
-1!
-b1 $
-b1 #
-#30000000
-0!
-#31000000
-1!
-b10 $
-b10 #
-#32000000
-0!
-#33000000
-1!
-b11 $
-b11 #
-#34000000
-0!
-#35000000
-1!
-b100 $
-b100 #
-#36000000
-0!
-#37000000
-1!
-b101 $
-b101 #
-#38000000
-0!
-#39000000
-1!
-b110 $
-b110 #
-#40000000
-0!
-#41000000
-1!
-b111 $
-b111 #
-#42000000
-0!
-#43000000
-1!
-b1000 $
-b1000 #
-#44000000
-0!
-#45000000
-1!
-b1001 $
-b1001 #
-#46000000
-0!
-#47000000
-1!
-b1010 $
-b1010 #
-#48000000
-0!
-#49000000
-1!
-b1011 $
-b1011 #
-#50000000
-0!
-#51000000
-1!
-b1100 $
-b1100 #
-#52000000
-0!
-#53000000
-1!
-b1101 $
-b1101 #
-#54000000
-0!
-#55000000
-1!
-b1110 $
-b1110 #
-#56000000
-0!
-#57000000
-1!
-b1111 $
-b1111 #
-#58000000
-0!
-#59000000
-1!
-b0 $
-b0 #
-#60000000
-0!
-#61000000
-1!
-b1 $
-b1 #
-#62000000
-0!
-#63000000
-1!
-b10 $
-b10 #
-#64000000
-0!
-#65000000
-1!
-b11 $
-b11 #
-#66000000
-"# {
+    if vcd != include_str!("sim/expected/counter_async.vcd") {
         panic!();
     }
     let sim_debug = format!("{sim:#?}");
     println!("#######\n{sim_debug}\n#######");
-    if sim_debug
-        != r#"Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 4,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 10,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
-                                ty: AsyncReset,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count_reg",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count_reg$next",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<5>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:1:1
-                Const {
-                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
-                    value: 1,
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
-                },
-                // at: module-XXXXXXXXXX.rs:3:1
-                IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                Const {
-                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
-                    value: 3,
-                },
-                // at: module-XXXXXXXXXX.rs:3:1
-                BranchIfZero {
-                    target: 6,
-                    value: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                Add {
-                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
-                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    rhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
-                },
-                CastToUInt {
-                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
-                    dest_width: 4,
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:6:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:3:1
-                IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
-                },
-                AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
-                },
-                BranchIfSmallNonZero {
-                    target: 16,
-                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
-                },
-                BranchIfSmallZero {
-                    target: 17,
-                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
-                },
-                Branch {
-                    target: 17,
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
-                },
-                NotSmall {
-                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                Return,
-            ],
-            ..
-        },
-        pc: 18,
-        small_slots: StatePart {
-            value: [
-                18446744073709551614,
-                0,
-                1,
-                0,
-            ],
-        },
-        big_slots: StatePart {
-            value: [
-                1,
-                0,
-                3,
-                3,
-                4,
-                3,
-                0,
-                1,
-                4,
-                4,
-            ],
-        },
-    },
-    io: Instance {
-        name: <simulator>::counter,
-        instantiated: Module {
-            name: counter,
-            ..
-        },
-    },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: AsyncReset,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
-                                ty: AsyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: AsyncReset,
-                                layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: AsyncReset,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd.rst: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: AsyncReset,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: AsyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.count: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-    },
-    made_initial_step: true,
-    needs_settle: false,
-    trace_decls: TraceModule {
-        name: "counter",
-        children: [
-            TraceModuleIO {
-                name: "cd",
-                child: TraceBundle {
-                    name: "cd",
-                    fields: [
-                        TraceClock {
-                            id: TraceScalarId(0),
-                            name: "clk",
-                            flow: Source,
-                        },
-                        TraceAsyncReset {
-                            id: TraceScalarId(1),
-                            name: "rst",
-                            flow: Source,
-                        },
-                    ],
-                    ty: Bundle {
-                        /* offset = 0 */
-                        clk: Clock,
-                        /* offset = 1 */
-                        rst: AsyncReset,
-                    },
-                    flow: Source,
-                },
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: AsyncReset,
-                },
-                flow: Source,
-            },
-            TraceModuleIO {
-                name: "count",
-                child: TraceUInt {
-                    id: TraceScalarId(2),
-                    name: "count",
-                    ty: UInt<4>,
-                    flow: Sink,
-                },
-                ty: UInt<4>,
-                flow: Sink,
-            },
-            TraceReg {
-                name: "count_reg",
-                child: TraceUInt {
-                    id: TraceScalarId(3),
-                    name: "count_reg",
-                    ty: UInt<4>,
-                    flow: Duplex,
-                },
-                ty: UInt<4>,
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(0),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(1),
-            kind: BigAsyncReset {
-                index: StatePartIndex<BigSlots>(1),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(2),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(2),
-                ty: UInt<4>,
-            },
-            state: 0x3,
-            last_state: 0x2,
-        },
-        SimTrace {
-            id: TraceScalarId(3),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(3),
-                ty: UInt<4>,
-            },
-            state: 0x3,
-            last_state: 0x3,
-        },
-    ],
-    trace_writers: [
-        Running(
-            VcdWriter {
-                finished_init: true,
-                timescale: 1 ps,
-                ..
-            },
-        ),
-    ],
-    instant: 66 μs,
-    clocks_triggered: [
-        StatePartIndex<SmallSlots>(1),
-    ],
-}"# {
+    if sim_debug != include_str!("sim/expected/counter_async.txt") {
         panic!();
     }
 }
@@ -2920,876 +283,12 @@ fn test_shift_register() {
     sim.flush_traces().unwrap();
     let vcd = String::from_utf8(writer.take()).unwrap();
     println!("####### VCD:\n{vcd}\n#######");
-    if vcd
-        != r#"$timescale 1 ps $end
-$scope module shift_register $end
-$scope struct cd $end
-$var wire 1 ! clk $end
-$var wire 1 " rst $end
-$upscope $end
-$var wire 1 # d $end
-$var wire 1 $ q $end
-$var reg 1 % reg0 $end
-$var reg 1 & reg1 $end
-$var reg 1 ' reg2 $end
-$var reg 1 ( reg3 $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-0!
-1"
-0#
-0$
-0%
-0&
-0'
-0(
-$end
-#1000000
-1!
-#1100000
-0"
-#2000000
-0!
-#3000000
-1!
-#4000000
-0!
-1#
-#5000000
-1!
-1%
-#6000000
-0!
-#7000000
-1!
-1&
-#8000000
-0!
-0#
-#9000000
-1!
-0%
-1'
-#10000000
-0!
-#11000000
-1!
-0&
-1(
-1$
-#12000000
-0!
-1#
-#13000000
-1!
-1%
-0'
-#14000000
-0!
-0#
-#15000000
-1!
-0%
-1&
-0(
-0$
-#16000000
-0!
-1#
-#17000000
-1!
-1%
-0&
-1'
-#18000000
-0!
-#19000000
-1!
-1&
-0'
-1(
-1$
-#20000000
-0!
-#21000000
-1!
-1'
-0(
-0$
-#22000000
-0!
-#23000000
-1!
-1(
-1$
-#24000000
-0!
-0#
-#25000000
-1!
-0%
-#26000000
-0!
-#27000000
-1!
-0&
-#28000000
-0!
-#29000000
-1!
-0'
-#30000000
-0!
-#31000000
-1!
-0(
-0$
-#32000000
-0!
-#33000000
-1!
-#34000000
-0!
-#35000000
-1!
-#36000000
-0!
-#37000000
-1!
-#38000000
-0!
-#39000000
-1!
-#40000000
-0!
-#41000000
-1!
-#42000000
-0!
-#43000000
-1!
-#44000000
-0!
-#45000000
-1!
-#46000000
-0!
-#47000000
-1!
-#48000000
-0!
-#49000000
-1!
-#50000000
-0!
-#51000000
-1!
-#52000000
-0!
-#53000000
-1!
-#54000000
-0!
-#55000000
-1!
-#56000000
-0!
-#57000000
-1!
-#58000000
-0!
-#59000000
-1!
-#60000000
-0!
-#61000000
-1!
-#62000000
-0!
-#63000000
-1!
-#64000000
-0!
-#65000000
-1!
-#66000000
-"# {
+    if vcd != include_str!("sim/expected/shift_register.vcd") {
         panic!();
     }
     let sim_debug = format!("{sim:#?}");
     println!("#######\n{sim_debug}\n#######");
-    if sim_debug
-        != r#"Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 4,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 13,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
-                                ty: SyncReset,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:13:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
-                    src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:12:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:10:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:8:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:6:1
-                Copy {
-                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:5:1
-                IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                Const {
-                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
-                    value: 0,
-                },
-                // at: module-XXXXXXXXXX.rs:5:1
-                IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
-                },
-                AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
-                },
-                BranchIfSmallZero {
-                    target: 14,
-                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
-                },
-                BranchIfSmallNonZero {
-                    target: 13,
-                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
-                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
-                },
-                Branch {
-                    target: 14,
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:7:1
-                BranchIfSmallZero {
-                    target: 19,
-                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
-                },
-                BranchIfSmallNonZero {
-                    target: 18,
-                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
-                },
-                Branch {
-                    target: 19,
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:9:1
-                BranchIfSmallZero {
-                    target: 24,
-                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
-                },
-                BranchIfSmallNonZero {
-                    target: 23,
-                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
-                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
-                },
-                Branch {
-                    target: 24,
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:11:1
-                BranchIfSmallZero {
-                    target: 29,
-                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
-                },
-                BranchIfSmallNonZero {
-                    target: 28,
-                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
-                    src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
-                },
-                Branch {
-                    target: 29,
-                },
-                Copy {
-                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:5:1
-                NotSmall {
-                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                Return,
-            ],
-            ..
-        },
-        pc: 30,
-        small_slots: StatePart {
-            value: [
-                18446744073709551614,
-                0,
-                1,
-                0,
-            ],
-        },
-        big_slots: StatePart {
-            value: [
-                1,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-            ],
-        },
-    },
-    io: Instance {
-        name: <simulator>::shift_register,
-        instantiated: Module {
-            name: shift_register,
-            ..
-        },
-    },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::shift_register,
-            instantiated: Module {
-                name: shift_register,
-                ..
-            },
-        }.cd: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: SyncReset,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
-                                ty: SyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SyncReset,
-                                layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SyncReset,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::shift_register,
-            instantiated: Module {
-                name: shift_register,
-                ..
-            },
-        }.cd.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::shift_register,
-            instantiated: Module {
-                name: shift_register,
-                ..
-            },
-        }.cd.rst: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SyncReset,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::shift_register,
-            instantiated: Module {
-                name: shift_register,
-                ..
-            },
-        }.d: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::shift_register,
-            instantiated: Module {
-                name: shift_register,
-                ..
-            },
-        }.q: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
-            },
-            write: None,
-        },
-    },
-    made_initial_step: true,
-    needs_settle: false,
-    trace_decls: TraceModule {
-        name: "shift_register",
-        children: [
-            TraceModuleIO {
-                name: "cd",
-                child: TraceBundle {
-                    name: "cd",
-                    fields: [
-                        TraceClock {
-                            id: TraceScalarId(0),
-                            name: "clk",
-                            flow: Source,
-                        },
-                        TraceSyncReset {
-                            id: TraceScalarId(1),
-                            name: "rst",
-                            flow: Source,
-                        },
-                    ],
-                    ty: Bundle {
-                        /* offset = 0 */
-                        clk: Clock,
-                        /* offset = 1 */
-                        rst: SyncReset,
-                    },
-                    flow: Source,
-                },
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: SyncReset,
-                },
-                flow: Source,
-            },
-            TraceModuleIO {
-                name: "d",
-                child: TraceBool {
-                    id: TraceScalarId(2),
-                    name: "d",
-                    flow: Source,
-                },
-                ty: Bool,
-                flow: Source,
-            },
-            TraceModuleIO {
-                name: "q",
-                child: TraceBool {
-                    id: TraceScalarId(3),
-                    name: "q",
-                    flow: Sink,
-                },
-                ty: Bool,
-                flow: Sink,
-            },
-            TraceReg {
-                name: "reg0",
-                child: TraceBool {
-                    id: TraceScalarId(4),
-                    name: "reg0",
-                    flow: Duplex,
-                },
-                ty: Bool,
-            },
-            TraceReg {
-                name: "reg1",
-                child: TraceBool {
-                    id: TraceScalarId(5),
-                    name: "reg1",
-                    flow: Duplex,
-                },
-                ty: Bool,
-            },
-            TraceReg {
-                name: "reg2",
-                child: TraceBool {
-                    id: TraceScalarId(6),
-                    name: "reg2",
-                    flow: Duplex,
-                },
-                ty: Bool,
-            },
-            TraceReg {
-                name: "reg3",
-                child: TraceBool {
-                    id: TraceScalarId(7),
-                    name: "reg3",
-                    flow: Duplex,
-                },
-                ty: Bool,
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(0),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(1),
-            kind: BigSyncReset {
-                index: StatePartIndex<BigSlots>(1),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(2),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(2),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(3),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(3),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(4),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(4),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(5),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(7),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(6),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(9),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(7),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(11),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-    ],
-    trace_writers: [
-        Running(
-            VcdWriter {
-                finished_init: true,
-                timescale: 1 ps,
-                ..
-            },
-        ),
-    ],
-    instant: 66 μs,
-    clocks_triggered: [
-        StatePartIndex<SmallSlots>(1),
-    ],
-}"# {
+    if sim_debug != include_str!("sim/expected/shift_register.txt") {
         panic!();
     }
 }
diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt
new file mode 100644
index 0000000..189056b
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/connect_const.txt
@@ -0,0 +1,130 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
+                    value: 5,
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Return,
+            ],
+            ..
+        },
+        pc: 2,
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                5,
+                5,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::connect_const,
+        instantiated: Module {
+            name: connect_const,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::connect_const,
+            instantiated: Module {
+                name: connect_const,
+                ..
+            },
+        }.o: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "connect_const",
+        children: [
+            TraceModuleIO {
+                name: "o",
+                child: TraceUInt {
+                    id: TraceScalarId(0),
+                    name: "o",
+                    ty: UInt<8>,
+                    flow: Sink,
+                },
+                ty: UInt<8>,
+                flow: Sink,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<8>,
+            },
+            state: 0x05,
+            last_state: 0x05,
+        },
+    ],
+    trace_writers: [],
+    instant: 0 s,
+    clocks_triggered: [],
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
new file mode 100644
index 0000000..5e6f0eb
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
@@ -0,0 +1,217 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 5,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
+                                ty: AsyncReset,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: AsyncReset,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    value: 1,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
+                    src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
+                    src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Return,
+            ],
+            ..
+        },
+        pc: 5,
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                1,
+                1,
+                1,
+                1,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::connect_const_reset,
+        instantiated: Module {
+            name: connect_const_reset,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::connect_const_reset,
+            instantiated: Module {
+                name: connect_const_reset,
+                ..
+            },
+        }.bit_out: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::connect_const_reset,
+            instantiated: Module {
+                name: connect_const_reset,
+                ..
+            },
+        }.reset_out: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: AsyncReset,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
+                                ty: AsyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "connect_const_reset",
+        children: [
+            TraceModuleIO {
+                name: "reset_out",
+                child: TraceAsyncReset {
+                    id: TraceScalarId(0),
+                    name: "reset_out",
+                    flow: Sink,
+                },
+                ty: AsyncReset,
+                flow: Sink,
+            },
+            TraceModuleIO {
+                name: "bit_out",
+                child: TraceBool {
+                    id: TraceScalarId(1),
+                    name: "bit_out",
+                    flow: Sink,
+                },
+                ty: Bool,
+                flow: Sink,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigAsyncReset {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+    ],
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 1 μs,
+    clocks_triggered: [],
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.vcd b/crates/fayalite/tests/sim/expected/connect_const_reset.vcd
new file mode 100644
index 0000000..50b427c
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/connect_const_reset.vcd
@@ -0,0 +1,11 @@
+$timescale 1 ps $end
+$scope module connect_const_reset $end
+$var wire 1 ! reset_out $end
+$var wire 1 " bit_out $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+1!
+1"
+$end
+#1000000
diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt
new file mode 100644
index 0000000..b72ebbb
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/counter_async.txt
@@ -0,0 +1,509 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 4,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 10,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
+                                ty: AsyncReset,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count_reg",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count_reg$next",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<5>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
+                    value: 1,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
+                    value: 3,
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                BranchIfZero {
+                    target: 6,
+                    value: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Add {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
+                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
+                },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
+                    dest_width: 4,
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
+                },
+                AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallNonZero {
+                    target: 16,
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallZero {
+                    target: 17,
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                },
+                Branch {
+                    target: 17,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                NotSmall {
+                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Return,
+            ],
+            ..
+        },
+        pc: 18,
+        small_slots: StatePart {
+            value: [
+                18446744073709551614,
+                0,
+                1,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                0,
+                3,
+                3,
+                4,
+                3,
+                0,
+                1,
+                4,
+                4,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::counter,
+        instantiated: Module {
+            name: counter,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.cd: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: AsyncReset,
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
+                                ty: AsyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Clock,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Clock,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: AsyncReset,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: AsyncReset,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.cd.clk: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.cd.rst: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: AsyncReset,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: AsyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.count: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<4>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "counter",
+        children: [
+            TraceModuleIO {
+                name: "cd",
+                child: TraceBundle {
+                    name: "cd",
+                    fields: [
+                        TraceClock {
+                            id: TraceScalarId(0),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceAsyncReset {
+                            id: TraceScalarId(1),
+                            name: "rst",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        rst: AsyncReset,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: AsyncReset,
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "count",
+                child: TraceUInt {
+                    id: TraceScalarId(2),
+                    name: "count",
+                    ty: UInt<4>,
+                    flow: Sink,
+                },
+                ty: UInt<4>,
+                flow: Sink,
+            },
+            TraceReg {
+                name: "count_reg",
+                child: TraceUInt {
+                    id: TraceScalarId(3),
+                    name: "count_reg",
+                    ty: UInt<4>,
+                    flow: Duplex,
+                },
+                ty: UInt<4>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigAsyncReset {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(2),
+                ty: UInt<4>,
+            },
+            state: 0x3,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<4>,
+            },
+            state: 0x3,
+            last_state: 0x3,
+        },
+    ],
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 66 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+    ],
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/counter_async.vcd b/crates/fayalite/tests/sim/expected/counter_async.vcd
new file mode 100644
index 0000000..a4b2ee9
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/counter_async.vcd
@@ -0,0 +1,217 @@
+$timescale 1 ps $end
+$scope module counter $end
+$scope struct cd $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$upscope $end
+$var wire 4 # count $end
+$var reg 4 $ count_reg $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+0"
+b0 #
+b0 $
+$end
+#500000
+1"
+b11 #
+b11 $
+#1000000
+1!
+#1500000
+0"
+#2000000
+0!
+#3000000
+1!
+b100 $
+b100 #
+#4000000
+0!
+#5000000
+1!
+b101 $
+b101 #
+#6000000
+0!
+#7000000
+1!
+b110 $
+b110 #
+#8000000
+0!
+#9000000
+1!
+b111 $
+b111 #
+#10000000
+0!
+#11000000
+1!
+b1000 $
+b1000 #
+#12000000
+0!
+#13000000
+1!
+b1001 $
+b1001 #
+#14000000
+0!
+#15000000
+1!
+b1010 $
+b1010 #
+#16000000
+0!
+#17000000
+1!
+b1011 $
+b1011 #
+#18000000
+0!
+#19000000
+1!
+b1100 $
+b1100 #
+#20000000
+0!
+#21000000
+1!
+b1101 $
+b1101 #
+#22000000
+0!
+#23000000
+1!
+b1110 $
+b1110 #
+#24000000
+0!
+#25000000
+1!
+b1111 $
+b1111 #
+#26000000
+0!
+#27000000
+1!
+b0 $
+b0 #
+#28000000
+0!
+#29000000
+1!
+b1 $
+b1 #
+#30000000
+0!
+#31000000
+1!
+b10 $
+b10 #
+#32000000
+0!
+#33000000
+1!
+b11 $
+b11 #
+#34000000
+0!
+#35000000
+1!
+b100 $
+b100 #
+#36000000
+0!
+#37000000
+1!
+b101 $
+b101 #
+#38000000
+0!
+#39000000
+1!
+b110 $
+b110 #
+#40000000
+0!
+#41000000
+1!
+b111 $
+b111 #
+#42000000
+0!
+#43000000
+1!
+b1000 $
+b1000 #
+#44000000
+0!
+#45000000
+1!
+b1001 $
+b1001 #
+#46000000
+0!
+#47000000
+1!
+b1010 $
+b1010 #
+#48000000
+0!
+#49000000
+1!
+b1011 $
+b1011 #
+#50000000
+0!
+#51000000
+1!
+b1100 $
+b1100 #
+#52000000
+0!
+#53000000
+1!
+b1101 $
+b1101 #
+#54000000
+0!
+#55000000
+1!
+b1110 $
+b1110 #
+#56000000
+0!
+#57000000
+1!
+b1111 $
+b1111 #
+#58000000
+0!
+#59000000
+1!
+b0 $
+b0 #
+#60000000
+0!
+#61000000
+1!
+b1 $
+b1 #
+#62000000
+0!
+#63000000
+1!
+b10 $
+b10 #
+#64000000
+0!
+#65000000
+1!
+b11 $
+b11 #
+#66000000
diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt
new file mode 100644
index 0000000..dbb6134
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/counter_sync.txt
@@ -0,0 +1,490 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 4,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 9,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count_reg",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count_reg$next",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<5>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:6:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
+                    value: 1,
+                },
+                Add {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
+                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
+                },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
+                    dest_width: 4,
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
+                    value: 3,
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
+                },
+                AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallZero {
+                    target: 14,
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallNonZero {
+                    target: 13,
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                },
+                Branch {
+                    target: 14,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                NotSmall {
+                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Return,
+            ],
+            ..
+        },
+        pc: 15,
+        small_slots: StatePart {
+            value: [
+                18446744073709551614,
+                0,
+                1,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                0,
+                3,
+                3,
+                4,
+                3,
+                1,
+                4,
+                4,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::counter,
+        instantiated: Module {
+            name: counter,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.cd: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: SyncReset,
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
+                                ty: SyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Clock,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Clock,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: SyncReset,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: SyncReset,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.cd.clk: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.cd.rst: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: SyncReset,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: SyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::counter,
+            instantiated: Module {
+                name: counter,
+                ..
+            },
+        }.count: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<4>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(counter: counter).counter::count",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "counter",
+        children: [
+            TraceModuleIO {
+                name: "cd",
+                child: TraceBundle {
+                    name: "cd",
+                    fields: [
+                        TraceClock {
+                            id: TraceScalarId(0),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceSyncReset {
+                            id: TraceScalarId(1),
+                            name: "rst",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        rst: SyncReset,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: SyncReset,
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "count",
+                child: TraceUInt {
+                    id: TraceScalarId(2),
+                    name: "count",
+                    ty: UInt<4>,
+                    flow: Sink,
+                },
+                ty: UInt<4>,
+                flow: Sink,
+            },
+            TraceReg {
+                name: "count_reg",
+                child: TraceUInt {
+                    id: TraceScalarId(3),
+                    name: "count_reg",
+                    ty: UInt<4>,
+                    flow: Duplex,
+                },
+                ty: UInt<4>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigSyncReset {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(2),
+                ty: UInt<4>,
+            },
+            state: 0x3,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<4>,
+            },
+            state: 0x3,
+            last_state: 0x3,
+        },
+    ],
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 66 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+    ],
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/counter_sync.vcd b/crates/fayalite/tests/sim/expected/counter_sync.vcd
new file mode 100644
index 0000000..bf6249e
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/counter_sync.vcd
@@ -0,0 +1,214 @@
+$timescale 1 ps $end
+$scope module counter $end
+$scope struct cd $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$upscope $end
+$var wire 4 # count $end
+$var reg 4 $ count_reg $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+1"
+b0 #
+b0 $
+$end
+#1000000
+1!
+b11 $
+b11 #
+0"
+#2000000
+0!
+#3000000
+1!
+b100 $
+b100 #
+#4000000
+0!
+#5000000
+1!
+b101 $
+b101 #
+#6000000
+0!
+#7000000
+1!
+b110 $
+b110 #
+#8000000
+0!
+#9000000
+1!
+b111 $
+b111 #
+#10000000
+0!
+#11000000
+1!
+b1000 $
+b1000 #
+#12000000
+0!
+#13000000
+1!
+b1001 $
+b1001 #
+#14000000
+0!
+#15000000
+1!
+b1010 $
+b1010 #
+#16000000
+0!
+#17000000
+1!
+b1011 $
+b1011 #
+#18000000
+0!
+#19000000
+1!
+b1100 $
+b1100 #
+#20000000
+0!
+#21000000
+1!
+b1101 $
+b1101 #
+#22000000
+0!
+#23000000
+1!
+b1110 $
+b1110 #
+#24000000
+0!
+#25000000
+1!
+b1111 $
+b1111 #
+#26000000
+0!
+#27000000
+1!
+b0 $
+b0 #
+#28000000
+0!
+#29000000
+1!
+b1 $
+b1 #
+#30000000
+0!
+#31000000
+1!
+b10 $
+b10 #
+#32000000
+0!
+#33000000
+1!
+b11 $
+b11 #
+#34000000
+0!
+#35000000
+1!
+b100 $
+b100 #
+#36000000
+0!
+#37000000
+1!
+b101 $
+b101 #
+#38000000
+0!
+#39000000
+1!
+b110 $
+b110 #
+#40000000
+0!
+#41000000
+1!
+b111 $
+b111 #
+#42000000
+0!
+#43000000
+1!
+b1000 $
+b1000 #
+#44000000
+0!
+#45000000
+1!
+b1001 $
+b1001 #
+#46000000
+0!
+#47000000
+1!
+b1010 $
+b1010 #
+#48000000
+0!
+#49000000
+1!
+b1011 $
+b1011 #
+#50000000
+0!
+#51000000
+1!
+b1100 $
+b1100 #
+#52000000
+0!
+#53000000
+1!
+b1101 $
+b1101 #
+#54000000
+0!
+#55000000
+1!
+b1110 $
+b1110 #
+#56000000
+0!
+#57000000
+1!
+b1111 $
+b1111 #
+#58000000
+0!
+#59000000
+1!
+b0 $
+b0 #
+#60000000
+0!
+#61000000
+1!
+b1 $
+b1 #
+#62000000
+0!
+#63000000
+1!
+b10 $
+b10 #
+#64000000
+0!
+#65000000
+1!
+b11 $
+b11 #
+#66000000
diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt
new file mode 100644
index 0000000..74ba140
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/mod1.txt
@@ -0,0 +1,798 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 17,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.i",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.o",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::child.i",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::child.o",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::child.i2",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::child.o2",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:4:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:2:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX-2.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
+                    value: 15,
+                },
+                Const {
+                    dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
+                    value: 5,
+                },
+                CmpLt {
+                    dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
+                },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
+                    dest_width: 4,
+                },
+                // at: module-XXXXXXXXXX-2.rs:7:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX-2.rs:8:1
+                BranchIfZero {
+                    target: 11,
+                    value: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX-2.rs:9:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:2:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX-2.rs:1:1
+                CastToSInt {
+                    dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
+                    dest_width: 2,
+                },
+                // at: module-XXXXXXXXXX-2.rs:6:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:2:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Return,
+            ],
+            ..
+        },
+        pc: 17,
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                10,
+                -2,
+                -2,
+                15,
+                10,
+                -2,
+                -2,
+                15,
+                10,
+                -2,
+                -2,
+                15,
+                -2,
+                14,
+                5,
+                1,
+                15,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::mod1,
+        instantiated: Module {
+            name: mod1,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::mod1,
+            instantiated: Module {
+                name: mod1,
+                ..
+            },
+        }.o: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    #[hdl(flip)] /* offset = 0 */
+                    i: UInt<4>,
+                    /* offset = 4 */
+                    o: SInt<2>,
+                    #[hdl(flip)] /* offset = 6 */
+                    i2: SInt<2>,
+                    /* offset = 8 */
+                    o2: UInt<4>,
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 4,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.i",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.o",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: UInt<4>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: UInt<4>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: SInt<2>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: SInt<2>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(2),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: SInt<2>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: SInt<2>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(3),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: UInt<4>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: UInt<4>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 4 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::mod1,
+            instantiated: Module {
+                name: mod1,
+                ..
+            },
+        }.o.i: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<4>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::mod1,
+            instantiated: Module {
+                name: mod1,
+                ..
+            },
+        }.o.i2: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: SInt<2>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: SInt<2>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::mod1,
+            instantiated: Module {
+                name: mod1,
+                ..
+            },
+        }.o.o: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: SInt<2>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: SInt<2>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::mod1,
+            instantiated: Module {
+                name: mod1,
+                ..
+            },
+        }.o.o2: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<4>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "mod1",
+        children: [
+            TraceModuleIO {
+                name: "o",
+                child: TraceBundle {
+                    name: "o",
+                    fields: [
+                        TraceUInt {
+                            id: TraceScalarId(0),
+                            name: "i",
+                            ty: UInt<4>,
+                            flow: Source,
+                        },
+                        TraceSInt {
+                            id: TraceScalarId(1),
+                            name: "o",
+                            ty: SInt<2>,
+                            flow: Sink,
+                        },
+                        TraceSInt {
+                            id: TraceScalarId(2),
+                            name: "i2",
+                            ty: SInt<2>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            id: TraceScalarId(3),
+                            name: "o2",
+                            ty: UInt<4>,
+                            flow: Sink,
+                        },
+                    ],
+                    ty: Bundle {
+                        #[hdl(flip)] /* offset = 0 */
+                        i: UInt<4>,
+                        /* offset = 4 */
+                        o: SInt<2>,
+                        #[hdl(flip)] /* offset = 6 */
+                        i2: SInt<2>,
+                        /* offset = 8 */
+                        o2: UInt<4>,
+                    },
+                    flow: Sink,
+                },
+                ty: Bundle {
+                    #[hdl(flip)] /* offset = 0 */
+                    i: UInt<4>,
+                    /* offset = 4 */
+                    o: SInt<2>,
+                    #[hdl(flip)] /* offset = 6 */
+                    i2: SInt<2>,
+                    /* offset = 8 */
+                    o2: UInt<4>,
+                },
+                flow: Sink,
+            },
+            TraceInstance {
+                name: "child",
+                instance_io: TraceBundle {
+                    name: "child",
+                    fields: [
+                        TraceUInt {
+                            id: TraceScalarId(8),
+                            name: "i",
+                            ty: UInt<4>,
+                            flow: Sink,
+                        },
+                        TraceSInt {
+                            id: TraceScalarId(9),
+                            name: "o",
+                            ty: SInt<2>,
+                            flow: Source,
+                        },
+                        TraceSInt {
+                            id: TraceScalarId(10),
+                            name: "i2",
+                            ty: SInt<2>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            id: TraceScalarId(11),
+                            name: "o2",
+                            ty: UInt<4>,
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        #[hdl(flip)] /* offset = 0 */
+                        i: UInt<4>,
+                        /* offset = 4 */
+                        o: SInt<2>,
+                        #[hdl(flip)] /* offset = 6 */
+                        i2: SInt<2>,
+                        /* offset = 8 */
+                        o2: UInt<4>,
+                    },
+                    flow: Source,
+                },
+                module: TraceModule {
+                    name: "mod1_child",
+                    children: [
+                        TraceModuleIO {
+                            name: "i",
+                            child: TraceUInt {
+                                id: TraceScalarId(4),
+                                name: "i",
+                                ty: UInt<4>,
+                                flow: Source,
+                            },
+                            ty: UInt<4>,
+                            flow: Source,
+                        },
+                        TraceModuleIO {
+                            name: "o",
+                            child: TraceSInt {
+                                id: TraceScalarId(5),
+                                name: "o",
+                                ty: SInt<2>,
+                                flow: Sink,
+                            },
+                            ty: SInt<2>,
+                            flow: Sink,
+                        },
+                        TraceModuleIO {
+                            name: "i2",
+                            child: TraceSInt {
+                                id: TraceScalarId(6),
+                                name: "i2",
+                                ty: SInt<2>,
+                                flow: Source,
+                            },
+                            ty: SInt<2>,
+                            flow: Source,
+                        },
+                        TraceModuleIO {
+                            name: "o2",
+                            child: TraceUInt {
+                                id: TraceScalarId(7),
+                                name: "o2",
+                                ty: UInt<4>,
+                                flow: Sink,
+                            },
+                            ty: UInt<4>,
+                            flow: Sink,
+                        },
+                    ],
+                },
+                ty: Bundle {
+                    #[hdl(flip)] /* offset = 0 */
+                    i: UInt<4>,
+                    /* offset = 4 */
+                    o: SInt<2>,
+                    #[hdl(flip)] /* offset = 6 */
+                    i2: SInt<2>,
+                    /* offset = 8 */
+                    o2: UInt<4>,
+                },
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<4>,
+            },
+            state: 0xa,
+            last_state: 0x3,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(1),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x3,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(2),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<4>,
+            },
+            state: 0xf,
+            last_state: 0xe,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(8),
+                ty: UInt<4>,
+            },
+            state: 0xa,
+            last_state: 0x3,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(9),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x3,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(10),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(11),
+                ty: UInt<4>,
+            },
+            state: 0xf,
+            last_state: 0xe,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(4),
+                ty: UInt<4>,
+            },
+            state: 0xa,
+            last_state: 0x3,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(5),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x3,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(6),
+                ty: SInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(7),
+                ty: UInt<4>,
+            },
+            state: 0xf,
+            last_state: 0xe,
+        },
+    ],
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 2 μs,
+    clocks_triggered: [],
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/mod1.vcd b/crates/fayalite/tests/sim/expected/mod1.vcd
new file mode 100644
index 0000000..0d1a6f4
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/mod1.vcd
@@ -0,0 +1,47 @@
+$timescale 1 ps $end
+$scope module mod1 $end
+$scope struct o $end
+$var wire 4 ! i $end
+$var wire 2 " o $end
+$var wire 2 # i2 $end
+$var wire 4 $ o2 $end
+$upscope $end
+$scope struct child $end
+$var wire 4 ) i $end
+$var wire 2 * o $end
+$var wire 2 + i2 $end
+$var wire 4 , o2 $end
+$upscope $end
+$scope module mod1_child $end
+$var wire 4 % i $end
+$var wire 2 & o $end
+$var wire 2 ' i2 $end
+$var wire 4 ( o2 $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+b11 !
+b11 "
+b10 #
+b1110 $
+b11 %
+b11 &
+b10 '
+b1110 (
+b11 )
+b11 *
+b10 +
+b1110 ,
+$end
+#1000000
+b1010 !
+b10 "
+b1111 $
+b1010 %
+b10 &
+b1111 (
+b1010 )
+b10 *
+b1111 ,
+#2000000
diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt
new file mode 100644
index 0000000..5447d49
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/shift_register.txt
@@ -0,0 +1,670 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 4,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 13,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:13:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
+                    src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:12:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                    value: 0,
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
+                },
+                AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallZero {
+                    target: 14,
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallNonZero {
+                    target: 13,
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
+                },
+                Branch {
+                    target: 14,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:7:1
+                BranchIfSmallZero {
+                    target: 19,
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallNonZero {
+                    target: 18,
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
+                },
+                Branch {
+                    target: 19,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                BranchIfSmallZero {
+                    target: 24,
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallNonZero {
+                    target: 23,
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
+                },
+                Branch {
+                    target: 24,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                BranchIfSmallZero {
+                    target: 29,
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallNonZero {
+                    target: 28,
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                    src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
+                },
+                Branch {
+                    target: 29,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                NotSmall {
+                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Return,
+            ],
+            ..
+        },
+        pc: 30,
+        small_slots: StatePart {
+            value: [
+                18446744073709551614,
+                0,
+                1,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::shift_register,
+        instantiated: Module {
+            name: shift_register,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::shift_register,
+            instantiated: Module {
+                name: shift_register,
+                ..
+            },
+        }.cd: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: SyncReset,
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
+                                ty: SyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Clock,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Clock,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: SyncReset,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: SyncReset,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::shift_register,
+            instantiated: Module {
+                name: shift_register,
+                ..
+            },
+        }.cd.clk: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::shift_register,
+            instantiated: Module {
+                name: shift_register,
+                ..
+            },
+        }.cd.rst: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: SyncReset,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: SyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::shift_register,
+            instantiated: Module {
+                name: shift_register,
+                ..
+            },
+        }.d: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::shift_register,
+            instantiated: Module {
+                name: shift_register,
+                ..
+            },
+        }.q: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "shift_register",
+        children: [
+            TraceModuleIO {
+                name: "cd",
+                child: TraceBundle {
+                    name: "cd",
+                    fields: [
+                        TraceClock {
+                            id: TraceScalarId(0),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceSyncReset {
+                            id: TraceScalarId(1),
+                            name: "rst",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        rst: SyncReset,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: SyncReset,
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "d",
+                child: TraceBool {
+                    id: TraceScalarId(2),
+                    name: "d",
+                    flow: Source,
+                },
+                ty: Bool,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "q",
+                child: TraceBool {
+                    id: TraceScalarId(3),
+                    name: "q",
+                    flow: Sink,
+                },
+                ty: Bool,
+                flow: Sink,
+            },
+            TraceReg {
+                name: "reg0",
+                child: TraceBool {
+                    id: TraceScalarId(4),
+                    name: "reg0",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+            TraceReg {
+                name: "reg1",
+                child: TraceBool {
+                    id: TraceScalarId(5),
+                    name: "reg1",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+            TraceReg {
+                name: "reg2",
+                child: TraceBool {
+                    id: TraceScalarId(6),
+                    name: "reg2",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+            TraceReg {
+                name: "reg3",
+                child: TraceBool {
+                    id: TraceScalarId(7),
+                    name: "reg3",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigSyncReset {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(3),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(4),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(7),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(9),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(11),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+    ],
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 66 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+    ],
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/shift_register.vcd b/crates/fayalite/tests/sim/expected/shift_register.vcd
new file mode 100644
index 0000000..0b5f429
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/shift_register.vcd
@@ -0,0 +1,193 @@
+$timescale 1 ps $end
+$scope module shift_register $end
+$scope struct cd $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$upscope $end
+$var wire 1 # d $end
+$var wire 1 $ q $end
+$var reg 1 % reg0 $end
+$var reg 1 & reg1 $end
+$var reg 1 ' reg2 $end
+$var reg 1 ( reg3 $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+1"
+0#
+0$
+0%
+0&
+0'
+0(
+$end
+#1000000
+1!
+#1100000
+0"
+#2000000
+0!
+#3000000
+1!
+#4000000
+0!
+1#
+#5000000
+1!
+1%
+#6000000
+0!
+#7000000
+1!
+1&
+#8000000
+0!
+0#
+#9000000
+1!
+0%
+1'
+#10000000
+0!
+#11000000
+1!
+0&
+1(
+1$
+#12000000
+0!
+1#
+#13000000
+1!
+1%
+0'
+#14000000
+0!
+0#
+#15000000
+1!
+0%
+1&
+0(
+0$
+#16000000
+0!
+1#
+#17000000
+1!
+1%
+0&
+1'
+#18000000
+0!
+#19000000
+1!
+1&
+0'
+1(
+1$
+#20000000
+0!
+#21000000
+1!
+1'
+0(
+0$
+#22000000
+0!
+#23000000
+1!
+1(
+1$
+#24000000
+0!
+0#
+#25000000
+1!
+0%
+#26000000
+0!
+#27000000
+1!
+0&
+#28000000
+0!
+#29000000
+1!
+0'
+#30000000
+0!
+#31000000
+1!
+0(
+0$
+#32000000
+0!
+#33000000
+1!
+#34000000
+0!
+#35000000
+1!
+#36000000
+0!
+#37000000
+1!
+#38000000
+0!
+#39000000
+1!
+#40000000
+0!
+#41000000
+1!
+#42000000
+0!
+#43000000
+1!
+#44000000
+0!
+#45000000
+1!
+#46000000
+0!
+#47000000
+1!
+#48000000
+0!
+#49000000
+1!
+#50000000
+0!
+#51000000
+1!
+#52000000
+0!
+#53000000
+1!
+#54000000
+0!
+#55000000
+1!
+#56000000
+0!
+#57000000
+1!
+#58000000
+0!
+#59000000
+1!
+#60000000
+0!
+#61000000
+1!
+#62000000
+0!
+#63000000
+1!
+#64000000
+0!
+#65000000
+1!
+#66000000
diff --git a/scripts/check-copyright.sh b/scripts/check-copyright.sh
index 8104f9c..3651931 100755
--- a/scripts/check-copyright.sh
+++ b/scripts/check-copyright.sh
@@ -46,7 +46,7 @@ function main()
         */LICENSE.md|*/Notices.txt)
             # copyright file
             ;;
-        /crates/fayalite/tests/ui/*.stderr)
+        /crates/fayalite/tests/ui/*.stderr|/crates/fayalite/tests/sim/expected/*.vcd|/crates/fayalite/tests/sim/expected/*.txt)
             # file that can't contain copyright header
             ;;
         /.forgejo/workflows/*.yml|*/.gitignore|*.toml)

From 9f42cab471ee6ba9f111e9a634b7a6b2ca4a4fcc Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 5 Dec 2024 20:26:28 -0800
Subject: [PATCH 120/190] change to version 0.3.0 for breaking change

---
 Cargo.lock | 8 ++++----
 Cargo.toml | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 1c54aeb..2e50abc 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -301,7 +301,7 @@ checksum = "25cbce373ec4653f1a01a31e8a5e5ec0c622dc27ff9c4e6606eefef5cbbed4a5"
 
 [[package]]
 name = "fayalite"
-version = "0.2.1"
+version = "0.3.0"
 dependencies = [
  "bitvec",
  "blake3",
@@ -326,14 +326,14 @@ dependencies = [
 
 [[package]]
 name = "fayalite-proc-macros"
-version = "0.2.1"
+version = "0.3.0"
 dependencies = [
  "fayalite-proc-macros-impl",
 ]
 
 [[package]]
 name = "fayalite-proc-macros-impl"
-version = "0.2.1"
+version = "0.3.0"
 dependencies = [
  "base16ct",
  "num-bigint",
@@ -347,7 +347,7 @@ dependencies = [
 
 [[package]]
 name = "fayalite-visit-gen"
-version = "0.2.1"
+version = "0.3.0"
 dependencies = [
  "indexmap",
  "prettyplease",
diff --git a/Cargo.toml b/Cargo.toml
index 50a4fb8..2cfa586 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -5,7 +5,7 @@ resolver = "2"
 members = ["crates/*"]
 
 [workspace.package]
-version = "0.2.1"
+version = "0.3.0"
 license = "LGPL-3.0-or-later"
 edition = "2021"
 repository = "https://git.libre-chip.org/libre-chip/fayalite"
@@ -14,9 +14,9 @@ categories = ["simulation", "development-tools", "compilers"]
 rust-version = "1.82.0"
 
 [workspace.dependencies]
-fayalite-proc-macros = { version = "=0.2.1", path = "crates/fayalite-proc-macros" }
-fayalite-proc-macros-impl = { version = "=0.2.1", path = "crates/fayalite-proc-macros-impl" }
-fayalite-visit-gen = { version = "=0.2.1", path = "crates/fayalite-visit-gen" }
+fayalite-proc-macros = { version = "=0.3.0", path = "crates/fayalite-proc-macros" }
+fayalite-proc-macros-impl = { version = "=0.3.0", path = "crates/fayalite-proc-macros-impl" }
+fayalite-visit-gen = { version = "=0.3.0", path = "crates/fayalite-visit-gen" }
 base16ct = "0.2.0"
 bitvec = { version = "1.0.1", features = ["serde"] }
 blake3 = { version = "1.5.4", features = ["serde"] }

From e504cfebfefa84dd0fd704b667d74989ec10130d Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 5 Dec 2024 20:27:50 -0800
Subject: [PATCH 121/190] add BoolOrIntType::copy_bits_from_bigint_wrapping and
 take BigInt arguments by reference

---
 crates/fayalite/src/expr/ops.rs |  8 ++++----
 crates/fayalite/src/int.rs      | 29 ++++++++++++++++-------------
 2 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/crates/fayalite/src/expr/ops.rs b/crates/fayalite/src/expr/ops.rs
index 0c8c4fa..15c195e 100644
--- a/crates/fayalite/src/expr/ops.rs
+++ b/crates/fayalite/src/expr/ops.rs
@@ -265,7 +265,7 @@ impl Neg {
         };
         let result_ty = retval.ty();
         retval.literal_bits = arg.to_literal_bits().map(|bits| {
-            Intern::intern_owned(result_ty.bits_from_bigint_wrapping(-SInt::bits_to_bigint(&bits)))
+            Intern::intern_owned(result_ty.bits_from_bigint_wrapping(&-SInt::bits_to_bigint(&bits)))
         });
         retval
     }
@@ -372,7 +372,7 @@ fn binary_op_literal_bits<ResultTy: BoolOrIntType, Lhs: BoolOrIntType, Rhs: Bool
     let rhs = Rhs::bits_to_bigint(&rhs);
     let result = f(lhs, rhs)?;
     Ok(Intern::intern_owned(
-        result_ty.bits_from_bigint_wrapping(result),
+        result_ty.bits_from_bigint_wrapping(&result),
     ))
 }
 
@@ -1347,7 +1347,7 @@ macro_rules! binary_op_fixed_shift {
                     literal_bits: Err(NotALiteralExpr),
                 };
                 retval.literal_bits = lhs.to_literal_bits().map(|bits| {
-                    Intern::intern_owned(retval.ty().bits_from_bigint_wrapping($Trait::$method(
+                    Intern::intern_owned(retval.ty().bits_from_bigint_wrapping(&$Trait::$method(
                         $ty::bits_to_bigint(&bits),
                         rhs,
                     )))
@@ -1624,7 +1624,7 @@ macro_rules! impl_cast_int_op {
                     ty,
                     literal_bits: arg.to_literal_bits().map(|bits| {
                         Intern::intern_owned(
-                            ty.bits_from_bigint_wrapping($from::bits_to_bigint(&bits)),
+                            ty.bits_from_bigint_wrapping(&$from::bits_to_bigint(&bits)),
                         )
                     }),
                 }
diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index b80c2b6..b49ca3f 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -202,17 +202,17 @@ macro_rules! impl_int {
                     bit_width: self.width(),
                 }
             }
-            pub fn bits_from_bigint_wrapping(self, v: BigInt) -> BitVec {
+            pub fn bits_from_bigint_wrapping(self, v: &BigInt) -> BitVec {
                 BoolOrIntType::bits_from_bigint_wrapping(self, v)
             }
-            pub fn from_bigint_wrapping(self, v: BigInt) -> $value<Width> {
+            pub fn from_bigint_wrapping(self, v: &BigInt) -> $value<Width> {
                 $value {
                     bits: Arc::new(self.bits_from_bigint_wrapping(v)),
                     _phantom: PhantomData,
                 }
             }
             pub fn from_int_wrapping(self, v: impl Into<BigInt>) -> $value<Width> {
-                self.from_bigint_wrapping(v.into())
+                self.from_bigint_wrapping(&v.into())
             }
             pub fn zero(self) -> $value<Width> {
                 self.from_int_wrapping(0u8)
@@ -234,7 +234,7 @@ macro_rules! impl_int {
             fn new(width: Width::SizeType) -> Self {
                 $name { width }
             }
-            fn value_from_bigint_wrapping(self, v: BigInt) -> Self::Value {
+            fn value_from_bigint_wrapping(self, v: &BigInt) -> Self::Value {
                 $value::<Width>::from_bigint_wrapping(self, v)
             }
             fn bits_to_value(bits: Cow<'_, BitSlice>) -> Self::Value {
@@ -378,7 +378,7 @@ macro_rules! impl_int {
                     self.bits.len()
                 }
             }
-            pub fn from_bigint_wrapping(ty: $name<Width>, v: BigInt) -> $value<Width> {
+            pub fn from_bigint_wrapping(ty: $name<Width>, v: &BigInt) -> $value<Width> {
                 ty.from_bigint_wrapping(v)
             }
             pub fn to_bigint(&self) -> BigInt {
@@ -603,20 +603,23 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
         UIntType::new(Self::Width::from_usize(self.width()))
     }
     fn value_from_int_wrapping(self, v: impl Into<BigInt>) -> Self::Value {
-        self.value_from_bigint_wrapping(v.into())
+        self.value_from_bigint_wrapping(&v.into())
     }
-    fn value_from_bigint_wrapping(self, v: BigInt) -> Self::Value;
-    fn bits_from_bigint_wrapping(self, v: BigInt) -> BitVec {
-        let width = self.width();
+    fn value_from_bigint_wrapping(self, v: &BigInt) -> Self::Value;
+    fn bits_from_bigint_wrapping(self, v: &BigInt) -> BitVec {
+        let mut bits = BitVec::repeat(false, self.width());
+        Self::copy_bits_from_bigint_wrapping(v, &mut bits);
+        bits
+    }
+    fn copy_bits_from_bigint_wrapping(v: &BigInt, bits: &mut BitSlice) {
+        let width = bits.len();
         let mut bytes = v.to_signed_bytes_le();
         bytes.resize(
             width.div_ceil(u8::BITS as usize),
             if v.is_negative() { 0xFF } else { 0 },
         );
         let bitslice = &BitSlice::<u8, Lsb0>::from_slice(&bytes)[..width];
-        let mut bits = BitVec::new();
-        bits.extend_from_bitslice(bitslice);
-        bits
+        bits.clone_from_bitslice(bitslice);
     }
     fn bits_to_bigint(bits: &BitSlice) -> BigInt {
         let sign_byte = if Self::Signed::VALUE && bits.last().as_deref().copied().unwrap_or(false) {
@@ -712,7 +715,7 @@ impl BoolOrIntType for Bool {
         Bool
     }
 
-    fn value_from_bigint_wrapping(self, v: BigInt) -> Self::Value {
+    fn value_from_bigint_wrapping(self, v: &BigInt) -> Self::Value {
         v.bit(0)
     }
 

From 3ed782748553d02fddcb57afd30db6f6baf3b32f Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 5 Dec 2024 21:35:23 -0800
Subject: [PATCH 122/190] sim: WIP adding memory support

---
 crates/fayalite/src/sim.rs                    | 112 ++++++++--
 crates/fayalite/src/sim/interpreter.rs        | 207 ++++++++++++++++--
 .../tests/sim/expected/connect_const.txt      |   9 +
 .../sim/expected/connect_const_reset.txt      |   9 +
 .../tests/sim/expected/counter_async.txt      |   9 +
 .../tests/sim/expected/counter_sync.txt       |   9 +
 crates/fayalite/tests/sim/expected/mod1.txt   |   9 +
 .../tests/sim/expected/shift_register.txt     |   9 +
 8 files changed, 335 insertions(+), 38 deletions(-)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 009e599..3802ae4 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -16,6 +16,7 @@ use crate::{
     },
     int::BoolOrIntType,
     intern::{Intern, Interned, Memoize},
+    memory::PortKind,
     module::{
         transform::deduce_resets::deduce_resets, AnnotatedModuleIO, Block, Id, InstantiatedModule,
         ModuleBody, NameId, NormalModuleBody, ScopedNameId, Stmt, StmtConnect, StmtDeclaration,
@@ -28,9 +29,9 @@ use crate::{
             Insn, InsnField, InsnFieldKind, InsnFieldType, Insns, InsnsBuilding, InsnsBuildingDone,
             SlotDebugData, SmallUInt, State, StatePartArrayIndex, StatePartArrayIndexed,
             StatePartIndex, StatePartIndexRange, StatePartKind, StatePartKindBigSlots,
-            StatePartKindSmallSlots, StatePartLayout, StatePartLen, StatePartsValue,
-            TypeArrayIndex, TypeArrayIndexes, TypeIndex, TypeIndexRange, TypeLayout, TypeLen,
-            TypeParts,
+            StatePartKindMemories, StatePartKindSmallSlots, StatePartLayout, StatePartLen,
+            StatePartsValue, TypeArrayIndex, TypeArrayIndexes, TypeIndex, TypeIndexRange,
+            TypeLayout, TypeLen, TypeParts,
         },
         time::{SimDuration, SimInstant},
     },
@@ -136,7 +137,7 @@ impl<T: Type> CompiledTypeLayout<T> {
                             name: Interned::default(),
                             ty: *input,
                         };
-                        layout.big_slots = StatePartLayout::scalar(debug_data);
+                        layout.big_slots = StatePartLayout::scalar(debug_data, ());
                         CompiledTypeLayout {
                             ty: *input,
                             layout: layout.into(),
@@ -1163,14 +1164,20 @@ impl Assignment {
                     }
                     (
                         _,
-                        InsnFieldType::SmallUInt(_)
+                        InsnFieldType::Memory(_)
+                        | InsnFieldType::SmallUInt(_)
                         | InsnFieldType::SmallSInt(_)
                         | InsnFieldType::InternedBigInt(_)
                         | InsnFieldType::U8(_)
                         | InsnFieldType::USize(_)
                         | InsnFieldType::Empty(_),
                     )
-                    | (InsnFieldKind::Immediate | InsnFieldKind::BranchTarget, _) => {}
+                    | (
+                        InsnFieldKind::Immediate
+                        | InsnFieldKind::Memory
+                        | InsnFieldKind::BranchTarget,
+                        _,
+                    ) => {}
                 }
             }
         }
@@ -1207,6 +1214,20 @@ struct Register {
     source_location: SourceLocation,
 }
 
+#[derive(Debug)]
+enum MemoryPort {
+    ReadOnly {},
+    WriteOnly {},
+    ReadWrite {},
+}
+
+#[derive(Debug)]
+struct Memory {
+    mem: Mem,
+    memory: StatePartIndex<StatePartKindMemories>,
+    ports: Vec<MemoryPort>,
+}
+
 #[derive(Debug)]
 pub struct Compiler {
     insns: Insns<InsnsBuilding>,
@@ -1227,6 +1248,7 @@ pub struct Compiler {
     enum_discriminants: HashMap<CompiledValue<Enum>, StatePartIndex<StatePartKindSmallSlots>>,
     registers: Vec<Register>,
     traces: Vec<SimTrace<()>>,
+    memories: Vec<Memory>,
 }
 
 impl Compiler {
@@ -1251,6 +1273,7 @@ impl Compiler {
             enum_discriminants: HashMap::new(),
             registers: Vec::new(),
             traces: Vec::new(),
+            memories: Vec::new(),
         }
     }
     fn new_sim_trace(&mut self, kind: SimTraceKind) -> TraceScalarId {
@@ -1809,7 +1832,7 @@ impl Compiler {
                 let dest = self
                     .insns
                     .allocate_variable(&TypeLayout {
-                        small_slots: StatePartLayout::scalar(debug_data),
+                        small_slots: StatePartLayout::scalar(debug_data, ()),
                         big_slots: StatePartLayout::empty(),
                     })
                     .small_slots
@@ -1851,7 +1874,7 @@ impl Compiler {
                 let dest = self
                     .insns
                     .allocate_variable(&TypeLayout {
-                        small_slots: StatePartLayout::scalar(debug_data),
+                        small_slots: StatePartLayout::scalar(debug_data, ()),
                         big_slots: StatePartLayout::empty(),
                     })
                     .small_slots
@@ -3038,10 +3061,13 @@ impl Compiler {
                 .state_layout
                 .ty
                 .small_slots
-                .allocate(&StatePartLayout::scalar(SlotDebugData {
-                    name: Interned::default(),
-                    ty: Bool.canonical(),
-                }))
+                .allocate(&StatePartLayout::scalar(
+                    SlotDebugData {
+                        name: Interned::default(),
+                        ty: Bool.canonical(),
+                    },
+                    (),
+                ))
                 .start
         };
         let last_clk_was_low = alloc_small_slot("last_clk_was_low");
@@ -3098,10 +3124,13 @@ impl Compiler {
                 .state_layout
                 .ty
                 .small_slots
-                .allocate(&StatePartLayout::scalar(SlotDebugData {
-                    name: Interned::default(),
-                    ty: retval_ty.canonical(),
-                }))
+                .allocate(&StatePartLayout::scalar(
+                    SlotDebugData {
+                        name: Interned::default(),
+                        ty: retval_ty.canonical(),
+                    },
+                    (),
+                ))
                 .start;
             let discriminant_bit_width = enum_value.layout.ty.discriminant_bit_width();
             let discriminant_mask = !(!0u64 << discriminant_bit_width);
@@ -3289,6 +3318,49 @@ impl Compiler {
         }
         self.make_trace_decl(*parent_module, target_base)
     }
+    fn compile_memory(
+        &mut self,
+        mem: Mem,
+        instantiated_module: InstantiatedModule,
+        conditions: Interned<[Cond]>,
+        trace_decls: &mut Vec<TraceDecl>,
+    ) {
+        let memory = self
+            .insns
+            .state_layout
+            .memories
+            .allocate(&StatePartLayout::scalar(
+                (),
+                mem.initial_value().unwrap_or_else(|| {
+                    Intern::intern_owned(BitVec::repeat(
+                        false,
+                        mem.array_type().type_properties().bit_width,
+                    ))
+                }),
+            ))
+            .start;
+        let ports = mem
+            .ports()
+            .iter()
+            .map(|&port| {
+                let target_base = TargetBase::MemPort(port);
+                let target = TargetInInstantiatedModule {
+                    instantiated_module,
+                    target: target_base.into(),
+                };
+                self.decl_conditions.insert(target, conditions);
+                trace_decls.push(self.make_trace_decl(instantiated_module, target_base));
+                todo!("handle read/write");
+                match port.port_kind() {
+                    PortKind::ReadOnly => MemoryPort::ReadOnly {},
+                    PortKind::WriteOnly => MemoryPort::WriteOnly {},
+                    PortKind::ReadWrite => MemoryPort::ReadWrite {},
+                }
+            })
+            .collect();
+        self.memories.push(Memory { mem, memory, ports });
+        todo!("implement memory");
+    }
     fn compile_block(
         &mut self,
         parent_module: Interned<InstantiatedModule>,
@@ -3298,7 +3370,7 @@ impl Compiler {
     ) {
         let Block { memories, stmts } = block;
         for memory in memories {
-            todo!("implement memory");
+            self.compile_memory(memory, *parent_module, conditions, trace_decls);
         }
         for stmt in stmts {
             match stmt {
@@ -3613,11 +3685,17 @@ impl Compiler {
             }
         }
     }
+    fn process_memories(&mut self) {
+        for memory in mem::take(&mut self.memories) {
+            todo!();
+        }
+    }
     pub fn compile(mut self) -> Compiled<Bundle> {
         let base_module =
             *self.compile_module(InstantiatedModule::Base(self.base_module).intern_sized());
         self.process_assignments();
         self.process_registers();
+        self.process_memories();
         let clocks_triggered = self.process_clocks();
         self.insns
             .push(Insn::Return, self.base_module.source_location());
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index cb1f29b..0fd0591 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -2,15 +2,18 @@
 // See Notices.txt for copyright information
 
 use crate::{
+    int::{BoolOrIntType, SInt, UInt},
     intern::{Intern, Interned, Memoize},
     source_location::SourceLocation,
     ty::CanonicalType,
     util::get_many_mut,
 };
+use bitvec::{boxed::BitBox, slice::BitSlice};
 use hashbrown::HashMap;
 use num_bigint::BigInt;
 use num_traits::{One, Signed, ToPrimitive, Zero};
 use std::{
+    any::TypeId,
     borrow::BorrowMut,
     convert::Infallible,
     fmt,
@@ -28,6 +31,7 @@ pub(crate) const MIN_BITS_FOR_NEEDING_BIG: usize = SmallUInt::BITS as usize + 1;
 pub(crate) enum InsnFieldKind {
     Input,
     Output,
+    Memory,
     Immediate,
     BranchTarget,
 }
@@ -108,6 +112,7 @@ macro_rules! insn_field_enum {
 
 insn_field_enum! {
     pub(crate) enum InsnFieldType<Transform: InsnFieldTypeTransform> {
+        Memory(Transform::Type<StatePartIndex<StatePartKindMemories>>),
         SmallSlot(Transform::Type<StatePartIndex<StatePartKindSmallSlots>>),
         BigSlot(Transform::Type<StatePartIndex<StatePartKindBigSlots>>),
         SmallSlotArrayIndexed(Transform::Type<StatePartArrayIndexed<StatePartKindSmallSlots>>),
@@ -206,7 +211,8 @@ impl Insn {
                             continue;
                         }
                     }
-                    InsnFieldType::SmallSlot(_)
+                    InsnFieldType::Memory(_)
+                    | InsnFieldType::SmallSlot(_)
                     | InsnFieldType::BigSlot(_)
                     | InsnFieldType::SmallSlotArrayIndexed(_)
                     | InsnFieldType::BigSlotArrayIndexed(_)
@@ -216,9 +222,15 @@ impl Insn {
                     | InsnFieldType::U8(_)
                     | InsnFieldType::Empty(_) => {}
                 },
-                InsnFieldKind::Input | InsnFieldKind::Output | InsnFieldKind::Immediate => {}
+                InsnFieldKind::Input
+                | InsnFieldKind::Memory
+                | InsnFieldKind::Output
+                | InsnFieldKind::Immediate => {}
             }
             match field.ty {
+                InsnFieldType::Memory(v) => {
+                    v.debug_fmt(f, ",", " // ", "", state_layout)?;
+                }
                 InsnFieldType::SmallSlot(v) => {
                     v.debug_fmt(f, ",", " // ", "", state_layout)?;
                 }
@@ -577,9 +589,10 @@ pub(crate) trait StatePartKind:
 {
     const NAME: &'static str;
     type DebugData: Send + Sync + Eq + Hash + fmt::Debug + 'static + Copy;
+    type LayoutData: Send + Sync + Eq + Hash + fmt::Debug + 'static + Copy;
     type State: fmt::Debug + 'static + Clone;
     type BorrowedState<'a>: 'a;
-    fn new_state(len: StatePartLen<Self>) -> Self::State;
+    fn new_state(layout_data: &[Self::LayoutData]) -> Self::State;
     fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a>;
     fn part_debug_data<BK: InsnsBuildingKind>(
         state_layout: &StateLayout<BK>,
@@ -950,8 +963,8 @@ macro_rules! make_state_part_kinds {
                 Self {
                     insns,
                     pc: 0,
-                    $($state_field: StatePart::new(insns.state_layout.$state_field.len()),)*
-                    $($type_field: StatePart::new(insns.state_layout.ty.$type_field.len()),)*
+                    $($state_field: StatePart::new(&insns.state_layout.$state_field.layout_data),)*
+                    $($type_field: StatePart::new(&insns.state_layout.ty.$type_field.layout_data),)*
                 }
             }
             pub(crate) fn borrow(&mut self) -> BorrowedState<'_> {
@@ -1150,10 +1163,11 @@ make_state_part_kinds! {
     impl StatePartKind for StatePartKindSmallStack {
         const NAME: &'static str = "SmallStack";
         type DebugData = ();
+        type LayoutData = ();
         type State = Stack<SmallUInt>;
         type BorrowedState<'a> = BorrowedStack<'a, SmallUInt>;
-        fn new_state(len: StatePartLen<Self>) -> Self::State {
-            Stack::new(len.value.try_into().expect("state is too big"))
+        fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
+            Stack::new(layout_data.len())
         }
         fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
             state.borrow()
@@ -1169,10 +1183,11 @@ make_state_part_kinds! {
     impl StatePartKind for StatePartKindBigStack {
         const NAME: &'static str = "BigStack";
         type DebugData = ();
+        type LayoutData = ();
         type State = Stack<BigInt>;
         type BorrowedState<'a> = BorrowedStack<'a, BigInt>;
-        fn new_state(len: StatePartLen<Self>) -> Self::State {
-            Stack::new(len.value.try_into().expect("state is too big"))
+        fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
+            Stack::new(layout_data.len())
         }
         fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
             state.borrow()
@@ -1184,14 +1199,35 @@ make_state_part_kinds! {
             state_layout.big_stack.debug_data.get(part_index.as_usize())
         }
     }*/
+    #[state, field = memories]
+    impl StatePartKind for StatePartKindMemories {
+        const NAME: &'static str = "Memories";
+        type DebugData = ();
+        type LayoutData = Interned<BitSlice>;
+        type State = Box<[BitBox]>;
+        type BorrowedState<'a> = &'a mut [BitBox];
+        fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
+            layout_data.iter().map(|initial_data| BitBox::from_bitslice(initial_data)).collect()
+        }
+        fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
+            state
+        }
+        fn part_debug_data<BK: InsnsBuildingKind>(
+            state_layout: &StateLayout<BK>,
+            part_index: StatePartIndex<Self>,
+        ) -> Option<&Self::DebugData> {
+            state_layout.memories.debug_data.get(part_index.as_usize())
+        }
+    }
     #[type, field = small_slots]
     impl StatePartKind for StatePartKindSmallSlots {
         const NAME: &'static str = "SmallSlots";
         type DebugData = SlotDebugData;
+        type LayoutData = ();
         type State = Box<[SmallUInt]>;
         type BorrowedState<'a> = &'a mut [SmallUInt];
-        fn new_state(len: StatePartLen<Self>) -> Self::State {
-            vec![0; len.value.try_into().expect("state is too big")].into_boxed_slice()
+        fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
+            vec![0; layout_data.len()].into_boxed_slice()
         }
         fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
             state
@@ -1207,10 +1243,11 @@ make_state_part_kinds! {
     impl StatePartKind for StatePartKindBigSlots {
         const NAME: &'static str = "BigSlots";
         type DebugData = SlotDebugData;
+        type LayoutData = ();
         type State = Box<[BigInt]>;
         type BorrowedState<'a> = &'a mut [BigInt];
-        fn new_state(len: StatePartLen<Self>) -> Self::State {
-            std::iter::repeat_with(BigInt::default).take(len.value.try_into().expect("state is too big")).collect()
+        fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
+            layout_data.iter().map(|_| BigInt::default()).collect()
         }
         fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
             state
@@ -1348,6 +1385,7 @@ impl<K: StatePartKind<DebugData = SlotDebugData>, BK: InsnsBuildingKind> StatePa
                 .iter()
                 .map(|v| v.with_prefixed_debug_names(prefix))
                 .collect(),
+            layout_data: self.layout_data.clone(),
             _phantom: PhantomData,
         }
     }
@@ -1358,6 +1396,7 @@ impl<K: StatePartKind<DebugData = SlotDebugData>, BK: InsnsBuildingKind> StatePa
                 .iter()
                 .map(|v| v.with_anonymized_debug_info())
                 .collect(),
+            layout_data: self.layout_data.clone(),
             _phantom: PhantomData,
         }
     }
@@ -1552,6 +1591,7 @@ impl<K: StatePartKind> fmt::Debug for StatePartLen<K> {
 #[derive(Clone, PartialEq, Eq, Hash)]
 pub(crate) struct StatePartLayout<K: StatePartKind, BK: InsnsBuildingKind> {
     pub(crate) debug_data: BK::Vec<K::DebugData>,
+    pub(crate) layout_data: BK::Vec<K::LayoutData>,
     pub(crate) _phantom: PhantomData<K>,
 }
 
@@ -1572,6 +1612,7 @@ impl<K: StatePartKind, BK: InsnsBuildingKind> StatePartLayout<K, BK> {
     pub(crate) fn empty() -> Self {
         Self {
             debug_data: Default::default(),
+            layout_data: Default::default(),
             _phantom: PhantomData,
         }
     }
@@ -1583,15 +1624,17 @@ impl<K: StatePartKind> From<StatePartLayout<K, InsnsBuilding>>
     fn from(value: StatePartLayout<K, InsnsBuilding>) -> Self {
         Self {
             debug_data: Intern::intern_owned(value.debug_data),
+            layout_data: Intern::intern_owned(value.layout_data),
             _phantom: PhantomData,
         }
     }
 }
 
 impl<K: StatePartKind> StatePartLayout<K, InsnsBuilding> {
-    pub(crate) fn scalar(debug_data: K::DebugData) -> Self {
+    pub(crate) fn scalar(debug_data: K::DebugData, layout_data: K::LayoutData) -> Self {
         Self {
             debug_data: vec![debug_data],
+            layout_data: vec![layout_data],
             _phantom: PhantomData,
         }
     }
@@ -1609,9 +1652,11 @@ impl<K: StatePartKind> StatePartLayout<K, InsnsBuilding> {
         let len = layout.len();
         let Self {
             debug_data,
+            layout_data,
             _phantom: _,
         } = self;
         debug_data.extend_from_slice(&layout.debug_data);
+        layout_data.extend_from_slice(&layout.layout_data);
         StatePartIndexRange { start, len }
     }
 }
@@ -1620,13 +1665,18 @@ impl<K: StatePartKind, BK: InsnsBuildingKind> fmt::Debug for StatePartLayout<K,
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
             debug_data,
+            layout_data,
             _phantom: _,
         } = self;
         write!(f, "StatePartAllocationLayout<{}>", K::NAME)?;
-        f.debug_struct("")
+        let mut debug_struct = f.debug_struct("");
+        debug_struct
             .field("len", &debug_data.len())
-            .field("debug_data", debug_data)
-            .finish_non_exhaustive()
+            .field("debug_data", debug_data);
+        if TypeId::of::<K::LayoutData>() != TypeId::of::<()>() {
+            debug_struct.field("layout_data", layout_data);
+        }
+        debug_struct.finish_non_exhaustive()
     }
 }
 
@@ -1723,9 +1773,9 @@ pub(crate) struct StatePart<K: StatePartKind> {
 }
 
 impl<K: StatePartKind> StatePart<K> {
-    pub(crate) fn new(len: StatePartLen<K>) -> Self {
+    pub(crate) fn new(layout_data: &[K::LayoutData]) -> Self {
         Self {
-            value: K::new_state(len),
+            value: K::new_state(layout_data),
         }
     }
     pub(crate) fn borrow<'a>(&'a mut self) -> BorrowedStatePart<'a, K> {
@@ -2020,7 +2070,8 @@ impl From<Insns<InsnsBuilding>> for Insns<InsnsBuildingDone> {
                                 .address
                                 .expect("label address not set");
                         }
-                        InsnFieldType::SmallSlot(_)
+                        InsnFieldType::Memory(_)
+                        | InsnFieldType::SmallSlot(_)
                         | InsnFieldType::BigSlot(_)
                         | InsnFieldType::SmallSlotArrayIndexed(_)
                         | InsnFieldType::BigSlotArrayIndexed(_)
@@ -2032,7 +2083,10 @@ impl From<Insns<InsnsBuilding>> for Insns<InsnsBuildingDone> {
                             unreachable!()
                         }
                     },
-                    InsnFieldKind::Input | InsnFieldKind::Output | InsnFieldKind::Immediate => {}
+                    InsnFieldKind::Input
+                    | InsnFieldKind::Memory
+                    | InsnFieldKind::Output
+                    | InsnFieldKind::Immediate => {}
                 }
             }
         }
@@ -2050,6 +2104,7 @@ impl State {
         let Self {
             insns: _,
             pc,
+            memories: _,
             small_slots: _,
             big_slots: _,
         } = self;
@@ -2161,6 +2216,44 @@ fn cast_bigint_to_uint(src: &BigInt, dest_width: usize) -> BigInt {
     src & &*bigint_mask(dest_width)
 }
 
+fn memory_get_mut(
+    memory: &mut BitSlice,
+    addr: SmallUInt,
+    stride: usize,
+    start: usize,
+    width: usize,
+) -> Option<&mut BitSlice> {
+    let start = usize::try_from(addr)
+        .ok()?
+        .checked_mul(stride)?
+        .checked_add(start)?;
+    memory.get_mut(start..start.checked_add(width)?)
+}
+
+fn memory_read_big<T: BoolOrIntType>(
+    memory: &mut BitSlice,
+    addr: SmallUInt,
+    stride: usize,
+    start: usize,
+    width: usize,
+) -> Option<BigInt> {
+    let bits = memory_get_mut(memory, addr, stride, start, width)?;
+    Some(T::bits_to_bigint(bits))
+}
+
+fn memory_write_big<T: BoolOrIntType>(
+    memory: &mut BitSlice,
+    addr: SmallUInt,
+    stride: usize,
+    start: usize,
+    width: usize,
+    value: &BigInt,
+) -> Option<()> {
+    let bits = memory_get_mut(memory, addr, stride, start, width)?;
+    T::copy_bits_from_bigint_wrapping(value, bits);
+    Some(())
+}
+
 impl_insns! {
     #[insn = Insn, next_macro = next, branch_macro = branch]
     pub(crate) fn State::run(&mut self) -> () {
@@ -2702,6 +2795,78 @@ impl_insns! {
             next!();
         }
     }
+    MemoryReadUInt {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Memory]
+        memory: StatePartIndex<StatePartKindMemories>,
+        #[kind = Input]
+        addr: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        stride: usize,
+        #[kind = Immediate]
+        start: usize,
+        #[kind = Immediate]
+        width: usize,
+    } => {
+        let addr = state.small_slots[addr];
+        state.big_slots[dest] = memory_read_big::<UInt>(&mut state.memories[memory], addr, stride, start, width).unwrap_or_default();
+        next!();
+    }
+    MemoryReadSInt {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Memory]
+        memory: StatePartIndex<StatePartKindMemories>,
+        #[kind = Input]
+        addr: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        stride: usize,
+        #[kind = Immediate]
+        start: usize,
+        #[kind = Immediate]
+        width: usize,
+    } => {
+        let addr = state.small_slots[addr];
+        state.big_slots[dest] = memory_read_big::<SInt>(&mut state.memories[memory], addr, stride, start, width).unwrap_or_default();
+        next!();
+    }
+    MemoryWriteUInt {
+        #[kind = Input]
+        value: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Memory]
+        memory: StatePartIndex<StatePartKindMemories>,
+        #[kind = Input]
+        addr: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        stride: usize,
+        #[kind = Immediate]
+        start: usize,
+        #[kind = Immediate]
+        width: usize,
+    } => {
+        let addr = state.small_slots[addr];
+        memory_write_big::<UInt>(&mut state.memories[memory], addr, stride, start, width, &mut state.big_slots[value]);
+        next!();
+    }
+    MemoryWriteSInt {
+        #[kind = Input]
+        value: StatePartIndex<StatePartKindBigSlots>,
+        #[kind = Memory]
+        memory: StatePartIndex<StatePartKindMemories>,
+        #[kind = Input]
+        addr: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        stride: usize,
+        #[kind = Immediate]
+        start: usize,
+        #[kind = Immediate]
+        width: usize,
+    } => {
+        let addr = state.small_slots[addr];
+        memory_write_big::<SInt>(&mut state.memories[memory], addr, stride, start, width, &mut state.big_slots[value]);
+        next!();
+    }
     Return => {
         break;
     }
diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt
index 189056b..f361cc3 100644
--- a/crates/fayalite/tests/sim/expected/connect_const.txt
+++ b/crates/fayalite/tests/sim/expected/connect_const.txt
@@ -23,6 +23,12 @@ Simulation {
                         ..
                     },
                 },
+                memories: StatePartAllocationLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
@@ -41,6 +47,9 @@ Simulation {
             ..
         },
         pc: 2,
+        memories: StatePart {
+            value: [],
+        },
         small_slots: StatePart {
             value: [],
         },
diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
index 5e6f0eb..0b0c043 100644
--- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt
+++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
@@ -35,6 +35,12 @@ Simulation {
                         ..
                     },
                 },
+                memories: StatePartAllocationLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
@@ -67,6 +73,9 @@ Simulation {
             ..
         },
         pc: 5,
+        memories: StatePart {
+            value: [],
+        },
         small_slots: StatePart {
             value: [],
         },
diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt
index b72ebbb..0f49e80 100644
--- a/crates/fayalite/tests/sim/expected/counter_async.txt
+++ b/crates/fayalite/tests/sim/expected/counter_async.txt
@@ -72,6 +72,12 @@ Simulation {
                         ..
                     },
                 },
+                memories: StatePartAllocationLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
@@ -162,6 +168,9 @@ Simulation {
             ..
         },
         pc: 18,
+        memories: StatePart {
+            value: [],
+        },
         small_slots: StatePart {
             value: [
                 18446744073709551614,
diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt
index dbb6134..30b84b2 100644
--- a/crates/fayalite/tests/sim/expected/counter_sync.txt
+++ b/crates/fayalite/tests/sim/expected/counter_sync.txt
@@ -68,6 +68,12 @@ Simulation {
                         ..
                     },
                 },
+                memories: StatePartAllocationLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:6:1
@@ -144,6 +150,9 @@ Simulation {
             ..
         },
         pc: 15,
+        memories: StatePart {
+            value: [],
+        },
         small_slots: StatePart {
             value: [
                 18446744073709551614,
diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt
index 74ba140..cf15b07 100644
--- a/crates/fayalite/tests/sim/expected/mod1.txt
+++ b/crates/fayalite/tests/sim/expected/mod1.txt
@@ -83,6 +83,12 @@ Simulation {
                         ..
                     },
                 },
+                memories: StatePartAllocationLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:4:1
@@ -174,6 +180,9 @@ Simulation {
             ..
         },
         pc: 17,
+        memories: StatePart {
+            value: [],
+        },
         small_slots: StatePart {
             value: [],
         },
diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt
index 5447d49..e89351d 100644
--- a/crates/fayalite/tests/sim/expected/shift_register.txt
+++ b/crates/fayalite/tests/sim/expected/shift_register.txt
@@ -84,6 +84,12 @@ Simulation {
                         ..
                     },
                 },
+                memories: StatePartAllocationLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:13:1
@@ -221,6 +227,9 @@ Simulation {
             ..
         },
         pc: 30,
+        memories: StatePart {
+            value: [],
+        },
         small_slots: StatePart {
             value: [
                 18446744073709551614,

From 9654167ca3644dd8ff143923bd9eddc38951af09 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 6 Dec 2024 15:53:34 -0800
Subject: [PATCH 123/190] sim: WIP working on memory

---
 crates/fayalite/src/sim.rs | 48 +++++++++++++++++++++++++++++++-------
 1 file changed, 40 insertions(+), 8 deletions(-)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 3802ae4..321ab49 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -1215,10 +1215,16 @@ struct Register {
 }
 
 #[derive(Debug)]
-enum MemoryPort {
-    ReadOnly {},
-    WriteOnly {},
-    ReadWrite {},
+
+struct MemoryPort {
+    clk_triggered: StatePartIndex<StatePartKindSmallSlots>,
+    addr_delayed: Vec<StatePartIndex<StatePartKindSmallSlots>>,
+    en_delayed: Vec<StatePartIndex<StatePartKindSmallSlots>>,
+    data: CompiledValue<CanonicalType>,
+    read_data_delayed: Vec<TypeIndex>,
+    write_data_delayed: Vec<TypeIndex>,
+    write_mask_delayed: Vec<TypeIndex>,
+    write_mode_delayed: Vec<StatePartIndex<StatePartKindSmallSlots>>,
 }
 
 #[derive(Debug)]
@@ -3350,11 +3356,37 @@ impl Compiler {
                 };
                 self.decl_conditions.insert(target, conditions);
                 trace_decls.push(self.make_trace_decl(instantiated_module, target_base));
-                todo!("handle read/write");
                 match port.port_kind() {
-                    PortKind::ReadOnly => MemoryPort::ReadOnly {},
-                    PortKind::WriteOnly => MemoryPort::WriteOnly {},
-                    PortKind::ReadWrite => MemoryPort::ReadWrite {},
+                    PortKind::ReadOnly => MemoryPort {
+                        clk_triggered: todo!(),
+                        addr_delayed: todo!(),
+                        en_delayed: todo!(),
+                        data: todo!(),
+                        read_data_delayed: todo!(),
+                        write_data_delayed: todo!(),
+                        write_mask_delayed: todo!(),
+                        write_mode_delayed: todo!(),
+                    },
+                    PortKind::WriteOnly => MemoryPort {
+                        clk_triggered: todo!(),
+                        addr_delayed: todo!(),
+                        en_delayed: todo!(),
+                        data: todo!(),
+                        read_data_delayed: todo!(),
+                        write_data_delayed: todo!(),
+                        write_mask_delayed: todo!(),
+                        write_mode_delayed: todo!(),
+                    },
+                    PortKind::ReadWrite => MemoryPort {
+                        clk_triggered: todo!(),
+                        addr_delayed: todo!(),
+                        en_delayed: todo!(),
+                        data: todo!(),
+                        read_data_delayed: todo!(),
+                        write_data_delayed: todo!(),
+                        write_mask_delayed: todo!(),
+                        write_mode_delayed: todo!(),
+                    },
                 }
             })
             .collect();

From 2e7d685dc7571f4411c25aec7b78ddd7f8e8c04a Mon Sep 17 00:00:00 2001
From: Cesar Strauss <cesar.strauss@inpe.br>
Date: Sun, 8 Dec 2024 15:25:21 -0300
Subject: [PATCH 124/190] add module exercising formal verification of memories

---
 crates/fayalite/tests/formal.rs | 170 +++++++++++++++++++++++++++++++-
 1 file changed, 166 insertions(+), 4 deletions(-)

diff --git a/crates/fayalite/tests/formal.rs b/crates/fayalite/tests/formal.rs
index 46b8292..65264dc 100644
--- a/crates/fayalite/tests/formal.rs
+++ b/crates/fayalite/tests/formal.rs
@@ -7,12 +7,13 @@ use fayalite::{
     clock::{Clock, ClockDomain},
     expr::{CastTo, HdlPartialEq},
     firrtl::ExportOptions,
-    formal::{any_seq, formal_reset, hdl_assert, hdl_assume},
-    hdl_module,
-    int::{Bool, UInt},
-    module::{connect, connect_any, reg_builder, wire},
+    formal::{any_const, any_seq, formal_reset, hdl_assert, hdl_assume},
+    hdl, hdl_module,
+    int::{Bool, DynSize, Size, UInt, UIntType},
+    module::{connect, connect_any, instance, memory, reg_builder, wire},
     reset::ToReset,
     testing::assert_formal,
+    ty::StaticType,
 };
 
 /// Test hidden state
@@ -131,3 +132,164 @@ mod hidden_state {
         );
     }
 }
+
+/// Formal verification of designs containing memories
+///
+/// There is a trick for memories, described in the [Zipcpu blog].
+/// First, select a fixed but arbitrary memory address, monitoring all reads
+/// and writes made to it. Then, assert that anything read from that location
+/// matches the last stored value.
+///
+/// A difficulty for induction is that the memory represents [hidden_state]. A
+/// solution is to include an additional read port to the memory and assert
+/// that the memory location effectively contains the last stored value.
+/// This additional debug port is present only to assist the proof and is
+/// unused (optimized out) in actual use.
+///
+/// [Zipcpu blog]: <https://zipcpu.com/zipcpu/2018/07/13/memories.html>
+mod memory {
+    use super::*;
+
+    /// Test a simple 8-bit SRAM model
+    #[test]
+    fn test_sram() {
+        #[hdl]
+        struct WritePort<AddrWidth: Size> {
+            addr: UIntType<AddrWidth>,
+            data: UInt<8>,
+            en: Bool,
+        }
+        #[hdl]
+        struct ReadPort<AddrWidth: Size> {
+            addr: UIntType<AddrWidth>,
+            #[hdl(flip)]
+            data: UInt<8>,
+        }
+        /// This debug port is only meant to assist the proof.
+        /// For normal use in a design, a wrapper could be provided,
+        /// omitting this port.
+        /// The implementation is forbidden to use any information
+        /// provided on this port in its internal workings.
+        #[hdl]
+        struct DebugPort<AddrWidth: Size> {
+            selected: UIntType<AddrWidth>,
+            stored: UInt<8>,
+            wrote: Bool,
+        }
+        /// simple 1R1W SRAM model (one asynchronous read port and one
+        /// independent write port) with `n`-bit address width
+        #[hdl_module]
+        fn example_sram(n: usize) {
+            #[hdl]
+            let wr: WritePort<DynSize> = m.input(WritePort[n]);
+            #[hdl]
+            let rd: ReadPort<DynSize> = m.input(ReadPort[n]);
+            #[hdl]
+            let cd: ClockDomain = m.input();
+
+            // declare and connect the backing memory
+            #[hdl]
+            let mut mem = memory();
+            mem.depth(1 << n);
+            let read_port = mem.new_read_port();
+            let write_port = mem.new_write_port();
+            connect(write_port.clk, cd.clk);
+            connect(write_port.addr, wr.addr);
+            connect(write_port.en, wr.en);
+            connect(write_port.data, wr.data);
+            connect(write_port.mask, true);
+            connect(read_port.clk, cd.clk);
+            connect(read_port.addr, rd.addr);
+            connect(read_port.en, true);
+            connect(rd.data, read_port.data);
+
+            // To assist with induction, ensure that the chosen memory location
+            // really contains, always, the last value written to it.
+            #[hdl]
+            let dbg: DebugPort<DynSize> = m.input(DebugPort[n]);
+            let debug_port = mem.new_read_port();
+            connect(debug_port.en, true);
+            connect(debug_port.clk, cd.clk);
+            connect(debug_port.addr, dbg.selected);
+            #[hdl]
+            if dbg.wrote {
+                hdl_assert(cd.clk, debug_port.data.cmp_eq(dbg.stored), "");
+                // Try commenting out the assert above, induction will fail.
+                // Opening the trace, it can be seen that the memory contents
+                // and the stored value don't match, which is an unreachable
+                // state. By asserting the above, it will become invalid
+                // as well, so induction will skip this kind of situation.
+            }
+        }
+
+        /// formal verification of the SRAM module, parametrized by the
+        /// address bit-width
+        #[hdl_module]
+        fn test_module(n: usize) {
+            #[hdl]
+            let clk: Clock = m.input();
+            let cd = #[hdl]
+            ClockDomain {
+                clk,
+                rst: formal_reset().to_reset(),
+            };
+
+            // instantiate the SRAM model, connecting its inputs to
+            // a random sequence
+            #[hdl]
+            let rd: ReadPort<DynSize> = wire(ReadPort[n]);
+            connect(rd.addr, any_seq(UInt[n]));
+            #[hdl]
+            let wr: WritePort<DynSize> = wire(WritePort[n]);
+            connect(wr.addr, any_seq(UInt[n]));
+            connect(wr.data, any_seq(UInt::<8>::TYPE));
+            connect(wr.en, any_seq(Bool));
+            #[hdl]
+            let dut = instance(example_sram(n));
+            connect(dut.cd, cd);
+            connect(dut.rd, rd);
+            connect(dut.wr, wr);
+
+            // select a fixed but arbitrary test address
+            #[hdl]
+            let selected = wire(UInt[n]);
+            connect(selected, any_const(UInt[n]));
+            // store the last value written to that address
+            #[hdl]
+            let stored: UInt<8> = reg_builder().clock_domain(cd).reset(0u8);
+            // since memories are not initialized, track whether we wrote to the
+            // memory at least once
+            #[hdl]
+            let wrote: Bool = reg_builder().clock_domain(cd).reset(false);
+            // on a write, capture the last written value
+            #[hdl]
+            if wr.en & wr.addr.cmp_eq(selected) {
+                connect(stored, wr.data);
+                connect(wrote, true);
+            }
+            // on a read, assert that the read value is the same which was stored
+            #[hdl]
+            if rd.addr.cmp_eq(selected) & wrote {
+                hdl_assert(clk, rd.data.cmp_eq(stored), "");
+            }
+
+            // to assist induction, pass our state to the underlying instance
+            let dbg = #[hdl]
+            DebugPort {
+                selected,
+                stored,
+                wrote,
+            };
+            connect(dut.dbg, dbg);
+        }
+
+        assert_formal(
+            "sram",
+            test_module(8),
+            FormalMode::Prove,
+            2,
+            None,
+            ExportOptions::default(),
+        );
+    }
+}

From cd0dd7b7eed3a67b895b33c775583b24364fe5b4 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 9 Dec 2024 23:01:40 -0800
Subject: [PATCH 125/190] change memory write latency to NonZeroUsize to match
 read latency being usize

---
 crates/fayalite/src/memory.rs | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/crates/fayalite/src/memory.rs b/crates/fayalite/src/memory.rs
index f583a8c..4992cd6 100644
--- a/crates/fayalite/src/memory.rs
+++ b/crates/fayalite/src/memory.rs
@@ -22,7 +22,7 @@ use std::{
     fmt,
     hash::{Hash, Hasher},
     marker::PhantomData,
-    num::NonZeroU32,
+    num::NonZeroUsize,
     rc::Rc,
 };
 
@@ -478,7 +478,7 @@ struct MemImpl<Element: Type, Len: Size, P> {
     initial_value: Option<Interned<BitSlice>>,
     ports: P,
     read_latency: usize,
-    write_latency: NonZeroU32,
+    write_latency: NonZeroUsize,
     read_under_write: ReadUnderWrite,
     port_annotations: Interned<[TargetedAnnotation]>,
     mem_annotations: Interned<[Annotation]>,
@@ -562,7 +562,7 @@ impl<Element: Type, Len: Size> Mem<Element, Len> {
         initial_value: Option<Interned<BitSlice>>,
         ports: Interned<[MemPort<DynPortType>]>,
         read_latency: usize,
-        write_latency: NonZeroU32,
+        write_latency: NonZeroUsize,
         read_under_write: ReadUnderWrite,
         port_annotations: Interned<[TargetedAnnotation]>,
         mem_annotations: Interned<[Annotation]>,
@@ -645,7 +645,7 @@ impl<Element: Type, Len: Size> Mem<Element, Len> {
     pub fn read_latency(self) -> usize {
         self.0.read_latency
     }
-    pub fn write_latency(self) -> NonZeroU32 {
+    pub fn write_latency(self) -> NonZeroUsize {
         self.0.write_latency
     }
     pub fn read_under_write(self) -> ReadUnderWrite {
@@ -707,7 +707,7 @@ pub(crate) struct MemBuilderTarget {
     pub(crate) initial_value: Option<Interned<BitSlice>>,
     pub(crate) ports: Vec<MemPort<DynPortType>>,
     pub(crate) read_latency: usize,
-    pub(crate) write_latency: NonZeroU32,
+    pub(crate) write_latency: NonZeroUsize,
     pub(crate) read_under_write: ReadUnderWrite,
     pub(crate) port_annotations: Vec<TargetedAnnotation>,
     pub(crate) mem_annotations: Vec<Annotation>,
@@ -867,7 +867,7 @@ impl<Element: Type, Len: Size> MemBuilder<Element, Len> {
             initial_value: None,
             ports: vec![],
             read_latency: 0,
-            write_latency: NonZeroU32::new(1).unwrap(),
+            write_latency: NonZeroUsize::new(1).unwrap(),
             read_under_write: ReadUnderWrite::Old,
             port_annotations: vec![],
             mem_annotations: vec![],
@@ -1030,10 +1030,10 @@ impl<Element: Type, Len: Size> MemBuilder<Element, Len> {
     pub fn read_latency(&mut self, read_latency: usize) {
         self.target.borrow_mut().read_latency = read_latency;
     }
-    pub fn get_write_latency(&self) -> NonZeroU32 {
+    pub fn get_write_latency(&self) -> NonZeroUsize {
         self.target.borrow().write_latency
     }
-    pub fn write_latency(&mut self, write_latency: NonZeroU32) {
+    pub fn write_latency(&mut self, write_latency: NonZeroUsize) {
         self.target.borrow_mut().write_latency = write_latency;
     }
     pub fn get_read_under_write(&self) -> ReadUnderWrite {

From e4cf66adf8e50cfe0b2d5ac95ba220878aa295ba Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 9 Dec 2024 23:03:01 -0800
Subject: [PATCH 126/190] sim: implement memories, still needs testing

---
 crates/fayalite/src/sim.rs             | 809 ++++++++++++++++++++++---
 crates/fayalite/src/sim/interpreter.rs |  90 ++-
 crates/fayalite/tests/sim.rs           |   1 +
 3 files changed, 808 insertions(+), 92 deletions(-)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 321ab49..d2906e1 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -26,12 +26,12 @@ use crate::{
     reset::{ResetType, ResetTypeDispatch},
     sim::{
         interpreter::{
-            Insn, InsnField, InsnFieldKind, InsnFieldType, Insns, InsnsBuilding, InsnsBuildingDone,
-            SlotDebugData, SmallUInt, State, StatePartArrayIndex, StatePartArrayIndexed,
-            StatePartIndex, StatePartIndexRange, StatePartKind, StatePartKindBigSlots,
-            StatePartKindMemories, StatePartKindSmallSlots, StatePartLayout, StatePartLen,
-            StatePartsValue, TypeArrayIndex, TypeArrayIndexes, TypeIndex, TypeIndexRange,
-            TypeLayout, TypeLen, TypeParts,
+            Insn, InsnField, InsnFieldKind, InsnFieldType, InsnOrLabel, Insns, InsnsBuilding,
+            InsnsBuildingDone, InsnsBuildingKind, Label, SlotDebugData, SmallUInt, State,
+            StatePartArrayIndex, StatePartArrayIndexed, StatePartIndex, StatePartIndexRange,
+            StatePartKind, StatePartKindBigSlots, StatePartKindMemories, StatePartKindSmallSlots,
+            StatePartLayout, StatePartLen, StatePartsValue, TypeArrayIndex, TypeArrayIndexes,
+            TypeIndex, TypeIndexRange, TypeLayout, TypeLen, TypeParts,
         },
         time::{SimDuration, SimInstant},
     },
@@ -970,7 +970,7 @@ struct Assignment {
     inputs: SlotSet,
     outputs: SlotSet,
     conditions: Interned<[Cond]>,
-    insns: Vec<Insn>,
+    insns: Vec<InsnOrLabel>,
     source_location: SourceLocation,
 }
 
@@ -1116,12 +1116,16 @@ impl<'a> Extend<&'a SlotSet> for SlotToAssignmentIndexFullMapKeysForAssignment<'
 impl Assignment {
     fn new(
         conditions: Interned<[Cond]>,
-        insns: Vec<Insn>,
+        insns: Vec<InsnOrLabel>,
         source_location: SourceLocation,
     ) -> Self {
         let mut inputs = SlotSet::default();
         let mut outputs = SlotSet::default();
         for insn in &insns {
+            let insn = match insn {
+                InsnOrLabel::Insn(insn) => insn,
+                InsnOrLabel::Label(_) => continue,
+            };
             for InsnField { ty, kind } in insn.fields() {
                 match (kind, ty) {
                     (InsnFieldKind::Input, InsnFieldType::SmallSlot(&slot)) => {
@@ -1220,11 +1224,29 @@ struct MemoryPort {
     clk_triggered: StatePartIndex<StatePartKindSmallSlots>,
     addr_delayed: Vec<StatePartIndex<StatePartKindSmallSlots>>,
     en_delayed: Vec<StatePartIndex<StatePartKindSmallSlots>>,
-    data: CompiledValue<CanonicalType>,
-    read_data_delayed: Vec<TypeIndex>,
-    write_data_delayed: Vec<TypeIndex>,
-    write_mask_delayed: Vec<TypeIndex>,
+    data_layout: CompiledTypeLayout<CanonicalType>,
+    read_data_delayed: Vec<TypeIndexRange>,
+    write_data_delayed: Vec<TypeIndexRange>,
+    write_mask_delayed: Vec<TypeIndexRange>,
     write_mode_delayed: Vec<StatePartIndex<StatePartKindSmallSlots>>,
+    write_insns: Vec<InsnOrLabel>,
+}
+
+struct MemoryPortReadInsns<'a> {
+    addr: StatePartIndex<StatePartKindSmallSlots>,
+    en: StatePartIndex<StatePartKindSmallSlots>,
+    write_mode: Option<StatePartIndex<StatePartKindSmallSlots>>,
+    data: TypeIndexRange,
+    insns: &'a mut Vec<InsnOrLabel>,
+}
+
+struct MemoryPortWriteInsns<'a> {
+    addr: StatePartIndex<StatePartKindSmallSlots>,
+    en: StatePartIndex<StatePartKindSmallSlots>,
+    write_mode: Option<StatePartIndex<StatePartKindSmallSlots>>,
+    data: TypeIndexRange,
+    mask: TypeIndexRange,
+    insns: &'a mut Vec<InsnOrLabel>,
 }
 
 #[derive(Debug)]
@@ -1749,13 +1771,13 @@ impl Compiler {
         self.compiled_exprs_to_values.insert(expr, retval);
         retval
     }
-    fn add_assignment(
+    fn add_assignment<T: Into<InsnOrLabel>>(
         &mut self,
         conditions: Interned<[Cond]>,
-        insns: impl IntoIterator<Item = Insn>,
+        insns: impl IntoIterator<Item = T>,
         source_location: SourceLocation,
     ) {
-        let insns = Vec::from_iter(insns);
+        let insns = Vec::from_iter(insns.into_iter().map(Into::into));
         self.assignments
             .push(Assignment::new(conditions, insns, source_location));
     }
@@ -1828,12 +1850,14 @@ impl Compiler {
         {
             return retval;
         }
+        let mut ty = compiled_value.layout.ty;
+        ty.width = ty.width.min(SmallUInt::BITS as usize);
         let retval = match compiled_value.range.len() {
             TypeLen::A_SMALL_SLOT => compiled_value.range.small_slots.start,
             TypeLen::A_BIG_SLOT => {
                 let debug_data = SlotDebugData {
                     name: Interned::default(),
-                    ty: UInt::<{ SmallUInt::BITS as usize }>::TYPE.canonical(),
+                    ty: ty.canonical(),
                 };
                 let dest = self
                     .insns
@@ -3324,6 +3348,443 @@ impl Compiler {
         }
         self.make_trace_decl(*parent_module, target_base)
     }
+    fn allocate_delay_chain<T, BK: InsnsBuildingKind>(
+        &mut self,
+        len: usize,
+        layout: &TypeLayout<BK>,
+        first: Option<T>,
+        last: Option<T>,
+        mut from_allocation: impl FnMut(TypeIndexRange) -> T,
+    ) -> Vec<T> {
+        match (len, first, last) {
+            (0, _, _) => Vec::new(),
+            (1, Some(v), _) | (1, None, Some(v)) => vec![v],
+            (2, Some(first), Some(last)) => vec![first, last],
+            (len, first, last) => {
+                let inner_len = len - first.is_some() as usize - last.is_some() as usize;
+                first
+                    .into_iter()
+                    .chain(
+                        (0..inner_len)
+                            .map(|_| from_allocation(self.insns.allocate_variable(layout))),
+                    )
+                    .chain(last)
+                    .collect()
+            }
+        }
+    }
+    fn allocate_delay_chain_small(
+        &mut self,
+        len: usize,
+        ty: CanonicalType,
+        first: Option<StatePartIndex<StatePartKindSmallSlots>>,
+        last: Option<StatePartIndex<StatePartKindSmallSlots>>,
+    ) -> Vec<StatePartIndex<StatePartKindSmallSlots>> {
+        self.allocate_delay_chain(
+            len,
+            &TypeLayout {
+                small_slots: StatePartLayout::scalar(
+                    SlotDebugData {
+                        name: Interned::default(),
+                        ty,
+                    },
+                    (),
+                ),
+                big_slots: StatePartLayout::empty(),
+            },
+            first,
+            last,
+            |range| range.small_slots.start,
+        )
+    }
+    fn compile_memory_port_rw_helper(
+        &mut self,
+        memory: StatePartIndex<StatePartKindMemories>,
+        stride: usize,
+        mut start: usize,
+        data_layout: CompiledTypeLayout<CanonicalType>,
+        mask_layout: CompiledTypeLayout<CanonicalType>,
+        mut read: Option<MemoryPortReadInsns<'_>>,
+        mut write: Option<MemoryPortWriteInsns<'_>>,
+    ) {
+        match data_layout.body {
+            CompiledTypeLayoutBody::Scalar => {
+                let CompiledTypeLayoutBody::Scalar = mask_layout.body else {
+                    unreachable!();
+                };
+                let signed = match data_layout.ty {
+                    CanonicalType::UInt(_) => false,
+                    CanonicalType::SInt(_) => true,
+                    CanonicalType::Bool(_) => false,
+                    CanonicalType::Array(_) => unreachable!(),
+                    CanonicalType::Enum(_) => false,
+                    CanonicalType::Bundle(_) => unreachable!(),
+                    CanonicalType::AsyncReset(_) => false,
+                    CanonicalType::SyncReset(_) => false,
+                    CanonicalType::Reset(_) => false,
+                    CanonicalType::Clock(_) => false,
+                };
+                let width = data_layout.ty.bit_width();
+                if let Some(MemoryPortReadInsns {
+                    addr,
+                    en: _,
+                    write_mode: _,
+                    data,
+                    insns,
+                }) = read
+                {
+                    insns.push(
+                        match data.len() {
+                            TypeLen::A_BIG_SLOT => {
+                                let dest = data.big_slots.start;
+                                if signed {
+                                    Insn::MemoryReadSInt {
+                                        dest,
+                                        memory,
+                                        addr,
+                                        stride,
+                                        start,
+                                        width,
+                                    }
+                                } else {
+                                    Insn::MemoryReadUInt {
+                                        dest,
+                                        memory,
+                                        addr,
+                                        stride,
+                                        start,
+                                        width,
+                                    }
+                                }
+                            }
+                            TypeLen::A_SMALL_SLOT => {
+                                let _dest = data.small_slots.start;
+                                todo!("memory ports' data are always big for now");
+                            }
+                            _ => unreachable!(),
+                        }
+                        .into(),
+                    );
+                }
+                if let Some(MemoryPortWriteInsns {
+                    addr,
+                    en: _,
+                    write_mode: _,
+                    data,
+                    mask,
+                    insns,
+                }) = write
+                {
+                    let end_label = self.insns.new_label();
+                    insns.push(
+                        match mask.len() {
+                            TypeLen::A_BIG_SLOT => Insn::BranchIfZero {
+                                target: end_label.0,
+                                value: mask.big_slots.start,
+                            },
+                            TypeLen::A_SMALL_SLOT => Insn::BranchIfSmallZero {
+                                target: end_label.0,
+                                value: mask.small_slots.start,
+                            },
+                            _ => unreachable!(),
+                        }
+                        .into(),
+                    );
+                    insns.push(
+                        match data.len() {
+                            TypeLen::A_BIG_SLOT => {
+                                let dest = data.big_slots.start;
+                                if signed {
+                                    Insn::MemoryReadSInt {
+                                        dest,
+                                        memory,
+                                        addr,
+                                        stride,
+                                        start,
+                                        width,
+                                    }
+                                } else {
+                                    Insn::MemoryReadUInt {
+                                        dest,
+                                        memory,
+                                        addr,
+                                        stride,
+                                        start,
+                                        width,
+                                    }
+                                }
+                            }
+                            TypeLen::A_SMALL_SLOT => {
+                                let _dest = data.small_slots.start;
+                                todo!("memory ports' data are always big for now");
+                            }
+                            _ => unreachable!(),
+                        }
+                        .into(),
+                    );
+                    insns.push(end_label.into());
+                }
+            }
+            CompiledTypeLayoutBody::Array { element } => {
+                let CompiledTypeLayoutBody::Array {
+                    element: mask_element,
+                } = mask_layout.body
+                else {
+                    unreachable!();
+                };
+                let ty = <Array>::from_canonical(data_layout.ty);
+                let element_bit_width = ty.element().bit_width();
+                let element_size = element.layout.len();
+                let mask_element_size = mask_element.layout.len();
+                for element_index in 0..ty.len() {
+                    self.compile_memory_port_rw_helper(
+                        memory,
+                        stride,
+                        start,
+                        *element,
+                        *mask_element,
+                        read.as_mut().map(
+                            |MemoryPortReadInsns {
+                                 addr,
+                                 en,
+                                 write_mode,
+                                 data,
+                                 insns,
+                             }| MemoryPortReadInsns {
+                                addr: *addr,
+                                en: *en,
+                                write_mode: *write_mode,
+                                data: data.index_array(element_size, element_index),
+                                insns,
+                            },
+                        ),
+                        write.as_mut().map(
+                            |MemoryPortWriteInsns {
+                                 addr,
+                                 en,
+                                 write_mode,
+                                 data,
+                                 mask,
+                                 insns,
+                             }| {
+                                MemoryPortWriteInsns {
+                                    addr: *addr,
+                                    en: *en,
+                                    write_mode: *write_mode,
+                                    data: data.index_array(element_size, element_index),
+                                    mask: mask.index_array(mask_element_size, element_index),
+                                    insns,
+                                }
+                            },
+                        ),
+                    );
+                    start += element_bit_width;
+                }
+            }
+            CompiledTypeLayoutBody::Bundle { fields } => {
+                let CompiledTypeLayoutBody::Bundle {
+                    fields: mask_fields,
+                } = mask_layout.body
+                else {
+                    unreachable!();
+                };
+                assert_eq!(fields.len(), mask_fields.len());
+                for (field, mask_field) in fields.into_iter().zip(mask_fields) {
+                    let field_index_range =
+                        TypeIndexRange::new(field.offset, field.ty.layout.len());
+                    let mask_field_index_range =
+                        TypeIndexRange::new(mask_field.offset, mask_field.ty.layout.len());
+                    self.compile_memory_port_rw_helper(
+                        memory,
+                        stride,
+                        start,
+                        field.ty,
+                        mask_field.ty,
+                        read.as_mut().map(
+                            |MemoryPortReadInsns {
+                                 addr,
+                                 en,
+                                 write_mode,
+                                 data,
+                                 insns,
+                             }| MemoryPortReadInsns {
+                                addr: *addr,
+                                en: *en,
+                                write_mode: *write_mode,
+                                data: data.slice(field_index_range),
+                                insns,
+                            },
+                        ),
+                        write.as_mut().map(
+                            |MemoryPortWriteInsns {
+                                 addr,
+                                 en,
+                                 write_mode,
+                                 data,
+                                 mask,
+                                 insns,
+                             }| {
+                                MemoryPortWriteInsns {
+                                    addr: *addr,
+                                    en: *en,
+                                    write_mode: *write_mode,
+                                    data: data.slice(field_index_range),
+                                    mask: mask.slice(mask_field_index_range),
+                                    insns,
+                                }
+                            },
+                        ),
+                    );
+                    start = start + field.ty.ty.bit_width();
+                }
+            }
+        }
+    }
+    fn compile_memory_port_rw(
+        &mut self,
+        memory: StatePartIndex<StatePartKindMemories>,
+        data_layout: CompiledTypeLayout<CanonicalType>,
+        mask_layout: CompiledTypeLayout<CanonicalType>,
+        mut read: Option<MemoryPortReadInsns<'_>>,
+        mut write: Option<MemoryPortWriteInsns<'_>>,
+    ) {
+        let read_else_label = read.as_mut().map(
+            |MemoryPortReadInsns {
+                 addr: _,
+                 en,
+                 write_mode,
+                 data: _,
+                 insns,
+             }| {
+                let else_label = self.insns.new_label();
+                insns.push(
+                    Insn::BranchIfSmallZero {
+                        target: else_label.0,
+                        value: *en,
+                    }
+                    .into(),
+                );
+                if let Some(write_mode) = *write_mode {
+                    insns.push(
+                        Insn::BranchIfSmallNonZero {
+                            target: else_label.0,
+                            value: write_mode,
+                        }
+                        .into(),
+                    );
+                }
+                else_label
+            },
+        );
+        let write_end_label = write.as_mut().map(
+            |MemoryPortWriteInsns {
+                 addr: _,
+                 en,
+                 write_mode,
+                 data: _,
+                 mask: _,
+                 insns,
+             }| {
+                let end_label = self.insns.new_label();
+                insns.push(
+                    Insn::BranchIfSmallZero {
+                        target: end_label.0,
+                        value: *en,
+                    }
+                    .into(),
+                );
+                if let Some(write_mode) = *write_mode {
+                    insns.push(
+                        Insn::BranchIfSmallZero {
+                            target: end_label.0,
+                            value: write_mode,
+                        }
+                        .into(),
+                    );
+                }
+                end_label
+            },
+        );
+        self.compile_memory_port_rw_helper(
+            memory,
+            data_layout.ty.bit_width(),
+            0,
+            data_layout,
+            mask_layout,
+            read.as_mut().map(
+                |MemoryPortReadInsns {
+                     addr,
+                     en,
+                     write_mode,
+                     data,
+                     insns,
+                 }| MemoryPortReadInsns {
+                    addr: *addr,
+                    en: *en,
+                    write_mode: *write_mode,
+                    data: *data,
+                    insns: *insns,
+                },
+            ),
+            write.as_mut().map(
+                |MemoryPortWriteInsns {
+                     addr,
+                     en,
+                     write_mode,
+                     data,
+                     mask,
+                     insns,
+                 }| MemoryPortWriteInsns {
+                    addr: *addr,
+                    en: *en,
+                    write_mode: *write_mode,
+                    data: *data,
+                    mask: *mask,
+                    insns: *insns,
+                },
+            ),
+        );
+        if let (
+            Some(else_label),
+            Some(MemoryPortReadInsns {
+                addr: _,
+                en: _,
+                write_mode: _,
+                data,
+                insns,
+            }),
+        ) = (read_else_label, read)
+        {
+            let end_label = self.insns.new_label();
+            insns.push(
+                Insn::Branch {
+                    target: end_label.0,
+                }
+                .into(),
+            );
+            insns.push(else_label.into());
+            let TypeIndexRange {
+                small_slots,
+                big_slots,
+            } = data;
+            for dest in small_slots.iter() {
+                insns.push(Insn::ConstSmall { dest, value: 0 }.into());
+            }
+            for dest in big_slots.iter() {
+                insns.push(
+                    Insn::Const {
+                        dest,
+                        value: BigInt::ZERO.intern_sized(),
+                    }
+                    .into(),
+                );
+            }
+            insns.push(end_label.into());
+        }
+        if let (Some(end_label), Some(write)) = (write_end_label, write) {
+            write.insns.push(end_label.into());
+        }
+    }
     fn compile_memory(
         &mut self,
         mem: Mem,
@@ -3331,6 +3792,22 @@ impl Compiler {
         conditions: Interned<[Cond]>,
         trace_decls: &mut Vec<TraceDecl>,
     ) {
+        let data_layout = CompiledTypeLayout::get(mem.array_type().element());
+        let mask_layout = CompiledTypeLayout::get(mem.array_type().element().mask_type());
+        let read_latency_plus_1 = mem
+            .read_latency()
+            .checked_add(1)
+            .expect("read latency too big");
+        let write_latency_plus_1 = mem
+            .write_latency()
+            .get()
+            .checked_add(1)
+            .expect("write latency too big");
+        let read_cycle = match mem.read_under_write() {
+            ReadUnderWrite::Old => 0,
+            ReadUnderWrite::New => mem.read_latency(),
+            ReadUnderWrite::Undefined => mem.read_latency() / 2, // something other than Old or New
+        };
         let memory = self
             .insns
             .state_layout
@@ -3356,42 +3833,188 @@ impl Compiler {
                 };
                 self.decl_conditions.insert(target, conditions);
                 trace_decls.push(self.make_trace_decl(instantiated_module, target_base));
-                match port.port_kind() {
-                    PortKind::ReadOnly => MemoryPort {
-                        clk_triggered: todo!(),
-                        addr_delayed: todo!(),
-                        en_delayed: todo!(),
-                        data: todo!(),
-                        read_data_delayed: todo!(),
-                        write_data_delayed: todo!(),
-                        write_mask_delayed: todo!(),
-                        write_mode_delayed: todo!(),
+                let clk = Expr::field(port.to_expr(), "clk");
+                let clk = self.compile_expr(instantiated_module, clk);
+                let clk = self.compiled_expr_to_value(clk, mem.source_location());
+                let clk_triggered = self
+                    .compile_clock(clk.map_ty(Clock::from_canonical), mem.source_location())
+                    .clk_triggered;
+                let en = Expr::field(port.to_expr(), "en");
+                let en = self.compile_expr(instantiated_module, en);
+                let en = self.compiled_expr_to_value(en, mem.source_location());
+                let en = self.compiled_value_bool_dest_is_small(en, mem.source_location());
+                let addr = Expr::field(port.to_expr(), "addr");
+                let addr = self.compile_expr(instantiated_module, addr);
+                let addr = self.compiled_expr_to_value(addr, mem.source_location());
+                let addr_ty = addr.layout.ty;
+                let addr = self.compiled_value_to_dyn_array_index(
+                    addr.map_ty(UInt::from_canonical),
+                    mem.source_location(),
+                );
+                let read_data = port.port_kind().rdata_name().map(|name| {
+                    let read_data =
+                        self.compile_expr(instantiated_module, Expr::field(port.to_expr(), name));
+                    let read_data = self.compiled_expr_to_value(read_data, mem.source_location());
+                    read_data.range
+                });
+                let write_data = port.port_kind().wdata_name().map(|name| {
+                    let write_data =
+                        self.compile_expr(instantiated_module, Expr::field(port.to_expr(), name));
+                    let write_data = self.compiled_expr_to_value(write_data, mem.source_location());
+                    write_data.range
+                });
+                let write_mask = port.port_kind().wmask_name().map(|name| {
+                    let write_mask =
+                        self.compile_expr(instantiated_module, Expr::field(port.to_expr(), name));
+                    let write_mask = self.compiled_expr_to_value(write_mask, mem.source_location());
+                    write_mask.range
+                });
+                let write_mode = port.port_kind().wmode_name().map(|name| {
+                    let write_mode =
+                        self.compile_expr(instantiated_module, Expr::field(port.to_expr(), name));
+                    let write_mode = self.compiled_expr_to_value(write_mode, mem.source_location());
+                    self.compiled_value_bool_dest_is_small(write_mode, mem.source_location())
+                });
+                struct PortParts {
+                    en_delayed_len: usize,
+                    addr_delayed_len: usize,
+                    read_data_delayed_len: usize,
+                    write_data_delayed_len: usize,
+                    write_mask_delayed_len: usize,
+                    write_mode_delayed_len: usize,
+                    read_cycle: Option<usize>,
+                    write_cycle: Option<usize>,
+                }
+                let PortParts {
+                    en_delayed_len,
+                    addr_delayed_len,
+                    read_data_delayed_len,
+                    write_data_delayed_len,
+                    write_mask_delayed_len,
+                    write_mode_delayed_len,
+                    read_cycle,
+                    write_cycle,
+                } = match port.port_kind() {
+                    PortKind::ReadOnly => PortParts {
+                        en_delayed_len: read_cycle + 1,
+                        addr_delayed_len: read_cycle + 1,
+                        read_data_delayed_len: read_latency_plus_1 - read_cycle,
+                        write_data_delayed_len: 0,
+                        write_mask_delayed_len: 0,
+                        write_mode_delayed_len: 0,
+                        read_cycle: Some(read_cycle),
+                        write_cycle: None,
                     },
-                    PortKind::WriteOnly => MemoryPort {
-                        clk_triggered: todo!(),
-                        addr_delayed: todo!(),
-                        en_delayed: todo!(),
-                        data: todo!(),
-                        read_data_delayed: todo!(),
-                        write_data_delayed: todo!(),
-                        write_mask_delayed: todo!(),
-                        write_mode_delayed: todo!(),
-                    },
-                    PortKind::ReadWrite => MemoryPort {
-                        clk_triggered: todo!(),
-                        addr_delayed: todo!(),
-                        en_delayed: todo!(),
-                        data: todo!(),
-                        read_data_delayed: todo!(),
-                        write_data_delayed: todo!(),
-                        write_mask_delayed: todo!(),
-                        write_mode_delayed: todo!(),
+                    PortKind::WriteOnly => PortParts {
+                        en_delayed_len: write_latency_plus_1,
+                        addr_delayed_len: write_latency_plus_1,
+                        read_data_delayed_len: 0,
+                        write_data_delayed_len: write_latency_plus_1,
+                        write_mask_delayed_len: write_latency_plus_1,
+                        write_mode_delayed_len: 0,
+                        read_cycle: None,
+                        write_cycle: Some(mem.write_latency().get()),
                     },
+                    PortKind::ReadWrite => {
+                        let can_rw_at_end = match mem.read_under_write() {
+                            ReadUnderWrite::Old => false,
+                            ReadUnderWrite::New | ReadUnderWrite::Undefined => true,
+                        };
+                        let latency_plus_1 = read_latency_plus_1;
+                        if latency_plus_1 != write_latency_plus_1 || !can_rw_at_end {
+                            todo!(
+                                "not sure what to do, issue: \
+                                https://github.com/chipsalliance/firrtl-spec/issues/263"
+                            );
+                        }
+                        PortParts {
+                            en_delayed_len: latency_plus_1,
+                            addr_delayed_len: latency_plus_1,
+                            read_data_delayed_len: 1,
+                            write_data_delayed_len: latency_plus_1,
+                            write_mask_delayed_len: latency_plus_1,
+                            write_mode_delayed_len: latency_plus_1,
+                            read_cycle: Some(latency_plus_1 - 1),
+                            write_cycle: Some(latency_plus_1 - 1),
+                        }
+                    }
+                };
+                let addr_delayed = self.allocate_delay_chain_small(
+                    addr_delayed_len,
+                    addr_ty.canonical(),
+                    Some(addr),
+                    None,
+                );
+                let en_delayed = self.allocate_delay_chain_small(
+                    en_delayed_len,
+                    Bool.canonical(),
+                    Some(en),
+                    None,
+                );
+                let read_data_delayed = self.allocate_delay_chain(
+                    read_data_delayed_len,
+                    &data_layout.layout,
+                    None,
+                    read_data,
+                    |v| v,
+                );
+                let write_data_delayed = self.allocate_delay_chain(
+                    write_data_delayed_len,
+                    &data_layout.layout,
+                    write_data,
+                    None,
+                    |v| v,
+                );
+                let write_mask_delayed = self.allocate_delay_chain(
+                    write_mask_delayed_len,
+                    &mask_layout.layout,
+                    write_mask,
+                    None,
+                    |v| v,
+                );
+                let write_mode_delayed = self.allocate_delay_chain_small(
+                    write_mode_delayed_len,
+                    Bool.canonical(),
+                    write_mode,
+                    None,
+                );
+                let mut read_insns = Vec::new();
+                let mut write_insns = Vec::new();
+                self.compile_memory_port_rw(
+                    memory,
+                    data_layout,
+                    mask_layout,
+                    read_cycle.map(|read_cycle| MemoryPortReadInsns {
+                        addr: addr_delayed[read_cycle],
+                        en: en_delayed[read_cycle],
+                        write_mode: write_mode_delayed.get(read_cycle).copied(),
+                        data: read_data_delayed[0],
+                        insns: &mut read_insns,
+                    }),
+                    write_cycle.map(|write_cycle| MemoryPortWriteInsns {
+                        addr: addr_delayed[write_cycle],
+                        en: en_delayed[write_cycle],
+                        write_mode: write_mode_delayed.get(write_cycle).copied(),
+                        data: write_data_delayed[write_cycle],
+                        mask: write_mask_delayed[write_cycle],
+                        insns: &mut write_insns,
+                    }),
+                );
+                self.add_assignment(Interned::default(), read_insns, mem.source_location());
+                MemoryPort {
+                    clk_triggered,
+                    addr_delayed,
+                    en_delayed,
+                    data_layout,
+                    read_data_delayed,
+                    write_data_delayed,
+                    write_mask_delayed,
+                    write_mode_delayed,
+                    write_insns,
                 }
             })
             .collect();
         self.memories.push(Memory { mem, memory, ports });
-        todo!("implement memory");
     }
     fn compile_block(
         &mut self,
@@ -3549,7 +4172,7 @@ impl Compiler {
         };
         struct CondStackEntry<'a> {
             cond: &'a Cond,
-            end_label_index: usize,
+            end_label: Label,
         }
         let mut cond_stack = Vec::<CondStackEntry<'_>>::new();
         for assignment_index in assignments_order {
@@ -3568,35 +4191,33 @@ impl Compiler {
                 same_len = index + 1;
             }
             while cond_stack.len() > same_len {
-                let CondStackEntry {
-                    cond: _,
-                    end_label_index,
-                } = cond_stack.pop().expect("just checked len");
-                self.insns.define_label_at_next_insn(end_label_index);
+                let CondStackEntry { cond: _, end_label } =
+                    cond_stack.pop().expect("just checked len");
+                self.insns.define_label_at_next_insn(end_label);
             }
             for cond in &conditions[cond_stack.len()..] {
-                let end_label_index = self.insns.new_label();
+                let end_label = self.insns.new_label();
                 match cond.body {
                     CondBody::IfTrue { cond: cond_value }
                     | CondBody::IfFalse { cond: cond_value } => {
                         let (branch_if_zero, branch_if_non_zero) = match cond_value.range.len() {
                             TypeLen::A_SMALL_SLOT => (
                                 Insn::BranchIfSmallZero {
-                                    target: end_label_index,
+                                    target: end_label.0,
                                     value: cond_value.range.small_slots.start,
                                 },
                                 Insn::BranchIfSmallNonZero {
-                                    target: end_label_index,
+                                    target: end_label.0,
                                     value: cond_value.range.small_slots.start,
                                 },
                             ),
                             TypeLen::A_BIG_SLOT => (
                                 Insn::BranchIfZero {
-                                    target: end_label_index,
+                                    target: end_label.0,
                                     value: cond_value.range.big_slots.start,
                                 },
                                 Insn::BranchIfNonZero {
-                                    target: end_label_index,
+                                    target: end_label.0,
                                     value: cond_value.range.big_slots.start,
                                 },
                             ),
@@ -3617,7 +4238,7 @@ impl Compiler {
                     } => {
                         self.insns.push(
                             Insn::BranchIfSmallNeImmediate {
-                                target: end_label_index,
+                                target: end_label.0,
                                 lhs: discriminant,
                                 rhs: variant_index as _,
                             },
@@ -3625,14 +4246,9 @@ impl Compiler {
                         );
                     }
                 }
-                cond_stack.push(CondStackEntry {
-                    cond,
-                    end_label_index,
-                });
-            }
-            for insn in insns {
-                self.insns.push(*insn, *source_location);
+                cond_stack.push(CondStackEntry { cond, end_label });
             }
+            self.insns.extend(insns.iter().copied(), *source_location);
         }
     }
     fn process_clocks(&mut self) -> Interned<[StatePartIndex<StatePartKindSmallSlots>]> {
@@ -3674,11 +4290,11 @@ impl Compiler {
                     let reg_end = self.insns.new_label();
                     let reg_reset = self.insns.new_label();
                     let branch_if_reset = Insn::BranchIfSmallNonZero {
-                        target: reg_reset,
+                        target: reg_reset.0,
                         value: rst,
                     };
                     let branch_if_not_triggered = Insn::BranchIfSmallZero {
-                        target: reg_end,
+                        target: reg_end.0,
                         value: clk_triggered,
                     };
                     if is_async {
@@ -3693,7 +4309,7 @@ impl Compiler {
                         source_location,
                     );
                     self.insns
-                        .push(Insn::Branch { target: reg_end }, source_location);
+                        .push(Insn::Branch { target: reg_end.0 }, source_location);
                     self.insns.define_label_at_next_insn(reg_reset);
                     self.insns
                         .extend(value.range.insns_for_copy_from(init.range), source_location);
@@ -3703,7 +4319,7 @@ impl Compiler {
                     let reg_end = self.insns.new_label();
                     self.insns.push(
                         Insn::BranchIfSmallZero {
-                            target: reg_end,
+                            target: reg_end.0,
                             value: clk_triggered,
                         },
                         source_location,
@@ -3718,8 +4334,59 @@ impl Compiler {
         }
     }
     fn process_memories(&mut self) {
-        for memory in mem::take(&mut self.memories) {
-            todo!();
+        for Memory {
+            mem,
+            memory: _,
+            ports,
+        } in mem::take(&mut self.memories)
+        {
+            for MemoryPort {
+                clk_triggered,
+                addr_delayed,
+                en_delayed,
+                data_layout: _,
+                read_data_delayed,
+                write_data_delayed,
+                write_mask_delayed,
+                write_mode_delayed,
+                write_insns,
+            } in ports
+            {
+                let port_end = self.insns.new_label();
+                self.insns.push(
+                    Insn::BranchIfSmallZero {
+                        target: port_end.0,
+                        value: clk_triggered,
+                    },
+                    mem.source_location(),
+                );
+                self.insns.extend(write_insns, mem.source_location());
+                let small_shift_reg =
+                    |this: &mut Self, values: &[StatePartIndex<StatePartKindSmallSlots>]| {
+                        for pair in values.windows(2).rev() {
+                            this.insns.push(
+                                Insn::CopySmall {
+                                    dest: pair[1],
+                                    src: pair[0],
+                                },
+                                mem.source_location(),
+                            );
+                        }
+                    };
+                let shift_reg = |this: &mut Self, values: &[TypeIndexRange]| {
+                    for pair in values.windows(2).rev() {
+                        this.insns
+                            .extend(pair[0].insns_for_copy_to(pair[1]), mem.source_location());
+                    }
+                };
+                small_shift_reg(self, &addr_delayed);
+                small_shift_reg(self, &en_delayed);
+                shift_reg(self, &read_data_delayed);
+                shift_reg(self, &write_data_delayed);
+                shift_reg(self, &write_mask_delayed);
+                small_shift_reg(self, &write_mode_delayed);
+                self.insns.define_label_at_next_insn(port_end);
+            }
         }
     }
     pub fn compile(mut self) -> Compiled<Bundle> {
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index 0fd0591..23d1275 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -477,14 +477,50 @@ impl InsnsBuildingKind for InsnsBuilding {
     }
 }
 
-struct Label {
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+pub(crate) struct Label(pub(crate) usize);
+
+impl fmt::Debug for Label {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "L{}:", self.0)
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+pub(crate) enum InsnOrLabel {
+    Insn(Insn),
+    Label(Label),
+}
+
+impl From<Insn> for InsnOrLabel {
+    fn from(value: Insn) -> Self {
+        Self::Insn(value)
+    }
+}
+
+impl From<Label> for InsnOrLabel {
+    fn from(value: Label) -> Self {
+        Self::Label(value)
+    }
+}
+
+impl fmt::Debug for InsnOrLabel {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self {
+            Self::Insn(v) => v.fmt(f),
+            Self::Label(v) => v.fmt(f),
+        }
+    }
+}
+
+struct LabelData {
     address: Option<usize>,
 }
 
 #[derive(Default)]
 pub(crate) struct Labels {
-    labels: Vec<Label>,
-    address_to_label_indexes_map: HashMap<usize, Vec<usize>>,
+    labels: Vec<LabelData>,
+    address_to_label_map: HashMap<usize, Vec<Label>>,
 }
 
 #[derive(Clone, PartialEq, Eq, Hash)]
@@ -518,12 +554,12 @@ struct InsnDebug<'a, BK: InsnsBuildingKind> {
 
 impl<BK: InsnsBuildingKind> fmt::Debug for InsnDebug<'_, BK> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        if let Some(label_indexes) = self
+        if let Some(labels) = self
             .labels
-            .and_then(|labels| labels.address_to_label_indexes_map.get(&self.address))
+            .and_then(|labels| labels.address_to_label_map.get(&self.address))
         {
-            for &label_index in label_indexes {
-                writeln!(f, "L{label_index}:")?;
+            for &label in labels {
+                writeln!(f, "{label:?}")?;
             }
         }
         if let Some(source_location) = self.source_location {
@@ -2019,14 +2055,17 @@ impl Insns<InsnsBuilding> {
         self.insns.push(insn);
         self.insn_source_locations.push(source_location);
     }
-    pub(crate) fn extend(
+    pub(crate) fn extend<T: Into<InsnOrLabel>>(
         &mut self,
-        insns: impl IntoIterator<Item = Insn>,
+        insns_or_labels: impl IntoIterator<Item = T>,
         source_location: SourceLocation,
     ) {
-        self.insns.extend(insns);
-        self.insn_source_locations
-            .resize(self.insns.len(), source_location);
+        for insn_or_label in insns_or_labels {
+            match insn_or_label.into() {
+                InsnOrLabel::Insn(insn) => self.push(insn, source_location),
+                InsnOrLabel::Label(label) => self.define_label_at_next_insn(label),
+            }
+        }
     }
     pub(crate) fn allocate_variable<BK: InsnsBuildingKind>(
         &mut self,
@@ -2034,22 +2073,22 @@ impl Insns<InsnsBuilding> {
     ) -> TypeIndexRange {
         self.state_layout.ty.allocate(layout)
     }
-    pub(crate) fn new_label(&mut self) -> usize {
-        let retval = self.labels.labels.len();
-        self.labels.labels.push(Label { address: None });
+    pub(crate) fn new_label(&mut self) -> Label {
+        let retval = Label(self.labels.labels.len());
+        self.labels.labels.push(LabelData { address: None });
         retval
     }
     #[track_caller]
-    pub(crate) fn define_label_at_next_insn(&mut self, label_index: usize) {
+    pub(crate) fn define_label_at_next_insn(&mut self, label: Label) {
         let address = self.next_insn_pc();
-        let label = &mut self.labels.labels[label_index];
-        assert!(label.address.is_none(), "label already defined");
-        label.address = Some(address);
+        let label_data = &mut self.labels.labels[label.0];
+        assert!(label_data.address.is_none(), "label already defined");
+        label_data.address = Some(address);
         self.labels
-            .address_to_label_indexes_map
+            .address_to_label_map
             .entry(address)
             .or_default()
-            .push(label_index);
+            .push(label);
     }
 }
 
@@ -2727,6 +2766,15 @@ impl_insns! {
         state.big_slots[dest].clone_from(&value);
         next!();
     }
+    ConstSmall {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        value: SmallUInt,
+    } => {
+        state.small_slots[dest] = value;
+        next!();
+    }
     Branch {
         #[kind = BranchTarget]
         target: usize,
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index e65064d..914e64f 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -294,3 +294,4 @@ fn test_shift_register() {
 }
 
 // TODO: add tests for enums
+// TODO: add tests for memories

From ca759168ff1af50d63c2353dded566e7d5d6ab13 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 10 Dec 2024 23:37:26 -0800
Subject: [PATCH 127/190] tests/sim: add WIP test for enums

---
 crates/fayalite/tests/sim.rs                 | 201 ++++++++++++++++++-
 crates/fayalite/tests/sim/expected/enums.txt |   0
 crates/fayalite/tests/sim/expected/enums.vcd |   0
 3 files changed, 200 insertions(+), 1 deletion(-)
 create mode 100644 crates/fayalite/tests/sim/expected/enums.txt
 create mode 100644 crates/fayalite/tests/sim/expected/enums.vcd

diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 914e64f..db20df2 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -293,5 +293,204 @@ fn test_shift_register() {
     }
 }
 
-// TODO: add tests for enums
+#[hdl_module(outline_generated)]
+pub fn enums() {
+    #[hdl]
+    let cd: ClockDomain<SyncReset> = m.input();
+    #[hdl]
+    let en: Bool = m.input();
+    #[hdl]
+    let which_in: UInt<2> = m.input();
+    #[hdl]
+    let data_in: UInt<4> = m.input();
+    #[hdl]
+    let which_out: UInt<2> = m.output();
+    #[hdl]
+    let data_out: UInt<4> = m.output();
+
+    #[hdl]
+    struct MyStruct<T> {
+        a: T,
+        b: SInt<2>,
+    }
+
+    #[hdl]
+    enum MyEnum {
+        A,
+        B((UInt<1>, Bool)),
+        C(MyStruct<Array<UInt<1>, 2>>),
+    }
+
+    #[hdl]
+    let the_reg = reg_builder().clock_domain(cd).reset(MyEnum.A());
+
+    #[hdl]
+    if en {
+        #[hdl]
+        if which_in.cmp_eq(0_hdl_u2) {
+            connect(the_reg, MyEnum.A());
+        } else if which_in.cmp_eq(1_hdl_u2) {
+            connect(the_reg, MyEnum.B((data_in[0].cast_to_static(), data_in[1])));
+        } else {
+            connect(
+                the_reg,
+                MyEnum.C(
+                    #[hdl]
+                    MyStruct {
+                        a: #[hdl]
+                        [data_in[0].cast_to_static(), data_in[1].cast_to_static()],
+                        b: data_in[2..4].cast_to_static(),
+                    },
+                ),
+            );
+        }
+    }
+
+    #[hdl]
+    match the_reg {
+        MyEnum::A => {
+            connect(which_out, 0_hdl_u2);
+            connect(data_out, 0_hdl_u4);
+        }
+        MyEnum::B(v) => {
+            connect(which_out, 1_hdl_u2);
+            connect_any(data_out, v.0 | (v.1.cast_to_static::<UInt<1>>() << 1));
+        }
+        MyEnum::C(v) => {
+            connect(which_out, 2_hdl_u2);
+            connect_any(data_out, v.cast_to_bits());
+        }
+    }
+}
+
+#[cfg(todo)] // FIXME: enum lowering currently broken
+#[hdl]
+#[test]
+fn test_enums() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(enums());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
+    sim.write_bool(sim.io().en, false);
+    sim.write_bool_or_int(sim.io().which_in, 0_hdl_u2);
+    sim.write_bool_or_int(sim.io().data_in, 0_hdl_u4);
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.write_clock(sim.io().cd.clk, true);
+    sim.advance_time(SimDuration::from_nanos(100));
+    sim.write_reset(sim.io().cd.rst, false);
+    sim.advance_time(SimDuration::from_nanos(900));
+    #[derive(Debug, PartialEq, Eq)]
+    struct IO {
+        en: bool,
+        which_in: u8,
+        data_in: u8,
+        which_out: u8,
+        data_out: u8,
+    }
+    let io_cycles = [
+        IO {
+            en: false,
+            which_in: 0,
+            data_in: 0,
+            which_out: 0,
+            data_out: 0,
+        },
+        IO {
+            en: true,
+            which_in: 1,
+            data_in: 0,
+            which_out: 0,
+            data_out: 0,
+        },
+        IO {
+            en: false,
+            which_in: 0,
+            data_in: 0,
+            which_out: 1,
+            data_out: 0,
+        },
+        IO {
+            en: true,
+            which_in: 1,
+            data_in: 0xF,
+            which_out: 1,
+            data_out: 0,
+        },
+        IO {
+            en: true,
+            which_in: 1,
+            data_in: 0xF,
+            which_out: 1,
+            data_out: 0x3,
+        },
+        IO {
+            en: true,
+            which_in: 2,
+            data_in: 0xF,
+            which_out: 1,
+            data_out: 0x3,
+        },
+        IO {
+            en: true,
+            which_in: 2,
+            data_in: 0xF,
+            which_out: 2,
+            data_out: 0xF,
+        },
+    ];
+    for (
+        cycle,
+        expected @ IO {
+            en,
+            which_in,
+            data_in,
+            which_out: _,
+            data_out: _,
+        },
+    ) in io_cycles.into_iter().enumerate()
+    {
+        sim.write_bool(sim.io().en, en);
+        sim.write_bool_or_int(sim.io().which_in, which_in.cast_to_static());
+        sim.write_bool_or_int(sim.io().data_in, data_in.cast_to_static());
+        let io = IO {
+            en,
+            which_in,
+            data_in,
+            which_out: sim
+                .read_bool_or_int(sim.io().which_out)
+                .to_bigint()
+                .try_into()
+                .expect("known to be in range"),
+            data_out: sim
+                .read_bool_or_int(sim.io().data_out)
+                .to_bigint()
+                .try_into()
+                .expect("known to be in range"),
+        };
+        assert_eq!(
+            expected,
+            io,
+            "cycle: {cycle}\nvcd:\n{}",
+            String::from_utf8(writer.take()).unwrap(),
+        );
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(SimDuration::from_micros(1));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/enums.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/enums.txt") {
+        panic!();
+    }
+}
+
 // TODO: add tests for memories
diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt
new file mode 100644
index 0000000..e69de29
diff --git a/crates/fayalite/tests/sim/expected/enums.vcd b/crates/fayalite/tests/sim/expected/enums.vcd
new file mode 100644
index 0000000..e69de29

From 564ccb30bcd995e8c85cf4bc06ec92aa73603c87 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 10 Dec 2024 23:39:17 -0800
Subject: [PATCH 128/190] sim/vcd: fix variable identifiers to follow verilog
 rules

---
 crates/fayalite/src/sim/vcd.rs | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs
index 8b5a58c..0779b5c 100644
--- a/crates/fayalite/src/sim/vcd.rs
+++ b/crates/fayalite/src/sim/vcd.rs
@@ -235,6 +235,17 @@ fn write_escaped<W: io::Write>(writer: &mut W, value: impl Display) -> io::Resul
     write!(Wrapper(writer), "{value}")
 }
 
+fn is_unescaped_verilog_identifier(ident: &str) -> bool {
+    // we only allow ascii, so we can just check bytes
+    let Some((&first, rest)) = ident.as_bytes().split_first() else {
+        return false; // empty string is not an identifier
+    };
+    (first.is_ascii_alphabetic() || first == b'_')
+        && rest
+            .iter()
+            .all(|&ch| ch.is_ascii_alphanumeric() || ch == b'_' || ch == b'$')
+}
+
 fn write_vcd_var<W: io::Write>(
     writer: &mut W,
     var_type: &str,
@@ -244,7 +255,12 @@ fn write_vcd_var<W: io::Write>(
 ) -> io::Result<()> {
     write!(writer, "$var {var_type} {size} ")?;
     write_scalar_id(writer, id)?;
-    writeln!(writer, " {name} $end")
+    writer.write_all(b" ")?;
+    if !is_unescaped_verilog_identifier(name) {
+        writer.write_all(b"\\")?;
+    }
+    write_escaped(writer, name)?;
+    writer.write_all(b" $end\n")
 }
 
 impl WriteTrace for TraceUInt {

From 6b31e6d515e6e30c44d56bd5432a3e3e50042f39 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 10 Dec 2024 23:40:33 -0800
Subject: [PATCH 129/190] sim: add .dot output for Assignments graph for
 debugging

---
 crates/fayalite/src/sim.rs             | 382 ++++++++++++++++++++++---
 crates/fayalite/src/sim/interpreter.rs |   3 +
 2 files changed, 342 insertions(+), 43 deletions(-)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index d2906e1..5d37baf 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -42,8 +42,12 @@ use bitvec::{bits, order::Lsb0, slice::BitSlice, vec::BitVec, view::BitView};
 use hashbrown::{HashMap, HashSet};
 use num_bigint::BigInt;
 use num_traits::{Signed, ToPrimitive, Zero};
-use petgraph::visit::{
-    GraphBase, IntoNeighbors, IntoNeighborsDirected, IntoNodeIdentifiers, VisitMap, Visitable,
+use petgraph::{
+    data::FromElements,
+    visit::{
+        EdgeRef, GraphBase, IntoEdgeReferences, IntoNeighbors, IntoNeighborsDirected,
+        IntoNodeIdentifiers, IntoNodeReferences, NodeRef, VisitMap, Visitable,
+    },
 };
 use std::{borrow::Cow, collections::BTreeSet, fmt, marker::PhantomData, mem, ops::IndexMut};
 
@@ -384,8 +388,8 @@ impl CompiledExpr<Array> {
 #[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
 enum AssignmentOrSlotIndex {
     AssignmentIndex(usize),
-    SmallSlots(StatePartIndex<StatePartKindSmallSlots>),
-    BigSlots(StatePartIndex<StatePartKindBigSlots>),
+    SmallSlot(StatePartIndex<StatePartKindSmallSlots>),
+    BigSlot(StatePartIndex<StatePartKindBigSlots>),
 }
 
 #[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
@@ -408,6 +412,15 @@ enum AssignmentIO {
     },
 }
 
+#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
+enum AssignmentsEdge {
+    IO(AssignmentIO),
+    AssignmentImmediatePredecessor {
+        predecessor_assignment_index: usize,
+        assignment_index: usize,
+    },
+}
+
 #[derive(Debug)]
 enum Assignments {
     Accumulating {
@@ -415,6 +428,7 @@ enum Assignments {
     },
     Finalized {
         assignments: Box<[Assignment]>,
+        slots_layout: TypeLayout<InsnsBuildingDone>,
         slot_readers: SlotToAssignmentIndexFullMap,
         slot_writers: SlotToAssignmentIndexFullMap,
         assignment_immediate_predecessors: Box<[Box<[usize]>]>,
@@ -431,13 +445,13 @@ impl Default for Assignments {
 }
 
 impl Assignments {
-    fn finalize(&mut self, slots_len: TypeLen) {
+    fn finalize(&mut self, slots_layout: TypeLayout<InsnsBuildingDone>) {
         let Self::Accumulating { assignments } = self else {
             unreachable!("already finalized");
         };
         let assignments = mem::take(assignments).into_boxed_slice();
-        let mut slot_readers = SlotToAssignmentIndexFullMap::new(slots_len);
-        let mut slot_writers = SlotToAssignmentIndexFullMap::new(slots_len);
+        let mut slot_readers = SlotToAssignmentIndexFullMap::new(slots_layout.len());
+        let mut slot_writers = SlotToAssignmentIndexFullMap::new(slots_layout.len());
         let mut assignment_immediate_predecessors = vec![BTreeSet::new(); assignments.len()];
         let mut assignment_immediate_successors = vec![BTreeSet::new(); assignments.len()];
         for (assignment_index, assignment) in assignments.iter().enumerate() {
@@ -465,6 +479,7 @@ impl Assignments {
         }
         *self = Self::Finalized {
             assignments,
+            slots_layout,
             slot_readers,
             slot_writers,
             assignment_immediate_predecessors: assignment_immediate_predecessors
@@ -489,6 +504,12 @@ impl Assignments {
         };
         assignments
     }
+    fn slots_layout(&self) -> TypeLayout<InsnsBuildingDone> {
+        let Self::Finalized { slots_layout, .. } = self else {
+            unreachable!("Assignments::finalize should have been called");
+        };
+        *slots_layout
+    }
     fn slot_readers(&self) -> &SlotToAssignmentIndexFullMap {
         let Self::Finalized { slot_readers, .. } = self else {
             unreachable!("Assignments::finalize should have been called");
@@ -521,46 +542,131 @@ impl Assignments {
         };
         assignment_immediate_successors
     }
+    fn elements(&self) -> AssignmentsElements<'_> {
+        let SlotToAssignmentIndexFullMap(TypeParts {
+            small_slots,
+            big_slots,
+        }) = self.slot_readers();
+        AssignmentsElements {
+            node_indexes: HashMap::with_capacity(
+                self.assignments().len() + small_slots.len() + big_slots.len(),
+            ),
+            nodes: self.node_references(),
+            edges: self.edge_references(),
+        }
+    }
 }
 
 impl GraphBase for Assignments {
-    type EdgeId = AssignmentIO;
+    type EdgeId = AssignmentsEdge;
     type NodeId = AssignmentOrSlotIndex;
 }
 
+#[derive(Debug, Clone, Copy)]
+enum AssignmentsNodeRef<'a> {
+    Assignment {
+        index: usize,
+        assignment: &'a Assignment,
+    },
+    SmallSlot(StatePartIndex<StatePartKindSmallSlots>, SlotDebugData),
+    BigSlot(StatePartIndex<StatePartKindBigSlots>, SlotDebugData),
+}
+
+impl<'a> NodeRef for AssignmentsNodeRef<'a> {
+    type NodeId = AssignmentOrSlotIndex;
+    type Weight = AssignmentsNodeRef<'a>;
+
+    fn id(&self) -> Self::NodeId {
+        match *self {
+            AssignmentsNodeRef::Assignment {
+                index,
+                assignment: _,
+            } => AssignmentOrSlotIndex::AssignmentIndex(index),
+            AssignmentsNodeRef::SmallSlot(slot, _) => AssignmentOrSlotIndex::SmallSlot(slot),
+            AssignmentsNodeRef::BigSlot(slot, _) => AssignmentOrSlotIndex::BigSlot(slot),
+        }
+    }
+
+    fn weight(&self) -> &Self::Weight {
+        self
+    }
+}
+
+impl<'a> petgraph::visit::Data for &'a Assignments {
+    type NodeWeight = AssignmentsNodeRef<'a>;
+    type EdgeWeight = AssignmentsEdge;
+}
+
+struct AssignmentsElements<'a> {
+    node_indexes: HashMap<AssignmentOrSlotIndex, usize>,
+    nodes: AssignmentsNodes<'a>,
+    edges: AssignmentsEdges<'a>,
+}
+
+impl<'a> Iterator for AssignmentsElements<'a> {
+    type Item = petgraph::data::Element<
+        <&'a Assignments as petgraph::visit::Data>::NodeWeight,
+        <&'a Assignments as petgraph::visit::Data>::EdgeWeight,
+    >;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        let Self {
+            node_indexes,
+            nodes,
+            edges,
+        } = self;
+        if let Some(node) = nodes.next() {
+            node_indexes.insert(node.id(), node_indexes.len());
+            return Some(petgraph::data::Element::Node { weight: node });
+        }
+        let edge = edges.next()?;
+        Some(petgraph::data::Element::Edge {
+            source: node_indexes[&edge.source()],
+            target: node_indexes[&edge.target()],
+            weight: *edge.weight(),
+        })
+    }
+}
+
+#[derive(Clone)]
 struct AssignmentsNodeIdentifiers {
     assignment_indexes: std::ops::Range<usize>,
     small_slots: std::ops::Range<u32>,
     big_slots: std::ops::Range<u32>,
 }
 
-impl Iterator for AssignmentsNodeIdentifiers {
-    type Item = AssignmentOrSlotIndex;
-    fn next(&mut self) -> Option<Self::Item> {
+impl AssignmentsNodeIdentifiers {
+    fn internal_iter<'a>(&'a mut self) -> impl Iterator<Item = AssignmentOrSlotIndex> + 'a {
         let Self {
             assignment_indexes,
             small_slots,
             big_slots,
         } = self;
         assignment_indexes
-            .next()
             .map(AssignmentOrSlotIndex::AssignmentIndex)
-            .or_else(|| {
-                small_slots.next().map(|value| {
-                    AssignmentOrSlotIndex::SmallSlots(StatePartIndex {
-                        value,
-                        _phantom: PhantomData,
-                    })
+            .chain(small_slots.map(|value| {
+                AssignmentOrSlotIndex::SmallSlot(StatePartIndex {
+                    value,
+                    _phantom: PhantomData,
                 })
-            })
-            .or_else(|| {
-                big_slots.next().map(|value| {
-                    AssignmentOrSlotIndex::BigSlots(StatePartIndex {
-                        value,
-                        _phantom: PhantomData,
-                    })
+            }))
+            .chain(big_slots.map(|value| {
+                AssignmentOrSlotIndex::BigSlot(StatePartIndex {
+                    value,
+                    _phantom: PhantomData,
                 })
-            })
+            }))
+    }
+}
+
+impl Iterator for AssignmentsNodeIdentifiers {
+    type Item = AssignmentOrSlotIndex;
+    fn next(&mut self) -> Option<Self::Item> {
+        self.internal_iter().next()
+    }
+
+    fn nth(&mut self, n: usize) -> Option<Self::Item> {
+        self.internal_iter().nth(n)
     }
 }
 
@@ -580,6 +686,44 @@ impl<'a> IntoNodeIdentifiers for &'a Assignments {
     }
 }
 
+struct AssignmentsNodes<'a> {
+    assignments: &'a Assignments,
+    nodes: AssignmentsNodeIdentifiers,
+}
+
+impl<'a> Iterator for AssignmentsNodes<'a> {
+    type Item = AssignmentsNodeRef<'a>;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        self.nodes.next().map(|node| match node {
+            AssignmentOrSlotIndex::AssignmentIndex(index) => AssignmentsNodeRef::Assignment {
+                index,
+                assignment: &self.assignments.assignments()[index],
+            },
+            AssignmentOrSlotIndex::SmallSlot(slot) => AssignmentsNodeRef::SmallSlot(
+                slot,
+                *self.assignments.slots_layout().small_slots.debug_data(slot),
+            ),
+            AssignmentOrSlotIndex::BigSlot(slot) => AssignmentsNodeRef::BigSlot(
+                slot,
+                *self.assignments.slots_layout().big_slots.debug_data(slot),
+            ),
+        })
+    }
+}
+
+impl<'a> IntoNodeReferences for &'a Assignments {
+    type NodeRef = AssignmentsNodeRef<'a>;
+    type NodeReferences = AssignmentsNodes<'a>;
+
+    fn node_references(self) -> Self::NodeReferences {
+        AssignmentsNodes {
+            assignments: self,
+            nodes: self.node_identifiers(),
+        }
+    }
+}
+
 struct AssignmentsNeighborsDirected<'a> {
     assignment_indexes: std::slice::Iter<'a, usize>,
     small_slots: std::collections::btree_set::Iter<'a, StatePartIndex<StatePartKindSmallSlots>>,
@@ -603,13 +747,13 @@ impl Iterator for AssignmentsNeighborsDirected<'_> {
         } else if let retval @ Some(_) = small_slots
             .next()
             .copied()
-            .map(AssignmentOrSlotIndex::SmallSlots)
+            .map(AssignmentOrSlotIndex::SmallSlot)
         {
             retval
         } else if let retval @ Some(_) = big_slots
             .next()
             .copied()
-            .map(AssignmentOrSlotIndex::BigSlots)
+            .map(AssignmentOrSlotIndex::BigSlot)
         {
             retval
         } else {
@@ -664,12 +808,12 @@ impl<'a> IntoNeighborsDirected for &'a Assignments {
                     big_slots: big_slots.iter(),
                 }
             }
-            AssignmentOrSlotIndex::SmallSlots(slot) => AssignmentsNeighborsDirected {
+            AssignmentOrSlotIndex::SmallSlot(slot) => AssignmentsNeighborsDirected {
                 assignment_indexes: slot_map[slot].iter(),
                 small_slots: Default::default(),
                 big_slots: Default::default(),
             },
-            AssignmentOrSlotIndex::BigSlots(slot) => AssignmentsNeighborsDirected {
+            AssignmentOrSlotIndex::BigSlot(slot) => AssignmentsNeighborsDirected {
                 assignment_indexes: slot_map[slot].iter(),
                 small_slots: Default::default(),
                 big_slots: Default::default(),
@@ -678,6 +822,149 @@ impl<'a> IntoNeighborsDirected for &'a Assignments {
     }
 }
 
+impl EdgeRef for AssignmentsEdge {
+    type NodeId = AssignmentOrSlotIndex;
+    type EdgeId = AssignmentsEdge;
+    type Weight = AssignmentsEdge;
+
+    fn source(&self) -> Self::NodeId {
+        match *self {
+            AssignmentsEdge::IO(AssignmentIO::BigInput {
+                assignment_index: _,
+                slot,
+            }) => AssignmentOrSlotIndex::BigSlot(slot),
+            AssignmentsEdge::IO(AssignmentIO::SmallInput {
+                assignment_index: _,
+                slot,
+            }) => AssignmentOrSlotIndex::SmallSlot(slot),
+            AssignmentsEdge::IO(AssignmentIO::BigOutput {
+                assignment_index,
+                slot: _,
+            }) => AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+            AssignmentsEdge::IO(AssignmentIO::SmallOutput {
+                assignment_index,
+                slot: _,
+            }) => AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+            AssignmentsEdge::AssignmentImmediatePredecessor {
+                predecessor_assignment_index,
+                assignment_index: _,
+            } => AssignmentOrSlotIndex::AssignmentIndex(predecessor_assignment_index),
+        }
+    }
+
+    fn target(&self) -> Self::NodeId {
+        match *self {
+            AssignmentsEdge::IO(AssignmentIO::BigInput {
+                assignment_index,
+                slot: _,
+            }) => AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+            AssignmentsEdge::IO(AssignmentIO::SmallInput {
+                assignment_index,
+                slot: _,
+            }) => AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+            AssignmentsEdge::IO(AssignmentIO::BigOutput {
+                assignment_index: _,
+                slot,
+            }) => AssignmentOrSlotIndex::BigSlot(slot),
+            AssignmentsEdge::IO(AssignmentIO::SmallOutput {
+                assignment_index: _,
+                slot,
+            }) => AssignmentOrSlotIndex::SmallSlot(slot),
+            AssignmentsEdge::AssignmentImmediatePredecessor {
+                predecessor_assignment_index: _,
+                assignment_index,
+            } => AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+        }
+    }
+
+    fn weight(&self) -> &Self::Weight {
+        self
+    }
+
+    fn id(&self) -> Self::EdgeId {
+        *self
+    }
+}
+
+struct AssignmentsEdges<'a> {
+    assignments: &'a Assignments,
+    nodes: AssignmentsNodeIdentifiers,
+    outgoing_neighbors: Option<(AssignmentOrSlotIndex, AssignmentsNeighborsDirected<'a>)>,
+}
+
+impl Iterator for AssignmentsEdges<'_> {
+    type Item = AssignmentsEdge;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        loop {
+            if let Some((node, outgoing_neighbors)) = &mut self.outgoing_neighbors {
+                if let Some(outgoing_neighbor) = outgoing_neighbors.next() {
+                    return Some(match (*node, outgoing_neighbor) {
+                        (
+                            AssignmentOrSlotIndex::SmallSlot(_) | AssignmentOrSlotIndex::BigSlot(_),
+                            AssignmentOrSlotIndex::SmallSlot(_) | AssignmentOrSlotIndex::BigSlot(_),
+                        ) => unreachable!(),
+                        (
+                            AssignmentOrSlotIndex::AssignmentIndex(predecessor_assignment_index),
+                            AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+                        ) => AssignmentsEdge::AssignmentImmediatePredecessor {
+                            predecessor_assignment_index,
+                            assignment_index,
+                        },
+                        (
+                            AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+                            AssignmentOrSlotIndex::SmallSlot(slot),
+                        ) => AssignmentsEdge::IO(AssignmentIO::SmallOutput {
+                            assignment_index,
+                            slot,
+                        }),
+                        (
+                            AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+                            AssignmentOrSlotIndex::BigSlot(slot),
+                        ) => AssignmentsEdge::IO(AssignmentIO::BigOutput {
+                            assignment_index,
+                            slot,
+                        }),
+                        (
+                            AssignmentOrSlotIndex::SmallSlot(slot),
+                            AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+                        ) => AssignmentsEdge::IO(AssignmentIO::SmallInput {
+                            assignment_index,
+                            slot,
+                        }),
+                        (
+                            AssignmentOrSlotIndex::BigSlot(slot),
+                            AssignmentOrSlotIndex::AssignmentIndex(assignment_index),
+                        ) => AssignmentsEdge::IO(AssignmentIO::BigInput {
+                            assignment_index,
+                            slot,
+                        }),
+                    });
+                }
+            }
+            let node = self.nodes.next()?;
+            self.outgoing_neighbors = Some((
+                node,
+                self.assignments
+                    .neighbors_directed(node, petgraph::Direction::Outgoing),
+            ));
+        }
+    }
+}
+
+impl<'a> IntoEdgeReferences for &'a Assignments {
+    type EdgeRef = AssignmentsEdge;
+    type EdgeReferences = AssignmentsEdges<'a>;
+
+    fn edge_references(self) -> Self::EdgeReferences {
+        AssignmentsEdges {
+            assignments: self,
+            nodes: self.node_identifiers(),
+            outgoing_neighbors: None,
+        }
+    }
+}
+
 struct AssignmentsVisitMap {
     assignments: Vec<bool>,
     slots: DenseSlotSet,
@@ -689,8 +976,8 @@ impl VisitMap<AssignmentOrSlotIndex> for AssignmentsVisitMap {
             AssignmentOrSlotIndex::AssignmentIndex(assignment_index) => {
                 !mem::replace(&mut self.assignments[assignment_index], true)
             }
-            AssignmentOrSlotIndex::SmallSlots(slot) => self.slots.insert(slot),
-            AssignmentOrSlotIndex::BigSlots(slot) => self.slots.insert(slot),
+            AssignmentOrSlotIndex::SmallSlot(slot) => self.slots.insert(slot),
+            AssignmentOrSlotIndex::BigSlot(slot) => self.slots.insert(slot),
         }
     }
 
@@ -699,8 +986,8 @@ impl VisitMap<AssignmentOrSlotIndex> for AssignmentsVisitMap {
             AssignmentOrSlotIndex::AssignmentIndex(assignment_index) => {
                 self.assignments[assignment_index]
             }
-            AssignmentOrSlotIndex::SmallSlots(slot) => self.slots.contains(slot),
-            AssignmentOrSlotIndex::BigSlots(slot) => self.slots.contains(slot),
+            AssignmentOrSlotIndex::SmallSlot(slot) => self.slots.contains(slot),
+            AssignmentOrSlotIndex::BigSlot(slot) => self.slots.contains(slot),
         }
     }
 }
@@ -2725,12 +3012,15 @@ impl Compiler {
                 .compile_expr(instantiated_module, Expr::canonical(expr.base()))
                 .map_ty(Bundle::from_canonical)
                 .field_by_index(expr.field_index()),
-            ExprEnum::VariantAccess(variant_access) => self.compile_expr(
-                instantiated_module,
-                variant_access.base().cast_to_bits()
-                    [Expr::ty(variant_access.base()).discriminant_bit_width()..]
-                    .cast_bits_to(Expr::ty(expr)),
-            ),
+            ExprEnum::VariantAccess(variant_access) => {
+                let start = Expr::ty(variant_access.base()).discriminant_bit_width();
+                let len = Expr::ty(expr).bit_width();
+                self.compile_expr(
+                    instantiated_module,
+                    variant_access.base().cast_to_bits()[start..start + len]
+                        .cast_bits_to(Expr::ty(expr)),
+                )
+            }
             ExprEnum::ArrayIndex(expr) => self
                 .compile_expr(instantiated_module, Expr::canonical(expr.base()))
                 .map_ty(Array::from_canonical)
@@ -4146,7 +4436,13 @@ impl Compiler {
     }
     fn process_assignments(&mut self) {
         self.assignments
-            .finalize(self.insns.state_layout().len().ty);
+            .finalize(self.insns.state_layout().ty.clone().into());
+        println!(
+            "{:#?}",
+            petgraph::dot::Dot::new(&petgraph::graph::DiGraph::<_, _, usize>::from_elements(
+                self.assignments.elements()
+            ))
+        );
         let assignments_order: Vec<_> = match petgraph::algo::toposort(&self.assignments, None) {
             Ok(nodes) => nodes
                 .into_iter()
@@ -4160,11 +4456,11 @@ impl Compiler {
                     "combinatorial logic cycle detected at: {}",
                     self.assignments.assignments()[assignment_index].source_location,
                 ),
-                AssignmentOrSlotIndex::SmallSlots(slot) => panic!(
+                AssignmentOrSlotIndex::SmallSlot(slot) => panic!(
                     "combinatorial logic cycle detected through: {}",
                     self.insns.state_layout().ty.small_slots.debug_data[slot.as_usize()].name,
                 ),
-                AssignmentOrSlotIndex::BigSlots(slot) => panic!(
+                AssignmentOrSlotIndex::BigSlot(slot) => panic!(
                     "combinatorial logic cycle detected through: {}",
                     self.insns.state_layout().ty.big_slots.debug_data[slot.as_usize()].name,
                 ),
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index 23d1275..aabf6e2 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -1652,6 +1652,9 @@ impl<K: StatePartKind, BK: InsnsBuildingKind> StatePartLayout<K, BK> {
             _phantom: PhantomData,
         }
     }
+    pub(crate) fn debug_data(&self, index: StatePartIndex<K>) -> &K::DebugData {
+        &self.debug_data[index.as_usize()]
+    }
 }
 
 impl<K: StatePartKind> From<StatePartLayout<K, InsnsBuilding>>

From 5087f16099b3b0f6e45f0346e6d24da52fafaa60 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 11 Dec 2024 00:00:21 -0800
Subject: [PATCH 130/190] sim: fix assignments graph by properly including
 conditions as assignment inputs

---
 crates/fayalite/src/sim.rs | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 5d37baf..ab5b7b7 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -458,6 +458,9 @@ impl Assignments {
             slot_readers
                 .keys_for_assignment(assignment_index)
                 .extend([&assignment.inputs]);
+            slot_readers
+                .keys_for_assignment(assignment_index)
+                .extend(&assignment.conditions);
             let SlotSet(TypeParts {
                 small_slots,
                 big_slots,
@@ -1400,6 +1403,30 @@ impl<'a> Extend<&'a SlotSet> for SlotToAssignmentIndexFullMapKeysForAssignment<'
     }
 }
 
+impl<'a> Extend<&'a Cond> for SlotToAssignmentIndexFullMapKeysForAssignment<'_> {
+    fn extend<T: IntoIterator<Item = &'a Cond>>(&mut self, iter: T) {
+        iter.into_iter().for_each(|cond| match cond.body {
+            CondBody::IfTrue { cond } | CondBody::IfFalse { cond } => {
+                let CompiledValue {
+                    range:
+                        TypeIndexRange {
+                            small_slots,
+                            big_slots,
+                        },
+                    layout: _,
+                    write: _,
+                } = cond;
+                self.extend(small_slots.iter());
+                self.extend(big_slots.iter());
+            }
+            CondBody::MatchArm {
+                discriminant,
+                variant_index: _,
+            } => self.extend([discriminant]),
+        });
+    }
+}
+
 impl Assignment {
     fn new(
         conditions: Interned<[Cond]>,

From 8616ee47370d24e43b96995cb10246fcae687fdd Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 11 Dec 2024 00:01:04 -0800
Subject: [PATCH 131/190] tests/sim: test_enums works!

---
 crates/fayalite/tests/sim.rs                 |    1 -
 crates/fayalite/tests/sim/expected/enums.txt | 1639 ++++++++++++++++++
 crates/fayalite/tests/sim/expected/enums.vcd |   94 +
 3 files changed, 1733 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index db20df2..a8b23f2 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -363,7 +363,6 @@ pub fn enums() {
     }
 }
 
-#[cfg(todo)] // FIXME: enum lowering currently broken
 #[hdl]
 #[test]
 fn test_enums() {
diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt
index e69de29..69c94dd 100644
--- a/crates/fayalite/tests/sim/expected/enums.txt
+++ b/crates/fayalite/tests/sim/expected/enums.txt
@@ -0,0 +1,1639 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 5,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    A,
+                                    B,
+                                    C,
+                                },
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 82,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::cd.rst",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::which_in",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::data_in",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::which_out",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::data_out",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::the_reg",
+                                ty: Enum {
+                                    A,
+                                    B(Bundle {0: UInt<1>, 1: Bool}),
+                                    C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::the_reg$next",
+                                ty: Enum {
+                                    A,
+                                    B(Bundle {0: UInt<1>, 1: Bool}),
+                                    C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    A,
+                                    B(Bundle {0: UInt<1>, 1: Bool}),
+                                    C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".a[0]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".a[1]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".b",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: ".1.0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1.1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    A,
+                                    B(Bundle {0: UInt<1>, 1: Bool}),
+                                    C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: ".1.a[0]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1.a[1]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1.b",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: ".a[0]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".a[1]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".b",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: SInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    A,
+                                    B(Bundle {0: UInt<1>, 1: Bool}),
+                                    C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartAllocationLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(72), // SlotDebugData { name: "", ty: UInt<4> },
+                    value: 0,
+                },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(61), // SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
+                    start: 2,
+                    len: 2,
+                },
+                CastToSInt {
+                    dest: StatePartIndex<BigSlots>(62), // SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(61), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest_width: 2,
+                },
+                Const {
+                    dest: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
+                    value: 2,
+                },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(41), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
+                    start: 1,
+                    len: 1,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(41), // SlotDebugData { name: "", ty: UInt<1> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(60), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
+                },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(38), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
+                    start: 0,
+                    len: 1,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(39), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(38), // SlotDebugData { name: "", ty: UInt<1> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(39), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(36), // SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(37), // SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(58), // SlotDebugData { name: "[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(59), // SlotDebugData { name: "[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(60), // SlotDebugData { name: "", ty: UInt<1> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(55), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(58), // SlotDebugData { name: "[0]", ty: UInt<1> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(56), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(59), // SlotDebugData { name: "[1]", ty: UInt<1> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(57), // SlotDebugData { name: ".b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(62), // SlotDebugData { name: "", ty: SInt<2> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(50), // SlotDebugData { name: ".0", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(51), // SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(55), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(52), // SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(56), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(53), // SlotDebugData { name: ".1.b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(57), // SlotDebugData { name: ".b", ty: SInt<2> },
+                },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(63), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(52), // SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
+                    rhs: 1,
+                },
+                Or {
+                    dest: StatePartIndex<BigSlots>(64), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(51), // SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(63), // SlotDebugData { name: "", ty: UInt<2> },
+                },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(65), // SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(53), // SlotDebugData { name: ".1.b", ty: SInt<2> },
+                    dest_width: 2,
+                },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(66), // SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(65), // SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: 2,
+                },
+                Or {
+                    dest: StatePartIndex<BigSlots>(67), // SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(64), // SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(66), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(68), // SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(67), // SlotDebugData { name: "", ty: UInt<4> },
+                    rhs: 2,
+                },
+                Or {
+                    dest: StatePartIndex<BigSlots>(69), // SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(50), // SlotDebugData { name: ".0", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(68), // SlotDebugData { name: "", ty: UInt<6> },
+                },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(70), // SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(69), // SlotDebugData { name: "", ty: UInt<6> },
+                    dest_width: 6,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(71), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(70), // SlotDebugData { name: "", ty: UInt<6> },
+                },
+                Const {
+                    dest: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
+                    value: 1,
+                },
+                CmpEq {
+                    dest: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(33), // SlotDebugData { name: ".0", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(34), // SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(36), // SlotDebugData { name: ".0", ty: UInt<1> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(35), // SlotDebugData { name: ".1.1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(37), // SlotDebugData { name: ".1", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(43), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(35), // SlotDebugData { name: ".1.1", ty: Bool },
+                },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(44), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(43), // SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 1,
+                },
+                Or {
+                    dest: StatePartIndex<BigSlots>(45), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(34), // SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(44), // SlotDebugData { name: "", ty: UInt<2> },
+                },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(46), // SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(45), // SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: 2,
+                },
+                Or {
+                    dest: StatePartIndex<BigSlots>(47), // SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(33), // SlotDebugData { name: ".0", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(46), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(48), // SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(47), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest_width: 6,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(49), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(48), // SlotDebugData { name: "", ty: UInt<6> },
+                },
+                Const {
+                    dest: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
+                    value: 0,
+                },
+                CmpEq {
+                    dest: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
+                    start: 2,
+                    len: 2,
+                },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
+                    start: 0,
+                    len: 1,
+                },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
+                    start: 1,
+                    len: 1,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(17), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<1> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: UInt<1> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(17), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(73), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: ".1", ty: Bool },
+                },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(74), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(73), // SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 1,
+                },
+                Or {
+                    dest: StatePartIndex<BigSlots>(75), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(11), // SlotDebugData { name: ".0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(74), // SlotDebugData { name: "", ty: UInt<2> },
+                },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(76), // SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(75), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest_width: 4,
+                },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
+                    start: 2,
+                    len: 4,
+                },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
+                    start: 0,
+                    len: 2,
+                },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(25), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
+                    start: 0,
+                    len: 1,
+                },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(26), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
+                    start: 1,
+                    len: 1,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(21), // SlotDebugData { name: "[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(25), // SlotDebugData { name: "", ty: UInt<1> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(22), // SlotDebugData { name: "[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(26), // SlotDebugData { name: "", ty: UInt<1> },
+                },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(27), // SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
+                    start: 2,
+                    len: 2,
+                },
+                CastToSInt {
+                    dest: StatePartIndex<BigSlots>(28), // SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(27), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest_width: 2,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(18), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(21), // SlotDebugData { name: "[0]", ty: UInt<1> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(19), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(22), // SlotDebugData { name: "[1]", ty: UInt<1> },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(20), // SlotDebugData { name: ".b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(28), // SlotDebugData { name: "", ty: SInt<2> },
+                },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(77), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(19), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    rhs: 1,
+                },
+                Or {
+                    dest: StatePartIndex<BigSlots>(78), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(18), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(77), // SlotDebugData { name: "", ty: UInt<2> },
+                },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(79), // SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(20), // SlotDebugData { name: ".b", ty: SInt<2> },
+                    dest_width: 2,
+                },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(80), // SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(79), // SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: 2,
+                },
+                Or {
+                    dest: StatePartIndex<BigSlots>(81), // SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(78), // SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(80), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    lhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    rhs: 3,
+                },
+                // at: module-XXXXXXXXXX.rs:15:1
+                BranchIfSmallNeImmediate {
+                    target: 75,
+                    lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 0,
+                },
+                // at: module-XXXXXXXXXX.rs:16:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:17:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(72), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:15:1
+                BranchIfSmallNeImmediate {
+                    target: 78,
+                    lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 1,
+                },
+                // at: module-XXXXXXXXXX.rs:18:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:19:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(76), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:15:1
+                BranchIfSmallNeImmediate {
+                    target: 81,
+                    lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 2,
+                },
+                // at: module-XXXXXXXXXX.rs:20:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:21:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(81), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Const {
+                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<6> },
+                    value: 0,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<6> },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                BranchIfZero {
+                    target: 92,
+                    value: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                BranchIfZero {
+                    target: 87,
+                    value: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                BranchIfNonZero {
+                    target: 92,
+                    value: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:12:1
+                BranchIfZero {
+                    target: 90,
+                    value: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:13:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(49), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                // at: module-XXXXXXXXXX.rs:12:1
+                BranchIfNonZero {
+                    target: 92,
+                    value: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:14:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(71), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock },
+                },
+                AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallZero {
+                    target: 99,
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallNonZero {
+                    target: 98,
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                Branch {
+                    target: 99,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                NotSmall {
+                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Return,
+            ],
+            ..
+        },
+        pc: 100,
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [
+                18446744073709551614,
+                0,
+                1,
+                0,
+                2,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                0,
+                1,
+                2,
+                15,
+                2,
+                15,
+                62,
+                62,
+                0,
+                0,
+                1,
+                1,
+                62,
+                3,
+                1,
+                1,
+                1,
+                1,
+                1,
+                -1,
+                1,
+                1,
+                15,
+                3,
+                1,
+                1,
+                3,
+                -1,
+                0,
+                0,
+                1,
+                0,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                1,
+                2,
+                3,
+                12,
+                13,
+                13,
+                13,
+                2,
+                1,
+                1,
+                -1,
+                2,
+                1,
+                1,
+                -1,
+                1,
+                1,
+                1,
+                3,
+                -1,
+                2,
+                3,
+                3,
+                12,
+                15,
+                60,
+                62,
+                62,
+                62,
+                0,
+                1,
+                2,
+                3,
+                3,
+                2,
+                3,
+                3,
+                12,
+                15,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::enums,
+        instantiated: Module {
+            name: enums,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::enums,
+            instantiated: Module {
+                name: enums,
+                ..
+            },
+        }.cd: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: SyncReset,
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::cd.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::cd.rst",
+                                ty: SyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Clock,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Clock,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: SyncReset,
+                                layout: TypeLayout {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: SyncReset,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::enums,
+            instantiated: Module {
+                name: enums,
+                ..
+            },
+        }.cd.clk: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::enums,
+            instantiated: Module {
+                name: enums,
+                ..
+            },
+        }.cd.rst: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: SyncReset,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: SyncReset,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::enums,
+            instantiated: Module {
+                name: enums,
+                ..
+            },
+        }.data_in: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<4>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::data_in",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::enums,
+            instantiated: Module {
+                name: enums,
+                ..
+            },
+        }.data_out: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<4>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::data_out",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 6, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::enums,
+            instantiated: Module {
+                name: enums,
+                ..
+            },
+        }.en: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::en",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::enums,
+            instantiated: Module {
+                name: enums,
+                ..
+            },
+        }.which_in: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<2>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::which_in",
+                                ty: UInt<2>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::enums,
+            instantiated: Module {
+                name: enums,
+                ..
+            },
+        }.which_out: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<2>,
+                layout: TypeLayout {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::which_out",
+                                ty: UInt<2>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "enums",
+        children: [
+            TraceModuleIO {
+                name: "cd",
+                child: TraceBundle {
+                    name: "cd",
+                    fields: [
+                        TraceClock {
+                            id: TraceScalarId(0),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceSyncReset {
+                            id: TraceScalarId(1),
+                            name: "rst",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        rst: SyncReset,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    rst: SyncReset,
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "en",
+                child: TraceBool {
+                    id: TraceScalarId(2),
+                    name: "en",
+                    flow: Source,
+                },
+                ty: Bool,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "which_in",
+                child: TraceUInt {
+                    id: TraceScalarId(3),
+                    name: "which_in",
+                    ty: UInt<2>,
+                    flow: Source,
+                },
+                ty: UInt<2>,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "data_in",
+                child: TraceUInt {
+                    id: TraceScalarId(4),
+                    name: "data_in",
+                    ty: UInt<4>,
+                    flow: Source,
+                },
+                ty: UInt<4>,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "which_out",
+                child: TraceUInt {
+                    id: TraceScalarId(5),
+                    name: "which_out",
+                    ty: UInt<2>,
+                    flow: Sink,
+                },
+                ty: UInt<2>,
+                flow: Sink,
+            },
+            TraceModuleIO {
+                name: "data_out",
+                child: TraceUInt {
+                    id: TraceScalarId(6),
+                    name: "data_out",
+                    ty: UInt<4>,
+                    flow: Sink,
+                },
+                ty: UInt<4>,
+                flow: Sink,
+            },
+            TraceReg {
+                name: "the_reg",
+                child: TraceEnumWithFields {
+                    name: "the_reg",
+                    discriminant: TraceEnumDiscriminant {
+                        id: TraceScalarId(7),
+                        name: "$tag",
+                        ty: Enum {
+                            A,
+                            B(Bundle {0: UInt<1>, 1: Bool}),
+                            C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                        },
+                        flow: Duplex,
+                    },
+                    non_empty_fields: [
+                        TraceBundle {
+                            name: "B",
+                            fields: [
+                                TraceUInt {
+                                    id: TraceScalarId(8),
+                                    name: "0",
+                                    ty: UInt<1>,
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    id: TraceScalarId(9),
+                                    name: "1",
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                0: UInt<1>,
+                                /* offset = 1 */
+                                1: Bool,
+                            },
+                            flow: Source,
+                        },
+                        TraceBundle {
+                            name: "C",
+                            fields: [
+                                TraceArray {
+                                    name: "a",
+                                    elements: [
+                                        TraceUInt {
+                                            id: TraceScalarId(10),
+                                            name: "[0]",
+                                            ty: UInt<1>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            id: TraceScalarId(11),
+                                            name: "[1]",
+                                            ty: UInt<1>,
+                                            flow: Source,
+                                        },
+                                    ],
+                                    ty: Array<UInt<1>, 2>,
+                                    flow: Source,
+                                },
+                                TraceSInt {
+                                    id: TraceScalarId(12),
+                                    name: "b",
+                                    ty: SInt<2>,
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                a: Array<UInt<1>, 2>,
+                                /* offset = 2 */
+                                b: SInt<2>,
+                            },
+                            flow: Source,
+                        },
+                    ],
+                    ty: Enum {
+                        A,
+                        B(Bundle {0: UInt<1>, 1: Bool}),
+                        C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                    },
+                    flow: Duplex,
+                },
+                ty: Enum {
+                    A,
+                    B(Bundle {0: UInt<1>, 1: Bool}),
+                    C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                },
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigSyncReset {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(4),
+                ty: UInt<4>,
+            },
+            state: 0xf,
+            last_state: 0xf,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(5),
+                ty: UInt<2>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(6),
+                ty: UInt<4>,
+            },
+            state: 0xf,
+            last_state: 0xf,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: EnumDiscriminant {
+                index: StatePartIndex<SmallSlots>(4),
+                ty: Enum {
+                    A,
+                    B(Bundle {0: UInt<1>, 1: Bool}),
+                    C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                },
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(11),
+                ty: UInt<1>,
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(12),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(18),
+                ty: UInt<1>,
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(19),
+                ty: UInt<1>,
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(12),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(20),
+                ty: SInt<2>,
+            },
+            state: 0x3,
+            last_state: 0x3,
+        },
+    ],
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 16 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+    ],
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/enums.vcd b/crates/fayalite/tests/sim/expected/enums.vcd
index e69de29..48a493b 100644
--- a/crates/fayalite/tests/sim/expected/enums.vcd
+++ b/crates/fayalite/tests/sim/expected/enums.vcd
@@ -0,0 +1,94 @@
+$timescale 1 ps $end
+$scope module enums $end
+$scope struct cd $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$upscope $end
+$var wire 1 # en $end
+$var wire 2 $ which_in $end
+$var wire 4 % data_in $end
+$var wire 2 & which_out $end
+$var wire 4 ' data_out $end
+$scope struct the_reg $end
+$var string 1 ( \$tag $end
+$scope struct B $end
+$var reg 1 ) \0 $end
+$var reg 1 * \1 $end
+$upscope $end
+$scope struct C $end
+$scope struct a $end
+$var reg 1 + \[0] $end
+$var reg 1 , \[1] $end
+$upscope $end
+$var reg 2 - b $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+1"
+0#
+b0 $
+b0 %
+b0 &
+b0 '
+sA\x20(0) (
+0)
+0*
+0+
+0,
+b0 -
+$end
+#1000000
+1!
+#1100000
+0"
+#2000000
+0!
+#3000000
+1!
+#4000000
+1#
+b1 $
+0!
+#5000000
+1!
+b1 &
+sB\x20(1) (
+#6000000
+0#
+b0 $
+0!
+#7000000
+1!
+#8000000
+1#
+b1 $
+b1111 %
+0!
+#9000000
+1!
+b11 '
+1)
+1*
+1+
+1,
+#10000000
+0!
+#11000000
+1!
+#12000000
+b10 $
+0!
+#13000000
+1!
+b10 &
+b1111 '
+sC\x20(2) (
+b11 -
+#14000000
+0!
+#15000000
+1!
+#16000000

From 393f78a14d94402a312bf9965e30aaa6c35857c5 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 11 Dec 2024 23:28:15 -0800
Subject: [PATCH 132/190] sim: add WIP memory test

---
 crates/fayalite/src/sim.rs                    | 717 ++++++++++++++----
 crates/fayalite/src/sim/interpreter.rs        |  19 +
 crates/fayalite/src/sim/vcd.rs                | 508 ++++++++++---
 crates/fayalite/tests/sim.rs                  | 113 ++-
 .../tests/sim/expected/connect_const.txt      |   4 +-
 .../sim/expected/connect_const_reset.txt      |   6 +-
 .../tests/sim/expected/counter_async.txt      |  10 +-
 .../tests/sim/expected/counter_sync.txt       |  10 +-
 crates/fayalite/tests/sim/expected/enums.txt  |  28 +-
 crates/fayalite/tests/sim/expected/mod1.txt   |  26 +-
 .../tests/sim/expected/shift_register.txt     |  18 +-
 11 files changed, 1155 insertions(+), 304 deletions(-)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index ab5b7b7..731f469 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -1567,9 +1567,37 @@ struct MemoryPortWriteInsns<'a> {
 struct Memory {
     mem: Mem,
     memory: StatePartIndex<StatePartKindMemories>,
+    trace: TraceMem,
     ports: Vec<MemoryPort>,
 }
 
+#[derive(Copy, Clone)]
+enum MakeTraceDeclTarget {
+    Expr(Expr<CanonicalType>),
+    Memory {
+        id: TraceMemoryId,
+        depth: usize,
+        stride: usize,
+        start: usize,
+        ty: CanonicalType,
+    },
+}
+
+impl MakeTraceDeclTarget {
+    fn flow(self) -> Flow {
+        match self {
+            MakeTraceDeclTarget::Expr(expr) => Expr::flow(expr),
+            MakeTraceDeclTarget::Memory { .. } => Flow::Duplex,
+        }
+    }
+    fn ty(self) -> CanonicalType {
+        match self {
+            MakeTraceDeclTarget::Expr(expr) => Expr::ty(expr),
+            MakeTraceDeclTarget::Memory { ty, .. } => ty,
+        }
+    }
+}
+
 #[derive(Debug)]
 pub struct Compiler {
     insns: Insns<InsnsBuilding>,
@@ -1589,7 +1617,7 @@ pub struct Compiler {
     compiled_value_to_clock_trigger_map: HashMap<CompiledValue<Clock>, ClockTrigger>,
     enum_discriminants: HashMap<CompiledValue<Enum>, StatePartIndex<StatePartKindSmallSlots>>,
     registers: Vec<Register>,
-    traces: Vec<SimTrace<()>>,
+    traces: SimTraces<Vec<SimTrace<SimTraceKind, ()>>>,
     memories: Vec<Memory>,
 }
 
@@ -1614,14 +1642,13 @@ impl Compiler {
             compiled_value_to_clock_trigger_map: HashMap::new(),
             enum_discriminants: HashMap::new(),
             registers: Vec::new(),
-            traces: Vec::new(),
+            traces: SimTraces(Vec::new()),
             memories: Vec::new(),
         }
     }
     fn new_sim_trace(&mut self, kind: SimTraceKind) -> TraceScalarId {
-        let id = TraceScalarId(self.traces.len());
-        self.traces.push(SimTrace {
-            id,
+        let id = TraceScalarId(self.traces.0.len());
+        self.traces.0.push(SimTrace {
             kind,
             state: (),
             last_state: (),
@@ -1631,30 +1658,47 @@ impl Compiler {
     fn make_trace_scalar_helper(
         &mut self,
         instantiated_module: InstantiatedModule,
-        target: Expr<CanonicalType>,
+        target: MakeTraceDeclTarget,
         source_location: SourceLocation,
         small_kind: impl FnOnce(StatePartIndex<StatePartKindSmallSlots>) -> SimTraceKind,
         big_kind: impl FnOnce(StatePartIndex<StatePartKindBigSlots>) -> SimTraceKind,
-    ) -> TraceScalarId {
-        let compiled_value = self.compile_expr(instantiated_module, target);
-        let compiled_value = self.compiled_expr_to_value(compiled_value, source_location);
-        self.new_sim_trace(match compiled_value.range.len() {
-            TypeLen::A_SMALL_SLOT => small_kind(compiled_value.range.small_slots.start),
-            TypeLen::A_BIG_SLOT => big_kind(compiled_value.range.big_slots.start),
-            _ => unreachable!(),
-        })
+    ) -> TraceLocation {
+        match target {
+            MakeTraceDeclTarget::Expr(target) => {
+                let compiled_value = self.compile_expr(instantiated_module, target);
+                let compiled_value = self.compiled_expr_to_value(compiled_value, source_location);
+                TraceLocation::Scalar(self.new_sim_trace(match compiled_value.range.len() {
+                    TypeLen::A_SMALL_SLOT => small_kind(compiled_value.range.small_slots.start),
+                    TypeLen::A_BIG_SLOT => big_kind(compiled_value.range.big_slots.start),
+                    _ => unreachable!(),
+                }))
+            }
+            MakeTraceDeclTarget::Memory {
+                id,
+                depth,
+                stride,
+                start,
+                ty,
+            } => TraceLocation::Memory(TraceMemoryLocation {
+                id,
+                depth,
+                stride,
+                start,
+                len: ty.bit_width(),
+            }),
+        }
     }
     fn make_trace_scalar(
         &mut self,
         instantiated_module: InstantiatedModule,
-        target: Expr<CanonicalType>,
+        target: MakeTraceDeclTarget,
         name: Interned<str>,
         source_location: SourceLocation,
     ) -> TraceDecl {
-        let flow = Expr::flow(target);
-        match Expr::ty(target) {
+        let flow = target.flow();
+        match target.ty() {
             CanonicalType::UInt(ty) => TraceUInt {
-                id: self.make_trace_scalar_helper(
+                location: self.make_trace_scalar_helper(
                     instantiated_module,
                     target,
                     source_location,
@@ -1667,7 +1711,7 @@ impl Compiler {
             }
             .into(),
             CanonicalType::SInt(ty) => TraceSInt {
-                id: self.make_trace_scalar_helper(
+                location: self.make_trace_scalar_helper(
                     instantiated_module,
                     target,
                     source_location,
@@ -1680,7 +1724,7 @@ impl Compiler {
             }
             .into(),
             CanonicalType::Bool(_) => TraceBool {
-                id: self.make_trace_scalar_helper(
+                location: self.make_trace_scalar_helper(
                     instantiated_module,
                     target,
                     source_location,
@@ -1694,17 +1738,36 @@ impl Compiler {
             CanonicalType::Array(_) => unreachable!(),
             CanonicalType::Enum(ty) => {
                 assert_eq!(ty.discriminant_bit_width(), ty.type_properties().bit_width);
-                let compiled_value = self.compile_expr(instantiated_module, target);
-                let compiled_value = self.compiled_expr_to_value(compiled_value, source_location);
-                let discriminant = self.compile_enum_discriminant(
-                    compiled_value.map_ty(Enum::from_canonical),
-                    source_location,
-                );
-                TraceFieldlessEnum {
-                    id: self.new_sim_trace(SimTraceKind::EnumDiscriminant {
-                        index: discriminant,
-                        ty,
+                let location = match target {
+                    MakeTraceDeclTarget::Expr(target) => {
+                        let compiled_value = self.compile_expr(instantiated_module, target);
+                        let compiled_value =
+                            self.compiled_expr_to_value(compiled_value, source_location);
+                        let discriminant = self.compile_enum_discriminant(
+                            compiled_value.map_ty(Enum::from_canonical),
+                            source_location,
+                        );
+                        TraceLocation::Scalar(self.new_sim_trace(SimTraceKind::EnumDiscriminant {
+                            index: discriminant,
+                            ty,
+                        }))
+                    }
+                    MakeTraceDeclTarget::Memory {
+                        id,
+                        depth,
+                        stride,
+                        start,
+                        ty: _,
+                    } => TraceLocation::Memory(TraceMemoryLocation {
+                        id,
+                        depth,
+                        stride,
+                        start,
+                        len: ty.type_properties().bit_width,
                     }),
+                };
+                TraceFieldlessEnum {
+                    location,
                     name,
                     ty,
                     flow,
@@ -1713,7 +1776,7 @@ impl Compiler {
             }
             CanonicalType::Bundle(_) => unreachable!(),
             CanonicalType::AsyncReset(_) => TraceAsyncReset {
-                id: self.make_trace_scalar_helper(
+                location: self.make_trace_scalar_helper(
                     instantiated_module,
                     target,
                     source_location,
@@ -1725,7 +1788,7 @@ impl Compiler {
             }
             .into(),
             CanonicalType::SyncReset(_) => TraceSyncReset {
-                id: self.make_trace_scalar_helper(
+                location: self.make_trace_scalar_helper(
                     instantiated_module,
                     target,
                     source_location,
@@ -1738,7 +1801,7 @@ impl Compiler {
             .into(),
             CanonicalType::Reset(_) => unreachable!(),
             CanonicalType::Clock(_) => TraceClock {
-                id: self.make_trace_scalar_helper(
+                location: self.make_trace_scalar_helper(
                     instantiated_module,
                     target,
                     source_location,
@@ -1754,16 +1817,33 @@ impl Compiler {
     fn make_trace_decl_child(
         &mut self,
         instantiated_module: InstantiatedModule,
-        target: Expr<CanonicalType>,
+        target: MakeTraceDeclTarget,
         name: Interned<str>,
         source_location: SourceLocation,
     ) -> TraceDecl {
-        match Expr::ty(target) {
+        match target.ty() {
             CanonicalType::Array(ty) => {
                 let elements = Interned::from_iter((0..ty.len()).map(|index| {
                     self.make_trace_decl_child(
                         instantiated_module,
-                        Expr::<Array>::from_canonical(target)[index],
+                        match target {
+                            MakeTraceDeclTarget::Expr(target) => MakeTraceDeclTarget::Expr(
+                                Expr::<Array>::from_canonical(target)[index],
+                            ),
+                            MakeTraceDeclTarget::Memory {
+                                id,
+                                depth,
+                                stride,
+                                start,
+                                ty: _,
+                            } => MakeTraceDeclTarget::Memory {
+                                id,
+                                depth,
+                                stride,
+                                start: start + ty.element().bit_width() * index,
+                                ty: ty.element(),
+                            },
+                        },
                         Intern::intern_owned(format!("[{index}]")),
                         source_location,
                     )
@@ -1772,7 +1852,7 @@ impl Compiler {
                     name,
                     elements,
                     ty,
-                    flow: Expr::flow(target),
+                    flow: target.flow(),
                 }
                 .into()
             }
@@ -1780,32 +1860,73 @@ impl Compiler {
                 if ty.variants().iter().all(|v| v.ty.is_none()) {
                     self.make_trace_scalar(instantiated_module, target, name, source_location)
                 } else {
-                    let flow = Expr::flow(target);
-                    let compiled_value = self.compile_expr(instantiated_module, target);
-                    let compiled_value =
-                        self.compiled_expr_to_value(compiled_value, source_location);
-                    let discriminant = self.compile_enum_discriminant(
-                        compiled_value.map_ty(Enum::from_canonical),
-                        source_location,
-                    );
-                    let discriminant = TraceEnumDiscriminant {
-                        id: self.new_sim_trace(SimTraceKind::EnumDiscriminant {
-                            index: discriminant,
-                            ty,
+                    let flow = target.flow();
+                    let location = match target {
+                        MakeTraceDeclTarget::Expr(target) => {
+                            let compiled_value = self.compile_expr(instantiated_module, target);
+                            let compiled_value =
+                                self.compiled_expr_to_value(compiled_value, source_location);
+                            let discriminant = self.compile_enum_discriminant(
+                                compiled_value.map_ty(Enum::from_canonical),
+                                source_location,
+                            );
+                            TraceLocation::Scalar(self.new_sim_trace(
+                                SimTraceKind::EnumDiscriminant {
+                                    index: discriminant,
+                                    ty,
+                                },
+                            ))
+                        }
+                        MakeTraceDeclTarget::Memory {
+                            id,
+                            depth,
+                            stride,
+                            start,
+                            ty: _,
+                        } => TraceLocation::Memory(TraceMemoryLocation {
+                            id,
+                            depth,
+                            stride,
+                            start,
+                            len: ty.discriminant_bit_width(),
                         }),
+                    };
+                    let discriminant = TraceEnumDiscriminant {
+                        location,
                         name: "$tag".intern(),
                         ty,
                         flow,
                     };
-                    let base = Expr::<Enum>::from_canonical(target);
                     let non_empty_fields =
                         Interned::from_iter(ty.variants().into_iter().enumerate().flat_map(
                             |(variant_index, variant)| {
-                                variant.ty.map(|_| {
+                                variant.ty.map(|variant_ty| {
                                     self.make_trace_decl_child(
                                         instantiated_module,
-                                        ops::VariantAccess::new_by_index(base, variant_index)
-                                            .to_expr(),
+                                        match target {
+                                            MakeTraceDeclTarget::Expr(target) => {
+                                                MakeTraceDeclTarget::Expr(
+                                                    ops::VariantAccess::new_by_index(
+                                                        Expr::<Enum>::from_canonical(target),
+                                                        variant_index,
+                                                    )
+                                                    .to_expr(),
+                                                )
+                                            }
+                                            MakeTraceDeclTarget::Memory {
+                                                id,
+                                                depth,
+                                                stride,
+                                                start,
+                                                ty: _,
+                                            } => MakeTraceDeclTarget::Memory {
+                                                id,
+                                                depth,
+                                                stride,
+                                                start: start + ty.discriminant_bit_width(),
+                                                ty: variant_ty,
+                                            },
+                                        },
                                         variant.name,
                                         source_location,
                                     )
@@ -1823,19 +1944,41 @@ impl Compiler {
                 }
             }
             CanonicalType::Bundle(ty) => {
-                let fields = Interned::from_iter(ty.fields().iter().map(|field| {
-                    self.make_trace_decl_child(
-                        instantiated_module,
-                        Expr::field(Expr::<Bundle>::from_canonical(target), &field.name),
-                        field.name,
-                        source_location,
-                    )
-                }));
+                let fields = Interned::from_iter(ty.fields().iter().zip(ty.field_offsets()).map(
+                    |(field, field_offset)| {
+                        self.make_trace_decl_child(
+                            instantiated_module,
+                            match target {
+                                MakeTraceDeclTarget::Expr(target) => {
+                                    MakeTraceDeclTarget::Expr(Expr::field(
+                                        Expr::<Bundle>::from_canonical(target),
+                                        &field.name,
+                                    ))
+                                }
+                                MakeTraceDeclTarget::Memory {
+                                    id,
+                                    depth,
+                                    stride,
+                                    start,
+                                    ty: _,
+                                } => MakeTraceDeclTarget::Memory {
+                                    id,
+                                    depth,
+                                    stride,
+                                    start: start + field_offset,
+                                    ty: field.ty,
+                                },
+                            },
+                            field.name,
+                            source_location,
+                        )
+                    },
+                ));
                 TraceBundle {
                     name,
                     fields,
                     ty,
-                    flow: Expr::flow(target),
+                    flow: target.flow(),
                 }
                 .into()
             }
@@ -1855,7 +1998,7 @@ impl Compiler {
         instantiated_module: InstantiatedModule,
         target_base: TargetBase,
     ) -> TraceDecl {
-        let target = target_base.to_expr();
+        let target = MakeTraceDeclTarget::Expr(target_base.to_expr());
         match target_base {
             TargetBase::ModuleIO(module_io) => TraceModuleIO {
                 name: module_io.name(),
@@ -3810,10 +3953,10 @@ impl Compiler {
                     insns.push(
                         match data.len() {
                             TypeLen::A_BIG_SLOT => {
-                                let dest = data.big_slots.start;
+                                let value = data.big_slots.start;
                                 if signed {
-                                    Insn::MemoryReadSInt {
-                                        dest,
+                                    Insn::MemoryWriteSInt {
+                                        value,
                                         memory,
                                         addr,
                                         stride,
@@ -3821,8 +3964,8 @@ impl Compiler {
                                         width,
                                     }
                                 } else {
-                                    Insn::MemoryReadUInt {
-                                        dest,
+                                    Insn::MemoryWriteUInt {
+                                        value,
                                         memory,
                                         addr,
                                         stride,
@@ -3832,7 +3975,7 @@ impl Compiler {
                                 }
                             }
                             TypeLen::A_SMALL_SLOT => {
-                                let _dest = data.small_slots.start;
+                                let _value = data.small_slots.start;
                                 todo!("memory ports' data are always big for now");
                             }
                             _ => unreachable!(),
@@ -4139,7 +4282,7 @@ impl Compiler {
                 }),
             ))
             .start;
-        let ports = mem
+        let (ports, trace_ports) = mem
             .ports()
             .iter()
             .map(|&port| {
@@ -4149,7 +4292,11 @@ impl Compiler {
                     target: target_base.into(),
                 };
                 self.decl_conditions.insert(target, conditions);
-                trace_decls.push(self.make_trace_decl(instantiated_module, target_base));
+                let TraceDecl::Scope(TraceScope::MemPort(trace_port)) =
+                    self.make_trace_decl(instantiated_module, target_base)
+                else {
+                    unreachable!();
+                };
                 let clk = Expr::field(port.to_expr(), "clk");
                 let clk = self.compile_expr(instantiated_module, clk);
                 let clk = self.compiled_expr_to_value(clk, mem.source_location());
@@ -4318,20 +4465,53 @@ impl Compiler {
                     }),
                 );
                 self.add_assignment(Interned::default(), read_insns, mem.source_location());
-                MemoryPort {
-                    clk_triggered,
-                    addr_delayed,
-                    en_delayed,
-                    data_layout,
-                    read_data_delayed,
-                    write_data_delayed,
-                    write_mask_delayed,
-                    write_mode_delayed,
-                    write_insns,
-                }
+                (
+                    MemoryPort {
+                        clk_triggered,
+                        addr_delayed,
+                        en_delayed,
+                        data_layout,
+                        read_data_delayed,
+                        write_data_delayed,
+                        write_mask_delayed,
+                        write_mode_delayed,
+                        write_insns,
+                    },
+                    trace_port,
+                )
             })
-            .collect();
-        self.memories.push(Memory { mem, memory, ports });
+            .unzip();
+        let name = mem.scoped_name().1 .0;
+        let id = TraceMemoryId(self.memories.len());
+        let stride = mem.array_type().element().bit_width();
+        let trace = TraceMem {
+            id,
+            name,
+            stride,
+            element_type: self
+                .make_trace_decl_child(
+                    instantiated_module,
+                    MakeTraceDeclTarget::Memory {
+                        id,
+                        depth: mem.array_type().len(),
+                        stride,
+                        start: 0,
+                        ty: mem.array_type().element(),
+                    },
+                    name,
+                    mem.source_location(),
+                )
+                .intern_sized(),
+            ports: Intern::intern_owned(trace_ports),
+            array_type: mem.array_type(),
+        };
+        trace_decls.push(trace.into());
+        self.memories.push(Memory {
+            mem,
+            memory,
+            trace,
+            ports,
+        });
     }
     fn compile_block(
         &mut self,
@@ -4657,12 +4837,13 @@ impl Compiler {
         }
     }
     fn process_memories(&mut self) {
-        for Memory {
-            mem,
-            memory: _,
-            ports,
-        } in mem::take(&mut self.memories)
-        {
+        for memory_index in 0..self.memories.len() {
+            let Memory {
+                mem,
+                memory: _,
+                trace: _,
+                ref mut ports,
+            } = self.memories[memory_index];
             for MemoryPort {
                 clk_triggered,
                 addr_delayed,
@@ -4673,7 +4854,7 @@ impl Compiler {
                 write_mask_delayed,
                 write_mode_delayed,
                 write_insns,
-            } in ports
+            } in mem::take(ports)
             {
                 let port_end = self.insns.new_label();
                 self.insns.push(
@@ -4732,7 +4913,15 @@ impl Compiler {
                 self.original_base_module,
                 self.original_base_module.source_location(),
             ),
-            traces: Intern::intern_owned(self.traces),
+            traces: SimTraces(Intern::intern_owned(self.traces.0)),
+            trace_memories: Interned::from_iter(self.memories.iter().map(
+                |&Memory {
+                     mem: _,
+                     memory,
+                     trace,
+                     ports: _,
+                 }| (memory, trace),
+            )),
             clocks_triggered,
         }
     }
@@ -4749,7 +4938,8 @@ pub struct Compiled<T: BundleType> {
     insns: Interned<Insns<InsnsBuildingDone>>,
     base_module: CompiledModule,
     io: Instance<T>,
-    traces: Interned<[SimTrace<()>]>,
+    traces: SimTraces<Interned<[SimTrace<SimTraceKind, ()>]>>,
+    trace_memories: Interned<[(StatePartIndex<StatePartKindMemories>, TraceMem)]>,
     clocks_triggered: Interned<[StatePartIndex<StatePartKindSmallSlots>]>,
 }
 
@@ -4763,6 +4953,7 @@ impl<T: BundleType> Compiled<T> {
             base_module,
             io,
             traces,
+            trace_memories,
             clocks_triggered,
         } = self;
         Compiled {
@@ -4770,6 +4961,7 @@ impl<T: BundleType> Compiled<T> {
             base_module,
             io: Instance::from_canonical(io.canonical()),
             traces,
+            trace_memories,
             clocks_triggered,
         }
     }
@@ -4779,6 +4971,7 @@ impl<T: BundleType> Compiled<T> {
             base_module,
             io,
             traces,
+            trace_memories,
             clocks_triggered,
         } = canonical;
         Self {
@@ -4786,6 +4979,7 @@ impl<T: BundleType> Compiled<T> {
             base_module,
             io: Instance::from_canonical(io.canonical()),
             traces,
+            trace_memories,
             clocks_triggered,
         }
     }
@@ -4806,6 +5000,45 @@ impl TraceScalarId {
     }
 }
 
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
+pub struct TraceMemoryId(usize);
+
+impl fmt::Debug for TraceMemoryId {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "TraceMemoryId({})", self.0)
+    }
+}
+
+impl TraceMemoryId {
+    pub fn as_usize(self) -> usize {
+        self.0
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
+pub struct TraceMemoryLocation {
+    pub id: TraceMemoryId,
+    pub depth: usize,
+    pub stride: usize,
+    pub start: usize,
+    pub len: usize,
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
+pub enum TraceLocation {
+    Scalar(TraceScalarId),
+    Memory(TraceMemoryLocation),
+}
+
+impl fmt::Debug for TraceLocation {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self {
+            Self::Scalar(v) => v.fmt(f),
+            Self::Memory(v) => v.fmt(f),
+        }
+    }
+}
+
 macro_rules! impl_trace_decl {
     (
         $(
@@ -4956,6 +5189,17 @@ impl_trace_decl! {
             module: TraceModule,
             ty: Bundle,
         }),
+        Mem(TraceMem {
+            fn children(self) -> _ {
+                Interned::from_iter([*self.element_type].into_iter().chain(self.ports.iter().map(|&v| v.into())))
+            }
+            id: TraceMemoryId,
+            name: Interned<str>,
+            stride: usize,
+            element_type: Interned<TraceDecl>,
+            ports: Interned<[TraceMemPort]>,
+            array_type: Array,
+        }),
         MemPort(TraceMemPort {
             fn children(self) -> _ {
                 [self.bundle.into()][..].intern()
@@ -5020,72 +5264,72 @@ impl_trace_decl! {
     }),
     #[kind = TraceScalarKind]
     Scalar(TraceScalar {
-        fn id(self) -> TraceScalarId;
+        fn location(self) -> TraceLocation;
         UInt(TraceUInt {
-            fn id(self) -> _ {
-                self.id
+            fn location(self) -> _ {
+                self.location
             }
-            id: TraceScalarId,
+            location: TraceLocation,
             name: Interned<str>,
             ty: UInt,
             flow: Flow,
         }),
         SInt(TraceSInt {
-            fn id(self) -> _ {
-                self.id
+            fn location(self) -> _ {
+                self.location
             }
-            id: TraceScalarId,
+            location: TraceLocation,
             name: Interned<str>,
             ty: SInt,
             flow: Flow,
         }),
         Bool(TraceBool {
-            fn id(self) -> _ {
-                self.id
+            fn location(self) -> _ {
+                self.location
             }
-            id: TraceScalarId,
+            location: TraceLocation,
             name: Interned<str>,
             flow: Flow,
         }),
         FieldlessEnum(TraceFieldlessEnum {
-            fn id(self) -> _ {
-                self.id
+            fn location(self) -> _ {
+                self.location
             }
-            id: TraceScalarId,
+            location: TraceLocation,
             name: Interned<str>,
             ty: Enum,
             flow: Flow,
         }),
         EnumDiscriminant(TraceEnumDiscriminant {
-            fn id(self) -> _ {
-                self.id
+            fn location(self) -> _ {
+                self.location
             }
-            id: TraceScalarId,
+            location: TraceLocation,
             name: Interned<str>,
             ty: Enum,
             flow: Flow,
         }),
         Clock(TraceClock {
-            fn id(self) -> _ {
-                self.id
+            fn location(self) -> _ {
+                self.location
             }
-            id: TraceScalarId,
+            location: TraceLocation,
             name: Interned<str>,
             flow: Flow,
         }),
         SyncReset(TraceSyncReset {
-            fn id(self) -> _ {
-                self.id
+            fn location(self) -> _ {
+                self.location
             }
-            id: TraceScalarId,
+            location: TraceLocation,
             name: Interned<str>,
             flow: Flow,
         }),
         AsyncReset(TraceAsyncReset {
-            fn id(self) -> _ {
-                self.id
+            fn location(self) -> _ {
+                self.location
             }
-            id: TraceScalarId,
+            location: TraceLocation,
             name: Interned<str>,
             flow: Flow,
         }),
@@ -5095,11 +5339,21 @@ impl_trace_decl! {
 pub trait TraceWriterDecls: fmt::Debug + 'static + Sized {
     type Error: std::error::Error + Send + Sync + 'static;
     type TraceWriter: TraceWriter<Error = Self::Error>;
-    fn write_decls(self, module: TraceModule) -> Result<Self::TraceWriter, Self::Error>;
+    fn write_decls(
+        self,
+        module: TraceModule,
+        trace_scalar_id_count: usize,
+        trace_memory_id_count: usize,
+    ) -> Result<Self::TraceWriter, Self::Error>;
 }
 
 trait TraceWriterDeclsDynTrait: fmt::Debug {
-    fn write_decls_dyn(self: Box<Self>, module: TraceModule) -> std::io::Result<DynTraceWriter>;
+    fn write_decls_dyn(
+        self: Box<Self>,
+        module: TraceModule,
+        trace_scalar_id_count: usize,
+        trace_memory_id_count: usize,
+    ) -> std::io::Result<DynTraceWriter>;
 }
 
 fn err_into_io<E: std::error::Error + Send + Sync + 'static>(e: E) -> std::io::Error {
@@ -5110,9 +5364,20 @@ fn err_into_io<E: std::error::Error + Send + Sync + 'static>(e: E) -> std::io::E
 }
 
 impl<T: TraceWriterDecls> TraceWriterDeclsDynTrait for T {
-    fn write_decls_dyn(self: Box<Self>, module: TraceModule) -> std::io::Result<DynTraceWriter> {
+    fn write_decls_dyn(
+        self: Box<Self>,
+        module: TraceModule,
+        trace_scalar_id_count: usize,
+        trace_memory_id_count: usize,
+    ) -> std::io::Result<DynTraceWriter> {
         Ok(DynTraceWriter(Box::new(
-            TraceWriterDecls::write_decls(*self, module).map_err(err_into_io)?,
+            TraceWriterDecls::write_decls(
+                *self,
+                module,
+                trace_scalar_id_count,
+                trace_memory_id_count,
+            )
+            .map_err(err_into_io)?,
         )))
     }
 }
@@ -5135,6 +5400,12 @@ pub trait TraceWriter: fmt::Debug + 'static {
     {
         Ok(())
     }
+    fn set_memory_element(
+        &mut self,
+        memory: TraceMemoryId,
+        element_index: usize,
+        element_data: &BitSlice,
+    ) -> Result<(), Self::Error>;
     fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error>;
     fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error>;
     fn set_signal_bool(&mut self, id: TraceScalarId, value: bool) -> Result<(), Self::Error> {
@@ -5182,8 +5453,14 @@ impl fmt::Debug for DynTraceWriterDecls {
 impl TraceWriterDecls for DynTraceWriterDecls {
     type Error = std::io::Error;
     type TraceWriter = DynTraceWriter;
-    fn write_decls(self, module: TraceModule) -> Result<Self::TraceWriter, Self::Error> {
-        self.0.write_decls_dyn(module)
+    fn write_decls(
+        self,
+        module: TraceModule,
+        trace_scalar_id_count: usize,
+        trace_memory_id_count: usize,
+    ) -> Result<Self::TraceWriter, Self::Error> {
+        self.0
+            .write_decls_dyn(module, trace_scalar_id_count, trace_memory_id_count)
     }
 }
 
@@ -5192,6 +5469,12 @@ trait TraceWriterDynTrait: fmt::Debug + 'static {
     fn change_time_to_dyn(&mut self, instant: SimInstant) -> std::io::Result<()>;
     fn flush_dyn(&mut self) -> std::io::Result<()>;
     fn close_dyn(self: Box<Self>) -> std::io::Result<()>;
+    fn set_memory_element_dyn(
+        &mut self,
+        memory: TraceMemoryId,
+        element_index: usize,
+        element_data: &BitSlice,
+    ) -> std::io::Result<()>;
     fn set_signal_uint_dyn(&mut self, id: TraceScalarId, value: &BitSlice) -> std::io::Result<()>;
     fn set_signal_sint_dyn(&mut self, id: TraceScalarId, value: &BitSlice) -> std::io::Result<()>;
     fn set_signal_bool_dyn(&mut self, id: TraceScalarId, value: bool) -> std::io::Result<()>;
@@ -5220,6 +5503,17 @@ impl<T: TraceWriter> TraceWriterDynTrait for T {
     fn close_dyn(self: Box<Self>) -> std::io::Result<()> {
         Ok(TraceWriter::close(*self).map_err(err_into_io)?)
     }
+    fn set_memory_element_dyn(
+        &mut self,
+        memory: TraceMemoryId,
+        element_index: usize,
+        element_data: &BitSlice,
+    ) -> std::io::Result<()> {
+        Ok(
+            TraceWriter::set_memory_element(self, memory, element_index, element_data)
+                .map_err(err_into_io)?,
+        )
+    }
     fn set_signal_uint_dyn(&mut self, id: TraceScalarId, value: &BitSlice) -> std::io::Result<()> {
         Ok(TraceWriter::set_signal_uint(self, id, value).map_err(err_into_io)?)
     }
@@ -5274,6 +5568,15 @@ impl TraceWriter for DynTraceWriter {
     fn close(self) -> Result<(), Self::Error> {
         self.0.close_dyn()
     }
+    fn set_memory_element(
+        &mut self,
+        memory: TraceMemoryId,
+        element_index: usize,
+        element_data: &BitSlice,
+    ) -> Result<(), Self::Error> {
+        self.0
+            .set_memory_element_dyn(memory, element_index, element_data)
+    }
     fn change_time_to(&mut self, instant: SimInstant) -> Result<(), Self::Error> {
         self.0.change_time_to_dyn(instant)
     }
@@ -5318,24 +5621,91 @@ enum TraceWriterState<T: TraceWriterDecls> {
     Errored(Option<T::Error>),
 }
 
+trait SimTraceDebug<I> {
+    fn fmt(&self, id: I, f: &mut fmt::Formatter<'_>) -> fmt::Result;
+}
+
+struct SimTraceDebugAsDebug<T, I>(T, I);
+
+impl<T: ?Sized, I: Copy> fmt::Debug for SimTraceDebugAsDebug<&'_ T, I>
+where
+    T: SimTraceDebug<I>,
+{
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.0.fmt(self.1, f)
+    }
+}
+
+impl<T, I> SimTraceDebug<I> for Vec<T>
+where
+    [T]: SimTraceDebug<I>,
+{
+    fn fmt(&self, id: I, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        <[T]>::fmt(&**self, id, f)
+    }
+}
+
+impl<T: ?Sized + 'static + Send + Sync, I> SimTraceDebug<I> for Interned<T>
+where
+    T: SimTraceDebug<I>,
+{
+    fn fmt(&self, id: I, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        T::fmt(&**self, id, f)
+    }
+}
+
+impl<T: ?Sized + 'static + Send + Sync, I> SimTraceDebug<I> for Box<T>
+where
+    T: SimTraceDebug<I>,
+{
+    fn fmt(&self, id: I, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        T::fmt(&**self, id, f)
+    }
+}
+
+impl<T> SimTraceDebug<()> for [T]
+where
+    T: SimTraceDebug<TraceScalarId>,
+{
+    fn fmt(&self, _id: (), f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_list()
+            .entries(
+                self.iter()
+                    .enumerate()
+                    .map(|(id, v)| SimTraceDebugAsDebug(v, TraceScalarId(id))),
+            )
+            .finish()
+    }
+}
+
 #[derive(Clone, PartialEq, Eq, Hash)]
-struct SimTrace<S> {
-    id: TraceScalarId,
-    kind: SimTraceKind,
+struct SimTrace<K, S> {
+    kind: K,
     state: S,
     last_state: S,
 }
 
-impl fmt::Debug for SimTrace<()> {
+#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+struct SimTraces<T>(T);
+
+impl<T> fmt::Debug for SimTraces<T>
+where
+    T: SimTraceDebug<()>,
+{
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.0.fmt((), f)
+    }
+}
+
+impl<K: fmt::Debug> SimTraceDebug<TraceScalarId> for SimTrace<K, ()> {
+    fn fmt(&self, id: TraceScalarId, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
-            id,
             kind,
             state,
             last_state,
         } = self;
         f.debug_struct("SimTrace")
-            .field("id", id)
+            .field("id", &id)
             .field("kind", kind)
             .field("state", state)
             .field("last_state", last_state)
@@ -5343,16 +5713,15 @@ impl fmt::Debug for SimTrace<()> {
     }
 }
 
-impl fmt::Debug for SimTrace<BitVec> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+impl<K: fmt::Debug> SimTraceDebug<TraceScalarId> for SimTrace<K, BitVec> {
+    fn fmt(&self, id: TraceScalarId, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
-            id,
             kind,
             state,
             last_state,
         } = self;
         f.debug_struct("SimTrace")
-            .field("id", id)
+            .field("id", &id)
             .field("kind", kind)
             .field("state", &BitSliceWriteWithBase(state))
             .field("last_state", &BitSliceWriteWithBase(last_state))
@@ -5440,7 +5809,8 @@ struct SimulationImpl {
     made_initial_step: bool,
     needs_settle: bool,
     trace_decls: TraceModule,
-    traces: Box<[SimTrace<BitVec>]>,
+    traces: SimTraces<Box<[SimTrace<SimTraceKind, BitVec>]>>,
+    trace_memories: HashMap<StatePartIndex<StatePartKindMemories>, TraceMem>,
     trace_writers: Vec<TraceWriterState<DynTraceWriterDecls>>,
     instant: SimInstant,
     clocks_triggered: Interned<[StatePartIndex<StatePartKindSmallSlots>]>,
@@ -5491,19 +5861,18 @@ impl SimulationImpl {
             made_initial_step: false,
             needs_settle: true,
             trace_decls: compiled.base_module.trace_decls,
-            traces: Box::from_iter(compiled.traces.iter().map(
+            traces: SimTraces(Box::from_iter(compiled.traces.0.iter().map(
                 |&SimTrace {
-                     id,
                      kind,
                      state: _,
                      last_state: _,
                  }| SimTrace {
-                    id,
                     kind,
                     state: kind.make_state(),
                     last_state: kind.make_state(),
                 },
-            )),
+            ))),
+            trace_memories: HashMap::from_iter(compiled.trace_memories.iter().copied()),
             trace_writers: vec![],
             instant: SimInstant::START,
             clocks_triggered: compiled.clocks_triggered,
@@ -5528,16 +5897,41 @@ impl SimulationImpl {
         &mut self,
         mut trace_writer: DynTraceWriter,
     ) -> std::io::Result<DynTraceWriter> {
-        for &SimTrace {
+        let mut set_memory_element = |memory: StatePartIndex<StatePartKindMemories>,
+                                      trace_mem: &TraceMem,
+                                      element_index: usize| {
+            let start = trace_mem.stride * element_index;
+            let end = start + trace_mem.stride;
+            trace_writer.set_memory_element(
+                self.trace_memories[&memory].id,
+                element_index,
+                &self.state.memories[memory][start..end],
+            )
+        };
+        if ONLY_IF_CHANGED {
+            for &(memory, element_index) in &self.state.memory_write_log {
+                set_memory_element(memory, &self.trace_memories[&memory], element_index)?;
+            }
+        } else {
+            for (&memory, trace_mem) in &self.trace_memories {
+                for element_index in 0..trace_mem.array_type.len() {
+                    set_memory_element(memory, trace_mem, element_index)?;
+                }
+            }
+        }
+        for (
             id,
-            kind,
-            ref state,
-            ref last_state,
-        } in &self.traces
+            &SimTrace {
+                kind,
+                ref state,
+                ref last_state,
+            },
+        ) in self.traces.0.iter().enumerate()
         {
             if ONLY_IF_CHANGED && state == last_state {
                 continue;
             }
+            let id = TraceScalarId(id);
             match kind {
                 SimTraceKind::BigUInt { .. } | SimTraceKind::SmallUInt { .. } => {
                     trace_writer.set_signal_uint(id, state)?;
@@ -5588,11 +5982,10 @@ impl SimulationImpl {
     #[inline(never)]
     fn read_traces<const IS_INITIAL_STEP: bool>(&mut self) {
         for &mut SimTrace {
-            id: _,
             kind,
             ref mut state,
             ref mut last_state,
-        } in &mut self.traces
+        } in &mut self.traces.0
         {
             if !IS_INITIAL_STEP {
                 mem::swap(state, last_state);
@@ -5667,6 +6060,8 @@ impl SimulationImpl {
             } else {
                 self.read_traces::<true>();
             }
+            self.state.memory_write_log.sort_unstable();
+            self.state.memory_write_log.dedup();
             self.made_initial_step = true;
             self.needs_settle = self
                 .clocks_triggered
@@ -5675,7 +6070,11 @@ impl SimulationImpl {
             self.for_each_trace_writer_storing_error(|this, trace_writer_state| {
                 Ok(match trace_writer_state {
                     TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running(
-                        this.init_trace_writer(trace_writer_decls.write_decls(this.trace_decls)?)?,
+                        this.init_trace_writer(trace_writer_decls.write_decls(
+                            this.trace_decls,
+                            this.traces.0.len(),
+                            this.trace_memories.len(),
+                        )?)?,
                     ),
                     TraceWriterState::Init(trace_writer) => {
                         TraceWriterState::Running(this.init_trace_writer(trace_writer)?)
@@ -5686,6 +6085,7 @@ impl SimulationImpl {
                     TraceWriterState::Errored(e) => TraceWriterState::Errored(e),
                 })
             });
+            self.state.memory_write_log.clear();
         }
         panic!("settle(): took too many steps");
     }
@@ -5712,7 +6112,12 @@ impl SimulationImpl {
         } else {
             match target.flow() {
                 Flow::Source => {
-                    panic!("can't read from an output before the simulation has made any steps");
+                    if !self.uninitialized_inputs.is_empty() {
+                        panic!(
+                            "can't read from an output before the simulation has made any steps"
+                        );
+                    }
+                    self.settle();
                 }
                 Flow::Sink => {
                     if self.uninitialized_inputs.contains(&*target) {
@@ -5802,7 +6207,13 @@ impl SimulationImpl {
         let mut retval = Ok(());
         let close_trace_writer =
             |trace_writer: TraceWriterState<DynTraceWriterDecls>| match trace_writer {
-                TraceWriterState::Decls(v) => v.write_decls(self.trace_decls)?.close(),
+                TraceWriterState::Decls(v) => v
+                    .write_decls(
+                        self.trace_decls,
+                        self.traces.0.len(),
+                        self.trace_memories.len(),
+                    )?
+                    .close(),
                 TraceWriterState::Init(v) => v.close(),
                 TraceWriterState::Running(v) => v.close(),
                 TraceWriterState::Errored(Some(e)) => Err(e),
@@ -5873,7 +6284,11 @@ impl SimulationImpl {
         self.for_each_trace_writer_getting_error(
             |this, trace_writer: TraceWriterState<DynTraceWriterDecls>| match trace_writer {
                 TraceWriterState::Decls(v) => {
-                    let mut v = v.write_decls(this.trace_decls)?;
+                    let mut v = v.write_decls(
+                        this.trace_decls,
+                        this.traces.0.len(),
+                        this.trace_memories.len(),
+                    )?;
                     v.flush()?;
                     Ok(TraceWriterState::Init(v))
                 }
@@ -5957,6 +6372,7 @@ impl<T: BundleType> fmt::Debug for Simulation<T> {
                     needs_settle,
                     trace_decls,
                     traces,
+                    trace_memories,
                     trace_writers,
                     instant,
                     clocks_triggered,
@@ -5975,6 +6391,7 @@ impl<T: BundleType> fmt::Debug for Simulation<T> {
             .field("needs_settle", needs_settle)
             .field("trace_decls", trace_decls)
             .field("traces", traces)
+            .field("trace_memories", trace_memories)
             .field("trace_writers", trace_writers)
             .field("instant", instant)
             .field("clocks_triggered", clocks_triggered)
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index aabf6e2..e4a0570 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -990,6 +990,7 @@ macro_rules! make_state_part_kinds {
         pub(crate) struct State {
             pub(crate) insns: Interned<Insns<InsnsBuildingDone>>,
             pub(crate) pc: usize,
+            pub(crate) memory_write_log: Vec<(StatePartIndex<StatePartKindMemories>, usize)>,
             $(pub(crate) $state_field: StatePart<$StateKind>,)*
             $(pub(crate) $type_field: StatePart<$TypeKind>,)*
         }
@@ -999,6 +1000,7 @@ macro_rules! make_state_part_kinds {
                 Self {
                     insns,
                     pc: 0,
+                    memory_write_log: Vec::with_capacity(32),
                     $($state_field: StatePart::new(&insns.state_layout.$state_field.layout_data),)*
                     $($type_field: StatePart::new(&insns.state_layout.ty.$type_field.layout_data),)*
                 }
@@ -1009,6 +1011,7 @@ macro_rules! make_state_part_kinds {
                     insns: &self.insns.insns,
                     pc: self.pc,
                     orig_pc: &mut self.pc,
+                    memory_write_log: &mut self.memory_write_log,
                     $($state_field: self.$state_field.borrow(),)*
                     $($type_field: self.$type_field.borrow(),)*
                 }
@@ -1021,6 +1024,7 @@ macro_rules! make_state_part_kinds {
             pub(crate) insns: &'a [Insn],
             pub(crate) orig_pc: &'a mut usize,
             pub(crate) pc: usize,
+            pub(crate) memory_write_log: &'a mut Vec<(StatePartIndex<StatePartKindMemories>, usize)>,
             $(pub(crate) $state_field: BorrowedStatePart<'a, $StateKind>,)*
             $(pub(crate) $type_field: BorrowedStatePart<'a, $TypeKind>,)*
         }
@@ -2146,6 +2150,7 @@ impl State {
         let Self {
             insns: _,
             pc,
+            memory_write_log: _,
             memories: _,
             small_slots: _,
             big_slots: _,
@@ -2172,6 +2177,18 @@ impl BorrowedState<'_> {
         }
         Some(retval)
     }
+    fn log_memory_write(&mut self, memory: StatePartIndex<StatePartKindMemories>, addr: SmallUInt) {
+        let Ok(addr) = usize::try_from(addr) else {
+            return;
+        };
+        if addr < self.memories.value.len() {
+            let log_entry = (memory, addr);
+            if self.memory_write_log.last().copied() == Some(log_entry) {
+                return;
+            }
+            self.memory_write_log.push(log_entry);
+        }
+    }
 }
 
 impl TypeIndexRange {
@@ -2898,6 +2915,7 @@ impl_insns! {
     } => {
         let addr = state.small_slots[addr];
         memory_write_big::<UInt>(&mut state.memories[memory], addr, stride, start, width, &mut state.big_slots[value]);
+        state.log_memory_write(memory, addr);
         next!();
     }
     MemoryWriteSInt {
@@ -2916,6 +2934,7 @@ impl_insns! {
     } => {
         let addr = state.small_slots[addr];
         memory_write_big::<SInt>(&mut state.memories[memory], addr, stride, start, width, &mut state.big_slots[value]);
+        state.log_memory_write(memory, addr);
         next!();
     }
     Return => {
diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs
index 0779b5c..b8248e3 100644
--- a/crates/fayalite/src/sim/vcd.rs
+++ b/crates/fayalite/src/sim/vcd.rs
@@ -9,13 +9,14 @@ use crate::{
         time::{SimDuration, SimInstant},
         TraceArray, TraceAsyncReset, TraceBool, TraceBundle, TraceClock, TraceDecl,
         TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceInstance,
-        TraceMemPort, TraceModule, TraceModuleIO, TraceReg, TraceSInt, TraceScalar, TraceScalarId,
-        TraceScope, TraceSyncReset, TraceUInt, TraceWire, TraceWriter, TraceWriterDecls,
+        TraceLocation, TraceMem, TraceMemPort, TraceMemoryId, TraceMemoryLocation, TraceModule,
+        TraceModuleIO, TraceReg, TraceSInt, TraceScalar, TraceScalarId, TraceScope, TraceSyncReset,
+        TraceUInt, TraceWire, TraceWriter, TraceWriterDecls,
     },
 };
-use bitvec::slice::BitSlice;
+use bitvec::{order::Lsb0, slice::BitSlice};
 use std::{
-    fmt::{self, Display},
+    fmt,
     io::{self, Write},
     mem,
 };
@@ -112,20 +113,20 @@ macro_rules! trait_arg {
     (
         trait $Arg:ident {
             $(
-                fn $fn:ident(self) -> $ty:ty;
+                fn $fn:ident(&mut self) -> $ty:ty;
             )*
         }
     ) => {
         trait $Arg: Sized {
-            $(fn $fn(self) -> $ty {
+            $(fn $fn(&mut self) -> $ty {
                 unreachable!()
             })*
         }
 
         $(
             impl $Arg for $ty {
-                fn $fn(self) -> $ty {
-                    self
+                fn $fn(&mut self) -> $ty {
+                    self.reborrow()
                 }
             }
         )*
@@ -134,21 +135,52 @@ macro_rules! trait_arg {
 
 trait_arg! {
     trait Arg {
-        fn module(self) -> ArgModule;
-        fn module_body(self) -> ArgModuleBody;
-        fn in_type(self) -> ArgInType;
+        fn module(&mut self) -> ArgModule<'_>;
+        fn module_body(&mut self) -> ArgModuleBody<'_>;
+        fn in_type(&mut self) -> ArgInType<'_>;
     }
 }
 
-struct ArgModule {}
+struct ArgModule<'a> {
+    properties: &'a mut VcdWriterProperties,
+}
 
-struct ArgModuleBody {}
+impl<'a> ArgModule<'a> {
+    fn reborrow(&mut self) -> ArgModule<'_> {
+        ArgModule {
+            properties: self.properties,
+        }
+    }
+}
 
-#[derive(Clone, Copy)]
-struct ArgInType {
+struct ArgModuleBody<'a> {
+    properties: &'a mut VcdWriterProperties,
+}
+
+impl<'a> ArgModuleBody<'a> {
+    fn reborrow(&mut self) -> ArgModuleBody<'_> {
+        ArgModuleBody {
+            properties: self.properties,
+        }
+    }
+}
+
+struct ArgInType<'a> {
     source_var_type: &'static str,
     sink_var_type: &'static str,
     duplex_var_type: &'static str,
+    properties: &'a mut VcdWriterProperties,
+}
+
+impl<'a> ArgInType<'a> {
+    fn reborrow(&mut self) -> ArgInType<'_> {
+        ArgInType {
+            source_var_type: self.source_var_type,
+            sink_var_type: self.sink_var_type,
+            duplex_var_type: self.duplex_var_type,
+            properties: self.properties,
+        }
+    }
 }
 
 trait WriteTrace: Copy {
@@ -179,11 +211,10 @@ impl WriteTrace for TraceScalar {
     }
 }
 
-fn write_scalar_id<W: io::Write>(writer: &mut W, id: TraceScalarId) -> io::Result<()> {
+fn write_vcd_id<W: io::Write>(writer: &mut W, mut id: usize) -> io::Result<()> {
     let min_char = b'!';
     let max_char = b'~';
     let base = (max_char - min_char + 1) as usize;
-    let mut id = id.as_usize();
     loop {
         let digit = (id % base) as u8 + min_char;
         id /= base;
@@ -195,7 +226,7 @@ fn write_scalar_id<W: io::Write>(writer: &mut W, id: TraceScalarId) -> io::Resul
     Ok(())
 }
 
-fn write_escaped<W: io::Write>(writer: &mut W, value: impl Display) -> io::Result<()> {
+fn write_escaped<W: io::Write>(writer: &mut W, value: impl fmt::Display) -> io::Result<()> {
     // escaping rules from function GTKWave uses to decode VCD strings:
     // https://github.com/gtkwave/gtkwave/blob/491f24d7e8619cfc1fcc65704ee5c967d1083c18/lib/libfst/fstapi.c#L7090
     struct Wrapper<W>(W);
@@ -247,14 +278,47 @@ fn is_unescaped_verilog_identifier(ident: &str) -> bool {
 }
 
 fn write_vcd_var<W: io::Write>(
+    properties: &mut VcdWriterProperties,
+    memory_element_part_body: MemoryElementPartBody,
     writer: &mut W,
     var_type: &str,
     size: usize,
-    id: TraceScalarId,
+    location: TraceLocation,
     name: &str,
 ) -> io::Result<()> {
+    let id = match location {
+        TraceLocation::Scalar(id) => id.as_usize(),
+        TraceLocation::Memory(TraceMemoryLocation {
+            id,
+            depth,
+            stride: _,
+            start,
+            len,
+        }) => {
+            let MemoryProperties {
+                element_parts,
+                element_part_index,
+                element_index,
+            } = &mut properties.memory_properties[id.as_usize()];
+            let first_id;
+            if let Some(element_part) = element_parts.get(*element_part_index) {
+                first_id = element_part.first_id;
+            } else {
+                first_id = properties.next_scalar_id;
+                properties.next_scalar_id += depth;
+                element_parts.push(MemoryElementPart {
+                    first_id,
+                    start,
+                    len,
+                    body: memory_element_part_body,
+                });
+            }
+            *element_part_index += 1;
+            first_id + *element_index
+        }
+    };
     write!(writer, "$var {var_type} {size} ")?;
-    write_scalar_id(writer, id)?;
+    write_vcd_id(writer, id)?;
     writer.write_all(b" ")?;
     if !is_unescaped_verilog_identifier(name) {
         writer.write_all(b"\\")?;
@@ -264,31 +328,49 @@ fn write_vcd_var<W: io::Write>(
 }
 
 impl WriteTrace for TraceUInt {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
         let ArgInType {
             source_var_type,
             sink_var_type,
             duplex_var_type,
+            properties,
         } = arg.in_type();
-        let Self { id, name, ty, flow } = self;
-        let var_type = match flow {
+        let Self {
+            location,
+            name,
+            ty,
+            flow,
+        } = self;
+        let mut var_type = match flow {
             Flow::Source => source_var_type,
             Flow::Sink => sink_var_type,
             Flow::Duplex => duplex_var_type,
         };
         if ty.width() == 0 {
-            write_vcd_var(writer, "string", ty.width(), id, &name)
-        } else {
-            write_vcd_var(writer, var_type, ty.width(), id, &name)
+            var_type = "string";
         }
+        write_vcd_var(
+            properties,
+            MemoryElementPartBody::Scalar,
+            writer,
+            var_type,
+            ty.width(),
+            location,
+            &name,
+        )
     }
 }
 
 impl WriteTrace for TraceSInt {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self { id, name, ty, flow } = self;
+        let Self {
+            location,
+            name,
+            ty,
+            flow,
+        } = self;
         TraceUInt {
-            id,
+            location,
             name,
             ty: UInt::new_dyn(ty.width()),
             flow,
@@ -299,9 +381,13 @@ impl WriteTrace for TraceSInt {
 
 impl WriteTrace for TraceBool {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self { id, name, flow } = self;
+        let Self {
+            location,
+            name,
+            flow,
+        } = self;
         TraceUInt {
-            id,
+            location,
             name,
             flow,
             ty: UInt::new_dyn(1),
@@ -312,46 +398,93 @@ impl WriteTrace for TraceBool {
 
 impl WriteTrace for TraceFieldlessEnum {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self { id, name, ty, flow } = self;
-        TraceEnumDiscriminant { id, name, ty, flow }.write_trace(writer, arg)
+        let Self {
+            location,
+            name,
+            ty,
+            flow,
+        } = self;
+        TraceEnumDiscriminant {
+            location,
+            name,
+            ty,
+            flow,
+        }
+        .write_trace(writer, arg)
     }
 }
 
 impl WriteTrace for TraceEnumDiscriminant {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
         let ArgInType {
             source_var_type: _,
             sink_var_type: _,
             duplex_var_type: _,
+            properties,
         } = arg.in_type();
         let Self {
-            id,
+            location,
             name,
-            ty: _,
+            ty,
             flow: _,
         } = self;
-        write_vcd_var(writer, "string", 1, id, &name)
+        write_vcd_var(
+            properties,
+            MemoryElementPartBody::EnumDiscriminant { ty },
+            writer,
+            "string",
+            1,
+            location,
+            &name,
+        )
     }
 }
 
 impl WriteTrace for TraceClock {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self { id, name, flow } = self;
-        TraceBool { id, name, flow }.write_trace(writer, arg)
+        let Self {
+            location,
+            name,
+            flow,
+        } = self;
+        TraceBool {
+            location,
+            name,
+            flow,
+        }
+        .write_trace(writer, arg)
     }
 }
 
 impl WriteTrace for TraceSyncReset {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self { id, name, flow } = self;
-        TraceBool { id, name, flow }.write_trace(writer, arg)
+        let Self {
+            location,
+            name,
+            flow,
+        } = self;
+        TraceBool {
+            location,
+            name,
+            flow,
+        }
+        .write_trace(writer, arg)
     }
 }
 
 impl WriteTrace for TraceAsyncReset {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self { id, name, flow } = self;
-        TraceBool { id, name, flow }.write_trace(writer, arg)
+        let Self {
+            location,
+            name,
+            flow,
+        } = self;
+        TraceBool {
+            location,
+            name,
+            flow,
+        }
+        .write_trace(writer, arg)
     }
 }
 
@@ -360,6 +493,7 @@ impl WriteTrace for TraceScope {
         match self {
             Self::Module(v) => v.write_trace(writer, arg),
             Self::Instance(v) => v.write_trace(writer, arg),
+            Self::Mem(v) => v.write_trace(writer, arg),
             Self::MemPort(v) => v.write_trace(writer, arg),
             Self::Wire(v) => v.write_trace(writer, arg),
             Self::Reg(v) => v.write_trace(writer, arg),
@@ -372,12 +506,12 @@ impl WriteTrace for TraceScope {
 }
 
 impl WriteTrace for TraceModule {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let ArgModule {} = arg.module();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgModule { properties } = arg.module();
         let Self { name, children } = self;
         write_vcd_scope(writer, "module", &name, |writer| {
             for child in children {
-                child.write_trace(writer, ArgModuleBody {})?;
+                child.write_trace(writer, ArgModuleBody { properties })?;
             }
             Ok(())
         })
@@ -385,8 +519,8 @@ impl WriteTrace for TraceModule {
 }
 
 impl WriteTrace for TraceInstance {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let ArgModuleBody {} = arg.module_body();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgModuleBody { properties } = arg.module_body();
         let Self {
             name: _,
             instance_io,
@@ -399,21 +533,74 @@ impl WriteTrace for TraceInstance {
                 source_var_type: "wire",
                 sink_var_type: "wire",
                 duplex_var_type: "wire",
+                properties,
             },
         )?;
-        module.write_trace(writer, ArgModule {})
+        module.write_trace(writer, ArgModule { properties })
+    }
+}
+
+impl WriteTrace for TraceMem {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgModuleBody { properties } = arg.module_body();
+        let Self {
+            id,
+            name,
+            stride: _,
+            element_type,
+            ports,
+            array_type,
+        } = self;
+        write_vcd_scope(writer, "struct", &*name, |writer| {
+            write_vcd_scope(writer, "struct", "contents", |writer| {
+                for element_index in 0..array_type.len() {
+                    write_vcd_scope(writer, "struct", &format!("[{element_index}]"), |writer| {
+                        properties.memory_properties[id.as_usize()].element_index = element_index;
+                        properties.memory_properties[id.as_usize()].element_part_index = 0;
+                        element_type.write_trace(
+                            writer,
+                            ArgInType {
+                                source_var_type: "reg",
+                                sink_var_type: "reg",
+                                duplex_var_type: "reg",
+                                properties,
+                            },
+                        )
+                    })?;
+                }
+                Ok(())
+            })?;
+            for port in ports {
+                port.write_trace(writer, ArgModuleBody { properties })?;
+            }
+            Ok(())
+        })
     }
 }
 
 impl WriteTrace for TraceMemPort {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        todo!()
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgModuleBody { properties } = arg.module_body();
+        let Self {
+            name: _,
+            bundle,
+            ty: _,
+        } = self;
+        bundle.write_trace(
+            writer,
+            ArgInType {
+                source_var_type: "wire",
+                sink_var_type: "wire",
+                duplex_var_type: "wire",
+                properties,
+            },
+        )
     }
 }
 
 impl WriteTrace for TraceWire {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let ArgModuleBody {} = arg.module_body();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgModuleBody { properties } = arg.module_body();
         let Self {
             name: _,
             child,
@@ -425,14 +612,15 @@ impl WriteTrace for TraceWire {
                 source_var_type: "wire",
                 sink_var_type: "wire",
                 duplex_var_type: "wire",
+                properties,
             },
         )
     }
 }
 
 impl WriteTrace for TraceReg {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let ArgModuleBody {} = arg.module_body();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgModuleBody { properties } = arg.module_body();
         let Self {
             name: _,
             child,
@@ -444,14 +632,15 @@ impl WriteTrace for TraceReg {
                 source_var_type: "reg",
                 sink_var_type: "reg",
                 duplex_var_type: "reg",
+                properties,
             },
         )
     }
 }
 
 impl WriteTrace for TraceModuleIO {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let ArgModuleBody {} = arg.module_body();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let ArgModuleBody { properties } = arg.module_body();
         let Self {
             name: _,
             child,
@@ -464,14 +653,15 @@ impl WriteTrace for TraceModuleIO {
                 source_var_type: "wire",
                 sink_var_type: "wire",
                 duplex_var_type: "wire",
+                properties,
             },
         )
     }
 }
 
 impl WriteTrace for TraceBundle {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let arg = arg.in_type();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let mut arg = arg.in_type();
         let Self {
             name,
             fields,
@@ -480,7 +670,7 @@ impl WriteTrace for TraceBundle {
         } = self;
         write_vcd_scope(writer, "struct", &name, |writer| {
             for field in fields {
-                field.write_trace(writer, arg)?;
+                field.write_trace(writer, arg.reborrow())?;
             }
             Ok(())
         })
@@ -488,8 +678,8 @@ impl WriteTrace for TraceBundle {
 }
 
 impl WriteTrace for TraceArray {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let arg = arg.in_type();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let mut arg = arg.in_type();
         let Self {
             name,
             elements,
@@ -498,7 +688,7 @@ impl WriteTrace for TraceArray {
         } = self;
         write_vcd_scope(writer, "struct", &name, |writer| {
             for element in elements {
-                element.write_trace(writer, arg)?;
+                element.write_trace(writer, arg.reborrow())?;
             }
             Ok(())
         })
@@ -506,8 +696,8 @@ impl WriteTrace for TraceArray {
 }
 
 impl WriteTrace for TraceEnumWithFields {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let arg = arg.in_type();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+        let mut arg = arg.in_type();
         let Self {
             name,
             discriminant,
@@ -516,9 +706,9 @@ impl WriteTrace for TraceEnumWithFields {
             flow: _,
         } = self;
         write_vcd_scope(writer, "struct", &name, |writer| {
-            discriminant.write_trace(writer, arg)?;
+            discriminant.write_trace(writer, arg.reborrow())?;
             for field in non_empty_fields {
-                field.write_trace(writer, arg)?;
+                field.write_trace(writer, arg.reborrow())?;
             }
             Ok(())
         })
@@ -529,76 +719,184 @@ impl<W: io::Write> TraceWriterDecls for VcdWriterDecls<W> {
     type Error = io::Error;
     type TraceWriter = VcdWriter<W>;
 
-    fn write_decls(self, module: TraceModule) -> Result<Self::TraceWriter, Self::Error> {
+    fn write_decls(
+        self,
+        module: TraceModule,
+        trace_scalar_id_count: usize,
+        trace_memory_id_count: usize,
+    ) -> Result<Self::TraceWriter, Self::Error> {
         let Self {
             mut writer,
             timescale,
         } = self;
         writeln!(writer, "$timescale {} $end", vcd_timescale(timescale))?;
-        module.write_trace(&mut writer, ArgModule {})?;
+        let mut properties = VcdWriterProperties {
+            next_scalar_id: trace_scalar_id_count,
+            memory_properties: (0..trace_memory_id_count)
+                .map(|_| MemoryProperties {
+                    element_parts: Vec::with_capacity(8),
+                    element_part_index: 0,
+                    element_index: 0,
+                })
+                .collect(),
+        };
+        module.write_trace(
+            &mut writer,
+            ArgModule {
+                properties: &mut properties,
+            },
+        )?;
         writeln!(writer, "$enddefinitions $end")?;
         writeln!(writer, "$dumpvars")?;
         Ok(VcdWriter {
             writer,
             finished_init: false,
             timescale,
+            properties,
         })
     }
 }
 
+enum MemoryElementPartBody {
+    Scalar,
+    EnumDiscriminant { ty: Enum },
+}
+
+struct MemoryElementPart {
+    first_id: usize,
+    start: usize,
+    len: usize,
+    body: MemoryElementPartBody,
+}
+
+struct MemoryProperties {
+    element_parts: Vec<MemoryElementPart>,
+    element_part_index: usize,
+    element_index: usize,
+}
+
+struct VcdWriterProperties {
+    next_scalar_id: usize,
+    memory_properties: Box<[MemoryProperties]>,
+}
+
 pub struct VcdWriter<W: io::Write + 'static> {
     writer: W,
     finished_init: bool,
     timescale: SimDuration,
+    properties: VcdWriterProperties,
 }
 
 impl<W: io::Write + 'static> VcdWriter<W> {
     pub fn timescale(&self) -> SimDuration {
         self.timescale
     }
-    fn write_string_value_change(
-        &mut self,
-        value: impl Display,
-        id: TraceScalarId,
-    ) -> io::Result<()> {
-        self.writer.write_all(b"s")?;
-        write_escaped(&mut self.writer, value)?;
-        self.writer.write_all(b" ")?;
-        write_scalar_id(&mut self.writer, id)?;
-        self.writer.write_all(b"\n")
+}
+
+fn write_string_value_change(
+    writer: &mut impl io::Write,
+    value: impl fmt::Display,
+    id: usize,
+) -> io::Result<()> {
+    writer.write_all(b"s")?;
+    write_escaped(writer, value)?;
+    writer.write_all(b" ")?;
+    write_vcd_id(writer, id)?;
+    writer.write_all(b"\n")
+}
+
+fn write_bits_value_change(
+    writer: &mut impl io::Write,
+    value: &BitSlice,
+    id: usize,
+) -> io::Result<()> {
+    match value.len() {
+        0 => writer.write_all(b"s0 ")?,
+        1 => writer.write_all(if value[0] { b"1" } else { b"0" })?,
+        _ => {
+            writer.write_all(b"b")?;
+            let mut any_ones = false;
+            for bit in value.iter().rev() {
+                if *bit {
+                    any_ones = true;
+                    writer.write_all(b"1")?;
+                } else if any_ones {
+                    writer.write_all(b"0")?;
+                }
+            }
+            if !any_ones {
+                writer.write_all(b"0")?;
+            }
+            writer.write_all(b" ")?;
+        }
     }
+    write_vcd_id(writer, id)?;
+    writer.write_all(b"\n")
+}
+
+fn write_enum_discriminant_value_change(
+    writer: &mut impl io::Write,
+    variant_index: usize,
+    ty: Enum,
+    id: usize,
+) -> io::Result<()> {
+    write_string_value_change(
+        writer,
+        format_args!(
+            "{} ({variant_index})",
+            ty.variants()
+                .get(variant_index)
+                .map(|v| &*v.name)
+                .unwrap_or("<invalid>"),
+        ),
+        id,
+    )
 }
 
 impl<W: io::Write> TraceWriter for VcdWriter<W> {
     type Error = io::Error;
 
-    fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
-        match value.len() {
-            0 => self.writer.write_all(b"s0 ")?,
-            1 => self.writer.write_all(if value[0] { b"1" } else { b"0" })?,
-            _ => {
-                self.writer.write_all(b"b")?;
-                let mut any_ones = false;
-                for bit in value.iter().rev() {
-                    if *bit {
-                        any_ones = true;
-                        self.writer.write_all(b"1")?;
-                    } else if any_ones {
-                        self.writer.write_all(b"0")?;
-                    }
+    fn set_memory_element(
+        &mut self,
+        memory: TraceMemoryId,
+        element_index: usize,
+        element_data: &BitSlice,
+    ) -> Result<(), Self::Error> {
+        for &MemoryElementPart {
+            first_id,
+            start,
+            len,
+            ref body,
+        } in &self.properties.memory_properties[memory.as_usize()].element_parts
+        {
+            match body {
+                MemoryElementPartBody::Scalar => write_bits_value_change(
+                    &mut self.writer,
+                    &element_data[start..start + len],
+                    first_id + element_index,
+                )?,
+                MemoryElementPartBody::EnumDiscriminant { ty } => {
+                    let mut variant_index = 0;
+                    BitSlice::<usize, Lsb0>::from_element_mut(&mut variant_index)[..len]
+                        .clone_from_bitslice(&element_data[start..start + len]);
+                    write_enum_discriminant_value_change(
+                        &mut self.writer,
+                        variant_index,
+                        *ty,
+                        first_id + element_index,
+                    )?
                 }
-                if !any_ones {
-                    self.writer.write_all(b"0")?;
-                }
-                self.writer.write_all(b" ")?;
             }
         }
-        write_scalar_id(&mut self.writer, id)?;
-        self.writer.write_all(b"\n")
+        Ok(())
+    }
+
+    fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
+        write_bits_value_change(&mut self.writer, value, id.as_usize())
     }
 
     fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
-        self.set_signal_uint(id, value)
+        write_bits_value_change(&mut self.writer, value, id.as_usize())
     }
 
     fn finish_init(&mut self) -> Result<(), Self::Error> {
@@ -630,16 +928,7 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
         variant_index: usize,
         ty: Enum,
     ) -> Result<(), Self::Error> {
-        self.write_string_value_change(
-            format_args!(
-                "{} ({variant_index})",
-                ty.variants()
-                    .get(variant_index)
-                    .map(|v| &*v.name)
-                    .unwrap_or("<invalid>"),
-            ),
-            id,
-        )
+        write_enum_discriminant_value_change(&mut self.writer, variant_index, ty, id.as_usize())
     }
 }
 
@@ -649,6 +938,7 @@ impl<W: io::Write> fmt::Debug for VcdWriter<W> {
             writer: _,
             finished_init,
             timescale,
+            properties: _,
         } = self;
         f.debug_struct("VcdWriter")
             .field("finished_init", finished_init)
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index a8b23f2..41d966b 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
+
 use fayalite::{
     int::UIntValue,
     prelude::*,
@@ -7,6 +8,7 @@ use fayalite::{
     sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
     util::RcWriter,
 };
+use std::num::NonZeroUsize;
 
 #[hdl_module(outline_generated)]
 pub fn connect_const() {
@@ -492,4 +494,113 @@ fn test_enums() {
     }
 }
 
-// TODO: add tests for memories
+#[hdl_module(outline_generated)]
+pub fn memories() {
+    #[hdl]
+    let r: fayalite::memory::ReadStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
+    #[hdl]
+    let w: fayalite::memory::WriteStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
+    #[hdl]
+    let mut mem = memory_with_init([(0x01u8, 0x23i8); 16]);
+    mem.read_latency(0);
+    mem.write_latency(NonZeroUsize::new(1).unwrap());
+    mem.read_under_write(ReadUnderWrite::Old);
+    connect_any(mem.new_read_port(), r);
+    connect_any(mem.new_write_port(), w);
+}
+
+#[cfg(todo)] // TODO: finish
+#[hdl]
+#[test]
+fn test_memories() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(memories());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_clock(sim.io().r.clk, false);
+    sim.write_clock(sim.io().w.clk, false);
+    #[derive(Debug, PartialEq, Eq)]
+    struct IO {
+        r_addr: u8,
+        r_en: bool,
+        r_data: (u8, i8),
+        w_addr: u8,
+        w_en: bool,
+        w_data: (u8, i8),
+        w_mask: (bool, bool),
+    }
+    let io_cycles = [IO {
+        r_addr: 0,
+        r_en: false,
+        r_data: (0, 0),
+        w_addr: 0,
+        w_en: false,
+        w_data: (0, 0),
+        w_mask: (false, false),
+    }];
+    for (
+        cycle,
+        expected @ IO {
+            r_addr,
+            r_en,
+            r_data: _,
+            w_addr,
+            w_en,
+            w_data,
+            w_mask,
+        },
+    ) in io_cycles.into_iter().enumerate()
+    {
+        sim.write_bool_or_int(sim.io().r.addr, r_addr.cast_to_static());
+        sim.write_bool(sim.io().r.en, r_en);
+        sim.write_bool_or_int(sim.io().w.addr, w_addr.cast_to_static());
+        sim.write_bool(sim.io().w.en, w_en);
+        sim.write_bool_or_int(sim.io().w.data.0, w_data.0);
+        sim.write_bool_or_int(sim.io().w.data.1, w_data.1);
+        sim.write_bool(sim.io().w.mask.0, w_mask.0);
+        sim.write_bool(sim.io().w.mask.1, w_mask.1);
+        let io = IO {
+            r_addr,
+            r_en,
+            r_data: (
+                sim.read_bool_or_int(sim.io().r.data.0)
+                    .to_bigint()
+                    .try_into()
+                    .expect("known to be in range"),
+                sim.read_bool_or_int(sim.io().r.data.1)
+                    .to_bigint()
+                    .try_into()
+                    .expect("known to be in range"),
+            ),
+            w_addr,
+            w_en,
+            w_data,
+            w_mask,
+        };
+        assert_eq!(
+            expected,
+            io,
+            "cycle: {cycle}\nvcd:\n{}",
+            String::from_utf8(writer.take()).unwrap(),
+        );
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write_clock(sim.io().r.clk, true);
+        sim.write_clock(sim.io().w.clk, true);
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write_clock(sim.io().r.clk, false);
+        sim.write_clock(sim.io().w.clk, false);
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/memories.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/memories.txt") {
+        panic!();
+    }
+}
+
+// TODO: add more tests for memories
diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt
index f361cc3..228e4a0 100644
--- a/crates/fayalite/tests/sim/expected/connect_const.txt
+++ b/crates/fayalite/tests/sim/expected/connect_const.txt
@@ -47,6 +47,7 @@ Simulation {
             ..
         },
         pc: 2,
+        memory_write_log: [],
         memories: StatePart {
             value: [],
         },
@@ -112,7 +113,7 @@ Simulation {
             TraceModuleIO {
                 name: "o",
                 child: TraceUInt {
-                    id: TraceScalarId(0),
+                    location: TraceScalarId(0),
                     name: "o",
                     ty: UInt<8>,
                     flow: Sink,
@@ -133,6 +134,7 @@ Simulation {
             last_state: 0x05,
         },
     ],
+    trace_memories: {},
     trace_writers: [],
     instant: 0 s,
     clocks_triggered: [],
diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
index 0b0c043..2421c14 100644
--- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt
+++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
@@ -73,6 +73,7 @@ Simulation {
             ..
         },
         pc: 5,
+        memory_write_log: [],
         memories: StatePart {
             value: [],
         },
@@ -175,7 +176,7 @@ Simulation {
             TraceModuleIO {
                 name: "reset_out",
                 child: TraceAsyncReset {
-                    id: TraceScalarId(0),
+                    location: TraceScalarId(0),
                     name: "reset_out",
                     flow: Sink,
                 },
@@ -185,7 +186,7 @@ Simulation {
             TraceModuleIO {
                 name: "bit_out",
                 child: TraceBool {
-                    id: TraceScalarId(1),
+                    location: TraceScalarId(1),
                     name: "bit_out",
                     flow: Sink,
                 },
@@ -212,6 +213,7 @@ Simulation {
             last_state: 0x1,
         },
     ],
+    trace_memories: {},
     trace_writers: [
         Running(
             VcdWriter {
diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt
index 0f49e80..104ddeb 100644
--- a/crates/fayalite/tests/sim/expected/counter_async.txt
+++ b/crates/fayalite/tests/sim/expected/counter_async.txt
@@ -168,6 +168,7 @@ Simulation {
             ..
         },
         pc: 18,
+        memory_write_log: [],
         memories: StatePart {
             value: [],
         },
@@ -417,12 +418,12 @@ Simulation {
                     name: "cd",
                     fields: [
                         TraceClock {
-                            id: TraceScalarId(0),
+                            location: TraceScalarId(0),
                             name: "clk",
                             flow: Source,
                         },
                         TraceAsyncReset {
-                            id: TraceScalarId(1),
+                            location: TraceScalarId(1),
                             name: "rst",
                             flow: Source,
                         },
@@ -446,7 +447,7 @@ Simulation {
             TraceModuleIO {
                 name: "count",
                 child: TraceUInt {
-                    id: TraceScalarId(2),
+                    location: TraceScalarId(2),
                     name: "count",
                     ty: UInt<4>,
                     flow: Sink,
@@ -457,7 +458,7 @@ Simulation {
             TraceReg {
                 name: "count_reg",
                 child: TraceUInt {
-                    id: TraceScalarId(3),
+                    location: TraceScalarId(3),
                     name: "count_reg",
                     ty: UInt<4>,
                     flow: Duplex,
@@ -502,6 +503,7 @@ Simulation {
             last_state: 0x3,
         },
     ],
+    trace_memories: {},
     trace_writers: [
         Running(
             VcdWriter {
diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt
index 30b84b2..cf425e0 100644
--- a/crates/fayalite/tests/sim/expected/counter_sync.txt
+++ b/crates/fayalite/tests/sim/expected/counter_sync.txt
@@ -150,6 +150,7 @@ Simulation {
             ..
         },
         pc: 15,
+        memory_write_log: [],
         memories: StatePart {
             value: [],
         },
@@ -398,12 +399,12 @@ Simulation {
                     name: "cd",
                     fields: [
                         TraceClock {
-                            id: TraceScalarId(0),
+                            location: TraceScalarId(0),
                             name: "clk",
                             flow: Source,
                         },
                         TraceSyncReset {
-                            id: TraceScalarId(1),
+                            location: TraceScalarId(1),
                             name: "rst",
                             flow: Source,
                         },
@@ -427,7 +428,7 @@ Simulation {
             TraceModuleIO {
                 name: "count",
                 child: TraceUInt {
-                    id: TraceScalarId(2),
+                    location: TraceScalarId(2),
                     name: "count",
                     ty: UInt<4>,
                     flow: Sink,
@@ -438,7 +439,7 @@ Simulation {
             TraceReg {
                 name: "count_reg",
                 child: TraceUInt {
-                    id: TraceScalarId(3),
+                    location: TraceScalarId(3),
                     name: "count_reg",
                     ty: UInt<4>,
                     flow: Duplex,
@@ -483,6 +484,7 @@ Simulation {
             last_state: 0x3,
         },
     ],
+    trace_memories: {},
     trace_writers: [
         Running(
             VcdWriter {
diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt
index 69c94dd..8b7f172 100644
--- a/crates/fayalite/tests/sim/expected/enums.txt
+++ b/crates/fayalite/tests/sim/expected/enums.txt
@@ -875,6 +875,7 @@ Simulation {
             ..
         },
         pc: 100,
+        memory_write_log: [],
         memories: StatePart {
             value: [],
         },
@@ -1333,12 +1334,12 @@ Simulation {
                     name: "cd",
                     fields: [
                         TraceClock {
-                            id: TraceScalarId(0),
+                            location: TraceScalarId(0),
                             name: "clk",
                             flow: Source,
                         },
                         TraceSyncReset {
-                            id: TraceScalarId(1),
+                            location: TraceScalarId(1),
                             name: "rst",
                             flow: Source,
                         },
@@ -1362,7 +1363,7 @@ Simulation {
             TraceModuleIO {
                 name: "en",
                 child: TraceBool {
-                    id: TraceScalarId(2),
+                    location: TraceScalarId(2),
                     name: "en",
                     flow: Source,
                 },
@@ -1372,7 +1373,7 @@ Simulation {
             TraceModuleIO {
                 name: "which_in",
                 child: TraceUInt {
-                    id: TraceScalarId(3),
+                    location: TraceScalarId(3),
                     name: "which_in",
                     ty: UInt<2>,
                     flow: Source,
@@ -1383,7 +1384,7 @@ Simulation {
             TraceModuleIO {
                 name: "data_in",
                 child: TraceUInt {
-                    id: TraceScalarId(4),
+                    location: TraceScalarId(4),
                     name: "data_in",
                     ty: UInt<4>,
                     flow: Source,
@@ -1394,7 +1395,7 @@ Simulation {
             TraceModuleIO {
                 name: "which_out",
                 child: TraceUInt {
-                    id: TraceScalarId(5),
+                    location: TraceScalarId(5),
                     name: "which_out",
                     ty: UInt<2>,
                     flow: Sink,
@@ -1405,7 +1406,7 @@ Simulation {
             TraceModuleIO {
                 name: "data_out",
                 child: TraceUInt {
-                    id: TraceScalarId(6),
+                    location: TraceScalarId(6),
                     name: "data_out",
                     ty: UInt<4>,
                     flow: Sink,
@@ -1418,7 +1419,7 @@ Simulation {
                 child: TraceEnumWithFields {
                     name: "the_reg",
                     discriminant: TraceEnumDiscriminant {
-                        id: TraceScalarId(7),
+                        location: TraceScalarId(7),
                         name: "$tag",
                         ty: Enum {
                             A,
@@ -1432,13 +1433,13 @@ Simulation {
                             name: "B",
                             fields: [
                                 TraceUInt {
-                                    id: TraceScalarId(8),
+                                    location: TraceScalarId(8),
                                     name: "0",
                                     ty: UInt<1>,
                                     flow: Source,
                                 },
                                 TraceBool {
-                                    id: TraceScalarId(9),
+                                    location: TraceScalarId(9),
                                     name: "1",
                                     flow: Source,
                                 },
@@ -1458,13 +1459,13 @@ Simulation {
                                     name: "a",
                                     elements: [
                                         TraceUInt {
-                                            id: TraceScalarId(10),
+                                            location: TraceScalarId(10),
                                             name: "[0]",
                                             ty: UInt<1>,
                                             flow: Source,
                                         },
                                         TraceUInt {
-                                            id: TraceScalarId(11),
+                                            location: TraceScalarId(11),
                                             name: "[1]",
                                             ty: UInt<1>,
                                             flow: Source,
@@ -1474,7 +1475,7 @@ Simulation {
                                     flow: Source,
                                 },
                                 TraceSInt {
-                                    id: TraceScalarId(12),
+                                    location: TraceScalarId(12),
                                     name: "b",
                                     ty: SInt<2>,
                                     flow: Source,
@@ -1623,6 +1624,7 @@ Simulation {
             last_state: 0x3,
         },
     ],
+    trace_memories: {},
     trace_writers: [
         Running(
             VcdWriter {
diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt
index cf15b07..82ec9ce 100644
--- a/crates/fayalite/tests/sim/expected/mod1.txt
+++ b/crates/fayalite/tests/sim/expected/mod1.txt
@@ -180,6 +180,7 @@ Simulation {
             ..
         },
         pc: 17,
+        memory_write_log: [],
         memories: StatePart {
             value: [],
         },
@@ -531,25 +532,25 @@ Simulation {
                     name: "o",
                     fields: [
                         TraceUInt {
-                            id: TraceScalarId(0),
+                            location: TraceScalarId(0),
                             name: "i",
                             ty: UInt<4>,
                             flow: Source,
                         },
                         TraceSInt {
-                            id: TraceScalarId(1),
+                            location: TraceScalarId(1),
                             name: "o",
                             ty: SInt<2>,
                             flow: Sink,
                         },
                         TraceSInt {
-                            id: TraceScalarId(2),
+                            location: TraceScalarId(2),
                             name: "i2",
                             ty: SInt<2>,
                             flow: Source,
                         },
                         TraceUInt {
-                            id: TraceScalarId(3),
+                            location: TraceScalarId(3),
                             name: "o2",
                             ty: UInt<4>,
                             flow: Sink,
@@ -585,25 +586,25 @@ Simulation {
                     name: "child",
                     fields: [
                         TraceUInt {
-                            id: TraceScalarId(8),
+                            location: TraceScalarId(8),
                             name: "i",
                             ty: UInt<4>,
                             flow: Sink,
                         },
                         TraceSInt {
-                            id: TraceScalarId(9),
+                            location: TraceScalarId(9),
                             name: "o",
                             ty: SInt<2>,
                             flow: Source,
                         },
                         TraceSInt {
-                            id: TraceScalarId(10),
+                            location: TraceScalarId(10),
                             name: "i2",
                             ty: SInt<2>,
                             flow: Sink,
                         },
                         TraceUInt {
-                            id: TraceScalarId(11),
+                            location: TraceScalarId(11),
                             name: "o2",
                             ty: UInt<4>,
                             flow: Source,
@@ -627,7 +628,7 @@ Simulation {
                         TraceModuleIO {
                             name: "i",
                             child: TraceUInt {
-                                id: TraceScalarId(4),
+                                location: TraceScalarId(4),
                                 name: "i",
                                 ty: UInt<4>,
                                 flow: Source,
@@ -638,7 +639,7 @@ Simulation {
                         TraceModuleIO {
                             name: "o",
                             child: TraceSInt {
-                                id: TraceScalarId(5),
+                                location: TraceScalarId(5),
                                 name: "o",
                                 ty: SInt<2>,
                                 flow: Sink,
@@ -649,7 +650,7 @@ Simulation {
                         TraceModuleIO {
                             name: "i2",
                             child: TraceSInt {
-                                id: TraceScalarId(6),
+                                location: TraceScalarId(6),
                                 name: "i2",
                                 ty: SInt<2>,
                                 flow: Source,
@@ -660,7 +661,7 @@ Simulation {
                         TraceModuleIO {
                             name: "o2",
                             child: TraceUInt {
-                                id: TraceScalarId(7),
+                                location: TraceScalarId(7),
                                 name: "o2",
                                 ty: UInt<4>,
                                 flow: Sink,
@@ -793,6 +794,7 @@ Simulation {
             last_state: 0xe,
         },
     ],
+    trace_memories: {},
     trace_writers: [
         Running(
             VcdWriter {
diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt
index e89351d..fac75cb 100644
--- a/crates/fayalite/tests/sim/expected/shift_register.txt
+++ b/crates/fayalite/tests/sim/expected/shift_register.txt
@@ -227,6 +227,7 @@ Simulation {
             ..
         },
         pc: 30,
+        memory_write_log: [],
         memories: StatePart {
             value: [],
         },
@@ -513,12 +514,12 @@ Simulation {
                     name: "cd",
                     fields: [
                         TraceClock {
-                            id: TraceScalarId(0),
+                            location: TraceScalarId(0),
                             name: "clk",
                             flow: Source,
                         },
                         TraceSyncReset {
-                            id: TraceScalarId(1),
+                            location: TraceScalarId(1),
                             name: "rst",
                             flow: Source,
                         },
@@ -542,7 +543,7 @@ Simulation {
             TraceModuleIO {
                 name: "d",
                 child: TraceBool {
-                    id: TraceScalarId(2),
+                    location: TraceScalarId(2),
                     name: "d",
                     flow: Source,
                 },
@@ -552,7 +553,7 @@ Simulation {
             TraceModuleIO {
                 name: "q",
                 child: TraceBool {
-                    id: TraceScalarId(3),
+                    location: TraceScalarId(3),
                     name: "q",
                     flow: Sink,
                 },
@@ -562,7 +563,7 @@ Simulation {
             TraceReg {
                 name: "reg0",
                 child: TraceBool {
-                    id: TraceScalarId(4),
+                    location: TraceScalarId(4),
                     name: "reg0",
                     flow: Duplex,
                 },
@@ -571,7 +572,7 @@ Simulation {
             TraceReg {
                 name: "reg1",
                 child: TraceBool {
-                    id: TraceScalarId(5),
+                    location: TraceScalarId(5),
                     name: "reg1",
                     flow: Duplex,
                 },
@@ -580,7 +581,7 @@ Simulation {
             TraceReg {
                 name: "reg2",
                 child: TraceBool {
-                    id: TraceScalarId(6),
+                    location: TraceScalarId(6),
                     name: "reg2",
                     flow: Duplex,
                 },
@@ -589,7 +590,7 @@ Simulation {
             TraceReg {
                 name: "reg3",
                 child: TraceBool {
-                    id: TraceScalarId(7),
+                    location: TraceScalarId(7),
                     name: "reg3",
                     flow: Duplex,
                 },
@@ -663,6 +664,7 @@ Simulation {
             last_state: 0x0,
         },
     ],
+    trace_memories: {},
     trace_writers: [
         Running(
             VcdWriter {

From 562c479b62f22ac76fe219ed775dabd54cf86b44 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 12 Dec 2024 15:06:17 -0800
Subject: [PATCH 133/190] sim/interpreter: fix StatePartLayout name in debug
 output

---
 crates/fayalite/src/sim/interpreter.rs        |  2 +-
 .../tests/sim/expected/connect_const.txt      | 10 ++--
 .../sim/expected/connect_const_reset.txt      | 14 +++---
 .../tests/sim/expected/counter_async.txt      | 30 ++++++------
 .../tests/sim/expected/counter_sync.txt       | 30 ++++++------
 crates/fayalite/tests/sim/expected/enums.txt  | 46 +++++++++----------
 crates/fayalite/tests/sim/expected/mod1.txt   | 42 ++++++++---------
 .../tests/sim/expected/shift_register.txt     | 34 +++++++-------
 8 files changed, 104 insertions(+), 104 deletions(-)

diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index e4a0570..b2b8a4b 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -1711,7 +1711,7 @@ impl<K: StatePartKind, BK: InsnsBuildingKind> fmt::Debug for StatePartLayout<K,
             layout_data,
             _phantom: _,
         } = self;
-        write!(f, "StatePartAllocationLayout<{}>", K::NAME)?;
+        write!(f, "StatePartLayout<{}>", K::NAME)?;
         let mut debug_struct = f.debug_struct("");
         debug_struct
             .field("len", &debug_data.len())
diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt
index 228e4a0..c3f8569 100644
--- a/crates/fayalite/tests/sim/expected/connect_const.txt
+++ b/crates/fayalite/tests/sim/expected/connect_const.txt
@@ -3,12 +3,12 @@ Simulation {
         insns: Insns {
             state_layout: StateLayout {
                 ty: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 2,
                         debug_data: [
                             SlotDebugData {
@@ -23,7 +23,7 @@ Simulation {
                         ..
                     },
                 },
-                memories: StatePartAllocationLayout<Memories> {
+                memories: StatePartLayout<Memories> {
                     len: 0,
                     debug_data: [],
                     layout_data: [],
@@ -80,12 +80,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<8>,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
index 2421c14..8494a13 100644
--- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt
+++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
@@ -3,12 +3,12 @@ Simulation {
         insns: Insns {
             state_layout: StateLayout {
                 ty: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 5,
                         debug_data: [
                             SlotDebugData {
@@ -35,7 +35,7 @@ Simulation {
                         ..
                     },
                 },
-                memories: StatePartAllocationLayout<Memories> {
+                memories: StatePartLayout<Memories> {
                     len: 0,
                     debug_data: [],
                     layout_data: [],
@@ -109,12 +109,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Bool,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -143,12 +143,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: AsyncReset,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt
index 104ddeb..ab379a1 100644
--- a/crates/fayalite/tests/sim/expected/counter_async.txt
+++ b/crates/fayalite/tests/sim/expected/counter_async.txt
@@ -3,7 +3,7 @@ Simulation {
         insns: Insns {
             state_layout: StateLayout {
                 ty: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 4,
                         debug_data: [
                             SlotDebugData {
@@ -25,7 +25,7 @@ Simulation {
                         ],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 10,
                         debug_data: [
                             SlotDebugData {
@@ -72,7 +72,7 @@ Simulation {
                         ..
                     },
                 },
-                memories: StatePartAllocationLayout<Memories> {
+                memories: StatePartLayout<Memories> {
                     len: 0,
                     debug_data: [],
                     layout_data: [],
@@ -219,12 +219,12 @@ Simulation {
                     rst: AsyncReset,
                 },
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 2,
                         debug_data: [
                             SlotDebugData {
@@ -249,12 +249,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: Clock,
                                 layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                    small_slots: StatePartLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                    big_slots: StatePartLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -276,12 +276,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: AsyncReset,
                                 layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                    small_slots: StatePartLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                    big_slots: StatePartLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -314,12 +314,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Clock,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -348,12 +348,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: AsyncReset,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -382,12 +382,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<4>,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt
index cf425e0..7006c1f 100644
--- a/crates/fayalite/tests/sim/expected/counter_sync.txt
+++ b/crates/fayalite/tests/sim/expected/counter_sync.txt
@@ -3,7 +3,7 @@ Simulation {
         insns: Insns {
             state_layout: StateLayout {
                 ty: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 4,
                         debug_data: [
                             SlotDebugData {
@@ -25,7 +25,7 @@ Simulation {
                         ],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 9,
                         debug_data: [
                             SlotDebugData {
@@ -68,7 +68,7 @@ Simulation {
                         ..
                     },
                 },
-                memories: StatePartAllocationLayout<Memories> {
+                memories: StatePartLayout<Memories> {
                     len: 0,
                     debug_data: [],
                     layout_data: [],
@@ -200,12 +200,12 @@ Simulation {
                     rst: SyncReset,
                 },
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 2,
                         debug_data: [
                             SlotDebugData {
@@ -230,12 +230,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: Clock,
                                 layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                    small_slots: StatePartLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                    big_slots: StatePartLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -257,12 +257,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: SyncReset,
                                 layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                    small_slots: StatePartLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                    big_slots: StatePartLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -295,12 +295,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Clock,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -329,12 +329,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: SyncReset,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -363,12 +363,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<4>,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt
index 8b7f172..f970c34 100644
--- a/crates/fayalite/tests/sim/expected/enums.txt
+++ b/crates/fayalite/tests/sim/expected/enums.txt
@@ -3,7 +3,7 @@ Simulation {
         insns: Insns {
             state_layout: StateLayout {
                 ty: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 5,
                         debug_data: [
                             SlotDebugData {
@@ -33,7 +33,7 @@ Simulation {
                         ],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 82,
                         debug_data: [
                             SlotDebugData {
@@ -388,7 +388,7 @@ Simulation {
                         ..
                     },
                 },
-                memories: StatePartAllocationLayout<Memories> {
+                memories: StatePartLayout<Memories> {
                     len: 0,
                     debug_data: [],
                     layout_data: [],
@@ -999,12 +999,12 @@ Simulation {
                     rst: SyncReset,
                 },
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 2,
                         debug_data: [
                             SlotDebugData {
@@ -1029,12 +1029,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: Clock,
                                 layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                    small_slots: StatePartLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                    big_slots: StatePartLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -1056,12 +1056,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: SyncReset,
                                 layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                    small_slots: StatePartLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                    big_slots: StatePartLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -1094,12 +1094,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Clock,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -1128,12 +1128,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: SyncReset,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -1162,12 +1162,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<4>,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -1196,12 +1196,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<4>,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -1230,12 +1230,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Bool,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -1264,12 +1264,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<2>,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -1298,12 +1298,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<2>,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt
index 82ec9ce..2625acf 100644
--- a/crates/fayalite/tests/sim/expected/mod1.txt
+++ b/crates/fayalite/tests/sim/expected/mod1.txt
@@ -3,12 +3,12 @@ Simulation {
         insns: Insns {
             state_layout: StateLayout {
                 ty: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 17,
                         debug_data: [
                             SlotDebugData {
@@ -83,7 +83,7 @@ Simulation {
                         ..
                     },
                 },
-                memories: StatePartAllocationLayout<Memories> {
+                memories: StatePartLayout<Memories> {
                     len: 0,
                     debug_data: [],
                     layout_data: [],
@@ -237,12 +237,12 @@ Simulation {
                     o2: UInt<4>,
                 },
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 4,
                         debug_data: [
                             SlotDebugData {
@@ -275,12 +275,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: UInt<4>,
                                 layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                    small_slots: StatePartLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                    big_slots: StatePartLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -302,12 +302,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: SInt<2>,
                                 layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                    small_slots: StatePartLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                    big_slots: StatePartLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -329,12 +329,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: SInt<2>,
                                 layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                    small_slots: StatePartLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                    big_slots: StatePartLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -356,12 +356,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: UInt<4>,
                                 layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                    small_slots: StatePartLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                    big_slots: StatePartLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -394,12 +394,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<4>,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -428,12 +428,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: SInt<2>,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -462,12 +462,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: SInt<2>,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -496,12 +496,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<4>,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt
index fac75cb..e33891c 100644
--- a/crates/fayalite/tests/sim/expected/shift_register.txt
+++ b/crates/fayalite/tests/sim/expected/shift_register.txt
@@ -3,7 +3,7 @@ Simulation {
         insns: Insns {
             state_layout: StateLayout {
                 ty: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 4,
                         debug_data: [
                             SlotDebugData {
@@ -25,7 +25,7 @@ Simulation {
                         ],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 13,
                         debug_data: [
                             SlotDebugData {
@@ -84,7 +84,7 @@ Simulation {
                         ..
                     },
                 },
-                memories: StatePartAllocationLayout<Memories> {
+                memories: StatePartLayout<Memories> {
                     len: 0,
                     debug_data: [],
                     layout_data: [],
@@ -281,12 +281,12 @@ Simulation {
                     rst: SyncReset,
                 },
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 2,
                         debug_data: [
                             SlotDebugData {
@@ -311,12 +311,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: Clock,
                                 layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                    small_slots: StatePartLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                    big_slots: StatePartLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -338,12 +338,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: SyncReset,
                                 layout: TypeLayout {
-                                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                                    small_slots: StatePartLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartAllocationLayout<BigSlots> {
+                                    big_slots: StatePartLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -376,12 +376,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Clock,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -410,12 +410,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: SyncReset,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -444,12 +444,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Bool,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -478,12 +478,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Bool,
                 layout: TypeLayout {
-                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                    small_slots: StatePartLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartAllocationLayout<BigSlots> {
+                    big_slots: StatePartLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {

From 8d030ac65d932896a57e55ecaf9b453f52b4fc6a Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 12 Dec 2024 16:25:38 -0800
Subject: [PATCH 134/190] sim/interpreter: add addresses to instruction listing

---
 crates/fayalite/src/sim/interpreter.rs        |   1 +
 .../tests/sim/expected/connect_const.txt      |   6 +-
 .../sim/expected/connect_const_reset.txt      |  12 +-
 .../tests/sim/expected/counter_async.txt      |  38 ++--
 .../tests/sim/expected/counter_sync.txt       |  32 +--
 crates/fayalite/tests/sim/expected/enums.txt  | 202 +++++++++---------
 crates/fayalite/tests/sim/expected/mod1.txt   |  36 ++--
 .../tests/sim/expected/shift_register.txt     |  62 +++---
 8 files changed, 195 insertions(+), 194 deletions(-)

diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index b2b8a4b..54645eb 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -565,6 +565,7 @@ impl<BK: InsnsBuildingKind> fmt::Debug for InsnDebug<'_, BK> {
         if let Some(source_location) = self.source_location {
             writeln!(f, "// at: {source_location}")?;
         }
+        write!(f, "{}: ", self.address)?;
         self.insn.debug_fmt(f, self.labels, Some(self.state_layout))
     }
 }
diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt
index c3f8569..e527678 100644
--- a/crates/fayalite/tests/sim/expected/connect_const.txt
+++ b/crates/fayalite/tests/sim/expected/connect_const.txt
@@ -32,17 +32,17 @@ Simulation {
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
-                Const {
+                0: Const {
                     dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
                     value: 5,
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                Copy {
+                1: Copy {
                     dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
                     src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                Return,
+                2: Return,
             ],
             ..
         },
diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
index 8494a13..f74dbec 100644
--- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt
+++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
@@ -44,31 +44,31 @@ Simulation {
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
-                Const {
+                0: Const {
                     dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
                     value: 1,
                 },
-                Copy {
+                1: Copy {
                     dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
                     src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
-                Copy {
+                2: Copy {
                     dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
                     src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                Copy {
+                3: Copy {
                     dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
-                Copy {
+                4: Copy {
                     dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
                     src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                Return,
+                5: Return,
             ],
             ..
         },
diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt
index ab379a1..b2bcd56 100644
--- a/crates/fayalite/tests/sim/expected/counter_async.txt
+++ b/crates/fayalite/tests/sim/expected/counter_async.txt
@@ -81,89 +81,89 @@ Simulation {
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
-                Const {
+                0: Const {
                     dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
                     value: 1,
                 },
-                Copy {
+                1: Copy {
                     dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                IsNonZeroDestIsSmall {
+                2: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                Const {
+                3: Const {
                     dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
                     value: 3,
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                BranchIfZero {
+                4: BranchIfZero {
                     target: 6,
                     value: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
                 },
-                Copy {
+                5: Copy {
                     dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                Add {
+                6: Add {
                     dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
                     lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     rhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                CastToUInt {
+                7: CastToUInt {
                     dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
                     dest_width: 4,
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
-                Copy {
+                8: Copy {
                     dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
-                Copy {
+                9: Copy {
                     dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                IsNonZeroDestIsSmall {
+                10: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
                 },
-                AndSmall {
+                11: AndSmall {
                     dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
                 },
-                BranchIfSmallNonZero {
+                12: BranchIfSmallNonZero {
                     target: 16,
                     value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                 },
-                BranchIfSmallZero {
+                13: BranchIfSmallZero {
                     target: 17,
                     value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                 },
-                Copy {
+                14: Copy {
                     dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
                 },
-                Branch {
+                15: Branch {
                     target: 17,
                 },
-                Copy {
+                16: Copy {
                     dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
                 },
-                NotSmall {
+                17: NotSmall {
                     dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                Return,
+                18: Return,
             ],
             ..
         },
diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt
index 7006c1f..1615917 100644
--- a/crates/fayalite/tests/sim/expected/counter_sync.txt
+++ b/crates/fayalite/tests/sim/expected/counter_sync.txt
@@ -77,75 +77,75 @@ Simulation {
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:6:1
-                Copy {
+                0: Copy {
                     dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                Const {
+                1: Const {
                     dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
                     value: 1,
                 },
-                Add {
+                2: Add {
                     dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
                     lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     rhs: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                CastToUInt {
+                3: CastToUInt {
                     dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
                     dest_width: 4,
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
-                Copy {
+                4: Copy {
                     dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                IsNonZeroDestIsSmall {
+                5: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                Const {
+                6: Const {
                     dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
                     value: 3,
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                IsNonZeroDestIsSmall {
+                7: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
                 },
-                AndSmall {
+                8: AndSmall {
                     dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
                 },
-                BranchIfSmallZero {
+                9: BranchIfSmallZero {
                     target: 14,
                     value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                 },
-                BranchIfSmallNonZero {
+                10: BranchIfSmallNonZero {
                     target: 13,
                     value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                 },
-                Copy {
+                11: Copy {
                     dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
                 },
-                Branch {
+                12: Branch {
                     target: 14,
                 },
-                Copy {
+                13: Copy {
                     dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
                 },
-                NotSmall {
+                14: NotSmall {
                     dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                Return,
+                15: Return,
             ],
             ..
         },
diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt
index f970c34..5f958ad 100644
--- a/crates/fayalite/tests/sim/expected/enums.txt
+++ b/crates/fayalite/tests/sim/expected/enums.txt
@@ -397,480 +397,480 @@ Simulation {
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
-                Const {
+                0: Const {
                     dest: StatePartIndex<BigSlots>(72), // SlotDebugData { name: "", ty: UInt<4> },
                     value: 0,
                 },
-                SliceInt {
+                1: SliceInt {
                     dest: StatePartIndex<BigSlots>(61), // SlotDebugData { name: "", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
                     start: 2,
                     len: 2,
                 },
-                CastToSInt {
+                2: CastToSInt {
                     dest: StatePartIndex<BigSlots>(62), // SlotDebugData { name: "", ty: SInt<2> },
                     src: StatePartIndex<BigSlots>(61), // SlotDebugData { name: "", ty: UInt<2> },
                     dest_width: 2,
                 },
-                Const {
+                3: Const {
                     dest: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
                     value: 2,
                 },
-                SliceInt {
+                4: SliceInt {
                     dest: StatePartIndex<BigSlots>(41), // SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
                     start: 1,
                     len: 1,
                 },
-                Copy {
+                5: Copy {
                     dest: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(41), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                Copy {
+                6: Copy {
                     dest: StatePartIndex<BigSlots>(60), // SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
                 },
-                SliceInt {
+                7: SliceInt {
                     dest: StatePartIndex<BigSlots>(38), // SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
                     start: 0,
                     len: 1,
                 },
-                Copy {
+                8: Copy {
                     dest: StatePartIndex<BigSlots>(39), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(38), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                Copy {
+                9: Copy {
                     dest: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(39), // SlotDebugData { name: "", ty: Bool },
                 },
-                Copy {
+                10: Copy {
                     dest: StatePartIndex<BigSlots>(36), // SlotDebugData { name: ".0", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                Copy {
+                11: Copy {
                     dest: StatePartIndex<BigSlots>(37), // SlotDebugData { name: ".1", ty: Bool },
                     src: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
                 },
-                Copy {
+                12: Copy {
                     dest: StatePartIndex<BigSlots>(58), // SlotDebugData { name: "[0]", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                Copy {
+                13: Copy {
                     dest: StatePartIndex<BigSlots>(59), // SlotDebugData { name: "[1]", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(60), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                Copy {
+                14: Copy {
                     dest: StatePartIndex<BigSlots>(55), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(58), // SlotDebugData { name: "[0]", ty: UInt<1> },
                 },
-                Copy {
+                15: Copy {
                     dest: StatePartIndex<BigSlots>(56), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(59), // SlotDebugData { name: "[1]", ty: UInt<1> },
                 },
-                Copy {
+                16: Copy {
                     dest: StatePartIndex<BigSlots>(57), // SlotDebugData { name: ".b", ty: SInt<2> },
                     src: StatePartIndex<BigSlots>(62), // SlotDebugData { name: "", ty: SInt<2> },
                 },
-                Copy {
+                17: Copy {
                     dest: StatePartIndex<BigSlots>(50), // SlotDebugData { name: ".0", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                Copy {
+                18: Copy {
                     dest: StatePartIndex<BigSlots>(51), // SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(55), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
                 },
-                Copy {
+                19: Copy {
                     dest: StatePartIndex<BigSlots>(52), // SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(56), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
                 },
-                Copy {
+                20: Copy {
                     dest: StatePartIndex<BigSlots>(53), // SlotDebugData { name: ".1.b", ty: SInt<2> },
                     src: StatePartIndex<BigSlots>(57), // SlotDebugData { name: ".b", ty: SInt<2> },
                 },
-                Shl {
+                21: Shl {
                     dest: StatePartIndex<BigSlots>(63), // SlotDebugData { name: "", ty: UInt<2> },
                     lhs: StatePartIndex<BigSlots>(52), // SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
                     rhs: 1,
                 },
-                Or {
+                22: Or {
                     dest: StatePartIndex<BigSlots>(64), // SlotDebugData { name: "", ty: UInt<2> },
                     lhs: StatePartIndex<BigSlots>(51), // SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
                     rhs: StatePartIndex<BigSlots>(63), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                CastToUInt {
+                23: CastToUInt {
                     dest: StatePartIndex<BigSlots>(65), // SlotDebugData { name: "", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(53), // SlotDebugData { name: ".1.b", ty: SInt<2> },
                     dest_width: 2,
                 },
-                Shl {
+                24: Shl {
                     dest: StatePartIndex<BigSlots>(66), // SlotDebugData { name: "", ty: UInt<4> },
                     lhs: StatePartIndex<BigSlots>(65), // SlotDebugData { name: "", ty: UInt<2> },
                     rhs: 2,
                 },
-                Or {
+                25: Or {
                     dest: StatePartIndex<BigSlots>(67), // SlotDebugData { name: "", ty: UInt<4> },
                     lhs: StatePartIndex<BigSlots>(64), // SlotDebugData { name: "", ty: UInt<2> },
                     rhs: StatePartIndex<BigSlots>(66), // SlotDebugData { name: "", ty: UInt<4> },
                 },
-                Shl {
+                26: Shl {
                     dest: StatePartIndex<BigSlots>(68), // SlotDebugData { name: "", ty: UInt<6> },
                     lhs: StatePartIndex<BigSlots>(67), // SlotDebugData { name: "", ty: UInt<4> },
                     rhs: 2,
                 },
-                Or {
+                27: Or {
                     dest: StatePartIndex<BigSlots>(69), // SlotDebugData { name: "", ty: UInt<6> },
                     lhs: StatePartIndex<BigSlots>(50), // SlotDebugData { name: ".0", ty: UInt<2> },
                     rhs: StatePartIndex<BigSlots>(68), // SlotDebugData { name: "", ty: UInt<6> },
                 },
-                CastToUInt {
+                28: CastToUInt {
                     dest: StatePartIndex<BigSlots>(70), // SlotDebugData { name: "", ty: UInt<6> },
                     src: StatePartIndex<BigSlots>(69), // SlotDebugData { name: "", ty: UInt<6> },
                     dest_width: 6,
                 },
-                Copy {
+                29: Copy {
                     dest: StatePartIndex<BigSlots>(71), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(70), // SlotDebugData { name: "", ty: UInt<6> },
                 },
-                Const {
+                30: Const {
                     dest: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
                     value: 1,
                 },
-                CmpEq {
+                31: CmpEq {
                     dest: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
                     rhs: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                Copy {
+                32: Copy {
                     dest: StatePartIndex<BigSlots>(33), // SlotDebugData { name: ".0", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                Copy {
+                33: Copy {
                     dest: StatePartIndex<BigSlots>(34), // SlotDebugData { name: ".1.0", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(36), // SlotDebugData { name: ".0", ty: UInt<1> },
                 },
-                Copy {
+                34: Copy {
                     dest: StatePartIndex<BigSlots>(35), // SlotDebugData { name: ".1.1", ty: Bool },
                     src: StatePartIndex<BigSlots>(37), // SlotDebugData { name: ".1", ty: Bool },
                 },
-                Copy {
+                35: Copy {
                     dest: StatePartIndex<BigSlots>(43), // SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(35), // SlotDebugData { name: ".1.1", ty: Bool },
                 },
-                Shl {
+                36: Shl {
                     dest: StatePartIndex<BigSlots>(44), // SlotDebugData { name: "", ty: UInt<2> },
                     lhs: StatePartIndex<BigSlots>(43), // SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 1,
                 },
-                Or {
+                37: Or {
                     dest: StatePartIndex<BigSlots>(45), // SlotDebugData { name: "", ty: UInt<2> },
                     lhs: StatePartIndex<BigSlots>(34), // SlotDebugData { name: ".1.0", ty: UInt<1> },
                     rhs: StatePartIndex<BigSlots>(44), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                Shl {
+                38: Shl {
                     dest: StatePartIndex<BigSlots>(46), // SlotDebugData { name: "", ty: UInt<4> },
                     lhs: StatePartIndex<BigSlots>(45), // SlotDebugData { name: "", ty: UInt<2> },
                     rhs: 2,
                 },
-                Or {
+                39: Or {
                     dest: StatePartIndex<BigSlots>(47), // SlotDebugData { name: "", ty: UInt<4> },
                     lhs: StatePartIndex<BigSlots>(33), // SlotDebugData { name: ".0", ty: UInt<2> },
                     rhs: StatePartIndex<BigSlots>(46), // SlotDebugData { name: "", ty: UInt<4> },
                 },
-                CastToUInt {
+                40: CastToUInt {
                     dest: StatePartIndex<BigSlots>(48), // SlotDebugData { name: "", ty: UInt<6> },
                     src: StatePartIndex<BigSlots>(47), // SlotDebugData { name: "", ty: UInt<4> },
                     dest_width: 6,
                 },
-                Copy {
+                41: Copy {
                     dest: StatePartIndex<BigSlots>(49), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(48), // SlotDebugData { name: "", ty: UInt<6> },
                 },
-                Const {
+                42: Const {
                     dest: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
                     value: 0,
                 },
-                CmpEq {
+                43: CmpEq {
                     dest: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
                     rhs: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                Copy {
+                44: Copy {
                     dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
                     src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
-                SliceInt {
+                45: SliceInt {
                     dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
                     start: 2,
                     len: 2,
                 },
-                SliceInt {
+                46: SliceInt {
                     dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
                     start: 0,
                     len: 1,
                 },
-                SliceInt {
+                47: SliceInt {
                     dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
                     start: 1,
                     len: 1,
                 },
-                Copy {
+                48: Copy {
                     dest: StatePartIndex<BigSlots>(17), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                Copy {
+                49: Copy {
                     dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: ".0", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                Copy {
+                50: Copy {
                     dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: ".1", ty: Bool },
                     src: StatePartIndex<BigSlots>(17), // SlotDebugData { name: "", ty: Bool },
                 },
-                Copy {
+                51: Copy {
                     dest: StatePartIndex<BigSlots>(73), // SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: ".1", ty: Bool },
                 },
-                Shl {
+                52: Shl {
                     dest: StatePartIndex<BigSlots>(74), // SlotDebugData { name: "", ty: UInt<2> },
                     lhs: StatePartIndex<BigSlots>(73), // SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 1,
                 },
-                Or {
+                53: Or {
                     dest: StatePartIndex<BigSlots>(75), // SlotDebugData { name: "", ty: UInt<2> },
                     lhs: StatePartIndex<BigSlots>(11), // SlotDebugData { name: ".0", ty: UInt<1> },
                     rhs: StatePartIndex<BigSlots>(74), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                CastToUInt {
+                54: CastToUInt {
                     dest: StatePartIndex<BigSlots>(76), // SlotDebugData { name: "", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(75), // SlotDebugData { name: "", ty: UInt<2> },
                     dest_width: 4,
                 },
-                SliceInt {
+                55: SliceInt {
                     dest: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
                     start: 2,
                     len: 4,
                 },
-                SliceInt {
+                56: SliceInt {
                     dest: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
                     start: 0,
                     len: 2,
                 },
-                SliceInt {
+                57: SliceInt {
                     dest: StatePartIndex<BigSlots>(25), // SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
                     start: 0,
                     len: 1,
                 },
-                SliceInt {
+                58: SliceInt {
                     dest: StatePartIndex<BigSlots>(26), // SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
                     start: 1,
                     len: 1,
                 },
-                Copy {
+                59: Copy {
                     dest: StatePartIndex<BigSlots>(21), // SlotDebugData { name: "[0]", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(25), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                Copy {
+                60: Copy {
                     dest: StatePartIndex<BigSlots>(22), // SlotDebugData { name: "[1]", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(26), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                SliceInt {
+                61: SliceInt {
                     dest: StatePartIndex<BigSlots>(27), // SlotDebugData { name: "", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
                     start: 2,
                     len: 2,
                 },
-                CastToSInt {
+                62: CastToSInt {
                     dest: StatePartIndex<BigSlots>(28), // SlotDebugData { name: "", ty: SInt<2> },
                     src: StatePartIndex<BigSlots>(27), // SlotDebugData { name: "", ty: UInt<2> },
                     dest_width: 2,
                 },
-                Copy {
+                63: Copy {
                     dest: StatePartIndex<BigSlots>(18), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(21), // SlotDebugData { name: "[0]", ty: UInt<1> },
                 },
-                Copy {
+                64: Copy {
                     dest: StatePartIndex<BigSlots>(19), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(22), // SlotDebugData { name: "[1]", ty: UInt<1> },
                 },
-                Copy {
+                65: Copy {
                     dest: StatePartIndex<BigSlots>(20), // SlotDebugData { name: ".b", ty: SInt<2> },
                     src: StatePartIndex<BigSlots>(28), // SlotDebugData { name: "", ty: SInt<2> },
                 },
-                Shl {
+                66: Shl {
                     dest: StatePartIndex<BigSlots>(77), // SlotDebugData { name: "", ty: UInt<2> },
                     lhs: StatePartIndex<BigSlots>(19), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
                     rhs: 1,
                 },
-                Or {
+                67: Or {
                     dest: StatePartIndex<BigSlots>(78), // SlotDebugData { name: "", ty: UInt<2> },
                     lhs: StatePartIndex<BigSlots>(18), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
                     rhs: StatePartIndex<BigSlots>(77), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                CastToUInt {
+                68: CastToUInt {
                     dest: StatePartIndex<BigSlots>(79), // SlotDebugData { name: "", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(20), // SlotDebugData { name: ".b", ty: SInt<2> },
                     dest_width: 2,
                 },
-                Shl {
+                69: Shl {
                     dest: StatePartIndex<BigSlots>(80), // SlotDebugData { name: "", ty: UInt<4> },
                     lhs: StatePartIndex<BigSlots>(79), // SlotDebugData { name: "", ty: UInt<2> },
                     rhs: 2,
                 },
-                Or {
+                70: Or {
                     dest: StatePartIndex<BigSlots>(81), // SlotDebugData { name: "", ty: UInt<4> },
                     lhs: StatePartIndex<BigSlots>(78), // SlotDebugData { name: "", ty: UInt<2> },
                     rhs: StatePartIndex<BigSlots>(80), // SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
-                AndBigWithSmallImmediate {
+                71: AndBigWithSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
                     lhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     rhs: 3,
                 },
                 // at: module-XXXXXXXXXX.rs:15:1
-                BranchIfSmallNeImmediate {
+                72: BranchIfSmallNeImmediate {
                     target: 75,
                     lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
                     rhs: 0,
                 },
                 // at: module-XXXXXXXXXX.rs:16:1
-                Copy {
+                73: Copy {
                     dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:17:1
-                Copy {
+                74: Copy {
                     dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(72), // SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:15:1
-                BranchIfSmallNeImmediate {
+                75: BranchIfSmallNeImmediate {
                     target: 78,
                     lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
                     rhs: 1,
                 },
                 // at: module-XXXXXXXXXX.rs:18:1
-                Copy {
+                76: Copy {
                     dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:19:1
-                Copy {
+                77: Copy {
                     dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(76), // SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:15:1
-                BranchIfSmallNeImmediate {
+                78: BranchIfSmallNeImmediate {
                     target: 81,
                     lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
                     rhs: 2,
                 },
                 // at: module-XXXXXXXXXX.rs:20:1
-                Copy {
+                79: Copy {
                     dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:21:1
-                Copy {
+                80: Copy {
                     dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(81), // SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
-                IsNonZeroDestIsSmall {
+                81: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                Const {
+                82: Const {
                     dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<6> },
                     value: 0,
                 },
-                Copy {
+                83: Copy {
                     dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<6> },
                 },
                 // at: module-XXXXXXXXXX.rs:9:1
-                BranchIfZero {
+                84: BranchIfZero {
                     target: 92,
                     value: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:10:1
-                BranchIfZero {
+                85: BranchIfZero {
                     target: 87,
                     value: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
-                Copy {
+                86: Copy {
                     dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 // at: module-XXXXXXXXXX.rs:10:1
-                BranchIfNonZero {
+                87: BranchIfNonZero {
                     target: 92,
                     value: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:12:1
-                BranchIfZero {
+                88: BranchIfZero {
                     target: 90,
                     value: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:13:1
-                Copy {
+                89: Copy {
                     dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(49), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 // at: module-XXXXXXXXXX.rs:12:1
-                BranchIfNonZero {
+                90: BranchIfNonZero {
                     target: 92,
                     value: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:14:1
-                Copy {
+                91: Copy {
                     dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(71), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
-                IsNonZeroDestIsSmall {
+                92: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock },
                 },
-                AndSmall {
+                93: AndSmall {
                     dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
                 },
-                BranchIfSmallZero {
+                94: BranchIfSmallZero {
                     target: 99,
                     value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                 },
-                BranchIfSmallNonZero {
+                95: BranchIfSmallNonZero {
                     target: 98,
                     value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                 },
-                Copy {
+                96: Copy {
                     dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
-                Branch {
+                97: Branch {
                     target: 99,
                 },
-                Copy {
+                98: Copy {
                     dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
-                NotSmall {
+                99: NotSmall {
                     dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                Return,
+                100: Return,
             ],
             ..
         },
diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt
index 2625acf..8c68108 100644
--- a/crates/fayalite/tests/sim/expected/mod1.txt
+++ b/crates/fayalite/tests/sim/expected/mod1.txt
@@ -92,90 +92,90 @@ Simulation {
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:4:1
-                Copy {
+                0: Copy {
                     dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
                     src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
                 },
-                Copy {
+                1: Copy {
                     dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:2:1
-                Copy {
+                2: Copy {
                     dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
                     src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
                 },
-                Copy {
+                3: Copy {
                     dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX-2.rs:1:1
-                Const {
+                4: Const {
                     dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
                     value: 15,
                 },
-                Const {
+                5: Const {
                     dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
                     value: 5,
                 },
-                CmpLt {
+                6: CmpLt {
                     dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
                     rhs: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
                 },
-                CastToUInt {
+                7: CastToUInt {
                     dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
                     dest_width: 4,
                 },
                 // at: module-XXXXXXXXXX-2.rs:7:1
-                Copy {
+                8: Copy {
                     dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX-2.rs:8:1
-                BranchIfZero {
+                9: BranchIfZero {
                     target: 11,
                     value: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX-2.rs:9:1
-                Copy {
+                10: Copy {
                     dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:2:1
-                Copy {
+                11: Copy {
                     dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
-                Copy {
+                12: Copy {
                     dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
                     src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX-2.rs:1:1
-                CastToSInt {
+                13: CastToSInt {
                     dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
                     src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
                     dest_width: 2,
                 },
                 // at: module-XXXXXXXXXX-2.rs:6:1
-                Copy {
+                14: Copy {
                     dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
                     src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:2:1
-                Copy {
+                15: Copy {
                     dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
                     src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
-                Copy {
+                16: Copy {
                     dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
                     src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                Return,
+                17: Return,
             ],
             ..
         },
diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt
index e33891c..007c15b 100644
--- a/crates/fayalite/tests/sim/expected/shift_register.txt
+++ b/crates/fayalite/tests/sim/expected/shift_register.txt
@@ -93,136 +93,136 @@ Simulation {
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:13:1
-                Copy {
+                0: Copy {
                     dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
                     src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:12:1
-                Copy {
+                1: Copy {
                     dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
                     src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:10:1
-                Copy {
+                2: Copy {
                     dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
                     src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
-                Copy {
+                3: Copy {
                     dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
                     src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
-                Copy {
+                4: Copy {
                     dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
                     src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
-                IsNonZeroDestIsSmall {
+                5: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                Const {
+                6: Const {
                     dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
                     value: 0,
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
-                IsNonZeroDestIsSmall {
+                7: IsNonZeroDestIsSmall {
                     dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
                 },
-                AndSmall {
+                8: AndSmall {
                     dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
                     rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
                 },
-                BranchIfSmallZero {
+                9: BranchIfSmallZero {
                     target: 14,
                     value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                 },
-                BranchIfSmallNonZero {
+                10: BranchIfSmallNonZero {
                     target: 13,
                     value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                 },
-                Copy {
+                11: Copy {
                     dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
                     src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
                 },
-                Branch {
+                12: Branch {
                     target: 14,
                 },
-                Copy {
+                13: Copy {
                     dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
                     src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:7:1
-                BranchIfSmallZero {
+                14: BranchIfSmallZero {
                     target: 19,
                     value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                 },
-                BranchIfSmallNonZero {
+                15: BranchIfSmallNonZero {
                     target: 18,
                     value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                 },
-                Copy {
+                16: Copy {
                     dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
                     src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
                 },
-                Branch {
+                17: Branch {
                     target: 19,
                 },
-                Copy {
+                18: Copy {
                     dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
                     src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:9:1
-                BranchIfSmallZero {
+                19: BranchIfSmallZero {
                     target: 24,
                     value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                 },
-                BranchIfSmallNonZero {
+                20: BranchIfSmallNonZero {
                     target: 23,
                     value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                 },
-                Copy {
+                21: Copy {
                     dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
                     src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
                 },
-                Branch {
+                22: Branch {
                     target: 24,
                 },
-                Copy {
+                23: Copy {
                     dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
                     src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
-                BranchIfSmallZero {
+                24: BranchIfSmallZero {
                     target: 29,
                     value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                 },
-                BranchIfSmallNonZero {
+                25: BranchIfSmallNonZero {
                     target: 28,
                     value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                 },
-                Copy {
+                26: Copy {
                     dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
                     src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
                 },
-                Branch {
+                27: Branch {
                     target: 29,
                 },
-                Copy {
+                28: Copy {
                     dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
                     src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
-                NotSmall {
+                29: NotSmall {
                     dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                Return,
+                30: Return,
             ],
             ..
         },

From 903ca1bf30827903608938f6993e586e13cf54ca Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 12 Dec 2024 19:47:57 -0800
Subject: [PATCH 135/190] sim: simple memory test works!

---
 crates/fayalite/src/memory.rs                 |   65 +-
 crates/fayalite/src/sim.rs                    |  168 +-
 crates/fayalite/src/sim/interpreter.rs        |  387 ++-
 crates/fayalite/tests/sim.rs                  |  111 +-
 .../tests/sim/expected/connect_const.txt      |    9 +-
 .../sim/expected/connect_const_reset.txt      |   21 +-
 .../tests/sim/expected/counter_async.txt      |   72 +-
 .../tests/sim/expected/counter_sync.txt       |   62 +-
 crates/fayalite/tests/sim/expected/enums.txt  |  412 +--
 .../fayalite/tests/sim/expected/memories.txt  | 2776 +++++++++++++++++
 .../fayalite/tests/sim/expected/memories.vcd  |  408 +++
 crates/fayalite/tests/sim/expected/mod1.txt   |   69 +-
 .../tests/sim/expected/shift_register.txt     |   96 +-
 13 files changed, 4146 insertions(+), 510 deletions(-)
 create mode 100644 crates/fayalite/tests/sim/expected/memories.txt
 create mode 100644 crates/fayalite/tests/sim/expected/memories.vcd

diff --git a/crates/fayalite/src/memory.rs b/crates/fayalite/src/memory.rs
index 4992cd6..2f0ec47 100644
--- a/crates/fayalite/src/memory.rs
+++ b/crates/fayalite/src/memory.rs
@@ -519,7 +519,12 @@ impl<Element: Type, Len: Size> fmt::Debug for Mem<Element, Len> {
         f.debug_struct("Mem")
             .field("name", scoped_name)
             .field("array_type", array_type)
-            .field("initial_value", initial_value)
+            .field(
+                "initial_value",
+                &initial_value.as_ref().map(|initial_value| {
+                    DebugMemoryData::from_bit_slice(*array_type, initial_value)
+                }),
+            )
             .field("read_latency", read_latency)
             .field("write_latency", write_latency)
             .field("read_under_write", read_under_write)
@@ -1079,3 +1084,61 @@ pub fn splat_mask<T: Type>(ty: T, value: Expr<Bool>) -> Expr<AsMask<T>> {
         )),
     }
 }
+
+pub trait DebugMemoryDataGetElement {
+    fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice;
+}
+
+impl<'a, F: ?Sized + Fn(usize, Array) -> &'a BitSlice> DebugMemoryDataGetElement for &'a F {
+    fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice {
+        self(element_index, array_type)
+    }
+}
+
+#[derive(Clone)]
+pub struct DebugMemoryData<GetElement: DebugMemoryDataGetElement> {
+    pub array_type: Array,
+    pub get_element: GetElement,
+}
+
+impl DebugMemoryDataGetElement for &'_ BitSlice {
+    fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice {
+        assert!(element_index < array_type.len());
+        let stride = array_type.element().bit_width();
+        let start = element_index
+            .checked_mul(stride)
+            .expect("memory is too big");
+        let end = start.checked_add(stride).expect("memory is too big");
+        &self[start..end]
+    }
+}
+
+impl<'a> DebugMemoryData<&'a BitSlice> {
+    pub fn from_bit_slice<T: Type, Depth: Size>(
+        array_type: ArrayType<T, Depth>,
+        bit_slice: &'a BitSlice,
+    ) -> Self {
+        let array_type = array_type.as_dyn_array();
+        assert_eq!(bit_slice.len(), array_type.type_properties().bit_width);
+        Self {
+            array_type,
+            get_element: bit_slice,
+        }
+    }
+}
+
+impl<GetElement: DebugMemoryDataGetElement> fmt::Debug for DebugMemoryData<GetElement> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        if self.array_type.len() == 0 {
+            return f.write_str("[]");
+        }
+        writeln!(f, "[\n    // len = {:#x}", self.array_type.len())?;
+        for element_index in 0..self.array_type.len() {
+            let element = crate::util::BitSliceWriteWithBase(
+                self.get_element.get_element(element_index, self.array_type),
+            );
+            writeln!(f, "    [{element_index:#x}]: {element:#x},")?;
+        }
+        f.write_str("]")
+    }
+}
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 731f469..a2b9648 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -26,12 +26,13 @@ use crate::{
     reset::{ResetType, ResetTypeDispatch},
     sim::{
         interpreter::{
-            Insn, InsnField, InsnFieldKind, InsnFieldType, InsnOrLabel, Insns, InsnsBuilding,
-            InsnsBuildingDone, InsnsBuildingKind, Label, SlotDebugData, SmallUInt, State,
-            StatePartArrayIndex, StatePartArrayIndexed, StatePartIndex, StatePartIndexRange,
-            StatePartKind, StatePartKindBigSlots, StatePartKindMemories, StatePartKindSmallSlots,
-            StatePartLayout, StatePartLen, StatePartsValue, TypeArrayIndex, TypeArrayIndexes,
-            TypeIndex, TypeIndexRange, TypeLayout, TypeLen, TypeParts,
+            BreakAction, BreakpointsSet, Insn, InsnField, InsnFieldKind, InsnFieldType,
+            InsnOrLabel, Insns, InsnsBuilding, InsnsBuildingDone, InsnsBuildingKind, Label,
+            MemoryData, RunResult, SlotDebugData, SmallUInt, State, StatePartArrayIndex,
+            StatePartArrayIndexed, StatePartIndex, StatePartIndexRange, StatePartKind,
+            StatePartKindBigSlots, StatePartKindMemories, StatePartKindSmallSlots, StatePartLayout,
+            StatePartLen, StatePartsValue, TypeArrayIndex, TypeArrayIndexes, TypeIndex,
+            TypeIndexRange, TypeLayout, TypeLen, TypeParts,
         },
         time::{SimDuration, SimInstant},
     },
@@ -4274,12 +4275,15 @@ impl Compiler {
             .memories
             .allocate(&StatePartLayout::scalar(
                 (),
-                mem.initial_value().unwrap_or_else(|| {
-                    Intern::intern_owned(BitVec::repeat(
-                        false,
-                        mem.array_type().type_properties().bit_width,
-                    ))
-                }),
+                MemoryData {
+                    array_type: mem.array_type(),
+                    data: mem.initial_value().unwrap_or_else(|| {
+                        Intern::intern_owned(BitVec::repeat(
+                            false,
+                            mem.array_type().type_properties().bit_width,
+                        ))
+                    }),
+                },
             ))
             .start;
         let (ports, trace_ports) = mem
@@ -4765,9 +4769,10 @@ impl Compiler {
                      source_location,
                  }| {
                     self.insns.push(
-                        Insn::NotSmall {
+                        Insn::XorSmallImmediate {
                             dest: last_clk_was_low,
-                            src: clk,
+                            lhs: clk,
+                            rhs: 1,
                         },
                         source_location,
                     );
@@ -4857,14 +4862,6 @@ impl Compiler {
             } in mem::take(ports)
             {
                 let port_end = self.insns.new_label();
-                self.insns.push(
-                    Insn::BranchIfSmallZero {
-                        target: port_end.0,
-                        value: clk_triggered,
-                    },
-                    mem.source_location(),
-                );
-                self.insns.extend(write_insns, mem.source_location());
                 let small_shift_reg =
                     |this: &mut Self, values: &[StatePartIndex<StatePartKindSmallSlots>]| {
                         for pair in values.windows(2).rev() {
@@ -4883,12 +4880,20 @@ impl Compiler {
                             .extend(pair[0].insns_for_copy_to(pair[1]), mem.source_location());
                     }
                 };
+                self.insns.push(
+                    Insn::BranchIfSmallZero {
+                        target: port_end.0,
+                        value: clk_triggered,
+                    },
+                    mem.source_location(),
+                );
                 small_shift_reg(self, &addr_delayed);
                 small_shift_reg(self, &en_delayed);
-                shift_reg(self, &read_data_delayed);
                 shift_reg(self, &write_data_delayed);
                 shift_reg(self, &write_mask_delayed);
                 small_shift_reg(self, &write_mode_delayed);
+                shift_reg(self, &read_data_delayed);
+                self.insns.extend(write_insns, mem.source_location());
                 self.insns.define_label_at_next_insn(port_end);
             }
         }
@@ -5814,9 +5819,50 @@ struct SimulationImpl {
     trace_writers: Vec<TraceWriterState<DynTraceWriterDecls>>,
     instant: SimInstant,
     clocks_triggered: Interned<[StatePartIndex<StatePartKindSmallSlots>]>,
+    breakpoints: Option<BreakpointsSet>,
+}
+
+impl fmt::Debug for SimulationImpl {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.debug_fmt(None, f)
+    }
 }
 
 impl SimulationImpl {
+    fn debug_fmt(&self, io: Option<&dyn fmt::Debug>, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            state,
+            io: self_io,
+            uninitialized_inputs,
+            io_targets,
+            made_initial_step,
+            needs_settle,
+            trace_decls,
+            traces,
+            trace_memories,
+            trace_writers,
+            instant,
+            clocks_triggered,
+            breakpoints: _,
+        } = self;
+        f.debug_struct("Simulation")
+            .field("state", state)
+            .field("io", io.unwrap_or(self_io))
+            .field(
+                "uninitialized_inputs",
+                &SortedSetDebug(uninitialized_inputs),
+            )
+            .field("io_targets", &SortedMapDebug(io_targets))
+            .field("made_initial_step", made_initial_step)
+            .field("needs_settle", needs_settle)
+            .field("trace_decls", trace_decls)
+            .field("traces", traces)
+            .field("trace_memories", trace_memories)
+            .field("trace_writers", trace_writers)
+            .field("instant", instant)
+            .field("clocks_triggered", clocks_triggered)
+            .finish_non_exhaustive()
+    }
     fn parse_io(&mut self, target: Target, value: CompiledValue<CanonicalType>) {
         self.io_targets.insert(target, value);
         match value.layout.body {
@@ -5876,6 +5922,7 @@ impl SimulationImpl {
             trace_writers: vec![],
             instant: SimInstant::START,
             clocks_triggered: compiled.clocks_triggered,
+            breakpoints: None,
         };
         let io_target = Target::from(compiled.io);
         for (BundleField { name, .. }, value) in compiled
@@ -5905,7 +5952,7 @@ impl SimulationImpl {
             trace_writer.set_memory_element(
                 self.trace_memories[&memory].id,
                 element_index,
-                &self.state.memories[memory][start..end],
+                &self.state.memories[memory].data[start..end],
             )
         };
         if ONLY_IF_CHANGED {
@@ -6054,7 +6101,30 @@ impl SimulationImpl {
                 return;
             }
             self.state.setup_call(0);
-            self.state.run();
+            if self.breakpoints.is_some() {
+                loop {
+                    match self
+                        .state
+                        .run(self.breakpoints.as_mut().expect("just checked"))
+                    {
+                        RunResult::Break(break_action) => {
+                            println!(
+                                "hit breakpoint at:\n{:?}",
+                                self.state.debug_insn_at(self.state.pc),
+                            );
+                            match break_action {
+                                BreakAction::DumpStateAndContinue => {
+                                    println!("{self:#?}");
+                                }
+                                BreakAction::Continue => {}
+                            }
+                        }
+                        RunResult::Return(()) => break,
+                    }
+                }
+            } else {
+                let RunResult::Return(()) = self.state.run(());
+            }
             if self.made_initial_step {
                 self.read_traces::<false>();
             } else {
@@ -6097,7 +6167,7 @@ impl SimulationImpl {
         if Some(&target) == self.io.target().as_deref()
             || Some(target.base()) != self.io.target().map(|v| v.base())
         {
-            panic!("simulator read/write expression must be an array element/field of `Simulator::io()`");
+            panic!("simulator read/write expression must be an array element/field of `Simulation::io()`");
         };
         panic!("simulator read/write expression must not have dynamic array indexes");
     }
@@ -6361,41 +6431,8 @@ impl<K: fmt::Debug, V: fmt::Debug> fmt::Debug for SortedMapDebug<'_, K, V> {
 
 impl<T: BundleType> fmt::Debug for Simulation<T> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        let Self {
-            sim_impl:
-                SimulationImpl {
-                    state,
-                    io: _,
-                    uninitialized_inputs,
-                    io_targets,
-                    made_initial_step,
-                    needs_settle,
-                    trace_decls,
-                    traces,
-                    trace_memories,
-                    trace_writers,
-                    instant,
-                    clocks_triggered,
-                },
-            io,
-        } = self;
-        f.debug_struct("Simulation")
-            .field("state", state)
-            .field("io", io)
-            .field(
-                "uninitialized_inputs",
-                &SortedSetDebug(uninitialized_inputs),
-            )
-            .field("io_targets", &SortedMapDebug(io_targets))
-            .field("made_initial_step", made_initial_step)
-            .field("needs_settle", needs_settle)
-            .field("trace_decls", trace_decls)
-            .field("traces", traces)
-            .field("trace_memories", trace_memories)
-            .field("trace_writers", trace_writers)
-            .field("instant", instant)
-            .field("clocks_triggered", clocks_triggered)
-            .finish()
+        let Self { sim_impl, io } = self;
+        sim_impl.debug_fmt(Some(io), f)
     }
 }
 
@@ -6488,4 +6525,13 @@ impl<T: BundleType> Simulation<T> {
     pub fn read_reset<R: ResetType>(&mut self, io: Expr<R>) -> bool {
         self.sim_impl.read_bit(Expr::canonical(io))
     }
+    #[doc(hidden)]
+    /// This is explicitly unstable and may be changed/removed at any time
+    pub fn set_breakpoints_unstable(&mut self, pcs: HashSet<usize>, trace: bool) {
+        self.sim_impl.breakpoints = Some(BreakpointsSet {
+            last_was_break: false,
+            set: pcs,
+            trace,
+        });
+    }
 }
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index 54645eb..22f6f5f 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -2,6 +2,7 @@
 // See Notices.txt for copyright information
 
 use crate::{
+    array::Array,
     int::{BoolOrIntType, SInt, UInt},
     intern::{Intern, Interned, Memoize},
     source_location::SourceLocation,
@@ -9,17 +10,17 @@ use crate::{
     util::get_many_mut,
 };
 use bitvec::{boxed::BitBox, slice::BitSlice};
-use hashbrown::HashMap;
+use hashbrown::{HashMap, HashSet};
 use num_bigint::BigInt;
 use num_traits::{One, Signed, ToPrimitive, Zero};
 use std::{
     any::TypeId,
     borrow::BorrowMut,
     convert::Infallible,
-    fmt,
+    fmt::{self, Write},
     hash::{Hash, Hasher},
     marker::PhantomData,
-    ops::{Deref, DerefMut, Index, IndexMut},
+    ops::{ControlFlow, Deref, DerefMut, Index, IndexMut},
 };
 use vec_map::VecMap;
 
@@ -174,7 +175,37 @@ fn make_array_into_iter<T, const I: usize, const N: usize>(
 
 impl fmt::Debug for Insn {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.debug_fmt::<InsnsBuildingDone>(f, None, None)
+        self.debug_fmt::<InsnsBuildingDone>(f, None, None, None)
+    }
+}
+
+struct PrefixLinesWrapper<'a, W> {
+    writer: W,
+    at_beginning_of_line: bool,
+    blank_line_prefix: &'a str,
+    line_prefix: &'a str,
+}
+
+impl<T: fmt::Write> fmt::Write for PrefixLinesWrapper<'_, T> {
+    fn write_str(&mut self, input: &str) -> fmt::Result {
+        for part in input.split_inclusive('\n') {
+            if part.is_empty() {
+                continue;
+            }
+            if self.at_beginning_of_line {
+                let prefix = match part {
+                    "\n" => self.blank_line_prefix,
+                    _ => self.line_prefix,
+                };
+                if !prefix.is_empty() {
+                    self.writer.write_str(prefix)?;
+                }
+                self.at_beginning_of_line = false;
+            }
+            self.writer.write_str(part)?;
+            self.at_beginning_of_line = part.ends_with('\n');
+        }
+        Ok(())
     }
 }
 
@@ -184,15 +215,22 @@ impl Insn {
         f: &mut fmt::Formatter<'_>,
         labels: Option<&Labels>,
         state_layout: Option<&StateLayout<BK>>,
+        state: Option<&State>,
     ) -> fmt::Result {
         let (insn_name, fields) = self.fields_with_names();
         write!(f, "{insn_name}")?;
         if fields.len() == 0 {
             return Ok(());
         }
+        let mut f = PrefixLinesWrapper {
+            writer: f,
+            at_beginning_of_line: false,
+            blank_line_prefix: "",
+            line_prefix: "    ",
+        };
         writeln!(f, " {{")?;
         for (field_name, field) in fields {
-            write!(f, "    {field_name}: ")?;
+            write!(f, "{field_name}: ")?;
             match field.kind {
                 InsnFieldKind::BranchTarget => match field.ty {
                     InsnFieldType::USize(&label_index) => {
@@ -227,35 +265,100 @@ impl Insn {
                 | InsnFieldKind::Output
                 | InsnFieldKind::Immediate => {}
             }
+            macro_rules! debug_fmt_state_part {
+                ($v:expr) => {
+                    $v.debug_fmt(&mut f, ",", " // ", "        // ", "", state_layout, state)
+                };
+            }
             match field.ty {
                 InsnFieldType::Memory(v) => {
-                    v.debug_fmt(f, ",", " // ", "", state_layout)?;
+                    debug_fmt_state_part!(v)?;
                 }
                 InsnFieldType::SmallSlot(v) => {
-                    v.debug_fmt(f, ",", " // ", "", state_layout)?;
+                    debug_fmt_state_part!(v)?;
                 }
                 InsnFieldType::BigSlot(v) => {
-                    v.debug_fmt(f, ",", " // ", "", state_layout)?;
+                    debug_fmt_state_part!(v)?;
                 }
                 InsnFieldType::SmallSlotArrayIndexed(v) => {
-                    v.debug_fmt(f, ",", " // ", "", state_layout)?;
+                    debug_fmt_state_part!(v)?;
                 }
                 InsnFieldType::BigSlotArrayIndexed(v) => {
-                    v.debug_fmt(f, ",", " // ", "", state_layout)?;
+                    debug_fmt_state_part!(v)?;
                 }
-                InsnFieldType::SmallUInt(v) => fmt::Debug::fmt(v, f)?,
-                InsnFieldType::SmallSInt(v) => fmt::Debug::fmt(v, f)?,
-                InsnFieldType::InternedBigInt(v) => fmt::Debug::fmt(v, f)?,
-                InsnFieldType::U8(v) => fmt::Debug::fmt(v, f)?,
-                InsnFieldType::USize(v) => fmt::Debug::fmt(v, f)?,
-                InsnFieldType::Empty(v) => fmt::Debug::fmt(v, f)?,
+                InsnFieldType::SmallUInt(v) => write!(f, "{v:#x}")?,
+                InsnFieldType::SmallSInt(v) => write!(f, "{v:#x}")?,
+                InsnFieldType::InternedBigInt(v) => write!(f, "{v:#x}")?,
+                InsnFieldType::U8(v) => write!(f, "{v:#x}")?,
+                InsnFieldType::USize(v) => write!(f, "{v}")?,
+                InsnFieldType::Empty(v) => write!(f, "{v:?}")?,
             }
             writeln!(f, ",")?;
         }
-        write!(f, "}}")
+        write!(f.writer, "}}")
     }
 }
 
+pub(crate) trait Breakpoints {
+    type Break;
+    fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break>;
+}
+
+impl<T: ?Sized + Breakpoints> Breakpoints for &'_ mut T {
+    type Break = T::Break;
+    fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break> {
+        T::check_for_breakpoint(self, pc)
+    }
+}
+
+impl<T: ?Sized + Breakpoints> Breakpoints for Box<T> {
+    type Break = T::Break;
+    fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break> {
+        T::check_for_breakpoint(self, pc)
+    }
+}
+
+impl Breakpoints for () {
+    type Break = Infallible;
+    fn check_for_breakpoint(&mut self, _pc: usize) -> ControlFlow<Self::Break> {
+        ControlFlow::Continue(())
+    }
+}
+
+pub(crate) struct BreakpointsSet {
+    pub(crate) last_was_break: bool,
+    pub(crate) set: HashSet<usize>,
+    pub(crate) trace: bool,
+}
+
+#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)]
+pub(crate) enum BreakAction {
+    DumpStateAndContinue,
+    Continue,
+}
+
+impl Breakpoints for BreakpointsSet {
+    type Break = BreakAction;
+    fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break> {
+        let retval = if self.last_was_break {
+            ControlFlow::Continue(())
+        } else if self.set.contains(&pc) {
+            ControlFlow::Break(BreakAction::DumpStateAndContinue)
+        } else if self.trace {
+            ControlFlow::Break(BreakAction::Continue)
+        } else {
+            ControlFlow::Continue(())
+        };
+        self.last_was_break = retval.is_break();
+        retval
+    }
+}
+
+pub(crate) enum RunResult<Break, Return> {
+    Break(Break),
+    Return(Return),
+}
+
 macro_rules! impl_insns {
     (
         #[insn = $Insn:ident, next_macro = $next_macro:ident, branch_macro = $branch_macro:ident]
@@ -402,11 +505,14 @@ macro_rules! impl_insns {
         }
 
         impl $State {
-            $vis fn $run(&mut $self) -> $run_ret_ty {
+            $vis fn $run<B: Breakpoints>(&mut $self, mut breakpoints: B) -> RunResult<B::Break, $run_ret_ty> {
                 let mut $state = $state_init;
                 $($setup)*
                 let mut insn = $state.insns[$state.pc];
                 let retval = 'main_loop: loop {
+                    if let ControlFlow::Break(b) = breakpoints.check_for_breakpoint($state.pc) {
+                        break RunResult::Break(b);
+                    }
                     macro_rules! $next_macro {
                         () => {
                             $state.pc += 1;
@@ -542,6 +648,7 @@ struct InsnsDebug<'a, BK: InsnsBuildingKind> {
     insn_source_locations: &'a [SourceLocation],
     labels: &'a BK::Labels,
     state_layout: &'a StateLayout<BK>,
+    state: Option<&'a State>,
 }
 
 struct InsnDebug<'a, BK: InsnsBuildingKind> {
@@ -550,6 +657,7 @@ struct InsnDebug<'a, BK: InsnsBuildingKind> {
     insn: &'a Insn,
     labels: Option<&'a Labels>,
     state_layout: &'a StateLayout<BK>,
+    state: Option<&'a State>,
 }
 
 impl<BK: InsnsBuildingKind> fmt::Debug for InsnDebug<'_, BK> {
@@ -566,7 +674,8 @@ impl<BK: InsnsBuildingKind> fmt::Debug for InsnDebug<'_, BK> {
             writeln!(f, "// at: {source_location}")?;
         }
         write!(f, "{}: ", self.address)?;
-        self.insn.debug_fmt(f, self.labels, Some(self.state_layout))
+        self.insn
+            .debug_fmt(f, self.labels, Some(self.state_layout), self.state)
     }
 }
 
@@ -591,6 +700,7 @@ impl<'a, BK: InsnsBuildingKind> fmt::Debug for InsnsDebug<'a, BK> {
                 insn,
                 labels,
                 state_layout: self.state_layout,
+                state: self.state,
             });
             last_source_location = Some(source_location);
         }
@@ -598,8 +708,45 @@ impl<'a, BK: InsnsBuildingKind> fmt::Debug for InsnsDebug<'a, BK> {
     }
 }
 
-impl<BK: InsnsBuildingKind> fmt::Debug for Insns<BK> {
+impl<BK: InsnsBuildingKind> Insns<BK> {
+    pub(crate) fn debug_insn_at<'a>(
+        &'a self,
+        address: usize,
+        state: Option<&'a State>,
+    ) -> impl fmt::Debug + 'a {
+        let Self {
+            insns,
+            insn_source_locations,
+            labels,
+            state_layout,
+        } = self;
+        InsnDebug {
+            address,
+            source_location: Some(insn_source_locations[address]),
+            insn: &insns[address],
+            labels: BK::labels(labels),
+            state_layout,
+            state,
+        }
+    }
+}
+
+impl State {
+    pub(crate) fn debug_insn_at(&self, address: usize) -> impl fmt::Debug + '_ {
+        self.insns.debug_insn_at(address, Some(self))
+    }
+}
+
+struct InsnsOfState<'a>(&'a State);
+
+impl fmt::Debug for InsnsOfState<'_> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.0.insns.debug_fmt(Some(self.0), f)
+    }
+}
+
+impl<BK: InsnsBuildingKind> Insns<BK> {
+    fn debug_fmt(&self, state: Option<&State>, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
             insns,
             insn_source_locations,
@@ -615,12 +762,19 @@ impl<BK: InsnsBuildingKind> fmt::Debug for Insns<BK> {
                     insn_source_locations,
                     labels,
                     state_layout,
+                    state,
                 },
             )
             .finish_non_exhaustive()
     }
 }
 
+impl<BK: InsnsBuildingKind> fmt::Debug for Insns<BK> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.debug_fmt(None, f)
+    }
+}
+
 pub(crate) trait StatePartKind:
     Send + Sync + Ord + Hash + fmt::Debug + 'static + Copy + Default
 {
@@ -635,6 +789,11 @@ pub(crate) trait StatePartKind:
         state_layout: &StateLayout<BK>,
         part_index: StatePartIndex<Self>,
     ) -> Option<&Self::DebugData>;
+    fn debug_fmt_state_value(
+        state: &State,
+        index: StatePartIndex<Self>,
+        f: &mut impl fmt::Write,
+    ) -> fmt::Result;
 }
 
 pub(crate) trait StatePartsValue {
@@ -987,7 +1146,6 @@ macro_rules! make_state_part_kinds {
             }
         }
 
-        #[derive(Debug)]
         pub(crate) struct State {
             pub(crate) insns: Interned<Insns<InsnsBuildingDone>>,
             pub(crate) pc: usize,
@@ -996,6 +1154,25 @@ macro_rules! make_state_part_kinds {
             $(pub(crate) $type_field: StatePart<$TypeKind>,)*
         }
 
+        impl fmt::Debug for State {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                let Self {
+                    insns: _,
+                    pc,
+                    memory_write_log,
+                    $($state_field,)*
+                    $($type_field,)*
+                } = self;
+                f.debug_struct("State")
+                    .field("insns", &InsnsOfState(self))
+                    .field("pc", pc)
+                    .field("memory_write_log", memory_write_log)
+                    $(.field(stringify!($state_field), $state_field))*
+                    $(.field(stringify!($type_field), $type_field))*
+                    .finish()
+            }
+        }
+
         impl State {
             pub(crate) fn new(insns: Interned<Insns<InsnsBuildingDone>>) -> Self {
                 Self {
@@ -1199,6 +1376,25 @@ macro_rules! make_state_part_kinds {
     };
 }
 
+#[derive(Copy, Clone, Hash, PartialEq, Eq)]
+pub(crate) struct MemoryData<T: Deref<Target = BitSlice>> {
+    pub(crate) array_type: Array,
+    pub(crate) data: T,
+}
+
+impl<T: Deref<Target = BitSlice>> fmt::Debug for MemoryData<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self { array_type, data } = self;
+        f.debug_struct("MemoryData")
+            .field("array_type", array_type)
+            .field(
+                "data",
+                &crate::memory::DebugMemoryData::from_bit_slice(*array_type, data),
+            )
+            .finish()
+    }
+}
+
 make_state_part_kinds! {
     /*#[state, field = small_stack]
     impl StatePartKind for StatePartKindSmallStack {
@@ -1244,11 +1440,14 @@ make_state_part_kinds! {
     impl StatePartKind for StatePartKindMemories {
         const NAME: &'static str = "Memories";
         type DebugData = ();
-        type LayoutData = Interned<BitSlice>;
-        type State = Box<[BitBox]>;
-        type BorrowedState<'a> = &'a mut [BitBox];
+        type LayoutData = MemoryData<Interned<BitSlice>>;
+        type State = Box<[MemoryData<BitBox>]>;
+        type BorrowedState<'a> = &'a mut [MemoryData<BitBox>];
         fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
-            layout_data.iter().map(|initial_data| BitBox::from_bitslice(initial_data)).collect()
+            layout_data.iter().map(|MemoryData { array_type, data }| MemoryData {
+                array_type: *array_type,
+                data: BitBox::from_bitslice(data),
+            }).collect()
         }
         fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
             state
@@ -1259,6 +1458,13 @@ make_state_part_kinds! {
         ) -> Option<&Self::DebugData> {
             state_layout.memories.debug_data.get(part_index.as_usize())
         }
+        fn debug_fmt_state_value(
+            state: &State,
+            index: StatePartIndex<Self>,
+            f: &mut impl fmt::Write,
+        ) -> fmt::Result {
+            write!(f, "{:#?}", &state.memories[index])
+        }
     }
     #[type, field = small_slots]
     impl StatePartKind for StatePartKindSmallSlots {
@@ -1279,6 +1485,15 @@ make_state_part_kinds! {
         ) -> Option<&Self::DebugData> {
             state_layout.ty.small_slots.debug_data.get(part_index.as_usize())
         }
+        fn debug_fmt_state_value(
+            state: &State,
+            index: StatePartIndex<Self>,
+            f: &mut impl fmt::Write,
+        ) -> fmt::Result {
+            let value = state.small_slots[index];
+            write!(f, "{value:#x} {}", value as SmallSInt)?;
+            Ok(())
+        }
     }
     #[type, field = big_slots]
     impl StatePartKind for StatePartKindBigSlots {
@@ -1299,6 +1514,13 @@ make_state_part_kinds! {
         ) -> Option<&Self::DebugData> {
             state_layout.ty.big_slots.debug_data.get(part_index.as_usize())
         }
+        fn debug_fmt_state_value(
+            state: &State,
+            index: StatePartIndex<Self>,
+            f: &mut impl fmt::Write,
+        ) -> fmt::Result {
+            write!(f, "{:#x}", state.big_slots[index])
+        }
     }
 }
 
@@ -1474,37 +1696,32 @@ pub(crate) struct StatePartArrayIndexed<K: StatePartKind> {
 impl<K: StatePartKind> StatePartArrayIndexed<K> {
     pub(crate) fn debug_fmt<BK: InsnsBuildingKind>(
         &self,
-        f: &mut fmt::Formatter<'_>,
+        f: &mut impl fmt::Write,
         before_debug_info_text: &str,
         comment_start: &str,
+        comment_line_start: &str,
         comment_end: &str,
         state_layout: Option<&StateLayout<BK>>,
+        state: Option<&State>,
     ) -> fmt::Result {
-        if let Some(state_layout) = state_layout {
-            let Self { base, indexes } = *self;
-            if indexes.is_empty() {
-                base.debug_fmt(
-                    f,
-                    before_debug_info_text,
-                    comment_start,
-                    comment_end,
-                    Some(state_layout),
-                )
-            } else {
-                base.debug_fmt(f, "", " /* ", " */ ", Some(state_layout))?;
-                for StatePartArrayIndex { index, len, stride } in indexes {
-                    f.write_str("[")?;
-                    index.debug_fmt(f, "", " /* ", " */ ", Some(state_layout))?;
-                    write!(f, ", len={len}, stride={}]", stride.value)?;
-                }
-                f.write_str(before_debug_info_text)
-            }
+        let Self { base, indexes } = *self;
+        if indexes.is_empty() {
+            base.debug_fmt(
+                f,
+                before_debug_info_text,
+                comment_start,
+                comment_line_start,
+                comment_end,
+                state_layout,
+                state,
+            )
         } else {
-            let Self { base, indexes } = self;
-            f.debug_struct("StatePartArrayIndexed")
-                .field("base", base)
-                .field("indexes", indexes)
-                .finish()?;
+            base.debug_fmt(f, "", " /* ", "", " */ ", state_layout, state)?;
+            for StatePartArrayIndex { index, len, stride } in indexes {
+                f.write_str("[")?;
+                index.debug_fmt(f, "", " /* ", "", " */ ", state_layout, state)?;
+                write!(f, ", len={len}, stride={}]", stride.value)?;
+            }
             f.write_str(before_debug_info_text)
         }
     }
@@ -1512,7 +1729,7 @@ impl<K: StatePartKind> StatePartArrayIndexed<K> {
 
 impl<K: StatePartKind + fmt::Debug> fmt::Debug for StatePartArrayIndexed<K> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", None)
+        self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", "", None, None)
     }
 }
 
@@ -1579,18 +1796,40 @@ impl<K: StatePartKind> StatePartIndex<K> {
     }
     pub(crate) fn debug_fmt<BK: InsnsBuildingKind>(
         &self,
-        f: &mut fmt::Formatter<'_>,
+        f: &mut impl fmt::Write,
         before_debug_info_text: &str,
         comment_start: &str,
+        comment_line_start: &str,
         comment_end: &str,
         state_layout: Option<&StateLayout<BK>>,
+        state: Option<&State>,
     ) -> fmt::Result {
         write!(f, "StatePartIndex<{}>({})", K::NAME, self.value)?;
         f.write_str(before_debug_info_text)?;
-        if let Some(state_layout) = state_layout {
-            if let Some(debug_data) = K::part_debug_data(state_layout, *self) {
-                write!(f, "{comment_start}{debug_data:?}{comment_end}")?;
-            }
+        let debug_data =
+            state_layout.and_then(|state_layout| K::part_debug_data(state_layout, *self));
+        if state.is_some() || debug_data.is_some() {
+            f.write_str(comment_start)?;
+        }
+        let mut f = PrefixLinesWrapper {
+            writer: f,
+            at_beginning_of_line: false,
+            blank_line_prefix: comment_line_start.trim_end(),
+            line_prefix: comment_line_start,
+        };
+        if let Some(state) = state {
+            f.write_str("(")?;
+            K::debug_fmt_state_value(state, *self, &mut f)?;
+            f.write_str(")")?;
+        }
+        if state.is_some() && debug_data.is_some() {
+            f.write_str(" ")?;
+        }
+        if let Some(debug_data) = debug_data {
+            write!(f, "{debug_data:?}")?;
+        }
+        if state.is_some() || debug_data.is_some() {
+            f.writer.write_str(comment_end)?;
         }
         Ok(())
     }
@@ -1598,7 +1837,7 @@ impl<K: StatePartKind> StatePartIndex<K> {
 
 impl<K: StatePartKind> fmt::Debug for StatePartIndex<K> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", None)
+        self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", "", None, None)
     }
 }
 
@@ -2182,7 +2421,7 @@ impl BorrowedState<'_> {
         let Ok(addr) = usize::try_from(addr) else {
             return;
         };
-        if addr < self.memories.value.len() {
+        if addr < self.memories[memory].array_type.len() {
             let log_entry = (memory, addr);
             if self.memory_write_log.last().copied() == Some(log_entry) {
                 return;
@@ -2521,6 +2760,18 @@ impl_insns! {
         state.big_slots[dest] = value;
         next!();
     }
+    XorSmallImmediate {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        lhs: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Immediate]
+        rhs: SmallUInt,
+    } => {
+        let value = state.small_slots[lhs] ^ rhs;
+        state.small_slots[dest] = value;
+        next!();
+    }
     NotS {
         #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,
@@ -2543,16 +2794,6 @@ impl_insns! {
         state.big_slots[dest] = value;
         next!();
     }
-    NotSmall {
-        #[kind = Output]
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        #[kind = Input]
-        src: StatePartIndex<StatePartKindSmallSlots>,
-    } => {
-        let value = !state.small_slots[src];
-        state.small_slots[dest] = value;
-        next!();
-    }
     Neg {
         #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,
@@ -2879,7 +3120,7 @@ impl_insns! {
         width: usize,
     } => {
         let addr = state.small_slots[addr];
-        state.big_slots[dest] = memory_read_big::<UInt>(&mut state.memories[memory], addr, stride, start, width).unwrap_or_default();
+        state.big_slots[dest] = memory_read_big::<UInt>(&mut state.memories[memory].data, addr, stride, start, width).unwrap_or_default();
         next!();
     }
     MemoryReadSInt {
@@ -2897,7 +3138,7 @@ impl_insns! {
         width: usize,
     } => {
         let addr = state.small_slots[addr];
-        state.big_slots[dest] = memory_read_big::<SInt>(&mut state.memories[memory], addr, stride, start, width).unwrap_or_default();
+        state.big_slots[dest] = memory_read_big::<SInt>(&mut state.memories[memory].data, addr, stride, start, width).unwrap_or_default();
         next!();
     }
     MemoryWriteUInt {
@@ -2915,7 +3156,7 @@ impl_insns! {
         width: usize,
     } => {
         let addr = state.small_slots[addr];
-        memory_write_big::<UInt>(&mut state.memories[memory], addr, stride, start, width, &mut state.big_slots[value]);
+        memory_write_big::<UInt>(&mut state.memories[memory].data, addr, stride, start, width, &mut state.big_slots[value]);
         state.log_memory_write(memory, addr);
         next!();
     }
@@ -2934,11 +3175,11 @@ impl_insns! {
         width: usize,
     } => {
         let addr = state.small_slots[addr];
-        memory_write_big::<SInt>(&mut state.memories[memory], addr, stride, start, width, &mut state.big_slots[value]);
+        memory_write_big::<SInt>(&mut state.memories[memory].data, addr, stride, start, width, &mut state.big_slots[value]);
         state.log_memory_write(memory, addr);
         next!();
     }
     Return => {
-        break;
+        break RunResult::Return(());
     }
 }
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 41d966b..2b8f276 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -509,7 +509,6 @@ pub fn memories() {
     connect_any(mem.new_write_port(), w);
 }
 
-#[cfg(todo)] // TODO: finish
 #[hdl]
 #[test]
 fn test_memories() {
@@ -529,15 +528,107 @@ fn test_memories() {
         w_data: (u8, i8),
         w_mask: (bool, bool),
     }
-    let io_cycles = [IO {
-        r_addr: 0,
-        r_en: false,
-        r_data: (0, 0),
-        w_addr: 0,
-        w_en: false,
-        w_data: (0, 0),
-        w_mask: (false, false),
-    }];
+    let io_cycles = [
+        IO {
+            r_addr: 0,
+            r_en: false,
+            r_data: (0, 0),
+            w_addr: 0,
+            w_en: false,
+            w_data: (0, 0),
+            w_mask: (false, false),
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: (0x1, 0x23),
+            w_addr: 0,
+            w_en: true,
+            w_data: (0x10, 0x20),
+            w_mask: (true, true),
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: (0x10, 0x20),
+            w_addr: 0,
+            w_en: true,
+            w_data: (0x30, 0x40),
+            w_mask: (false, true),
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: (0x10, 0x40),
+            w_addr: 0,
+            w_en: true,
+            w_data: (0x50, 0x60),
+            w_mask: (true, false),
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: (0x50, 0x40),
+            w_addr: 0,
+            w_en: true,
+            w_data: (0x70, -0x80),
+            w_mask: (false, false),
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: (0x50, 0x40),
+            w_addr: 0,
+            w_en: false,
+            w_data: (0x90, 0xA0u8 as i8),
+            w_mask: (false, false),
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: (0x50, 0x40),
+            w_addr: 1,
+            w_en: true,
+            w_data: (0x90, 0xA0u8 as i8),
+            w_mask: (true, true),
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: (0x50, 0x40),
+            w_addr: 2,
+            w_en: true,
+            w_data: (0xB0, 0xC0u8 as i8),
+            w_mask: (true, true),
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: (0x50, 0x40),
+            w_addr: 2,
+            w_en: false,
+            w_data: (0xD0, 0xE0u8 as i8),
+            w_mask: (true, true),
+        },
+        IO {
+            r_addr: 1,
+            r_en: true,
+            r_data: (0x90, 0xA0u8 as i8),
+            w_addr: 2,
+            w_en: false,
+            w_data: (0xD0, 0xE0u8 as i8),
+            w_mask: (true, true),
+        },
+        IO {
+            r_addr: 2,
+            r_en: true,
+            r_data: (0xB0, 0xC0u8 as i8),
+            w_addr: 2,
+            w_en: false,
+            w_data: (0xD0, 0xE0u8 as i8),
+            w_mask: (true, true),
+        },
+    ];
     for (
         cycle,
         expected @ IO {
diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt
index e527678..e44c50d 100644
--- a/crates/fayalite/tests/sim/expected/connect_const.txt
+++ b/crates/fayalite/tests/sim/expected/connect_const.txt
@@ -33,13 +33,13 @@ Simulation {
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
                 0: Const {
-                    dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
-                    value: 5,
+                    dest: StatePartIndex<BigSlots>(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x5,
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
                 1: Copy {
-                    dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
+                    dest: StatePartIndex<BigSlots>(0), // (0x5) SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 2: Return,
@@ -138,4 +138,5 @@ Simulation {
     trace_writers: [],
     instant: 0 s,
     clocks_triggered: [],
+    ..
 }
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
index f74dbec..d1ab998 100644
--- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt
+++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
@@ -45,27 +45,27 @@ Simulation {
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
                 0: Const {
-                    dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    value: 1,
+                    dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    value: 0x1,
                 },
                 1: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
-                    src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "", ty: AsyncReset },
+                    src: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
                 2: Copy {
-                    dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
-                    src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
+                    dest: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
+                    src: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "", ty: AsyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 3: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
+                    dest: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
                 4: Copy {
-                    dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
-                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
+                    src: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 5: Return,
@@ -225,4 +225,5 @@ Simulation {
     ],
     instant: 1 μs,
     clocks_triggered: [],
+    ..
 }
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt
index b2bcd56..2e005a0 100644
--- a/crates/fayalite/tests/sim/expected/counter_async.txt
+++ b/crates/fayalite/tests/sim/expected/counter_async.txt
@@ -82,85 +82,86 @@ Simulation {
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
                 0: Const {
-                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
-                    value: 1,
+                    dest: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    value: 0x1,
                 },
                 1: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
+                    dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
                 2: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
+                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 3: Const {
-                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
-                    value: 3,
+                    dest: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                    value: 0x3,
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
                 4: BranchIfZero {
                     target: 6,
-                    value: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 5: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 6: Add {
-                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
-                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    rhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
+                    lhs: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 7: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
+                    dest: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
                     dest_width: 4,
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
                 8: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
                 9: Copy {
-                    dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
                 10: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
+                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
                 },
                 11: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 12: BranchIfSmallNonZero {
                     target: 16,
-                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 13: BranchIfSmallZero {
                     target: 17,
-                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 14: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
                 },
                 15: Branch {
                     target: 17,
                 },
                 16: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
                 },
-                17: NotSmall {
-                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                17: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 18: Return,
@@ -174,7 +175,7 @@ Simulation {
         },
         small_slots: StatePart {
             value: [
-                18446744073709551614,
+                0,
                 0,
                 1,
                 0,
@@ -517,4 +518,5 @@ Simulation {
     clocks_triggered: [
         StatePartIndex<SmallSlots>(1),
     ],
+    ..
 }
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt
index 1615917..78fc200 100644
--- a/crates/fayalite/tests/sim/expected/counter_sync.txt
+++ b/crates/fayalite/tests/sim/expected/counter_sync.txt
@@ -78,71 +78,72 @@ Simulation {
             insns: [
                 // at: module-XXXXXXXXXX.rs:6:1
                 0: Copy {
-                    dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 1: Const {
-                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
-                    value: 1,
+                    dest: StatePartIndex<BigSlots>(6), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    value: 0x1,
                 },
                 2: Add {
-                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
-                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    rhs: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
+                    lhs: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(6), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 3: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
+                    dest: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
                     dest_width: 4,
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
                 4: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
                 5: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
+                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 6: Const {
-                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
-                    value: 3,
+                    dest: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                    value: 0x3,
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
                 7: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
+                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
                 },
                 8: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 9: BranchIfSmallZero {
                     target: 14,
-                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 10: BranchIfSmallNonZero {
                     target: 13,
-                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 11: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
                 },
                 12: Branch {
                     target: 14,
                 },
                 13: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
                 },
-                14: NotSmall {
-                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                14: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 15: Return,
@@ -156,7 +157,7 @@ Simulation {
         },
         small_slots: StatePart {
             value: [
-                18446744073709551614,
+                0,
                 0,
                 1,
                 0,
@@ -498,4 +499,5 @@ Simulation {
     clocks_triggered: [
         StatePartIndex<SmallSlots>(1),
     ],
+    ..
 }
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt
index 5f958ad..ebdcf7e 100644
--- a/crates/fayalite/tests/sim/expected/enums.txt
+++ b/crates/fayalite/tests/sim/expected/enums.txt
@@ -398,476 +398,477 @@ Simulation {
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
                 0: Const {
-                    dest: StatePartIndex<BigSlots>(72), // SlotDebugData { name: "", ty: UInt<4> },
-                    value: 0,
+                    dest: StatePartIndex<BigSlots>(72), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
+                    value: 0x0,
                 },
                 1: SliceInt {
-                    dest: StatePartIndex<BigSlots>(61), // SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
                     start: 2,
                     len: 2,
                 },
                 2: CastToSInt {
-                    dest: StatePartIndex<BigSlots>(62), // SlotDebugData { name: "", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(61), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(62), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     dest_width: 2,
                 },
                 3: Const {
-                    dest: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
-                    value: 2,
+                    dest: StatePartIndex<BigSlots>(54), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    value: 0x2,
                 },
                 4: SliceInt {
-                    dest: StatePartIndex<BigSlots>(41), // SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
                     start: 1,
                     len: 1,
                 },
                 5: Copy {
-                    dest: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(41), // SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 6: Copy {
-                    dest: StatePartIndex<BigSlots>(60), // SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(60), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: "", ty: Bool },
                 },
                 7: SliceInt {
-                    dest: StatePartIndex<BigSlots>(38), // SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(38), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
                     start: 0,
                     len: 1,
                 },
                 8: Copy {
-                    dest: StatePartIndex<BigSlots>(39), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(38), // SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(38), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 9: Copy {
-                    dest: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(39), // SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(40), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: Bool },
                 },
                 10: Copy {
-                    dest: StatePartIndex<BigSlots>(36), // SlotDebugData { name: ".0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(36), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(40), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 11: Copy {
-                    dest: StatePartIndex<BigSlots>(37), // SlotDebugData { name: ".1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: "", ty: Bool },
                 },
                 12: Copy {
-                    dest: StatePartIndex<BigSlots>(58), // SlotDebugData { name: "[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(58), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(40), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 13: Copy {
-                    dest: StatePartIndex<BigSlots>(59), // SlotDebugData { name: "[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(60), // SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(60), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 14: Copy {
-                    dest: StatePartIndex<BigSlots>(55), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(58), // SlotDebugData { name: "[0]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(55), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(58), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
                 },
                 15: Copy {
-                    dest: StatePartIndex<BigSlots>(56), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(59), // SlotDebugData { name: "[1]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(56), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
                 },
                 16: Copy {
-                    dest: StatePartIndex<BigSlots>(57), // SlotDebugData { name: ".b", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(62), // SlotDebugData { name: "", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(57), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(62), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
                 },
                 17: Copy {
-                    dest: StatePartIndex<BigSlots>(50), // SlotDebugData { name: ".0", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(50), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(54), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 18: Copy {
-                    dest: StatePartIndex<BigSlots>(51), // SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(55), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(55), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
                 },
                 19: Copy {
-                    dest: StatePartIndex<BigSlots>(52), // SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(56), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(56), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
                 },
                 20: Copy {
-                    dest: StatePartIndex<BigSlots>(53), // SlotDebugData { name: ".1.b", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(57), // SlotDebugData { name: ".b", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(53), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(57), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
                 },
                 21: Shl {
-                    dest: StatePartIndex<BigSlots>(63), // SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(52), // SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(63), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
                     rhs: 1,
                 },
                 22: Or {
-                    dest: StatePartIndex<BigSlots>(64), // SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(51), // SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(63), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(63), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 23: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(65), // SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(53), // SlotDebugData { name: ".1.b", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(65), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(53), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
                     dest_width: 2,
                 },
                 24: Shl {
-                    dest: StatePartIndex<BigSlots>(66), // SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(65), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(66), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(65), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     rhs: 2,
                 },
                 25: Or {
-                    dest: StatePartIndex<BigSlots>(67), // SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(64), // SlotDebugData { name: "", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(66), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(67), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(66), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 26: Shl {
-                    dest: StatePartIndex<BigSlots>(68), // SlotDebugData { name: "", ty: UInt<6> },
-                    lhs: StatePartIndex<BigSlots>(67), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(68), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(67), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
                     rhs: 2,
                 },
                 27: Or {
-                    dest: StatePartIndex<BigSlots>(69), // SlotDebugData { name: "", ty: UInt<6> },
-                    lhs: StatePartIndex<BigSlots>(50), // SlotDebugData { name: ".0", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(68), // SlotDebugData { name: "", ty: UInt<6> },
+                    dest: StatePartIndex<BigSlots>(69), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(50), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(68), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
                 },
                 28: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(70), // SlotDebugData { name: "", ty: UInt<6> },
-                    src: StatePartIndex<BigSlots>(69), // SlotDebugData { name: "", ty: UInt<6> },
+                    dest: StatePartIndex<BigSlots>(70), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(69), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
                     dest_width: 6,
                 },
                 29: Copy {
-                    dest: StatePartIndex<BigSlots>(71), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(70), // SlotDebugData { name: "", ty: UInt<6> },
+                    dest: StatePartIndex<BigSlots>(71), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(70), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
                 },
                 30: Const {
-                    dest: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
-                    value: 1,
+                    dest: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                    value: 0x1,
                 },
                 31: CmpEq {
-                    dest: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<BigSlots>(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 32: Copy {
-                    dest: StatePartIndex<BigSlots>(33), // SlotDebugData { name: ".0", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 33: Copy {
-                    dest: StatePartIndex<BigSlots>(34), // SlotDebugData { name: ".1.0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(36), // SlotDebugData { name: ".0", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(36), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
                 },
                 34: Copy {
-                    dest: StatePartIndex<BigSlots>(35), // SlotDebugData { name: ".1.1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(37), // SlotDebugData { name: ".1", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: ".1", ty: Bool },
                 },
                 35: Copy {
-                    dest: StatePartIndex<BigSlots>(43), // SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(35), // SlotDebugData { name: ".1.1", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(43), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
                 },
                 36: Shl {
-                    dest: StatePartIndex<BigSlots>(44), // SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(43), // SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(44), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(43), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 1,
                 },
                 37: Or {
-                    dest: StatePartIndex<BigSlots>(45), // SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(34), // SlotDebugData { name: ".1.0", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(44), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(45), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(44), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 38: Shl {
-                    dest: StatePartIndex<BigSlots>(46), // SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(45), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(46), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(45), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     rhs: 2,
                 },
                 39: Or {
-                    dest: StatePartIndex<BigSlots>(47), // SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(33), // SlotDebugData { name: ".0", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(46), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(47), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(46), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 40: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(48), // SlotDebugData { name: "", ty: UInt<6> },
-                    src: StatePartIndex<BigSlots>(47), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(48), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(47), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
                     dest_width: 6,
                 },
                 41: Copy {
-                    dest: StatePartIndex<BigSlots>(49), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(48), // SlotDebugData { name: "", ty: UInt<6> },
+                    dest: StatePartIndex<BigSlots>(49), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(48), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
                 },
                 42: Const {
-                    dest: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
-                    value: 0,
+                    dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    value: 0x0,
                 },
                 43: CmpEq {
-                    dest: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<BigSlots>(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 44: Copy {
-                    dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
-                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    dest: StatePartIndex<BigSlots>(13), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 45: SliceInt {
-                    dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
+                    dest: StatePartIndex<BigSlots>(14), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(13), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
                     start: 2,
                     len: 2,
                 },
                 46: SliceInt {
-                    dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(14), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     start: 0,
                     len: 1,
                 },
                 47: SliceInt {
-                    dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(16), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(14), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     start: 1,
                     len: 1,
                 },
                 48: Copy {
-                    dest: StatePartIndex<BigSlots>(17), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(17), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(16), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 49: Copy {
-                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: ".0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 50: Copy {
-                    dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: ".1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(17), // SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(17), // (0x1) SlotDebugData { name: "", ty: Bool },
                 },
                 51: Copy {
-                    dest: StatePartIndex<BigSlots>(73), // SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: ".1", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(73), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: ".1", ty: Bool },
                 },
                 52: Shl {
-                    dest: StatePartIndex<BigSlots>(74), // SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(73), // SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(74), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(73), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 1,
                 },
                 53: Or {
-                    dest: StatePartIndex<BigSlots>(75), // SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(11), // SlotDebugData { name: ".0", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(74), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(75), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(74), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 54: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(76), // SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(75), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(76), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(75), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     dest_width: 4,
                 },
                 55: SliceInt {
-                    dest: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
+                    dest: StatePartIndex<BigSlots>(23), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(13), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
                     start: 2,
                     len: 4,
                 },
                 56: SliceInt {
-                    dest: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(24), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(23), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
                     start: 0,
                     len: 2,
                 },
                 57: SliceInt {
-                    dest: StatePartIndex<BigSlots>(25), // SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(24), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     start: 0,
                     len: 1,
                 },
                 58: SliceInt {
-                    dest: StatePartIndex<BigSlots>(26), // SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(24), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     start: 1,
                     len: 1,
                 },
                 59: Copy {
-                    dest: StatePartIndex<BigSlots>(21), // SlotDebugData { name: "[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(25), // SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 60: Copy {
-                    dest: StatePartIndex<BigSlots>(22), // SlotDebugData { name: "[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(26), // SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 61: SliceInt {
-                    dest: StatePartIndex<BigSlots>(27), // SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(27), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(23), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
                     start: 2,
                     len: 2,
                 },
                 62: CastToSInt {
-                    dest: StatePartIndex<BigSlots>(28), // SlotDebugData { name: "", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(27), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(28), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(27), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     dest_width: 2,
                 },
                 63: Copy {
-                    dest: StatePartIndex<BigSlots>(18), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(21), // SlotDebugData { name: "[0]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(18), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
                 },
                 64: Copy {
-                    dest: StatePartIndex<BigSlots>(19), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(22), // SlotDebugData { name: "[1]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
                 },
                 65: Copy {
-                    dest: StatePartIndex<BigSlots>(20), // SlotDebugData { name: ".b", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(28), // SlotDebugData { name: "", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(20), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(28), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
                 },
                 66: Shl {
-                    dest: StatePartIndex<BigSlots>(77), // SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(19), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(77), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
                     rhs: 1,
                 },
                 67: Or {
-                    dest: StatePartIndex<BigSlots>(78), // SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(18), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(77), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(78), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(18), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(77), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 68: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(79), // SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(20), // SlotDebugData { name: ".b", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(79), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(20), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
                     dest_width: 2,
                 },
                 69: Shl {
-                    dest: StatePartIndex<BigSlots>(80), // SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(79), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(80), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(79), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     rhs: 2,
                 },
                 70: Or {
-                    dest: StatePartIndex<BigSlots>(81), // SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(78), // SlotDebugData { name: "", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(80), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(81), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(78), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(80), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
                 71: AndBigWithSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    lhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    rhs: 3,
+                    dest: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    lhs: StatePartIndex<BigSlots>(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    rhs: 0x3,
                 },
                 // at: module-XXXXXXXXXX.rs:15:1
                 72: BranchIfSmallNeImmediate {
                     target: 75,
-                    lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    rhs: 0,
+                    lhs: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 0x0,
                 },
                 // at: module-XXXXXXXXXX.rs:16:1
                 73: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:17:1
                 74: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(72), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(72), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:15:1
                 75: BranchIfSmallNeImmediate {
                     target: 78,
-                    lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    rhs: 1,
+                    lhs: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:18:1
                 76: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:19:1
                 77: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(76), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(76), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:15:1
                 78: BranchIfSmallNeImmediate {
                     target: 81,
-                    lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    rhs: 2,
+                    lhs: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 0x2,
                 },
                 // at: module-XXXXXXXXXX.rs:20:1
                 79: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(54), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:21:1
                 80: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(81), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(81), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
                 81: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset },
+                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 82: Const {
-                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<6> },
-                    value: 0,
+                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
+                    value: 0x0,
                 },
                 83: Copy {
-                    dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<6> },
+                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                 },
                 // at: module-XXXXXXXXXX.rs:9:1
                 84: BranchIfZero {
                     target: 92,
-                    value: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool },
+                    value: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:10:1
                 85: BranchIfZero {
                     target: 87,
-                    value: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
                 86: Copy {
-                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    dest: StatePartIndex<BigSlots>(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 // at: module-XXXXXXXXXX.rs:10:1
                 87: BranchIfNonZero {
                     target: 92,
-                    value: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:12:1
                 88: BranchIfZero {
                     target: 90,
-                    value: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:13:1
                 89: Copy {
-                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(49), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    dest: StatePartIndex<BigSlots>(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(49), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 // at: module-XXXXXXXXXX.rs:12:1
                 90: BranchIfNonZero {
                     target: 92,
-                    value: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:14:1
                 91: Copy {
-                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(71), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    dest: StatePartIndex<BigSlots>(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(71), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
                 92: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock },
+                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock },
                 },
                 93: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 94: BranchIfSmallZero {
                     target: 99,
-                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 95: BranchIfSmallNonZero {
                     target: 98,
-                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 96: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    dest: StatePartIndex<BigSlots>(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 97: Branch {
                     target: 99,
                 },
                 98: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    dest: StatePartIndex<BigSlots>(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
-                99: NotSmall {
-                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                99: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 100: Return,
@@ -881,7 +882,7 @@ Simulation {
         },
         small_slots: StatePart {
             value: [
-                18446744073709551614,
+                0,
                 0,
                 1,
                 0,
@@ -1638,4 +1639,5 @@ Simulation {
     clocks_triggered: [
         StatePartIndex<SmallSlots>(1),
     ],
+    ..
 }
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/memories.txt b/crates/fayalite/tests/sim/expected/memories.txt
new file mode 100644
index 0000000..afccd8a
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/memories.txt
@@ -0,0 +1,2776 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 12,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 28,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::r.addr",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::r.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::r.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::r.data.0",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::r.data.1",
+                                ty: SInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.addr",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.data.0",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.data.1",
+                                ty: SInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.mask.0",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.mask.1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::r0.addr",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::r0.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::r0.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1",
+                                ty: SInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::w1.addr",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::w1.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::w1.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::w1.data.0",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::w1.data.1",
+                                ty: SInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.0",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: SInt<8>,
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 1,
+                    debug_data: [
+                        (),
+                    ],
+                    layout_data: [
+                        MemoryData {
+                            array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+                            data: [
+                                // len = 0x10
+                                [0x0]: 0x2301,
+                                [0x1]: 0x2301,
+                                [0x2]: 0x2301,
+                                [0x3]: 0x2301,
+                                [0x4]: 0x2301,
+                                [0x5]: 0x2301,
+                                [0x6]: 0x2301,
+                                [0x7]: 0x2301,
+                                [0x8]: 0x2301,
+                                [0x9]: 0x2301,
+                                [0xa]: 0x2301,
+                                [0xb]: 0x2301,
+                                [0xc]: 0x2301,
+                                [0xd]: 0x2301,
+                                [0xe]: 0x2301,
+                                [0xf]: 0x2301,
+                            ],
+                        },
+                    ],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:8:1
+                0: Copy {
+                    dest: StatePartIndex<BigSlots>(17), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.addr", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.addr", ty: UInt<4> },
+                },
+                1: Copy {
+                    dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.en", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.en", ty: Bool },
+                },
+                2: Copy {
+                    dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.clk", ty: Clock },
+                },
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0xd0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.0", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(8), // (0xd0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.data.0", ty: UInt<8> },
+                },
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(21), // (-0x20) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.1", ty: SInt<8> },
+                    src: StatePartIndex<BigSlots>(9), // (-0x20) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.data.1", ty: SInt<8> },
+                },
+                5: Copy {
+                    dest: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(10), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.mask.0", ty: Bool },
+                },
+                6: Copy {
+                    dest: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.mask.1", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                7: Copy {
+                    dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.clk", ty: Clock },
+                },
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.en", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.en", ty: Bool },
+                },
+                9: Copy {
+                    dest: StatePartIndex<BigSlots>(12), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.addr", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(0), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.addr", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                10: CastBigToArrayIndex {
+                    dest: StatePartIndex<SmallSlots>(9), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(17), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.addr", ty: UInt<4> },
+                },
+                11: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.en", ty: Bool },
+                },
+                12: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.clk", ty: Clock },
+                },
+                13: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                14: CastBigToArrayIndex {
+                    dest: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(12), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.addr", ty: UInt<4> },
+                },
+                15: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.en", ty: Bool },
+                },
+                16: BranchIfSmallZero {
+                    target: 20,
+                    value: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                17: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(15), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+                            //     data: [
+                            //         // len = 0x10
+                            //         [0x0]: 0x4050,
+                            //         [0x1]: 0xa090,
+                            //         [0x2]: 0xc0b0,
+                            //         [0x3]: 0x2301,
+                            //         [0x4]: 0x2301,
+                            //         [0x5]: 0x2301,
+                            //         [0x6]: 0x2301,
+                            //         [0x7]: 0x2301,
+                            //         [0x8]: 0x2301,
+                            //         [0x9]: 0x2301,
+                            //         [0xa]: 0x2301,
+                            //         [0xb]: 0x2301,
+                            //         [0xc]: 0x2301,
+                            //         [0xd]: 0x2301,
+                            //         [0xe]: 0x2301,
+                            //         [0xf]: 0x2301,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                    stride: 16,
+                    start: 0,
+                    width: 8,
+                },
+                18: MemoryReadSInt {
+                    dest: StatePartIndex<BigSlots>(16), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", ty: SInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+                            //     data: [
+                            //         // len = 0x10
+                            //         [0x0]: 0x4050,
+                            //         [0x1]: 0xa090,
+                            //         [0x2]: 0xc0b0,
+                            //         [0x3]: 0x2301,
+                            //         [0x4]: 0x2301,
+                            //         [0x5]: 0x2301,
+                            //         [0x6]: 0x2301,
+                            //         [0x7]: 0x2301,
+                            //         [0x8]: 0x2301,
+                            //         [0x9]: 0x2301,
+                            //         [0xa]: 0x2301,
+                            //         [0xb]: 0x2301,
+                            //         [0xc]: 0x2301,
+                            //         [0xd]: 0x2301,
+                            //         [0xe]: 0x2301,
+                            //         [0xf]: 0x2301,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                    stride: 16,
+                    start: 8,
+                    width: 8,
+                },
+                19: Branch {
+                    target: 22,
+                },
+                20: Const {
+                    dest: StatePartIndex<BigSlots>(15), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", ty: UInt<8> },
+                    value: 0x0,
+                },
+                21: Const {
+                    dest: StatePartIndex<BigSlots>(16), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", ty: SInt<8> },
+                    value: 0x0,
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                22: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.data.0", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(15), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", ty: UInt<8> },
+                },
+                23: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.data.1", ty: SInt<8> },
+                    src: StatePartIndex<BigSlots>(16), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", ty: SInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                24: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.clk", ty: Clock },
+                },
+                25: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                26: BranchIfSmallZero {
+                    target: 27,
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                27: BranchIfSmallZero {
+                    target: 39,
+                    value: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                28: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(10), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<SmallSlots>(9), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                29: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                30: Copy {
+                    dest: StatePartIndex<BigSlots>(24), // (0xd0) SlotDebugData { name: ".0", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(20), // (0xd0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.0", ty: UInt<8> },
+                },
+                31: Copy {
+                    dest: StatePartIndex<BigSlots>(25), // (-0x20) SlotDebugData { name: ".1", ty: SInt<8> },
+                    src: StatePartIndex<BigSlots>(21), // (-0x20) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.1", ty: SInt<8> },
+                },
+                32: Copy {
+                    dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.0", ty: Bool },
+                },
+                33: Copy {
+                    dest: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.1", ty: Bool },
+                },
+                34: BranchIfSmallZero {
+                    target: 39,
+                    value: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                35: BranchIfZero {
+                    target: 37,
+                    value: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: Bool },
+                },
+                36: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(24), // (0xd0) SlotDebugData { name: ".0", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+                            //     data: [
+                            //         // len = 0x10
+                            //         [0x0]: 0x4050,
+                            //         [0x1]: 0xa090,
+                            //         [0x2]: 0xc0b0,
+                            //         [0x3]: 0x2301,
+                            //         [0x4]: 0x2301,
+                            //         [0x5]: 0x2301,
+                            //         [0x6]: 0x2301,
+                            //         [0x7]: 0x2301,
+                            //         [0x8]: 0x2301,
+                            //         [0x9]: 0x2301,
+                            //         [0xa]: 0x2301,
+                            //         [0xb]: 0x2301,
+                            //         [0xc]: 0x2301,
+                            //         [0xd]: 0x2301,
+                            //         [0xe]: 0x2301,
+                            //         [0xf]: 0x2301,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(10), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                    stride: 16,
+                    start: 0,
+                    width: 8,
+                },
+                37: BranchIfZero {
+                    target: 39,
+                    value: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                },
+                38: MemoryWriteSInt {
+                    value: StatePartIndex<BigSlots>(25), // (-0x20) SlotDebugData { name: ".1", ty: SInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+                            //     data: [
+                            //         // len = 0x10
+                            //         [0x0]: 0x4050,
+                            //         [0x1]: 0xa090,
+                            //         [0x2]: 0xc0b0,
+                            //         [0x3]: 0x2301,
+                            //         [0x4]: 0x2301,
+                            //         [0x5]: 0x2301,
+                            //         [0x6]: 0x2301,
+                            //         [0x7]: 0x2301,
+                            //         [0x8]: 0x2301,
+                            //         [0x9]: 0x2301,
+                            //         [0xa]: 0x2301,
+                            //         [0xb]: 0x2301,
+                            //         [0xc]: 0x2301,
+                            //         [0xd]: 0x2301,
+                            //         [0xe]: 0x2301,
+                            //         [0xf]: 0x2301,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(10), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
+                    stride: 16,
+                    start: 8,
+                    width: 8,
+                },
+                39: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                40: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                41: Return,
+            ],
+            ..
+        },
+        pc: 41,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [
+                MemoryData {
+                    array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+                    data: [
+                        // len = 0x10
+                        [0x0]: 0x4050,
+                        [0x1]: 0xa090,
+                        [0x2]: 0xc0b0,
+                        [0x3]: 0x2301,
+                        [0x4]: 0x2301,
+                        [0x5]: 0x2301,
+                        [0x6]: 0x2301,
+                        [0x7]: 0x2301,
+                        [0x8]: 0x2301,
+                        [0x9]: 0x2301,
+                        [0xa]: 0x2301,
+                        [0xb]: 0x2301,
+                        [0xc]: 0x2301,
+                        [0xd]: 0x2301,
+                        [0xe]: 0x2301,
+                        [0xf]: 0x2301,
+                    ],
+                },
+            ],
+        },
+        small_slots: StatePart {
+            value: [
+                1,
+                0,
+                0,
+                1,
+                2,
+                1,
+                0,
+                0,
+                0,
+                2,
+                2,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                2,
+                1,
+                0,
+                176,
+                -64,
+                2,
+                0,
+                0,
+                208,
+                -32,
+                1,
+                1,
+                2,
+                1,
+                0,
+                176,
+                -64,
+                2,
+                0,
+                0,
+                208,
+                -32,
+                1,
+                1,
+                208,
+                -32,
+                1,
+                1,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::memories,
+        instantiated: Module {
+            name: memories,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.r: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    /* offset = 0 */
+                    addr: UInt<4>,
+                    /* offset = 4 */
+                    en: Bool,
+                    /* offset = 5 */
+                    clk: Clock,
+                    #[hdl(flip)] /* offset = 6 */
+                    data: Bundle {
+                        /* offset = 0 */
+                        0: UInt<8>,
+                        /* offset = 8 */
+                        1: SInt<8>,
+                    },
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 5,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::r.addr",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::r.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::r.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::r.data.0",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::r.data.1",
+                                ty: SInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: UInt<4>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: UInt<4>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Bool,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Bool,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(2),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Clock,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Clock,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(3),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Bundle {
+                                    /* offset = 0 */
+                                    0: UInt<8>,
+                                    /* offset = 8 */
+                                    1: SInt<8>,
+                                },
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 2,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: ".0",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: ".1",
+                                                ty: SInt<8>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Bundle {
+                                    fields: [
+                                        CompiledBundleField {
+                                            offset: TypeIndex {
+                                                small_slots: StatePartIndex<SmallSlots>(0),
+                                                big_slots: StatePartIndex<BigSlots>(0),
+                                            },
+                                            ty: CompiledTypeLayout {
+                                                ty: UInt<8>,
+                                                layout: TypeLayout {
+                                                    small_slots: StatePartLayout<SmallSlots> {
+                                                        len: 0,
+                                                        debug_data: [],
+                                                        ..
+                                                    },
+                                                    big_slots: StatePartLayout<BigSlots> {
+                                                        len: 1,
+                                                        debug_data: [
+                                                            SlotDebugData {
+                                                                name: "",
+                                                                ty: UInt<8>,
+                                                            },
+                                                        ],
+                                                        ..
+                                                    },
+                                                },
+                                                body: Scalar,
+                                            },
+                                        },
+                                        CompiledBundleField {
+                                            offset: TypeIndex {
+                                                small_slots: StatePartIndex<SmallSlots>(0),
+                                                big_slots: StatePartIndex<BigSlots>(1),
+                                            },
+                                            ty: CompiledTypeLayout {
+                                                ty: SInt<8>,
+                                                layout: TypeLayout {
+                                                    small_slots: StatePartLayout<SmallSlots> {
+                                                        len: 0,
+                                                        debug_data: [],
+                                                        ..
+                                                    },
+                                                    big_slots: StatePartLayout<BigSlots> {
+                                                        len: 1,
+                                                        debug_data: [
+                                                            SlotDebugData {
+                                                                name: "",
+                                                                ty: SInt<8>,
+                                                            },
+                                                        ],
+                                                        ..
+                                                    },
+                                                },
+                                                body: Scalar,
+                                            },
+                                        },
+                                    ],
+                                },
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 5 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.r.addr: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<4>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.r.clk: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.r.data: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    /* offset = 0 */
+                    0: UInt<8>,
+                    /* offset = 8 */
+                    1: SInt<8>,
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: SInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: UInt<8>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: UInt<8>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: SInt<8>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: SInt<8>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 2 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.r.data.0: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.r.data.1: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: SInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: SInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.r.en: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.w: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    /* offset = 0 */
+                    addr: UInt<4>,
+                    /* offset = 4 */
+                    en: Bool,
+                    /* offset = 5 */
+                    clk: Clock,
+                    /* offset = 6 */
+                    data: Bundle {
+                        /* offset = 0 */
+                        0: UInt<8>,
+                        /* offset = 8 */
+                        1: SInt<8>,
+                    },
+                    /* offset = 22 */
+                    mask: Bundle {
+                        /* offset = 0 */
+                        0: Bool,
+                        /* offset = 1 */
+                        1: Bool,
+                    },
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 7,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.addr",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.data.0",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.data.1",
+                                ty: SInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.mask.0",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories: memories).memories::w.mask.1",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: UInt<4>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: UInt<4>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Bool,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Bool,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(2),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Clock,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Clock,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(3),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Bundle {
+                                    /* offset = 0 */
+                                    0: UInt<8>,
+                                    /* offset = 8 */
+                                    1: SInt<8>,
+                                },
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 2,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: ".0",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: ".1",
+                                                ty: SInt<8>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Bundle {
+                                    fields: [
+                                        CompiledBundleField {
+                                            offset: TypeIndex {
+                                                small_slots: StatePartIndex<SmallSlots>(0),
+                                                big_slots: StatePartIndex<BigSlots>(0),
+                                            },
+                                            ty: CompiledTypeLayout {
+                                                ty: UInt<8>,
+                                                layout: TypeLayout {
+                                                    small_slots: StatePartLayout<SmallSlots> {
+                                                        len: 0,
+                                                        debug_data: [],
+                                                        ..
+                                                    },
+                                                    big_slots: StatePartLayout<BigSlots> {
+                                                        len: 1,
+                                                        debug_data: [
+                                                            SlotDebugData {
+                                                                name: "",
+                                                                ty: UInt<8>,
+                                                            },
+                                                        ],
+                                                        ..
+                                                    },
+                                                },
+                                                body: Scalar,
+                                            },
+                                        },
+                                        CompiledBundleField {
+                                            offset: TypeIndex {
+                                                small_slots: StatePartIndex<SmallSlots>(0),
+                                                big_slots: StatePartIndex<BigSlots>(1),
+                                            },
+                                            ty: CompiledTypeLayout {
+                                                ty: SInt<8>,
+                                                layout: TypeLayout {
+                                                    small_slots: StatePartLayout<SmallSlots> {
+                                                        len: 0,
+                                                        debug_data: [],
+                                                        ..
+                                                    },
+                                                    big_slots: StatePartLayout<BigSlots> {
+                                                        len: 1,
+                                                        debug_data: [
+                                                            SlotDebugData {
+                                                                name: "",
+                                                                ty: SInt<8>,
+                                                            },
+                                                        ],
+                                                        ..
+                                                    },
+                                                },
+                                                body: Scalar,
+                                            },
+                                        },
+                                    ],
+                                },
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(5),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Bundle {
+                                    /* offset = 0 */
+                                    0: Bool,
+                                    /* offset = 1 */
+                                    1: Bool,
+                                },
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 2,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: ".0",
+                                                ty: Bool,
+                                            },
+                                            SlotDebugData {
+                                                name: ".1",
+                                                ty: Bool,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Bundle {
+                                    fields: [
+                                        CompiledBundleField {
+                                            offset: TypeIndex {
+                                                small_slots: StatePartIndex<SmallSlots>(0),
+                                                big_slots: StatePartIndex<BigSlots>(0),
+                                            },
+                                            ty: CompiledTypeLayout {
+                                                ty: Bool,
+                                                layout: TypeLayout {
+                                                    small_slots: StatePartLayout<SmallSlots> {
+                                                        len: 0,
+                                                        debug_data: [],
+                                                        ..
+                                                    },
+                                                    big_slots: StatePartLayout<BigSlots> {
+                                                        len: 1,
+                                                        debug_data: [
+                                                            SlotDebugData {
+                                                                name: "",
+                                                                ty: Bool,
+                                                            },
+                                                        ],
+                                                        ..
+                                                    },
+                                                },
+                                                body: Scalar,
+                                            },
+                                        },
+                                        CompiledBundleField {
+                                            offset: TypeIndex {
+                                                small_slots: StatePartIndex<SmallSlots>(0),
+                                                big_slots: StatePartIndex<BigSlots>(1),
+                                            },
+                                            ty: CompiledTypeLayout {
+                                                ty: Bool,
+                                                layout: TypeLayout {
+                                                    small_slots: StatePartLayout<SmallSlots> {
+                                                        len: 0,
+                                                        debug_data: [],
+                                                        ..
+                                                    },
+                                                    big_slots: StatePartLayout<BigSlots> {
+                                                        len: 1,
+                                                        debug_data: [
+                                                            SlotDebugData {
+                                                                name: "",
+                                                                ty: Bool,
+                                                            },
+                                                        ],
+                                                        ..
+                                                    },
+                                                },
+                                                body: Scalar,
+                                            },
+                                        },
+                                    ],
+                                },
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 7 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.w.addr: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<4>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.w.clk: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 7, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.w.data: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    /* offset = 0 */
+                    0: UInt<8>,
+                    /* offset = 8 */
+                    1: SInt<8>,
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: SInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: UInt<8>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: UInt<8>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: SInt<8>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: SInt<8>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 8, len: 2 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.w.data.0: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 8, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.w.data.1: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: SInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: SInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 9, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.w.en: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 6, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.w.mask: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    /* offset = 0 */
+                    0: Bool,
+                    /* offset = 1 */
+                    1: Bool,
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: ".0",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Bool,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Bool,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Bool,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Bool,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 10, len: 2 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.w.mask.0: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 10, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories,
+            instantiated: Module {
+                name: memories,
+                ..
+            },
+        }.w.mask.1: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 11, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "memories",
+        children: [
+            TraceModuleIO {
+                name: "r",
+                child: TraceBundle {
+                    name: "r",
+                    fields: [
+                        TraceUInt {
+                            location: TraceScalarId(0),
+                            name: "addr",
+                            ty: UInt<4>,
+                            flow: Source,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(1),
+                            name: "en",
+                            flow: Source,
+                        },
+                        TraceClock {
+                            location: TraceScalarId(2),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceBundle {
+                            name: "data",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(3),
+                                    name: "0",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceSInt {
+                                    location: TraceScalarId(4),
+                                    name: "1",
+                                    ty: SInt<8>,
+                                    flow: Sink,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                0: UInt<8>,
+                                /* offset = 8 */
+                                1: SInt<8>,
+                            },
+                            flow: Sink,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<4>,
+                        /* offset = 4 */
+                        en: Bool,
+                        /* offset = 5 */
+                        clk: Clock,
+                        #[hdl(flip)] /* offset = 6 */
+                        data: Bundle {
+                            /* offset = 0 */
+                            0: UInt<8>,
+                            /* offset = 8 */
+                            1: SInt<8>,
+                        },
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    addr: UInt<4>,
+                    /* offset = 4 */
+                    en: Bool,
+                    /* offset = 5 */
+                    clk: Clock,
+                    #[hdl(flip)] /* offset = 6 */
+                    data: Bundle {
+                        /* offset = 0 */
+                        0: UInt<8>,
+                        /* offset = 8 */
+                        1: SInt<8>,
+                    },
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "w",
+                child: TraceBundle {
+                    name: "w",
+                    fields: [
+                        TraceUInt {
+                            location: TraceScalarId(5),
+                            name: "addr",
+                            ty: UInt<4>,
+                            flow: Source,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(6),
+                            name: "en",
+                            flow: Source,
+                        },
+                        TraceClock {
+                            location: TraceScalarId(7),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceBundle {
+                            name: "data",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(8),
+                                    name: "0",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceSInt {
+                                    location: TraceScalarId(9),
+                                    name: "1",
+                                    ty: SInt<8>,
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                0: UInt<8>,
+                                /* offset = 8 */
+                                1: SInt<8>,
+                            },
+                            flow: Source,
+                        },
+                        TraceBundle {
+                            name: "mask",
+                            fields: [
+                                TraceBool {
+                                    location: TraceScalarId(10),
+                                    name: "0",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(11),
+                                    name: "1",
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                0: Bool,
+                                /* offset = 1 */
+                                1: Bool,
+                            },
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<4>,
+                        /* offset = 4 */
+                        en: Bool,
+                        /* offset = 5 */
+                        clk: Clock,
+                        /* offset = 6 */
+                        data: Bundle {
+                            /* offset = 0 */
+                            0: UInt<8>,
+                            /* offset = 8 */
+                            1: SInt<8>,
+                        },
+                        /* offset = 22 */
+                        mask: Bundle {
+                            /* offset = 0 */
+                            0: Bool,
+                            /* offset = 1 */
+                            1: Bool,
+                        },
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    addr: UInt<4>,
+                    /* offset = 4 */
+                    en: Bool,
+                    /* offset = 5 */
+                    clk: Clock,
+                    /* offset = 6 */
+                    data: Bundle {
+                        /* offset = 0 */
+                        0: UInt<8>,
+                        /* offset = 8 */
+                        1: SInt<8>,
+                    },
+                    /* offset = 22 */
+                    mask: Bundle {
+                        /* offset = 0 */
+                        0: Bool,
+                        /* offset = 1 */
+                        1: Bool,
+                    },
+                },
+                flow: Source,
+            },
+            TraceMem {
+                id: TraceMemoryId(0),
+                name: "mem",
+                stride: 16,
+                element_type: TraceBundle {
+                    name: "mem",
+                    fields: [
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 16,
+                                stride: 16,
+                                start: 0,
+                                len: 8,
+                            },
+                            name: "0",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceSInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 16,
+                                stride: 16,
+                                start: 8,
+                                len: 8,
+                            },
+                            name: "1",
+                            ty: SInt<8>,
+                            flow: Duplex,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        0: UInt<8>,
+                        /* offset = 8 */
+                        1: SInt<8>,
+                    },
+                    flow: Duplex,
+                },
+                ports: [
+                    TraceMemPort {
+                        name: "r0",
+                        bundle: TraceBundle {
+                            name: "r0",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(12),
+                                    name: "addr",
+                                    ty: UInt<4>,
+                                    flow: Sink,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(13),
+                                    name: "en",
+                                    flow: Sink,
+                                },
+                                TraceClock {
+                                    location: TraceScalarId(14),
+                                    name: "clk",
+                                    flow: Sink,
+                                },
+                                TraceBundle {
+                                    name: "data",
+                                    fields: [
+                                        TraceUInt {
+                                            location: TraceScalarId(15),
+                                            name: "0",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceSInt {
+                                            location: TraceScalarId(16),
+                                            name: "1",
+                                            ty: SInt<8>,
+                                            flow: Source,
+                                        },
+                                    ],
+                                    ty: Bundle {
+                                        /* offset = 0 */
+                                        0: UInt<8>,
+                                        /* offset = 8 */
+                                        1: SInt<8>,
+                                    },
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                addr: UInt<4>,
+                                /* offset = 4 */
+                                en: Bool,
+                                /* offset = 5 */
+                                clk: Clock,
+                                #[hdl(flip)] /* offset = 6 */
+                                data: Bundle {
+                                    /* offset = 0 */
+                                    0: UInt<8>,
+                                    /* offset = 8 */
+                                    1: SInt<8>,
+                                },
+                            },
+                            flow: Sink,
+                        },
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<4>,
+                            /* offset = 4 */
+                            en: Bool,
+                            /* offset = 5 */
+                            clk: Clock,
+                            #[hdl(flip)] /* offset = 6 */
+                            data: Bundle {
+                                /* offset = 0 */
+                                0: UInt<8>,
+                                /* offset = 8 */
+                                1: SInt<8>,
+                            },
+                        },
+                    },
+                    TraceMemPort {
+                        name: "w1",
+                        bundle: TraceBundle {
+                            name: "w1",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(17),
+                                    name: "addr",
+                                    ty: UInt<4>,
+                                    flow: Sink,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(18),
+                                    name: "en",
+                                    flow: Sink,
+                                },
+                                TraceClock {
+                                    location: TraceScalarId(19),
+                                    name: "clk",
+                                    flow: Sink,
+                                },
+                                TraceBundle {
+                                    name: "data",
+                                    fields: [
+                                        TraceUInt {
+                                            location: TraceScalarId(20),
+                                            name: "0",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceSInt {
+                                            location: TraceScalarId(21),
+                                            name: "1",
+                                            ty: SInt<8>,
+                                            flow: Sink,
+                                        },
+                                    ],
+                                    ty: Bundle {
+                                        /* offset = 0 */
+                                        0: UInt<8>,
+                                        /* offset = 8 */
+                                        1: SInt<8>,
+                                    },
+                                    flow: Sink,
+                                },
+                                TraceBundle {
+                                    name: "mask",
+                                    fields: [
+                                        TraceBool {
+                                            location: TraceScalarId(22),
+                                            name: "0",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(23),
+                                            name: "1",
+                                            flow: Sink,
+                                        },
+                                    ],
+                                    ty: Bundle {
+                                        /* offset = 0 */
+                                        0: Bool,
+                                        /* offset = 1 */
+                                        1: Bool,
+                                    },
+                                    flow: Sink,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                addr: UInt<4>,
+                                /* offset = 4 */
+                                en: Bool,
+                                /* offset = 5 */
+                                clk: Clock,
+                                /* offset = 6 */
+                                data: Bundle {
+                                    /* offset = 0 */
+                                    0: UInt<8>,
+                                    /* offset = 8 */
+                                    1: SInt<8>,
+                                },
+                                /* offset = 22 */
+                                mask: Bundle {
+                                    /* offset = 0 */
+                                    0: Bool,
+                                    /* offset = 1 */
+                                    1: Bool,
+                                },
+                            },
+                            flow: Sink,
+                        },
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<4>,
+                            /* offset = 4 */
+                            en: Bool,
+                            /* offset = 5 */
+                            clk: Clock,
+                            /* offset = 6 */
+                            data: Bundle {
+                                /* offset = 0 */
+                                0: UInt<8>,
+                                /* offset = 8 */
+                                1: SInt<8>,
+                            },
+                            /* offset = 22 */
+                            mask: Bundle {
+                                /* offset = 0 */
+                                0: Bool,
+                                /* offset = 1 */
+                                1: Bool,
+                            },
+                        },
+                    },
+                ],
+                array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<4>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<8>,
+            },
+            state: 0xb0,
+            last_state: 0xb0,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(4),
+                ty: SInt<8>,
+            },
+            state: 0xc0,
+            last_state: 0xc0,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(5),
+                ty: UInt<4>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(6),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(7),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(8),
+                ty: UInt<8>,
+            },
+            state: 0xd0,
+            last_state: 0xd0,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(9),
+                ty: SInt<8>,
+            },
+            state: 0xe0,
+            last_state: 0xe0,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(10),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(11),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(12),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(12),
+                ty: UInt<4>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(13),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(13),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(14),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(14),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(15),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(15),
+                ty: UInt<8>,
+            },
+            state: 0xb0,
+            last_state: 0xb0,
+        },
+        SimTrace {
+            id: TraceScalarId(16),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(16),
+                ty: SInt<8>,
+            },
+            state: 0xc0,
+            last_state: 0xc0,
+        },
+        SimTrace {
+            id: TraceScalarId(17),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(17),
+                ty: UInt<4>,
+            },
+            state: 0x2,
+            last_state: 0x2,
+        },
+        SimTrace {
+            id: TraceScalarId(18),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(18),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(19),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(19),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(20),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(20),
+                ty: UInt<8>,
+            },
+            state: 0xd0,
+            last_state: 0xd0,
+        },
+        SimTrace {
+            id: TraceScalarId(21),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(21),
+                ty: SInt<8>,
+            },
+            state: 0xe0,
+            last_state: 0xe0,
+        },
+        SimTrace {
+            id: TraceScalarId(22),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(22),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(23),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(23),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+    ],
+    trace_memories: {
+        StatePartIndex<Memories>(0): TraceMem {
+            id: TraceMemoryId(0),
+            name: "mem",
+            stride: 16,
+            element_type: TraceBundle {
+                name: "mem",
+                fields: [
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 16,
+                            stride: 16,
+                            start: 0,
+                            len: 8,
+                        },
+                        name: "0",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceSInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 16,
+                            stride: 16,
+                            start: 8,
+                            len: 8,
+                        },
+                        name: "1",
+                        ty: SInt<8>,
+                        flow: Duplex,
+                    },
+                ],
+                ty: Bundle {
+                    /* offset = 0 */
+                    0: UInt<8>,
+                    /* offset = 8 */
+                    1: SInt<8>,
+                },
+                flow: Duplex,
+            },
+            ports: [
+                TraceMemPort {
+                    name: "r0",
+                    bundle: TraceBundle {
+                        name: "r0",
+                        fields: [
+                            TraceUInt {
+                                location: TraceScalarId(12),
+                                name: "addr",
+                                ty: UInt<4>,
+                                flow: Sink,
+                            },
+                            TraceBool {
+                                location: TraceScalarId(13),
+                                name: "en",
+                                flow: Sink,
+                            },
+                            TraceClock {
+                                location: TraceScalarId(14),
+                                name: "clk",
+                                flow: Sink,
+                            },
+                            TraceBundle {
+                                name: "data",
+                                fields: [
+                                    TraceUInt {
+                                        location: TraceScalarId(15),
+                                        name: "0",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceSInt {
+                                        location: TraceScalarId(16),
+                                        name: "1",
+                                        ty: SInt<8>,
+                                        flow: Source,
+                                    },
+                                ],
+                                ty: Bundle {
+                                    /* offset = 0 */
+                                    0: UInt<8>,
+                                    /* offset = 8 */
+                                    1: SInt<8>,
+                                },
+                                flow: Source,
+                            },
+                        ],
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<4>,
+                            /* offset = 4 */
+                            en: Bool,
+                            /* offset = 5 */
+                            clk: Clock,
+                            #[hdl(flip)] /* offset = 6 */
+                            data: Bundle {
+                                /* offset = 0 */
+                                0: UInt<8>,
+                                /* offset = 8 */
+                                1: SInt<8>,
+                            },
+                        },
+                        flow: Sink,
+                    },
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<4>,
+                        /* offset = 4 */
+                        en: Bool,
+                        /* offset = 5 */
+                        clk: Clock,
+                        #[hdl(flip)] /* offset = 6 */
+                        data: Bundle {
+                            /* offset = 0 */
+                            0: UInt<8>,
+                            /* offset = 8 */
+                            1: SInt<8>,
+                        },
+                    },
+                },
+                TraceMemPort {
+                    name: "w1",
+                    bundle: TraceBundle {
+                        name: "w1",
+                        fields: [
+                            TraceUInt {
+                                location: TraceScalarId(17),
+                                name: "addr",
+                                ty: UInt<4>,
+                                flow: Sink,
+                            },
+                            TraceBool {
+                                location: TraceScalarId(18),
+                                name: "en",
+                                flow: Sink,
+                            },
+                            TraceClock {
+                                location: TraceScalarId(19),
+                                name: "clk",
+                                flow: Sink,
+                            },
+                            TraceBundle {
+                                name: "data",
+                                fields: [
+                                    TraceUInt {
+                                        location: TraceScalarId(20),
+                                        name: "0",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceSInt {
+                                        location: TraceScalarId(21),
+                                        name: "1",
+                                        ty: SInt<8>,
+                                        flow: Sink,
+                                    },
+                                ],
+                                ty: Bundle {
+                                    /* offset = 0 */
+                                    0: UInt<8>,
+                                    /* offset = 8 */
+                                    1: SInt<8>,
+                                },
+                                flow: Sink,
+                            },
+                            TraceBundle {
+                                name: "mask",
+                                fields: [
+                                    TraceBool {
+                                        location: TraceScalarId(22),
+                                        name: "0",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(23),
+                                        name: "1",
+                                        flow: Sink,
+                                    },
+                                ],
+                                ty: Bundle {
+                                    /* offset = 0 */
+                                    0: Bool,
+                                    /* offset = 1 */
+                                    1: Bool,
+                                },
+                                flow: Sink,
+                            },
+                        ],
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<4>,
+                            /* offset = 4 */
+                            en: Bool,
+                            /* offset = 5 */
+                            clk: Clock,
+                            /* offset = 6 */
+                            data: Bundle {
+                                /* offset = 0 */
+                                0: UInt<8>,
+                                /* offset = 8 */
+                                1: SInt<8>,
+                            },
+                            /* offset = 22 */
+                            mask: Bundle {
+                                /* offset = 0 */
+                                0: Bool,
+                                /* offset = 1 */
+                                1: Bool,
+                            },
+                        },
+                        flow: Sink,
+                    },
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<4>,
+                        /* offset = 4 */
+                        en: Bool,
+                        /* offset = 5 */
+                        clk: Clock,
+                        /* offset = 6 */
+                        data: Bundle {
+                            /* offset = 0 */
+                            0: UInt<8>,
+                            /* offset = 8 */
+                            1: SInt<8>,
+                        },
+                        /* offset = 22 */
+                        mask: Bundle {
+                            /* offset = 0 */
+                            0: Bool,
+                            /* offset = 1 */
+                            1: Bool,
+                        },
+                    },
+                },
+            ],
+            array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
+        },
+    },
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 22 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+        StatePartIndex<SmallSlots>(6),
+    ],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/memories.vcd b/crates/fayalite/tests/sim/expected/memories.vcd
new file mode 100644
index 0000000..72af410
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/memories.vcd
@@ -0,0 +1,408 @@
+$timescale 1 ps $end
+$scope module memories $end
+$scope struct r $end
+$var wire 4 ! addr $end
+$var wire 1 " en $end
+$var wire 1 # clk $end
+$scope struct data $end
+$var wire 8 $ \0 $end
+$var wire 8 % \1 $end
+$upscope $end
+$upscope $end
+$scope struct w $end
+$var wire 4 & addr $end
+$var wire 1 ' en $end
+$var wire 1 ( clk $end
+$scope struct data $end
+$var wire 8 ) \0 $end
+$var wire 8 * \1 $end
+$upscope $end
+$scope struct mask $end
+$var wire 1 + \0 $end
+$var wire 1 , \1 $end
+$upscope $end
+$upscope $end
+$scope struct mem $end
+$scope struct contents $end
+$scope struct [0] $end
+$scope struct mem $end
+$var reg 8 9 \0 $end
+$var reg 8 I \1 $end
+$upscope $end
+$upscope $end
+$scope struct [1] $end
+$scope struct mem $end
+$var reg 8 : \0 $end
+$var reg 8 J \1 $end
+$upscope $end
+$upscope $end
+$scope struct [2] $end
+$scope struct mem $end
+$var reg 8 ; \0 $end
+$var reg 8 K \1 $end
+$upscope $end
+$upscope $end
+$scope struct [3] $end
+$scope struct mem $end
+$var reg 8 < \0 $end
+$var reg 8 L \1 $end
+$upscope $end
+$upscope $end
+$scope struct [4] $end
+$scope struct mem $end
+$var reg 8 = \0 $end
+$var reg 8 M \1 $end
+$upscope $end
+$upscope $end
+$scope struct [5] $end
+$scope struct mem $end
+$var reg 8 > \0 $end
+$var reg 8 N \1 $end
+$upscope $end
+$upscope $end
+$scope struct [6] $end
+$scope struct mem $end
+$var reg 8 ? \0 $end
+$var reg 8 O \1 $end
+$upscope $end
+$upscope $end
+$scope struct [7] $end
+$scope struct mem $end
+$var reg 8 @ \0 $end
+$var reg 8 P \1 $end
+$upscope $end
+$upscope $end
+$scope struct [8] $end
+$scope struct mem $end
+$var reg 8 A \0 $end
+$var reg 8 Q \1 $end
+$upscope $end
+$upscope $end
+$scope struct [9] $end
+$scope struct mem $end
+$var reg 8 B \0 $end
+$var reg 8 R \1 $end
+$upscope $end
+$upscope $end
+$scope struct [10] $end
+$scope struct mem $end
+$var reg 8 C \0 $end
+$var reg 8 S \1 $end
+$upscope $end
+$upscope $end
+$scope struct [11] $end
+$scope struct mem $end
+$var reg 8 D \0 $end
+$var reg 8 T \1 $end
+$upscope $end
+$upscope $end
+$scope struct [12] $end
+$scope struct mem $end
+$var reg 8 E \0 $end
+$var reg 8 U \1 $end
+$upscope $end
+$upscope $end
+$scope struct [13] $end
+$scope struct mem $end
+$var reg 8 F \0 $end
+$var reg 8 V \1 $end
+$upscope $end
+$upscope $end
+$scope struct [14] $end
+$scope struct mem $end
+$var reg 8 G \0 $end
+$var reg 8 W \1 $end
+$upscope $end
+$upscope $end
+$scope struct [15] $end
+$scope struct mem $end
+$var reg 8 H \0 $end
+$var reg 8 X \1 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct r0 $end
+$var wire 4 - addr $end
+$var wire 1 . en $end
+$var wire 1 / clk $end
+$scope struct data $end
+$var wire 8 0 \0 $end
+$var wire 8 1 \1 $end
+$upscope $end
+$upscope $end
+$scope struct w1 $end
+$var wire 4 2 addr $end
+$var wire 1 3 en $end
+$var wire 1 4 clk $end
+$scope struct data $end
+$var wire 8 5 \0 $end
+$var wire 8 6 \1 $end
+$upscope $end
+$scope struct mask $end
+$var wire 1 7 \0 $end
+$var wire 1 8 \1 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+b1 9
+b100011 I
+b1 :
+b100011 J
+b1 ;
+b100011 K
+b1 <
+b100011 L
+b1 =
+b100011 M
+b1 >
+b100011 N
+b1 ?
+b100011 O
+b1 @
+b100011 P
+b1 A
+b100011 Q
+b1 B
+b100011 R
+b1 C
+b100011 S
+b1 D
+b100011 T
+b1 E
+b100011 U
+b1 F
+b100011 V
+b1 G
+b100011 W
+b1 H
+b100011 X
+b0 !
+0"
+0#
+b0 $
+b0 %
+b0 &
+0'
+0(
+b0 )
+b0 *
+0+
+0,
+b0 -
+0.
+0/
+b0 0
+b0 1
+b0 2
+03
+04
+b0 5
+b0 6
+07
+08
+$end
+#1000000
+1#
+1(
+1/
+14
+#2000000
+1"
+0#
+b1 $
+b100011 %
+1'
+0(
+b10000 )
+b100000 *
+1+
+1,
+1.
+0/
+b1 0
+b100011 1
+13
+04
+b10000 5
+b100000 6
+17
+18
+#3000000
+b10000 9
+b100000 I
+1#
+1(
+1/
+14
+b10000 $
+b100000 %
+b10000 0
+b100000 1
+#4000000
+0#
+0(
+b110000 )
+b1000000 *
+0+
+0/
+04
+b110000 5
+b1000000 6
+07
+#5000000
+b10000 9
+b1000000 I
+1#
+1(
+1/
+14
+b1000000 %
+b1000000 1
+#6000000
+0#
+0(
+b1010000 )
+b1100000 *
+1+
+0,
+0/
+04
+b1010000 5
+b1100000 6
+17
+08
+#7000000
+b1010000 9
+b1000000 I
+1#
+1(
+1/
+14
+b1010000 $
+b1010000 0
+#8000000
+0#
+0(
+b1110000 )
+b10000000 *
+0+
+0/
+04
+b1110000 5
+b10000000 6
+07
+#9000000
+1#
+1(
+1/
+14
+#10000000
+0#
+0'
+0(
+b10010000 )
+b10100000 *
+0/
+03
+04
+b10010000 5
+b10100000 6
+#11000000
+1#
+1(
+1/
+14
+#12000000
+0#
+b1 &
+1'
+0(
+1+
+1,
+0/
+b1 2
+13
+04
+17
+18
+#13000000
+b10010000 :
+b10100000 J
+1#
+1(
+1/
+14
+#14000000
+0#
+b10 &
+0(
+b10110000 )
+b11000000 *
+0/
+b10 2
+04
+b10110000 5
+b11000000 6
+#15000000
+b10110000 ;
+b11000000 K
+1#
+1(
+1/
+14
+#16000000
+0#
+0'
+0(
+b11010000 )
+b11100000 *
+0/
+03
+04
+b11010000 5
+b11100000 6
+#17000000
+1#
+1(
+1/
+14
+#18000000
+b1 !
+0#
+b10010000 $
+b10100000 %
+0(
+b1 -
+0/
+b10010000 0
+b10100000 1
+04
+#19000000
+1#
+1(
+1/
+14
+#20000000
+b10 !
+0#
+b10110000 $
+b11000000 %
+0(
+b10 -
+0/
+b10110000 0
+b11000000 1
+04
+#21000000
+1#
+1(
+1/
+14
+#22000000
+0#
+0(
+0/
+04
diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt
index 8c68108..5c2b7eb 100644
--- a/crates/fayalite/tests/sim/expected/mod1.txt
+++ b/crates/fayalite/tests/sim/expected/mod1.txt
@@ -93,86 +93,86 @@ Simulation {
             insns: [
                 // at: module-XXXXXXXXXX.rs:4:1
                 0: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(6), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(2), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
                 },
                 1: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(4), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(0), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:2:1
                 2: Copy {
-                    dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(10), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(6), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
                 },
                 3: Copy {
-                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(4), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX-2.rs:1:1
                 4: Const {
-                    dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
-                    value: 15,
+                    dest: StatePartIndex<BigSlots>(16), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    value: 0xf,
                 },
                 5: Const {
-                    dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
-                    value: 5,
+                    dest: StatePartIndex<BigSlots>(14), // (0x5) SlotDebugData { name: "", ty: UInt<4> },
+                    value: 0x5,
                 },
                 6: CmpLt {
-                    dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
-                    rhs: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<BigSlots>(14), // (0x5) SlotDebugData { name: "", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
                 },
                 7: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(13), // (0xe) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(10), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
                     dest_width: 4,
                 },
                 // at: module-XXXXXXXXXX-2.rs:7:1
                 8: Copy {
-                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(13), // (0xe) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX-2.rs:8:1
                 9: BranchIfZero {
                     target: 11,
-                    value: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX-2.rs:9:1
                 10: Copy {
-                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(16), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:2:1
                 11: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(7), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
                 12: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(3), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(7), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX-2.rs:1:1
                 13: CastToSInt {
-                    dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(12), // (-0x2) SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
                     dest_width: 2,
                 },
                 // at: module-XXXXXXXXXX-2.rs:6:1
                 14: Copy {
-                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(9), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(12), // (-0x2) SlotDebugData { name: "", ty: SInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:2:1
                 15: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(5), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(9), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
                 16: Copy {
-                    dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(1), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(5), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 17: Return,
@@ -806,4 +806,5 @@ Simulation {
     ],
     instant: 2 μs,
     clocks_triggered: [],
+    ..
 }
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt
index 007c15b..73f6263 100644
--- a/crates/fayalite/tests/sim/expected/shift_register.txt
+++ b/crates/fayalite/tests/sim/expected/shift_register.txt
@@ -94,132 +94,133 @@ Simulation {
             insns: [
                 // at: module-XXXXXXXXXX.rs:13:1
                 0: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
-                    src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
+                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:12:1
                 1: Copy {
-                    dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:10:1
                 2: Copy {
-                    dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
                 3: Copy {
-                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
                 4: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
                 5: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
+                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 6: Const {
-                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
-                    value: 0,
+                    dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    value: 0x0,
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
                 7: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
+                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
                 },
                 8: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 9: BranchIfSmallZero {
                     target: 14,
-                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 10: BranchIfSmallNonZero {
                     target: 13,
-                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 11: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
-                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
                 },
                 12: Branch {
                     target: 14,
                 },
                 13: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:7:1
                 14: BranchIfSmallZero {
                     target: 19,
-                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 15: BranchIfSmallNonZero {
                     target: 18,
-                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 16: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
                 },
                 17: Branch {
                     target: 19,
                 },
                 18: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:9:1
                 19: BranchIfSmallZero {
                     target: 24,
-                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 20: BranchIfSmallNonZero {
                     target: 23,
-                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 21: Copy {
-                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
-                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                    src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
                 },
                 22: Branch {
                     target: 24,
                 },
                 23: Copy {
-                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
                 24: BranchIfSmallZero {
                     target: 29,
-                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 25: BranchIfSmallNonZero {
                     target: 28,
-                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
                 26: Copy {
-                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
-                    src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
                 },
                 27: Branch {
                     target: 29,
                 },
                 28: Copy {
-                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
-                29: NotSmall {
-                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                29: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 30: Return,
@@ -233,7 +234,7 @@ Simulation {
         },
         small_slots: StatePart {
             value: [
-                18446744073709551614,
+                0,
                 0,
                 1,
                 0,
@@ -678,4 +679,5 @@ Simulation {
     clocks_triggered: [
         StatePartIndex<SmallSlots>(1),
     ],
+    ..
 }
\ No newline at end of file

From c756aeec704e3abcb54b023b6f215d25338701ca Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 12 Dec 2024 20:50:41 -0800
Subject: [PATCH 136/190] tests/sim: add test for memory rw port

---
 crates/fayalite/tests/sim.rs                  |  273 +++
 .../fayalite/tests/sim/expected/memories2.txt | 1694 +++++++++++++++++
 .../fayalite/tests/sim/expected/memories2.vcd |  363 ++++
 3 files changed, 2330 insertions(+)
 create mode 100644 crates/fayalite/tests/sim/expected/memories2.txt
 create mode 100644 crates/fayalite/tests/sim/expected/memories2.vcd

diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 2b8f276..3fc643c 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -694,4 +694,277 @@ fn test_memories() {
     }
 }
 
+#[hdl_module(outline_generated)]
+pub fn memories2() {
+    #[hdl]
+    let rw: fayalite::memory::ReadWriteStruct<UInt<2>, ConstUsize<3>> = m.input();
+    #[hdl]
+    let mut mem = memory_with_init([HdlSome(true); 5]);
+    mem.read_latency(1);
+    mem.write_latency(NonZeroUsize::new(1).unwrap());
+    mem.read_under_write(ReadUnderWrite::New);
+    let rw_port = mem.new_rw_port();
+    connect_any(rw_port.addr, rw.addr);
+    connect(rw_port.en, rw.en);
+    connect(rw_port.clk, rw.clk);
+    connect_any(rw.rdata, rw_port.rdata.cast_to_bits());
+    connect(rw_port.wmode, rw.wmode);
+    connect(rw_port.wdata, HdlNone());
+    #[hdl]
+    if rw.wdata[0] {
+        connect(rw_port.wdata, HdlSome(rw.wdata[1]));
+    }
+    connect(rw_port.wmask, rw.wmask);
+}
+
+#[hdl]
+#[test]
+fn test_memories2() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(memories2());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_clock(sim.io().rw.clk, false);
+    #[derive(Debug, PartialEq, Eq)]
+    struct IO {
+        addr: u8,
+        en: bool,
+        rdata: u8,
+        wmode: bool,
+        wdata: u8,
+        wmask: bool,
+    }
+    let io_cycles = [
+        IO {
+            addr: 0,
+            en: false,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 0,
+            en: true,
+            rdata: 0x3,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 0,
+            en: false,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 0,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 0,
+            wmask: true,
+        },
+        IO {
+            addr: 0,
+            en: true,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 0,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 3,
+            wmask: false,
+        },
+        IO {
+            addr: 1,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 1,
+            wmask: true,
+        },
+        IO {
+            addr: 2,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 2,
+            wmask: true,
+        },
+        IO {
+            addr: 3,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 3,
+            wmask: true,
+        },
+        IO {
+            addr: 4,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 2,
+            wmask: true,
+        },
+        IO {
+            addr: 5,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 1,
+            wmask: true,
+        },
+        IO {
+            addr: 6,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 1,
+            wmask: true,
+        },
+        IO {
+            addr: 7,
+            en: true,
+            rdata: 0,
+            wmode: true,
+            wdata: 1,
+            wmask: true,
+        },
+        IO {
+            addr: 7,
+            en: true,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 6,
+            en: true,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 5,
+            en: true,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 4,
+            en: true,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 3,
+            en: true,
+            rdata: 3,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 2,
+            en: true,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 0,
+            en: true,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 1,
+            en: true,
+            rdata: 1,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+        IO {
+            addr: 0,
+            en: false,
+            rdata: 0,
+            wmode: false,
+            wdata: 0,
+            wmask: false,
+        },
+    ];
+    for (
+        cycle,
+        expected @ IO {
+            addr,
+            en,
+            rdata: _,
+            wmode,
+            wdata,
+            wmask,
+        },
+    ) in io_cycles.into_iter().enumerate()
+    {
+        sim.write_bool_or_int(sim.io().rw.addr, addr.cast_to_static());
+        sim.write_bool(sim.io().rw.en, en);
+        sim.write_bool(sim.io().rw.wmode, wmode);
+        sim.write_bool_or_int(sim.io().rw.wdata, wdata.cast_to_static());
+        sim.write_bool(sim.io().rw.wmask, wmask);
+        sim.advance_time(SimDuration::from_nanos(250));
+        sim.write_clock(sim.io().rw.clk, true);
+        sim.advance_time(SimDuration::from_nanos(250));
+        let io = IO {
+            addr,
+            en,
+            rdata: sim
+                .read_bool_or_int(sim.io().rw.rdata)
+                .to_bigint()
+                .try_into()
+                .expect("known to be in range"),
+            wmode,
+            wdata,
+            wmask,
+        };
+        assert_eq!(
+            expected,
+            io,
+            "cycle: {cycle}\nvcd:\n{}",
+            String::from_utf8(writer.take()).unwrap(),
+        );
+        sim.advance_time(SimDuration::from_nanos(250));
+        sim.write_clock(sim.io().rw.clk, false);
+        sim.advance_time(SimDuration::from_nanos(250));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/memories2.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/memories2.txt") {
+        panic!();
+    }
+}
+
 // TODO: add more tests for memories
diff --git a/crates/fayalite/tests/sim/expected/memories2.txt b/crates/fayalite/tests/sim/expected/memories2.txt
new file mode 100644
index 0000000..5d90815
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/memories2.txt
@@ -0,0 +1,1694 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 11,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome,
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome,
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 36,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.addr",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 1,
+                    debug_data: [
+                        (),
+                    ],
+                    layout_data: [
+                        MemoryData {
+                            array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
+                            data: [
+                                // len = 0x5
+                                [0x0]: 0x3,
+                                [0x1]: 0x3,
+                                [0x2]: 0x3,
+                                [0x3]: 0x3,
+                                [0x4]: 0x3,
+                            ],
+                        },
+                    ],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:13:1
+                0: Copy {
+                    dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                1: SliceInt {
+                    dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", ty: UInt<2> },
+                    start: 1,
+                    len: 1,
+                },
+                2: Copy {
+                    dest: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                3: Const {
+                    dest: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    value: 0x1,
+                },
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                5: Copy {
+                    dest: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                6: Copy {
+                    dest: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: ".1", ty: Bool },
+                },
+                7: Shl {
+                    dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 1,
+                },
+                8: Or {
+                    dest: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                9: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                    dest_width: 2,
+                },
+                10: Copy {
+                    dest: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    src: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                11: SliceInt {
+                    dest: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", ty: UInt<2> },
+                    start: 0,
+                    len: 1,
+                },
+                12: Copy {
+                    dest: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                13: Const {
+                    dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    value: 0x0,
+                },
+                14: Copy {
+                    dest: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    src: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                15: Copy {
+                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    src: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                16: BranchIfZero {
+                    target: 18,
+                    value: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:12:1
+                17: Copy {
+                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    src: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                18: Copy {
+                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode", ty: Bool },
+                    src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:7:1
+                19: Copy {
+                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.clk", ty: Clock },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                20: Copy {
+                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.en", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                21: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(0), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.addr", ty: UInt<3> },
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                22: BranchIfSmallZero {
+                    target: 26,
+                    value: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                23: BranchIfSmallNonZero {
+                    target: 26,
+                    value: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                24: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
+                            //     data: [
+                            //         // len = 0x5
+                            //         [0x0]: 0x0,
+                            //         [0x1]: 0x1,
+                            //         [0x2]: 0x0,
+                            //         [0x3]: 0x3,
+                            //         [0x4]: 0x0,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 2,
+                    start: 0,
+                    width: 2,
+                },
+                25: Branch {
+                    target: 27,
+                },
+                26: Const {
+                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    value: 0x0,
+                },
+                27: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode", ty: Bool },
+                },
+                28: CastBigToArrayIndex {
+                    dest: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr", ty: UInt<3> },
+                },
+                29: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en", ty: Bool },
+                },
+                30: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk", ty: Clock },
+                },
+                31: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                32: Copy {
+                    dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                },
+                33: SliceInt {
+                    dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 1,
+                    len: 1,
+                },
+                34: Copy {
+                    dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                35: AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
+                    lhs: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                36: Copy {
+                    dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                },
+                37: SliceInt {
+                    dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 1,
+                    len: 1,
+                },
+                38: Copy {
+                    dest: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                39: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                40: AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
+                    lhs: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                41: BranchIfSmallZero {
+                    target: 51,
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                42: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                },
+                43: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                44: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
+                },
+                45: Copy {
+                    dest: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask", ty: Bool },
+                },
+                46: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                47: BranchIfSmallZero {
+                    target: 51,
+                    value: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                48: BranchIfSmallZero {
+                    target: 51,
+                    value: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                49: BranchIfZero {
+                    target: 51,
+                    value: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                50: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
+                            //     data: [
+                            //         // len = 0x5
+                            //         [0x0]: 0x0,
+                            //         [0x1]: 0x1,
+                            //         [0x2]: 0x0,
+                            //         [0x3]: 0x3,
+                            //         [0x4]: 0x0,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 2,
+                    start: 0,
+                    width: 2,
+                },
+                51: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                52: Return,
+            ],
+            ..
+        },
+        pc: 52,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [
+                MemoryData {
+                    array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
+                    data: [
+                        // len = 0x5
+                        [0x0]: 0x0,
+                        [0x1]: 0x1,
+                        [0x2]: 0x0,
+                        [0x3]: 0x3,
+                        [0x4]: 0x0,
+                    ],
+                },
+            ],
+        },
+        small_slots: StatePart {
+            value: [
+                0,
+                0,
+                1,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                1,
+                0,
+                1,
+                0,
+                0,
+                0,
+                0,
+                1,
+                1,
+                1,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::memories2,
+        instantiated: Module {
+            name: memories2,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::memories2,
+            instantiated: Module {
+                name: memories2,
+                ..
+            },
+        }.rw: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    /* offset = 0 */
+                    addr: UInt<3>,
+                    /* offset = 3 */
+                    en: Bool,
+                    /* offset = 4 */
+                    clk: Clock,
+                    #[hdl(flip)] /* offset = 5 */
+                    rdata: UInt<2>,
+                    /* offset = 7 */
+                    wmode: Bool,
+                    /* offset = 8 */
+                    wdata: UInt<2>,
+                    /* offset = 10 */
+                    wmask: Bool,
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 7,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.addr",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: UInt<3>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: UInt<3>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Bool,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Bool,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(2),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Clock,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Clock,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(3),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: UInt<2>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: UInt<2>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(4),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Bool,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Bool,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(5),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: UInt<2>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: UInt<2>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(6),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Bool,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Bool,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 7 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories2,
+            instantiated: Module {
+                name: memories2,
+                ..
+            },
+        }.rw.addr: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<3>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories2,
+            instantiated: Module {
+                name: memories2,
+                ..
+            },
+        }.rw.clk: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories2,
+            instantiated: Module {
+                name: memories2,
+                ..
+            },
+        }.rw.en: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories2,
+            instantiated: Module {
+                name: memories2,
+                ..
+            },
+        }.rw.rdata: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<2>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories2,
+            instantiated: Module {
+                name: memories2,
+                ..
+            },
+        }.rw.wdata: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<2>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories2,
+            instantiated: Module {
+                name: memories2,
+                ..
+            },
+        }.rw.wmask: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 6, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories2,
+            instantiated: Module {
+                name: memories2,
+                ..
+            },
+        }.rw.wmode: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "memories2",
+        children: [
+            TraceModuleIO {
+                name: "rw",
+                child: TraceBundle {
+                    name: "rw",
+                    fields: [
+                        TraceUInt {
+                            location: TraceScalarId(0),
+                            name: "addr",
+                            ty: UInt<3>,
+                            flow: Source,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(1),
+                            name: "en",
+                            flow: Source,
+                        },
+                        TraceClock {
+                            location: TraceScalarId(2),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(3),
+                            name: "rdata",
+                            ty: UInt<2>,
+                            flow: Sink,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(4),
+                            name: "wmode",
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(5),
+                            name: "wdata",
+                            ty: UInt<2>,
+                            flow: Source,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(6),
+                            name: "wmask",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<3>,
+                        /* offset = 3 */
+                        en: Bool,
+                        /* offset = 4 */
+                        clk: Clock,
+                        #[hdl(flip)] /* offset = 5 */
+                        rdata: UInt<2>,
+                        /* offset = 7 */
+                        wmode: Bool,
+                        /* offset = 8 */
+                        wdata: UInt<2>,
+                        /* offset = 10 */
+                        wmask: Bool,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    addr: UInt<3>,
+                    /* offset = 3 */
+                    en: Bool,
+                    /* offset = 4 */
+                    clk: Clock,
+                    #[hdl(flip)] /* offset = 5 */
+                    rdata: UInt<2>,
+                    /* offset = 7 */
+                    wmode: Bool,
+                    /* offset = 8 */
+                    wdata: UInt<2>,
+                    /* offset = 10 */
+                    wmask: Bool,
+                },
+                flow: Source,
+            },
+            TraceMem {
+                id: TraceMemoryId(0),
+                name: "mem",
+                stride: 2,
+                element_type: TraceEnumWithFields {
+                    name: "mem",
+                    discriminant: TraceEnumDiscriminant {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 5,
+                            stride: 2,
+                            start: 0,
+                            len: 1,
+                        },
+                        name: "$tag",
+                        ty: Enum {
+                            HdlNone,
+                            HdlSome(Bool),
+                        },
+                        flow: Duplex,
+                    },
+                    non_empty_fields: [
+                        TraceBool {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 5,
+                                stride: 2,
+                                start: 1,
+                                len: 1,
+                            },
+                            name: "HdlSome",
+                            flow: Duplex,
+                        },
+                    ],
+                    ty: Enum {
+                        HdlNone,
+                        HdlSome(Bool),
+                    },
+                    flow: Duplex,
+                },
+                ports: [
+                    TraceMemPort {
+                        name: "rw0",
+                        bundle: TraceBundle {
+                            name: "rw0",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(7),
+                                    name: "addr",
+                                    ty: UInt<3>,
+                                    flow: Sink,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(8),
+                                    name: "en",
+                                    flow: Sink,
+                                },
+                                TraceClock {
+                                    location: TraceScalarId(9),
+                                    name: "clk",
+                                    flow: Sink,
+                                },
+                                TraceEnumWithFields {
+                                    name: "rdata",
+                                    discriminant: TraceEnumDiscriminant {
+                                        location: TraceScalarId(10),
+                                        name: "$tag",
+                                        ty: Enum {
+                                            HdlNone,
+                                            HdlSome(Bool),
+                                        },
+                                        flow: Source,
+                                    },
+                                    non_empty_fields: [
+                                        TraceBool {
+                                            location: TraceScalarId(11),
+                                            name: "HdlSome",
+                                            flow: Source,
+                                        },
+                                    ],
+                                    ty: Enum {
+                                        HdlNone,
+                                        HdlSome(Bool),
+                                    },
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(12),
+                                    name: "wmode",
+                                    flow: Sink,
+                                },
+                                TraceEnumWithFields {
+                                    name: "wdata",
+                                    discriminant: TraceEnumDiscriminant {
+                                        location: TraceScalarId(13),
+                                        name: "$tag",
+                                        ty: Enum {
+                                            HdlNone,
+                                            HdlSome(Bool),
+                                        },
+                                        flow: Sink,
+                                    },
+                                    non_empty_fields: [
+                                        TraceBool {
+                                            location: TraceScalarId(14),
+                                            name: "HdlSome",
+                                            flow: Source,
+                                        },
+                                    ],
+                                    ty: Enum {
+                                        HdlNone,
+                                        HdlSome(Bool),
+                                    },
+                                    flow: Sink,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(15),
+                                    name: "wmask",
+                                    flow: Sink,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                addr: UInt<3>,
+                                /* offset = 3 */
+                                en: Bool,
+                                /* offset = 4 */
+                                clk: Clock,
+                                #[hdl(flip)] /* offset = 5 */
+                                rdata: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                                /* offset = 7 */
+                                wmode: Bool,
+                                /* offset = 8 */
+                                wdata: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                                /* offset = 10 */
+                                wmask: Bool,
+                            },
+                            flow: Sink,
+                        },
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<3>,
+                            /* offset = 3 */
+                            en: Bool,
+                            /* offset = 4 */
+                            clk: Clock,
+                            #[hdl(flip)] /* offset = 5 */
+                            rdata: Enum {
+                                HdlNone,
+                                HdlSome(Bool),
+                            },
+                            /* offset = 7 */
+                            wmode: Bool,
+                            /* offset = 8 */
+                            wdata: Enum {
+                                HdlNone,
+                                HdlSome(Bool),
+                            },
+                            /* offset = 10 */
+                            wmask: Bool,
+                        },
+                    },
+                ],
+                array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<3>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<2>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(4),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(5),
+                ty: UInt<2>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(6),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(7),
+                ty: UInt<3>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(8),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(9),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: EnumDiscriminant {
+                index: StatePartIndex<SmallSlots>(0),
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Bool),
+                },
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(16),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(12),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(11),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(13),
+            kind: EnumDiscriminant {
+                index: StatePartIndex<SmallSlots>(1),
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Bool),
+                },
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(14),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(19),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(15),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(13),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+    ],
+    trace_memories: {
+        StatePartIndex<Memories>(0): TraceMem {
+            id: TraceMemoryId(0),
+            name: "mem",
+            stride: 2,
+            element_type: TraceEnumWithFields {
+                name: "mem",
+                discriminant: TraceEnumDiscriminant {
+                    location: TraceMemoryLocation {
+                        id: TraceMemoryId(0),
+                        depth: 5,
+                        stride: 2,
+                        start: 0,
+                        len: 1,
+                    },
+                    name: "$tag",
+                    ty: Enum {
+                        HdlNone,
+                        HdlSome(Bool),
+                    },
+                    flow: Duplex,
+                },
+                non_empty_fields: [
+                    TraceBool {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 5,
+                            stride: 2,
+                            start: 1,
+                            len: 1,
+                        },
+                        name: "HdlSome",
+                        flow: Duplex,
+                    },
+                ],
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Bool),
+                },
+                flow: Duplex,
+            },
+            ports: [
+                TraceMemPort {
+                    name: "rw0",
+                    bundle: TraceBundle {
+                        name: "rw0",
+                        fields: [
+                            TraceUInt {
+                                location: TraceScalarId(7),
+                                name: "addr",
+                                ty: UInt<3>,
+                                flow: Sink,
+                            },
+                            TraceBool {
+                                location: TraceScalarId(8),
+                                name: "en",
+                                flow: Sink,
+                            },
+                            TraceClock {
+                                location: TraceScalarId(9),
+                                name: "clk",
+                                flow: Sink,
+                            },
+                            TraceEnumWithFields {
+                                name: "rdata",
+                                discriminant: TraceEnumDiscriminant {
+                                    location: TraceScalarId(10),
+                                    name: "$tag",
+                                    ty: Enum {
+                                        HdlNone,
+                                        HdlSome(Bool),
+                                    },
+                                    flow: Source,
+                                },
+                                non_empty_fields: [
+                                    TraceBool {
+                                        location: TraceScalarId(11),
+                                        name: "HdlSome",
+                                        flow: Source,
+                                    },
+                                ],
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                                flow: Source,
+                            },
+                            TraceBool {
+                                location: TraceScalarId(12),
+                                name: "wmode",
+                                flow: Sink,
+                            },
+                            TraceEnumWithFields {
+                                name: "wdata",
+                                discriminant: TraceEnumDiscriminant {
+                                    location: TraceScalarId(13),
+                                    name: "$tag",
+                                    ty: Enum {
+                                        HdlNone,
+                                        HdlSome(Bool),
+                                    },
+                                    flow: Sink,
+                                },
+                                non_empty_fields: [
+                                    TraceBool {
+                                        location: TraceScalarId(14),
+                                        name: "HdlSome",
+                                        flow: Source,
+                                    },
+                                ],
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bool),
+                                },
+                                flow: Sink,
+                            },
+                            TraceBool {
+                                location: TraceScalarId(15),
+                                name: "wmask",
+                                flow: Sink,
+                            },
+                        ],
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<3>,
+                            /* offset = 3 */
+                            en: Bool,
+                            /* offset = 4 */
+                            clk: Clock,
+                            #[hdl(flip)] /* offset = 5 */
+                            rdata: Enum {
+                                HdlNone,
+                                HdlSome(Bool),
+                            },
+                            /* offset = 7 */
+                            wmode: Bool,
+                            /* offset = 8 */
+                            wdata: Enum {
+                                HdlNone,
+                                HdlSome(Bool),
+                            },
+                            /* offset = 10 */
+                            wmask: Bool,
+                        },
+                        flow: Sink,
+                    },
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<3>,
+                        /* offset = 3 */
+                        en: Bool,
+                        /* offset = 4 */
+                        clk: Clock,
+                        #[hdl(flip)] /* offset = 5 */
+                        rdata: Enum {
+                            HdlNone,
+                            HdlSome(Bool),
+                        },
+                        /* offset = 7 */
+                        wmode: Bool,
+                        /* offset = 8 */
+                        wdata: Enum {
+                            HdlNone,
+                            HdlSome(Bool),
+                        },
+                        /* offset = 10 */
+                        wmask: Bool,
+                    },
+                },
+            ],
+            array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
+        },
+    },
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 22 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(3),
+    ],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/memories2.vcd b/crates/fayalite/tests/sim/expected/memories2.vcd
new file mode 100644
index 0000000..bd48f24
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/memories2.vcd
@@ -0,0 +1,363 @@
+$timescale 1 ps $end
+$scope module memories2 $end
+$scope struct rw $end
+$var wire 3 ! addr $end
+$var wire 1 " en $end
+$var wire 1 # clk $end
+$var wire 2 $ rdata $end
+$var wire 1 % wmode $end
+$var wire 2 & wdata $end
+$var wire 1 ' wmask $end
+$upscope $end
+$scope struct mem $end
+$scope struct contents $end
+$scope struct [0] $end
+$scope struct mem $end
+$var string 1 1 \$tag $end
+$var reg 1 6 HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct [1] $end
+$scope struct mem $end
+$var string 1 2 \$tag $end
+$var reg 1 7 HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct [2] $end
+$scope struct mem $end
+$var string 1 3 \$tag $end
+$var reg 1 8 HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct [3] $end
+$scope struct mem $end
+$var string 1 4 \$tag $end
+$var reg 1 9 HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct [4] $end
+$scope struct mem $end
+$var string 1 5 \$tag $end
+$var reg 1 : HdlSome $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct rw0 $end
+$var wire 3 ( addr $end
+$var wire 1 ) en $end
+$var wire 1 * clk $end
+$scope struct rdata $end
+$var string 1 + \$tag $end
+$var wire 1 , HdlSome $end
+$upscope $end
+$var wire 1 - wmode $end
+$scope struct wdata $end
+$var string 1 . \$tag $end
+$var wire 1 / HdlSome $end
+$upscope $end
+$var wire 1 0 wmask $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+sHdlSome\x20(1) 1
+16
+sHdlSome\x20(1) 2
+17
+sHdlSome\x20(1) 3
+18
+sHdlSome\x20(1) 4
+19
+sHdlSome\x20(1) 5
+1:
+b0 !
+0"
+0#
+b0 $
+0%
+b0 &
+0'
+b0 (
+0)
+0*
+sHdlNone\x20(0) +
+0,
+0-
+sHdlNone\x20(0) .
+0/
+00
+$end
+#250000
+1#
+1*
+#500000
+#750000
+0#
+0*
+#1000000
+1"
+1)
+#1250000
+1#
+1*
+b11 $
+sHdlSome\x20(1) +
+1,
+#1500000
+#1750000
+0#
+0*
+#2000000
+0"
+0)
+#2250000
+1#
+1*
+b0 $
+sHdlNone\x20(0) +
+0,
+#2500000
+#2750000
+0#
+0*
+#3000000
+1"
+1%
+1'
+1)
+1-
+10
+#3250000
+sHdlNone\x20(0) 1
+06
+1#
+1*
+#3500000
+#3750000
+0#
+0*
+#4000000
+0%
+0'
+0-
+00
+#4250000
+1#
+1*
+#4500000
+#4750000
+0#
+0*
+#5000000
+1%
+b11 &
+1-
+sHdlSome\x20(1) .
+1/
+#5250000
+1#
+1*
+#5500000
+#5750000
+0#
+0*
+#6000000
+b1 !
+b1 &
+1'
+b1 (
+0/
+10
+#6250000
+sHdlSome\x20(1) 2
+07
+1#
+1*
+#6500000
+#6750000
+0#
+0*
+#7000000
+b10 !
+b10 &
+b10 (
+sHdlNone\x20(0) .
+#7250000
+sHdlNone\x20(0) 3
+08
+1#
+1*
+#7500000
+#7750000
+0#
+0*
+#8000000
+b11 !
+b11 &
+b11 (
+sHdlSome\x20(1) .
+1/
+#8250000
+sHdlSome\x20(1) 4
+19
+1#
+1*
+#8500000
+#8750000
+0#
+0*
+#9000000
+b100 !
+b10 &
+b100 (
+sHdlNone\x20(0) .
+0/
+#9250000
+sHdlNone\x20(0) 5
+0:
+1#
+1*
+#9500000
+#9750000
+0#
+0*
+#10000000
+b101 !
+b1 &
+b101 (
+sHdlSome\x20(1) .
+#10250000
+1#
+1*
+#10500000
+#10750000
+0#
+0*
+#11000000
+b110 !
+b110 (
+#11250000
+1#
+1*
+#11500000
+#11750000
+0#
+0*
+#12000000
+b111 !
+b111 (
+#12250000
+1#
+1*
+#12500000
+#12750000
+0#
+0*
+#13000000
+0%
+b0 &
+0'
+0-
+sHdlNone\x20(0) .
+00
+#13250000
+1#
+1*
+#13500000
+#13750000
+0#
+0*
+#14000000
+b110 !
+b110 (
+#14250000
+1#
+1*
+#14500000
+#14750000
+0#
+0*
+#15000000
+b101 !
+b101 (
+#15250000
+1#
+1*
+#15500000
+#15750000
+0#
+0*
+#16000000
+b100 !
+b100 (
+#16250000
+1#
+1*
+#16500000
+#16750000
+0#
+0*
+#17000000
+b11 !
+b11 (
+#17250000
+1#
+1*
+b11 $
+sHdlSome\x20(1) +
+1,
+#17500000
+#17750000
+0#
+0*
+#18000000
+b10 !
+b10 (
+#18250000
+1#
+1*
+b0 $
+sHdlNone\x20(0) +
+0,
+#18500000
+#18750000
+0#
+0*
+#19000000
+b0 !
+b0 (
+#19250000
+1#
+1*
+#19500000
+#19750000
+0#
+0*
+#20000000
+b1 !
+b1 (
+#20250000
+1#
+1*
+b1 $
+sHdlSome\x20(1) +
+#20500000
+#20750000
+0#
+0*
+#21000000
+b0 !
+0"
+b0 (
+0)
+#21250000
+1#
+1*
+b0 $
+sHdlNone\x20(0) +
+#21500000
+#21750000
+0#
+0*
+#22000000

From 2af38de900547dd145b91e62a24a05e0fde86ded Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 13 Dec 2024 15:04:48 -0800
Subject: [PATCH 137/190] add more memory tests

---
 crates/fayalite/tests/sim.rs                  |  247 +-
 .../fayalite/tests/sim/expected/memories3.txt | 4882 +++++++++++++++++
 .../fayalite/tests/sim/expected/memories3.vcd |  836 +++
 3 files changed, 5960 insertions(+), 5 deletions(-)
 create mode 100644 crates/fayalite/tests/sim/expected/memories3.txt
 create mode 100644 crates/fayalite/tests/sim/expected/memories3.vcd

diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 3fc643c..008d792 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -271,7 +271,7 @@ fn test_shift_register() {
                 assert_eq!(
                     *expected,
                     sim.read_bool(sim.io().q),
-                    "cycle: {cycle}\nvcd:\n{}",
+                    "vcd:\n{}\ncycle: {cycle}",
                     String::from_utf8(writer.take()).unwrap(),
                 );
             }
@@ -473,7 +473,7 @@ fn test_enums() {
         assert_eq!(
             expected,
             io,
-            "cycle: {cycle}\nvcd:\n{}",
+            "vcd:\n{}\ncycle: {cycle}",
             String::from_utf8(writer.take()).unwrap(),
         );
         sim.write_clock(sim.io().cd.clk, false);
@@ -671,7 +671,7 @@ fn test_memories() {
         assert_eq!(
             expected,
             io,
-            "cycle: {cycle}\nvcd:\n{}",
+            "vcd:\n{}\ncycle: {cycle}",
             String::from_utf8(writer.take()).unwrap(),
         );
         sim.advance_time(SimDuration::from_micros(1));
@@ -947,7 +947,7 @@ fn test_memories2() {
         assert_eq!(
             expected,
             io,
-            "cycle: {cycle}\nvcd:\n{}",
+            "vcd:\n{}\ncycle: {cycle}",
             String::from_utf8(writer.take()).unwrap(),
         );
         sim.advance_time(SimDuration::from_nanos(250));
@@ -967,4 +967,241 @@ fn test_memories2() {
     }
 }
 
-// TODO: add more tests for memories
+#[hdl_module(outline_generated)]
+pub fn memories3() {
+    #[hdl]
+    let r: fayalite::memory::ReadStruct<Array<UInt<8>, 8>, ConstUsize<3>> = m.input();
+    #[hdl]
+    let w: fayalite::memory::WriteStruct<Array<UInt<8>, 8>, ConstUsize<3>> = m.input();
+    #[hdl]
+    let mut mem: MemBuilder<Array<UInt<8>, 8>> = memory();
+    mem.depth(8);
+    mem.read_latency(2);
+    mem.write_latency(NonZeroUsize::new(2).unwrap());
+    mem.read_under_write(ReadUnderWrite::Old);
+    connect_any(mem.new_read_port(), r);
+    connect_any(mem.new_write_port(), w);
+}
+
+#[hdl]
+#[test]
+fn test_memories3() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(memories3());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write_clock(sim.io().r.clk, false);
+    sim.write_clock(sim.io().w.clk, false);
+    #[derive(Debug, PartialEq, Eq, Clone, Copy)]
+    struct IO {
+        r_addr: u8,
+        r_en: bool,
+        r_data: [u8; 8],
+        w_addr: u8,
+        w_en: bool,
+        w_data: [u8; 8],
+        w_mask: [bool; 8],
+    }
+    let io_cycles = [
+        IO {
+            r_addr: 0,
+            r_en: false,
+            r_data: [0; 8],
+            w_addr: 0,
+            w_en: true,
+            w_data: [0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0],
+            w_mask: [false, true, false, true, true, false, false, true],
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: [0; 8],
+            w_addr: 1,
+            w_en: false,
+            w_data: [0; 8],
+            w_mask: [false; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: [0, 0x34, 0, 0x78, 0x9A, 0, 0, 0xF0],
+            w_addr: 1,
+            w_en: false,
+            w_data: [0; 8],
+            w_mask: [false; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: [0, 0x34, 0, 0x78, 0x9A, 0, 0, 0xF0],
+            w_addr: 0,
+            w_en: true,
+            w_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10],
+            w_mask: [true; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: [0, 0x34, 0, 0x78, 0x9A, 0, 0, 0xF0],
+            w_addr: 0,
+            w_en: true,
+            w_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10],
+            w_mask: [true; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10],
+            w_addr: 0,
+            w_en: true,
+            w_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10],
+            w_mask: [true; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: false,
+            r_data: [0; 8],
+            w_addr: 1,
+            w_en: true,
+            w_data: [0x13, 0x57, 0x9B, 0xDF, 0x02, 0x46, 0x8A, 0xCE],
+            w_mask: [true; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: false,
+            r_data: [0; 8],
+            w_addr: 2,
+            w_en: true,
+            w_data: *b"testing!",
+            w_mask: [true; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: false,
+            r_data: [0; 8],
+            w_addr: 3,
+            w_en: true,
+            w_data: *b"more tst",
+            w_mask: [true; 8],
+        },
+        IO {
+            r_addr: 0,
+            r_en: true,
+            r_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10],
+            w_addr: 0,
+            w_en: false,
+            w_data: [0; 8],
+            w_mask: [false; 8],
+        },
+        IO {
+            r_addr: 1,
+            r_en: true,
+            r_data: [0x13, 0x57, 0x9B, 0xDF, 0x02, 0x46, 0x8A, 0xCE],
+            w_addr: 0,
+            w_en: false,
+            w_data: [0; 8],
+            w_mask: [false; 8],
+        },
+        IO {
+            r_addr: 2,
+            r_en: true,
+            r_data: *b"testing!",
+            w_addr: 0,
+            w_en: false,
+            w_data: [0; 8],
+            w_mask: [false; 8],
+        },
+        IO {
+            r_addr: 3,
+            r_en: true,
+            r_data: *b"more tst",
+            w_addr: 0,
+            w_en: false,
+            w_data: [0; 8],
+            w_mask: [false; 8],
+        },
+    ];
+    for cycle in 0..io_cycles.len() + 2 {
+        {
+            let IO {
+                r_addr,
+                r_en,
+                r_data: _,
+                w_addr,
+                w_en,
+                w_data,
+                w_mask,
+            } = io_cycles.get(cycle).copied().unwrap_or(IO {
+                r_addr: 0,
+                r_en: false,
+                r_data: [0; 8],
+                w_addr: 0,
+                w_en: false,
+                w_data: [0; 8],
+                w_mask: [false; 8],
+            });
+            sim.write_bool_or_int(sim.io().r.addr, r_addr.cast_to_static());
+            sim.write_bool(sim.io().r.en, r_en);
+            sim.write_bool_or_int(sim.io().w.addr, w_addr.cast_to_static());
+            sim.write_bool(sim.io().w.en, w_en);
+            for (i, v) in w_data.into_iter().enumerate() {
+                sim.write_bool_or_int(sim.io().w.data[i], v);
+            }
+            for (i, v) in w_mask.into_iter().enumerate() {
+                sim.write_bool_or_int(sim.io().w.mask[i], v);
+            }
+        }
+        sim.advance_time(SimDuration::from_nanos(250));
+        sim.write_clock(sim.io().r.clk, true);
+        sim.write_clock(sim.io().w.clk, true);
+        sim.advance_time(SimDuration::from_nanos(250));
+        if let Some(
+            expected @ IO {
+                r_addr,
+                r_en,
+                r_data: _,
+                w_addr,
+                w_en,
+                w_data,
+                w_mask,
+            },
+        ) = cycle.checked_sub(1).and_then(|i| io_cycles.get(i).copied())
+        {
+            let io = IO {
+                r_addr,
+                r_en,
+                r_data: std::array::from_fn(|i| {
+                    sim.read_bool_or_int(sim.io().r.data[i])
+                        .to_bigint()
+                        .try_into()
+                        .expect("known to be in range")
+                }),
+                w_addr,
+                w_en,
+                w_data,
+                w_mask,
+            };
+            assert_eq!(
+                expected,
+                io,
+                "vcd:\n{}\ncycle: {cycle}",
+                String::from_utf8(writer.take()).unwrap(),
+            );
+        }
+        sim.advance_time(SimDuration::from_nanos(250));
+        sim.write_clock(sim.io().r.clk, false);
+        sim.write_clock(sim.io().w.clk, false);
+        sim.advance_time(SimDuration::from_nanos(250));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/memories3.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/memories3.txt") {
+        panic!();
+    }
+}
diff --git a/crates/fayalite/tests/sim/expected/memories3.txt b/crates/fayalite/tests/sim/expected/memories3.txt
new file mode 100644
index 0000000..7860bc5
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/memories3.txt
@@ -0,0 +1,4882 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 14,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 108,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.addr",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.addr",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[0]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[1]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[2]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[3]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[4]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[5]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[6]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[7]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.addr",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.addr",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[0]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[1]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[2]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[3]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[4]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[5]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[6]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[7]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[4]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[5]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[6]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[7]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[4]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[5]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[6]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[7]",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 1,
+                    debug_data: [
+                        (),
+                    ],
+                    layout_data: [
+                        MemoryData {
+                            array_type: Array<Array<UInt<8>, 8>, 8>,
+                            data: [
+                                // len = 0x8
+                                [0x0]: 0x0000000000000000,
+                                [0x1]: 0x0000000000000000,
+                                [0x2]: 0x0000000000000000,
+                                [0x3]: 0x0000000000000000,
+                                [0x4]: 0x0000000000000000,
+                                [0x5]: 0x0000000000000000,
+                                [0x6]: 0x0000000000000000,
+                                [0x7]: 0x0000000000000000,
+                            ],
+                        },
+                    ],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:8:1
+                0: Copy {
+                    dest: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.addr", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.addr", ty: UInt<3> },
+                },
+                1: Copy {
+                    dest: StatePartIndex<BigSlots>(58), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.en", ty: Bool },
+                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.en", ty: Bool },
+                },
+                2: Copy {
+                    dest: StatePartIndex<BigSlots>(59), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.clk", ty: Clock },
+                },
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(60), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[0]", ty: UInt<8> },
+                },
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(61), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[1]", ty: UInt<8> },
+                },
+                5: Copy {
+                    dest: StatePartIndex<BigSlots>(62), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[2]", ty: UInt<8> },
+                },
+                6: Copy {
+                    dest: StatePartIndex<BigSlots>(63), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[3]", ty: UInt<8> },
+                },
+                7: Copy {
+                    dest: StatePartIndex<BigSlots>(64), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[4]", ty: UInt<8> },
+                },
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(65), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[5]", ty: UInt<8> },
+                },
+                9: Copy {
+                    dest: StatePartIndex<BigSlots>(66), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[6]", ty: UInt<8> },
+                },
+                10: Copy {
+                    dest: StatePartIndex<BigSlots>(67), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[7]", ty: UInt<8> },
+                },
+                11: Copy {
+                    dest: StatePartIndex<BigSlots>(68), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[0]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[0]", ty: Bool },
+                },
+                12: Copy {
+                    dest: StatePartIndex<BigSlots>(69), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[1]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[1]", ty: Bool },
+                },
+                13: Copy {
+                    dest: StatePartIndex<BigSlots>(70), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[2]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[2]", ty: Bool },
+                },
+                14: Copy {
+                    dest: StatePartIndex<BigSlots>(71), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[3]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[3]", ty: Bool },
+                },
+                15: Copy {
+                    dest: StatePartIndex<BigSlots>(72), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[4]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[4]", ty: Bool },
+                },
+                16: Copy {
+                    dest: StatePartIndex<BigSlots>(73), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[5]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[5]", ty: Bool },
+                },
+                17: Copy {
+                    dest: StatePartIndex<BigSlots>(74), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[6]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(28), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[6]", ty: Bool },
+                },
+                18: Copy {
+                    dest: StatePartIndex<BigSlots>(75), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[7]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[7]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                19: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(33), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[0]", ty: UInt<8> },
+                },
+                20: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(34), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[1]", ty: UInt<8> },
+                },
+                21: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[2]", ty: UInt<8> },
+                },
+                22: Copy {
+                    dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[3]", ty: UInt<8> },
+                },
+                23: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[4]", ty: UInt<8> },
+                },
+                24: Copy {
+                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[5]", ty: UInt<8> },
+                },
+                25: Copy {
+                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(39), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[6]", ty: UInt<8> },
+                },
+                26: Copy {
+                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[7]", ty: UInt<8> },
+                },
+                27: Copy {
+                    dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.clk", ty: Clock },
+                },
+                28: Copy {
+                    dest: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.en", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.en", ty: Bool },
+                },
+                29: Copy {
+                    dest: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.addr", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(0), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.addr", ty: UInt<3> },
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                30: CastBigToArrayIndex {
+                    dest: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.addr", ty: UInt<3> },
+                },
+                31: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(58), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.en", ty: Bool },
+                },
+                32: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(59), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.clk", ty: Clock },
+                },
+                33: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                34: CastBigToArrayIndex {
+                    dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.addr", ty: UInt<3> },
+                },
+                35: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.en", ty: Bool },
+                },
+                36: BranchIfSmallZero {
+                    target: 46,
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                37: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(41), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 0,
+                    width: 8,
+                },
+                38: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 8,
+                    width: 8,
+                },
+                39: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 16,
+                    width: 8,
+                },
+                40: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 24,
+                    width: 8,
+                },
+                41: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 32,
+                    width: 8,
+                },
+                42: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 40,
+                    width: 8,
+                },
+                43: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 48,
+                    width: 8,
+                },
+                44: MemoryReadUInt {
+                    dest: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 56,
+                    width: 8,
+                },
+                45: Branch {
+                    target: 54,
+                },
+                46: Const {
+                    dest: StatePartIndex<BigSlots>(41), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                47: Const {
+                    dest: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                48: Const {
+                    dest: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                49: Const {
+                    dest: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                50: Const {
+                    dest: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                51: Const {
+                    dest: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                52: Const {
+                    dest: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                53: Const {
+                    dest: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                    value: 0x0,
+                },
+                54: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.clk", ty: Clock },
+                },
+                55: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                56: BranchIfSmallZero {
+                    target: 73,
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                57: Copy {
+                    dest: StatePartIndex<BigSlots>(33), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                },
+                58: Copy {
+                    dest: StatePartIndex<BigSlots>(34), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(50), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                },
+                59: Copy {
+                    dest: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                },
+                60: Copy {
+                    dest: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(52), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                },
+                61: Copy {
+                    dest: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                },
+                62: Copy {
+                    dest: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(54), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                },
+                63: Copy {
+                    dest: StatePartIndex<BigSlots>(39), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(55), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                },
+                64: Copy {
+                    dest: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(56), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                },
+                65: Copy {
+                    dest: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(41), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                },
+                66: Copy {
+                    dest: StatePartIndex<BigSlots>(50), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                },
+                67: Copy {
+                    dest: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                },
+                68: Copy {
+                    dest: StatePartIndex<BigSlots>(52), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                },
+                69: Copy {
+                    dest: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                },
+                70: Copy {
+                    dest: StatePartIndex<BigSlots>(54), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                },
+                71: Copy {
+                    dest: StatePartIndex<BigSlots>(55), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                },
+                72: Copy {
+                    dest: StatePartIndex<BigSlots>(56), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                },
+                73: BranchIfSmallZero {
+                    target: 127,
+                    value: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                74: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                },
+                75: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                },
+                76: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(13), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(12), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                77: CopySmall {
+                    dest: StatePartIndex<SmallSlots>(12), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                78: Copy {
+                    dest: StatePartIndex<BigSlots>(84), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(76), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                },
+                79: Copy {
+                    dest: StatePartIndex<BigSlots>(85), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(77), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                },
+                80: Copy {
+                    dest: StatePartIndex<BigSlots>(86), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(78), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                },
+                81: Copy {
+                    dest: StatePartIndex<BigSlots>(87), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(79), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                },
+                82: Copy {
+                    dest: StatePartIndex<BigSlots>(88), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(80), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                },
+                83: Copy {
+                    dest: StatePartIndex<BigSlots>(89), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(81), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                },
+                84: Copy {
+                    dest: StatePartIndex<BigSlots>(90), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(82), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                },
+                85: Copy {
+                    dest: StatePartIndex<BigSlots>(91), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(83), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                },
+                86: Copy {
+                    dest: StatePartIndex<BigSlots>(76), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(60), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[0]", ty: UInt<8> },
+                },
+                87: Copy {
+                    dest: StatePartIndex<BigSlots>(77), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(61), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[1]", ty: UInt<8> },
+                },
+                88: Copy {
+                    dest: StatePartIndex<BigSlots>(78), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(62), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[2]", ty: UInt<8> },
+                },
+                89: Copy {
+                    dest: StatePartIndex<BigSlots>(79), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(63), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[3]", ty: UInt<8> },
+                },
+                90: Copy {
+                    dest: StatePartIndex<BigSlots>(80), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(64), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[4]", ty: UInt<8> },
+                },
+                91: Copy {
+                    dest: StatePartIndex<BigSlots>(81), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(65), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[5]", ty: UInt<8> },
+                },
+                92: Copy {
+                    dest: StatePartIndex<BigSlots>(82), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(66), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[6]", ty: UInt<8> },
+                },
+                93: Copy {
+                    dest: StatePartIndex<BigSlots>(83), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(67), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[7]", ty: UInt<8> },
+                },
+                94: Copy {
+                    dest: StatePartIndex<BigSlots>(100), // (0x0) SlotDebugData { name: "[0]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(92), // (0x0) SlotDebugData { name: "[0]", ty: Bool },
+                },
+                95: Copy {
+                    dest: StatePartIndex<BigSlots>(101), // (0x0) SlotDebugData { name: "[1]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(93), // (0x0) SlotDebugData { name: "[1]", ty: Bool },
+                },
+                96: Copy {
+                    dest: StatePartIndex<BigSlots>(102), // (0x0) SlotDebugData { name: "[2]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(94), // (0x0) SlotDebugData { name: "[2]", ty: Bool },
+                },
+                97: Copy {
+                    dest: StatePartIndex<BigSlots>(103), // (0x0) SlotDebugData { name: "[3]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(95), // (0x0) SlotDebugData { name: "[3]", ty: Bool },
+                },
+                98: Copy {
+                    dest: StatePartIndex<BigSlots>(104), // (0x0) SlotDebugData { name: "[4]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(96), // (0x0) SlotDebugData { name: "[4]", ty: Bool },
+                },
+                99: Copy {
+                    dest: StatePartIndex<BigSlots>(105), // (0x0) SlotDebugData { name: "[5]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(97), // (0x0) SlotDebugData { name: "[5]", ty: Bool },
+                },
+                100: Copy {
+                    dest: StatePartIndex<BigSlots>(106), // (0x0) SlotDebugData { name: "[6]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(98), // (0x0) SlotDebugData { name: "[6]", ty: Bool },
+                },
+                101: Copy {
+                    dest: StatePartIndex<BigSlots>(107), // (0x0) SlotDebugData { name: "[7]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(99), // (0x0) SlotDebugData { name: "[7]", ty: Bool },
+                },
+                102: Copy {
+                    dest: StatePartIndex<BigSlots>(92), // (0x0) SlotDebugData { name: "[0]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(68), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[0]", ty: Bool },
+                },
+                103: Copy {
+                    dest: StatePartIndex<BigSlots>(93), // (0x0) SlotDebugData { name: "[1]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(69), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[1]", ty: Bool },
+                },
+                104: Copy {
+                    dest: StatePartIndex<BigSlots>(94), // (0x0) SlotDebugData { name: "[2]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(70), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[2]", ty: Bool },
+                },
+                105: Copy {
+                    dest: StatePartIndex<BigSlots>(95), // (0x0) SlotDebugData { name: "[3]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(71), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[3]", ty: Bool },
+                },
+                106: Copy {
+                    dest: StatePartIndex<BigSlots>(96), // (0x0) SlotDebugData { name: "[4]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(72), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[4]", ty: Bool },
+                },
+                107: Copy {
+                    dest: StatePartIndex<BigSlots>(97), // (0x0) SlotDebugData { name: "[5]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(73), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[5]", ty: Bool },
+                },
+                108: Copy {
+                    dest: StatePartIndex<BigSlots>(98), // (0x0) SlotDebugData { name: "[6]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(74), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[6]", ty: Bool },
+                },
+                109: Copy {
+                    dest: StatePartIndex<BigSlots>(99), // (0x0) SlotDebugData { name: "[7]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(75), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[7]", ty: Bool },
+                },
+                110: BranchIfSmallZero {
+                    target: 127,
+                    value: StatePartIndex<SmallSlots>(13), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                111: BranchIfZero {
+                    target: 113,
+                    value: StatePartIndex<BigSlots>(100), // (0x0) SlotDebugData { name: "[0]", ty: Bool },
+                },
+                112: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(84), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 0,
+                    width: 8,
+                },
+                113: BranchIfZero {
+                    target: 115,
+                    value: StatePartIndex<BigSlots>(101), // (0x0) SlotDebugData { name: "[1]", ty: Bool },
+                },
+                114: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(85), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 8,
+                    width: 8,
+                },
+                115: BranchIfZero {
+                    target: 117,
+                    value: StatePartIndex<BigSlots>(102), // (0x0) SlotDebugData { name: "[2]", ty: Bool },
+                },
+                116: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(86), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 16,
+                    width: 8,
+                },
+                117: BranchIfZero {
+                    target: 119,
+                    value: StatePartIndex<BigSlots>(103), // (0x0) SlotDebugData { name: "[3]", ty: Bool },
+                },
+                118: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(87), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 24,
+                    width: 8,
+                },
+                119: BranchIfZero {
+                    target: 121,
+                    value: StatePartIndex<BigSlots>(104), // (0x0) SlotDebugData { name: "[4]", ty: Bool },
+                },
+                120: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(88), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 32,
+                    width: 8,
+                },
+                121: BranchIfZero {
+                    target: 123,
+                    value: StatePartIndex<BigSlots>(105), // (0x0) SlotDebugData { name: "[5]", ty: Bool },
+                },
+                122: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(89), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 40,
+                    width: 8,
+                },
+                123: BranchIfZero {
+                    target: 125,
+                    value: StatePartIndex<BigSlots>(106), // (0x0) SlotDebugData { name: "[6]", ty: Bool },
+                },
+                124: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(90), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 48,
+                    width: 8,
+                },
+                125: BranchIfZero {
+                    target: 127,
+                    value: StatePartIndex<BigSlots>(107), // (0x0) SlotDebugData { name: "[7]", ty: Bool },
+                },
+                126: MemoryWriteUInt {
+                    value: StatePartIndex<BigSlots>(91), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
+                    memory: StatePartIndex<Memories>(0), // (MemoryData {
+                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
+                            //     data: [
+                            //         // len = 0x8
+                            //         [0x0]: 0x1032547698badcfe,
+                            //         [0x1]: 0xce8a4602df9b5713,
+                            //         [0x2]: 0x21676e6974736574,
+                            //         [0x3]: 0x7473742065726f6d,
+                            //         [0x4]: 0x0000000000000000,
+                            //         [0x5]: 0x0000000000000000,
+                            //         [0x6]: 0x0000000000000000,
+                            //         [0x7]: 0x0000000000000000,
+                            //     ],
+                            // }) (),
+                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
+                    stride: 64,
+                    start: 56,
+                    width: 8,
+                },
+                127: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                128: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                129: Return,
+            ],
+            ..
+        },
+        pc: 129,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [
+                MemoryData {
+                    array_type: Array<Array<UInt<8>, 8>, 8>,
+                    data: [
+                        // len = 0x8
+                        [0x0]: 0x1032547698badcfe,
+                        [0x1]: 0xce8a4602df9b5713,
+                        [0x2]: 0x21676e6974736574,
+                        [0x3]: 0x7473742065726f6d,
+                        [0x4]: 0x0000000000000000,
+                        [0x5]: 0x0000000000000000,
+                        [0x6]: 0x0000000000000000,
+                        [0x7]: 0x0000000000000000,
+                    ],
+                },
+            ],
+        },
+        small_slots: StatePart {
+            value: [
+                1,
+                0,
+                0,
+                0,
+                0,
+                1,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::memories3,
+        instantiated: Module {
+            name: memories3,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.r: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    /* offset = 0 */
+                    addr: UInt<3>,
+                    /* offset = 3 */
+                    en: Bool,
+                    /* offset = 4 */
+                    clk: Clock,
+                    #[hdl(flip)] /* offset = 5 */
+                    data: Array<UInt<8>, 8>,
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 11,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.addr",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[7]",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: UInt<3>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: UInt<3>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Bool,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Bool,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(2),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Clock,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Clock,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(3),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Array<UInt<8>, 8>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 8,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "[0]",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: "[1]",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: "[2]",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: "[3]",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: "[4]",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: "[5]",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: "[6]",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: "[7]",
+                                                ty: UInt<8>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Array {
+                                    element: CompiledTypeLayout {
+                                        ty: UInt<8>,
+                                        layout: TypeLayout {
+                                            small_slots: StatePartLayout<SmallSlots> {
+                                                len: 0,
+                                                debug_data: [],
+                                                ..
+                                            },
+                                            big_slots: StatePartLayout<BigSlots> {
+                                                len: 1,
+                                                debug_data: [
+                                                    SlotDebugData {
+                                                        name: "",
+                                                        ty: UInt<8>,
+                                                    },
+                                                ],
+                                                ..
+                                            },
+                                        },
+                                        body: Scalar,
+                                    },
+                                },
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 11 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.r.addr: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<3>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.r.clk: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.r.data: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Array<UInt<8>, 8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 8,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[7]",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Array {
+                    element: CompiledTypeLayout {
+                        ty: UInt<8>,
+                        layout: TypeLayout {
+                            small_slots: StatePartLayout<SmallSlots> {
+                                len: 0,
+                                debug_data: [],
+                                ..
+                            },
+                            big_slots: StatePartLayout<BigSlots> {
+                                len: 1,
+                                debug_data: [
+                                    SlotDebugData {
+                                        name: "",
+                                        ty: UInt<8>,
+                                    },
+                                ],
+                                ..
+                            },
+                        },
+                        body: Scalar,
+                    },
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 8 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.r.data[0]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.r.data[1]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.r.data[2]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.r.data[3]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 6, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.r.data[4]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 7, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.r.data[5]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 8, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.r.data[6]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 9, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.r.data[7]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 10, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.r.en: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bundle {
+                    /* offset = 0 */
+                    addr: UInt<3>,
+                    /* offset = 3 */
+                    en: Bool,
+                    /* offset = 4 */
+                    clk: Clock,
+                    /* offset = 5 */
+                    data: Array<UInt<8>, 8>,
+                    /* offset = 69 */
+                    mask: Array<Bool, 8>,
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 19,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.addr",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[0]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[1]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[2]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[3]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[4]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[5]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[6]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[7]",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Bundle {
+                    fields: [
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(0),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: UInt<3>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: UInt<3>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(1),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Bool,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Bool,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(2),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Clock,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 1,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "",
+                                                ty: Clock,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Scalar,
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(3),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Array<UInt<8>, 8>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 8,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "[0]",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: "[1]",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: "[2]",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: "[3]",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: "[4]",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: "[5]",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: "[6]",
+                                                ty: UInt<8>,
+                                            },
+                                            SlotDebugData {
+                                                name: "[7]",
+                                                ty: UInt<8>,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Array {
+                                    element: CompiledTypeLayout {
+                                        ty: UInt<8>,
+                                        layout: TypeLayout {
+                                            small_slots: StatePartLayout<SmallSlots> {
+                                                len: 0,
+                                                debug_data: [],
+                                                ..
+                                            },
+                                            big_slots: StatePartLayout<BigSlots> {
+                                                len: 1,
+                                                debug_data: [
+                                                    SlotDebugData {
+                                                        name: "",
+                                                        ty: UInt<8>,
+                                                    },
+                                                ],
+                                                ..
+                                            },
+                                        },
+                                        body: Scalar,
+                                    },
+                                },
+                            },
+                        },
+                        CompiledBundleField {
+                            offset: TypeIndex {
+                                small_slots: StatePartIndex<SmallSlots>(0),
+                                big_slots: StatePartIndex<BigSlots>(11),
+                            },
+                            ty: CompiledTypeLayout {
+                                ty: Array<Bool, 8>,
+                                layout: TypeLayout {
+                                    small_slots: StatePartLayout<SmallSlots> {
+                                        len: 0,
+                                        debug_data: [],
+                                        ..
+                                    },
+                                    big_slots: StatePartLayout<BigSlots> {
+                                        len: 8,
+                                        debug_data: [
+                                            SlotDebugData {
+                                                name: "[0]",
+                                                ty: Bool,
+                                            },
+                                            SlotDebugData {
+                                                name: "[1]",
+                                                ty: Bool,
+                                            },
+                                            SlotDebugData {
+                                                name: "[2]",
+                                                ty: Bool,
+                                            },
+                                            SlotDebugData {
+                                                name: "[3]",
+                                                ty: Bool,
+                                            },
+                                            SlotDebugData {
+                                                name: "[4]",
+                                                ty: Bool,
+                                            },
+                                            SlotDebugData {
+                                                name: "[5]",
+                                                ty: Bool,
+                                            },
+                                            SlotDebugData {
+                                                name: "[6]",
+                                                ty: Bool,
+                                            },
+                                            SlotDebugData {
+                                                name: "[7]",
+                                                ty: Bool,
+                                            },
+                                        ],
+                                        ..
+                                    },
+                                },
+                                body: Array {
+                                    element: CompiledTypeLayout {
+                                        ty: Bool,
+                                        layout: TypeLayout {
+                                            small_slots: StatePartLayout<SmallSlots> {
+                                                len: 0,
+                                                debug_data: [],
+                                                ..
+                                            },
+                                            big_slots: StatePartLayout<BigSlots> {
+                                                len: 1,
+                                                debug_data: [
+                                                    SlotDebugData {
+                                                        name: "",
+                                                        ty: Bool,
+                                                    },
+                                                ],
+                                                ..
+                                            },
+                                        },
+                                        body: Scalar,
+                                    },
+                                },
+                            },
+                        },
+                    ],
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 11, len: 19 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.addr: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<3>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 11, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.clk: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 13, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.data: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Array<UInt<8>, 8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 8,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "[7]",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Array {
+                    element: CompiledTypeLayout {
+                        ty: UInt<8>,
+                        layout: TypeLayout {
+                            small_slots: StatePartLayout<SmallSlots> {
+                                len: 0,
+                                debug_data: [],
+                                ..
+                            },
+                            big_slots: StatePartLayout<BigSlots> {
+                                len: 1,
+                                debug_data: [
+                                    SlotDebugData {
+                                        name: "",
+                                        ty: UInt<8>,
+                                    },
+                                ],
+                                ..
+                            },
+                        },
+                        body: Scalar,
+                    },
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 14, len: 8 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.data[0]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 14, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.data[1]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 15, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.data[2]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 16, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.data[3]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 17, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.data[4]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 18, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.data[5]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 19, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.data[6]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 20, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.data[7]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 21, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.en: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 12, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.mask: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Array<Bool, 8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 8,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "[0]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[1]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[2]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[3]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[4]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[5]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[6]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "[7]",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Array {
+                    element: CompiledTypeLayout {
+                        ty: Bool,
+                        layout: TypeLayout {
+                            small_slots: StatePartLayout<SmallSlots> {
+                                len: 0,
+                                debug_data: [],
+                                ..
+                            },
+                            big_slots: StatePartLayout<BigSlots> {
+                                len: 1,
+                                debug_data: [
+                                    SlotDebugData {
+                                        name: "",
+                                        ty: Bool,
+                                    },
+                                ],
+                                ..
+                            },
+                        },
+                        body: Scalar,
+                    },
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 22, len: 8 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.mask[0]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 22, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.mask[1]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 23, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.mask[2]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 24, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.mask[3]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 25, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.mask[4]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 26, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.mask[5]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 27, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.mask[6]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 28, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::memories3,
+            instantiated: Module {
+                name: memories3,
+                ..
+            },
+        }.w.mask[7]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 29, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "memories3",
+        children: [
+            TraceModuleIO {
+                name: "r",
+                child: TraceBundle {
+                    name: "r",
+                    fields: [
+                        TraceUInt {
+                            location: TraceScalarId(0),
+                            name: "addr",
+                            ty: UInt<3>,
+                            flow: Source,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(1),
+                            name: "en",
+                            flow: Source,
+                        },
+                        TraceClock {
+                            location: TraceScalarId(2),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceArray {
+                            name: "data",
+                            elements: [
+                                TraceUInt {
+                                    location: TraceScalarId(3),
+                                    name: "[0]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(4),
+                                    name: "[1]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(5),
+                                    name: "[2]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(6),
+                                    name: "[3]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(7),
+                                    name: "[4]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(8),
+                                    name: "[5]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(9),
+                                    name: "[6]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(10),
+                                    name: "[7]",
+                                    ty: UInt<8>,
+                                    flow: Sink,
+                                },
+                            ],
+                            ty: Array<UInt<8>, 8>,
+                            flow: Sink,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<3>,
+                        /* offset = 3 */
+                        en: Bool,
+                        /* offset = 4 */
+                        clk: Clock,
+                        #[hdl(flip)] /* offset = 5 */
+                        data: Array<UInt<8>, 8>,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    addr: UInt<3>,
+                    /* offset = 3 */
+                    en: Bool,
+                    /* offset = 4 */
+                    clk: Clock,
+                    #[hdl(flip)] /* offset = 5 */
+                    data: Array<UInt<8>, 8>,
+                },
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "w",
+                child: TraceBundle {
+                    name: "w",
+                    fields: [
+                        TraceUInt {
+                            location: TraceScalarId(11),
+                            name: "addr",
+                            ty: UInt<3>,
+                            flow: Source,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(12),
+                            name: "en",
+                            flow: Source,
+                        },
+                        TraceClock {
+                            location: TraceScalarId(13),
+                            name: "clk",
+                            flow: Source,
+                        },
+                        TraceArray {
+                            name: "data",
+                            elements: [
+                                TraceUInt {
+                                    location: TraceScalarId(14),
+                                    name: "[0]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(15),
+                                    name: "[1]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(16),
+                                    name: "[2]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(17),
+                                    name: "[3]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(18),
+                                    name: "[4]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(19),
+                                    name: "[5]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(20),
+                                    name: "[6]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                                TraceUInt {
+                                    location: TraceScalarId(21),
+                                    name: "[7]",
+                                    ty: UInt<8>,
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Array<UInt<8>, 8>,
+                            flow: Source,
+                        },
+                        TraceArray {
+                            name: "mask",
+                            elements: [
+                                TraceBool {
+                                    location: TraceScalarId(22),
+                                    name: "[0]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(23),
+                                    name: "[1]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(24),
+                                    name: "[2]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(25),
+                                    name: "[3]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(26),
+                                    name: "[4]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(27),
+                                    name: "[5]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(28),
+                                    name: "[6]",
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(29),
+                                    name: "[7]",
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Array<Bool, 8>,
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<3>,
+                        /* offset = 3 */
+                        en: Bool,
+                        /* offset = 4 */
+                        clk: Clock,
+                        /* offset = 5 */
+                        data: Array<UInt<8>, 8>,
+                        /* offset = 69 */
+                        mask: Array<Bool, 8>,
+                    },
+                    flow: Source,
+                },
+                ty: Bundle {
+                    /* offset = 0 */
+                    addr: UInt<3>,
+                    /* offset = 3 */
+                    en: Bool,
+                    /* offset = 4 */
+                    clk: Clock,
+                    /* offset = 5 */
+                    data: Array<UInt<8>, 8>,
+                    /* offset = 69 */
+                    mask: Array<Bool, 8>,
+                },
+                flow: Source,
+            },
+            TraceMem {
+                id: TraceMemoryId(0),
+                name: "mem",
+                stride: 64,
+                element_type: TraceArray {
+                    name: "mem",
+                    elements: [
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 0,
+                                len: 8,
+                            },
+                            name: "[0]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 8,
+                                len: 8,
+                            },
+                            name: "[1]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 16,
+                                len: 8,
+                            },
+                            name: "[2]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 24,
+                                len: 8,
+                            },
+                            name: "[3]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 32,
+                                len: 8,
+                            },
+                            name: "[4]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 40,
+                                len: 8,
+                            },
+                            name: "[5]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 48,
+                                len: 8,
+                            },
+                            name: "[6]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceMemoryLocation {
+                                id: TraceMemoryId(0),
+                                depth: 8,
+                                stride: 64,
+                                start: 56,
+                                len: 8,
+                            },
+                            name: "[7]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                    ],
+                    ty: Array<UInt<8>, 8>,
+                    flow: Duplex,
+                },
+                ports: [
+                    TraceMemPort {
+                        name: "r0",
+                        bundle: TraceBundle {
+                            name: "r0",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(30),
+                                    name: "addr",
+                                    ty: UInt<3>,
+                                    flow: Sink,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(31),
+                                    name: "en",
+                                    flow: Sink,
+                                },
+                                TraceClock {
+                                    location: TraceScalarId(32),
+                                    name: "clk",
+                                    flow: Sink,
+                                },
+                                TraceArray {
+                                    name: "data",
+                                    elements: [
+                                        TraceUInt {
+                                            location: TraceScalarId(33),
+                                            name: "[0]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(34),
+                                            name: "[1]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(35),
+                                            name: "[2]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(36),
+                                            name: "[3]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(37),
+                                            name: "[4]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(38),
+                                            name: "[5]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(39),
+                                            name: "[6]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(40),
+                                            name: "[7]",
+                                            ty: UInt<8>,
+                                            flow: Source,
+                                        },
+                                    ],
+                                    ty: Array<UInt<8>, 8>,
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                addr: UInt<3>,
+                                /* offset = 3 */
+                                en: Bool,
+                                /* offset = 4 */
+                                clk: Clock,
+                                #[hdl(flip)] /* offset = 5 */
+                                data: Array<UInt<8>, 8>,
+                            },
+                            flow: Sink,
+                        },
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<3>,
+                            /* offset = 3 */
+                            en: Bool,
+                            /* offset = 4 */
+                            clk: Clock,
+                            #[hdl(flip)] /* offset = 5 */
+                            data: Array<UInt<8>, 8>,
+                        },
+                    },
+                    TraceMemPort {
+                        name: "w1",
+                        bundle: TraceBundle {
+                            name: "w1",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(41),
+                                    name: "addr",
+                                    ty: UInt<3>,
+                                    flow: Sink,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(42),
+                                    name: "en",
+                                    flow: Sink,
+                                },
+                                TraceClock {
+                                    location: TraceScalarId(43),
+                                    name: "clk",
+                                    flow: Sink,
+                                },
+                                TraceArray {
+                                    name: "data",
+                                    elements: [
+                                        TraceUInt {
+                                            location: TraceScalarId(44),
+                                            name: "[0]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(45),
+                                            name: "[1]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(46),
+                                            name: "[2]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(47),
+                                            name: "[3]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(48),
+                                            name: "[4]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(49),
+                                            name: "[5]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(50),
+                                            name: "[6]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                        TraceUInt {
+                                            location: TraceScalarId(51),
+                                            name: "[7]",
+                                            ty: UInt<8>,
+                                            flow: Sink,
+                                        },
+                                    ],
+                                    ty: Array<UInt<8>, 8>,
+                                    flow: Sink,
+                                },
+                                TraceArray {
+                                    name: "mask",
+                                    elements: [
+                                        TraceBool {
+                                            location: TraceScalarId(52),
+                                            name: "[0]",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(53),
+                                            name: "[1]",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(54),
+                                            name: "[2]",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(55),
+                                            name: "[3]",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(56),
+                                            name: "[4]",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(57),
+                                            name: "[5]",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(58),
+                                            name: "[6]",
+                                            flow: Sink,
+                                        },
+                                        TraceBool {
+                                            location: TraceScalarId(59),
+                                            name: "[7]",
+                                            flow: Sink,
+                                        },
+                                    ],
+                                    ty: Array<Bool, 8>,
+                                    flow: Sink,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                addr: UInt<3>,
+                                /* offset = 3 */
+                                en: Bool,
+                                /* offset = 4 */
+                                clk: Clock,
+                                /* offset = 5 */
+                                data: Array<UInt<8>, 8>,
+                                /* offset = 69 */
+                                mask: Array<Bool, 8>,
+                            },
+                            flow: Sink,
+                        },
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<3>,
+                            /* offset = 3 */
+                            en: Bool,
+                            /* offset = 4 */
+                            clk: Clock,
+                            /* offset = 5 */
+                            data: Array<UInt<8>, 8>,
+                            /* offset = 69 */
+                            mask: Array<Bool, 8>,
+                        },
+                    },
+                ],
+                array_type: Array<Array<UInt<8>, 8>, 8>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<3>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(4),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(5),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(6),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(7),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(8),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(9),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(10),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(11),
+                ty: UInt<3>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(12),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(12),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(13),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(13),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(14),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(14),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(15),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(15),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(16),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(16),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(17),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(17),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(18),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(18),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(19),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(19),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(20),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(20),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(21),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(21),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(22),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(22),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(23),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(23),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(24),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(24),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(25),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(25),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(26),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(26),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(27),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(27),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(28),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(28),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(29),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(29),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(30),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(30),
+                ty: UInt<3>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(31),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(31),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(32),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(32),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(33),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(33),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(34),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(34),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(35),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(35),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(36),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(36),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(37),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(37),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(38),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(38),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(39),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(39),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(40),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(40),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(41),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(57),
+                ty: UInt<3>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(42),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(58),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(43),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(59),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(44),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(60),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(45),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(61),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(46),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(62),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(47),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(63),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(48),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(64),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(49),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(65),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(50),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(66),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(51),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(67),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(52),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(68),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(53),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(69),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(54),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(70),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(55),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(71),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(56),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(72),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(57),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(73),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(58),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(74),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(59),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(75),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+    ],
+    trace_memories: {
+        StatePartIndex<Memories>(0): TraceMem {
+            id: TraceMemoryId(0),
+            name: "mem",
+            stride: 64,
+            element_type: TraceArray {
+                name: "mem",
+                elements: [
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 0,
+                            len: 8,
+                        },
+                        name: "[0]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 8,
+                            len: 8,
+                        },
+                        name: "[1]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 16,
+                            len: 8,
+                        },
+                        name: "[2]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 24,
+                            len: 8,
+                        },
+                        name: "[3]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 32,
+                            len: 8,
+                        },
+                        name: "[4]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 40,
+                            len: 8,
+                        },
+                        name: "[5]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 48,
+                            len: 8,
+                        },
+                        name: "[6]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                    TraceUInt {
+                        location: TraceMemoryLocation {
+                            id: TraceMemoryId(0),
+                            depth: 8,
+                            stride: 64,
+                            start: 56,
+                            len: 8,
+                        },
+                        name: "[7]",
+                        ty: UInt<8>,
+                        flow: Duplex,
+                    },
+                ],
+                ty: Array<UInt<8>, 8>,
+                flow: Duplex,
+            },
+            ports: [
+                TraceMemPort {
+                    name: "r0",
+                    bundle: TraceBundle {
+                        name: "r0",
+                        fields: [
+                            TraceUInt {
+                                location: TraceScalarId(30),
+                                name: "addr",
+                                ty: UInt<3>,
+                                flow: Sink,
+                            },
+                            TraceBool {
+                                location: TraceScalarId(31),
+                                name: "en",
+                                flow: Sink,
+                            },
+                            TraceClock {
+                                location: TraceScalarId(32),
+                                name: "clk",
+                                flow: Sink,
+                            },
+                            TraceArray {
+                                name: "data",
+                                elements: [
+                                    TraceUInt {
+                                        location: TraceScalarId(33),
+                                        name: "[0]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(34),
+                                        name: "[1]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(35),
+                                        name: "[2]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(36),
+                                        name: "[3]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(37),
+                                        name: "[4]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(38),
+                                        name: "[5]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(39),
+                                        name: "[6]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(40),
+                                        name: "[7]",
+                                        ty: UInt<8>,
+                                        flow: Source,
+                                    },
+                                ],
+                                ty: Array<UInt<8>, 8>,
+                                flow: Source,
+                            },
+                        ],
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<3>,
+                            /* offset = 3 */
+                            en: Bool,
+                            /* offset = 4 */
+                            clk: Clock,
+                            #[hdl(flip)] /* offset = 5 */
+                            data: Array<UInt<8>, 8>,
+                        },
+                        flow: Sink,
+                    },
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<3>,
+                        /* offset = 3 */
+                        en: Bool,
+                        /* offset = 4 */
+                        clk: Clock,
+                        #[hdl(flip)] /* offset = 5 */
+                        data: Array<UInt<8>, 8>,
+                    },
+                },
+                TraceMemPort {
+                    name: "w1",
+                    bundle: TraceBundle {
+                        name: "w1",
+                        fields: [
+                            TraceUInt {
+                                location: TraceScalarId(41),
+                                name: "addr",
+                                ty: UInt<3>,
+                                flow: Sink,
+                            },
+                            TraceBool {
+                                location: TraceScalarId(42),
+                                name: "en",
+                                flow: Sink,
+                            },
+                            TraceClock {
+                                location: TraceScalarId(43),
+                                name: "clk",
+                                flow: Sink,
+                            },
+                            TraceArray {
+                                name: "data",
+                                elements: [
+                                    TraceUInt {
+                                        location: TraceScalarId(44),
+                                        name: "[0]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(45),
+                                        name: "[1]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(46),
+                                        name: "[2]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(47),
+                                        name: "[3]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(48),
+                                        name: "[4]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(49),
+                                        name: "[5]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(50),
+                                        name: "[6]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                    TraceUInt {
+                                        location: TraceScalarId(51),
+                                        name: "[7]",
+                                        ty: UInt<8>,
+                                        flow: Sink,
+                                    },
+                                ],
+                                ty: Array<UInt<8>, 8>,
+                                flow: Sink,
+                            },
+                            TraceArray {
+                                name: "mask",
+                                elements: [
+                                    TraceBool {
+                                        location: TraceScalarId(52),
+                                        name: "[0]",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(53),
+                                        name: "[1]",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(54),
+                                        name: "[2]",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(55),
+                                        name: "[3]",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(56),
+                                        name: "[4]",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(57),
+                                        name: "[5]",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(58),
+                                        name: "[6]",
+                                        flow: Sink,
+                                    },
+                                    TraceBool {
+                                        location: TraceScalarId(59),
+                                        name: "[7]",
+                                        flow: Sink,
+                                    },
+                                ],
+                                ty: Array<Bool, 8>,
+                                flow: Sink,
+                            },
+                        ],
+                        ty: Bundle {
+                            /* offset = 0 */
+                            addr: UInt<3>,
+                            /* offset = 3 */
+                            en: Bool,
+                            /* offset = 4 */
+                            clk: Clock,
+                            /* offset = 5 */
+                            data: Array<UInt<8>, 8>,
+                            /* offset = 69 */
+                            mask: Array<Bool, 8>,
+                        },
+                        flow: Sink,
+                    },
+                    ty: Bundle {
+                        /* offset = 0 */
+                        addr: UInt<3>,
+                        /* offset = 3 */
+                        en: Bool,
+                        /* offset = 4 */
+                        clk: Clock,
+                        /* offset = 5 */
+                        data: Array<UInt<8>, 8>,
+                        /* offset = 69 */
+                        mask: Array<Bool, 8>,
+                    },
+                },
+            ],
+            array_type: Array<Array<UInt<8>, 8>, 8>,
+        },
+    },
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 15 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+        StatePartIndex<SmallSlots>(6),
+    ],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/memories3.vcd b/crates/fayalite/tests/sim/expected/memories3.vcd
new file mode 100644
index 0000000..328fcaa
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/memories3.vcd
@@ -0,0 +1,836 @@
+$timescale 1 ps $end
+$scope module memories3 $end
+$scope struct r $end
+$var wire 3 ! addr $end
+$var wire 1 " en $end
+$var wire 1 # clk $end
+$scope struct data $end
+$var wire 8 $ \[0] $end
+$var wire 8 % \[1] $end
+$var wire 8 & \[2] $end
+$var wire 8 ' \[3] $end
+$var wire 8 ( \[4] $end
+$var wire 8 ) \[5] $end
+$var wire 8 * \[6] $end
+$var wire 8 + \[7] $end
+$upscope $end
+$upscope $end
+$scope struct w $end
+$var wire 3 , addr $end
+$var wire 1 - en $end
+$var wire 1 . clk $end
+$scope struct data $end
+$var wire 8 / \[0] $end
+$var wire 8 0 \[1] $end
+$var wire 8 1 \[2] $end
+$var wire 8 2 \[3] $end
+$var wire 8 3 \[4] $end
+$var wire 8 4 \[5] $end
+$var wire 8 5 \[6] $end
+$var wire 8 6 \[7] $end
+$upscope $end
+$scope struct mask $end
+$var wire 1 7 \[0] $end
+$var wire 1 8 \[1] $end
+$var wire 1 9 \[2] $end
+$var wire 1 : \[3] $end
+$var wire 1 ; \[4] $end
+$var wire 1 < \[5] $end
+$var wire 1 = \[6] $end
+$var wire 1 > \[7] $end
+$upscope $end
+$upscope $end
+$scope struct mem $end
+$scope struct contents $end
+$scope struct [0] $end
+$scope struct mem $end
+$var reg 8 ] \[0] $end
+$var reg 8 e \[1] $end
+$var reg 8 m \[2] $end
+$var reg 8 u \[3] $end
+$var reg 8 } \[4] $end
+$var reg 8 '" \[5] $end
+$var reg 8 /" \[6] $end
+$var reg 8 7" \[7] $end
+$upscope $end
+$upscope $end
+$scope struct [1] $end
+$scope struct mem $end
+$var reg 8 ^ \[0] $end
+$var reg 8 f \[1] $end
+$var reg 8 n \[2] $end
+$var reg 8 v \[3] $end
+$var reg 8 ~ \[4] $end
+$var reg 8 (" \[5] $end
+$var reg 8 0" \[6] $end
+$var reg 8 8" \[7] $end
+$upscope $end
+$upscope $end
+$scope struct [2] $end
+$scope struct mem $end
+$var reg 8 _ \[0] $end
+$var reg 8 g \[1] $end
+$var reg 8 o \[2] $end
+$var reg 8 w \[3] $end
+$var reg 8 !" \[4] $end
+$var reg 8 )" \[5] $end
+$var reg 8 1" \[6] $end
+$var reg 8 9" \[7] $end
+$upscope $end
+$upscope $end
+$scope struct [3] $end
+$scope struct mem $end
+$var reg 8 ` \[0] $end
+$var reg 8 h \[1] $end
+$var reg 8 p \[2] $end
+$var reg 8 x \[3] $end
+$var reg 8 "" \[4] $end
+$var reg 8 *" \[5] $end
+$var reg 8 2" \[6] $end
+$var reg 8 :" \[7] $end
+$upscope $end
+$upscope $end
+$scope struct [4] $end
+$scope struct mem $end
+$var reg 8 a \[0] $end
+$var reg 8 i \[1] $end
+$var reg 8 q \[2] $end
+$var reg 8 y \[3] $end
+$var reg 8 #" \[4] $end
+$var reg 8 +" \[5] $end
+$var reg 8 3" \[6] $end
+$var reg 8 ;" \[7] $end
+$upscope $end
+$upscope $end
+$scope struct [5] $end
+$scope struct mem $end
+$var reg 8 b \[0] $end
+$var reg 8 j \[1] $end
+$var reg 8 r \[2] $end
+$var reg 8 z \[3] $end
+$var reg 8 $" \[4] $end
+$var reg 8 ," \[5] $end
+$var reg 8 4" \[6] $end
+$var reg 8 <" \[7] $end
+$upscope $end
+$upscope $end
+$scope struct [6] $end
+$scope struct mem $end
+$var reg 8 c \[0] $end
+$var reg 8 k \[1] $end
+$var reg 8 s \[2] $end
+$var reg 8 { \[3] $end
+$var reg 8 %" \[4] $end
+$var reg 8 -" \[5] $end
+$var reg 8 5" \[6] $end
+$var reg 8 =" \[7] $end
+$upscope $end
+$upscope $end
+$scope struct [7] $end
+$scope struct mem $end
+$var reg 8 d \[0] $end
+$var reg 8 l \[1] $end
+$var reg 8 t \[2] $end
+$var reg 8 | \[3] $end
+$var reg 8 &" \[4] $end
+$var reg 8 ." \[5] $end
+$var reg 8 6" \[6] $end
+$var reg 8 >" \[7] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct r0 $end
+$var wire 3 ? addr $end
+$var wire 1 @ en $end
+$var wire 1 A clk $end
+$scope struct data $end
+$var wire 8 B \[0] $end
+$var wire 8 C \[1] $end
+$var wire 8 D \[2] $end
+$var wire 8 E \[3] $end
+$var wire 8 F \[4] $end
+$var wire 8 G \[5] $end
+$var wire 8 H \[6] $end
+$var wire 8 I \[7] $end
+$upscope $end
+$upscope $end
+$scope struct w1 $end
+$var wire 3 J addr $end
+$var wire 1 K en $end
+$var wire 1 L clk $end
+$scope struct data $end
+$var wire 8 M \[0] $end
+$var wire 8 N \[1] $end
+$var wire 8 O \[2] $end
+$var wire 8 P \[3] $end
+$var wire 8 Q \[4] $end
+$var wire 8 R \[5] $end
+$var wire 8 S \[6] $end
+$var wire 8 T \[7] $end
+$upscope $end
+$scope struct mask $end
+$var wire 1 U \[0] $end
+$var wire 1 V \[1] $end
+$var wire 1 W \[2] $end
+$var wire 1 X \[3] $end
+$var wire 1 Y \[4] $end
+$var wire 1 Z \[5] $end
+$var wire 1 [ \[6] $end
+$var wire 1 \ \[7] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+b0 ]
+b0 e
+b0 m
+b0 u
+b0 }
+b0 '"
+b0 /"
+b0 7"
+b0 ^
+b0 f
+b0 n
+b0 v
+b0 ~
+b0 ("
+b0 0"
+b0 8"
+b0 _
+b0 g
+b0 o
+b0 w
+b0 !"
+b0 )"
+b0 1"
+b0 9"
+b0 `
+b0 h
+b0 p
+b0 x
+b0 ""
+b0 *"
+b0 2"
+b0 :"
+b0 a
+b0 i
+b0 q
+b0 y
+b0 #"
+b0 +"
+b0 3"
+b0 ;"
+b0 b
+b0 j
+b0 r
+b0 z
+b0 $"
+b0 ,"
+b0 4"
+b0 <"
+b0 c
+b0 k
+b0 s
+b0 {
+b0 %"
+b0 -"
+b0 5"
+b0 ="
+b0 d
+b0 l
+b0 t
+b0 |
+b0 &"
+b0 ."
+b0 6"
+b0 >"
+b0 !
+0"
+0#
+b0 $
+b0 %
+b0 &
+b0 '
+b0 (
+b0 )
+b0 *
+b0 +
+b0 ,
+1-
+0.
+b10010 /
+b110100 0
+b1010110 1
+b1111000 2
+b10011010 3
+b10111100 4
+b11011110 5
+b11110000 6
+07
+18
+09
+1:
+1;
+0<
+0=
+1>
+b0 ?
+0@
+0A
+b0 B
+b0 C
+b0 D
+b0 E
+b0 F
+b0 G
+b0 H
+b0 I
+b0 J
+1K
+0L
+b10010 M
+b110100 N
+b1010110 O
+b1111000 P
+b10011010 Q
+b10111100 R
+b11011110 S
+b11110000 T
+0U
+1V
+0W
+1X
+1Y
+0Z
+0[
+1\
+$end
+#250000
+1#
+1.
+1A
+1L
+#500000
+#750000
+0#
+0.
+0A
+0L
+#1000000
+1"
+b1 ,
+0-
+b0 /
+b0 0
+b0 1
+b0 2
+b0 3
+b0 4
+b0 5
+b0 6
+08
+0:
+0;
+0>
+1@
+b1 J
+0K
+b0 M
+b0 N
+b0 O
+b0 P
+b0 Q
+b0 R
+b0 S
+b0 T
+0V
+0X
+0Y
+0\
+#1250000
+b0 ]
+b110100 e
+b0 m
+b1111000 u
+b10011010 }
+b0 '"
+b0 /"
+b11110000 7"
+1#
+1.
+1A
+1L
+#1500000
+#1750000
+0#
+0.
+0A
+0L
+#2000000
+#2250000
+1#
+1.
+1A
+1L
+#2500000
+#2750000
+0#
+0.
+0A
+0L
+#3000000
+b0 ,
+1-
+b11111110 /
+b11011100 0
+b10111010 1
+b10011000 2
+b1110110 3
+b1010100 4
+b110010 5
+b10000 6
+17
+18
+19
+1:
+1;
+1<
+1=
+1>
+b0 J
+1K
+b11111110 M
+b11011100 N
+b10111010 O
+b10011000 P
+b1110110 Q
+b1010100 R
+b110010 S
+b10000 T
+1U
+1V
+1W
+1X
+1Y
+1Z
+1[
+1\
+#3250000
+1#
+1.
+1A
+b110100 C
+b1111000 E
+b10011010 F
+b11110000 I
+1L
+b110100 %
+b1111000 '
+b10011010 (
+b11110000 +
+#3500000
+#3750000
+0#
+0.
+0A
+0L
+#4000000
+#4250000
+b11111110 ]
+b11011100 e
+b10111010 m
+b10011000 u
+b1110110 }
+b1010100 '"
+b110010 /"
+b10000 7"
+1#
+1.
+1A
+1L
+#4500000
+#4750000
+0#
+0.
+0A
+0L
+#5000000
+#5250000
+b11111110 ]
+b11011100 e
+b10111010 m
+b10011000 u
+b1110110 }
+b1010100 '"
+b110010 /"
+b10000 7"
+1#
+1.
+1A
+1L
+#5500000
+#5750000
+0#
+0.
+0A
+0L
+#6000000
+0"
+b1 ,
+b10011 /
+b1010111 0
+b10011011 1
+b11011111 2
+b10 3
+b1000110 4
+b10001010 5
+b11001110 6
+0@
+b1 J
+b10011 M
+b1010111 N
+b10011011 O
+b11011111 P
+b10 Q
+b1000110 R
+b10001010 S
+b11001110 T
+#6250000
+b11111110 ]
+b11011100 e
+b10111010 m
+b10011000 u
+b1110110 }
+b1010100 '"
+b110010 /"
+b10000 7"
+1#
+1.
+1A
+b11111110 B
+b11011100 C
+b10111010 D
+b10011000 E
+b1110110 F
+b1010100 G
+b110010 H
+b10000 I
+1L
+b11111110 $
+b11011100 %
+b10111010 &
+b10011000 '
+b1110110 (
+b1010100 )
+b110010 *
+b10000 +
+#6500000
+#6750000
+0#
+0.
+0A
+0L
+#7000000
+b10 ,
+b1110100 /
+b1100101 0
+b1110011 1
+b1110100 2
+b1101001 3
+b1101110 4
+b1100111 5
+b100001 6
+b10 J
+b1110100 M
+b1100101 N
+b1110011 O
+b1110100 P
+b1101001 Q
+b1101110 R
+b1100111 S
+b100001 T
+#7250000
+b10011 ^
+b1010111 f
+b10011011 n
+b11011111 v
+b10 ~
+b1000110 ("
+b10001010 0"
+b11001110 8"
+1#
+1.
+1A
+b0 B
+b0 C
+b0 D
+b0 E
+b0 F
+b0 G
+b0 H
+b0 I
+1L
+b0 $
+b0 %
+b0 &
+b0 '
+b0 (
+b0 )
+b0 *
+b0 +
+#7500000
+#7750000
+0#
+0.
+0A
+0L
+#8000000
+b11 ,
+b1101101 /
+b1101111 0
+b1110010 1
+b1100101 2
+b100000 3
+b1110100 4
+b1110011 5
+b1110100 6
+b11 J
+b1101101 M
+b1101111 N
+b1110010 O
+b1100101 P
+b100000 Q
+b1110100 R
+b1110011 S
+b1110100 T
+#8250000
+b1110100 _
+b1100101 g
+b1110011 o
+b1110100 w
+b1101001 !"
+b1101110 )"
+b1100111 1"
+b100001 9"
+1#
+1.
+1A
+1L
+#8500000
+#8750000
+0#
+0.
+0A
+0L
+#9000000
+1"
+b0 ,
+0-
+b0 /
+b0 0
+b0 1
+b0 2
+b0 3
+b0 4
+b0 5
+b0 6
+07
+08
+09
+0:
+0;
+0<
+0=
+0>
+1@
+b0 J
+0K
+b0 M
+b0 N
+b0 O
+b0 P
+b0 Q
+b0 R
+b0 S
+b0 T
+0U
+0V
+0W
+0X
+0Y
+0Z
+0[
+0\
+#9250000
+b1101101 `
+b1101111 h
+b1110010 p
+b1100101 x
+b100000 ""
+b1110100 *"
+b1110011 2"
+b1110100 :"
+1#
+1.
+1A
+1L
+#9500000
+#9750000
+0#
+0.
+0A
+0L
+#10000000
+b1 !
+b1 ?
+#10250000
+1#
+1.
+1A
+b11111110 B
+b11011100 C
+b10111010 D
+b10011000 E
+b1110110 F
+b1010100 G
+b110010 H
+b10000 I
+1L
+b11111110 $
+b11011100 %
+b10111010 &
+b10011000 '
+b1110110 (
+b1010100 )
+b110010 *
+b10000 +
+#10500000
+#10750000
+0#
+0.
+0A
+0L
+#11000000
+b10 !
+b10 ?
+#11250000
+1#
+1.
+1A
+b10011 B
+b1010111 C
+b10011011 D
+b11011111 E
+b10 F
+b1000110 G
+b10001010 H
+b11001110 I
+1L
+b10011 $
+b1010111 %
+b10011011 &
+b11011111 '
+b10 (
+b1000110 )
+b10001010 *
+b11001110 +
+#11500000
+#11750000
+0#
+0.
+0A
+0L
+#12000000
+b11 !
+b11 ?
+#12250000
+1#
+1.
+1A
+b1110100 B
+b1100101 C
+b1110011 D
+b1110100 E
+b1101001 F
+b1101110 G
+b1100111 H
+b100001 I
+1L
+b1110100 $
+b1100101 %
+b1110011 &
+b1110100 '
+b1101001 (
+b1101110 )
+b1100111 *
+b100001 +
+#12500000
+#12750000
+0#
+0.
+0A
+0L
+#13000000
+b0 !
+0"
+b0 ?
+0@
+#13250000
+1#
+1.
+1A
+b1101101 B
+b1101111 C
+b1110010 D
+b1100101 E
+b100000 F
+b1110100 G
+b1110011 H
+b1110100 I
+1L
+b1101101 $
+b1101111 %
+b1110010 &
+b1100101 '
+b100000 (
+b1110100 )
+b1110011 *
+b1110100 +
+#13500000
+#13750000
+0#
+0.
+0A
+0L
+#14000000
+#14250000
+1#
+1.
+1A
+b0 B
+b0 C
+b0 D
+b0 E
+b0 F
+b0 G
+b0 H
+b0 I
+1L
+b0 $
+b0 %
+b0 &
+b0 '
+b0 (
+b0 )
+b0 *
+b0 +
+#14500000
+#14750000
+0#
+0.
+0A
+0L
+#15000000

From 21c73051ecd71151999af3c27a82bbe4a1abb7b2 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 18 Dec 2024 01:39:35 -0800
Subject: [PATCH 138/190] sim: add SimValue and reading/writing more than just
 a scalar

---
 crates/fayalite/src/bundle.rs                |  125 +-
 crates/fayalite/src/sim.rs                   |  768 ++++++++++-
 crates/fayalite/tests/sim.rs                 |   39 +-
 crates/fayalite/tests/sim/expected/enums.txt | 1205 +++++++++++-------
 crates/fayalite/tests/sim/expected/enums.vcd |   42 +-
 5 files changed, 1719 insertions(+), 460 deletions(-)

diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs
index 843eb6c..995510e 100644
--- a/crates/fayalite/src/bundle.rs
+++ b/crates/fayalite/src/bundle.rs
@@ -4,12 +4,14 @@
 use crate::{
     expr::{ops::BundleLiteral, Expr, ToExpr},
     intern::{Intern, Interned},
+    sim::{SimValue, ToSimValue},
     source_location::SourceLocation,
     ty::{
         impl_match_variant_as_self, CanonicalType, MatchVariantWithoutScope, StaticType, Type,
         TypeProperties, TypeWithDeref,
     },
 };
+use bitvec::vec::BitVec;
 use hashbrown::HashMap;
 use std::{fmt, marker::PhantomData};
 
@@ -323,7 +325,7 @@ macro_rules! impl_tuple_builder_fields {
 }
 
 macro_rules! impl_tuples {
-    ([$({#[num = $num:literal, field = $field:ident] $var:ident: $T:ident})*] []) => {
+    ([$({#[num = $num:literal, field = $field:ident, ty = $ty_var:ident: $Ty:ident] $var:ident: $T:ident})*] []) => {
         impl_tuple_builder_fields! {
             {}
             [$({
@@ -423,6 +425,79 @@ macro_rules! impl_tuples {
                 BundleLiteral::new(ty, field_values[..].intern()).to_expr()
             }
         }
+        impl<$($T: ToSimValue<CanonicalType>,)*> ToSimValue<CanonicalType> for ($($T,)*) {
+            #[track_caller]
+            fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+                ToSimValue::<Bundle>::to_sim_value(self, Bundle::from_canonical(ty)).into_canonical()
+            }
+            #[track_caller]
+            fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType>
+            {
+                ToSimValue::<Bundle>::into_sim_value(self, Bundle::from_canonical(ty)).into_canonical()
+            }
+            #[track_caller]
+            fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
+                ToSimValue::<Bundle>::box_into_sim_value(self, Bundle::from_canonical(ty)).into_canonical()
+            }
+        }
+        impl<$($T: ToSimValue<CanonicalType>,)*> ToSimValue<Bundle> for ($($T,)*) {
+            #[track_caller]
+            fn to_sim_value(&self, ty: Bundle) -> SimValue<Bundle> {
+                let ($($var,)*) = self;
+                let [$($ty_var,)*] = *ty.fields() else {
+                    panic!("bundle has wrong number of fields");
+                };
+                $(let $var = $var.to_sim_value($ty_var.ty);)*
+                ToSimValue::into_sim_value(($($var,)*), ty)
+            }
+            #[track_caller]
+            fn into_sim_value(self, ty: Bundle) -> SimValue<Bundle> {
+                #![allow(unused_mut)]
+                #![allow(clippy::unused_unit)]
+                let ($($var,)*) = self;
+                let [$($ty_var,)*] = *ty.fields() else {
+                    panic!("bundle has wrong number of fields");
+                };
+                let mut bits: Option<BitVec> = None;
+                $(let $var = $var.into_sim_value($ty_var.ty);
+                assert_eq!($var.ty(), $ty_var.ty);
+                if !$var.bits().is_empty() {
+                    if let Some(bits) = &mut bits {
+                        bits.extend_from_bitslice($var.bits());
+                    } else {
+                        let mut $var = $var.into_bits();
+                        $var.reserve(ty.type_properties().bit_width - $var.len());
+                        bits = Some($var);
+                    }
+                }
+                )*
+                bits.unwrap_or_else(BitVec::new).into_sim_value(ty)
+            }
+            #[track_caller]
+            fn box_into_sim_value(self: Box<Self>, ty: Bundle) -> SimValue<Bundle> {
+                Self::into_sim_value(*self, ty)
+            }
+        }
+        impl<$($T: ToSimValue<$Ty>, $Ty: Type,)*> ToSimValue<($($Ty,)*)> for ($($T,)*) {
+            #[track_caller]
+            fn to_sim_value(&self, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
+                let ($($var,)*) = self;
+                let ($($ty_var,)*) = ty;
+                $(let $var = $var.to_sim_value($ty_var).into_canonical();)*
+                SimValue::from_canonical(ToSimValue::into_sim_value(($($var,)*), ty.canonical()))
+            }
+            #[track_caller]
+            fn into_sim_value(self, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
+                let ($($var,)*) = self;
+                let ($($ty_var,)*) = ty;
+                $(let $var = $var.into_sim_value($ty_var).into_canonical();)*
+                SimValue::from_canonical(ToSimValue::into_sim_value(($($var,)*), ty.canonical()))
+            }
+            #[track_caller]
+            fn box_into_sim_value(self: Box<Self>, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
+                Self::into_sim_value(*self, ty)
+            }
+        }
     };
     ([$($lhs:tt)*] [$rhs_first:tt $($rhs:tt)*]) => {
         impl_tuples!([$($lhs)*] []);
@@ -432,18 +507,18 @@ macro_rules! impl_tuples {
 
 impl_tuples! {
     [] [
-        {#[num = 0, field = field_0] v0: T0}
-        {#[num = 1, field = field_1] v1: T1}
-        {#[num = 2, field = field_2] v2: T2}
-        {#[num = 3, field = field_3] v3: T3}
-        {#[num = 4, field = field_4] v4: T4}
-        {#[num = 5, field = field_5] v5: T5}
-        {#[num = 6, field = field_6] v6: T6}
-        {#[num = 7, field = field_7] v7: T7}
-        {#[num = 8, field = field_8] v8: T8}
-        {#[num = 9, field = field_9] v9: T9}
-        {#[num = 10, field = field_10] v10: T10}
-        {#[num = 11, field = field_11] v11: T11}
+        {#[num = 0, field = field_0, ty = ty0: Ty0] v0: T0}
+        {#[num = 1, field = field_1, ty = ty1: Ty1] v1: T1}
+        {#[num = 2, field = field_2, ty = ty2: Ty2] v2: T2}
+        {#[num = 3, field = field_3, ty = ty3: Ty3] v3: T3}
+        {#[num = 4, field = field_4, ty = ty4: Ty4] v4: T4}
+        {#[num = 5, field = field_5, ty = ty5: Ty5] v5: T5}
+        {#[num = 6, field = field_6, ty = ty6: Ty6] v6: T6}
+        {#[num = 7, field = field_7, ty = ty7: Ty7] v7: T7}
+        {#[num = 8, field = field_8, ty = ty8: Ty8] v8: T8}
+        {#[num = 9, field = field_9, ty = ty9: Ty9] v9: T9}
+        {#[num = 10, field = field_10, ty = ty10: Ty10] v10: T10}
+        {#[num = 11, field = field_11, ty = ty11: Ty11] v11: T11}
     ]
 }
 
@@ -528,3 +603,27 @@ impl<T: ?Sized + Send + Sync + 'static> ToExpr for PhantomData<T> {
         BundleLiteral::new(PhantomData, Interned::default()).to_expr()
     }
 }
+
+impl<T: ?Sized + Send + Sync + 'static> ToSimValue<Self> for PhantomData<T> {
+    #[track_caller]
+    fn to_sim_value(&self, ty: Self) -> SimValue<Self> {
+        ToSimValue::into_sim_value(BitVec::new(), ty)
+    }
+}
+
+impl<T: ?Sized> ToSimValue<Bundle> for PhantomData<T> {
+    #[track_caller]
+    fn to_sim_value(&self, ty: Bundle) -> SimValue<Bundle> {
+        assert!(ty.fields().is_empty());
+        ToSimValue::into_sim_value(BitVec::new(), ty)
+    }
+}
+
+impl<T: ?Sized> ToSimValue<CanonicalType> for PhantomData<T> {
+    #[track_caller]
+    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        let ty = Bundle::from_canonical(ty);
+        assert!(ty.fields().is_empty());
+        ToSimValue::into_sim_value(BitVec::new(), ty).into_canonical()
+    }
+}
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index a2b9648..10fbb92 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -14,7 +14,7 @@ use crate::{
         },
         ExprEnum, Flow, ToLiteralBits,
     },
-    int::BoolOrIntType,
+    int::{BoolOrIntType, IntType, SIntValue, UIntValue},
     intern::{Intern, Interned, Memoize},
     memory::PortKind,
     module::{
@@ -42,7 +42,7 @@ use crate::{
 use bitvec::{bits, order::Lsb0, slice::BitSlice, vec::BitVec, view::BitView};
 use hashbrown::{HashMap, HashSet};
 use num_bigint::BigInt;
-use num_traits::{Signed, ToPrimitive, Zero};
+use num_traits::{Signed, Zero};
 use petgraph::{
     data::FromElements,
     visit::{
@@ -50,7 +50,9 @@ use petgraph::{
         IntoNodeIdentifiers, IntoNodeReferences, NodeRef, VisitMap, Visitable,
     },
 };
-use std::{borrow::Cow, collections::BTreeSet, fmt, marker::PhantomData, mem, ops::IndexMut};
+use std::{
+    borrow::Cow, collections::BTreeSet, fmt, marker::PhantomData, mem, ops::IndexMut, sync::Arc,
+};
 
 mod interpreter;
 pub mod time;
@@ -5806,6 +5808,624 @@ impl SimTraceKind {
     }
 }
 
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub struct SimValue<T: Type> {
+    ty: T,
+    bits: BitVec,
+}
+
+impl SimValue<CanonicalType> {
+    #[track_caller]
+    fn to_expr_impl(ty: CanonicalType, bits: &BitSlice) -> Expr<CanonicalType> {
+        match ty {
+            CanonicalType::UInt(_) => Expr::canonical(<UInt>::bits_to_expr(Cow::Borrowed(bits))),
+            CanonicalType::SInt(_) => Expr::canonical(<SInt>::bits_to_expr(Cow::Borrowed(bits))),
+            CanonicalType::Bool(_) => Expr::canonical(Bool::bits_to_expr(Cow::Borrowed(bits))),
+            CanonicalType::Array(ty) => {
+                let element_bit_width = ty.element().bit_width();
+                Expr::<Array>::canonical(
+                    crate::expr::ops::ArrayLiteral::new(
+                        ty.element(),
+                        (0..ty.len())
+                            .map(|array_index| {
+                                let start = element_bit_width * array_index;
+                                let end = start + element_bit_width;
+                                Self::to_expr_impl(ty.element(), &bits[start..end])
+                            })
+                            .collect(),
+                    )
+                    .to_expr(),
+                )
+            }
+            CanonicalType::Enum(ty) => {
+                let discriminant_bit_width = ty.discriminant_bit_width();
+                let mut variant_index = [0; mem::size_of::<usize>()];
+                variant_index.view_bits_mut::<Lsb0>()[0..discriminant_bit_width]
+                    .clone_from_bitslice(&bits[..discriminant_bit_width]);
+                let variant_index = usize::from_le_bytes(variant_index);
+                if let Some(variant) = ty.variants().get(variant_index) {
+                    let data_bit_width = variant.ty.map_or(0, CanonicalType::bit_width);
+                    Expr::canonical(
+                        crate::expr::ops::EnumLiteral::new_by_index(
+                            ty,
+                            variant_index,
+                            variant.ty.map(|ty| {
+                                Self::to_expr_impl(
+                                    ty,
+                                    &bits[discriminant_bit_width
+                                        ..discriminant_bit_width + data_bit_width],
+                                )
+                            }),
+                        )
+                        .to_expr(),
+                    )
+                } else {
+                    Expr::canonical(<UInt>::bits_to_expr(Cow::Borrowed(bits)).cast_bits_to(ty))
+                }
+            }
+            CanonicalType::Bundle(ty) => Expr::canonical(
+                crate::expr::ops::BundleLiteral::new(
+                    ty,
+                    ty.fields()
+                        .iter()
+                        .zip(ty.field_offsets().iter())
+                        .map(|(field, &field_offset)| {
+                            Self::to_expr_impl(
+                                field.ty,
+                                &bits[field_offset..field_offset + field.ty.bit_width()],
+                            )
+                        })
+                        .collect(),
+                )
+                .to_expr(),
+            ),
+            CanonicalType::AsyncReset(ty) => {
+                Expr::canonical(Bool::bits_to_expr(Cow::Borrowed(bits)).cast_to(ty))
+            }
+            CanonicalType::SyncReset(ty) => {
+                Expr::canonical(Bool::bits_to_expr(Cow::Borrowed(bits)).cast_to(ty))
+            }
+            CanonicalType::Reset(_) => panic!(
+                "can't convert SimValue<Reset> to Expr<Reset> -- \
+                can't deduce whether reset value should be sync or async"
+            ),
+            CanonicalType::Clock(ty) => {
+                Expr::canonical(Bool::bits_to_expr(Cow::Borrowed(bits)).cast_to(ty))
+            }
+        }
+    }
+}
+
+impl<T: Type> ToExpr for SimValue<T> {
+    type Type = T;
+
+    #[track_caller]
+    fn to_expr(&self) -> Expr<Self::Type> {
+        Expr::from_canonical(SimValue::to_expr_impl(self.ty.canonical(), &self.bits))
+    }
+}
+
+impl<T: Type> ToSimValue<T> for SimValue<T> {
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        assert_eq!(self.ty, ty);
+        self.clone()
+    }
+
+    #[track_caller]
+    fn into_sim_value(self, ty: T) -> SimValue<T> {
+        assert_eq!(self.ty, ty);
+        self
+    }
+
+    #[track_caller]
+    fn box_into_sim_value(self: Box<Self>, ty: T) -> SimValue<T> {
+        assert_eq!(self.ty, ty);
+        *self
+    }
+}
+
+impl<T: Type> ToSimValue<T> for BitVec {
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        self.clone().into_sim_value(ty)
+    }
+
+    #[track_caller]
+    fn into_sim_value(self, ty: T) -> SimValue<T> {
+        assert_eq!(ty.canonical().bit_width(), self.len());
+        SimValue { ty, bits: self }
+    }
+
+    #[track_caller]
+    fn box_into_sim_value(self: Box<Self>, ty: T) -> SimValue<T> {
+        Self::into_sim_value(*self, ty)
+    }
+}
+
+impl<T: Type> ToSimValue<T> for bitvec::boxed::BitBox {
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        self.clone().into_sim_value(ty)
+    }
+
+    #[track_caller]
+    fn into_sim_value(self, ty: T) -> SimValue<T> {
+        assert_eq!(ty.canonical().bit_width(), self.len());
+        SimValue {
+            ty,
+            bits: self.into_bitvec(),
+        }
+    }
+
+    #[track_caller]
+    fn box_into_sim_value(self: Box<Self>, ty: T) -> SimValue<T> {
+        Self::into_sim_value(*self, ty)
+    }
+}
+
+impl<T: Type> ToSimValue<T> for BitSlice {
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        assert_eq!(ty.canonical().bit_width(), self.len());
+        SimValue {
+            ty,
+            bits: self.to_bitvec(),
+        }
+    }
+}
+
+impl<T: Type> SimValue<T> {
+    pub fn ty(&self) -> T {
+        self.ty
+    }
+    pub fn bits(&self) -> &BitSlice {
+        &self.bits
+    }
+    pub fn into_bits(self) -> BitVec {
+        self.bits
+    }
+    #[track_caller]
+    pub fn from_canonical(v: SimValue<CanonicalType>) -> Self {
+        Self {
+            ty: T::from_canonical(v.ty),
+            bits: v.bits,
+        }
+    }
+    pub fn into_canonical(self) -> SimValue<CanonicalType> {
+        SimValue {
+            ty: self.ty.canonical(),
+            bits: self.bits,
+        }
+    }
+    #[track_caller]
+    pub fn from_dyn_int(v: SimValue<T::Dyn>) -> Self
+    where
+        T: IntType,
+    {
+        Self {
+            ty: T::from_dyn_int(v.ty),
+            bits: v.bits,
+        }
+    }
+    pub fn into_dyn_int(self) -> SimValue<T::Dyn>
+    where
+        T: IntType,
+    {
+        SimValue {
+            ty: self.ty.as_dyn_int(),
+            bits: self.bits,
+        }
+    }
+    #[track_caller]
+    pub fn from_bundle(v: SimValue<Bundle>) -> Self
+    where
+        T: BundleType,
+    {
+        Self {
+            ty: T::from_canonical(CanonicalType::Bundle(v.ty)),
+            bits: v.bits,
+        }
+    }
+    pub fn into_bundle(self) -> SimValue<Bundle>
+    where
+        T: BundleType,
+    {
+        SimValue {
+            ty: Bundle::from_canonical(self.ty.canonical()),
+            bits: self.bits,
+        }
+    }
+    #[track_caller]
+    pub fn from_enum(v: SimValue<Enum>) -> Self
+    where
+        T: EnumType,
+    {
+        Self {
+            ty: T::from_canonical(CanonicalType::Enum(v.ty)),
+            bits: v.bits,
+        }
+    }
+    pub fn into_enum(self) -> SimValue<Enum>
+    where
+        T: EnumType,
+    {
+        SimValue {
+            ty: Enum::from_canonical(self.ty.canonical()),
+            bits: self.bits,
+        }
+    }
+}
+
+pub trait ToSimValue<T: Type> {
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T>;
+    #[track_caller]
+    fn into_sim_value(self, ty: T) -> SimValue<T>
+    where
+        Self: Sized,
+    {
+        self.to_sim_value(ty)
+    }
+    #[track_caller]
+    fn box_into_sim_value(self: Box<Self>, ty: T) -> SimValue<T> {
+        self.to_sim_value(ty)
+    }
+}
+
+impl<This: ?Sized + ToSimValue<T>, T: Type> ToSimValue<T> for &'_ This {
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value(self, ty)
+    }
+}
+
+impl<This: ?Sized + ToSimValue<T>, T: Type> ToSimValue<T> for &'_ mut This {
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value(self, ty)
+    }
+}
+
+impl<This: ?Sized + ToSimValue<T>, T: Type> ToSimValue<T> for Box<This> {
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value(self, ty)
+    }
+    #[track_caller]
+    fn into_sim_value(self, ty: T) -> SimValue<T> {
+        This::box_into_sim_value(self, ty)
+    }
+    #[track_caller]
+    fn box_into_sim_value(self: Box<Self>, ty: T) -> SimValue<T> {
+        This::box_into_sim_value(*self, ty)
+    }
+}
+
+impl<This: ?Sized + ToSimValue<T> + Send + Sync + 'static, T: Type> ToSimValue<T>
+    for Interned<This>
+{
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value(self, ty)
+    }
+}
+
+impl<T: Type, Len: Size> SimValue<ArrayType<T, Len>> {
+    #[track_caller]
+    pub fn from_array_elements<
+        I: IntoIterator<Item: ToSimValue<T>, IntoIter: ExactSizeIterator>,
+    >(
+        elements: I,
+        ty: ArrayType<T, Len>,
+    ) -> Self {
+        let mut iter = elements.into_iter();
+        assert_eq!(iter.len(), ty.len());
+        let Some(first) = iter.next() else {
+            return SimValue {
+                ty,
+                bits: BitVec::new(),
+            };
+        };
+        let SimValue {
+            ty: element_ty,
+            mut bits,
+        } = first.into_sim_value(ty.element());
+        assert_eq!(element_ty, ty.element());
+        bits.reserve(ty.type_properties().bit_width - bits.len());
+        for element in iter {
+            let SimValue {
+                ty: element_ty,
+                bits: element_bits,
+            } = element.into_sim_value(ty.element());
+            assert_eq!(element_ty, ty.element());
+            bits.extend_from_bitslice(&element_bits);
+        }
+        SimValue { ty, bits }
+    }
+}
+
+impl<Element: ToSimValue<T>, T: Type> ToSimValue<Array<T>> for [Element] {
+    #[track_caller]
+    fn to_sim_value(&self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(self, ty)
+    }
+    #[track_caller]
+    fn box_into_sim_value(self: Box<Self>, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(self, ty)
+    }
+}
+
+impl<Element: ToSimValue<CanonicalType>> ToSimValue<CanonicalType> for [Element] {
+    #[track_caller]
+    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
+    }
+    #[track_caller]
+    fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
+    }
+}
+
+impl<Element: ToSimValue<T>, T: Type, const N: usize> ToSimValue<Array<T, N>> for [Element; N]
+where
+    ConstUsize<N>: KnownSize,
+{
+    #[track_caller]
+    fn to_sim_value(&self, ty: Array<T, N>) -> SimValue<Array<T, N>> {
+        SimValue::from_array_elements(self, ty)
+    }
+    #[track_caller]
+    fn into_sim_value(self, ty: Array<T, N>) -> SimValue<Array<T, N>> {
+        SimValue::from_array_elements(self, ty)
+    }
+    #[track_caller]
+    fn box_into_sim_value(self: Box<Self>, ty: Array<T, N>) -> SimValue<Array<T, N>> {
+        SimValue::from_array_elements(<Vec<Element> as From<Box<[Element]>>>::from(self), ty)
+    }
+}
+
+impl<Element: ToSimValue<T>, T: Type, const N: usize> ToSimValue<Array<T>> for [Element; N]
+where
+    ConstUsize<N>: KnownSize,
+{
+    #[track_caller]
+    fn to_sim_value(&self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(self, ty)
+    }
+    #[track_caller]
+    fn into_sim_value(self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(self, ty)
+    }
+    #[track_caller]
+    fn box_into_sim_value(self: Box<Self>, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(<Vec<Element> as From<Box<[Element]>>>::from(self), ty)
+    }
+}
+
+impl<Element: ToSimValue<CanonicalType>, const N: usize> ToSimValue<CanonicalType>
+    for [Element; N]
+{
+    #[track_caller]
+    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
+    }
+    #[track_caller]
+    fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
+    }
+    #[track_caller]
+    fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::from_array_elements(
+            <Vec<Element> as From<Box<[Element]>>>::from(self),
+            <Array>::from_canonical(ty),
+        )
+        .into_canonical()
+    }
+}
+
+impl<Element: ToSimValue<T>, T: Type> ToSimValue<Array<T>> for Vec<Element> {
+    #[track_caller]
+    fn to_sim_value(&self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(self, ty)
+    }
+    #[track_caller]
+    fn into_sim_value(self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(self, ty)
+    }
+    #[track_caller]
+    fn box_into_sim_value(self: Box<Self>, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(*self, ty)
+    }
+}
+
+impl<Element: ToSimValue<CanonicalType>> ToSimValue<CanonicalType> for Vec<Element> {
+    #[track_caller]
+    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
+    }
+    #[track_caller]
+    fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
+    }
+    #[track_caller]
+    fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::from_array_elements(*self, <Array>::from_canonical(ty)).into_canonical()
+    }
+}
+
+impl<T: Type> ToSimValue<T> for Expr<T> {
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        assert_eq!(Expr::ty(*self), ty);
+        SimValue {
+            ty,
+            bits: self
+                .to_literal_bits()
+                .expect("must be a literal expression")
+                .to_bitvec(),
+        }
+    }
+}
+
+macro_rules! impl_to_sim_value_for_bool_like {
+    ($ty:ident) => {
+        impl ToSimValue<$ty> for bool {
+            fn to_sim_value(&self, ty: $ty) -> SimValue<$ty> {
+                SimValue {
+                    ty,
+                    bits: BitVec::repeat(*self, 1),
+                }
+            }
+        }
+    };
+}
+
+impl_to_sim_value_for_bool_like!(Bool);
+impl_to_sim_value_for_bool_like!(AsyncReset);
+impl_to_sim_value_for_bool_like!(SyncReset);
+impl_to_sim_value_for_bool_like!(Reset);
+impl_to_sim_value_for_bool_like!(Clock);
+
+impl ToSimValue<CanonicalType> for bool {
+    #[track_caller]
+    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        match ty {
+            CanonicalType::UInt(_)
+            | CanonicalType::SInt(_)
+            | CanonicalType::Array(_)
+            | CanonicalType::Enum(_)
+            | CanonicalType::Bundle(_) => {
+                panic!("can't create SimValue from bool: expected value of type: {ty:?}");
+            }
+            CanonicalType::Bool(_)
+            | CanonicalType::AsyncReset(_)
+            | CanonicalType::SyncReset(_)
+            | CanonicalType::Reset(_)
+            | CanonicalType::Clock(_) => SimValue {
+                ty,
+                bits: BitVec::repeat(*self, 1),
+            },
+        }
+    }
+}
+
+macro_rules! impl_to_sim_value_for_primitive_int {
+    ($prim:ident) => {
+        impl ToSimValue<<$prim as ToExpr>::Type> for $prim {
+            #[track_caller]
+            fn to_sim_value(
+                &self,
+                ty: <$prim as ToExpr>::Type,
+            ) -> SimValue<<$prim as ToExpr>::Type> {
+                SimValue {
+                    ty,
+                    bits: <<$prim as ToExpr>::Type as BoolOrIntType>::le_bytes_to_bits_wrapping(
+                        &self.to_le_bytes(),
+                        ty.width(),
+                    ),
+                }
+            }
+        }
+
+        impl ToSimValue<<<$prim as ToExpr>::Type as IntType>::Dyn> for $prim {
+            #[track_caller]
+            fn to_sim_value(
+                &self,
+                ty: <<$prim as ToExpr>::Type as IntType>::Dyn,
+            ) -> SimValue<<<$prim as ToExpr>::Type as IntType>::Dyn> {
+                SimValue {
+                    ty,
+                    bits: <<$prim as ToExpr>::Type as BoolOrIntType>::le_bytes_to_bits_wrapping(
+                        &self.to_le_bytes(),
+                        ty.width(),
+                    ),
+                }
+            }
+        }
+
+        impl ToSimValue<CanonicalType> for $prim {
+            #[track_caller]
+            fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+                let ty: <<$prim as ToExpr>::Type as IntType>::Dyn = Type::from_canonical(ty);
+                self.to_sim_value(ty).into_canonical()
+            }
+        }
+    };
+}
+
+impl_to_sim_value_for_primitive_int!(u8);
+impl_to_sim_value_for_primitive_int!(u16);
+impl_to_sim_value_for_primitive_int!(u32);
+impl_to_sim_value_for_primitive_int!(u64);
+impl_to_sim_value_for_primitive_int!(u128);
+impl_to_sim_value_for_primitive_int!(usize);
+impl_to_sim_value_for_primitive_int!(i8);
+impl_to_sim_value_for_primitive_int!(i16);
+impl_to_sim_value_for_primitive_int!(i32);
+impl_to_sim_value_for_primitive_int!(i64);
+impl_to_sim_value_for_primitive_int!(i128);
+impl_to_sim_value_for_primitive_int!(isize);
+
+macro_rules! impl_to_sim_value_for_int_value {
+    ($IntValue:ident, $Int:ident, $IntType:ident) => {
+        impl<Width: KnownSize> ToSimValue<$IntType<Width>> for $IntValue<Width> {
+            fn to_sim_value(&self, ty: $IntType<Width>) -> SimValue<$IntType<Width>> {
+                self.bits().to_bitvec().into_sim_value(ty)
+            }
+
+            fn into_sim_value(self, ty: $IntType<Width>) -> SimValue<$IntType<Width>> {
+                Arc::try_unwrap(self.into_bits())
+                    .unwrap_or_else(|v: Arc<BitVec>| v.to_bitvec())
+                    .into_sim_value(ty)
+            }
+
+            fn box_into_sim_value(
+                self: Box<Self>,
+                ty: $IntType<Width>,
+            ) -> SimValue<$IntType<Width>> {
+                Self::into_sim_value(*self, ty)
+            }
+        }
+
+        impl<Width: Size> ToSimValue<$Int> for $IntValue<Width> {
+            fn to_sim_value(&self, ty: $Int) -> SimValue<$Int> {
+                self.bits().to_bitvec().into_sim_value(ty)
+            }
+
+            fn into_sim_value(self, ty: $Int) -> SimValue<$Int> {
+                Arc::try_unwrap(self.into_bits())
+                    .unwrap_or_else(|v: Arc<BitVec>| v.to_bitvec())
+                    .into_sim_value(ty)
+            }
+
+            fn box_into_sim_value(self: Box<Self>, ty: $Int) -> SimValue<$Int> {
+                Self::into_sim_value(*self, ty)
+            }
+        }
+
+        impl<Width: Size> ToSimValue<CanonicalType> for $IntValue<Width> {
+            #[track_caller]
+            fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+                ToSimValue::<$Int>::to_sim_value(self, $Int::from_canonical(ty)).into_canonical()
+            }
+
+            #[track_caller]
+            fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType> {
+                ToSimValue::<$Int>::into_sim_value(self, $Int::from_canonical(ty)).into_canonical()
+            }
+
+            #[track_caller]
+            fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
+                Self::into_sim_value(*self, ty)
+            }
+        }
+    };
+}
+
+impl_to_sim_value_for_int_value!(UIntValue, UInt, UIntType);
+impl_to_sim_value_for_int_value!(SIntValue, SInt, SIntType);
+
 struct SimulationImpl {
     state: interpreter::State,
     io: Expr<Bundle>,
@@ -6263,8 +6883,11 @@ impl SimulationImpl {
         let value: BigInt = value.into();
         match compiled_value.range.len() {
             TypeLen::A_SMALL_SLOT => {
-                self.state.small_slots[compiled_value.range.small_slots.start] =
-                    value.to_u64().expect("value out of range");
+                let mut small_value = value.iter_u64_digits().next().unwrap_or(0);
+                if value.is_negative() {
+                    small_value = small_value.wrapping_neg();
+                }
+                self.state.small_slots[compiled_value.range.small_slots.start] = small_value;
             }
             TypeLen::A_BIG_SLOT => {
                 self.state.big_slots[compiled_value.range.big_slots.start] = value
@@ -6272,6 +6895,130 @@ impl SimulationImpl {
             _ => unreachable!(),
         }
     }
+    #[track_caller]
+    fn read_write_sim_value_helper(
+        &mut self,
+        compiled_value: CompiledValue<CanonicalType>,
+        bits: &mut BitSlice,
+        read_write_big_scalar: impl Fn(bool, &mut BitSlice, &mut BigInt) + Copy,
+        read_write_small_scalar: impl Fn(bool, &mut BitSlice, &mut SmallUInt) + Copy,
+    ) {
+        match compiled_value.layout.body {
+            CompiledTypeLayoutBody::Scalar => {
+                let signed = match compiled_value.layout.ty {
+                    CanonicalType::UInt(_) => false,
+                    CanonicalType::SInt(_) => true,
+                    CanonicalType::Bool(_) => false,
+                    CanonicalType::Array(_) => unreachable!(),
+                    CanonicalType::Enum(_) => false,
+                    CanonicalType::Bundle(_) => unreachable!(),
+                    CanonicalType::AsyncReset(_) => false,
+                    CanonicalType::SyncReset(_) => false,
+                    CanonicalType::Reset(_) => false,
+                    CanonicalType::Clock(_) => false,
+                };
+                match compiled_value.range.len() {
+                    TypeLen::A_SMALL_SLOT => read_write_small_scalar(
+                        signed,
+                        bits,
+                        &mut self.state.small_slots[compiled_value.range.small_slots.start],
+                    ),
+                    TypeLen::A_BIG_SLOT => read_write_big_scalar(
+                        signed,
+                        bits,
+                        &mut self.state.big_slots[compiled_value.range.big_slots.start],
+                    ),
+                    _ => unreachable!(),
+                }
+            }
+            CompiledTypeLayoutBody::Array { element } => {
+                let ty = <Array>::from_canonical(compiled_value.layout.ty);
+                let element_bit_width = ty.element().bit_width();
+                for element_index in 0..ty.len() {
+                    self.read_write_sim_value_helper(
+                        CompiledValue {
+                            layout: *element,
+                            range: compiled_value
+                                .range
+                                .index_array(element.layout.len(), element_index),
+                            write: None,
+                        },
+                        &mut bits[element_index * element_bit_width..][..element_bit_width],
+                        read_write_big_scalar,
+                        read_write_small_scalar,
+                    );
+                }
+            }
+            CompiledTypeLayoutBody::Bundle { fields } => {
+                let ty = Bundle::from_canonical(compiled_value.layout.ty);
+                for (
+                    (field, offset),
+                    CompiledBundleField {
+                        offset: layout_offset,
+                        ty: field_layout,
+                    },
+                ) in ty.fields().iter().zip(ty.field_offsets()).zip(fields)
+                {
+                    self.read_write_sim_value_helper(
+                        CompiledValue {
+                            layout: field_layout,
+                            range: compiled_value.range.slice(TypeIndexRange::new(
+                                layout_offset,
+                                field_layout.layout.len(),
+                            )),
+                            write: None,
+                        },
+                        &mut bits[offset..][..field.ty.bit_width()],
+                        read_write_big_scalar,
+                        read_write_small_scalar,
+                    );
+                }
+            }
+        }
+    }
+    #[track_caller]
+    fn read(&mut self, io: Expr<CanonicalType>) -> SimValue<CanonicalType> {
+        let compiled_value = self.read_helper(io);
+        let mut bits = BitVec::repeat(false, compiled_value.layout.ty.bit_width());
+        self.read_write_sim_value_helper(
+            compiled_value,
+            &mut bits,
+            |_signed, bits, value| <UInt>::copy_bits_from_bigint_wrapping(value, bits),
+            |_signed, bits, value| {
+                let bytes = value.to_le_bytes();
+                let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
+                bits.clone_from_bitslice(&bitslice[..bits.len()]);
+            },
+        );
+        SimValue {
+            ty: Expr::ty(io),
+            bits,
+        }
+    }
+    #[track_caller]
+    fn write(&mut self, io: Expr<CanonicalType>, value: SimValue<CanonicalType>) {
+        let compiled_value = self.write_helper(io);
+        assert_eq!(Expr::ty(io), value.ty());
+        self.read_write_sim_value_helper(
+            compiled_value,
+            &mut value.into_bits(),
+            |signed, bits, value| {
+                if signed {
+                    *value = SInt::bits_to_bigint(bits);
+                } else {
+                    *value = UInt::bits_to_bigint(bits);
+                }
+            },
+            |signed, bits, value| {
+                let mut small_value = [0; mem::size_of::<SmallUInt>()];
+                if signed && bits.last().as_deref().copied() == Some(true) {
+                    small_value.fill(u8::MAX);
+                }
+                small_value.view_bits_mut::<Lsb0>()[0..bits.len()].clone_from_bitslice(bits);
+                *value = SmallUInt::from_le_bytes(small_value);
+            },
+        );
+    }
     fn close_all_trace_writers(&mut self) -> std::io::Result<()> {
         let trace_writers = mem::take(&mut self.trace_writers);
         let mut retval = Ok(());
@@ -6525,6 +7272,17 @@ impl<T: BundleType> Simulation<T> {
     pub fn read_reset<R: ResetType>(&mut self, io: Expr<R>) -> bool {
         self.sim_impl.read_bit(Expr::canonical(io))
     }
+    #[track_caller]
+    pub fn read<IO: Type>(&mut self, io: Expr<IO>) -> SimValue<IO> {
+        SimValue::from_canonical(self.sim_impl.read(Expr::canonical(io)))
+    }
+    #[track_caller]
+    pub fn write<IO: Type, V: ToSimValue<IO>>(&mut self, io: Expr<IO>, value: V) {
+        self.sim_impl.write(
+            Expr::canonical(io),
+            value.into_sim_value(Expr::ty(io)).into_canonical(),
+        );
+    }
     #[doc(hidden)]
     /// This is explicitly unstable and may be changed/removed at any time
     pub fn set_breakpoints_unstable(&mut self, pcs: HashSet<usize>, trace: bool) {
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 008d792..bea7d93 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -5,7 +5,8 @@ use fayalite::{
     int::UIntValue,
     prelude::*,
     reset::ResetType,
-    sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
+    sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation, ToSimValue},
+    ty::StaticType,
     util::RcWriter,
 };
 use std::num::NonZeroUsize;
@@ -309,6 +310,8 @@ pub fn enums() {
     let which_out: UInt<2> = m.output();
     #[hdl]
     let data_out: UInt<4> = m.output();
+    #[hdl]
+    let b_out: HdlOption<(UInt<1>, Bool)> = m.output();
 
     #[hdl]
     struct MyStruct<T> {
@@ -348,6 +351,8 @@ pub fn enums() {
         }
     }
 
+    connect(b_out, HdlNone());
+
     #[hdl]
     match the_reg {
         MyEnum::A => {
@@ -357,6 +362,7 @@ pub fn enums() {
         MyEnum::B(v) => {
             connect(which_out, 1_hdl_u2);
             connect_any(data_out, v.0 | (v.1.cast_to_static::<UInt<1>>() << 1));
+            connect(b_out, HdlSome(v));
         }
         MyEnum::C(v) => {
             connect(which_out, 2_hdl_u2);
@@ -382,13 +388,33 @@ fn test_enums() {
     sim.advance_time(SimDuration::from_nanos(100));
     sim.write_reset(sim.io().cd.rst, false);
     sim.advance_time(SimDuration::from_nanos(900));
-    #[derive(Debug, PartialEq, Eq)]
+    type BOutTy = HdlOption<(UInt<1>, Bool)>;
+    #[derive(Debug)]
     struct IO {
         en: bool,
         which_in: u8,
         data_in: u8,
         which_out: u8,
         data_out: u8,
+        b_out: Expr<BOutTy>,
+    }
+    impl PartialEq for IO {
+        fn eq(&self, other: &Self) -> bool {
+            let Self {
+                en,
+                which_in,
+                data_in,
+                which_out,
+                data_out,
+                b_out,
+            } = *self;
+            en == other.en
+                && which_in == other.which_in
+                && data_in == other.data_in
+                && which_out == other.which_out
+                && data_out == other.data_out
+                && b_out.to_sim_value(BOutTy::TYPE) == other.b_out.to_sim_value(BOutTy::TYPE)
+        }
     }
     let io_cycles = [
         IO {
@@ -397,6 +423,7 @@ fn test_enums() {
             data_in: 0,
             which_out: 0,
             data_out: 0,
+            b_out: HdlNone(),
         },
         IO {
             en: true,
@@ -404,6 +431,7 @@ fn test_enums() {
             data_in: 0,
             which_out: 0,
             data_out: 0,
+            b_out: HdlNone(),
         },
         IO {
             en: false,
@@ -411,6 +439,7 @@ fn test_enums() {
             data_in: 0,
             which_out: 1,
             data_out: 0,
+            b_out: HdlSome((0_hdl_u1, false)),
         },
         IO {
             en: true,
@@ -418,6 +447,7 @@ fn test_enums() {
             data_in: 0xF,
             which_out: 1,
             data_out: 0,
+            b_out: HdlSome((0_hdl_u1, false)),
         },
         IO {
             en: true,
@@ -425,6 +455,7 @@ fn test_enums() {
             data_in: 0xF,
             which_out: 1,
             data_out: 0x3,
+            b_out: HdlSome((1_hdl_u1, true)),
         },
         IO {
             en: true,
@@ -432,6 +463,7 @@ fn test_enums() {
             data_in: 0xF,
             which_out: 1,
             data_out: 0x3,
+            b_out: HdlSome((1_hdl_u1, true)),
         },
         IO {
             en: true,
@@ -439,6 +471,7 @@ fn test_enums() {
             data_in: 0xF,
             which_out: 2,
             data_out: 0xF,
+            b_out: HdlNone(),
         },
     ];
     for (
@@ -449,6 +482,7 @@ fn test_enums() {
             data_in,
             which_out: _,
             data_out: _,
+            b_out: _,
         },
     ) in io_cycles.into_iter().enumerate()
     {
@@ -469,6 +503,7 @@ fn test_enums() {
                 .to_bigint()
                 .try_into()
                 .expect("known to be in range"),
+            b_out: sim.read(sim.io().b_out).to_expr(),
         };
         assert_eq!(
             expected,
diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt
index ebdcf7e..ebfae3e 100644
--- a/crates/fayalite/tests/sim/expected/enums.txt
+++ b/crates/fayalite/tests/sim/expected/enums.txt
@@ -4,8 +4,15 @@ Simulation {
             state_layout: StateLayout {
                 ty: TypeLayout {
                     small_slots: StatePartLayout<SmallSlots> {
-                        len: 5,
+                        len: 6,
                         debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome,
+                                },
+                            },
                             SlotDebugData {
                                 name: "",
                                 ty: Bool,
@@ -34,7 +41,7 @@ Simulation {
                         ..
                     },
                     big_slots: StatePartLayout<BigSlots> {
-                        len: 82,
+                        len: 103,
                         debug_data: [
                             SlotDebugData {
                                 name: "InstantiatedModule(enums: enums).enums::cd.clk",
@@ -64,6 +71,41 @@ Simulation {
                                 name: "InstantiatedModule(enums: enums).enums::data_out",
                                 ty: UInt<4>,
                             },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::b_out",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
                             SlotDebugData {
                                 name: "InstantiatedModule(enums: enums).enums::the_reg",
                                 ty: Enum {
@@ -344,6 +386,17 @@ Simulation {
                                     C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
                                 },
                             },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                                },
+                            },
                             SlotDebugData {
                                 name: "",
                                 ty: UInt<4>,
@@ -364,6 +417,53 @@ Simulation {
                                 name: "",
                                 ty: UInt<4>,
                             },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1.0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1.1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                                },
+                            },
                             SlotDebugData {
                                 name: "",
                                 ty: UInt<2>,
@@ -398,490 +498,601 @@ Simulation {
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
                 0: Const {
-                    dest: StatePartIndex<BigSlots>(72), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
-                    value: 0x0,
-                },
-                1: SliceInt {
-                    dest: StatePartIndex<BigSlots>(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
-                    start: 2,
-                    len: 2,
-                },
-                2: CastToSInt {
-                    dest: StatePartIndex<BigSlots>(62), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    dest_width: 2,
-                },
-                3: Const {
-                    dest: StatePartIndex<BigSlots>(54), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    value: 0x2,
-                },
-                4: SliceInt {
-                    dest: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
-                    start: 1,
-                    len: 1,
-                },
-                5: Copy {
-                    dest: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                6: Copy {
-                    dest: StatePartIndex<BigSlots>(60), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
-                7: SliceInt {
-                    dest: StatePartIndex<BigSlots>(38), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
-                    start: 0,
-                    len: 1,
-                },
-                8: Copy {
-                    dest: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(38), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                9: Copy {
-                    dest: StatePartIndex<BigSlots>(40), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
-                10: Copy {
-                    dest: StatePartIndex<BigSlots>(36), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(40), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                11: Copy {
-                    dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: ".1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: "", ty: Bool },
-                },
-                12: Copy {
-                    dest: StatePartIndex<BigSlots>(58), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(40), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                13: Copy {
-                    dest: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(60), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                14: Copy {
-                    dest: StatePartIndex<BigSlots>(55), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(58), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
-                },
-                15: Copy {
-                    dest: StatePartIndex<BigSlots>(56), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
-                },
-                16: Copy {
-                    dest: StatePartIndex<BigSlots>(57), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(62), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
-                },
-                17: Copy {
-                    dest: StatePartIndex<BigSlots>(50), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(54), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                18: Copy {
-                    dest: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(55), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
-                },
-                19: Copy {
-                    dest: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(56), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
-                },
-                20: Copy {
-                    dest: StatePartIndex<BigSlots>(53), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(57), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
-                },
-                21: Shl {
-                    dest: StatePartIndex<BigSlots>(63), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
-                    rhs: 1,
-                },
-                22: Or {
-                    dest: StatePartIndex<BigSlots>(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(63), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                23: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(65), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(53), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
-                    dest_width: 2,
-                },
-                24: Shl {
-                    dest: StatePartIndex<BigSlots>(66), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(65), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    rhs: 2,
-                },
-                25: Or {
-                    dest: StatePartIndex<BigSlots>(67), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(66), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                26: Shl {
-                    dest: StatePartIndex<BigSlots>(68), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
-                    lhs: StatePartIndex<BigSlots>(67), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
-                    rhs: 2,
-                },
-                27: Or {
-                    dest: StatePartIndex<BigSlots>(69), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
-                    lhs: StatePartIndex<BigSlots>(50), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(68), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
-                },
-                28: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(70), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
-                    src: StatePartIndex<BigSlots>(69), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
-                    dest_width: 6,
-                },
-                29: Copy {
-                    dest: StatePartIndex<BigSlots>(71), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(70), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
-                },
-                30: Const {
-                    dest: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(90), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                     value: 0x1,
                 },
-                31: CmpEq {
-                    dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                32: Copy {
-                    dest: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                33: Copy {
-                    dest: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(36), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                },
-                34: Copy {
-                    dest: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: ".1", ty: Bool },
-                },
-                35: Copy {
-                    dest: StatePartIndex<BigSlots>(43), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
-                },
-                36: Shl {
-                    dest: StatePartIndex<BigSlots>(44), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(43), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    rhs: 1,
-                },
-                37: Or {
-                    dest: StatePartIndex<BigSlots>(45), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(44), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                38: Shl {
-                    dest: StatePartIndex<BigSlots>(46), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(45), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    rhs: 2,
-                },
-                39: Or {
-                    dest: StatePartIndex<BigSlots>(47), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(46), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                40: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(48), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
-                    src: StatePartIndex<BigSlots>(47), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
-                    dest_width: 6,
-                },
-                41: Copy {
-                    dest: StatePartIndex<BigSlots>(49), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(48), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
-                },
-                42: Const {
-                    dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                1: Const {
+                    dest: StatePartIndex<BigSlots>(82), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
                     value: 0x0,
                 },
-                43: CmpEq {
-                    dest: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                2: Const {
+                    dest: StatePartIndex<BigSlots>(80), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    value: 0x0,
                 },
-                44: Copy {
-                    dest: StatePartIndex<BigSlots>(13), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
-                    src: StatePartIndex<BigSlots>(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(81), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    src: StatePartIndex<BigSlots>(80), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                 },
-                45: SliceInt {
-                    dest: StatePartIndex<BigSlots>(14), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(13), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                // at: module-XXXXXXXXXX.rs:16:1
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    src: StatePartIndex<BigSlots>(81), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                5: SliceInt {
+                    dest: StatePartIndex<BigSlots>(69), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
                     start: 2,
                     len: 2,
                 },
-                46: SliceInt {
-                    dest: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(14), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    start: 0,
-                    len: 1,
+                6: CastToSInt {
+                    dest: StatePartIndex<BigSlots>(70), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(69), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest_width: 2,
                 },
-                47: SliceInt {
-                    dest: StatePartIndex<BigSlots>(16), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(14), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                7: Const {
+                    dest: StatePartIndex<BigSlots>(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    value: 0x2,
+                },
+                8: SliceInt {
+                    dest: StatePartIndex<BigSlots>(49), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
                     start: 1,
                     len: 1,
                 },
-                48: Copy {
-                    dest: StatePartIndex<BigSlots>(17), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(16), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                9: Copy {
+                    dest: StatePartIndex<BigSlots>(50), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(49), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                49: Copy {
-                    dest: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                10: Copy {
+                    dest: StatePartIndex<BigSlots>(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(50), // (0x1) SlotDebugData { name: "", ty: Bool },
                 },
-                50: Copy {
-                    dest: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: ".1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(17), // (0x1) SlotDebugData { name: "", ty: Bool },
+                11: SliceInt {
+                    dest: StatePartIndex<BigSlots>(46), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
+                    start: 0,
+                    len: 1,
                 },
-                51: Copy {
-                    dest: StatePartIndex<BigSlots>(73), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                12: Copy {
+                    dest: StatePartIndex<BigSlots>(47), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(46), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                52: Shl {
-                    dest: StatePartIndex<BigSlots>(74), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(73), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                13: Copy {
+                    dest: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(47), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                14: Copy {
+                    dest: StatePartIndex<BigSlots>(44), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                15: Copy {
+                    dest: StatePartIndex<BigSlots>(45), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(50), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                16: Copy {
+                    dest: StatePartIndex<BigSlots>(66), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                17: Copy {
+                    dest: StatePartIndex<BigSlots>(67), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                18: Copy {
+                    dest: StatePartIndex<BigSlots>(63), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(66), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                },
+                19: Copy {
+                    dest: StatePartIndex<BigSlots>(64), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(67), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                },
+                20: Copy {
+                    dest: StatePartIndex<BigSlots>(65), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(70), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                },
+                21: Copy {
+                    dest: StatePartIndex<BigSlots>(58), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                22: Copy {
+                    dest: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(63), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                },
+                23: Copy {
+                    dest: StatePartIndex<BigSlots>(60), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(64), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                },
+                24: Copy {
+                    dest: StatePartIndex<BigSlots>(61), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(65), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                },
+                25: Shl {
+                    dest: StatePartIndex<BigSlots>(71), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(60), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
                     rhs: 1,
                 },
-                53: Or {
-                    dest: StatePartIndex<BigSlots>(75), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(74), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                26: Or {
+                    dest: StatePartIndex<BigSlots>(72), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(71), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
                 },
-                54: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(76), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(75), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                27: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(73), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(61), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
+                    dest_width: 2,
+                },
+                28: Shl {
+                    dest: StatePartIndex<BigSlots>(74), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(73), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: 2,
+                },
+                29: Or {
+                    dest: StatePartIndex<BigSlots>(75), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(72), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(74), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                30: Shl {
+                    dest: StatePartIndex<BigSlots>(76), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(75), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    rhs: 2,
+                },
+                31: Or {
+                    dest: StatePartIndex<BigSlots>(77), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(58), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(76), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
+                },
+                32: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(78), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(77), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    dest_width: 6,
+                },
+                33: Copy {
+                    dest: StatePartIndex<BigSlots>(79), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(78), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                },
+                34: Const {
+                    dest: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                    value: 0x1,
+                },
+                35: CmpEq {
+                    dest: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<BigSlots>(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                36: Copy {
+                    dest: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                37: Copy {
+                    dest: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(44), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                },
+                38: Copy {
+                    dest: StatePartIndex<BigSlots>(43), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(45), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                },
+                39: Copy {
+                    dest: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(43), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
+                },
+                40: Shl {
+                    dest: StatePartIndex<BigSlots>(52), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 1,
+                },
+                41: Or {
+                    dest: StatePartIndex<BigSlots>(53), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(52), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                42: Shl {
+                    dest: StatePartIndex<BigSlots>(54), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(53), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: 2,
+                },
+                43: Or {
+                    dest: StatePartIndex<BigSlots>(55), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(54), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                44: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(56), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(55), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
+                    dest_width: 6,
+                },
+                45: Copy {
+                    dest: StatePartIndex<BigSlots>(57), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(56), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
+                },
+                46: Const {
+                    dest: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    value: 0x0,
+                },
+                47: CmpEq {
+                    dest: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<BigSlots>(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                48: Copy {
+                    dest: StatePartIndex<BigSlots>(21), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(15), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                49: SliceInt {
+                    dest: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(21), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    start: 2,
+                    len: 2,
+                },
+                50: SliceInt {
+                    dest: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 0,
+                    len: 1,
+                },
+                51: SliceInt {
+                    dest: StatePartIndex<BigSlots>(24), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 1,
+                    len: 1,
+                },
+                52: Copy {
+                    dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(24), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                53: Copy {
+                    dest: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                54: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                55: Copy {
+                    dest: StatePartIndex<BigSlots>(83), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                },
+                56: Shl {
+                    dest: StatePartIndex<BigSlots>(84), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(83), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 1,
+                },
+                57: Or {
+                    dest: StatePartIndex<BigSlots>(85), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(84), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                58: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(86), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(85), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     dest_width: 4,
                 },
-                55: SliceInt {
-                    dest: StatePartIndex<BigSlots>(23), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(13), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                59: Copy {
+                    dest: StatePartIndex<BigSlots>(87), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(90), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                60: Copy {
+                    dest: StatePartIndex<BigSlots>(88), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                },
+                61: Copy {
+                    dest: StatePartIndex<BigSlots>(89), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                },
+                62: Copy {
+                    dest: StatePartIndex<BigSlots>(91), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(89), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
+                },
+                63: Shl {
+                    dest: StatePartIndex<BigSlots>(92), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(91), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 1,
+                },
+                64: Or {
+                    dest: StatePartIndex<BigSlots>(93), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(88), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(92), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                65: Shl {
+                    dest: StatePartIndex<BigSlots>(94), // (0x6) SlotDebugData { name: "", ty: UInt<3> },
+                    lhs: StatePartIndex<BigSlots>(93), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: 1,
+                },
+                66: Or {
+                    dest: StatePartIndex<BigSlots>(95), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
+                    lhs: StatePartIndex<BigSlots>(87), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(94), // (0x6) SlotDebugData { name: "", ty: UInt<3> },
+                },
+                67: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(96), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(95), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
+                    dest_width: 3,
+                },
+                68: Copy {
+                    dest: StatePartIndex<BigSlots>(97), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    src: StatePartIndex<BigSlots>(96), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
+                },
+                69: SliceInt {
+                    dest: StatePartIndex<BigSlots>(31), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(21), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
                     start: 2,
                     len: 4,
                 },
-                56: SliceInt {
-                    dest: StatePartIndex<BigSlots>(24), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(23), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                70: SliceInt {
+                    dest: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(31), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
                     start: 0,
                     len: 2,
                 },
-                57: SliceInt {
-                    dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(24), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                71: SliceInt {
+                    dest: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     start: 0,
                     len: 1,
                 },
-                58: SliceInt {
-                    dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(24), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                72: SliceInt {
+                    dest: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     start: 1,
                     len: 1,
                 },
-                59: Copy {
-                    dest: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                73: Copy {
+                    dest: StatePartIndex<BigSlots>(29), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                60: Copy {
-                    dest: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                74: Copy {
+                    dest: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                61: SliceInt {
-                    dest: StatePartIndex<BigSlots>(27), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(23), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                75: SliceInt {
+                    dest: StatePartIndex<BigSlots>(35), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(31), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
                     start: 2,
                     len: 2,
                 },
-                62: CastToSInt {
-                    dest: StatePartIndex<BigSlots>(28), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(27), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                76: CastToSInt {
+                    dest: StatePartIndex<BigSlots>(36), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(35), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     dest_width: 2,
                 },
-                63: Copy {
-                    dest: StatePartIndex<BigSlots>(18), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                77: Copy {
+                    dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(29), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
                 },
-                64: Copy {
-                    dest: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                78: Copy {
+                    dest: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
                 },
-                65: Copy {
-                    dest: StatePartIndex<BigSlots>(20), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(28), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                79: Copy {
+                    dest: StatePartIndex<BigSlots>(28), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(36), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
                 },
-                66: Shl {
-                    dest: StatePartIndex<BigSlots>(77), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                80: Shl {
+                    dest: StatePartIndex<BigSlots>(98), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
                     rhs: 1,
                 },
-                67: Or {
-                    dest: StatePartIndex<BigSlots>(78), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(18), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(77), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                81: Or {
+                    dest: StatePartIndex<BigSlots>(99), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(98), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
                 },
-                68: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(79), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(20), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                82: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(100), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(28), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
                     dest_width: 2,
                 },
-                69: Shl {
-                    dest: StatePartIndex<BigSlots>(80), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(79), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                83: Shl {
+                    dest: StatePartIndex<BigSlots>(101), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(100), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     rhs: 2,
                 },
-                70: Or {
-                    dest: StatePartIndex<BigSlots>(81), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(78), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(80), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                84: Or {
+                    dest: StatePartIndex<BigSlots>(102), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(99), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(101), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
                 },
-                // at: module-XXXXXXXXXX.rs:8:1
-                71: AndBigWithSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    lhs: StatePartIndex<BigSlots>(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                // at: module-XXXXXXXXXX.rs:9:1
+                85: AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(5), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    lhs: StatePartIndex<BigSlots>(15), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     rhs: 0x3,
                 },
-                // at: module-XXXXXXXXXX.rs:15:1
-                72: BranchIfSmallNeImmediate {
-                    target: 75,
-                    lhs: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                // at: module-XXXXXXXXXX.rs:17:1
+                86: BranchIfSmallNeImmediate {
+                    target: 89,
+                    lhs: StatePartIndex<SmallSlots>(5), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
                     rhs: 0x0,
                 },
-                // at: module-XXXXXXXXXX.rs:16:1
-                73: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                // at: module-XXXXXXXXXX.rs:17:1
-                74: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(72), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:15:1
-                75: BranchIfSmallNeImmediate {
-                    target: 78,
-                    lhs: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    rhs: 0x1,
-                },
                 // at: module-XXXXXXXXXX.rs:18:1
-                76: Copy {
+                87: Copy {
                     dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:19:1
-                77: Copy {
+                88: Copy {
                     dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(76), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(82), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
                 },
-                // at: module-XXXXXXXXXX.rs:15:1
-                78: BranchIfSmallNeImmediate {
-                    target: 81,
-                    lhs: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    rhs: 0x2,
+                // at: module-XXXXXXXXXX.rs:17:1
+                89: BranchIfSmallNeImmediate {
+                    target: 93,
+                    lhs: StatePartIndex<SmallSlots>(5), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:20:1
-                79: Copy {
+                90: Copy {
                     dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(54), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:21:1
-                80: Copy {
+                91: Copy {
                     dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(81), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(86), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
                 },
-                // at: module-XXXXXXXXXX.rs:8:1
-                81: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                // at: module-XXXXXXXXXX.rs:22:1
+                92: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    src: StatePartIndex<BigSlots>(97), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                },
+                // at: module-XXXXXXXXXX.rs:17:1
+                93: BranchIfSmallNeImmediate {
+                    target: 96,
+                    lhs: StatePartIndex<SmallSlots>(5), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 0x2,
+                },
+                // at: module-XXXXXXXXXX.rs:23:1
+                94: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:24:1
+                95: Copy {
+                    dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(102), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                96: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                82: Const {
-                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
+                97: Const {
+                    dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                     value: 0x0,
                 },
-                83: Copy {
-                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
+                98: Copy {
+                    dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                 },
-                // at: module-XXXXXXXXXX.rs:9:1
-                84: BranchIfZero {
-                    target: 92,
+                // at: module-XXXXXXXXXX.rs:10:1
+                99: BranchIfZero {
+                    target: 107,
                     value: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool },
                 },
-                // at: module-XXXXXXXXXX.rs:10:1
-                85: BranchIfZero {
-                    target: 87,
-                    value: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
+                // at: module-XXXXXXXXXX.rs:11:1
+                100: BranchIfZero {
+                    target: 102,
+                    value: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:12:1
+                101: Copy {
+                    dest: StatePartIndex<BigSlots>(16), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
-                86: Copy {
-                    dest: StatePartIndex<BigSlots>(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                },
-                // at: module-XXXXXXXXXX.rs:10:1
-                87: BranchIfNonZero {
-                    target: 92,
-                    value: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:12:1
-                88: BranchIfZero {
-                    target: 90,
-                    value: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: Bool },
+                102: BranchIfNonZero {
+                    target: 107,
+                    value: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:13:1
-                89: Copy {
-                    dest: StatePartIndex<BigSlots>(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(49), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                },
-                // at: module-XXXXXXXXXX.rs:12:1
-                90: BranchIfNonZero {
-                    target: 92,
-                    value: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: Bool },
+                103: BranchIfZero {
+                    target: 105,
+                    value: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:14:1
-                91: Copy {
-                    dest: StatePartIndex<BigSlots>(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(71), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                104: Copy {
+                    dest: StatePartIndex<BigSlots>(16), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(57), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
-                // at: module-XXXXXXXXXX.rs:8:1
-                92: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                // at: module-XXXXXXXXXX.rs:13:1
+                105: BranchIfNonZero {
+                    target: 107,
+                    value: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:15:1
+                106: Copy {
+                    dest: StatePartIndex<BigSlots>(16), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(79), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                107: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock },
                 },
-                93: AndSmall {
+                108: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                109: Copy {
+                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                },
+                110: SliceInt {
+                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    start: 1,
+                    len: 2,
+                },
+                111: SliceInt {
+                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 0,
+                    len: 1,
+                },
+                112: SliceInt {
+                    dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 1,
+                    len: 1,
+                },
+                113: Copy {
+                    dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                114: Copy {
+                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                115: Copy {
+                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                116: AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
+                    lhs: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                117: BranchIfSmallZero {
+                    target: 122,
+                    value: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                118: BranchIfSmallNonZero {
+                    target: 121,
+                    value: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                119: Copy {
+                    dest: StatePartIndex<BigSlots>(15), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(16), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                120: Branch {
+                    target: 122,
+                },
+                121: Copy {
+                    dest: StatePartIndex<BigSlots>(15), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                122: XorSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                94: BranchIfSmallZero {
-                    target: 99,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                95: BranchIfSmallNonZero {
-                    target: 98,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                96: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(8), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                },
-                97: Branch {
-                    target: 99,
-                },
-                98: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                },
-                99: XorSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                100: Return,
+                123: Return,
             ],
             ..
         },
-        pc: 100,
+        pc: 123,
         memory_write_log: [],
         memories: StatePart {
             value: [],
         },
         small_slots: StatePart {
             value: [
+                0,
                 0,
                 0,
                 1,
@@ -898,6 +1109,14 @@ Simulation {
                 15,
                 2,
                 15,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
                 62,
                 62,
                 0,
@@ -964,10 +1183,23 @@ Simulation {
                 62,
                 62,
                 0,
+                0,
+                0,
                 1,
                 2,
                 3,
                 3,
+                1,
+                1,
+                1,
+                1,
+                1,
+                2,
+                3,
+                6,
+                7,
+                7,
+                7,
                 2,
                 3,
                 3,
@@ -985,6 +1217,46 @@ Simulation {
     },
     uninitialized_inputs: {},
     io_targets: {
+        Instance {
+            name: <simulator>::enums,
+            instantiated: Module {
+                name: enums,
+                ..
+            },
+        }.b_out: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                },
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::b_out",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                                },
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 7, len: 1 },
+            },
+            write: None,
+        },
         Instance {
             name: <simulator>::enums,
             instantiated: Module {
@@ -1415,23 +1687,22 @@ Simulation {
                 ty: UInt<4>,
                 flow: Sink,
             },
-            TraceReg {
-                name: "the_reg",
+            TraceModuleIO {
+                name: "b_out",
                 child: TraceEnumWithFields {
-                    name: "the_reg",
+                    name: "b_out",
                     discriminant: TraceEnumDiscriminant {
                         location: TraceScalarId(7),
                         name: "$tag",
                         ty: Enum {
-                            A,
-                            B(Bundle {0: UInt<1>, 1: Bool}),
-                            C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                            HdlNone,
+                            HdlSome(Bundle {0: UInt<1>, 1: Bool}),
                         },
-                        flow: Duplex,
+                        flow: Sink,
                     },
                     non_empty_fields: [
                         TraceBundle {
-                            name: "B",
+                            name: "HdlSome",
                             fields: [
                                 TraceUInt {
                                     location: TraceScalarId(8),
@@ -1453,6 +1724,57 @@ Simulation {
                             },
                             flow: Source,
                         },
+                    ],
+                    ty: Enum {
+                        HdlNone,
+                        HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                    },
+                    flow: Sink,
+                },
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                },
+                flow: Sink,
+            },
+            TraceReg {
+                name: "the_reg",
+                child: TraceEnumWithFields {
+                    name: "the_reg",
+                    discriminant: TraceEnumDiscriminant {
+                        location: TraceScalarId(10),
+                        name: "$tag",
+                        ty: Enum {
+                            A,
+                            B(Bundle {0: UInt<1>, 1: Bool}),
+                            C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                        },
+                        flow: Duplex,
+                    },
+                    non_empty_fields: [
+                        TraceBundle {
+                            name: "B",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(11),
+                                    name: "0",
+                                    ty: UInt<1>,
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(12),
+                                    name: "1",
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                0: UInt<1>,
+                                /* offset = 1 */
+                                1: Bool,
+                            },
+                            flow: Source,
+                        },
                         TraceBundle {
                             name: "C",
                             fields: [
@@ -1460,13 +1782,13 @@ Simulation {
                                     name: "a",
                                     elements: [
                                         TraceUInt {
-                                            location: TraceScalarId(10),
+                                            location: TraceScalarId(13),
                                             name: "[0]",
                                             ty: UInt<1>,
                                             flow: Source,
                                         },
                                         TraceUInt {
-                                            location: TraceScalarId(11),
+                                            location: TraceScalarId(14),
                                             name: "[1]",
                                             ty: UInt<1>,
                                             flow: Source,
@@ -1476,7 +1798,7 @@ Simulation {
                                     flow: Source,
                                 },
                                 TraceSInt {
-                                    location: TraceScalarId(12),
+                                    location: TraceScalarId(15),
                                     name: "b",
                                     ty: SInt<2>,
                                     flow: Source,
@@ -1570,7 +1892,36 @@ Simulation {
         SimTrace {
             id: TraceScalarId(7),
             kind: EnumDiscriminant {
-                index: StatePartIndex<SmallSlots>(4),
+                index: StatePartIndex<SmallSlots>(0),
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                },
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(8),
+                ty: UInt<1>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(9),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: EnumDiscriminant {
+                index: StatePartIndex<SmallSlots>(5),
                 ty: Enum {
                     A,
                     B(Bundle {0: UInt<1>, 1: Bool}),
@@ -1580,32 +1931,6 @@ Simulation {
             state: 0x2,
             last_state: 0x2,
         },
-        SimTrace {
-            id: TraceScalarId(8),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(11),
-                ty: UInt<1>,
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(9),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(12),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(10),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(18),
-                ty: UInt<1>,
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
         SimTrace {
             id: TraceScalarId(11),
             kind: BigUInt {
@@ -1617,8 +1942,34 @@ Simulation {
         },
         SimTrace {
             id: TraceScalarId(12),
-            kind: BigSInt {
+            kind: BigBool {
                 index: StatePartIndex<BigSlots>(20),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(13),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(26),
+                ty: UInt<1>,
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(14),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(27),
+                ty: UInt<1>,
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(15),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(28),
                 ty: SInt<2>,
             },
             state: 0x3,
@@ -1637,7 +1988,7 @@ Simulation {
     ],
     instant: 16 μs,
     clocks_triggered: [
-        StatePartIndex<SmallSlots>(1),
+        StatePartIndex<SmallSlots>(2),
     ],
     ..
 }
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/enums.vcd b/crates/fayalite/tests/sim/expected/enums.vcd
index 48a493b..07cbd32 100644
--- a/crates/fayalite/tests/sim/expected/enums.vcd
+++ b/crates/fayalite/tests/sim/expected/enums.vcd
@@ -9,18 +9,25 @@ $var wire 2 $ which_in $end
 $var wire 4 % data_in $end
 $var wire 2 & which_out $end
 $var wire 4 ' data_out $end
-$scope struct the_reg $end
+$scope struct b_out $end
 $var string 1 ( \$tag $end
+$scope struct HdlSome $end
+$var wire 1 ) \0 $end
+$var wire 1 * \1 $end
+$upscope $end
+$upscope $end
+$scope struct the_reg $end
+$var string 1 + \$tag $end
 $scope struct B $end
-$var reg 1 ) \0 $end
-$var reg 1 * \1 $end
+$var reg 1 , \0 $end
+$var reg 1 - \1 $end
 $upscope $end
 $scope struct C $end
 $scope struct a $end
-$var reg 1 + \[0] $end
-$var reg 1 , \[1] $end
+$var reg 1 . \[0] $end
+$var reg 1 / \[1] $end
 $upscope $end
-$var reg 2 - b $end
+$var reg 2 0 b $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -33,12 +40,15 @@ b0 $
 b0 %
 b0 &
 b0 '
-sA\x20(0) (
+sHdlNone\x20(0) (
 0)
 0*
-0+
+sA\x20(0) +
 0,
-b0 -
+0-
+0.
+0/
+b0 0
 $end
 #1000000
 1!
@@ -55,7 +65,8 @@ b1 $
 #5000000
 1!
 b1 &
-sB\x20(1) (
+sHdlSome\x20(1) (
+sB\x20(1) +
 #6000000
 0#
 b0 $
@@ -72,8 +83,10 @@ b1111 %
 b11 '
 1)
 1*
-1+
 1,
+1-
+1.
+1/
 #10000000
 0!
 #11000000
@@ -85,8 +98,11 @@ b10 $
 1!
 b10 &
 b1111 '
-sC\x20(2) (
-b11 -
+sHdlNone\x20(0) (
+0)
+0*
+sC\x20(2) +
+b11 0
 #14000000
 0!
 #15000000

From 36bad529789f70e1732c6f43ef12a9bfd0e3afc7 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 18 Dec 2024 20:50:50 -0800
Subject: [PATCH 139/190] sim: fix sim.write to struct

---
 crates/fayalite/src/sim.rs   | 86 +++++++++++++++++++++++++++---------
 crates/fayalite/tests/sim.rs | 10 ++++-
 2 files changed, 73 insertions(+), 23 deletions(-)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 10fbb92..988afca 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -6429,7 +6429,7 @@ impl_to_sim_value_for_int_value!(SIntValue, SInt, SIntType);
 struct SimulationImpl {
     state: interpreter::State,
     io: Expr<Bundle>,
-    uninitialized_inputs: HashSet<Target>,
+    uninitialized_inputs: HashMap<Target, Vec<Target>>,
     io_targets: HashMap<Target, CompiledValue<CanonicalType>>,
     made_initial_step: bool,
     needs_settle: bool,
@@ -6483,37 +6483,52 @@ impl SimulationImpl {
             .field("clocks_triggered", clocks_triggered)
             .finish_non_exhaustive()
     }
-    fn parse_io(&mut self, target: Target, value: CompiledValue<CanonicalType>) {
+    /// returns `true` if `target` or any sub-targets are uninitialized inputs
+    fn parse_io(&mut self, target: Target, value: CompiledValue<CanonicalType>) -> bool {
         self.io_targets.insert(target, value);
         match value.layout.body {
             CompiledTypeLayoutBody::Scalar => match target.flow() {
-                Flow::Source => {}
+                Flow::Source => false,
                 Flow::Sink => {
-                    self.uninitialized_inputs.insert(target);
+                    self.uninitialized_inputs.insert(target, vec![]);
+                    true
                 }
                 Flow::Duplex => unreachable!(),
             },
             CompiledTypeLayoutBody::Array { .. } => {
                 let value = value.map_ty(Array::from_canonical);
+                let mut sub_targets = Vec::new();
                 for index in 0..value.layout.ty.len() {
-                    self.parse_io(
-                        target.join(
-                            TargetPathElement::from(TargetPathArrayElement { index })
-                                .intern_sized(),
-                        ),
-                        value.element(index),
+                    let sub_target = target.join(
+                        TargetPathElement::from(TargetPathArrayElement { index }).intern_sized(),
                     );
+                    if self.parse_io(sub_target, value.element(index)) {
+                        sub_targets.push(sub_target);
+                    }
+                }
+                if sub_targets.is_empty() {
+                    false
+                } else {
+                    self.uninitialized_inputs.insert(target, sub_targets);
+                    true
                 }
             }
             CompiledTypeLayoutBody::Bundle { .. } => {
                 let value = value.map_ty(Bundle::from_canonical);
+                let mut sub_targets = Vec::new();
                 for BundleField { name, .. } in value.layout.ty.fields() {
-                    self.parse_io(
-                        target.join(
-                            TargetPathElement::from(TargetPathBundleField { name }).intern_sized(),
-                        ),
-                        value.field_by_name(name),
+                    let sub_target = target.join(
+                        TargetPathElement::from(TargetPathBundleField { name }).intern_sized(),
                     );
+                    if self.parse_io(sub_target, value.field_by_name(name)) {
+                        sub_targets.push(sub_target);
+                    }
+                }
+                if sub_targets.is_empty() {
+                    false
+                } else {
+                    self.uninitialized_inputs.insert(target, sub_targets);
+                    true
                 }
             }
         }
@@ -6522,7 +6537,7 @@ impl SimulationImpl {
         let mut retval = Self {
             state: State::new(compiled.insns),
             io: compiled.io.to_expr(),
-            uninitialized_inputs: HashSet::new(),
+            uninitialized_inputs: HashMap::new(),
             io_targets: HashMap::new(),
             made_initial_step: false,
             needs_settle: true,
@@ -6791,6 +6806,35 @@ impl SimulationImpl {
         };
         panic!("simulator read/write expression must not have dynamic array indexes");
     }
+    fn mark_target_as_initialized(&mut self, mut target: Target) {
+        fn remove_target_and_children(
+            uninitialized_inputs: &mut HashMap<Target, Vec<Target>>,
+            target: Target,
+        ) {
+            let Some(children) = uninitialized_inputs.remove(&target) else {
+                return;
+            };
+            for child in children {
+                remove_target_and_children(uninitialized_inputs, child);
+            }
+        }
+        remove_target_and_children(&mut self.uninitialized_inputs, target);
+        while let Some(target_child) = target.child() {
+            let parent = target_child.parent();
+            for child in self
+                .uninitialized_inputs
+                .get(&*parent)
+                .map(|v| &**v)
+                .unwrap_or(&[])
+            {
+                if self.uninitialized_inputs.contains_key(child) {
+                    return;
+                }
+            }
+            target = *parent;
+            self.uninitialized_inputs.remove(&target);
+        }
+    }
     #[track_caller]
     fn read_helper(&mut self, io: Expr<CanonicalType>) -> CompiledValue<CanonicalType> {
         let Some(target) = io.target() else {
@@ -6810,7 +6854,7 @@ impl SimulationImpl {
                     self.settle();
                 }
                 Flow::Sink => {
-                    if self.uninitialized_inputs.contains(&*target) {
+                    if self.uninitialized_inputs.contains_key(&*target) {
                         panic!("can't read from an uninitialized input");
                     }
                 }
@@ -6833,7 +6877,7 @@ impl SimulationImpl {
             Flow::Duplex => unreachable!(),
         }
         if !self.made_initial_step {
-            self.uninitialized_inputs.remove(&*target);
+            self.mark_target_as_initialized(*target);
         }
         self.needs_settle = true;
         compiled_value
@@ -7136,11 +7180,11 @@ pub struct Simulation<T: BundleType> {
     io: Expr<T>,
 }
 
-struct SortedSetDebug<'a, T>(&'a HashSet<T>);
+struct SortedSetDebug<'a, T, V>(&'a HashMap<T, V>);
 
-impl<T: fmt::Debug> fmt::Debug for SortedSetDebug<'_, T> {
+impl<T: fmt::Debug, V> fmt::Debug for SortedSetDebug<'_, T, V> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        let mut entries = Vec::from_iter(self.0.iter().map(|v| {
+        let mut entries = Vec::from_iter(self.0.iter().map(|(v, _)| {
             if f.alternate() {
                 format!("{v:#?}")
             } else {
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index bea7d93..a249235 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -255,8 +255,14 @@ fn test_shift_register() {
     let mut sim = Simulation::new(shift_register());
     let mut writer = RcWriter::default();
     sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
-    sim.write_clock(sim.io().cd.clk, false);
-    sim.write_reset(sim.io().cd.rst, true);
+    sim.write(
+        sim.io().cd,
+        #[hdl]
+        ClockDomain {
+            clk: false.to_clock(),
+            rst: true.to_sync_reset(),
+        },
+    );
     sim.write_bool(sim.io().d, false);
     sim.advance_time(SimDuration::from_micros(1));
     sim.write_clock(sim.io().cd.clk, true);

From 9b06019bf54303e51989484a0cfa1641b0e9d543 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 18 Dec 2024 21:15:09 -0800
Subject: [PATCH 140/190] make sim::Compiler not print things to stdout unless
 you ask for it

---
 crates/fayalite/src/sim.rs | 26 ++++++++++++++++++++------
 1 file changed, 20 insertions(+), 6 deletions(-)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 988afca..cb6228d 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -1601,6 +1601,14 @@ impl MakeTraceDeclTarget {
     }
 }
 
+struct DebugOpaque<T>(T);
+
+impl<T> fmt::Debug for DebugOpaque<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.write_str("<...>")
+    }
+}
+
 #[derive(Debug)]
 pub struct Compiler {
     insns: Insns<InsnsBuilding>,
@@ -1622,6 +1630,7 @@ pub struct Compiler {
     registers: Vec<Register>,
     traces: SimTraces<Vec<SimTrace<SimTraceKind, ()>>>,
     memories: Vec<Memory>,
+    dump_assignments_dot: Option<DebugOpaque<Box<dyn Fn(&dyn fmt::Debug)>>>,
 }
 
 impl Compiler {
@@ -1647,8 +1656,14 @@ impl Compiler {
             registers: Vec::new(),
             traces: SimTraces(Vec::new()),
             memories: Vec::new(),
+            dump_assignments_dot: None,
         }
     }
+    #[doc(hidden)]
+    /// This is explicitly unstable and may be changed/removed at any time
+    pub fn dump_assignments_dot(&mut self, callback: Box<dyn Fn(&dyn fmt::Debug)>) {
+        self.dump_assignments_dot = Some(DebugOpaque(callback));
+    }
     fn new_sim_trace(&mut self, kind: SimTraceKind) -> TraceScalarId {
         let id = TraceScalarId(self.traces.0.len());
         self.traces.0.push(SimTrace {
@@ -4650,12 +4665,11 @@ impl Compiler {
     fn process_assignments(&mut self) {
         self.assignments
             .finalize(self.insns.state_layout().ty.clone().into());
-        println!(
-            "{:#?}",
-            petgraph::dot::Dot::new(&petgraph::graph::DiGraph::<_, _, usize>::from_elements(
-                self.assignments.elements()
-            ))
-        );
+        if let Some(DebugOpaque(dump_assignments_dot)) = &self.dump_assignments_dot {
+            let graph =
+                petgraph::graph::DiGraph::<_, _, usize>::from_elements(self.assignments.elements());
+            dump_assignments_dot(&petgraph::dot::Dot::new(&graph));
+        }
         let assignments_order: Vec<_> = match petgraph::algo::toposort(&self.assignments, None) {
             Ok(nodes) => nodes
                 .into_iter()

From 2ab84280627c5a7f5d9d07192cdd0edb36a25faa Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sat, 28 Dec 2024 23:34:46 -0800
Subject: [PATCH 141/190] upgrade syn version

---
 Cargo.lock | 8 ++++----
 Cargo.toml | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 2e50abc..23cdc34 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -543,9 +543,9 @@ dependencies = [
 
 [[package]]
 name = "proc-macro2"
-version = "1.0.83"
+version = "1.0.92"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0b33eb56c327dec362a9e55b3ad14f9d2f0904fb5a5b03b513ab5465399e9f43"
+checksum = "37d3544b3f2748c54e147655edb5025752e2303145b5aefb3c3ea2c78b973bb0"
 dependencies = [
  "unicode-ident",
 ]
@@ -647,9 +647,9 @@ checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f"
 
 [[package]]
 name = "syn"
-version = "2.0.66"
+version = "2.0.93"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c42f3f41a2de00b01c0aaad383c5a45241efc8b2d1eda5661812fda5f3cdcff5"
+checksum = "9c786062daee0d6db1132800e623df74274a0a87322d8e183338e01b3d98d058"
 dependencies = [
  "proc-macro2",
  "quote",
diff --git a/Cargo.toml b/Cargo.toml
index 2cfa586..54de3a8 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -37,7 +37,7 @@ quote = "1.0.36"
 serde = { version = "1.0.202", features = ["derive"] }
 serde_json = { version = "1.0.117", features = ["preserve_order"] }
 sha2 = "0.10.8"
-syn = { version = "2.0.66", features = ["full", "fold", "visit", "extra-traits"] }
+syn = { version = "2.0.93", features = ["full", "fold", "visit", "extra-traits"] }
 tempfile = "3.10.1"
 thiserror = "1.0.61"
 trybuild = "1.0"

From 7005fa3330d6715008a3e3cd0b57c71108b465d2 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 27 Dec 2024 04:02:39 -0800
Subject: [PATCH 142/190] implement handling #[cfg] and #[cfg_attr] in proc
 macro inputs

---
 crates/fayalite-proc-macros-impl/src/lib.rs   |  363 ++-
 .../src/process_cfg.rs                        | 2527 +++++++++++++++++
 crates/fayalite/src/lib.rs                    |   50 +
 3 files changed, 2929 insertions(+), 11 deletions(-)
 create mode 100644 crates/fayalite-proc-macros-impl/src/process_cfg.rs

diff --git a/crates/fayalite-proc-macros-impl/src/lib.rs b/crates/fayalite-proc-macros-impl/src/lib.rs
index 0ffd4d4..1b1b61f 100644
--- a/crates/fayalite-proc-macros-impl/src/lib.rs
+++ b/crates/fayalite-proc-macros-impl/src/lib.rs
@@ -3,14 +3,20 @@
 #![cfg_attr(test, recursion_limit = "512")]
 use proc_macro2::{Span, TokenStream};
 use quote::{quote, ToTokens};
-use std::io::{ErrorKind, Write};
+use std::{
+    collections::{hash_map::Entry, HashMap},
+    io::{ErrorKind, Write},
+};
 use syn::{
-    bracketed, parenthesized,
+    bracketed,
+    ext::IdentExt,
+    parenthesized,
     parse::{Parse, ParseStream, Parser},
     parse_quote,
-    punctuated::Pair,
+    punctuated::{Pair, Punctuated},
     spanned::Spanned,
-    AttrStyle, Attribute, Error, Item, ItemFn, Token,
+    token::{Bracket, Paren},
+    AttrStyle, Attribute, Error, Ident, Item, ItemFn, LitBool, LitStr, Meta, Token,
 };
 
 mod fold;
@@ -19,6 +25,7 @@ mod hdl_enum;
 mod hdl_type_alias;
 mod hdl_type_common;
 mod module;
+mod process_cfg;
 
 pub(crate) trait CustomToken:
     Copy
@@ -59,6 +66,11 @@ mod kw {
         };
     }
 
+    custom_keyword!(__evaluated_cfgs);
+    custom_keyword!(all);
+    custom_keyword!(any);
+    custom_keyword!(cfg);
+    custom_keyword!(cfg_attr);
     custom_keyword!(clock_domain);
     custom_keyword!(connect_inexact);
     custom_keyword!(custom_bounds);
@@ -75,6 +87,7 @@ mod kw {
     custom_keyword!(no_reset);
     custom_keyword!(no_runtime_generics);
     custom_keyword!(no_static);
+    custom_keyword!(not);
     custom_keyword!(outline_generated);
     custom_keyword!(output);
     custom_keyword!(reg_builder);
@@ -901,15 +914,335 @@ fn hdl_module_impl(item: ItemFn) -> syn::Result<TokenStream> {
     Ok(contents)
 }
 
-pub fn hdl_module(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
-    let kw = kw::hdl_module::default();
-    hdl_module_impl(syn::parse2(quote! { #[#kw(#attr)] #item })?)
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) enum CfgExpr {
+    Option {
+        ident: Ident,
+        value: Option<(Token![=], LitStr)>,
+    },
+    All {
+        all: kw::all,
+        paren: Paren,
+        exprs: Punctuated<CfgExpr, Token![,]>,
+    },
+    Any {
+        any: kw::any,
+        paren: Paren,
+        exprs: Punctuated<CfgExpr, Token![,]>,
+    },
+    Not {
+        not: kw::not,
+        paren: Paren,
+        expr: Box<CfgExpr>,
+        trailing_comma: Option<Token![,]>,
+    },
 }
 
-pub fn hdl_attr(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
-    let kw = kw::hdl::default();
-    let item = quote! { #[#kw(#attr)] #item };
-    let item = syn::parse2::<Item>(item)?;
+impl Parse for CfgExpr {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        match input.cursor().ident() {
+            Some((_, cursor)) if cursor.eof() => {
+                return Ok(CfgExpr::Option {
+                    ident: input.call(Ident::parse_any)?,
+                    value: None,
+                });
+            }
+            _ => {}
+        }
+        if input.peek(Ident::peek_any) && input.peek2(Token![=]) {
+            return Ok(CfgExpr::Option {
+                ident: input.call(Ident::parse_any)?,
+                value: Some((input.parse()?, input.parse()?)),
+            });
+        }
+        let contents;
+        if input.peek(kw::all) {
+            Ok(CfgExpr::All {
+                all: input.parse()?,
+                paren: parenthesized!(contents in input),
+                exprs: contents.call(Punctuated::parse_terminated)?,
+            })
+        } else if input.peek(kw::any) {
+            Ok(CfgExpr::Any {
+                any: input.parse()?,
+                paren: parenthesized!(contents in input),
+                exprs: contents.call(Punctuated::parse_terminated)?,
+            })
+        } else if input.peek(kw::not) {
+            Ok(CfgExpr::Not {
+                not: input.parse()?,
+                paren: parenthesized!(contents in input),
+                expr: contents.parse()?,
+                trailing_comma: contents.parse()?,
+            })
+        } else {
+            Err(input.error("expected cfg-pattern"))
+        }
+    }
+}
+
+impl ToTokens for CfgExpr {
+    fn to_tokens(&self, tokens: &mut TokenStream) {
+        match self {
+            CfgExpr::Option { ident, value } => {
+                ident.to_tokens(tokens);
+                if let Some((eq, value)) = value {
+                    eq.to_tokens(tokens);
+                    value.to_tokens(tokens);
+                }
+            }
+            CfgExpr::All { all, paren, exprs } => {
+                all.to_tokens(tokens);
+                paren.surround(tokens, |tokens| exprs.to_tokens(tokens));
+            }
+            CfgExpr::Any { any, paren, exprs } => {
+                any.to_tokens(tokens);
+                paren.surround(tokens, |tokens| exprs.to_tokens(tokens));
+            }
+            CfgExpr::Not {
+                not,
+                paren,
+                expr,
+                trailing_comma,
+            } => {
+                not.to_tokens(tokens);
+                paren.surround(tokens, |tokens| {
+                    expr.to_tokens(tokens);
+                    trailing_comma.to_tokens(tokens);
+                });
+            }
+        }
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct Cfg {
+    cfg: kw::cfg,
+    paren: Paren,
+    expr: CfgExpr,
+    trailing_comma: Option<Token![,]>,
+}
+
+impl Cfg {
+    fn parse_meta(meta: &Meta) -> syn::Result<Self> {
+        syn::parse2(meta.to_token_stream())
+    }
+}
+
+impl ToTokens for Cfg {
+    fn to_tokens(&self, tokens: &mut TokenStream) {
+        let Self {
+            cfg,
+            paren,
+            expr,
+            trailing_comma,
+        } = self;
+        cfg.to_tokens(tokens);
+        paren.surround(tokens, |tokens| {
+            expr.to_tokens(tokens);
+            trailing_comma.to_tokens(tokens);
+        });
+    }
+}
+
+impl Parse for Cfg {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let contents;
+        Ok(Self {
+            cfg: input.parse()?,
+            paren: parenthesized!(contents in input),
+            expr: contents.parse()?,
+            trailing_comma: contents.parse()?,
+        })
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub(crate) struct CfgAttr {
+    cfg_attr: kw::cfg_attr,
+    paren: Paren,
+    expr: CfgExpr,
+    comma: Token![,],
+    attrs: Punctuated<Meta, Token![,]>,
+}
+
+impl CfgAttr {
+    pub(crate) fn to_cfg(&self) -> Cfg {
+        Cfg {
+            cfg: kw::cfg(self.cfg_attr.span),
+            paren: self.paren,
+            expr: self.expr.clone(),
+            trailing_comma: None,
+        }
+    }
+    fn parse_meta(meta: &Meta) -> syn::Result<Self> {
+        syn::parse2(meta.to_token_stream())
+    }
+}
+
+impl Parse for CfgAttr {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let contents;
+        Ok(Self {
+            cfg_attr: input.parse()?,
+            paren: parenthesized!(contents in input),
+            expr: contents.parse()?,
+            comma: contents.parse()?,
+            attrs: contents.call(Punctuated::parse_terminated)?,
+        })
+    }
+}
+
+pub(crate) struct CfgAndValue {
+    cfg: Cfg,
+    eq_token: Token![=],
+    value: LitBool,
+}
+
+impl Parse for CfgAndValue {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        Ok(Self {
+            cfg: input.parse()?,
+            eq_token: input.parse()?,
+            value: input.parse()?,
+        })
+    }
+}
+
+pub(crate) struct Cfgs<T> {
+    pub(crate) bracket: Bracket,
+    pub(crate) cfgs_map: HashMap<Cfg, T>,
+    pub(crate) cfgs_list: Vec<Cfg>,
+}
+
+impl<T> Default for Cfgs<T> {
+    fn default() -> Self {
+        Self {
+            bracket: Default::default(),
+            cfgs_map: Default::default(),
+            cfgs_list: Default::default(),
+        }
+    }
+}
+
+impl<T> Cfgs<T> {
+    fn insert_cfg(&mut self, cfg: Cfg, value: T) {
+        match self.cfgs_map.entry(cfg) {
+            Entry::Occupied(_) => {}
+            Entry::Vacant(entry) => {
+                self.cfgs_list.push(entry.key().clone());
+                entry.insert(value);
+            }
+        }
+    }
+}
+
+impl Parse for Cfgs<bool> {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let contents;
+        let bracket = bracketed!(contents in input);
+        let mut cfgs_map = HashMap::new();
+        let mut cfgs_list = Vec::new();
+        for CfgAndValue {
+            cfg,
+            eq_token,
+            value,
+        } in contents.call(Punctuated::<CfgAndValue, Token![,]>::parse_terminated)?
+        {
+            let _ = eq_token;
+            match cfgs_map.entry(cfg) {
+                Entry::Occupied(_) => {}
+                Entry::Vacant(entry) => {
+                    cfgs_list.push(entry.key().clone());
+                    entry.insert(value.value);
+                }
+            }
+        }
+        Ok(Self {
+            bracket,
+            cfgs_map,
+            cfgs_list,
+        })
+    }
+}
+
+impl Parse for Cfgs<()> {
+    fn parse(input: ParseStream) -> syn::Result<Self> {
+        let contents;
+        let bracket = bracketed!(contents in input);
+        let mut cfgs_map = HashMap::new();
+        let mut cfgs_list = Vec::new();
+        for cfg in contents.call(Punctuated::<Cfg, Token![,]>::parse_terminated)? {
+            match cfgs_map.entry(cfg) {
+                Entry::Occupied(_) => {}
+                Entry::Vacant(entry) => {
+                    cfgs_list.push(entry.key().clone());
+                    entry.insert(());
+                }
+            }
+        }
+        Ok(Self {
+            bracket,
+            cfgs_map,
+            cfgs_list,
+        })
+    }
+}
+
+impl ToTokens for Cfgs<()> {
+    fn to_tokens(&self, tokens: &mut TokenStream) {
+        let Self {
+            bracket,
+            cfgs_map: _,
+            cfgs_list,
+        } = self;
+        bracket.surround(tokens, |tokens| {
+            for cfg in cfgs_list {
+                cfg.to_tokens(tokens);
+                <Token![,]>::default().to_tokens(tokens);
+            }
+        });
+    }
+}
+
+fn hdl_main(
+    kw: impl CustomToken,
+    attr: TokenStream,
+    item: TokenStream,
+) -> syn::Result<TokenStream> {
+    let (evaluated_cfgs, attr): (_, TokenStream) = Parser::parse2(
+        |input: ParseStream| {
+            if input.peek(Bracket) && input.peek2(kw::__evaluated_cfgs) {
+                let cfgs = input.parse()?;
+                let _: kw::__evaluated_cfgs = input.parse()?;
+                Ok((Some(cfgs), input.parse()?))
+            } else {
+                Ok((None, input.parse()?))
+            }
+        },
+        attr,
+    )?;
+    let cfgs = if let Some(cfgs) = evaluated_cfgs {
+        cfgs
+    } else {
+        let cfgs = process_cfg::collect_cfgs(syn::parse2(item.clone())?)?;
+        if cfgs.cfgs_list.is_empty() {
+            Cfgs::default()
+        } else {
+            let key = kw::__evaluated_cfgs::default();
+            return Ok(quote! {
+                ::fayalite::__cfg_expansion_helper! {
+                    []
+                    #cfgs
+                    #[::fayalite::#kw:(#key #attr)] { #item }
+                }
+            });
+        }
+    };
+    let item = syn::parse2(quote! { #[#kw(#attr)] #item })?;
+    let Some(item) = process_cfg::process_cfgs(item, cfgs)? else {
+        return Ok(TokenStream::new());
+    };
     match item {
         Item::Enum(item) => hdl_enum::hdl_enum(item),
         Item::Struct(item) => hdl_bundle::hdl_bundle(item),
@@ -921,3 +1254,11 @@ pub fn hdl_attr(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream
         )),
     }
 }
+
+pub fn hdl_module(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
+    hdl_main(kw::hdl_module::default(), attr, item)
+}
+
+pub fn hdl_attr(attr: TokenStream, item: TokenStream) -> syn::Result<TokenStream> {
+    hdl_main(kw::hdl::default(), attr, item)
+}
diff --git a/crates/fayalite-proc-macros-impl/src/process_cfg.rs b/crates/fayalite-proc-macros-impl/src/process_cfg.rs
new file mode 100644
index 0000000..5cff08f
--- /dev/null
+++ b/crates/fayalite-proc-macros-impl/src/process_cfg.rs
@@ -0,0 +1,2527 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::{Cfg, CfgAttr, Cfgs, Errors};
+use proc_macro2::Ident;
+use std::{collections::VecDeque, marker::PhantomData};
+use syn::{
+    punctuated::{Pair, Punctuated},
+    Token,
+};
+
+struct State<P: Phase> {
+    cfgs: Cfgs<P::CfgsValue>,
+    errors: Errors,
+    _phantom: PhantomData<P>,
+}
+
+impl<P: Phase> State<P> {
+    #[must_use]
+    fn eval_cfg(&mut self, cfg: Cfg) -> bool {
+        struct MyDispatch<'a> {
+            cfg: Cfg,
+            _phantom: PhantomData<&'a ()>,
+        }
+        impl<'a> PhaseDispatch for MyDispatch<'a> {
+            type Args<P: Phase> = &'a mut State<P>;
+            type Output<P: Phase> = bool;
+
+            fn dispatch_collect(
+                self,
+                args: Self::Args<CollectCfgsPhase>,
+            ) -> Self::Output<CollectCfgsPhase> {
+                args.cfgs.insert_cfg(self.cfg, ());
+                true
+            }
+
+            fn dispatch_process(
+                self,
+                args: Self::Args<ProcessCfgsPhase>,
+            ) -> Self::Output<ProcessCfgsPhase> {
+                if let Some(&retval) = args.cfgs.cfgs_map.get(&self.cfg) {
+                    retval
+                } else {
+                    args.errors.error(self.cfg, "unrecognized cfg -- cfg wasn't evaluated when running `__cfg_expansion_helper!`");
+                    true
+                }
+            }
+        }
+        P::dispatch(
+            MyDispatch {
+                cfg,
+                _phantom: PhantomData,
+            },
+            self,
+        )
+    }
+    #[must_use]
+    fn eval_cfgs(
+        &mut self,
+        mut attrs: Vec<syn::Attribute>,
+    ) -> Option<Output<Vec<syn::Attribute>, P>> {
+        let mut queue = VecDeque::from(attrs);
+        attrs = Vec::with_capacity(queue.len()); // cfg_attr is rare, and cfg can't increase length
+        while let Some(attr) = queue.pop_front() {
+            if attr.path().is_ident("cfg") {
+                if let Some(cfg) = self.errors.ok(Cfg::parse_meta(&attr.meta)) {
+                    if !self.eval_cfg(cfg) {
+                        return None;
+                    }
+                    continue;
+                }
+            } else if attr.path().is_ident("cfg_attr") {
+                if let Some(cfg_attr) = self.errors.ok(CfgAttr::parse_meta(&attr.meta)) {
+                    if self.eval_cfg(cfg_attr.to_cfg()) {
+                        // push onto queue since cfg_attr(<cond1>, cfg_attr(<cond2>, <attr>)) is valid
+                        for meta in cfg_attr.attrs {
+                            queue.push_front(syn::Attribute {
+                                pound_token: attr.pound_token,
+                                style: attr.style,
+                                bracket_token: attr.bracket_token,
+                                meta,
+                            });
+                        }
+                    }
+                    continue;
+                }
+            }
+            attrs.push(attr);
+        }
+        Some(Output::new(attrs))
+    }
+    fn process_qself_and_path(
+        &mut self,
+        qself: Option<syn::QSelf>,
+        path: syn::Path,
+    ) -> Option<(Output<Option<syn::QSelf>, P>, Output<syn::Path, P>)> {
+        let qself = if let Some(syn::QSelf {
+            lt_token,
+            ty,
+            position,
+            as_token,
+            gt_token,
+        }) = qself
+        {
+            ty.process(self)?.map(|ty| {
+                Some(syn::QSelf {
+                    lt_token,
+                    ty,
+                    position,
+                    as_token,
+                    gt_token,
+                })
+            })
+        } else {
+            Output::new(None)
+        };
+        let syn::Path {
+            leading_colon,
+            segments,
+        } = path;
+        // path segments don't get removed
+        let path = segments.process(self)?.map(|segments| syn::Path {
+            leading_colon,
+            segments,
+        });
+        Some((qself, path))
+    }
+}
+
+trait PhaseDispatch {
+    type Args<P: Phase>;
+    type Output<P: Phase>;
+    fn dispatch_collect(self, args: Self::Args<CollectCfgsPhase>)
+        -> Self::Output<CollectCfgsPhase>;
+    fn dispatch_process(self, args: Self::Args<ProcessCfgsPhase>)
+        -> Self::Output<ProcessCfgsPhase>;
+}
+
+trait Phase: Sized + 'static {
+    type Output<T>;
+    type CfgsValue;
+    fn output_new<T>(v: T) -> Output<T, Self>;
+    fn output_map<T, U, F: FnOnce(T) -> U>(v: Output<T, Self>, f: F) -> Output<U, Self>;
+    fn output_zip<T, U>(t: Output<T, Self>, u: Output<U, Self>) -> Output<(T, U), Self>;
+    fn dispatch<D: PhaseDispatch>(d: D, args: D::Args<Self>) -> D::Output<Self>;
+}
+
+struct CollectCfgsPhase;
+
+impl Phase for CollectCfgsPhase {
+    type Output<T> = ();
+    type CfgsValue = ();
+
+    fn output_new<T>(_v: T) -> Output<T, Self> {
+        Output(())
+    }
+
+    fn output_map<T, U, F: FnOnce(T) -> U>(_v: Output<T, Self>, _f: F) -> Output<U, Self> {
+        Output(())
+    }
+
+    fn output_zip<T, U>(_t: Output<T, Self>, _u: Output<U, Self>) -> Output<(T, U), Self> {
+        Output(())
+    }
+
+    fn dispatch<D: PhaseDispatch>(d: D, args: D::Args<Self>) -> D::Output<Self> {
+        d.dispatch_collect(args)
+    }
+}
+
+struct ProcessCfgsPhase;
+
+impl Phase for ProcessCfgsPhase {
+    type Output<T> = T;
+    type CfgsValue = bool;
+
+    fn output_new<T>(v: T) -> Output<T, Self> {
+        Output(v)
+    }
+
+    fn output_map<T, U, F: FnOnce(T) -> U>(v: Output<T, Self>, f: F) -> Output<U, Self> {
+        Output(f(v.0))
+    }
+
+    fn output_zip<T, U>(t: Output<T, Self>, u: Output<U, Self>) -> Output<(T, U), Self> {
+        Output((t.0, u.0))
+    }
+
+    fn dispatch<D: PhaseDispatch>(d: D, args: D::Args<Self>) -> D::Output<Self> {
+        d.dispatch_process(args)
+    }
+}
+
+struct Output<T, P: Phase>(P::Output<T>);
+
+trait OutputZip<P: Phase>: Sized {
+    type Output;
+    fn zip(self) -> Output<Self::Output, P>;
+    fn call<R, F: FnOnce(Self::Output) -> R>(self, f: F) -> Output<R, P> {
+        self.zip().map(f)
+    }
+}
+
+impl<P: Phase> OutputZip<P> for () {
+    type Output = ();
+
+    fn zip(self) -> Output<Self::Output, P> {
+        Output::new(())
+    }
+}
+
+impl<P: Phase, T> OutputZip<P> for (Output<T, P>,) {
+    type Output = (T,);
+
+    fn zip(self) -> Output<Self::Output, P> {
+        self.0.map(|v| (v,))
+    }
+}
+
+macro_rules! impl_zip {
+    ($first_arg:ident: $first_T:ident, $($arg:ident: $T:ident),* $(,)?) => {
+        impl_zip!(@step [], [($first_arg: $first_T) $(($arg: $T))*], (),);
+    };
+    (
+        @impl($first_arg:tt,),
+        $tuple_pat:tt,
+    ) => {};
+    (
+        @impl(($first_arg:ident: $first_T:ident),
+            $(($arg:ident: $T:ident),)*),
+        $tuple_pat:tt,
+    ) => {
+        impl<$first_T, $($T,)* P: Phase> OutputZip<P> for (Output<$first_T, P>, $(Output<$T, P>),*) {
+            type Output = ($first_T, $($T),*);
+            fn zip(self) -> Output<($first_T, $($T),*), P> {
+                let (tuples, $($arg),*) = self;
+                $(let tuples = P::output_zip(tuples, $arg);)*
+                tuples.map(|$tuple_pat| ($first_arg, $($arg),*))
+            }
+        }
+    };
+    (
+        @step [$($cur:tt)*],
+        [],
+        $tuple_pat:tt,
+    ) => {};
+    (
+        @step [$($cur:tt)*],
+        [($next_arg:ident: $next_T:ident) $($rest:tt)*],
+        (),
+    ) => {
+        impl_zip!(@impl($($cur,)* ($next_arg: $next_T),), $next_arg,);
+        impl_zip!(@step [$($cur)* ($next_arg: $next_T)], [$($rest)*], $next_arg,);
+    };
+    (
+        @step [$($cur:tt)*],
+        [($next_arg:ident: $next_T:ident) $($rest:tt)*],
+        $tuple_pat:tt,
+    ) => {
+        impl_zip!(@impl($($cur,)* ($next_arg: $next_T),), ($tuple_pat, $next_arg),);
+        impl_zip!(@step [$($cur)* ($next_arg: $next_T)], [$($rest)*], ($tuple_pat, $next_arg),);
+    };
+}
+
+impl_zip!(t0: T0, t1: T1, t2: T2, t3: T3, t4: T4, t5: T5, t6: T6, t7: T7, t8: T8, t9: T9, t10: T10, t11: T11);
+
+impl<T, P: Phase> Copy for Output<T, P> where P::Output<T>: Copy {}
+
+impl<T, P: Phase> Clone for Output<T, P>
+where
+    P::Output<T>: Clone,
+{
+    fn clone(&self) -> Self {
+        Self(self.0.clone())
+    }
+}
+
+impl<T, P: Phase> Output<T, P> {
+    fn new(v: T) -> Self {
+        P::output_new(v)
+    }
+    fn map<U, F: FnOnce(T) -> U>(self, f: F) -> Output<U, P> {
+        P::output_map(self, f)
+    }
+}
+
+trait Process<P: Phase>: Sized {
+    #[must_use]
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>>;
+}
+
+impl<P: Phase> Process<P> for syn::Item {
+    fn process(self, _state: &mut State<P>) -> Option<Output<Self, P>> {
+        // don't recurse into items
+        Some(Output::new(self))
+    }
+}
+
+impl<P: Phase> Process<P> for Vec<syn::Attribute> {
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        state.eval_cfgs(self)
+    }
+}
+
+impl<T: Process<P>, P: Phase> Process<P> for Box<T> {
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        Some(T::process(*self, state)?.map(Box::new))
+    }
+}
+
+trait ProcessVecElement {
+    const REMOVE_ELEMENTS: bool;
+}
+
+impl ProcessVecElement for syn::Arm {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessVecElement for syn::Stmt {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessVecElement for syn::ForeignItem {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessVecElement for syn::ImplItem {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessVecElement for syn::Item {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessVecElement for syn::TraitItem {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl<T: Process<P> + ProcessVecElement, P: Phase> Process<P> for Vec<T> {
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        let mut output = Output::new(Vec::new());
+        for value in self {
+            if let Some(value) = value.process(state) {
+                output = (output, value).call(|(mut output, value)| {
+                    output.push(value);
+                    output
+                });
+            } else if !T::REMOVE_ELEMENTS {
+                return None;
+            }
+        }
+        Some(output)
+    }
+}
+
+trait ProcessOption {
+    /// if a configured-off value causes this value to be `None` instead of propagating the configuring-off
+    const REMOVE_VALUE: bool;
+}
+
+impl ProcessOption for syn::Abi {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::Block {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::WhereClause {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::Expr {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::Type {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for Box<syn::Expr> {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::AngleBracketedGenericArguments {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::ImplRestriction {
+    const REMOVE_VALUE: bool = false;
+}
+
+impl ProcessOption for syn::BoundLifetimes {
+    const REMOVE_VALUE: bool = false;
+}
+
+impl ProcessOption for (Token![=], syn::Expr) {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Token![=], syn::Type) {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Token![if], Box<syn::Expr>) {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Token![else], Box<syn::Expr>) {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Token![&], Option<syn::Lifetime>) {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Token![as], Ident) {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Ident, Token![:]) {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Option<Token![!]>, syn::Path, Token![for]) {
+    const REMOVE_VALUE: bool = false;
+}
+
+impl ProcessOption for syn::BareVariadic {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::Variadic {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::LocalInit {
+    const REMOVE_VALUE: bool = false;
+}
+
+impl ProcessOption for syn::Label {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for syn::PatRest {
+    const REMOVE_VALUE: bool = true;
+}
+
+impl ProcessOption for (Box<syn::Pat>, Token![:]) {
+    const REMOVE_VALUE: bool = false;
+}
+
+impl ProcessOption for (Token![@], Box<syn::Pat>) {
+    const REMOVE_VALUE: bool = false;
+}
+
+impl ProcessOption for (syn::token::Brace, Vec<syn::Item>) {
+    const REMOVE_VALUE: bool = false;
+}
+
+impl<T: Process<P> + ProcessOption, P: Phase> Process<P> for Option<T> {
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        if let Some(this) = self {
+            match this.process(state) {
+                Some(v) => Some(v.map(Some)),
+                None => {
+                    if T::REMOVE_VALUE {
+                        Some(Output::new(None))
+                    } else {
+                        None
+                    }
+                }
+            }
+        } else {
+            Some(Output::new(None))
+        }
+    }
+}
+
+trait ProcessPunctuatedElement {
+    const REMOVE_ELEMENTS: bool;
+}
+
+impl<T: Process<P> + ProcessPunctuatedElement, P: Phase, Punct: Default> Process<P>
+    for Punctuated<T, Punct>
+{
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        let mut output = Output::new(Punctuated::<T, Punct>::new());
+        for pair in self.into_pairs() {
+            let (value, punct) = pair.into_tuple();
+            if let Some(value) = value.process(state) {
+                output = (output, value).call(|(mut output, value)| {
+                    output.extend([Pair::new(value, punct)]);
+                    output
+                });
+            } else if !T::REMOVE_ELEMENTS {
+                return None;
+            }
+        }
+        Some(output)
+    }
+}
+
+impl ProcessPunctuatedElement for syn::PathSegment {
+    const REMOVE_ELEMENTS: bool = false;
+}
+
+impl ProcessPunctuatedElement for syn::Type {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::Expr {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::Pat {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::CapturedParam {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::GenericArgument {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::GenericParam {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::Lifetime {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::WherePredicate {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::Variant {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::FnArg {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::BareFnArg {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::TypeParamBound {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::FieldValue {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::Field {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::FieldPat {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl ProcessPunctuatedElement for syn::UseTree {
+    const REMOVE_ELEMENTS: bool = true;
+}
+
+impl<T: Process<P>, U: Process<P>, P: Phase> Process<P> for (T, U) {
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        let (t, u) = self;
+        let t = t.process(state)?;
+        let u = u.process(state)?;
+        Some((t, u).zip())
+    }
+}
+
+impl<T: Process<P>, U: Process<P>, V: Process<P>, P: Phase> Process<P> for (T, U, V) {
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        let (t, u, v) = self;
+        let t = t.process(state)?;
+        let u = u.process(state)?;
+        let v = v.process(state)?;
+        Some((t, u, v).zip())
+    }
+}
+
+macro_rules! process_no_op {
+    ($ty:ty) => {
+        impl<P: Phase> Process<P> for $ty {
+            fn process(self, _state: &mut State<P>) -> Option<Output<Self, P>> {
+                Some(Output::new(self))
+            }
+        }
+
+        impl ProcessOption for $ty {
+            const REMOVE_VALUE: bool = false;
+        }
+    };
+}
+
+process_no_op!(Token![Self]);
+process_no_op!(Token![abstract]);
+process_no_op!(Token![as]);
+process_no_op!(Token![async]);
+process_no_op!(Token![auto]);
+process_no_op!(Token![await]);
+process_no_op!(Token![become]);
+process_no_op!(Token![box]);
+process_no_op!(Token![break]);
+process_no_op!(Token![const]);
+process_no_op!(Token![continue]);
+process_no_op!(Token![crate]);
+process_no_op!(Token![default]);
+process_no_op!(Token![do]);
+process_no_op!(Token![dyn]);
+process_no_op!(Token![else]);
+process_no_op!(Token![enum]);
+process_no_op!(Token![extern]);
+process_no_op!(Token![final]);
+process_no_op!(Token![fn]);
+process_no_op!(Token![for]);
+process_no_op!(Token![if]);
+process_no_op!(Token![impl]);
+process_no_op!(Token![in]);
+process_no_op!(Token![let]);
+process_no_op!(Token![loop]);
+process_no_op!(Token![macro]);
+process_no_op!(Token![match]);
+process_no_op!(Token![mod]);
+process_no_op!(Token![move]);
+process_no_op!(Token![mut]);
+process_no_op!(Token![override]);
+process_no_op!(Token![priv]);
+process_no_op!(Token![pub]);
+process_no_op!(Token![raw]);
+process_no_op!(Token![ref]);
+process_no_op!(Token![return]);
+process_no_op!(Token![self]);
+process_no_op!(Token![static]);
+process_no_op!(Token![struct]);
+process_no_op!(Token![super]);
+process_no_op!(Token![trait]);
+process_no_op!(Token![try]);
+process_no_op!(Token![type]);
+process_no_op!(Token![typeof]);
+process_no_op!(Token![union]);
+process_no_op!(Token![unsafe]);
+process_no_op!(Token![unsized]);
+process_no_op!(Token![use]);
+process_no_op!(Token![virtual]);
+process_no_op!(Token![where]);
+process_no_op!(Token![while]);
+process_no_op!(Token![yield]);
+
+process_no_op!(Token![!]);
+process_no_op!(Token![!=]);
+process_no_op!(Token![#]);
+process_no_op!(Token![$]);
+process_no_op!(Token![%]);
+process_no_op!(Token![%=]);
+process_no_op!(Token![&]);
+process_no_op!(Token![&&]);
+process_no_op!(Token![&=]);
+process_no_op!(Token![*]);
+process_no_op!(Token![*=]);
+process_no_op!(Token![+]);
+process_no_op!(Token![+=]);
+process_no_op!(Token![,]);
+process_no_op!(Token![-]);
+process_no_op!(Token![-=]);
+process_no_op!(Token![->]);
+process_no_op!(Token![.]);
+process_no_op!(Token![..]);
+process_no_op!(Token![...]);
+process_no_op!(Token![..=]);
+process_no_op!(Token![/]);
+process_no_op!(Token![/=]);
+process_no_op!(Token![:]);
+process_no_op!(Token![::]);
+process_no_op!(Token![;]);
+process_no_op!(Token![<]);
+process_no_op!(Token![<-]);
+process_no_op!(Token![<<]);
+process_no_op!(Token![<<=]);
+process_no_op!(Token![<=]);
+process_no_op!(Token![=]);
+process_no_op!(Token![==]);
+process_no_op!(Token![=>]);
+process_no_op!(Token![>]);
+process_no_op!(Token![>=]);
+process_no_op!(Token![>>]);
+process_no_op!(Token![>>=]);
+process_no_op!(Token![?]);
+process_no_op!(Token![@]);
+process_no_op!(Token![^]);
+process_no_op!(Token![^=]);
+process_no_op!(Token![_]);
+process_no_op!(Token![|]);
+process_no_op!(Token![|=]);
+process_no_op!(Token![||]);
+process_no_op!(Token![~]);
+
+process_no_op!(syn::token::Brace);
+process_no_op!(syn::token::Bracket);
+process_no_op!(syn::token::Paren);
+process_no_op!(syn::token::Group);
+
+process_no_op!(Ident);
+process_no_op!(syn::Index);
+process_no_op!(syn::Lifetime);
+process_no_op!(syn::LitBool);
+process_no_op!(syn::LitByte);
+process_no_op!(syn::LitByteStr);
+process_no_op!(syn::LitChar);
+process_no_op!(syn::LitCStr);
+process_no_op!(syn::LitFloat);
+process_no_op!(syn::LitInt);
+process_no_op!(syn::LitStr);
+process_no_op!(proc_macro2::TokenStream);
+process_no_op!(proc_macro2::Literal);
+
+macro_rules! process_struct {
+    ($ty:path {
+        $($field:ident,)*
+    }) => {
+        impl<P: Phase> Process<P> for $ty {
+            fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+                let Self {
+                    $($field,)*
+                } = self;
+                $(let $field = $field.process(state)?;)*
+                Some(($($field,)*).call(|($($field,)*)| Self {
+                    $($field,)*
+                }))
+            }
+        }
+    };
+    ($ty:path {
+        $($fields_before:ident,)*
+        #[qself]
+        $qself:ident,
+        $path:ident,
+        $($fields_after:ident,)*
+    }) => {
+        impl<P: Phase> Process<P> for $ty {
+            fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+                let Self {
+                    $($fields_before,)*
+                    $qself,
+                    $path,
+                    $($fields_after,)*
+                } = self;
+                $(let $fields_before = $fields_before.process(state)?;)*
+                let ($qself, $path) = state.process_qself_and_path($qself, $path)?;
+                $(let $fields_after = $fields_after.process(state)?;)*
+                Some((
+                    $($fields_before,)*
+                    $qself,
+                    $path,
+                    $($fields_after,)*
+                ).call(|(
+                    $($fields_before,)*
+                    $qself,
+                    $path,
+                    $($fields_after,)*
+                )| Self {
+                    $($fields_before,)*
+                    $qself,
+                    $path,
+                    $($fields_after,)*
+                }))
+            }
+        }
+    };
+}
+
+process_struct! {
+    syn::Abi {
+        extern_token,
+        name,
+    }
+}
+
+process_struct! {
+    syn::AngleBracketedGenericArguments {
+        colon2_token,
+        lt_token,
+        args,
+        gt_token,
+    }
+}
+
+process_struct! {
+    syn::Arm {
+        attrs,
+        pat,
+        guard,
+        fat_arrow_token,
+        body,
+        comma,
+    }
+}
+
+process_struct! {
+    syn::AssocConst {
+        ident,
+        generics,
+        eq_token,
+        value,
+    }
+}
+
+process_struct! {
+    syn::AssocType {
+        ident,
+        generics,
+        eq_token,
+        ty,
+    }
+}
+
+process_struct! {
+    syn::BareFnArg {
+        attrs,
+        name,
+        ty,
+    }
+}
+
+process_struct! {
+    syn::BareVariadic {
+        attrs,
+        name,
+        dots,
+        comma,
+    }
+}
+
+process_struct! {
+    syn::Block {
+        brace_token,
+        stmts,
+    }
+}
+
+process_struct! {
+    syn::BoundLifetimes {
+        for_token,
+        lt_token,
+        lifetimes,
+        gt_token,
+    }
+}
+
+process_struct! {
+    syn::ConstParam {
+        attrs,
+        const_token,
+        ident,
+        colon_token,
+        ty,
+        eq_token,
+        default,
+    }
+}
+
+process_struct! {
+    syn::Constraint {
+        ident,
+        generics,
+        colon_token,
+        bounds,
+    }
+}
+
+process_struct! {
+    syn::DataEnum {
+        enum_token,
+        brace_token,
+        variants,
+    }
+}
+
+process_struct! {
+    syn::DataStruct {
+        struct_token,
+        fields,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::DataUnion {
+        union_token,
+        fields,
+    }
+}
+
+process_struct! {
+    syn::DeriveInput {
+        attrs,
+        vis,
+        ident,
+        generics,
+        data,
+    }
+}
+
+process_struct! {
+    syn::ExprArray {
+        attrs,
+        bracket_token,
+        elems,
+    }
+}
+
+process_struct! {
+    syn::ExprAssign {
+        attrs,
+        left,
+        eq_token,
+        right,
+    }
+}
+
+process_struct! {
+    syn::ExprAsync {
+        attrs,
+        async_token,
+        capture,
+        block,
+    }
+}
+
+process_struct! {
+    syn::ExprAwait {
+        attrs,
+        base,
+        dot_token,
+        await_token,
+    }
+}
+
+process_struct! {
+    syn::ExprBinary {
+        attrs,
+        left,
+        op,
+        right,
+    }
+}
+
+process_struct! {
+    syn::ExprBlock {
+        attrs,
+        label,
+        block,
+    }
+}
+
+process_struct! {
+    syn::ExprBreak {
+        attrs,
+        break_token,
+        label,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprCall {
+        attrs,
+        func,
+        paren_token,
+        args,
+    }
+}
+
+process_struct! {
+    syn::ExprCast {
+        attrs,
+        expr,
+        as_token,
+        ty,
+    }
+}
+
+process_struct! {
+    syn::ExprClosure {
+        attrs,
+        lifetimes,
+        constness,
+        movability,
+        asyncness,
+        capture,
+        or1_token,
+        inputs,
+        or2_token,
+        output,
+        body,
+    }
+}
+
+process_struct! {
+    syn::ExprConst {
+        attrs,
+        const_token,
+        block,
+    }
+}
+
+process_struct! {
+    syn::ExprContinue {
+        attrs,
+        continue_token,
+        label,
+    }
+}
+
+process_struct! {
+    syn::ExprField {
+        attrs,
+        base,
+        dot_token,
+        member,
+    }
+}
+
+process_struct! {
+    syn::ExprForLoop {
+        attrs,
+        label,
+        for_token,
+        pat,
+        in_token,
+        expr,
+        body,
+    }
+}
+
+process_struct! {
+    syn::ExprGroup {
+        attrs,
+        group_token,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprIf {
+        attrs,
+        if_token,
+        cond,
+        then_branch,
+        else_branch,
+    }
+}
+
+process_struct! {
+    syn::ExprIndex {
+        attrs,
+        expr,
+        bracket_token,
+        index,
+    }
+}
+
+process_struct! {
+    syn::ExprInfer {
+        attrs,
+        underscore_token,
+    }
+}
+
+process_struct! {
+    syn::ExprLet {
+        attrs,
+        let_token,
+        pat,
+        eq_token,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprLit {
+        attrs,
+        lit,
+    }
+}
+
+process_struct! {
+    syn::ExprLoop {
+        attrs,
+        label,
+        loop_token,
+        body,
+    }
+}
+
+process_struct! {
+    syn::ExprMacro {
+        attrs,
+        mac,
+    }
+}
+
+process_struct! {
+    syn::ExprMatch {
+        attrs,
+        match_token,
+        expr,
+        brace_token,
+        arms,
+    }
+}
+
+process_struct! {
+    syn::ExprMethodCall {
+        attrs,
+        receiver,
+        dot_token,
+        method,
+        turbofish,
+        paren_token,
+        args,
+    }
+}
+
+process_struct! {
+    syn::ExprParen {
+        attrs,
+        paren_token,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprPath {
+        attrs,
+        #[qself]
+        qself,
+        path,
+    }
+}
+
+process_struct! {
+    syn::ExprRange {
+        attrs,
+        start,
+        limits,
+        end,
+    }
+}
+
+process_struct! {
+    syn::ExprRawAddr {
+        attrs,
+        and_token,
+        raw,
+        mutability,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprReference {
+        attrs,
+        and_token,
+        mutability,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprRepeat {
+        attrs,
+        bracket_token,
+        expr,
+        semi_token,
+        len,
+    }
+}
+
+process_struct! {
+    syn::ExprReturn {
+        attrs,
+        return_token,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprStruct {
+        attrs,
+        #[qself]
+        qself,
+        path,
+        brace_token,
+        fields,
+        dot2_token,
+        rest,
+    }
+}
+
+process_struct! {
+    syn::ExprTry {
+        attrs,
+        expr,
+        question_token,
+    }
+}
+
+process_struct! {
+    syn::ExprTryBlock {
+        attrs,
+        try_token,
+        block,
+    }
+}
+
+process_struct! {
+    syn::ExprTuple {
+        attrs,
+        paren_token,
+        elems,
+    }
+}
+
+process_struct! {
+    syn::ExprUnary {
+        attrs,
+        op,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::ExprUnsafe {
+        attrs,
+        unsafe_token,
+        block,
+    }
+}
+
+process_struct! {
+    syn::ExprWhile {
+        attrs,
+        label,
+        while_token,
+        cond,
+        body,
+    }
+}
+
+process_struct! {
+    syn::ExprYield {
+        attrs,
+        yield_token,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::Field {
+        attrs,
+        vis,
+        mutability,
+        ident,
+        colon_token,
+        ty,
+    }
+}
+
+process_struct! {
+    syn::FieldPat {
+        attrs,
+        member,
+        colon_token,
+        pat,
+    }
+}
+
+process_struct! {
+    syn::FieldValue {
+        attrs,
+        member,
+        colon_token,
+        expr,
+    }
+}
+
+process_struct! {
+    syn::FieldsNamed {
+        brace_token,
+        named,
+    }
+}
+
+process_struct! {
+    syn::FieldsUnnamed {
+        paren_token,
+        unnamed,
+    }
+}
+
+process_struct! {
+    syn::ForeignItemFn {
+        attrs,
+        vis,
+        sig,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ForeignItemMacro {
+        attrs,
+        mac,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ForeignItemStatic {
+        attrs,
+        vis,
+        static_token,
+        mutability,
+        ident,
+        colon_token,
+        ty,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ForeignItemType {
+        attrs,
+        vis,
+        type_token,
+        ident,
+        generics,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::Generics {
+        lt_token,
+        params,
+        gt_token,
+        where_clause,
+    }
+}
+
+process_struct! {
+    syn::ImplItemConst {
+        attrs,
+        vis,
+        defaultness,
+        const_token,
+        ident,
+        generics,
+        colon_token,
+        ty,
+        eq_token,
+        expr,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ImplItemFn {
+        attrs,
+        vis,
+        defaultness,
+        sig,
+        block,
+    }
+}
+
+process_struct! {
+    syn::ImplItemMacro {
+        attrs,
+        mac,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ImplItemType {
+        attrs,
+        vis,
+        defaultness,
+        type_token,
+        ident,
+        generics,
+        eq_token,
+        ty,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemConst {
+        attrs,
+        vis,
+        const_token,
+        ident,
+        generics,
+        colon_token,
+        ty,
+        eq_token,
+        expr,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemEnum {
+        attrs,
+        vis,
+        enum_token,
+        ident,
+        generics,
+        brace_token,
+        variants,
+    }
+}
+
+process_struct! {
+    syn::ItemExternCrate {
+        attrs,
+        vis,
+        extern_token,
+        crate_token,
+        ident,
+        rename,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemFn {
+        attrs,
+        vis,
+        sig,
+        block,
+    }
+}
+
+process_struct! {
+    syn::ItemForeignMod {
+        attrs,
+        unsafety,
+        abi,
+        brace_token,
+        items,
+    }
+}
+
+process_struct! {
+    syn::ItemImpl {
+        attrs,
+        defaultness,
+        unsafety,
+        impl_token,
+        generics,
+        trait_,
+        self_ty,
+        brace_token,
+        items,
+    }
+}
+
+process_struct! {
+    syn::ItemMacro {
+        attrs,
+        ident,
+        mac,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemMod {
+        attrs,
+        vis,
+        unsafety,
+        mod_token,
+        ident,
+        content,
+        semi,
+    }
+}
+
+process_struct! {
+    syn::ItemStatic {
+        attrs,
+        vis,
+        static_token,
+        mutability,
+        ident,
+        colon_token,
+        ty,
+        eq_token,
+        expr,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemStruct {
+        attrs,
+        vis,
+        struct_token,
+        ident,
+        generics,
+        fields,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemTrait {
+        attrs,
+        vis,
+        unsafety,
+        auto_token,
+        restriction,
+        trait_token,
+        ident,
+        generics,
+        colon_token,
+        supertraits,
+        brace_token,
+        items,
+    }
+}
+
+process_struct! {
+    syn::ItemTraitAlias {
+        attrs,
+        vis,
+        trait_token,
+        ident,
+        generics,
+        eq_token,
+        bounds,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemType {
+        attrs,
+        vis,
+        type_token,
+        ident,
+        generics,
+        eq_token,
+        ty,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::ItemUnion {
+        attrs,
+        vis,
+        union_token,
+        ident,
+        generics,
+        fields,
+    }
+}
+
+process_struct! {
+    syn::ItemUse {
+        attrs,
+        vis,
+        use_token,
+        leading_colon,
+        tree,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::Label {
+        name,
+        colon_token,
+    }
+}
+
+process_struct! {
+    syn::LifetimeParam {
+        attrs,
+        lifetime,
+        colon_token,
+        bounds,
+    }
+}
+
+process_struct! {
+    syn::Local {
+        attrs,
+        let_token,
+        pat,
+        init,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::LocalInit {
+        eq_token,
+        expr,
+        diverge,
+    }
+}
+
+process_struct! {
+    syn::Macro {
+        path,
+        bang_token,
+        delimiter,
+        tokens,
+    }
+}
+
+process_struct! {
+    syn::MetaList {
+        path,
+        delimiter,
+        tokens,
+    }
+}
+
+process_struct! {
+    syn::MetaNameValue {
+        path,
+        eq_token,
+        value,
+    }
+}
+
+process_struct! {
+    syn::ParenthesizedGenericArguments {
+        paren_token,
+        inputs,
+        output,
+    }
+}
+
+process_struct! {
+    syn::PatIdent {
+        attrs,
+        by_ref,
+        mutability,
+        ident,
+        subpat,
+    }
+}
+
+process_struct! {
+    syn::PatOr {
+        attrs,
+        leading_vert,
+        cases,
+    }
+}
+
+process_struct! {
+    syn::PatParen {
+        attrs,
+        paren_token,
+        pat,
+    }
+}
+
+process_struct! {
+    syn::PatReference {
+        attrs,
+        and_token,
+        mutability,
+        pat,
+    }
+}
+
+process_struct! {
+    syn::PatRest {
+        attrs,
+        dot2_token,
+    }
+}
+
+process_struct! {
+    syn::PatSlice {
+        attrs,
+        bracket_token,
+        elems,
+    }
+}
+
+process_struct! {
+    syn::PatStruct {
+        attrs,
+        #[qself]
+        qself,
+        path,
+        brace_token,
+        fields,
+        rest,
+    }
+}
+
+process_struct! {
+    syn::PatTuple {
+        attrs,
+        paren_token,
+        elems,
+    }
+}
+
+process_struct! {
+    syn::PatTupleStruct {
+        attrs,
+        #[qself]
+        qself,
+        path,
+        paren_token,
+        elems,
+    }
+}
+
+process_struct! {
+    syn::PatType {
+        attrs,
+        pat,
+        colon_token,
+        ty,
+    }
+}
+
+process_struct! {
+    syn::PatWild {
+        attrs,
+        underscore_token,
+    }
+}
+
+process_struct! {
+    syn::Path {
+        leading_colon,
+        segments,
+    }
+}
+
+process_struct! {
+    syn::PathSegment {
+        ident,
+        arguments,
+    }
+}
+
+process_struct! {
+    syn::PreciseCapture {
+        use_token,
+        lt_token,
+        params,
+        gt_token,
+    }
+}
+
+process_struct! {
+    syn::PredicateLifetime {
+        lifetime,
+        colon_token,
+        bounds,
+    }
+}
+
+process_struct! {
+    syn::PredicateType {
+        lifetimes,
+        bounded_ty,
+        colon_token,
+        bounds,
+    }
+}
+
+process_struct! {
+    syn::Receiver {
+        attrs,
+        reference,
+        mutability,
+        self_token,
+        colon_token,
+        ty,
+    }
+}
+
+process_struct! {
+    syn::Signature {
+        constness,
+        asyncness,
+        unsafety,
+        abi,
+        fn_token,
+        ident,
+        generics,
+        paren_token,
+        inputs,
+        variadic,
+        output,
+    }
+}
+
+process_struct! {
+    syn::StmtMacro {
+        attrs,
+        mac,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::TraitBound {
+        paren_token,
+        modifier,
+        lifetimes,
+        path,
+    }
+}
+
+process_struct! {
+    syn::TraitItemConst {
+        attrs,
+        const_token,
+        ident,
+        generics,
+        colon_token,
+        ty,
+        default,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::TraitItemFn {
+        attrs,
+        sig,
+        default,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::TraitItemMacro {
+        attrs,
+        mac,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::TraitItemType {
+        attrs,
+        type_token,
+        ident,
+        generics,
+        colon_token,
+        bounds,
+        default,
+        semi_token,
+    }
+}
+
+process_struct! {
+    syn::TypeArray {
+        bracket_token,
+        elem,
+        semi_token,
+        len,
+    }
+}
+
+process_struct! {
+    syn::TypeBareFn {
+        lifetimes,
+        unsafety,
+        abi,
+        fn_token,
+        paren_token,
+        inputs,
+        variadic,
+        output,
+    }
+}
+
+process_struct! {
+    syn::TypeGroup {
+        group_token,
+        elem,
+    }
+}
+
+process_struct! {
+    syn::TypeImplTrait {
+        impl_token,
+        bounds,
+    }
+}
+
+process_struct! {
+    syn::TypeInfer {
+        underscore_token,
+    }
+}
+
+process_struct! {
+    syn::TypeMacro {
+        mac,
+    }
+}
+
+process_struct! {
+    syn::TypeNever {
+        bang_token,
+    }
+}
+
+process_struct! {
+    syn::TypeParam {
+        attrs,
+        ident,
+        colon_token,
+        bounds,
+        eq_token,
+        default,
+    }
+}
+
+process_struct! {
+    syn::TypeParen {
+        paren_token,
+        elem,
+    }
+}
+
+process_struct! {
+    syn::TypePath {
+        #[qself]
+        qself,
+        path,
+    }
+}
+
+process_struct! {
+    syn::TypePtr {
+        star_token,
+        const_token,
+        mutability,
+        elem,
+    }
+}
+
+process_struct! {
+    syn::TypeReference {
+        and_token,
+        lifetime,
+        mutability,
+        elem,
+    }
+}
+
+process_struct! {
+    syn::TypeSlice {
+        bracket_token,
+        elem,
+    }
+}
+
+process_struct! {
+    syn::TypeTraitObject {
+        dyn_token,
+        bounds,
+    }
+}
+
+process_struct! {
+    syn::TypeTuple {
+        paren_token,
+        elems,
+    }
+}
+
+process_struct! {
+    syn::UseGlob {
+        star_token,
+    }
+}
+
+process_struct! {
+    syn::UseGroup {
+        brace_token,
+        items,
+    }
+}
+
+process_struct! {
+    syn::UseName {
+        ident,
+    }
+}
+
+process_struct! {
+    syn::UsePath {
+        ident,
+        colon2_token,
+        tree,
+    }
+}
+
+process_struct! {
+    syn::UseRename {
+        ident,
+        as_token,
+        rename,
+    }
+}
+
+process_struct! {
+    syn::Variadic {
+        attrs,
+        pat,
+        dots,
+        comma,
+    }
+}
+
+process_struct! {
+    syn::Variant {
+        attrs,
+        ident,
+        fields,
+        discriminant,
+    }
+}
+
+process_struct! {
+    syn::VisRestricted {
+        pub_token,
+        paren_token,
+        in_token,
+        path,
+    }
+}
+
+process_struct! {
+    syn::WhereClause {
+        where_token,
+        predicates,
+    }
+}
+
+macro_rules! process_enum {
+    ($path:path {
+        $($variant:ident$(($($field:ident),* $(,)?))?,)*
+    }) => {
+        impl<P: Phase> Process<P> for $path {
+            fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+                match self {
+                    $(Self::$variant$(($($field),*))? => Some(($($($field.process(state)?,)*)?).call(|($($($field,)*)?)| Self::$variant$(($($field),*))?)),)*
+                }
+            }
+        }
+    };
+    ($path:path {
+        $($variant:ident$(($($field:ident),* $(,)?))?,)*
+        #[no_op]
+        _,
+    }) => {
+        impl<P: Phase> Process<P> for $path {
+            fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+                #![allow(unused_variables)]
+                match self {
+                    $(Self::$variant$(($($field),*))? => Some(($($($field.process(state)?,)*)?).call(|($($($field,)*)?)| Self::$variant$(($($field),*))?)),)*
+                    _ => Some(Output::new(self)),
+                }
+            }
+        }
+    };
+}
+
+process_enum! {
+    syn::AttrStyle {
+        Outer,
+        Inner(f0),
+    }
+}
+
+process_enum! {
+    syn::BinOp {
+        Add(f0),
+        Sub(f0),
+        Mul(f0),
+        Div(f0),
+        Rem(f0),
+        And(f0),
+        Or(f0),
+        BitXor(f0),
+        BitAnd(f0),
+        BitOr(f0),
+        Shl(f0),
+        Shr(f0),
+        Eq(f0),
+        Lt(f0),
+        Le(f0),
+        Ne(f0),
+        Ge(f0),
+        Gt(f0),
+        AddAssign(f0),
+        SubAssign(f0),
+        MulAssign(f0),
+        DivAssign(f0),
+        RemAssign(f0),
+        BitXorAssign(f0),
+        BitAndAssign(f0),
+        BitOrAssign(f0),
+        ShlAssign(f0),
+        ShrAssign(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::CapturedParam {
+        Lifetime(f0),
+        Ident(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::Data {
+        Struct(f0),
+        Enum(f0),
+        Union(f0),
+    }
+}
+
+process_enum! {
+    syn::Expr {
+        Array(f0),
+        Assign(f0),
+        Async(f0),
+        Await(f0),
+        Binary(f0),
+        Block(f0),
+        Break(f0),
+        Call(f0),
+        Cast(f0),
+        Closure(f0),
+        Const(f0),
+        Continue(f0),
+        Field(f0),
+        ForLoop(f0),
+        Group(f0),
+        If(f0),
+        Index(f0),
+        Infer(f0),
+        Let(f0),
+        Lit(f0),
+        Loop(f0),
+        Macro(f0),
+        Match(f0),
+        MethodCall(f0),
+        Paren(f0),
+        Path(f0),
+        Range(f0),
+        RawAddr(f0),
+        Reference(f0),
+        Repeat(f0),
+        Return(f0),
+        Struct(f0),
+        Try(f0),
+        TryBlock(f0),
+        Tuple(f0),
+        Unary(f0),
+        Unsafe(f0),
+        Verbatim(f0),
+        While(f0),
+        Yield(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::FieldMutability {
+        None,
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::Fields {
+        Named(f0),
+        Unnamed(f0),
+        Unit,
+    }
+}
+
+process_enum! {
+    syn::FnArg {
+        Receiver(f0),
+        Typed(f0),
+    }
+}
+
+process_enum! {
+    syn::ForeignItem {
+        Fn(f0),
+        Static(f0),
+        Type(f0),
+        Macro(f0),
+        Verbatim(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::GenericArgument {
+        Lifetime(f0),
+        Type(f0),
+        Const(f0),
+        AssocType(f0),
+        AssocConst(f0),
+        Constraint(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::GenericParam {
+        Lifetime(f0),
+        Type(f0),
+        Const(f0),
+    }
+}
+
+process_enum! {
+    syn::ImplItem {
+        Const(f0),
+        Fn(f0),
+        Type(f0),
+        Macro(f0),
+        Verbatim(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::ImplRestriction {
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::Lit {
+        Str(f0),
+        ByteStr(f0),
+        CStr(f0),
+        Byte(f0),
+        Char(f0),
+        Int(f0),
+        Float(f0),
+        Bool(f0),
+        Verbatim(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::MacroDelimiter {
+        Paren(f0),
+        Brace(f0),
+        Bracket(f0),
+    }
+}
+
+process_enum! {
+    syn::Member {
+        Named(f0),
+        Unnamed(f0),
+    }
+}
+
+process_enum! {
+    syn::Meta {
+        Path(f0),
+        List(f0),
+        NameValue(f0),
+    }
+}
+
+process_enum! {
+    syn::Pat {
+        Const(f0),
+        Ident(f0),
+        Lit(f0),
+        Macro(f0),
+        Or(f0),
+        Paren(f0),
+        Path(f0),
+        Range(f0),
+        Reference(f0),
+        Rest(f0),
+        Slice(f0),
+        Struct(f0),
+        Tuple(f0),
+        TupleStruct(f0),
+        Type(f0),
+        Verbatim(f0),
+        Wild(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::PathArguments {
+        None,
+        AngleBracketed(f0),
+        Parenthesized(f0),
+    }
+}
+
+process_enum! {
+    syn::PointerMutability {
+        Const(f0),
+        Mut(f0),
+    }
+}
+
+process_enum! {
+    syn::RangeLimits {
+        HalfOpen(f0),
+        Closed(f0),
+    }
+}
+
+process_enum! {
+    syn::ReturnType {
+        Default,
+        Type(f0, f1),
+    }
+}
+
+process_enum! {
+    syn::StaticMutability {
+        Mut(f0),
+        None,
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::Stmt {
+        Local(f0),
+        Item(f0),
+        Expr(f0, f1),
+        Macro(f0),
+    }
+}
+
+process_enum! {
+    syn::TraitBoundModifier {
+        None,
+        Maybe(f0),
+    }
+}
+
+process_enum! {
+    syn::TraitItem {
+        Const(f0),
+        Fn(f0),
+        Type(f0),
+        Macro(f0),
+        Verbatim(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::Type {
+        Array(f0),
+        BareFn(f0),
+        Group(f0),
+        ImplTrait(f0),
+        Infer(f0),
+        Macro(f0),
+        Never(f0),
+        Paren(f0),
+        Path(f0),
+        Ptr(f0),
+        Reference(f0),
+        Slice(f0),
+        TraitObject(f0),
+        Tuple(f0),
+        Verbatim(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::TypeParamBound {
+        Trait(f0),
+        Lifetime(f0),
+        PreciseCapture(f0),
+        Verbatim(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::UnOp {
+        Deref(f0),
+        Not(f0),
+        Neg(f0),
+        #[no_op]
+        _,
+    }
+}
+
+process_enum! {
+    syn::UseTree {
+        Path(f0),
+        Name(f0),
+        Rename(f0),
+        Glob(f0),
+        Group(f0),
+    }
+}
+
+process_enum! {
+    syn::Visibility {
+        Public(f0),
+        Restricted(f0),
+        Inherited,
+    }
+}
+
+process_enum! {
+    syn::WherePredicate {
+        Lifetime(f0),
+        Type(f0),
+        #[no_op]
+        _,
+    }
+}
+
+struct TopItem(syn::Item);
+
+impl<P: Phase> Process<P> for TopItem {
+    fn process(self, state: &mut State<P>) -> Option<Output<Self, P>> {
+        match self.0 {
+            syn::Item::Const(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Enum(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::ExternCrate(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Fn(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::ForeignMod(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Impl(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Macro(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Mod(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Static(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Struct(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Trait(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::TraitAlias(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Type(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Union(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            syn::Item::Use(item) => Some(item.process(state)?.map(Into::into).map(TopItem)),
+            _ => Some(Output::new(self)),
+        }
+    }
+}
+
+pub(crate) fn process_cfgs(item: syn::Item, cfgs: Cfgs<bool>) -> syn::Result<Option<syn::Item>> {
+    let mut state = State::<ProcessCfgsPhase> {
+        cfgs,
+        errors: Errors::new(),
+        _phantom: PhantomData,
+    };
+    let retval = TopItem(item).process(&mut state).map(|v| v.0 .0);
+    state.errors.finish()?;
+    Ok(retval)
+}
+
+pub(crate) fn collect_cfgs(item: syn::Item) -> syn::Result<Cfgs<()>> {
+    let mut state = State::<CollectCfgsPhase> {
+        cfgs: Cfgs::default(),
+        errors: Errors::new(),
+        _phantom: PhantomData,
+    };
+    let (None | Some(Output(()))) = TopItem(item).process(&mut state);
+    state.errors.finish()?;
+    Ok(state.cfgs)
+}
diff --git a/crates/fayalite/src/lib.rs b/crates/fayalite/src/lib.rs
index fba7ada..5b5afb4 100644
--- a/crates/fayalite/src/lib.rs
+++ b/crates/fayalite/src/lib.rs
@@ -11,6 +11,56 @@ extern crate self as fayalite;
 #[doc(hidden)]
 pub use std as __std;
 
+#[doc(hidden)]
+#[macro_export]
+macro_rules! __cfg_expansion_helper {
+    (
+        [
+            $($evaluated_cfgs:ident($($evaluated_exprs:tt)*) = $evaluated_results:ident,)*
+        ]
+        [
+            $cfg:ident($($expr:tt)*),
+            $($unevaluated_cfgs:ident($($unevaluated_exprs:tt)*),)*
+        ]
+        #[$after_evaluation:path:($($after_evaluation_attr_args:tt)*)] {$($after_evaluation_args:tt)*}
+    ) => {
+        #[$cfg($($expr)*)]
+        $crate::__cfg_expansion_helper! {
+            [
+                $($evaluated_cfgs($($evaluated_exprs)*) = $evaluated_results,)*
+                $cfg($($expr)*) = true,
+            ]
+            [
+                $($unevaluated_cfgs($($unevaluated_exprs)*),)*
+            ]
+            #[$after_evaluation:($($after_evaluation_attr_args)*)] {$($after_evaluation_args)*}
+        }
+        #[$cfg(not($($expr)*))]
+        $crate::__cfg_expansion_helper! {
+            [
+                $($evaluated_cfgs($($evaluated_exprs)*) = $evaluated_results,)*
+                $cfg($($expr)*) = false,
+            ]
+            [
+                $($unevaluated_cfgs($($unevaluated_exprs)*),)*
+            ]
+            #[$after_evaluation:($($after_evaluation_attr_args)*)] {$($after_evaluation_args)*}
+        }
+    };
+    (
+        [
+            $($evaluated_cfgs:ident($($evaluated_exprs:tt)*) = $evaluated_results:ident,)*
+        ]
+        []
+        #[$after_evaluation:path:($($after_evaluation_attr_args:tt)*)] {$($after_evaluation_args:tt)*}
+    ) => {
+        #[$after_evaluation([
+            $($evaluated_cfgs($($evaluated_exprs)*) = $evaluated_results,)*
+        ] $($after_evaluation_attr_args)*)]
+        $($after_evaluation_args)*
+    };
+}
+
 #[doc(inline)]
 /// The `#[hdl_module]` attribute is applied to a Rust function so that that function creates
 /// a [`Module`][`::fayalite::module::Module`] when called.

From b63676d0caff9387d4401f938c4489df85e7b185 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 27 Dec 2024 04:01:53 -0800
Subject: [PATCH 143/190] add test for cfgs

---
 crates/fayalite/build.rs        |  3 ++
 crates/fayalite/tests/module.rs | 57 +++++++++++++++++++++++++++++++++
 2 files changed, 60 insertions(+)

diff --git a/crates/fayalite/build.rs b/crates/fayalite/build.rs
index 24d8f31..c6680d5 100644
--- a/crates/fayalite/build.rs
+++ b/crates/fayalite/build.rs
@@ -5,6 +5,9 @@ use std::{env, fs, path::Path};
 
 fn main() {
     println!("cargo::rustc-check-cfg=cfg(todo)");
+    println!("cargo::rustc-check-cfg=cfg(cfg_false_for_tests)");
+    println!("cargo::rustc-check-cfg=cfg(cfg_true_for_tests)");
+    println!("cargo::rustc-cfg=cfg_true_for_tests");
     let path = "visit_types.json";
     println!("cargo::rerun-if-changed={path}");
     println!("cargo::rerun-if-changed=build.rs");
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 4cb3057..42cc528 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -4287,3 +4287,60 @@ circuit check_deduce_resets:
 ",
     };
 }
+
+#[hdl_module(outline_generated)]
+pub fn check_cfgs<#[cfg(cfg_false_for_tests)] A: Type, #[cfg(cfg_true_for_tests)] B: Type>(
+    #[cfg(cfg_false_for_tests)] a: A,
+    #[cfg(cfg_true_for_tests)] b: B,
+) {
+    #[hdl]
+    struct S<#[cfg(cfg_false_for_tests)] A, #[cfg(cfg_true_for_tests)] B> {
+        #[cfg(cfg_false_for_tests)]
+        a: A,
+        #[cfg(cfg_true_for_tests)]
+        b: B,
+    }
+    #[hdl]
+    #[cfg(cfg_false_for_tests)]
+    let i_a: A = m.input(a);
+    #[hdl]
+    #[cfg(cfg_true_for_tests)]
+    let i_b: B = m.input(b);
+    #[hdl]
+    let w: S<UInt<8>> = wire();
+    #[cfg(cfg_false_for_tests)]
+    {
+        #[hdl]
+        let o_a: A = m.output(a);
+        connect(o_a, w.a.cast_bits_to(a));
+        connect_any(w.a, i_a.cast_to_bits());
+    }
+    #[cfg(cfg_true_for_tests)]
+    {
+        #[hdl]
+        let o_b: B = m.output(b);
+        connect(o_b, w.b.cast_bits_to(b));
+        connect_any(w.b, i_b.cast_to_bits());
+    }
+}
+
+#[test]
+fn test_cfgs() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_cfgs(UInt[8]);
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_cfgs.fir": r"FIRRTL version 3.2.0
+circuit check_cfgs:
+    type Ty0 = {b: UInt<8>}
+    module check_cfgs: @[module-XXXXXXXXXX.rs 1:1]
+        input i_b: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
+        output o_b: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
+        wire w: Ty0 @[module-XXXXXXXXXX.rs 3:1]
+        connect o_b, w.b @[module-XXXXXXXXXX.rs 5:1]
+        connect w.b, i_b @[module-XXXXXXXXXX.rs 6:1]
+",
+    };
+}

From c16726cee63cd5afbf720dad14fcba7f738cf6b6 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 29 Dec 2024 00:48:15 -0800
Subject: [PATCH 144/190] fix #[hdl]/#[hdl_module] attributes getting the wrong
 hygiene when processing #[cfg]s

---
 crates/fayalite-proc-macros-impl/src/lib.rs | 27 +++++++++++++++------
 crates/fayalite/src/lib.rs                  | 17 +++++++------
 crates/fayalite/tests/module.rs             | 15 ++++++------
 3 files changed, 37 insertions(+), 22 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/lib.rs b/crates/fayalite-proc-macros-impl/src/lib.rs
index 1b1b61f..6ba177b 100644
--- a/crates/fayalite-proc-macros-impl/src/lib.rs
+++ b/crates/fayalite-proc-macros-impl/src/lib.rs
@@ -1210,17 +1210,29 @@ fn hdl_main(
     attr: TokenStream,
     item: TokenStream,
 ) -> syn::Result<TokenStream> {
-    let (evaluated_cfgs, attr): (_, TokenStream) = Parser::parse2(
+    fn parse_evaluated_cfgs_attr<R>(
+        input: ParseStream,
+        parse_inner: impl FnOnce(ParseStream) -> syn::Result<R>,
+    ) -> syn::Result<R> {
+        let _: Token![#] = input.parse()?;
+        let bracket_content;
+        bracketed!(bracket_content in input);
+        let _: kw::__evaluated_cfgs = bracket_content.parse()?;
+        let paren_content;
+        parenthesized!(paren_content in bracket_content);
+        parse_inner(&paren_content)
+    }
+    let (evaluated_cfgs, item): (_, TokenStream) = Parser::parse2(
         |input: ParseStream| {
-            if input.peek(Bracket) && input.peek2(kw::__evaluated_cfgs) {
-                let cfgs = input.parse()?;
-                let _: kw::__evaluated_cfgs = input.parse()?;
-                Ok((Some(cfgs), input.parse()?))
+            let peek = input.fork();
+            if parse_evaluated_cfgs_attr(&peek, |_| Ok(())).is_ok() {
+                let evaluated_cfgs = parse_evaluated_cfgs_attr(input, Cfgs::<bool>::parse)?;
+                Ok((Some(evaluated_cfgs), input.parse()?))
             } else {
                 Ok((None, input.parse()?))
             }
         },
-        attr,
+        item,
     )?;
     let cfgs = if let Some(cfgs) = evaluated_cfgs {
         cfgs
@@ -1229,12 +1241,11 @@ fn hdl_main(
         if cfgs.cfgs_list.is_empty() {
             Cfgs::default()
         } else {
-            let key = kw::__evaluated_cfgs::default();
             return Ok(quote! {
                 ::fayalite::__cfg_expansion_helper! {
                     []
                     #cfgs
-                    #[::fayalite::#kw:(#key #attr)] { #item }
+                    {#[::fayalite::#kw(#attr)]} { #item }
                 }
             });
         }
diff --git a/crates/fayalite/src/lib.rs b/crates/fayalite/src/lib.rs
index 5b5afb4..88fe169 100644
--- a/crates/fayalite/src/lib.rs
+++ b/crates/fayalite/src/lib.rs
@@ -22,7 +22,8 @@ macro_rules! __cfg_expansion_helper {
             $cfg:ident($($expr:tt)*),
             $($unevaluated_cfgs:ident($($unevaluated_exprs:tt)*),)*
         ]
-        #[$after_evaluation:path:($($after_evaluation_attr_args:tt)*)] {$($after_evaluation_args:tt)*}
+        // pass as tt so we get right span for attribute
+        $after_evaluation_attr:tt $after_evaluation_body:tt
     ) => {
         #[$cfg($($expr)*)]
         $crate::__cfg_expansion_helper! {
@@ -33,7 +34,7 @@ macro_rules! __cfg_expansion_helper {
             [
                 $($unevaluated_cfgs($($unevaluated_exprs)*),)*
             ]
-            #[$after_evaluation:($($after_evaluation_attr_args)*)] {$($after_evaluation_args)*}
+            $after_evaluation_attr $after_evaluation_body
         }
         #[$cfg(not($($expr)*))]
         $crate::__cfg_expansion_helper! {
@@ -44,7 +45,7 @@ macro_rules! __cfg_expansion_helper {
             [
                 $($unevaluated_cfgs($($unevaluated_exprs)*),)*
             ]
-            #[$after_evaluation:($($after_evaluation_attr_args)*)] {$($after_evaluation_args)*}
+            $after_evaluation_attr $after_evaluation_body
         }
     };
     (
@@ -52,12 +53,14 @@ macro_rules! __cfg_expansion_helper {
             $($evaluated_cfgs:ident($($evaluated_exprs:tt)*) = $evaluated_results:ident,)*
         ]
         []
-        #[$after_evaluation:path:($($after_evaluation_attr_args:tt)*)] {$($after_evaluation_args:tt)*}
+        // don't use #[...] so we get right span for `#` and `[]` of attribute
+        {$($after_evaluation_attr:tt)*} {$($after_evaluation_body:tt)*}
     ) => {
-        #[$after_evaluation([
+        $($after_evaluation_attr)*
+        #[__evaluated_cfgs([
             $($evaluated_cfgs($($evaluated_exprs)*) = $evaluated_results,)*
-        ] $($after_evaluation_attr_args)*)]
-        $($after_evaluation_args)*
+        ])]
+        $($after_evaluation_body)*
     };
 }
 
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 42cc528..4e56df4 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -4288,7 +4288,8 @@ circuit check_deduce_resets:
     };
 }
 
-#[hdl_module(outline_generated)]
+// intentionally not outline_generated to ensure we get correct macro hygiene
+#[hdl_module]
 pub fn check_cfgs<#[cfg(cfg_false_for_tests)] A: Type, #[cfg(cfg_true_for_tests)] B: Type>(
     #[cfg(cfg_false_for_tests)] a: A,
     #[cfg(cfg_true_for_tests)] b: B,
@@ -4335,12 +4336,12 @@ fn test_cfgs() {
         "/test/check_cfgs.fir": r"FIRRTL version 3.2.0
 circuit check_cfgs:
     type Ty0 = {b: UInt<8>}
-    module check_cfgs: @[module-XXXXXXXXXX.rs 1:1]
-        input i_b: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
-        output o_b: UInt<8> @[module-XXXXXXXXXX.rs 4:1]
-        wire w: Ty0 @[module-XXXXXXXXXX.rs 3:1]
-        connect o_b, w.b @[module-XXXXXXXXXX.rs 5:1]
-        connect w.b, i_b @[module-XXXXXXXXXX.rs 6:1]
+    module check_cfgs: @[the_test_file.rs 9962:1]
+        input i_b: UInt<8> @[the_test_file.rs 9979:20]
+        output o_b: UInt<8> @[the_test_file.rs 9992:24]
+        wire w: Ty0 @[the_test_file.rs 9981:25]
+        connect o_b, w.b @[the_test_file.rs 9993:9]
+        connect w.b, i_b @[the_test_file.rs 9994:9]
 ",
     };
 }

From 31d01046a81fdb3b14b53efb767ce95aeb891868 Mon Sep 17 00:00:00 2001
From: Cesar Strauss <cestrauss@gmail.com>
Date: Sun, 29 Dec 2024 13:04:01 -0300
Subject: [PATCH 145/190] Initial queue formal proof based on one-entry FIFO
 equivalence

For now, only check that the basic properties work in bounded model check
mode, leave the induction proof for later.

Partially replace the previously existing proof.

Remove earlier assumptions and bounds that don't apply for this proof.

Use parameterized types instead of hard-coded types.
---
 crates/fayalite/src/util/ready_valid.rs | 190 ++++++++++++++----------
 1 file changed, 112 insertions(+), 78 deletions(-)

diff --git a/crates/fayalite/src/util/ready_valid.rs b/crates/fayalite/src/util/ready_valid.rs
index 82d3f1e..9a81b1b 100644
--- a/crates/fayalite/src/util/ready_valid.rs
+++ b/crates/fayalite/src/util/ready_valid.rs
@@ -195,7 +195,7 @@ mod tests {
         assert_formal(
             format_args!("test_queue_{capacity}_{inp_ready_is_comb}_{out_valid_is_comb}"),
             queue_test(capacity, inp_ready_is_comb, out_valid_is_comb),
-            FormalMode::Prove,
+            FormalMode::BMC,
             14,
             None,
             ExportOptions {
@@ -203,6 +203,16 @@ mod tests {
                 ..ExportOptions::default()
             },
         );
+        /// Formal verification of the FIFO queue
+        ///
+        /// The strategy derives from the observation that, if we filter its
+        /// input and output streams to consider just one in every N reads and
+        /// writes (where N is the FIFO capacity), then the FIFO effectively
+        /// behaves as a one-entry FIFO.
+        ///
+        /// In particular, any counterexample of the full FIFO behaving badly
+        /// will also be caught by one of the filtered versions (one which
+        /// happens to be in phase with the offending input or output).
         #[hdl_module]
         fn queue_test(capacity: NonZeroUsize, inp_ready_is_comb: bool, out_valid_is_comb: bool) {
             #[hdl]
@@ -217,6 +227,8 @@ mod tests {
                     rst: formal_reset().to_reset(),
                 },
             );
+
+            // random input data
             #[hdl]
             let inp_data: HdlOption<UInt<8>> = wire();
             #[hdl]
@@ -225,16 +237,25 @@ mod tests {
             } else {
                 connect(inp_data, HdlNone());
             }
+
+            // assert output ready at random
             #[hdl]
             let out_ready: Bool = wire();
             connect(out_ready, any_seq(Bool));
-            let index_ty: UInt<32> = UInt::TYPE;
+
+            // The current number of elements in the FIFO ranges from zero to
+            // maximum capacity, inclusive.
+            let count_ty = UInt::range_inclusive(0..=capacity.get());
+            // type for counters that wrap around at the FIFO capacity
+            let index_ty = UInt::range(0..capacity.get());
+
+            // among all entries of the FIFO internal circular memory, choose
+            // one at random to check
             #[hdl]
-            let index_to_check = wire();
+            let index_to_check = wire(index_ty);
             connect(index_to_check, any_const(index_ty));
-            let index_max = !index_ty.zero();
-            // we saturate at index_max, so only check indexes where we properly maintain position
-            hdl_assume(clk, index_to_check.cmp_ne(index_max), "");
+
+            // instantiate and connect the queue
             #[hdl]
             let dut = instance(queue(
                 UInt[ConstUsize::<8>],
@@ -245,108 +266,121 @@ mod tests {
             connect(dut.cd, cd);
             connect(dut.inp.data, inp_data);
             connect(dut.out.ready, out_ready);
-            hdl_assume(
-                clk,
-                index_to_check.cmp_ne(!Expr::ty(index_to_check).zero()),
-                "",
-            );
 
+            // Keep an independent count of words in the FIFO. Ensure that
+            // it's always correct, and never overflows.
             #[hdl]
-            let expected_count_reg = reg_builder().clock_domain(cd).reset(0u32);
-            #[hdl]
-            let next_expected_count = wire();
-            connect(next_expected_count, expected_count_reg);
-            connect(expected_count_reg, next_expected_count);
+            let expected_count_reg = reg_builder().clock_domain(cd).reset(count_ty.zero());
             #[hdl]
             if ReadyValid::firing(dut.inp) & !ReadyValid::firing(dut.out) {
-                connect_any(next_expected_count, expected_count_reg + 1u8);
+                hdl_assert(clk, expected_count_reg.cmp_ne(capacity.get()), "");
+                connect_any(expected_count_reg, expected_count_reg + 1u8);
             } else if !ReadyValid::firing(dut.inp) & ReadyValid::firing(dut.out) {
-                connect_any(next_expected_count, expected_count_reg - 1u8);
+                hdl_assert(clk, expected_count_reg.cmp_ne(count_ty.zero()), "");
+                connect_any(expected_count_reg, expected_count_reg - 1u8);
             }
-            hdl_assert(cd.clk, expected_count_reg.cmp_eq(dut.count), "");
-
-            #[hdl]
-            let prev_out_ready_reg = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
-            connect_any(
-                prev_out_ready_reg,
-                (prev_out_ready_reg << 1) | out_ready.cast_to(UInt[1]),
-            );
-            #[hdl]
-            let prev_inp_valid_reg = reg_builder().clock_domain(cd).reset(!0_hdl_u3);
-            connect_any(
-                prev_inp_valid_reg,
-                (prev_inp_valid_reg << 1) | HdlOption::is_some(inp_data).cast_to(UInt[1]),
-            );
-            hdl_assume(
-                clk,
-                (prev_out_ready_reg & prev_inp_valid_reg).cmp_ne(0u8),
-                "",
-            );
+            hdl_assert(clk, expected_count_reg.cmp_eq(dut.count), "");
 
+            // keep an independent write index into the FIFO's circular buffer
             #[hdl]
             let inp_index_reg = reg_builder().clock_domain(cd).reset(index_ty.zero());
             #[hdl]
-            let stored_inp_data_reg = reg_builder().clock_domain(cd).reset(0u8);
-
-            #[hdl]
-            if let HdlSome(data) = ReadyValid::firing_data(dut.inp) {
+            if ReadyValid::firing(dut.inp) {
                 #[hdl]
-                if inp_index_reg.cmp_lt(index_max) {
+                if inp_index_reg.cmp_ne(capacity.get() - 1) {
                     connect_any(inp_index_reg, inp_index_reg + 1u8);
-                    #[hdl]
-                    if inp_index_reg.cmp_eq(index_to_check) {
-                        connect(stored_inp_data_reg, data);
-                    }
+                } else {
+                    connect_any(inp_index_reg, 0_hdl_u0);
                 }
             }
 
-            #[hdl]
-            if inp_index_reg.cmp_lt(index_to_check) {
-                hdl_assert(clk, stored_inp_data_reg.cmp_eq(0u8), "");
-            }
-
+            // keep an independent read index into the FIFO's circular buffer
             #[hdl]
             let out_index_reg = reg_builder().clock_domain(cd).reset(index_ty.zero());
             #[hdl]
-            let stored_out_data_reg = reg_builder().clock_domain(cd).reset(0u8);
-
-            #[hdl]
-            if let HdlSome(data) = ReadyValid::firing_data(dut.out) {
+            if ReadyValid::firing(dut.out) {
                 #[hdl]
-                if out_index_reg.cmp_lt(index_max) {
+                if out_index_reg.cmp_ne(capacity.get() - 1) {
                     connect_any(out_index_reg, out_index_reg + 1u8);
-                    #[hdl]
-                    if out_index_reg.cmp_eq(index_to_check) {
-                        connect(stored_out_data_reg, data);
-                    }
+                } else {
+                    connect_any(out_index_reg, 0_hdl_u0);
                 }
             }
 
+            // filter the input data stream, predicated by the read index
+            // matching the chosen position in the FIFO's circular buffer
             #[hdl]
-            if out_index_reg.cmp_lt(index_to_check) {
-                hdl_assert(clk, stored_out_data_reg.cmp_eq(0u8), "");
+            let inp_index_matches = wire();
+            connect(inp_index_matches, inp_index_reg.cmp_eq(index_to_check));
+            #[hdl]
+            let inp_firing_data = wire();
+            connect(inp_firing_data, HdlNone());
+            #[hdl]
+            if inp_index_matches {
+                connect(inp_firing_data, ReadyValid::firing_data(dut.inp));
             }
 
-            hdl_assert(clk, inp_index_reg.cmp_ge(out_index_reg), "");
-
+            // filter the output data stream, predicated by the write index
+            // matching the chosen position in the FIFO's circular buffer
             #[hdl]
-            if inp_index_reg.cmp_lt(index_max) & out_index_reg.cmp_lt(index_max) {
-                hdl_assert(
-                    clk,
-                    expected_count_reg.cmp_eq(inp_index_reg - out_index_reg),
-                    "",
-                );
-            } else {
-                hdl_assert(
-                    clk,
-                    expected_count_reg.cmp_ge(inp_index_reg - out_index_reg),
-                    "",
-                );
+            let out_index_matches = wire();
+            connect(out_index_matches, out_index_reg.cmp_eq(index_to_check));
+            #[hdl]
+            let out_firing_data = wire();
+            connect(out_firing_data, HdlNone());
+            #[hdl]
+            if out_index_matches {
+                connect(out_firing_data, ReadyValid::firing_data(dut.out));
             }
 
+            // Implement a one-entry FIFO and ensure its equivalence to the
+            // filtered FIFO.
+            //
+            // the holding register for our one-entry FIFO
             #[hdl]
-            if inp_index_reg.cmp_gt(index_to_check) & out_index_reg.cmp_gt(index_to_check) {
-                hdl_assert(clk, stored_inp_data_reg.cmp_eq(stored_out_data_reg), "");
+            let stored_reg = reg_builder().clock_domain(cd).reset(HdlNone());
+            #[hdl]
+            match stored_reg {
+                // If the holding register is empty...
+                HdlNone => {
+                    #[hdl]
+                    match inp_firing_data {
+                        // ... and we are not receiving data, then we must not
+                        // transmit any data.
+                        HdlNone => hdl_assert(clk, HdlOption::is_none(out_firing_data), ""),
+                        // If we are indeed receiving some data...
+                        HdlSome(data_in) => {
+                            #[hdl]
+                            match out_firing_data {
+                                // ... and transmitting at the same time, we
+                                // must be transmitting the input data itself,
+                                // since the holding register is empty.
+                                HdlSome(data_out) => hdl_assert(clk, data_out.cmp_eq(data_in), ""),
+                                // If we are receiving, but not transmitting,
+                                // store the received data in the holding
+                                // register.
+                                HdlNone => connect(stored_reg, HdlSome(data_in)),
+                            }
+                        }
+                    }
+                }
+                // If there is some value stored in the holding register...
+                HdlSome(stored) => {
+                    #[hdl]
+                    match out_firing_data {
+                        // ... and we are not transmitting it, we cannot
+                        // receive any more data.
+                        HdlNone => hdl_assert(clk, HdlOption::is_none(inp_firing_data), ""),
+                        // If we are transmitting a previously stored value...
+                        HdlSome(data_out) => {
+                            // ... it must be the same data we stored earlier.
+                            hdl_assert(clk, data_out.cmp_eq(stored), "");
+                            // Also, accept new data, if any. Otherwise,
+                            // let the holding register become empty.
+                            connect(stored_reg, inp_firing_data);
+                        }
+                    }
+                }
             }
         }
     }

From dcf865caec1010082b2568de575ea0bdf7adf748 Mon Sep 17 00:00:00 2001
From: Cesar Strauss <cestrauss@gmail.com>
Date: Sun, 29 Dec 2024 13:12:58 -0300
Subject: [PATCH 146/190] Add assertions and debug ports in order for the FIFO
 to pass induction

As some proofs involving memories, it is necessary to add more ports to
the queue interface, to sync state. These changes are predicated on the
test environment, so normal use is not affected.

Since some speedup is achieved, use the saved time to test with a deeper
FIFO.
---
 crates/fayalite/src/util/ready_valid.rs | 99 ++++++++++++++++++++++++-
 1 file changed, 97 insertions(+), 2 deletions(-)

diff --git a/crates/fayalite/src/util/ready_valid.rs b/crates/fayalite/src/util/ready_valid.rs
index 9a81b1b..28ea691 100644
--- a/crates/fayalite/src/util/ready_valid.rs
+++ b/crates/fayalite/src/util/ready_valid.rs
@@ -178,6 +178,30 @@ pub fn queue<T: Type>(
             }
         }
     }
+    // These debug ports expose some internal state during the Induction phase
+    // of Formal Verification. They are not present in normal use.
+    //
+    // TODO: gather the new debug ports in a bundle
+    #[cfg(test)]
+    {
+        // read the memory word currently stored at some fixed index
+        let debug_port = mem.new_read_port();
+        #[hdl]
+        let dbg_index_to_check: UInt = m.input(index_ty);
+        #[hdl]
+        let dbg_stored: T = m.output(ty);
+        connect(debug_port.addr, dbg_index_to_check);
+        connect(debug_port.en, true);
+        connect(debug_port.clk, cd.clk);
+        connect(dbg_stored, debug_port.data);
+        // also expose the current read and write indices
+        #[hdl]
+        let dbg_inp_index: UInt = m.output(index_ty);
+        #[hdl]
+        let dbg_out_index: UInt = m.output(index_ty);
+        connect(dbg_inp_index, inp_index_reg);
+        connect(dbg_out_index, out_index_reg);
+    }
 }
 
 #[cfg(test)]
@@ -195,8 +219,8 @@ mod tests {
         assert_formal(
             format_args!("test_queue_{capacity}_{inp_ready_is_comb}_{out_valid_is_comb}"),
             queue_test(capacity, inp_ready_is_comb, out_valid_is_comb),
-            FormalMode::BMC,
-            14,
+            FormalMode::Prove,
+            2,
             None,
             ExportOptions {
                 simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts),
@@ -254,6 +278,7 @@ mod tests {
             #[hdl]
             let index_to_check = wire(index_ty);
             connect(index_to_check, any_const(index_ty));
+            hdl_assume(clk, index_to_check.cmp_lt(capacity.get()), "");
 
             // instantiate and connect the queue
             #[hdl]
@@ -382,6 +407,56 @@ mod tests {
                     }
                 }
             }
+
+            // from now on, some extra assertions in order to pass induction
+
+            // sync the holding register, when it's occupied, to the
+            // corresponding entry in the FIFO's circular buffer
+            connect(dut.dbg_index_to_check, index_to_check);
+            #[hdl]
+            if let HdlSome(stored) = stored_reg {
+                hdl_assert(clk, stored.cmp_eq(dut.dbg_stored), "");
+            }
+
+            // sync the read and write indices
+            hdl_assert(clk, inp_index_reg.cmp_eq(dut.dbg_inp_index), "");
+            hdl_assert(clk, out_index_reg.cmp_eq(dut.dbg_out_index), "");
+
+            // the indices should never go past the capacity, but induction
+            // doesn't know that...
+            hdl_assert(clk, inp_index_reg.cmp_lt(capacity.get()), "");
+            hdl_assert(clk, out_index_reg.cmp_lt(capacity.get()), "");
+
+            // strongly constrain the state of the holding register
+            //
+            // The holding register is full if and only if the corresponding
+            // FIFO entry was written to and not yet read. In other words, if
+            // the number of pending reads until the chosen entry is read out
+            // is greater than the current FIFO count, then the entry couldn't
+            // be in the FIFO in the first place.
+            #[hdl]
+            let pending_reads: UInt = wire(index_ty);
+            // take care of wrap-around when subtracting indices, add the
+            // capacity amount to keep the result positive if necessary
+            #[hdl]
+            if index_to_check.cmp_ge(out_index_reg) {
+                connect(pending_reads, index_to_check - out_index_reg);
+            } else {
+                connect(
+                    pending_reads,
+                    index_to_check + capacity.get() - out_index_reg,
+                );
+            }
+            // check whether the chosen entry is in the FIFO
+            #[hdl]
+            let expected_stored: Bool = wire();
+            connect(expected_stored, pending_reads.cmp_lt(dut.count));
+            // sync with the state of the holding register
+            hdl_assert(
+                clk,
+                expected_stored.cmp_eq(HdlOption::is_some(stored_reg)),
+                "",
+            );
         }
     }
 
@@ -464,4 +539,24 @@ mod tests {
     fn test_4_true_true() {
         test_queue(NonZero::new(4).unwrap(), true, true);
     }
+
+    #[test]
+    fn test_many_false_false() {
+        test_queue(NonZero::new((2 << 16) - 5).unwrap(), false, false);
+    }
+
+    #[test]
+    fn test_many_false_true() {
+        test_queue(NonZero::new((2 << 16) - 5).unwrap(), false, true);
+    }
+
+    #[test]
+    fn test_many_true_false() {
+        test_queue(NonZero::new((2 << 16) - 5).unwrap(), true, false);
+    }
+
+    #[test]
+    fn test_many_true_true() {
+        test_queue(NonZero::new((2 << 16) - 5).unwrap(), true, true);
+    }
 }

From 3771cea78e34fd28af6ef4a76c1013eb2406de1d Mon Sep 17 00:00:00 2001
From: Cesar Strauss <cestrauss@gmail.com>
Date: Sun, 29 Dec 2024 13:17:24 -0300
Subject: [PATCH 147/190] Gather the FIFO debug ports in a bundle

---
 crates/fayalite/src/util/ready_valid.rs | 40 ++++++++++++++-----------
 1 file changed, 22 insertions(+), 18 deletions(-)

diff --git a/crates/fayalite/src/util/ready_valid.rs b/crates/fayalite/src/util/ready_valid.rs
index 28ea691..ac08a64 100644
--- a/crates/fayalite/src/util/ready_valid.rs
+++ b/crates/fayalite/src/util/ready_valid.rs
@@ -49,6 +49,18 @@ impl<T: Type> ReadyValid<T> {
     }
 }
 
+/// This debug port is only meant to assist the formal proof of the queue.
+#[cfg(test)]
+#[doc(hidden)]
+#[hdl]
+pub struct QueueDebugPort<Element, Index> {
+    #[hdl(flip)]
+    index_to_check: Index,
+    stored: Element,
+    inp_index: Index,
+    out_index: Index,
+}
+
 #[hdl_module]
 pub fn queue<T: Type>(
     ty: T,
@@ -180,27 +192,19 @@ pub fn queue<T: Type>(
     }
     // These debug ports expose some internal state during the Induction phase
     // of Formal Verification. They are not present in normal use.
-    //
-    // TODO: gather the new debug ports in a bundle
     #[cfg(test)]
     {
+        #[hdl]
+        let dbg: QueueDebugPort<T, UInt> = m.output(QueueDebugPort[ty][index_ty]);
         // read the memory word currently stored at some fixed index
         let debug_port = mem.new_read_port();
-        #[hdl]
-        let dbg_index_to_check: UInt = m.input(index_ty);
-        #[hdl]
-        let dbg_stored: T = m.output(ty);
-        connect(debug_port.addr, dbg_index_to_check);
+        connect(debug_port.addr, dbg.index_to_check);
         connect(debug_port.en, true);
         connect(debug_port.clk, cd.clk);
-        connect(dbg_stored, debug_port.data);
+        connect(dbg.stored, debug_port.data);
         // also expose the current read and write indices
-        #[hdl]
-        let dbg_inp_index: UInt = m.output(index_ty);
-        #[hdl]
-        let dbg_out_index: UInt = m.output(index_ty);
-        connect(dbg_inp_index, inp_index_reg);
-        connect(dbg_out_index, out_index_reg);
+        connect(dbg.inp_index, inp_index_reg);
+        connect(dbg.out_index, out_index_reg);
     }
 }
 
@@ -412,15 +416,15 @@ mod tests {
 
             // sync the holding register, when it's occupied, to the
             // corresponding entry in the FIFO's circular buffer
-            connect(dut.dbg_index_to_check, index_to_check);
+            connect(dut.dbg.index_to_check, index_to_check);
             #[hdl]
             if let HdlSome(stored) = stored_reg {
-                hdl_assert(clk, stored.cmp_eq(dut.dbg_stored), "");
+                hdl_assert(clk, stored.cmp_eq(dut.dbg.stored), "");
             }
 
             // sync the read and write indices
-            hdl_assert(clk, inp_index_reg.cmp_eq(dut.dbg_inp_index), "");
-            hdl_assert(clk, out_index_reg.cmp_eq(dut.dbg_out_index), "");
+            hdl_assert(clk, inp_index_reg.cmp_eq(dut.dbg.inp_index), "");
+            hdl_assert(clk, out_index_reg.cmp_eq(dut.dbg.out_index), "");
 
             // the indices should never go past the capacity, but induction
             // doesn't know that...

From e3a2ccd41c89eb659dde86d3d7f0581a17d45509 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 9 Jan 2025 22:52:22 -0800
Subject: [PATCH 148/190] properly handle duplicate names in vcd

---
 crates/fayalite/src/sim/vcd.rs                | 376 +++++++++++++-----
 crates/fayalite/tests/sim.rs                  |  30 ++
 .../tests/sim/expected/duplicate_names.txt    | 153 +++++++
 .../tests/sim/expected/duplicate_names.vcd    |  11 +
 .../fayalite/tests/sim/expected/memories.vcd  |  32 +-
 .../fayalite/tests/sim/expected/memories2.vcd |  10 +-
 .../fayalite/tests/sim/expected/memories3.vcd |  16 +-
 7 files changed, 499 insertions(+), 129 deletions(-)
 create mode 100644 crates/fayalite/tests/sim/expected/duplicate_names.txt
 create mode 100644 crates/fayalite/tests/sim/expected/duplicate_names.vcd

diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs
index b8248e3..fde30be 100644
--- a/crates/fayalite/src/sim/vcd.rs
+++ b/crates/fayalite/src/sim/vcd.rs
@@ -5,6 +5,7 @@ use crate::{
     enum_::{Enum, EnumType},
     expr::Flow,
     int::UInt,
+    intern::{Intern, Interned},
     sim::{
         time::{SimDuration, SimInstant},
         TraceArray, TraceAsyncReset, TraceBool, TraceBundle, TraceClock, TraceDecl,
@@ -15,12 +16,73 @@ use crate::{
     },
 };
 use bitvec::{order::Lsb0, slice::BitSlice};
+use hashbrown::{hash_map::Entry, HashMap};
 use std::{
-    fmt,
-    io::{self, Write},
-    mem,
+    fmt::{self, Write as _},
+    io, mem,
 };
 
+#[derive(Default)]
+struct Scope {
+    last_inserted: HashMap<Interned<str>, usize>,
+}
+
+#[derive(Copy, Clone)]
+struct VerilogIdentifier {
+    unescaped_name: Interned<str>,
+}
+
+impl VerilogIdentifier {
+    fn needs_escape(self) -> bool {
+        // we only allow ascii, so we can just check bytes
+        let Some((&first, rest)) = self.unescaped_name.as_bytes().split_first() else {
+            unreachable!("Scope::new_identifier guarantees a non-empty name");
+        };
+        if !first.is_ascii_alphabetic() && first != b'_' {
+            true
+        } else {
+            rest.iter()
+                .any(|&ch| !ch.is_ascii_alphanumeric() && ch != b'_' && ch != b'$')
+        }
+    }
+}
+
+impl fmt::Display for VerilogIdentifier {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        if self.needs_escape() {
+            f.write_str("\\")?;
+        }
+        write!(f, "{}", Escaped(self.unescaped_name))
+    }
+}
+
+impl Scope {
+    fn new_identifier(&mut self, unescaped_name: Interned<str>) -> VerilogIdentifier {
+        let next_disambiguator = match self.last_inserted.entry(unescaped_name) {
+            Entry::Vacant(entry) => {
+                entry.insert(1);
+                return VerilogIdentifier { unescaped_name };
+            }
+            Entry::Occupied(entry) => entry.get() + 1,
+        };
+        let mut disambiguated_name = String::from(&*unescaped_name);
+        for disambiguator in next_disambiguator.. {
+            disambiguated_name.truncate(unescaped_name.len());
+            write!(disambiguated_name, "_{disambiguator}").expect("can't fail");
+            if let Entry::Vacant(entry) = self.last_inserted.entry((*disambiguated_name).intern()) {
+                let retval = VerilogIdentifier {
+                    unescaped_name: *entry.key(),
+                };
+                entry.insert(1);
+                // speed up future searches
+                self.last_inserted.insert(unescaped_name, disambiguator);
+                return retval;
+            }
+        }
+        panic!("too many names");
+    }
+}
+
 pub struct VcdWriterDecls<W: io::Write + 'static> {
     writer: W,
     timescale: SimDuration,
@@ -97,14 +159,20 @@ impl<W: io::Write> fmt::Debug for VcdWriterDecls<W> {
     }
 }
 
+/// pass in scope to ensure it's not available in child scope
 fn write_vcd_scope<W: io::Write, R>(
     writer: &mut W,
     scope_type: &str,
-    scope_name: &str,
-    f: impl FnOnce(&mut W) -> io::Result<R>,
+    scope_name: Interned<str>,
+    scope: &mut Scope,
+    f: impl FnOnce(&mut W, &mut Scope) -> io::Result<R>,
 ) -> io::Result<R> {
-    writeln!(writer, "$scope {scope_type} {scope_name} $end")?;
-    let retval = f(writer)?;
+    writeln!(
+        writer,
+        "$scope {scope_type} {} $end",
+        scope.new_identifier(scope_name),
+    )?;
+    let retval = f(writer, &mut Scope::default())?;
     writeln!(writer, "$upscope $end")?;
     Ok(retval)
 }
@@ -143,24 +211,28 @@ trait_arg! {
 
 struct ArgModule<'a> {
     properties: &'a mut VcdWriterProperties,
+    scope: &'a mut Scope,
 }
 
 impl<'a> ArgModule<'a> {
     fn reborrow(&mut self) -> ArgModule<'_> {
         ArgModule {
             properties: self.properties,
+            scope: self.scope,
         }
     }
 }
 
 struct ArgModuleBody<'a> {
     properties: &'a mut VcdWriterProperties,
+    scope: &'a mut Scope,
 }
 
 impl<'a> ArgModuleBody<'a> {
     fn reborrow(&mut self) -> ArgModuleBody<'_> {
         ArgModuleBody {
             properties: self.properties,
+            scope: self.scope,
         }
     }
 }
@@ -170,6 +242,7 @@ struct ArgInType<'a> {
     sink_var_type: &'static str,
     duplex_var_type: &'static str,
     properties: &'a mut VcdWriterProperties,
+    scope: &'a mut Scope,
 }
 
 impl<'a> ArgInType<'a> {
@@ -179,6 +252,7 @@ impl<'a> ArgInType<'a> {
             sink_var_type: self.sink_var_type,
             duplex_var_type: self.duplex_var_type,
             properties: self.properties,
+            scope: self.scope,
         }
     }
 }
@@ -226,55 +300,42 @@ fn write_vcd_id<W: io::Write>(writer: &mut W, mut id: usize) -> io::Result<()> {
     Ok(())
 }
 
-fn write_escaped<W: io::Write>(writer: &mut W, value: impl fmt::Display) -> io::Result<()> {
-    // escaping rules from function GTKWave uses to decode VCD strings:
-    // https://github.com/gtkwave/gtkwave/blob/491f24d7e8619cfc1fcc65704ee5c967d1083c18/lib/libfst/fstapi.c#L7090
-    struct Wrapper<W>(W);
-    impl<W: io::Write> io::Write for Wrapper<W> {
-        fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
-            if buf.is_empty() {
-                return self.0.write(buf);
-            }
-            let mut retval = 0;
-            for &byte in buf {
-                match byte {
-                    b'\\' | b'\'' | b'"' | b'?' => self.0.write_all(&[b'\\', byte])?,
-                    b'\n' => self.0.write_all(br"\n")?,
-                    b'\r' => self.0.write_all(br"\r")?,
-                    b'\t' => self.0.write_all(br"\t")?,
-                    0x7 => self.0.write_all(br"\a")?,
-                    0x8 => self.0.write_all(br"\b")?,
-                    0xC => self.0.write_all(br"\f")?,
-                    0xB => self.0.write_all(br"\v")?,
-                    _ => {
-                        if byte.is_ascii_graphic() {
-                            self.0.write_all(&[byte])?;
-                        } else {
-                            write!(self.0, r"\x{byte:02x}")?;
+struct Escaped<T: fmt::Display>(T);
+
+impl<T: fmt::Display> fmt::Display for Escaped<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        // escaping rules from function GTKWave uses to decode VCD strings:
+        // https://github.com/gtkwave/gtkwave/blob/491f24d7e8619cfc1fcc65704ee5c967d1083c18/lib/libfst/fstapi.c#L7090
+        struct Wrapper<W>(W);
+        impl<W: fmt::Write> fmt::Write for Wrapper<W> {
+            fn write_str(&mut self, s: &str) -> fmt::Result {
+                for byte in s.bytes() {
+                    match byte {
+                        b'\\' | b'\'' | b'"' | b'?' => {
+                            self.0.write_str("\\")?;
+                            self.0.write_char(byte as char)?;
+                        }
+                        b'\n' => self.0.write_str(r"\n")?,
+                        b'\r' => self.0.write_str(r"\r")?,
+                        b'\t' => self.0.write_str(r"\t")?,
+                        0x7 => self.0.write_str(r"\a")?,
+                        0x8 => self.0.write_str(r"\b")?,
+                        0xC => self.0.write_str(r"\f")?,
+                        0xB => self.0.write_str(r"\v")?,
+                        _ => {
+                            if byte.is_ascii_graphic() {
+                                self.0.write_char(byte as char)?;
+                            } else {
+                                write!(self.0, r"\x{byte:02x}")?;
+                            }
                         }
                     }
                 }
-                retval += 1;
+                Ok(())
             }
-            Ok(retval)
-        }
-
-        fn flush(&mut self) -> io::Result<()> {
-            self.0.flush()
         }
+        write!(Wrapper(f), "{}", self.0)
     }
-    write!(Wrapper(writer), "{value}")
-}
-
-fn is_unescaped_verilog_identifier(ident: &str) -> bool {
-    // we only allow ascii, so we can just check bytes
-    let Some((&first, rest)) = ident.as_bytes().split_first() else {
-        return false; // empty string is not an identifier
-    };
-    (first.is_ascii_alphabetic() || first == b'_')
-        && rest
-            .iter()
-            .all(|&ch| ch.is_ascii_alphanumeric() || ch == b'_' || ch == b'$')
 }
 
 fn write_vcd_var<W: io::Write>(
@@ -284,7 +345,7 @@ fn write_vcd_var<W: io::Write>(
     var_type: &str,
     size: usize,
     location: TraceLocation,
-    name: &str,
+    name: VerilogIdentifier,
 ) -> io::Result<()> {
     let id = match location {
         TraceLocation::Scalar(id) => id.as_usize(),
@@ -319,12 +380,7 @@ fn write_vcd_var<W: io::Write>(
     };
     write!(writer, "$var {var_type} {size} ")?;
     write_vcd_id(writer, id)?;
-    writer.write_all(b" ")?;
-    if !is_unescaped_verilog_identifier(name) {
-        writer.write_all(b"\\")?;
-    }
-    write_escaped(writer, name)?;
-    writer.write_all(b" $end\n")
+    writeln!(writer, " {name} $end")
 }
 
 impl WriteTrace for TraceUInt {
@@ -334,6 +390,7 @@ impl WriteTrace for TraceUInt {
             sink_var_type,
             duplex_var_type,
             properties,
+            scope,
         } = arg.in_type();
         let Self {
             location,
@@ -356,7 +413,7 @@ impl WriteTrace for TraceUInt {
             var_type,
             ty.width(),
             location,
-            &name,
+            scope.new_identifier(name),
         )
     }
 }
@@ -421,6 +478,7 @@ impl WriteTrace for TraceEnumDiscriminant {
             sink_var_type: _,
             duplex_var_type: _,
             properties,
+            scope,
         } = arg.in_type();
         let Self {
             location,
@@ -435,7 +493,7 @@ impl WriteTrace for TraceEnumDiscriminant {
             "string",
             1,
             location,
-            &name,
+            scope.new_identifier(name),
         )
     }
 }
@@ -507,11 +565,11 @@ impl WriteTrace for TraceScope {
 
 impl WriteTrace for TraceModule {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModule { properties } = arg.module();
+        let ArgModule { properties, scope } = arg.module();
         let Self { name, children } = self;
-        write_vcd_scope(writer, "module", &name, |writer| {
+        write_vcd_scope(writer, "module", name, scope, |writer, scope| {
             for child in children {
-                child.write_trace(writer, ArgModuleBody { properties })?;
+                child.write_trace(writer, ArgModuleBody { properties, scope })?;
             }
             Ok(())
         })
@@ -520,7 +578,7 @@ impl WriteTrace for TraceModule {
 
 impl WriteTrace for TraceInstance {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
+        let ArgModuleBody { properties, scope } = arg.module_body();
         let Self {
             name: _,
             instance_io,
@@ -534,15 +592,16 @@ impl WriteTrace for TraceInstance {
                 sink_var_type: "wire",
                 duplex_var_type: "wire",
                 properties,
+                scope,
             },
         )?;
-        module.write_trace(writer, ArgModule { properties })
+        module.write_trace(writer, ArgModule { properties, scope })
     }
 }
 
 impl WriteTrace for TraceMem {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
+        let ArgModuleBody { properties, scope } = arg.module_body();
         let Self {
             id,
             name,
@@ -551,27 +610,41 @@ impl WriteTrace for TraceMem {
             ports,
             array_type,
         } = self;
-        write_vcd_scope(writer, "struct", &*name, |writer| {
-            write_vcd_scope(writer, "struct", "contents", |writer| {
-                for element_index in 0..array_type.len() {
-                    write_vcd_scope(writer, "struct", &format!("[{element_index}]"), |writer| {
-                        properties.memory_properties[id.as_usize()].element_index = element_index;
-                        properties.memory_properties[id.as_usize()].element_part_index = 0;
-                        element_type.write_trace(
+        write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
+            write_vcd_scope(
+                writer,
+                "struct",
+                "contents".intern(),
+                scope,
+                |writer, scope| {
+                    for element_index in 0..array_type.len() {
+                        write_vcd_scope(
                             writer,
-                            ArgInType {
-                                source_var_type: "reg",
-                                sink_var_type: "reg",
-                                duplex_var_type: "reg",
-                                properties,
+                            "struct",
+                            Intern::intern_owned(format!("[{element_index}]")),
+                            scope,
+                            |writer, scope| {
+                                properties.memory_properties[id.as_usize()].element_index =
+                                    element_index;
+                                properties.memory_properties[id.as_usize()].element_part_index = 0;
+                                element_type.write_trace(
+                                    writer,
+                                    ArgInType {
+                                        source_var_type: "reg",
+                                        sink_var_type: "reg",
+                                        duplex_var_type: "reg",
+                                        properties,
+                                        scope,
+                                    },
+                                )
                             },
-                        )
-                    })?;
-                }
-                Ok(())
-            })?;
+                        )?;
+                    }
+                    Ok(())
+                },
+            )?;
             for port in ports {
-                port.write_trace(writer, ArgModuleBody { properties })?;
+                port.write_trace(writer, ArgModuleBody { properties, scope })?;
             }
             Ok(())
         })
@@ -580,7 +653,7 @@ impl WriteTrace for TraceMem {
 
 impl WriteTrace for TraceMemPort {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
+        let ArgModuleBody { properties, scope } = arg.module_body();
         let Self {
             name: _,
             bundle,
@@ -593,6 +666,7 @@ impl WriteTrace for TraceMemPort {
                 sink_var_type: "wire",
                 duplex_var_type: "wire",
                 properties,
+                scope,
             },
         )
     }
@@ -600,7 +674,7 @@ impl WriteTrace for TraceMemPort {
 
 impl WriteTrace for TraceWire {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
+        let ArgModuleBody { properties, scope } = arg.module_body();
         let Self {
             name: _,
             child,
@@ -613,6 +687,7 @@ impl WriteTrace for TraceWire {
                 sink_var_type: "wire",
                 duplex_var_type: "wire",
                 properties,
+                scope,
             },
         )
     }
@@ -620,7 +695,7 @@ impl WriteTrace for TraceWire {
 
 impl WriteTrace for TraceReg {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
+        let ArgModuleBody { properties, scope } = arg.module_body();
         let Self {
             name: _,
             child,
@@ -633,6 +708,7 @@ impl WriteTrace for TraceReg {
                 sink_var_type: "reg",
                 duplex_var_type: "reg",
                 properties,
+                scope,
             },
         )
     }
@@ -640,7 +716,7 @@ impl WriteTrace for TraceReg {
 
 impl WriteTrace for TraceModuleIO {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
+        let ArgModuleBody { properties, scope } = arg.module_body();
         let Self {
             name: _,
             child,
@@ -654,6 +730,7 @@ impl WriteTrace for TraceModuleIO {
                 sink_var_type: "wire",
                 duplex_var_type: "wire",
                 properties,
+                scope,
             },
         )
     }
@@ -661,16 +738,31 @@ impl WriteTrace for TraceModuleIO {
 
 impl WriteTrace for TraceBundle {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let mut arg = arg.in_type();
+        let ArgInType {
+            source_var_type,
+            sink_var_type,
+            duplex_var_type,
+            properties,
+            scope,
+        } = arg.in_type();
         let Self {
             name,
             fields,
             ty: _,
             flow: _,
         } = self;
-        write_vcd_scope(writer, "struct", &name, |writer| {
+        write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
             for field in fields {
-                field.write_trace(writer, arg.reborrow())?;
+                field.write_trace(
+                    writer,
+                    ArgInType {
+                        source_var_type,
+                        sink_var_type,
+                        duplex_var_type,
+                        properties,
+                        scope,
+                    },
+                )?;
             }
             Ok(())
         })
@@ -679,16 +771,31 @@ impl WriteTrace for TraceBundle {
 
 impl WriteTrace for TraceArray {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let mut arg = arg.in_type();
+        let ArgInType {
+            source_var_type,
+            sink_var_type,
+            duplex_var_type,
+            properties,
+            scope,
+        } = arg.in_type();
         let Self {
             name,
             elements,
             ty: _,
             flow: _,
         } = self;
-        write_vcd_scope(writer, "struct", &name, |writer| {
+        write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
             for element in elements {
-                element.write_trace(writer, arg.reborrow())?;
+                element.write_trace(
+                    writer,
+                    ArgInType {
+                        source_var_type,
+                        sink_var_type,
+                        duplex_var_type,
+                        properties,
+                        scope,
+                    },
+                )?;
             }
             Ok(())
         })
@@ -697,7 +804,13 @@ impl WriteTrace for TraceArray {
 
 impl WriteTrace for TraceEnumWithFields {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let mut arg = arg.in_type();
+        let ArgInType {
+            source_var_type,
+            sink_var_type,
+            duplex_var_type,
+            properties,
+            scope,
+        } = arg.in_type();
         let Self {
             name,
             discriminant,
@@ -705,10 +818,28 @@ impl WriteTrace for TraceEnumWithFields {
             ty: _,
             flow: _,
         } = self;
-        write_vcd_scope(writer, "struct", &name, |writer| {
-            discriminant.write_trace(writer, arg.reborrow())?;
+        write_vcd_scope(writer, "struct", name, scope, |writer, scope| {
+            discriminant.write_trace(
+                writer,
+                ArgInType {
+                    source_var_type,
+                    sink_var_type,
+                    duplex_var_type,
+                    properties,
+                    scope,
+                },
+            )?;
             for field in non_empty_fields {
-                field.write_trace(writer, arg.reborrow())?;
+                field.write_trace(
+                    writer,
+                    ArgInType {
+                        source_var_type,
+                        sink_var_type,
+                        duplex_var_type,
+                        properties,
+                        scope,
+                    },
+                )?;
             }
             Ok(())
         })
@@ -744,6 +875,7 @@ impl<W: io::Write> TraceWriterDecls for VcdWriterDecls<W> {
             &mut writer,
             ArgModule {
                 properties: &mut properties,
+                scope: &mut Scope::default(),
             },
         )?;
         writeln!(writer, "$enddefinitions $end")?;
@@ -798,9 +930,7 @@ fn write_string_value_change(
     value: impl fmt::Display,
     id: usize,
 ) -> io::Result<()> {
-    writer.write_all(b"s")?;
-    write_escaped(writer, value)?;
-    writer.write_all(b" ")?;
+    write!(writer, "s{} ", Escaped(value))?;
     write_vcd_id(writer, id)?;
     writer.write_all(b"\n")
 }
@@ -946,3 +1076,49 @@ impl<W: io::Write> fmt::Debug for VcdWriter<W> {
             .finish_non_exhaustive()
     }
 }
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_scope() {
+        let mut scope = Scope::default();
+        assert_eq!(&*scope.new_identifier("foo".intern()).unescaped_name, "foo");
+        assert_eq!(
+            &*scope.new_identifier("foo_0".intern()).unescaped_name,
+            "foo_0"
+        );
+        assert_eq!(
+            &*scope.new_identifier("foo_1".intern()).unescaped_name,
+            "foo_1"
+        );
+        assert_eq!(
+            &*scope.new_identifier("foo_3".intern()).unescaped_name,
+            "foo_3"
+        );
+        assert_eq!(
+            &*scope.new_identifier("foo".intern()).unescaped_name,
+            "foo_2"
+        );
+        assert_eq!(
+            &*scope.new_identifier("foo".intern()).unescaped_name,
+            "foo_4"
+        );
+        assert_eq!(
+            &*scope.new_identifier("foo_0".intern()).unescaped_name,
+            "foo_0_2"
+        );
+        assert_eq!(
+            &*scope.new_identifier("foo_1".intern()).unescaped_name,
+            "foo_1_2"
+        );
+        for i in 5..1000u64 {
+            // verify it actually picks the next available identifier with no skips or duplicates
+            assert_eq!(
+                *scope.new_identifier("foo".intern()).unescaped_name,
+                format!("foo_{i}"),
+            );
+        }
+    }
+}
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index a249235..13e84eb 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -1246,3 +1246,33 @@ fn test_memories3() {
         panic!();
     }
 }
+
+#[hdl_module(outline_generated)]
+pub fn duplicate_names() {
+    #[hdl]
+    let w = wire();
+    connect(w, 5u8);
+    #[hdl]
+    let w = wire();
+    connect(w, 6u8);
+}
+
+#[test]
+fn test_duplicate_names() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(duplicate_names());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/duplicate_names.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/duplicate_names.txt") {
+        panic!();
+    }
+}
diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.txt b/crates/fayalite/tests/sim/expected/duplicate_names.txt
new file mode 100644
index 0000000..8a59861
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/duplicate_names.txt
@@ -0,0 +1,153 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 4,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(duplicate_names: duplicate_names).duplicate_names::w",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(duplicate_names: duplicate_names).duplicate_names::w",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: Const {
+                    dest: StatePartIndex<BigSlots>(3), // (0x6) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x6,
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                1: Copy {
+                    dest: StatePartIndex<BigSlots>(2), // (0x6) SlotDebugData { name: "InstantiatedModule(duplicate_names: duplicate_names).duplicate_names::w", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(3), // (0x6) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                2: Const {
+                    dest: StatePartIndex<BigSlots>(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> },
+                    value: 0x5,
+                },
+                // at: module-XXXXXXXXXX.rs:3:1
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(0), // (0x5) SlotDebugData { name: "InstantiatedModule(duplicate_names: duplicate_names).duplicate_names::w", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                4: Return,
+            ],
+            ..
+        },
+        pc: 4,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                5,
+                5,
+                6,
+                6,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::duplicate_names,
+        instantiated: Module {
+            name: duplicate_names,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {},
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "duplicate_names",
+        children: [
+            TraceWire {
+                name: "w",
+                child: TraceUInt {
+                    location: TraceScalarId(0),
+                    name: "w",
+                    ty: UInt<8>,
+                    flow: Duplex,
+                },
+                ty: UInt<8>,
+            },
+            TraceWire {
+                name: "w",
+                child: TraceUInt {
+                    location: TraceScalarId(1),
+                    name: "w",
+                    ty: UInt<8>,
+                    flow: Duplex,
+                },
+                ty: UInt<8>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<8>,
+            },
+            state: 0x05,
+            last_state: 0x05,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(2),
+                ty: UInt<8>,
+            },
+            state: 0x06,
+            last_state: 0x06,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 1 μs,
+    clocks_triggered: [],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.vcd b/crates/fayalite/tests/sim/expected/duplicate_names.vcd
new file mode 100644
index 0000000..1e9f6c6
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/duplicate_names.vcd
@@ -0,0 +1,11 @@
+$timescale 1 ps $end
+$scope module duplicate_names $end
+$var wire 8 ! w $end
+$var wire 8 " w_2 $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+b101 !
+b110 "
+$end
+#1000000
diff --git a/crates/fayalite/tests/sim/expected/memories.vcd b/crates/fayalite/tests/sim/expected/memories.vcd
index 72af410..bedc354 100644
--- a/crates/fayalite/tests/sim/expected/memories.vcd
+++ b/crates/fayalite/tests/sim/expected/memories.vcd
@@ -24,97 +24,97 @@ $upscope $end
 $upscope $end
 $scope struct mem $end
 $scope struct contents $end
-$scope struct [0] $end
+$scope struct \[0] $end
 $scope struct mem $end
 $var reg 8 9 \0 $end
 $var reg 8 I \1 $end
 $upscope $end
 $upscope $end
-$scope struct [1] $end
+$scope struct \[1] $end
 $scope struct mem $end
 $var reg 8 : \0 $end
 $var reg 8 J \1 $end
 $upscope $end
 $upscope $end
-$scope struct [2] $end
+$scope struct \[2] $end
 $scope struct mem $end
 $var reg 8 ; \0 $end
 $var reg 8 K \1 $end
 $upscope $end
 $upscope $end
-$scope struct [3] $end
+$scope struct \[3] $end
 $scope struct mem $end
 $var reg 8 < \0 $end
 $var reg 8 L \1 $end
 $upscope $end
 $upscope $end
-$scope struct [4] $end
+$scope struct \[4] $end
 $scope struct mem $end
 $var reg 8 = \0 $end
 $var reg 8 M \1 $end
 $upscope $end
 $upscope $end
-$scope struct [5] $end
+$scope struct \[5] $end
 $scope struct mem $end
 $var reg 8 > \0 $end
 $var reg 8 N \1 $end
 $upscope $end
 $upscope $end
-$scope struct [6] $end
+$scope struct \[6] $end
 $scope struct mem $end
 $var reg 8 ? \0 $end
 $var reg 8 O \1 $end
 $upscope $end
 $upscope $end
-$scope struct [7] $end
+$scope struct \[7] $end
 $scope struct mem $end
 $var reg 8 @ \0 $end
 $var reg 8 P \1 $end
 $upscope $end
 $upscope $end
-$scope struct [8] $end
+$scope struct \[8] $end
 $scope struct mem $end
 $var reg 8 A \0 $end
 $var reg 8 Q \1 $end
 $upscope $end
 $upscope $end
-$scope struct [9] $end
+$scope struct \[9] $end
 $scope struct mem $end
 $var reg 8 B \0 $end
 $var reg 8 R \1 $end
 $upscope $end
 $upscope $end
-$scope struct [10] $end
+$scope struct \[10] $end
 $scope struct mem $end
 $var reg 8 C \0 $end
 $var reg 8 S \1 $end
 $upscope $end
 $upscope $end
-$scope struct [11] $end
+$scope struct \[11] $end
 $scope struct mem $end
 $var reg 8 D \0 $end
 $var reg 8 T \1 $end
 $upscope $end
 $upscope $end
-$scope struct [12] $end
+$scope struct \[12] $end
 $scope struct mem $end
 $var reg 8 E \0 $end
 $var reg 8 U \1 $end
 $upscope $end
 $upscope $end
-$scope struct [13] $end
+$scope struct \[13] $end
 $scope struct mem $end
 $var reg 8 F \0 $end
 $var reg 8 V \1 $end
 $upscope $end
 $upscope $end
-$scope struct [14] $end
+$scope struct \[14] $end
 $scope struct mem $end
 $var reg 8 G \0 $end
 $var reg 8 W \1 $end
 $upscope $end
 $upscope $end
-$scope struct [15] $end
+$scope struct \[15] $end
 $scope struct mem $end
 $var reg 8 H \0 $end
 $var reg 8 X \1 $end
diff --git a/crates/fayalite/tests/sim/expected/memories2.vcd b/crates/fayalite/tests/sim/expected/memories2.vcd
index bd48f24..4039754 100644
--- a/crates/fayalite/tests/sim/expected/memories2.vcd
+++ b/crates/fayalite/tests/sim/expected/memories2.vcd
@@ -11,31 +11,31 @@ $var wire 1 ' wmask $end
 $upscope $end
 $scope struct mem $end
 $scope struct contents $end
-$scope struct [0] $end
+$scope struct \[0] $end
 $scope struct mem $end
 $var string 1 1 \$tag $end
 $var reg 1 6 HdlSome $end
 $upscope $end
 $upscope $end
-$scope struct [1] $end
+$scope struct \[1] $end
 $scope struct mem $end
 $var string 1 2 \$tag $end
 $var reg 1 7 HdlSome $end
 $upscope $end
 $upscope $end
-$scope struct [2] $end
+$scope struct \[2] $end
 $scope struct mem $end
 $var string 1 3 \$tag $end
 $var reg 1 8 HdlSome $end
 $upscope $end
 $upscope $end
-$scope struct [3] $end
+$scope struct \[3] $end
 $scope struct mem $end
 $var string 1 4 \$tag $end
 $var reg 1 9 HdlSome $end
 $upscope $end
 $upscope $end
-$scope struct [4] $end
+$scope struct \[4] $end
 $scope struct mem $end
 $var string 1 5 \$tag $end
 $var reg 1 : HdlSome $end
diff --git a/crates/fayalite/tests/sim/expected/memories3.vcd b/crates/fayalite/tests/sim/expected/memories3.vcd
index 328fcaa..5768560 100644
--- a/crates/fayalite/tests/sim/expected/memories3.vcd
+++ b/crates/fayalite/tests/sim/expected/memories3.vcd
@@ -42,7 +42,7 @@ $upscope $end
 $upscope $end
 $scope struct mem $end
 $scope struct contents $end
-$scope struct [0] $end
+$scope struct \[0] $end
 $scope struct mem $end
 $var reg 8 ] \[0] $end
 $var reg 8 e \[1] $end
@@ -54,7 +54,7 @@ $var reg 8 /" \[6] $end
 $var reg 8 7" \[7] $end
 $upscope $end
 $upscope $end
-$scope struct [1] $end
+$scope struct \[1] $end
 $scope struct mem $end
 $var reg 8 ^ \[0] $end
 $var reg 8 f \[1] $end
@@ -66,7 +66,7 @@ $var reg 8 0" \[6] $end
 $var reg 8 8" \[7] $end
 $upscope $end
 $upscope $end
-$scope struct [2] $end
+$scope struct \[2] $end
 $scope struct mem $end
 $var reg 8 _ \[0] $end
 $var reg 8 g \[1] $end
@@ -78,7 +78,7 @@ $var reg 8 1" \[6] $end
 $var reg 8 9" \[7] $end
 $upscope $end
 $upscope $end
-$scope struct [3] $end
+$scope struct \[3] $end
 $scope struct mem $end
 $var reg 8 ` \[0] $end
 $var reg 8 h \[1] $end
@@ -90,7 +90,7 @@ $var reg 8 2" \[6] $end
 $var reg 8 :" \[7] $end
 $upscope $end
 $upscope $end
-$scope struct [4] $end
+$scope struct \[4] $end
 $scope struct mem $end
 $var reg 8 a \[0] $end
 $var reg 8 i \[1] $end
@@ -102,7 +102,7 @@ $var reg 8 3" \[6] $end
 $var reg 8 ;" \[7] $end
 $upscope $end
 $upscope $end
-$scope struct [5] $end
+$scope struct \[5] $end
 $scope struct mem $end
 $var reg 8 b \[0] $end
 $var reg 8 j \[1] $end
@@ -114,7 +114,7 @@ $var reg 8 4" \[6] $end
 $var reg 8 <" \[7] $end
 $upscope $end
 $upscope $end
-$scope struct [6] $end
+$scope struct \[6] $end
 $scope struct mem $end
 $var reg 8 c \[0] $end
 $var reg 8 k \[1] $end
@@ -126,7 +126,7 @@ $var reg 8 5" \[6] $end
 $var reg 8 =" \[7] $end
 $upscope $end
 $upscope $end
-$scope struct [7] $end
+$scope struct \[7] $end
 $scope struct mem $end
 $var reg 8 d \[0] $end
 $var reg 8 l \[1] $end

From 404a2ee043b851e00e7571b5779714812accc5f7 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 12 Jan 2025 21:36:54 -0800
Subject: [PATCH 149/190] tests/sim: add test_array_rw

---
 crates/fayalite/tests/sim.rs                  |  131 +
 .../fayalite/tests/sim/expected/array_rw.txt  | 2859 +++++++++++++++++
 .../fayalite/tests/sim/expected/array_rw.vcd  |  283 ++
 3 files changed, 3273 insertions(+)
 create mode 100644 crates/fayalite/tests/sim/expected/array_rw.txt
 create mode 100644 crates/fayalite/tests/sim/expected/array_rw.vcd

diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 13e84eb..cae08de 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -1276,3 +1276,134 @@ fn test_duplicate_names() {
         panic!();
     }
 }
+
+#[hdl_module(outline_generated)]
+pub fn array_rw() {
+    #[hdl]
+    let array_in: Array<UInt<8>, 16> = m.input();
+    #[hdl]
+    let array_out: Array<UInt<8>, 16> = m.output();
+    #[hdl]
+    let read_index: UInt<8> = m.input();
+    #[hdl]
+    let read_data: UInt<8> = m.output();
+    #[hdl]
+    let write_index: UInt<8> = m.input();
+    #[hdl]
+    let write_data: UInt<8> = m.input();
+    #[hdl]
+    let write_en: Bool = m.input();
+    #[hdl]
+    let array_wire = wire();
+    connect(array_wire, array_in);
+    connect(array_out, array_wire);
+    #[hdl]
+    if write_en {
+        connect(array_wire[write_index], write_data);
+    }
+    connect(read_data, array_wire[read_index]);
+}
+
+#[test]
+fn test_array_rw() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(array_rw());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    #[derive(Debug, PartialEq)]
+    struct State {
+        array_in: [u8; 16],
+        array_out: [u8; 16],
+        read_index: u8,
+        read_data: u8,
+        write_index: u8,
+        write_data: u8,
+        write_en: bool,
+    }
+    let mut states = Vec::new();
+    let array_in = [
+        0xFFu8, 0x7F, 0x3F, 0x1F, 0x0F, 0x07, 0x03, 0x01, //
+        0x00u8, 0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xFC, 0xFE,
+    ];
+    for i in 0..=16 {
+        states.push(State {
+            array_in,
+            array_out: array_in,
+            read_index: i,
+            read_data: array_in.get(i as usize).copied().unwrap_or(0),
+            write_index: 0,
+            write_data: 0,
+            write_en: false,
+        });
+    }
+    for i in 0..=16u8 {
+        let mut array_out = array_in;
+        let write_data = i.wrapping_mul(i);
+        if let Some(v) = array_out.get_mut(i as usize) {
+            *v = write_data;
+        }
+        states.push(State {
+            array_in,
+            array_out,
+            read_index: 0,
+            read_data: array_out[0],
+            write_index: i,
+            write_data,
+            write_en: true,
+        });
+    }
+    for (cycle, expected) in states.into_iter().enumerate() {
+        let State {
+            array_in,
+            array_out: _,
+            read_index,
+            read_data: _,
+            write_index,
+            write_data,
+            write_en,
+        } = expected;
+        sim.write(sim.io().array_in, array_in);
+        sim.write(sim.io().read_index, read_index);
+        sim.write(sim.io().write_index, write_index);
+        sim.write(sim.io().write_data, write_data);
+        sim.write(sim.io().write_en, write_en);
+        sim.advance_time(SimDuration::from_micros(1));
+        let array_out = std::array::from_fn(|index| {
+            sim.read_bool_or_int(sim.io().array_out[index])
+                .to_bigint()
+                .try_into()
+                .expect("known to be in range")
+        });
+        let read_data = sim
+            .read_bool_or_int(sim.io().read_data)
+            .to_bigint()
+            .try_into()
+            .expect("known to be in range");
+        let state = State {
+            array_in,
+            array_out,
+            read_index,
+            read_data,
+            write_index,
+            write_data,
+            write_en,
+        };
+        assert_eq!(
+            state,
+            expected,
+            "vcd:\n{}\ncycle: {cycle}",
+            String::from_utf8(writer.take()).unwrap(),
+        );
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/array_rw.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/array_rw.txt") {
+        panic!();
+    }
+}
diff --git a/crates/fayalite/tests/sim/expected/array_rw.txt b/crates/fayalite/tests/sim/expected/array_rw.txt
new file mode 100644
index 0000000..f016e72
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/array_rw.txt
@@ -0,0 +1,2859 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 54,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[8]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[9]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[10]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[11]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[12]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[13]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[14]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[15]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[8]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[9]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[10]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[11]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[12]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[13]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[14]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[15]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::read_index",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::read_data",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::write_index",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::write_data",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::write_en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[8]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[9]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[10]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[11]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[12]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[13]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[14]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[15]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: CastBigToArrayIndex {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::read_index", ty: UInt<8> },
+                },
+                1: CastBigToArrayIndex {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x10 16) SlotDebugData { name: "", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(34), // (0x10) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::write_index", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                2: Copy {
+                    dest: StatePartIndex<BigSlots>(37), // (0xff) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(0), // (0xff) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[0]", ty: UInt<8> },
+                },
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(38), // (0x7f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(1), // (0x7f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[1]", ty: UInt<8> },
+                },
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(39), // (0x3f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[2]", ty: UInt<8> },
+                },
+                5: Copy {
+                    dest: StatePartIndex<BigSlots>(40), // (0x1f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(3), // (0x1f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[3]", ty: UInt<8> },
+                },
+                6: Copy {
+                    dest: StatePartIndex<BigSlots>(41), // (0xf) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[4]", ty: UInt<8> },
+                },
+                7: Copy {
+                    dest: StatePartIndex<BigSlots>(42), // (0x7) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(5), // (0x7) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[5]", ty: UInt<8> },
+                },
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(43), // (0x3) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(6), // (0x3) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[6]", ty: UInt<8> },
+                },
+                9: Copy {
+                    dest: StatePartIndex<BigSlots>(44), // (0x1) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[7]", ty: UInt<8> },
+                },
+                10: Copy {
+                    dest: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[8]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[8]", ty: UInt<8> },
+                },
+                11: Copy {
+                    dest: StatePartIndex<BigSlots>(46), // (0x80) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[9]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(9), // (0x80) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[9]", ty: UInt<8> },
+                },
+                12: Copy {
+                    dest: StatePartIndex<BigSlots>(47), // (0xc0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[10]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(10), // (0xc0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[10]", ty: UInt<8> },
+                },
+                13: Copy {
+                    dest: StatePartIndex<BigSlots>(48), // (0xe0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[11]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(11), // (0xe0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[11]", ty: UInt<8> },
+                },
+                14: Copy {
+                    dest: StatePartIndex<BigSlots>(49), // (0xf0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[12]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(12), // (0xf0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[12]", ty: UInt<8> },
+                },
+                15: Copy {
+                    dest: StatePartIndex<BigSlots>(50), // (0xf8) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[13]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(13), // (0xf8) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[13]", ty: UInt<8> },
+                },
+                16: Copy {
+                    dest: StatePartIndex<BigSlots>(51), // (0xfc) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[14]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(14), // (0xfc) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[14]", ty: UInt<8> },
+                },
+                17: Copy {
+                    dest: StatePartIndex<BigSlots>(52), // (0xfe) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[15]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(15), // (0xfe) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[15]", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:12:1
+                18: BranchIfZero {
+                    target: 20,
+                    value: StatePartIndex<BigSlots>(36), // (0x1) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::write_en", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:13:1
+                19: WriteIndexed {
+                    dest: StatePartIndex<BigSlots>(37) /* (0xff) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[0]", ty: UInt<8> } */ [StatePartIndex<SmallSlots>(0) /* (0x10 16) SlotDebugData { name: "", ty: UInt<8> } */ , len=16, stride=1],,
+                    src: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::write_data", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                20: Copy {
+                    dest: StatePartIndex<BigSlots>(16), // (0xff) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[0]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(37), // (0xff) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[0]", ty: UInt<8> },
+                },
+                21: Copy {
+                    dest: StatePartIndex<BigSlots>(17), // (0x7f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[1]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(38), // (0x7f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[1]", ty: UInt<8> },
+                },
+                22: Copy {
+                    dest: StatePartIndex<BigSlots>(18), // (0x3f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[2]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(39), // (0x3f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[2]", ty: UInt<8> },
+                },
+                23: Copy {
+                    dest: StatePartIndex<BigSlots>(19), // (0x1f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[3]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(40), // (0x1f) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[3]", ty: UInt<8> },
+                },
+                24: Copy {
+                    dest: StatePartIndex<BigSlots>(20), // (0xf) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[4]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(41), // (0xf) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[4]", ty: UInt<8> },
+                },
+                25: Copy {
+                    dest: StatePartIndex<BigSlots>(21), // (0x7) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[5]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(42), // (0x7) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[5]", ty: UInt<8> },
+                },
+                26: Copy {
+                    dest: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[6]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(43), // (0x3) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[6]", ty: UInt<8> },
+                },
+                27: Copy {
+                    dest: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[7]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(44), // (0x1) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[7]", ty: UInt<8> },
+                },
+                28: Copy {
+                    dest: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[8]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[8]", ty: UInt<8> },
+                },
+                29: Copy {
+                    dest: StatePartIndex<BigSlots>(25), // (0x80) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[9]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(46), // (0x80) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[9]", ty: UInt<8> },
+                },
+                30: Copy {
+                    dest: StatePartIndex<BigSlots>(26), // (0xc0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[10]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(47), // (0xc0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[10]", ty: UInt<8> },
+                },
+                31: Copy {
+                    dest: StatePartIndex<BigSlots>(27), // (0xe0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[11]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(48), // (0xe0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[11]", ty: UInt<8> },
+                },
+                32: Copy {
+                    dest: StatePartIndex<BigSlots>(28), // (0xf0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[12]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(49), // (0xf0) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[12]", ty: UInt<8> },
+                },
+                33: Copy {
+                    dest: StatePartIndex<BigSlots>(29), // (0xf8) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[13]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(50), // (0xf8) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[13]", ty: UInt<8> },
+                },
+                34: Copy {
+                    dest: StatePartIndex<BigSlots>(30), // (0xfc) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[14]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(51), // (0xfc) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[14]", ty: UInt<8> },
+                },
+                35: Copy {
+                    dest: StatePartIndex<BigSlots>(31), // (0xfe) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[15]", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(52), // (0xfe) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[15]", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:14:1
+                36: ReadIndexed {
+                    dest: StatePartIndex<BigSlots>(53), // (0xff) SlotDebugData { name: "", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(37) /* (0xff) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::array_wire[0]", ty: UInt<8> } */ [StatePartIndex<SmallSlots>(1) /* (0x0 0) SlotDebugData { name: "", ty: UInt<8> } */ , len=16, stride=1],,
+                },
+                37: Copy {
+                    dest: StatePartIndex<BigSlots>(33), // (0xff) SlotDebugData { name: "InstantiatedModule(array_rw: array_rw).array_rw::read_data", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(53), // (0xff) SlotDebugData { name: "", ty: UInt<8> },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                38: Return,
+            ],
+            ..
+        },
+        pc: 38,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [
+                16,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                255,
+                127,
+                63,
+                31,
+                15,
+                7,
+                3,
+                1,
+                0,
+                128,
+                192,
+                224,
+                240,
+                248,
+                252,
+                254,
+                255,
+                127,
+                63,
+                31,
+                15,
+                7,
+                3,
+                1,
+                0,
+                128,
+                192,
+                224,
+                240,
+                248,
+                252,
+                254,
+                0,
+                255,
+                16,
+                0,
+                1,
+                255,
+                127,
+                63,
+                31,
+                15,
+                7,
+                3,
+                1,
+                0,
+                128,
+                192,
+                224,
+                240,
+                248,
+                252,
+                254,
+                255,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::array_rw,
+        instantiated: Module {
+            name: array_rw,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Array<UInt<8>, 16>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 16,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[8]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[9]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[10]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[11]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[12]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[13]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[14]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[15]",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Array {
+                    element: CompiledTypeLayout {
+                        ty: UInt<8>,
+                        layout: TypeLayout {
+                            small_slots: StatePartLayout<SmallSlots> {
+                                len: 0,
+                                debug_data: [],
+                                ..
+                            },
+                            big_slots: StatePartLayout<BigSlots> {
+                                len: 1,
+                                debug_data: [
+                                    SlotDebugData {
+                                        name: "",
+                                        ty: UInt<8>,
+                                    },
+                                ],
+                                ..
+                            },
+                        },
+                        body: Scalar,
+                    },
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 16 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[0]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[10]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 10, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[11]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 11, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[12]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 12, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[13]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 13, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[14]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 14, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[15]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 15, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[1]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[2]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[3]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[4]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[5]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[6]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 6, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[7]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 7, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[8]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 8, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_in[9]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 9, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Array<UInt<8>, 16>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 16,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[2]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[3]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[4]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[5]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[6]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[7]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[8]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[9]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[10]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[11]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[12]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[13]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[14]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[15]",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Array {
+                    element: CompiledTypeLayout {
+                        ty: UInt<8>,
+                        layout: TypeLayout {
+                            small_slots: StatePartLayout<SmallSlots> {
+                                len: 0,
+                                debug_data: [],
+                                ..
+                            },
+                            big_slots: StatePartLayout<BigSlots> {
+                                len: 1,
+                                debug_data: [
+                                    SlotDebugData {
+                                        name: "",
+                                        ty: UInt<8>,
+                                    },
+                                ],
+                                ..
+                            },
+                        },
+                        body: Scalar,
+                    },
+                },
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 16, len: 16 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[0]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 16, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[10]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 26, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[11]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 27, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[12]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 28, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[13]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 29, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[14]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 30, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[15]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 31, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[1]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 17, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[2]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 18, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[3]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 19, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[4]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 20, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[5]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 21, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[6]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 22, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[7]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 23, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[8]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 24, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.array_out[9]: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 25, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.read_data: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::read_data",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 33, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.read_index: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::read_index",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 32, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.write_data: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::write_data",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 35, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.write_en: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::write_en",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 36, len: 1 },
+            },
+            write: None,
+        },
+        Instance {
+            name: <simulator>::array_rw,
+            instantiated: Module {
+                name: array_rw,
+                ..
+            },
+        }.write_index: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: UInt<8>,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(array_rw: array_rw).array_rw::write_index",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 34, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "array_rw",
+        children: [
+            TraceModuleIO {
+                name: "array_in",
+                child: TraceArray {
+                    name: "array_in",
+                    elements: [
+                        TraceUInt {
+                            location: TraceScalarId(0),
+                            name: "[0]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(1),
+                            name: "[1]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(2),
+                            name: "[2]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(3),
+                            name: "[3]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(4),
+                            name: "[4]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(5),
+                            name: "[5]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(6),
+                            name: "[6]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(7),
+                            name: "[7]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(8),
+                            name: "[8]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(9),
+                            name: "[9]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(10),
+                            name: "[10]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(11),
+                            name: "[11]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(12),
+                            name: "[12]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(13),
+                            name: "[13]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(14),
+                            name: "[14]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(15),
+                            name: "[15]",
+                            ty: UInt<8>,
+                            flow: Source,
+                        },
+                    ],
+                    ty: Array<UInt<8>, 16>,
+                    flow: Source,
+                },
+                ty: Array<UInt<8>, 16>,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "array_out",
+                child: TraceArray {
+                    name: "array_out",
+                    elements: [
+                        TraceUInt {
+                            location: TraceScalarId(16),
+                            name: "[0]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(17),
+                            name: "[1]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(18),
+                            name: "[2]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(19),
+                            name: "[3]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(20),
+                            name: "[4]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(21),
+                            name: "[5]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(22),
+                            name: "[6]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(23),
+                            name: "[7]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(24),
+                            name: "[8]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(25),
+                            name: "[9]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(26),
+                            name: "[10]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(27),
+                            name: "[11]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(28),
+                            name: "[12]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(29),
+                            name: "[13]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(30),
+                            name: "[14]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(31),
+                            name: "[15]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                    ],
+                    ty: Array<UInt<8>, 16>,
+                    flow: Sink,
+                },
+                ty: Array<UInt<8>, 16>,
+                flow: Sink,
+            },
+            TraceModuleIO {
+                name: "read_index",
+                child: TraceUInt {
+                    location: TraceScalarId(32),
+                    name: "read_index",
+                    ty: UInt<8>,
+                    flow: Source,
+                },
+                ty: UInt<8>,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "read_data",
+                child: TraceUInt {
+                    location: TraceScalarId(33),
+                    name: "read_data",
+                    ty: UInt<8>,
+                    flow: Sink,
+                },
+                ty: UInt<8>,
+                flow: Sink,
+            },
+            TraceModuleIO {
+                name: "write_index",
+                child: TraceUInt {
+                    location: TraceScalarId(34),
+                    name: "write_index",
+                    ty: UInt<8>,
+                    flow: Source,
+                },
+                ty: UInt<8>,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "write_data",
+                child: TraceUInt {
+                    location: TraceScalarId(35),
+                    name: "write_data",
+                    ty: UInt<8>,
+                    flow: Source,
+                },
+                ty: UInt<8>,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "write_en",
+                child: TraceBool {
+                    location: TraceScalarId(36),
+                    name: "write_en",
+                    flow: Source,
+                },
+                ty: Bool,
+                flow: Source,
+            },
+            TraceWire {
+                name: "array_wire",
+                child: TraceArray {
+                    name: "array_wire",
+                    elements: [
+                        TraceUInt {
+                            location: TraceScalarId(37),
+                            name: "[0]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(38),
+                            name: "[1]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(39),
+                            name: "[2]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(40),
+                            name: "[3]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(41),
+                            name: "[4]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(42),
+                            name: "[5]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(43),
+                            name: "[6]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(44),
+                            name: "[7]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(45),
+                            name: "[8]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(46),
+                            name: "[9]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(47),
+                            name: "[10]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(48),
+                            name: "[11]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(49),
+                            name: "[12]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(50),
+                            name: "[13]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(51),
+                            name: "[14]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(52),
+                            name: "[15]",
+                            ty: UInt<8>,
+                            flow: Duplex,
+                        },
+                    ],
+                    ty: Array<UInt<8>, 16>,
+                    flow: Duplex,
+                },
+                ty: Array<UInt<8>, 16>,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(0),
+                ty: UInt<8>,
+            },
+            state: 0xff,
+            last_state: 0xff,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(1),
+                ty: UInt<8>,
+            },
+            state: 0x7f,
+            last_state: 0x7f,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(2),
+                ty: UInt<8>,
+            },
+            state: 0x3f,
+            last_state: 0x3f,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<8>,
+            },
+            state: 0x1f,
+            last_state: 0x1f,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(4),
+                ty: UInt<8>,
+            },
+            state: 0x0f,
+            last_state: 0x0f,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(5),
+                ty: UInt<8>,
+            },
+            state: 0x07,
+            last_state: 0x07,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(6),
+                ty: UInt<8>,
+            },
+            state: 0x03,
+            last_state: 0x03,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(7),
+                ty: UInt<8>,
+            },
+            state: 0x01,
+            last_state: 0x01,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(8),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(9),
+                ty: UInt<8>,
+            },
+            state: 0x80,
+            last_state: 0x80,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(10),
+                ty: UInt<8>,
+            },
+            state: 0xc0,
+            last_state: 0xc0,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(11),
+                ty: UInt<8>,
+            },
+            state: 0xe0,
+            last_state: 0xe0,
+        },
+        SimTrace {
+            id: TraceScalarId(12),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(12),
+                ty: UInt<8>,
+            },
+            state: 0xf0,
+            last_state: 0xf0,
+        },
+        SimTrace {
+            id: TraceScalarId(13),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(13),
+                ty: UInt<8>,
+            },
+            state: 0xf8,
+            last_state: 0xf8,
+        },
+        SimTrace {
+            id: TraceScalarId(14),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(14),
+                ty: UInt<8>,
+            },
+            state: 0xfc,
+            last_state: 0xfc,
+        },
+        SimTrace {
+            id: TraceScalarId(15),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(15),
+                ty: UInt<8>,
+            },
+            state: 0xfe,
+            last_state: 0xfe,
+        },
+        SimTrace {
+            id: TraceScalarId(16),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(16),
+                ty: UInt<8>,
+            },
+            state: 0xff,
+            last_state: 0xff,
+        },
+        SimTrace {
+            id: TraceScalarId(17),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(17),
+                ty: UInt<8>,
+            },
+            state: 0x7f,
+            last_state: 0x7f,
+        },
+        SimTrace {
+            id: TraceScalarId(18),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(18),
+                ty: UInt<8>,
+            },
+            state: 0x3f,
+            last_state: 0x3f,
+        },
+        SimTrace {
+            id: TraceScalarId(19),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(19),
+                ty: UInt<8>,
+            },
+            state: 0x1f,
+            last_state: 0x1f,
+        },
+        SimTrace {
+            id: TraceScalarId(20),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(20),
+                ty: UInt<8>,
+            },
+            state: 0x0f,
+            last_state: 0x0f,
+        },
+        SimTrace {
+            id: TraceScalarId(21),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(21),
+                ty: UInt<8>,
+            },
+            state: 0x07,
+            last_state: 0x07,
+        },
+        SimTrace {
+            id: TraceScalarId(22),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(22),
+                ty: UInt<8>,
+            },
+            state: 0x03,
+            last_state: 0x03,
+        },
+        SimTrace {
+            id: TraceScalarId(23),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(23),
+                ty: UInt<8>,
+            },
+            state: 0x01,
+            last_state: 0x01,
+        },
+        SimTrace {
+            id: TraceScalarId(24),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(24),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(25),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(25),
+                ty: UInt<8>,
+            },
+            state: 0x80,
+            last_state: 0x80,
+        },
+        SimTrace {
+            id: TraceScalarId(26),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(26),
+                ty: UInt<8>,
+            },
+            state: 0xc0,
+            last_state: 0xc0,
+        },
+        SimTrace {
+            id: TraceScalarId(27),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(27),
+                ty: UInt<8>,
+            },
+            state: 0xe0,
+            last_state: 0xe0,
+        },
+        SimTrace {
+            id: TraceScalarId(28),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(28),
+                ty: UInt<8>,
+            },
+            state: 0xf0,
+            last_state: 0xf0,
+        },
+        SimTrace {
+            id: TraceScalarId(29),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(29),
+                ty: UInt<8>,
+            },
+            state: 0xf8,
+            last_state: 0xf8,
+        },
+        SimTrace {
+            id: TraceScalarId(30),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(30),
+                ty: UInt<8>,
+            },
+            state: 0xfc,
+            last_state: 0xfc,
+        },
+        SimTrace {
+            id: TraceScalarId(31),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(31),
+                ty: UInt<8>,
+            },
+            state: 0xfe,
+            last_state: 0xe1,
+        },
+        SimTrace {
+            id: TraceScalarId(32),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(32),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(33),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(33),
+                ty: UInt<8>,
+            },
+            state: 0xff,
+            last_state: 0xff,
+        },
+        SimTrace {
+            id: TraceScalarId(34),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(34),
+                ty: UInt<8>,
+            },
+            state: 0x10,
+            last_state: 0x0f,
+        },
+        SimTrace {
+            id: TraceScalarId(35),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(35),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0xe1,
+        },
+        SimTrace {
+            id: TraceScalarId(36),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(36),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(37),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(37),
+                ty: UInt<8>,
+            },
+            state: 0xff,
+            last_state: 0xff,
+        },
+        SimTrace {
+            id: TraceScalarId(38),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(38),
+                ty: UInt<8>,
+            },
+            state: 0x7f,
+            last_state: 0x7f,
+        },
+        SimTrace {
+            id: TraceScalarId(39),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(39),
+                ty: UInt<8>,
+            },
+            state: 0x3f,
+            last_state: 0x3f,
+        },
+        SimTrace {
+            id: TraceScalarId(40),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(40),
+                ty: UInt<8>,
+            },
+            state: 0x1f,
+            last_state: 0x1f,
+        },
+        SimTrace {
+            id: TraceScalarId(41),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(41),
+                ty: UInt<8>,
+            },
+            state: 0x0f,
+            last_state: 0x0f,
+        },
+        SimTrace {
+            id: TraceScalarId(42),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(42),
+                ty: UInt<8>,
+            },
+            state: 0x07,
+            last_state: 0x07,
+        },
+        SimTrace {
+            id: TraceScalarId(43),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(43),
+                ty: UInt<8>,
+            },
+            state: 0x03,
+            last_state: 0x03,
+        },
+        SimTrace {
+            id: TraceScalarId(44),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(44),
+                ty: UInt<8>,
+            },
+            state: 0x01,
+            last_state: 0x01,
+        },
+        SimTrace {
+            id: TraceScalarId(45),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(45),
+                ty: UInt<8>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(46),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(46),
+                ty: UInt<8>,
+            },
+            state: 0x80,
+            last_state: 0x80,
+        },
+        SimTrace {
+            id: TraceScalarId(47),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(47),
+                ty: UInt<8>,
+            },
+            state: 0xc0,
+            last_state: 0xc0,
+        },
+        SimTrace {
+            id: TraceScalarId(48),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(48),
+                ty: UInt<8>,
+            },
+            state: 0xe0,
+            last_state: 0xe0,
+        },
+        SimTrace {
+            id: TraceScalarId(49),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(49),
+                ty: UInt<8>,
+            },
+            state: 0xf0,
+            last_state: 0xf0,
+        },
+        SimTrace {
+            id: TraceScalarId(50),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(50),
+                ty: UInt<8>,
+            },
+            state: 0xf8,
+            last_state: 0xf8,
+        },
+        SimTrace {
+            id: TraceScalarId(51),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(51),
+                ty: UInt<8>,
+            },
+            state: 0xfc,
+            last_state: 0xfc,
+        },
+        SimTrace {
+            id: TraceScalarId(52),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(52),
+                ty: UInt<8>,
+            },
+            state: 0xfe,
+            last_state: 0xe1,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 34 μs,
+    clocks_triggered: [],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/array_rw.vcd b/crates/fayalite/tests/sim/expected/array_rw.vcd
new file mode 100644
index 0000000..8ede394
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/array_rw.vcd
@@ -0,0 +1,283 @@
+$timescale 1 ps $end
+$scope module array_rw $end
+$scope struct array_in $end
+$var wire 8 ! \[0] $end
+$var wire 8 " \[1] $end
+$var wire 8 # \[2] $end
+$var wire 8 $ \[3] $end
+$var wire 8 % \[4] $end
+$var wire 8 & \[5] $end
+$var wire 8 ' \[6] $end
+$var wire 8 ( \[7] $end
+$var wire 8 ) \[8] $end
+$var wire 8 * \[9] $end
+$var wire 8 + \[10] $end
+$var wire 8 , \[11] $end
+$var wire 8 - \[12] $end
+$var wire 8 . \[13] $end
+$var wire 8 / \[14] $end
+$var wire 8 0 \[15] $end
+$upscope $end
+$scope struct array_out $end
+$var wire 8 1 \[0] $end
+$var wire 8 2 \[1] $end
+$var wire 8 3 \[2] $end
+$var wire 8 4 \[3] $end
+$var wire 8 5 \[4] $end
+$var wire 8 6 \[5] $end
+$var wire 8 7 \[6] $end
+$var wire 8 8 \[7] $end
+$var wire 8 9 \[8] $end
+$var wire 8 : \[9] $end
+$var wire 8 ; \[10] $end
+$var wire 8 < \[11] $end
+$var wire 8 = \[12] $end
+$var wire 8 > \[13] $end
+$var wire 8 ? \[14] $end
+$var wire 8 @ \[15] $end
+$upscope $end
+$var wire 8 A read_index $end
+$var wire 8 B read_data $end
+$var wire 8 C write_index $end
+$var wire 8 D write_data $end
+$var wire 1 E write_en $end
+$scope struct array_wire $end
+$var wire 8 F \[0] $end
+$var wire 8 G \[1] $end
+$var wire 8 H \[2] $end
+$var wire 8 I \[3] $end
+$var wire 8 J \[4] $end
+$var wire 8 K \[5] $end
+$var wire 8 L \[6] $end
+$var wire 8 M \[7] $end
+$var wire 8 N \[8] $end
+$var wire 8 O \[9] $end
+$var wire 8 P \[10] $end
+$var wire 8 Q \[11] $end
+$var wire 8 R \[12] $end
+$var wire 8 S \[13] $end
+$var wire 8 T \[14] $end
+$var wire 8 U \[15] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+b11111111 !
+b1111111 "
+b111111 #
+b11111 $
+b1111 %
+b111 &
+b11 '
+b1 (
+b0 )
+b10000000 *
+b11000000 +
+b11100000 ,
+b11110000 -
+b11111000 .
+b11111100 /
+b11111110 0
+b11111111 1
+b1111111 2
+b111111 3
+b11111 4
+b1111 5
+b111 6
+b11 7
+b1 8
+b0 9
+b10000000 :
+b11000000 ;
+b11100000 <
+b11110000 =
+b11111000 >
+b11111100 ?
+b11111110 @
+b0 A
+b11111111 B
+b0 C
+b0 D
+0E
+b11111111 F
+b1111111 G
+b111111 H
+b11111 I
+b1111 J
+b111 K
+b11 L
+b1 M
+b0 N
+b10000000 O
+b11000000 P
+b11100000 Q
+b11110000 R
+b11111000 S
+b11111100 T
+b11111110 U
+$end
+#1000000
+b1 A
+b1111111 B
+#2000000
+b10 A
+b111111 B
+#3000000
+b11 A
+b11111 B
+#4000000
+b100 A
+b1111 B
+#5000000
+b101 A
+b111 B
+#6000000
+b110 A
+b11 B
+#7000000
+b111 A
+b1 B
+#8000000
+b1000 A
+b0 B
+#9000000
+b1001 A
+b10000000 B
+#10000000
+b1010 A
+b11000000 B
+#11000000
+b1011 A
+b11100000 B
+#12000000
+b1100 A
+b11110000 B
+#13000000
+b1101 A
+b11111000 B
+#14000000
+b1110 A
+b11111100 B
+#15000000
+b1111 A
+b11111110 B
+#16000000
+b10000 A
+b0 B
+#17000000
+b0 1
+b0 A
+1E
+b0 F
+#18000000
+b11111111 1
+b1 2
+b11111111 B
+b1 C
+b1 D
+b11111111 F
+b1 G
+#19000000
+b1111111 2
+b100 3
+b10 C
+b100 D
+b1111111 G
+b100 H
+#20000000
+b111111 3
+b1001 4
+b11 C
+b1001 D
+b111111 H
+b1001 I
+#21000000
+b11111 4
+b10000 5
+b100 C
+b10000 D
+b11111 I
+b10000 J
+#22000000
+b1111 5
+b11001 6
+b101 C
+b11001 D
+b1111 J
+b11001 K
+#23000000
+b111 6
+b100100 7
+b110 C
+b100100 D
+b111 K
+b100100 L
+#24000000
+b11 7
+b110001 8
+b111 C
+b110001 D
+b11 L
+b110001 M
+#25000000
+b1 8
+b1000000 9
+b1000 C
+b1000000 D
+b1 M
+b1000000 N
+#26000000
+b0 9
+b1010001 :
+b1001 C
+b1010001 D
+b0 N
+b1010001 O
+#27000000
+b10000000 :
+b1100100 ;
+b1010 C
+b1100100 D
+b10000000 O
+b1100100 P
+#28000000
+b11000000 ;
+b1111001 <
+b1011 C
+b1111001 D
+b11000000 P
+b1111001 Q
+#29000000
+b11100000 <
+b10010000 =
+b1100 C
+b10010000 D
+b11100000 Q
+b10010000 R
+#30000000
+b11110000 =
+b10101001 >
+b1101 C
+b10101001 D
+b11110000 R
+b10101001 S
+#31000000
+b11111000 >
+b11000100 ?
+b1110 C
+b11000100 D
+b11111000 S
+b11000100 T
+#32000000
+b11111100 ?
+b11100001 @
+b1111 C
+b11100001 D
+b11111100 T
+b11100001 U
+#33000000
+b11111110 @
+b10000 C
+b0 D
+b11111110 U
+#34000000

From d4ea8260512e54c5187c1c59bd9bac47a319f86d Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 15 Jan 2025 19:04:40 -0800
Subject: [PATCH 150/190] sim: fix "label address not set" bug when the last
 Assignment is conditional

---
 crates/fayalite/src/sim.rs                    |   3 +
 crates/fayalite/tests/sim.rs                  |  36 ++++
 .../expected/conditional_assignment_last.txt  | 189 ++++++++++++++++++
 .../expected/conditional_assignment_last.vcd  |  14 ++
 4 files changed, 242 insertions(+)
 create mode 100644 crates/fayalite/tests/sim/expected/conditional_assignment_last.txt
 create mode 100644 crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index cb6228d..f630f5a 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -4773,6 +4773,9 @@ impl Compiler {
             }
             self.insns.extend(insns.iter().copied(), *source_location);
         }
+        for CondStackEntry { cond: _, end_label } in cond_stack {
+            self.insns.define_label_at_next_insn(end_label);
+        }
     }
     fn process_clocks(&mut self) -> Interned<[StatePartIndex<StatePartKindSmallSlots>]> {
         mem::take(&mut self.clock_triggers)
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index cae08de..8c8a10f 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -1407,3 +1407,39 @@ fn test_array_rw() {
         panic!();
     }
 }
+
+#[hdl_module(outline_generated)]
+pub fn conditional_assignment_last() {
+    #[hdl]
+    let i: Bool = m.input();
+    #[hdl]
+    let w = wire();
+    connect(w, true);
+    #[hdl]
+    if i {
+        connect(w, false);
+    }
+}
+
+#[test]
+fn test_conditional_assignment_last() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(conditional_assignment_last());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write(sim.io().i, false);
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.write(sim.io().i, true);
+    sim.advance_time(SimDuration::from_micros(1));
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/conditional_assignment_last.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/conditional_assignment_last.txt") {
+        panic!();
+    }
+}
diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt
new file mode 100644
index 0000000..186e5a5
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt
@@ -0,0 +1,189 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 4,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::i",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::w",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: Const {
+                    dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    value: 0x0,
+                },
+                1: Const {
+                    dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    value: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:4:1
+                2: Copy {
+                    dest: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::w", ty: Bool },
+                    src: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                3: BranchIfZero {
+                    target: 5,
+                    value: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::i", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::w", ty: Bool },
+                    src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                5: Return,
+            ],
+            ..
+        },
+        pc: 5,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                0,
+                1,
+                0,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::conditional_assignment_last,
+        instantiated: Module {
+            name: conditional_assignment_last,
+            ..
+        },
+    },
+    uninitialized_inputs: {},
+    io_targets: {
+        Instance {
+            name: <simulator>::conditional_assignment_last,
+            instantiated: Module {
+                name: conditional_assignment_last,
+                ..
+            },
+        }.i: CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Bool,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::i",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+            },
+            write: None,
+        },
+    },
+    made_initial_step: true,
+    needs_settle: false,
+    trace_decls: TraceModule {
+        name: "conditional_assignment_last",
+        children: [
+            TraceModuleIO {
+                name: "i",
+                child: TraceBool {
+                    location: TraceScalarId(0),
+                    name: "i",
+                    flow: Source,
+                },
+                ty: Bool,
+                flow: Source,
+            },
+            TraceWire {
+                name: "w",
+                child: TraceBool {
+                    location: TraceScalarId(1),
+                    name: "w",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 2 μs,
+    clocks_triggered: [],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd b/crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd
new file mode 100644
index 0000000..dd9a85a
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.vcd
@@ -0,0 +1,14 @@
+$timescale 1 ps $end
+$scope module conditional_assignment_last $end
+$var wire 1 ! i $end
+$var wire 1 " w $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+1"
+$end
+#1000000
+1!
+0"
+#2000000

From 209d5b5fe1b16652dacbd9a72156764a2f4138eb Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 10 Feb 2025 22:49:16 -0800
Subject: [PATCH 151/190] fix broken doc links

---
 crates/fayalite/src/int.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index b49ca3f..5d10b29 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -567,12 +567,12 @@ impl_prim_int!(i64, SInt<64>);
 impl_prim_int!(i128, SInt<128>);
 
 impl_prim_int!(
-    /// for portability reasons, [`usize`] always translates to [`UInt<64>`]
+    /// for portability reasons, [`usize`] always translates to [`UInt<64>`][type@UInt]
     usize, UInt<64>
 );
 
 impl_prim_int!(
-    /// for portability reasons, [`isize`] always translates to [`SInt<64>`]
+    /// for portability reasons, [`isize`] always translates to [`SInt<64>`][type@SInt]
     isize, SInt<64>
 );
 

From 86a1bb46be4690e854470cf4a1a6e90c92268391 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 10 Feb 2025 22:49:41 -0800
Subject: [PATCH 152/190] add #[hdl] let destructuring and, while at it, tuple
 patterns

---
 .../src/module/transform_body.rs              |  25 +-
 .../src/module/transform_body/expand_match.rs | 330 +++++++++++++++++-
 .../module_bodies/hdl_let_statements.rs       |   1 +
 .../hdl_let_statements/destructuring.rs       |  33 ++
 .../module_bodies/hdl_match_statements.rs     |   2 +-
 crates/fayalite/tests/module.rs               |  76 ++++
 6 files changed, 454 insertions(+), 13 deletions(-)
 create mode 100644 crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs

diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
index 6e99e87..c67f8dc 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
@@ -1109,7 +1109,7 @@ fn parse_quote_let_pat<T, R: ToTokens, C: Borrow<Token![:]>>(
     }
 }
 
-fn wrap_ty_with_expr(ty: impl ToTokens) -> Type {
+pub(crate) fn wrap_ty_with_expr(ty: impl ToTokens) -> Type {
     parse_quote_spanned! {ty.span()=>
         ::fayalite::expr::Expr<#ty>
     }
@@ -1586,7 +1586,7 @@ impl Visitor<'_> {
     }
 }
 
-fn empty_let() -> Local {
+pub(crate) fn empty_let() -> Local {
     Local {
         attrs: vec![],
         let_token: Default::default(),
@@ -1672,7 +1672,7 @@ impl Fold for Visitor<'_> {
         }
     }
 
-    fn fold_local(&mut self, let_stmt: Local) -> Local {
+    fn fold_local(&mut self, mut let_stmt: Local) -> Local {
         match self
             .errors
             .ok(HdlAttr::<Nothing, kw::hdl>::parse_and_leave_attr(
@@ -1682,6 +1682,25 @@ impl Fold for Visitor<'_> {
             Some(None) => return fold_local(self, let_stmt),
             Some(Some(HdlAttr { .. })) => {}
         };
+        let mut pat = &let_stmt.pat;
+        if let Pat::Type(pat_type) = pat {
+            pat = &pat_type.pat;
+        }
+        let Pat::Ident(syn::PatIdent {
+            attrs: _,
+            by_ref: None,
+            mutability: _,
+            ident: _,
+            subpat: None,
+        }) = pat
+        else {
+            let hdl_attr = HdlAttr::<Nothing, kw::hdl>::parse_and_take_attr(&mut let_stmt.attrs)
+                .ok()
+                .flatten()
+                .expect("already checked above");
+            let let_stmt = fold_local(self, let_stmt);
+            return self.process_hdl_let_pat(hdl_attr, let_stmt);
+        };
         let hdl_let = syn::parse2::<HdlLet<HdlLetKind<Type>>>(let_stmt.into_token_stream());
         let Some(hdl_let) = self.errors.ok(hdl_let) else {
             return empty_let();
diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
index 1d53104..f1ff2c2 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
@@ -3,22 +3,111 @@
 use crate::{
     fold::{impl_fold, DoFold},
     kw,
-    module::transform_body::{with_debug_clone_and_fold, Visitor},
+    module::transform_body::{empty_let, with_debug_clone_and_fold, wrap_ty_with_expr, Visitor},
     Errors, HdlAttr, PairsIterExt,
 };
 use proc_macro2::{Span, TokenStream};
 use quote::{format_ident, quote_spanned, ToTokens, TokenStreamExt};
+use std::collections::BTreeSet;
 use syn::{
-    fold::{fold_arm, fold_expr_match, fold_pat, Fold},
+    fold::{fold_arm, fold_expr_match, fold_local, fold_pat, Fold},
     parse::Nothing,
     parse_quote_spanned,
     punctuated::Punctuated,
     spanned::Spanned,
     token::{Brace, Paren},
-    Arm, Attribute, Expr, ExprMatch, FieldPat, Ident, Member, Pat, PatIdent, PatOr, PatParen,
-    PatPath, PatRest, PatStruct, PatTupleStruct, PatWild, Path, PathSegment, Token, TypePath,
+    Arm, Attribute, Expr, ExprMatch, FieldPat, Ident, Local, Member, Pat, PatIdent, PatOr,
+    PatParen, PatPath, PatRest, PatStruct, PatTuple, PatTupleStruct, PatWild, Path, PathSegment,
+    Token, TypePath,
 };
 
+macro_rules! visit_trait {
+    (
+        $($vis:vis fn $fn:ident($state:ident: _, $value:ident: &$Value:ty) $block:block)*
+    ) => {
+        trait VisitMatchPat<'a> {
+            $(fn $fn(&mut self, $value: &'a $Value) {
+                $fn(self, $value);
+            })*
+        }
+
+        $($vis fn $fn<'a>($state: &mut (impl ?Sized + VisitMatchPat<'a>), $value: &'a $Value) $block)*
+    };
+}
+
+visit_trait! {
+    fn visit_match_pat_binding(_state: _, v: &MatchPatBinding) {
+        let MatchPatBinding { ident: _ } = v;
+    }
+    fn visit_match_pat_wild(_state: _, v: &MatchPatWild) {
+        let MatchPatWild { underscore_token: _ } = v;
+    }
+    fn visit_match_pat_rest(_state: _, v: &MatchPatRest) {
+        let MatchPatRest { dot2_token: _ } = v;
+    }
+    fn visit_match_pat_paren(state: _, v: &MatchPatParen<MatchPat>) {
+        let MatchPatParen { paren_token: _, pat } = v;
+        state.visit_match_pat(pat);
+    }
+    fn visit_match_pat_paren_simple(state: _, v: &MatchPatParen<MatchPatSimple>) {
+        let MatchPatParen { paren_token: _, pat } = v;
+        state.visit_match_pat_simple(pat);
+    }
+    fn visit_match_pat_or(state: _, v: &MatchPatOr<MatchPat>) {
+        let MatchPatOr { leading_vert: _, cases } = v;
+        for v in cases {
+            state.visit_match_pat(v);
+        }
+    }
+    fn visit_match_pat_or_simple(state: _, v: &MatchPatOr<MatchPatSimple>) {
+        let MatchPatOr { leading_vert: _, cases } = v;
+        for v in cases {
+            state.visit_match_pat_simple(v);
+        }
+    }
+    fn visit_match_pat_struct_field(state: _, v: &MatchPatStructField) {
+        let MatchPatStructField { field_name: _, colon_token: _, pat } = v;
+        state.visit_match_pat_simple(pat);
+    }
+    fn visit_match_pat_struct(state: _, v: &MatchPatStruct) {
+        let MatchPatStruct { match_span: _, path: _, brace_token: _, fields, rest: _ } = v;
+        for v in fields {
+            state.visit_match_pat_struct_field(v);
+        }
+    }
+    fn visit_match_pat_tuple(state: _, v: &MatchPatTuple) {
+        let MatchPatTuple { paren_token: _, fields } = v;
+        for v in fields {
+            state.visit_match_pat_simple(v);
+        }
+    }
+    fn visit_match_pat_enum_variant(state: _, v: &MatchPatEnumVariant) {
+        let MatchPatEnumVariant {match_span:_, variant_path: _, enum_path: _, variant_name: _, field } = v;
+        if let Some((_, v)) = field {
+            state.visit_match_pat_simple(v);
+        }
+    }
+    fn visit_match_pat_simple(state: _, v: &MatchPatSimple) {
+        match v {
+            MatchPatSimple::Paren(v) => state.visit_match_pat_paren_simple(v),
+            MatchPatSimple::Or(v) => state.visit_match_pat_or_simple(v),
+            MatchPatSimple::Binding(v) => state.visit_match_pat_binding(v),
+            MatchPatSimple::Wild(v) => state.visit_match_pat_wild(v),
+            MatchPatSimple::Rest(v) => state.visit_match_pat_rest(v),
+        }
+    }
+    fn visit_match_pat(state: _, v: &MatchPat) {
+        match v {
+            MatchPat::Simple(v) => state.visit_match_pat_simple(v),
+            MatchPat::Or(v) => state.visit_match_pat_or(v),
+            MatchPat::Paren(v) => state.visit_match_pat_paren(v),
+            MatchPat::Struct(v) => state.visit_match_pat_struct(v),
+            MatchPat::Tuple(v) => state.visit_match_pat_tuple(v),
+            MatchPat::EnumVariant(v) => state.visit_match_pat_enum_variant(v),
+        }
+    }
+}
+
 with_debug_clone_and_fold! {
     struct MatchPatBinding<> {
         ident: Ident,
@@ -53,6 +142,15 @@ with_debug_clone_and_fold! {
     }
 }
 
+impl<P> MatchPatOr<P> {
+    /// returns the first `|` between two patterns
+    fn first_inner_vert(&self) -> Option<Token![|]> {
+        let mut pairs = self.cases.pairs();
+        pairs.next_back();
+        pairs.next().and_then(|v| v.into_tuple().1.copied())
+    }
+}
+
 impl<P: ToTokens> ToTokens for MatchPatOr<P> {
     fn to_tokens(&self, tokens: &mut TokenStream) {
         let Self {
@@ -77,6 +175,19 @@ impl ToTokens for MatchPatWild {
     }
 }
 
+with_debug_clone_and_fold! {
+    struct MatchPatRest<> {
+        dot2_token: Token![..],
+    }
+}
+
+impl ToTokens for MatchPatRest {
+    fn to_tokens(&self, tokens: &mut TokenStream) {
+        let Self { dot2_token } = self;
+        dot2_token.to_tokens(tokens);
+    }
+}
+
 with_debug_clone_and_fold! {
     struct MatchPatStructField<> {
         field_name: Ident,
@@ -159,6 +270,25 @@ impl ToTokens for MatchPatStruct {
     }
 }
 
+with_debug_clone_and_fold! {
+    struct MatchPatTuple<> {
+        paren_token: Paren,
+        fields: Punctuated<MatchPatSimple, Token![,]>,
+    }
+}
+
+impl ToTokens for MatchPatTuple {
+    fn to_tokens(&self, tokens: &mut TokenStream) {
+        let Self {
+            paren_token,
+            fields,
+        } = self;
+        paren_token.surround(tokens, |tokens| {
+            fields.to_tokens(tokens);
+        })
+    }
+}
+
 with_debug_clone_and_fold! {
     struct MatchPatEnumVariant<> {
         match_span: Span,
@@ -194,6 +324,7 @@ enum MatchPatSimple {
     Or(MatchPatOr<MatchPatSimple>),
     Binding(MatchPatBinding),
     Wild(MatchPatWild),
+    Rest(MatchPatRest),
 }
 
 impl_fold! {
@@ -202,6 +333,7 @@ impl_fold! {
         Or(MatchPatOr<MatchPatSimple>),
         Binding(MatchPatBinding),
         Wild(MatchPatWild),
+        Rest(MatchPatRest),
     }
 }
 
@@ -212,6 +344,7 @@ impl ToTokens for MatchPatSimple {
             Self::Paren(v) => v.to_tokens(tokens),
             Self::Binding(v) => v.to_tokens(tokens),
             Self::Wild(v) => v.to_tokens(tokens),
+            Self::Rest(v) => v.to_tokens(tokens),
         }
     }
 }
@@ -278,6 +411,7 @@ trait ParseMatchPat: Sized {
     fn or(v: MatchPatOr<Self>) -> Self;
     fn paren(v: MatchPatParen<Self>) -> Self;
     fn struct_(state: &mut HdlMatchParseState<'_>, v: MatchPatStruct) -> Result<Self, ()>;
+    fn tuple(state: &mut HdlMatchParseState<'_>, v: MatchPatTuple) -> Result<Self, ()>;
     fn enum_variant(state: &mut HdlMatchParseState<'_>, v: MatchPatEnumVariant)
         -> Result<Self, ()>;
     fn parse(state: &mut HdlMatchParseState<'_>, pat: Pat) -> Result<Self, ()> {
@@ -462,7 +596,34 @@ trait ParseMatchPat: Sized {
             }) => Ok(Self::simple(MatchPatSimple::Wild(MatchPatWild {
                 underscore_token,
             }))),
-            Pat::Tuple(_) | Pat::Slice(_) | Pat::Const(_) | Pat::Lit(_) | Pat::Range(_) => {
+            Pat::Tuple(PatTuple {
+                attrs: _,
+                paren_token,
+                elems,
+            }) => {
+                let fields = elems
+                    .into_pairs()
+                    .filter_map_pair_value(|field_pat| {
+                        if let Pat::Rest(PatRest {
+                            attrs: _,
+                            dot2_token,
+                        }) = field_pat
+                        {
+                            Some(MatchPatSimple::Rest(MatchPatRest { dot2_token }))
+                        } else {
+                            MatchPatSimple::parse(state, field_pat).ok()
+                        }
+                    })
+                    .collect();
+                Self::tuple(
+                    state,
+                    MatchPatTuple {
+                        paren_token,
+                        fields,
+                    },
+                )
+            }
+            Pat::Slice(_) | Pat::Const(_) | Pat::Lit(_) | Pat::Range(_) => {
                 state
                     .errors
                     .error(pat, "not yet implemented in #[hdl] patterns");
@@ -497,6 +658,14 @@ impl ParseMatchPat for MatchPatSimple {
         Err(())
     }
 
+    fn tuple(state: &mut HdlMatchParseState<'_>, v: MatchPatTuple) -> Result<Self, ()> {
+        state.errors.push(syn::Error::new(
+            v.paren_token.span.open(),
+            "matching tuples is not yet implemented inside structs/enums in #[hdl] patterns",
+        ));
+        Err(())
+    }
+
     fn enum_variant(
         state: &mut HdlMatchParseState<'_>,
         v: MatchPatEnumVariant,
@@ -515,6 +684,7 @@ enum MatchPat {
     Or(MatchPatOr<MatchPat>),
     Paren(MatchPatParen<MatchPat>),
     Struct(MatchPatStruct),
+    Tuple(MatchPatTuple),
     EnumVariant(MatchPatEnumVariant),
 }
 
@@ -524,6 +694,7 @@ impl_fold! {
         Or(MatchPatOr<MatchPat>),
         Paren(MatchPatParen<MatchPat>),
         Struct(MatchPatStruct),
+        Tuple(MatchPatTuple),
         EnumVariant(MatchPatEnumVariant),
     }
 }
@@ -545,6 +716,10 @@ impl ParseMatchPat for MatchPat {
         Ok(Self::Struct(v))
     }
 
+    fn tuple(_state: &mut HdlMatchParseState<'_>, v: MatchPatTuple) -> Result<Self, ()> {
+        Ok(Self::Tuple(v))
+    }
+
     fn enum_variant(
         _state: &mut HdlMatchParseState<'_>,
         v: MatchPatEnumVariant,
@@ -560,6 +735,7 @@ impl ToTokens for MatchPat {
             Self::Or(v) => v.to_tokens(tokens),
             Self::Paren(v) => v.to_tokens(tokens),
             Self::Struct(v) => v.to_tokens(tokens),
+            Self::Tuple(v) => v.to_tokens(tokens),
             Self::EnumVariant(v) => v.to_tokens(tokens),
         }
     }
@@ -622,10 +798,6 @@ struct RewriteAsCheckMatch {
 }
 
 impl Fold for RewriteAsCheckMatch {
-    fn fold_field_pat(&mut self, mut i: FieldPat) -> FieldPat {
-        i.colon_token = Some(Token![:](i.member.span()));
-        i
-    }
     fn fold_pat(&mut self, pat: Pat) -> Pat {
         match pat {
             Pat::Ident(mut pat_ident) => match parse_enum_ident(pat_ident.ident) {
@@ -740,6 +912,30 @@ impl Fold for RewriteAsCheckMatch {
         // don't recurse into expressions
         i
     }
+    fn fold_local(&mut self, mut let_stmt: Local) -> Local {
+        if let Some(syn::LocalInit {
+            eq_token,
+            expr: _,
+            diverge,
+        }) = let_stmt.init.take()
+        {
+            let_stmt.init = Some(syn::LocalInit {
+                eq_token,
+                expr: parse_quote_spanned! {self.span=>
+                    __match_value
+                },
+                diverge: diverge.map(|(else_, _expr)| {
+                    (
+                        else_,
+                        parse_quote_spanned! {self.span=>
+                            match __infallible {}
+                        },
+                    )
+                }),
+            });
+        }
+        fold_local(self, let_stmt)
+    }
 }
 
 struct HdlMatchParseState<'a> {
@@ -747,7 +943,123 @@ struct HdlMatchParseState<'a> {
     errors: &'a mut Errors,
 }
 
+struct HdlLetPatVisitState<'a> {
+    errors: &'a mut Errors,
+    bindings: BTreeSet<&'a Ident>,
+}
+
+impl<'a> VisitMatchPat<'a> for HdlLetPatVisitState<'a> {
+    fn visit_match_pat_binding(&mut self, v: &'a MatchPatBinding) {
+        self.bindings.insert(&v.ident);
+    }
+
+    fn visit_match_pat_or(&mut self, v: &'a MatchPatOr<MatchPat>) {
+        if let Some(first_inner_vert) = v.first_inner_vert() {
+            self.errors.error(
+                first_inner_vert,
+                "or-patterns are not supported in let statements",
+            );
+        }
+        visit_match_pat_or(self, v);
+    }
+
+    fn visit_match_pat_or_simple(&mut self, v: &'a MatchPatOr<MatchPatSimple>) {
+        if let Some(first_inner_vert) = v.first_inner_vert() {
+            self.errors.error(
+                first_inner_vert,
+                "or-patterns are not supported in let statements",
+            );
+        }
+        visit_match_pat_or_simple(self, v);
+    }
+
+    fn visit_match_pat_enum_variant(&mut self, v: &'a MatchPatEnumVariant) {
+        self.errors.error(v, "refutable pattern in let statement");
+    }
+}
+
 impl Visitor<'_> {
+    pub(crate) fn process_hdl_let_pat(
+        &mut self,
+        _hdl_attr: HdlAttr<Nothing, kw::hdl>,
+        mut let_stmt: Local,
+    ) -> Local {
+        let span = let_stmt.let_token.span();
+        if let Pat::Type(pat) = &mut let_stmt.pat {
+            *pat.ty = wrap_ty_with_expr((*pat.ty).clone());
+        }
+        let check_let_stmt = RewriteAsCheckMatch { span }.fold_local(let_stmt.clone());
+        let Local {
+            attrs: _,
+            let_token,
+            pat,
+            init,
+            semi_token,
+        } = let_stmt;
+        self.require_normal_module_or_fn(let_token);
+        let Some(syn::LocalInit {
+            eq_token,
+            expr,
+            diverge,
+        }) = init
+        else {
+            self.errors
+                .error(let_token, "#[hdl] let must be assigned a value");
+            return empty_let();
+        };
+        if let Some((else_, _)) = diverge {
+            // TODO: implement let-else
+            self.errors
+                .error(else_, "#[hdl] let ... else { ... } is not implemented");
+            return empty_let();
+        }
+        let Ok(pat) = MatchPat::parse(
+            &mut HdlMatchParseState {
+                match_span: span,
+                errors: &mut self.errors,
+            },
+            pat,
+        ) else {
+            return empty_let();
+        };
+        let mut state = HdlLetPatVisitState {
+            errors: &mut self.errors,
+            bindings: BTreeSet::new(),
+        };
+        state.visit_match_pat(&pat);
+        let HdlLetPatVisitState {
+            errors: _,
+            bindings,
+        } = state;
+        let retval = parse_quote_spanned! {span=>
+            let (#(#bindings,)* __scope,) = {
+                type __MatchTy<T> = <T as ::fayalite::ty::Type>::MatchVariant;
+                let __match_expr = ::fayalite::expr::ToExpr::to_expr(&(#expr));
+                ::fayalite::expr::check_match_expr(__match_expr, |__match_value, __infallible| {
+                    #[allow(unused_variables)]
+                    #check_let_stmt
+                    match __infallible {}
+                });
+                let mut __match_iter = ::fayalite::module::match_(__match_expr);
+                let ::fayalite::__std::option::Option::Some(__match_variant) = ::fayalite::__std::iter::Iterator::next(&mut __match_iter) else {
+                    ::fayalite::__std::unreachable!("#[hdl] let with uninhabited type");
+                };
+                let ::fayalite::__std::option::Option::None = ::fayalite::__std::iter::Iterator::next(&mut __match_iter) else {
+                    ::fayalite::__std::unreachable!("#[hdl] let with refutable pattern");
+                };
+                let (__match_variant, __scope) =
+                    ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
+                        __match_variant,
+                    );
+                #let_token #pat #eq_token __match_variant #semi_token
+                (#(#bindings,)* __scope,)
+            };
+        };
+        match retval {
+            syn::Stmt::Local(retval) => retval,
+            _ => unreachable!(),
+        }
+    }
     pub(crate) fn process_hdl_match(
         &mut self,
         _hdl_attr: HdlAttr<Nothing, kw::hdl>,
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements.rs
index 61d29b5..229871b 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements.rs
@@ -2,6 +2,7 @@
 // See Notices.txt for copyright information
 //! ## `#[hdl] let` statements
 
+pub mod destructuring;
 pub mod inputs_outputs;
 pub mod instances;
 pub mod memories;
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs
new file mode 100644
index 0000000..1fc4705
--- /dev/null
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+//! ### Destructuring Let
+//!
+//! You can use `#[hdl] let` to destructure types, similarly to Rust `let` statements with non-trivial patterns.
+//!
+//! `#[hdl] let` statements can only match one level of struct/tuple pattern for now,
+//! e.g. you can match with the pattern `MyStruct { a, b }`, but not `MyStruct { a, b: Struct2 { v } }`.
+//!
+//! ```
+//! # use fayalite::prelude::*;
+//! #[hdl]
+//! struct MyStruct {
+//!     a: UInt<8>,
+//!     b: Bool,
+//! }
+//!
+//! #[hdl_module]
+//! fn my_module() {
+//!     #[hdl]
+//!     let my_input: MyStruct = m.input();
+//!     #[hdl]
+//!     let my_output: UInt<8> = m.input();
+//!     #[hdl]
+//!     let MyStruct { a, b } = my_input;
+//!     #[hdl]
+//!     if b {
+//!         connect(my_output, a);
+//!     } else {
+//!         connect(my_output, 0_hdl_u8);
+//!     }
+//! }
+//! ```
diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs
index 9e6c511..6df70f1 100644
--- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs
+++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs
@@ -7,5 +7,5 @@
 //!
 //! `#[hdl] match` statements' bodies must evaluate to type `()` for now.
 //!
-//! `#[hdl] match` statements can only match one level of struct/enum pattern for now,
+//! `#[hdl] match` statements can only match one level of struct/tuple/enum pattern for now,
 //! e.g. you can match with the pattern `HdlSome(v)`, but not `HdlSome(HdlSome(_))`.
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 4e56df4..49f5689 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -4345,3 +4345,79 @@ circuit check_cfgs:
 ",
     };
 }
+
+#[hdl_module(outline_generated)]
+pub fn check_let_patterns() {
+    #[hdl]
+    let tuple_in: (UInt<1>, SInt<1>, Bool) = m.input();
+    #[hdl]
+    let (tuple_0, tuple_1, tuple_2) = tuple_in;
+    #[hdl]
+    let tuple_0_out: UInt<1> = m.output();
+    connect(tuple_0_out, tuple_0);
+    #[hdl]
+    let tuple_1_out: SInt<1> = m.output();
+    connect(tuple_1_out, tuple_1);
+    #[hdl]
+    let tuple_2_out: Bool = m.output();
+    connect(tuple_2_out, tuple_2);
+
+    #[hdl]
+    let test_struct_in: TestStruct<SInt<8>> = m.input();
+    #[hdl]
+    let TestStruct::<_> { a, b } = test_struct_in;
+    #[hdl]
+    let test_struct_a_out: SInt<8> = m.output();
+    connect(test_struct_a_out, a);
+    #[hdl]
+    let test_struct_b_out: UInt<8> = m.output();
+    connect(test_struct_b_out, b);
+
+    #[hdl]
+    let test_struct_2_in: TestStruct2 = m.input();
+    #[hdl]
+    let TestStruct2 { v } = test_struct_2_in;
+    #[hdl]
+    let test_struct_2_v_out: UInt<8> = m.output();
+    connect(test_struct_2_v_out, v);
+
+    #[hdl]
+    let test_struct_3_in: TestStruct3 = m.input();
+    #[hdl]
+    let TestStruct3 {} = test_struct_3_in;
+}
+
+#[test]
+fn test_let_patterns() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_let_patterns();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_let_patterns.fir": r"FIRRTL version 3.2.0
+circuit check_let_patterns:
+    type Ty0 = {`0`: UInt<1>, `1`: SInt<1>, `2`: UInt<1>}
+    type Ty1 = {a: SInt<8>, b: UInt<8>}
+    type Ty2 = {v: UInt<8>}
+    type Ty3 = {}
+    module check_let_patterns: @[module-XXXXXXXXXX.rs 1:1]
+        input tuple_in: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        output tuple_0_out: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
+        output tuple_1_out: SInt<1> @[module-XXXXXXXXXX.rs 6:1]
+        output tuple_2_out: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
+        input test_struct_in: Ty1 @[module-XXXXXXXXXX.rs 10:1]
+        output test_struct_a_out: SInt<8> @[module-XXXXXXXXXX.rs 12:1]
+        output test_struct_b_out: UInt<8> @[module-XXXXXXXXXX.rs 14:1]
+        input test_struct_2_in: Ty2 @[module-XXXXXXXXXX.rs 16:1]
+        output test_struct_2_v_out: UInt<8> @[module-XXXXXXXXXX.rs 18:1]
+        input test_struct_3_in: Ty3 @[module-XXXXXXXXXX.rs 20:1]
+        connect tuple_0_out, tuple_in.`0` @[module-XXXXXXXXXX.rs 5:1]
+        connect tuple_1_out, tuple_in.`1` @[module-XXXXXXXXXX.rs 7:1]
+        connect tuple_2_out, tuple_in.`2` @[module-XXXXXXXXXX.rs 9:1]
+        connect test_struct_a_out, test_struct_in.a @[module-XXXXXXXXXX.rs 13:1]
+        connect test_struct_b_out, test_struct_in.b @[module-XXXXXXXXXX.rs 15:1]
+        connect test_struct_2_v_out, test_struct_2_in.v @[module-XXXXXXXXXX.rs 19:1]
+",
+    };
+}

From cdd84953d076cd9a83db50e9d11a63b6181b0976 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 13 Feb 2025 18:35:30 -0800
Subject: [PATCH 153/190] support unknown trait bounds in type parameters

---
 .../src/hdl_type_common.rs                    | 130 +++++++++++++++---
 crates/fayalite/tests/module.rs               |   6 +-
 2 files changed, 119 insertions(+), 17 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
index 6193dc3..3b2e1ec 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
@@ -2069,11 +2069,16 @@ macro_rules! impl_bounds {
             $(
                 $Variant:ident,
             )*
+            $(
+                #[unknown]
+                $Unknown:ident,
+            )?
         }
     ) => {
         #[derive(Clone, Debug)]
         $vis enum $enum_type {
             $($Variant(known_items::$Variant),)*
+            $($Unknown(syn::TypeParamBound),)?
         }
 
         $(impl From<known_items::$Variant> for $enum_type {
@@ -2086,28 +2091,54 @@ macro_rules! impl_bounds {
             fn to_tokens(&self, tokens: &mut TokenStream) {
                 match self {
                     $(Self::$Variant(v) => v.to_tokens(tokens),)*
+                    $(Self::$Unknown(v) => v.to_tokens(tokens),)?
                 }
             }
         }
 
         impl $enum_type {
             $vis fn parse_path(path: Path) -> Result<Self, Path> {
+                #![allow(unreachable_code)]
                 $(let path = match known_items::$Variant::parse_path(path) {
                     Ok(v) => return Ok(Self::$Variant(v)),
                     Err(path) => path,
                 };)*
+                $(return Ok(Self::$Unknown(syn::TraitBound {
+                    paren_token: None,
+                    modifier: syn::TraitBoundModifier::None,
+                    lifetimes: None,
+                    path,
+                }.into()));)?
                 Err(path)
             }
+            $vis fn parse_type_param_bound(mut type_param_bound: syn::TypeParamBound) -> Result<Self, syn::TypeParamBound> {
+                #![allow(unreachable_code)]
+                if let syn::TypeParamBound::Trait(mut trait_bound) = type_param_bound {
+                    if let syn::TraitBound {
+                        paren_token: _,
+                        modifier: syn::TraitBoundModifier::None,
+                        lifetimes: None,
+                        path: _,
+                    } = trait_bound {
+                        match Self::parse_path(trait_bound.path) {
+                            Ok(retval) => return Ok(retval),
+                            Err(path) => trait_bound.path = path,
+                        }
+                    }
+                    type_param_bound = trait_bound.into();
+                }
+                $(return Ok(Self::$Unknown(type_param_bound));)?
+                Err(type_param_bound)
+            }
         }
 
         impl Parse for $enum_type {
             fn parse(input: ParseStream) -> syn::Result<Self> {
-                Self::parse_path(Path::parse_mod_style(input)?).map_err(|path| {
-                    syn::Error::new_spanned(
-                        path,
+                Self::parse_type_param_bound(input.parse()?)
+                    .map_err(|type_param_bound| syn::Error::new_spanned(
+                        type_param_bound,
                         format_args!("expected one of: {}", [$(stringify!($Variant)),*].join(", ")),
-                    )
-                })
+                    ))
             }
         }
 
@@ -2115,6 +2146,7 @@ macro_rules! impl_bounds {
         #[allow(non_snake_case)]
         $vis struct $struct_type {
             $($vis $Variant: Option<known_items::$Variant>,)*
+            $($vis $Unknown: Vec<syn::TypeParamBound>,)?
         }
 
         impl ToTokens for $struct_type {
@@ -2126,42 +2158,63 @@ macro_rules! impl_bounds {
                     separator = Some(<Token![+]>::default());
                     v.to_tokens(tokens);
                 })*
+                $(for v in &self.$Unknown {
+                    separator.to_tokens(tokens);
+                    separator = Some(<Token![+]>::default());
+                    v.to_tokens(tokens);
+                })*
             }
         }
 
         const _: () = {
             #[derive(Clone, Debug)]
-            $vis struct Iter($vis $struct_type);
+            #[allow(non_snake_case)]
+            $vis struct Iter {
+                $($Variant: Option<known_items::$Variant>,)*
+                $($Unknown: std::vec::IntoIter<syn::TypeParamBound>,)?
+            }
 
             impl IntoIterator for $struct_type {
                 type Item = $enum_type;
                 type IntoIter = Iter;
 
                 fn into_iter(self) -> Self::IntoIter {
-                    Iter(self)
+                    Iter {
+                        $($Variant: self.$Variant,)*
+                        $($Unknown: self.$Unknown.into_iter(),)?
+                    }
                 }
             }
 
             impl Iterator for Iter {
                 type Item = $enum_type;
 
-
                 fn next(&mut self) -> Option<Self::Item> {
                     $(
-                        if let Some(value) = self.0.$Variant.take() {
+                        if let Some(value) = self.$Variant.take() {
                             return Some($enum_type::$Variant(value));
                         }
                     )*
+                    $(
+                        if let Some(value) = self.$Unknown.next() {
+                            return Some($enum_type::$Unknown(value));
+                        }
+                    )?
                     None
                 }
 
                 #[allow(unused_mut, unused_variables)]
                 fn fold<B, F: FnMut(B, Self::Item) -> B>(mut self, mut init: B, mut f: F) -> B {
                     $(
-                        if let Some(value) = self.0.$Variant.take() {
+                        if let Some(value) = self.$Variant.take() {
                             init = f(init, $enum_type::$Variant(value));
                         }
                     )*
+                    $(
+                        if let Some(value) = self.$Unknown.next() {
+                            init = f(init, $enum_type::$Unknown(value));
+                        }
+                    )?
                     init
                 }
             }
@@ -2173,6 +2226,9 @@ macro_rules! impl_bounds {
                     $($enum_type::$Variant(v) => {
                         self.$Variant = Some(v);
                     })*
+                    $($enum_type::$Unknown(v) => {
+                        self.$Unknown.push(v);
+                    })?
                 });
             }
         }
@@ -2191,6 +2247,7 @@ macro_rules! impl_bounds {
                     $(if let Some(v) = v.$Variant {
                         self.$Variant = Some(v);
                     })*
+                    $(self.$Unknown.extend(v.$Unknown);)*
                 });
             }
         }
@@ -2244,6 +2301,8 @@ impl_bounds! {
         Size,
         StaticType,
         Type,
+        #[unknown]
+        Unknown,
     }
 }
 
@@ -2257,6 +2316,8 @@ impl_bounds! {
         ResetType,
         StaticType,
         Type,
+        #[unknown]
+        Unknown,
     }
 }
 
@@ -2270,6 +2331,7 @@ impl From<ParsedTypeBound> for ParsedBound {
             ParsedTypeBound::ResetType(v) => ParsedBound::ResetType(v),
             ParsedTypeBound::StaticType(v) => ParsedBound::StaticType(v),
             ParsedTypeBound::Type(v) => ParsedBound::Type(v),
+            ParsedTypeBound::Unknown(v) => ParsedBound::Unknown(v),
         }
     }
 }
@@ -2284,6 +2346,7 @@ impl From<ParsedTypeBounds> for ParsedBounds {
             ResetType,
             StaticType,
             Type,
+            Unknown,
         } = value;
         Self {
             BoolOrIntType,
@@ -2295,6 +2358,7 @@ impl From<ParsedTypeBounds> for ParsedBounds {
             Size: None,
             StaticType,
             Type,
+            Unknown,
         }
     }
 }
@@ -2330,6 +2394,7 @@ impl ParsedTypeBound {
                 ParsedTypeBound::Type(known_items::Type(span)),
             ]),
             Self::Type(v) => ParsedTypeBounds::from_iter([ParsedTypeBound::from(v)]),
+            Self::Unknown(v) => ParsedTypeBounds::from_iter([ParsedTypeBound::Unknown(v)]),
         }
     }
 }
@@ -2364,6 +2429,7 @@ impl From<ParsedSizeTypeBounds> for ParsedBounds {
             Size,
             StaticType: None,
             Type: None,
+            Unknown: vec![],
         }
     }
 }
@@ -2391,6 +2457,7 @@ impl ParsedBounds {
     fn categorize(self, errors: &mut Errors, span: Span) -> ParsedBoundsCategory {
         let mut type_bounds = None;
         let mut size_type_bounds = None;
+        let mut unknown_bounds = vec![];
         self.into_iter().for_each(|bound| match bound.categorize() {
             ParsedBoundCategory::Type(bound) => {
                 type_bounds
@@ -2402,15 +2469,37 @@ impl ParsedBounds {
                     .get_or_insert_with(ParsedSizeTypeBounds::default)
                     .extend([bound]);
             }
+            ParsedBoundCategory::Unknown(bound) => unknown_bounds.push(bound),
         });
-        match (type_bounds, size_type_bounds) {
-            (None, None) => ParsedBoundsCategory::Type(ParsedTypeBounds {
+        match (type_bounds, size_type_bounds, unknown_bounds.is_empty()) {
+            (None, None, true) => ParsedBoundsCategory::Type(ParsedTypeBounds {
                 Type: Some(known_items::Type(span)),
                 ..Default::default()
             }),
-            (None, Some(bounds)) => ParsedBoundsCategory::SizeType(bounds),
-            (Some(bounds), None) => ParsedBoundsCategory::Type(bounds),
-            (Some(type_bounds), Some(size_type_bounds)) => {
+            (None, None, false) => {
+                errors.error(
+                    unknown_bounds.remove(0),
+                    "unknown bounds: must use at least one known bound (such as `Type`) with any unknown bounds",
+                );
+                ParsedBoundsCategory::Type(ParsedTypeBounds {
+                    Unknown: unknown_bounds,
+                    ..Default::default()
+                })
+            }
+            (None, Some(bounds), true) => ParsedBoundsCategory::SizeType(bounds),
+            (None, Some(bounds), false) => {
+                // TODO: implement
+                errors.error(
+                    unknown_bounds.remove(0),
+                    "unknown bounds with `Size` bounds are not implemented",
+                );
+                ParsedBoundsCategory::SizeType(bounds)
+            }
+            (Some(bounds), None, _) => ParsedBoundsCategory::Type(ParsedTypeBounds {
+                Unknown: unknown_bounds,
+                ..bounds
+            }),
+            (Some(type_bounds), Some(size_type_bounds), _) => {
                 errors.error(
                     size_type_bounds
                         .Size
@@ -2427,6 +2516,7 @@ impl ParsedBounds {
 pub(crate) enum ParsedBoundCategory {
     Type(ParsedTypeBound),
     SizeType(ParsedSizeTypeBound),
+    Unknown(syn::TypeParamBound),
 }
 
 impl ParsedBound {
@@ -2441,12 +2531,14 @@ impl ParsedBound {
             Self::Size(v) => ParsedBoundCategory::SizeType(ParsedSizeTypeBound::Size(v)),
             Self::StaticType(v) => ParsedBoundCategory::Type(ParsedTypeBound::StaticType(v)),
             Self::Type(v) => ParsedBoundCategory::Type(ParsedTypeBound::Type(v)),
+            Self::Unknown(v) => ParsedBoundCategory::Unknown(v),
         }
     }
     fn implied_bounds(self) -> ParsedBounds {
         match self.categorize() {
             ParsedBoundCategory::Type(v) => v.implied_bounds().into(),
             ParsedBoundCategory::SizeType(v) => v.implied_bounds().into(),
+            ParsedBoundCategory::Unknown(v) => ParsedBounds::from_iter([ParsedBound::Unknown(v)]),
         }
     }
 }
@@ -3325,7 +3417,7 @@ impl ParsedGenerics {
                                 | ParsedTypeBound::EnumType(_)
                                 | ParsedTypeBound::IntType(_)
                                 | ParsedTypeBound::ResetType(_) => {
-                                    errors.error(bound, "bound on mask type not implemented");
+                                    errors.error(bound, "bounds on mask types are not implemented");
                                 }
                                 ParsedTypeBound::StaticType(bound) => {
                                     if bounds.StaticType.is_none() {
@@ -3337,6 +3429,12 @@ impl ParsedGenerics {
                                     }
                                 }
                                 ParsedTypeBound::Type(_) => {}
+                                ParsedTypeBound::Unknown(_) => {
+                                    errors.error(
+                                        bound,
+                                        "unknown bounds on mask types are not implemented",
+                                    );
+                                }
                             }
                         }
                         bounds.add_implied_bounds();
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 49f5689..2f93fa5 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -191,10 +191,14 @@ circuit check_array_repeat:
     };
 }
 
+pub trait UnknownTrait {}
+
+impl<T: ?Sized> UnknownTrait for T {}
+
 #[hdl_module(outline_generated)]
 pub fn check_skipped_generics<T, #[hdl(skip)] U, const N: usize, #[hdl(skip)] const M: usize>(v: U)
 where
-    T: StaticType,
+    T: StaticType + UnknownTrait,
     ConstUsize<N>: KnownSize,
     U: std::fmt::Display,
 {

From 43797db36eac26681ebcf62d13465cb5557af081 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 16 Feb 2025 20:46:54 -0800
Subject: [PATCH 154/190] sort custom keywords

---
 crates/fayalite-proc-macros-impl/src/lib.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/crates/fayalite-proc-macros-impl/src/lib.rs b/crates/fayalite-proc-macros-impl/src/lib.rs
index 6ba177b..cbd5f4a 100644
--- a/crates/fayalite-proc-macros-impl/src/lib.rs
+++ b/crates/fayalite-proc-macros-impl/src/lib.rs
@@ -77,8 +77,8 @@ mod kw {
     custom_keyword!(flip);
     custom_keyword!(hdl);
     custom_keyword!(hdl_module);
-    custom_keyword!(input);
     custom_keyword!(incomplete_wire);
+    custom_keyword!(input);
     custom_keyword!(instance);
     custom_keyword!(m);
     custom_keyword!(memory);

From 3458c21f442652713f2f531f02d747d43550562c Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 16 Feb 2025 20:48:16 -0800
Subject: [PATCH 155/190] add #[hdl(cmp_eq)] to implement HdlPartialEq
 automatically

---
 .../src/hdl_bundle.rs                         |  65 +++++++++
 .../fayalite-proc-macros-impl/src/hdl_enum.rs |   5 +
 .../src/hdl_type_alias.rs                     |   5 +
 .../src/hdl_type_common.rs                    |   1 +
 crates/fayalite-proc-macros-impl/src/lib.rs   |   1 +
 crates/fayalite/src/array.rs                  |  40 +++++-
 crates/fayalite/src/bundle.rs                 |  67 +++++++--
 crates/fayalite/src/enum_.rs                  |  59 +++++++-
 crates/fayalite/tests/module.rs               | 128 +++++++++++++++++-
 9 files changed, 351 insertions(+), 20 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
index 79326e2..b0fe498 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
@@ -83,6 +83,7 @@ impl ParsedBundle {
             custom_bounds,
             no_static: _,
             no_runtime_generics: _,
+            cmp_eq: _,
         } = options.body;
         let mut fields = match fields {
             syn::Fields::Named(fields) => fields,
@@ -437,6 +438,7 @@ impl ToTokens for ParsedBundle {
             custom_bounds: _,
             no_static,
             no_runtime_generics,
+            cmp_eq,
         } = &options.body;
         let target = get_target(target, ident);
         let mut item_attrs = attrs.clone();
@@ -765,6 +767,69 @@ impl ToTokens for ParsedBundle {
             }
         }
         .to_tokens(tokens);
+        if let Some((cmp_eq,)) = cmp_eq {
+            let mut where_clause =
+                Generics::from(generics)
+                    .where_clause
+                    .unwrap_or_else(|| syn::WhereClause {
+                        where_token: Token![where](span),
+                        predicates: Punctuated::new(),
+                    });
+            let mut fields_cmp_eq = vec![];
+            let mut fields_cmp_ne = vec![];
+            for field in fields.named() {
+                let field_ident = field.ident();
+                let field_ty = field.ty();
+                where_clause
+                    .predicates
+                    .push(parse_quote_spanned! {cmp_eq.span=>
+                        #field_ty: ::fayalite::expr::ops::ExprPartialEq<#field_ty>
+                    });
+                fields_cmp_eq.push(quote_spanned! {span=>
+                    ::fayalite::expr::ops::ExprPartialEq::cmp_eq(__lhs.#field_ident, __rhs.#field_ident)
+                });
+                fields_cmp_ne.push(quote_spanned! {span=>
+                    ::fayalite::expr::ops::ExprPartialEq::cmp_ne(__lhs.#field_ident, __rhs.#field_ident)
+                });
+            }
+            let cmp_eq_body;
+            let cmp_ne_body;
+            if fields_len == 0 {
+                cmp_eq_body = quote_spanned! {span=>
+                    ::fayalite::expr::ToExpr::to_expr(&true)
+                };
+                cmp_ne_body = quote_spanned! {span=>
+                    ::fayalite::expr::ToExpr::to_expr(&false)
+                };
+            } else {
+                cmp_eq_body = quote_spanned! {span=>
+                    #(#fields_cmp_eq)&*
+                };
+                cmp_ne_body = quote_spanned! {span=>
+                    #(#fields_cmp_ne)|*
+                };
+            };
+            quote_spanned! {span=>
+                #[automatically_derived]
+                impl #impl_generics ::fayalite::expr::ops::ExprPartialEq<Self> for #target #type_generics
+                #where_clause
+                {
+                    fn cmp_eq(
+                        __lhs: ::fayalite::expr::Expr<Self>,
+                        __rhs: ::fayalite::expr::Expr<Self>,
+                    ) -> ::fayalite::expr::Expr<::fayalite::int::Bool> {
+                        #cmp_eq_body
+                    }
+                    fn cmp_ne(
+                        __lhs: ::fayalite::expr::Expr<Self>,
+                        __rhs: ::fayalite::expr::Expr<Self>,
+                    ) -> ::fayalite::expr::Expr<::fayalite::int::Bool> {
+                        #cmp_ne_body
+                    }
+                }
+            }
+            .to_tokens(tokens);
+        }
         if let (None, MaybeParsed::Parsed(generics)) = (no_static, &self.generics) {
             let static_generics = generics.clone().for_static_type();
             let (static_impl_generics, static_type_generics, static_where_clause) =
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
index 1d16177..9174566 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
@@ -155,7 +155,11 @@ impl ParsedEnum {
             custom_bounds,
             no_static: _,
             no_runtime_generics: _,
+            cmp_eq,
         } = options.body;
+        if let Some((cmp_eq,)) = cmp_eq {
+            errors.error(cmp_eq, "#[hdl(cmp_eq)] is not yet implemented for enums");
+        }
         attrs.retain(|attr| {
             if attr.path().is_ident("repr") {
                 errors.error(attr, "#[repr] is not supported on #[hdl] enums");
@@ -211,6 +215,7 @@ impl ToTokens for ParsedEnum {
             custom_bounds: _,
             no_static,
             no_runtime_generics,
+            cmp_eq: _, // TODO: implement cmp_eq for enums
         } = &options.body;
         let target = get_target(target, ident);
         let mut struct_attrs = attrs.clone();
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs
index e5d5f7b..97501e7 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs
@@ -49,10 +49,14 @@ impl ParsedTypeAlias {
             custom_bounds,
             no_static,
             no_runtime_generics: _,
+            cmp_eq,
         } = options.body;
         if let Some((no_static,)) = no_static {
             errors.error(no_static, "no_static is not valid on type aliases");
         }
+        if let Some((cmp_eq,)) = cmp_eq {
+            errors.error(cmp_eq, "cmp_eq is not valid on type aliases");
+        }
         let generics = if custom_bounds.is_some() {
             MaybeParsed::Unrecognized(generics)
         } else if let Some(generics) = errors.ok(ParsedGenerics::parse(&mut generics)) {
@@ -95,6 +99,7 @@ impl ToTokens for ParsedTypeAlias {
             custom_bounds: _,
             no_static: _,
             no_runtime_generics,
+            cmp_eq: _,
         } = &options.body;
         let target = get_target(target, ident);
         let mut type_attrs = attrs.clone();
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
index 3b2e1ec..2da0915 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs
@@ -26,6 +26,7 @@ crate::options! {
         CustomBounds(custom_bounds),
         NoStatic(no_static),
         NoRuntimeGenerics(no_runtime_generics),
+        CmpEq(cmp_eq),
     }
 }
 
diff --git a/crates/fayalite-proc-macros-impl/src/lib.rs b/crates/fayalite-proc-macros-impl/src/lib.rs
index cbd5f4a..5fe3ae8 100644
--- a/crates/fayalite-proc-macros-impl/src/lib.rs
+++ b/crates/fayalite-proc-macros-impl/src/lib.rs
@@ -72,6 +72,7 @@ mod kw {
     custom_keyword!(cfg);
     custom_keyword!(cfg_attr);
     custom_keyword!(clock_domain);
+    custom_keyword!(cmp_eq);
     custom_keyword!(connect_inexact);
     custom_keyword!(custom_bounds);
     custom_keyword!(flip);
diff --git a/crates/fayalite/src/array.rs b/crates/fayalite/src/array.rs
index f617f91..647b2e2 100644
--- a/crates/fayalite/src/array.rs
+++ b/crates/fayalite/src/array.rs
@@ -2,8 +2,11 @@
 // See Notices.txt for copyright information
 
 use crate::{
-    expr::{ops::ArrayIndex, Expr, ToExpr},
-    int::{DynSize, KnownSize, Size, SizeType, DYN_SIZE},
+    expr::{
+        ops::{ArrayIndex, ArrayLiteral, ExprPartialEq},
+        CastToBits, Expr, HdlPartialEq, ReduceBits, ToExpr,
+    },
+    int::{Bool, DynSize, KnownSize, Size, SizeType, DYN_SIZE},
     intern::{Intern, Interned, LazyInterned},
     module::transform::visit::{Fold, Folder, Visit, Visitor},
     source_location::SourceLocation,
@@ -218,3 +221,36 @@ impl<T: Type, L: SizeType> Index<L> for ArrayWithoutLen<T> {
         Interned::into_inner(Intern::intern_sized(ArrayType::new(self.element, len)))
     }
 }
+
+impl<Lhs: Type, Rhs: Type, Len: Size> ExprPartialEq<ArrayType<Rhs, Len>> for ArrayType<Lhs, Len>
+where
+    Lhs: ExprPartialEq<Rhs>,
+{
+    fn cmp_eq(lhs: Expr<Self>, rhs: Expr<ArrayType<Rhs, Len>>) -> Expr<Bool> {
+        let lhs_ty = Expr::ty(lhs);
+        let rhs_ty = Expr::ty(rhs);
+        assert_eq!(lhs_ty.len(), rhs_ty.len());
+        ArrayLiteral::<Bool, DynSize>::new(
+            Bool,
+            (0..lhs_ty.len())
+                .map(|i| Expr::canonical(lhs[i].cmp_eq(rhs[i])))
+                .collect(),
+        )
+        .cast_to_bits()
+        .all_one_bits()
+    }
+
+    fn cmp_ne(lhs: Expr<Self>, rhs: Expr<ArrayType<Rhs, Len>>) -> Expr<Bool> {
+        let lhs_ty = Expr::ty(lhs);
+        let rhs_ty = Expr::ty(rhs);
+        assert_eq!(lhs_ty.len(), rhs_ty.len());
+        ArrayLiteral::<Bool, DynSize>::new(
+            Bool,
+            (0..lhs_ty.len())
+                .map(|i| Expr::canonical(lhs[i].cmp_ne(rhs[i])))
+                .collect(),
+        )
+        .cast_to_bits()
+        .any_one_bits()
+    }
+}
diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs
index 995510e..9807b92 100644
--- a/crates/fayalite/src/bundle.rs
+++ b/crates/fayalite/src/bundle.rs
@@ -2,7 +2,11 @@
 // See Notices.txt for copyright information
 
 use crate::{
-    expr::{ops::BundleLiteral, Expr, ToExpr},
+    expr::{
+        ops::{ArrayLiteral, BundleLiteral, ExprPartialEq},
+        CastToBits, Expr, ReduceBits, ToExpr,
+    },
+    int::{Bool, DynSize},
     intern::{Intern, Interned},
     sim::{SimValue, ToSimValue},
     source_location::SourceLocation,
@@ -325,7 +329,19 @@ macro_rules! impl_tuple_builder_fields {
 }
 
 macro_rules! impl_tuples {
-    ([$({#[num = $num:literal, field = $field:ident, ty = $ty_var:ident: $Ty:ident] $var:ident: $T:ident})*] []) => {
+    (
+        [$({
+            #[
+                num = $num:tt,
+                field = $field:ident,
+                ty = $ty_var:ident: $Ty:ident,
+                lhs = $lhs_var:ident: $Lhs:ident,
+                rhs = $rhs_var:ident: $Rhs:ident
+            ]
+            $var:ident: $T:ident
+        })*]
+        []
+    ) => {
         impl_tuple_builder_fields! {
             {}
             [$({
@@ -498,6 +514,29 @@ macro_rules! impl_tuples {
                 Self::into_sim_value(*self, ty)
             }
         }
+        impl<$($Lhs: Type + ExprPartialEq<$Rhs>, $Rhs: Type,)*> ExprPartialEq<($($Rhs,)*)> for ($($Lhs,)*) {
+            fn cmp_eq(lhs: Expr<Self>, rhs: Expr<($($Rhs,)*)>) -> Expr<Bool> {
+                let ($($lhs_var,)*) = *lhs;
+                let ($($rhs_var,)*) = *rhs;
+                ArrayLiteral::<Bool, DynSize>::new(
+                    Bool,
+                    FromIterator::from_iter([$(Expr::canonical(ExprPartialEq::cmp_eq($lhs_var, $rhs_var)),)*]),
+                )
+                .cast_to_bits()
+                .all_one_bits()
+            }
+
+            fn cmp_ne(lhs: Expr<Self>, rhs: Expr<($($Rhs,)*)>) -> Expr<Bool> {
+                let ($($lhs_var,)*) = *lhs;
+                let ($($rhs_var,)*) = *rhs;
+                ArrayLiteral::<Bool, DynSize>::new(
+                    Bool,
+                    FromIterator::from_iter([$(Expr::canonical(ExprPartialEq::cmp_ne($lhs_var, $rhs_var)),)*]),
+                )
+                .cast_to_bits()
+                .any_one_bits()
+            }
+        }
     };
     ([$($lhs:tt)*] [$rhs_first:tt $($rhs:tt)*]) => {
         impl_tuples!([$($lhs)*] []);
@@ -507,18 +546,18 @@ macro_rules! impl_tuples {
 
 impl_tuples! {
     [] [
-        {#[num = 0, field = field_0, ty = ty0: Ty0] v0: T0}
-        {#[num = 1, field = field_1, ty = ty1: Ty1] v1: T1}
-        {#[num = 2, field = field_2, ty = ty2: Ty2] v2: T2}
-        {#[num = 3, field = field_3, ty = ty3: Ty3] v3: T3}
-        {#[num = 4, field = field_4, ty = ty4: Ty4] v4: T4}
-        {#[num = 5, field = field_5, ty = ty5: Ty5] v5: T5}
-        {#[num = 6, field = field_6, ty = ty6: Ty6] v6: T6}
-        {#[num = 7, field = field_7, ty = ty7: Ty7] v7: T7}
-        {#[num = 8, field = field_8, ty = ty8: Ty8] v8: T8}
-        {#[num = 9, field = field_9, ty = ty9: Ty9] v9: T9}
-        {#[num = 10, field = field_10, ty = ty10: Ty10] v10: T10}
-        {#[num = 11, field = field_11, ty = ty11: Ty11] v11: T11}
+        {#[num = 0, field = field_0, ty = ty0: Ty0, lhs = lhs0: Lhs0, rhs = rhs0: Rhs0] v0: T0}
+        {#[num = 1, field = field_1, ty = ty1: Ty1, lhs = lhs1: Lhs1, rhs = rhs1: Rhs1] v1: T1}
+        {#[num = 2, field = field_2, ty = ty2: Ty2, lhs = lhs2: Lhs2, rhs = rhs2: Rhs2] v2: T2}
+        {#[num = 3, field = field_3, ty = ty3: Ty3, lhs = lhs3: Lhs3, rhs = rhs3: Rhs3] v3: T3}
+        {#[num = 4, field = field_4, ty = ty4: Ty4, lhs = lhs4: Lhs4, rhs = rhs4: Rhs4] v4: T4}
+        {#[num = 5, field = field_5, ty = ty5: Ty5, lhs = lhs5: Lhs5, rhs = rhs5: Rhs5] v5: T5}
+        {#[num = 6, field = field_6, ty = ty6: Ty6, lhs = lhs6: Lhs6, rhs = rhs6: Rhs6] v6: T6}
+        {#[num = 7, field = field_7, ty = ty7: Ty7, lhs = lhs7: Lhs7, rhs = rhs7: Rhs7] v7: T7}
+        {#[num = 8, field = field_8, ty = ty8: Ty8, lhs = lhs8: Lhs8, rhs = rhs8: Rhs8] v8: T8}
+        {#[num = 9, field = field_9, ty = ty9: Ty9, lhs = lhs9: Lhs9, rhs = rhs9: Rhs9] v9: T9}
+        {#[num = 10, field = field_10, ty = ty10: Ty10, lhs = lhs10: Lhs10, rhs = rhs10: Rhs10] v10: T10}
+        {#[num = 11, field = field_11, ty = ty11: Ty11, lhs = lhs11: Lhs11, rhs = rhs11: Rhs11] v11: T11}
     ]
 }
 
diff --git a/crates/fayalite/src/enum_.rs b/crates/fayalite/src/enum_.rs
index 2ed0b8e..70c58c0 100644
--- a/crates/fayalite/src/enum_.rs
+++ b/crates/fayalite/src/enum_.rs
@@ -2,7 +2,10 @@
 // See Notices.txt for copyright information
 
 use crate::{
-    expr::{ops::VariantAccess, Expr, ToExpr},
+    expr::{
+        ops::{ExprPartialEq, VariantAccess},
+        Expr, ToExpr,
+    },
     hdl,
     int::Bool,
     intern::{Intern, Interned},
@@ -360,6 +363,60 @@ pub enum HdlOption<T: Type> {
     HdlSome(T),
 }
 
+impl<Lhs: Type + ExprPartialEq<Rhs>, Rhs: Type> ExprPartialEq<HdlOption<Rhs>> for HdlOption<Lhs> {
+    #[hdl]
+    fn cmp_eq(lhs: Expr<Self>, rhs: Expr<HdlOption<Rhs>>) -> Expr<Bool> {
+        #[hdl]
+        let cmp_eq = wire();
+        #[hdl]
+        match lhs {
+            HdlSome(lhs) =>
+            {
+                #[hdl]
+                match rhs {
+                    HdlSome(rhs) => connect(cmp_eq, ExprPartialEq::cmp_eq(lhs, rhs)),
+                    HdlNone => connect(cmp_eq, false),
+                }
+            }
+            HdlNone =>
+            {
+                #[hdl]
+                match rhs {
+                    HdlSome(_) => connect(cmp_eq, false),
+                    HdlNone => connect(cmp_eq, true),
+                }
+            }
+        }
+        cmp_eq
+    }
+
+    #[hdl]
+    fn cmp_ne(lhs: Expr<Self>, rhs: Expr<HdlOption<Rhs>>) -> Expr<Bool> {
+        #[hdl]
+        let cmp_ne = wire();
+        #[hdl]
+        match lhs {
+            HdlSome(lhs) =>
+            {
+                #[hdl]
+                match rhs {
+                    HdlSome(rhs) => connect(cmp_ne, ExprPartialEq::cmp_ne(lhs, rhs)),
+                    HdlNone => connect(cmp_ne, true),
+                }
+            }
+            HdlNone =>
+            {
+                #[hdl]
+                match rhs {
+                    HdlSome(_) => connect(cmp_ne, true),
+                    HdlNone => connect(cmp_ne, false),
+                }
+            }
+        }
+        cmp_ne
+    }
+}
+
 #[allow(non_snake_case)]
 pub fn HdlNone<T: StaticType>() -> Expr<HdlOption<T>> {
     HdlOption[T::TYPE].HdlNone()
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 2f93fa5..49b226a 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -380,18 +380,18 @@ circuit check_written_inside_both_if_else:
     };
 }
 
-#[hdl(outline_generated)]
+#[hdl(outline_generated, cmp_eq)]
 pub struct TestStruct<T> {
     pub a: T,
     pub b: UInt<8>,
 }
 
-#[hdl(outline_generated)]
+#[hdl(outline_generated, cmp_eq)]
 pub struct TestStruct2 {
     pub v: UInt<8>,
 }
 
-#[hdl(outline_generated)]
+#[hdl(outline_generated, cmp_eq)]
 pub struct TestStruct3 {}
 
 #[hdl_module(outline_generated)]
@@ -4425,3 +4425,125 @@ circuit check_let_patterns:
 ",
     };
 }
+
+#[hdl_module(outline_generated)]
+pub fn check_struct_cmp_eq() {
+    #[hdl]
+    let tuple_lhs: (UInt<1>, SInt<1>, Bool) = m.input();
+    #[hdl]
+    let tuple_rhs: (UInt<1>, SInt<1>, Bool) = m.input();
+    #[hdl]
+    let tuple_cmp_eq: Bool = m.output();
+    connect(tuple_cmp_eq, tuple_lhs.cmp_eq(tuple_rhs));
+    #[hdl]
+    let tuple_cmp_ne: Bool = m.output();
+    connect(tuple_cmp_ne, tuple_lhs.cmp_ne(tuple_rhs));
+
+    #[hdl]
+    let test_struct_lhs: TestStruct<SInt<8>> = m.input();
+    #[hdl]
+    let test_struct_rhs: TestStruct<SInt<8>> = m.input();
+    #[hdl]
+    let test_struct_cmp_eq: Bool = m.output();
+    connect(test_struct_cmp_eq, test_struct_lhs.cmp_eq(test_struct_rhs));
+    #[hdl]
+    let test_struct_cmp_ne: Bool = m.output();
+    connect(test_struct_cmp_ne, test_struct_lhs.cmp_ne(test_struct_rhs));
+
+    #[hdl]
+    let test_struct_2_lhs: TestStruct2 = m.input();
+    #[hdl]
+    let test_struct_2_rhs: TestStruct2 = m.input();
+    #[hdl]
+    let test_struct_2_cmp_eq: Bool = m.output();
+    connect(
+        test_struct_2_cmp_eq,
+        test_struct_2_lhs.cmp_eq(test_struct_2_rhs),
+    );
+    #[hdl]
+    let test_struct_2_cmp_ne: Bool = m.output();
+    connect(
+        test_struct_2_cmp_ne,
+        test_struct_2_lhs.cmp_ne(test_struct_2_rhs),
+    );
+
+    #[hdl]
+    let test_struct_3_lhs: TestStruct3 = m.input();
+    #[hdl]
+    let test_struct_3_rhs: TestStruct3 = m.input();
+    #[hdl]
+    let test_struct_3_cmp_eq: Bool = m.output();
+    connect(
+        test_struct_3_cmp_eq,
+        test_struct_3_lhs.cmp_eq(test_struct_3_rhs),
+    );
+    #[hdl]
+    let test_struct_3_cmp_ne: Bool = m.output();
+    connect(
+        test_struct_3_cmp_ne,
+        test_struct_3_lhs.cmp_ne(test_struct_3_rhs),
+    );
+}
+
+#[test]
+fn test_struct_cmp_eq() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_struct_cmp_eq();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_struct_cmp_eq.fir": r"FIRRTL version 3.2.0
+circuit check_struct_cmp_eq:
+    type Ty0 = {`0`: UInt<1>, `1`: SInt<1>, `2`: UInt<1>}
+    type Ty1 = {a: SInt<8>, b: UInt<8>}
+    type Ty2 = {v: UInt<8>}
+    type Ty3 = {}
+    module check_struct_cmp_eq: @[module-XXXXXXXXXX.rs 1:1]
+        input tuple_lhs: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input tuple_rhs: Ty0 @[module-XXXXXXXXXX.rs 3:1]
+        output tuple_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
+        output tuple_cmp_ne: UInt<1> @[module-XXXXXXXXXX.rs 6:1]
+        input test_struct_lhs: Ty1 @[module-XXXXXXXXXX.rs 8:1]
+        input test_struct_rhs: Ty1 @[module-XXXXXXXXXX.rs 9:1]
+        output test_struct_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 10:1]
+        output test_struct_cmp_ne: UInt<1> @[module-XXXXXXXXXX.rs 12:1]
+        input test_struct_2_lhs: Ty2 @[module-XXXXXXXXXX.rs 14:1]
+        input test_struct_2_rhs: Ty2 @[module-XXXXXXXXXX.rs 15:1]
+        output test_struct_2_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 16:1]
+        output test_struct_2_cmp_ne: UInt<1> @[module-XXXXXXXXXX.rs 18:1]
+        input test_struct_3_lhs: Ty3 @[module-XXXXXXXXXX.rs 20:1]
+        input test_struct_3_rhs: Ty3 @[module-XXXXXXXXXX.rs 21:1]
+        output test_struct_3_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 22:1]
+        output test_struct_3_cmp_ne: UInt<1> @[module-XXXXXXXXXX.rs 24:1]
+        wire _array_literal_expr: UInt<1>[3]
+        connect _array_literal_expr[0], eq(tuple_lhs.`0`, tuple_rhs.`0`)
+        connect _array_literal_expr[1], eq(tuple_lhs.`1`, tuple_rhs.`1`)
+        connect _array_literal_expr[2], eq(tuple_lhs.`2`, tuple_rhs.`2`)
+        wire _cast_array_to_bits_expr: UInt<1>[3]
+        connect _cast_array_to_bits_expr[0], _array_literal_expr[0]
+        connect _cast_array_to_bits_expr[1], _array_literal_expr[1]
+        connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
+        wire _cast_to_bits_expr: UInt<3>
+        connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
+        connect tuple_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1]
+        wire _array_literal_expr_1: UInt<1>[3]
+        connect _array_literal_expr_1[0], neq(tuple_lhs.`0`, tuple_rhs.`0`)
+        connect _array_literal_expr_1[1], neq(tuple_lhs.`1`, tuple_rhs.`1`)
+        connect _array_literal_expr_1[2], neq(tuple_lhs.`2`, tuple_rhs.`2`)
+        wire _cast_array_to_bits_expr_1: UInt<1>[3]
+        connect _cast_array_to_bits_expr_1[0], _array_literal_expr_1[0]
+        connect _cast_array_to_bits_expr_1[1], _array_literal_expr_1[1]
+        connect _cast_array_to_bits_expr_1[2], _array_literal_expr_1[2]
+        wire _cast_to_bits_expr_1: UInt<3>
+        connect _cast_to_bits_expr_1, cat(_cast_array_to_bits_expr_1[2], cat(_cast_array_to_bits_expr_1[1], _cast_array_to_bits_expr_1[0]))
+        connect tuple_cmp_ne, orr(_cast_to_bits_expr_1) @[module-XXXXXXXXXX.rs 7:1]
+        connect test_struct_cmp_eq, and(eq(test_struct_lhs.a, test_struct_rhs.a), eq(test_struct_lhs.b, test_struct_rhs.b)) @[module-XXXXXXXXXX.rs 11:1]
+        connect test_struct_cmp_ne, or(neq(test_struct_lhs.a, test_struct_rhs.a), neq(test_struct_lhs.b, test_struct_rhs.b)) @[module-XXXXXXXXXX.rs 13:1]
+        connect test_struct_2_cmp_eq, eq(test_struct_2_lhs.v, test_struct_2_rhs.v) @[module-XXXXXXXXXX.rs 17:1]
+        connect test_struct_2_cmp_ne, neq(test_struct_2_lhs.v, test_struct_2_rhs.v) @[module-XXXXXXXXXX.rs 19:1]
+        connect test_struct_3_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 23:1]
+        connect test_struct_3_cmp_ne, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 25:1]
+",
+    };
+}

From 60734cc9d170a87496c69a532a029a9ea23e48b8 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 2 Mar 2025 17:43:29 -0800
Subject: [PATCH 156/190] switch CI to use mirrors

---
 .forgejo/workflows/deps.yml | 12 ++++++------
 .forgejo/workflows/test.yml |  6 +++---
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/.forgejo/workflows/deps.yml b/.forgejo/workflows/deps.yml
index ffaca53..b29723c 100644
--- a/.forgejo/workflows/deps.yml
+++ b/.forgejo/workflows/deps.yml
@@ -12,10 +12,10 @@ jobs:
     outputs:
       cache-primary-key: ${{ steps.restore-deps.outputs.cache-primary-key }}
     steps:
-      - uses: https://code.forgejo.org/actions/checkout@v3
+      - uses: https://git.libre-chip.org/mirrors/checkout@v3
         with:
           fetch-depth: 0
-      - uses: https://code.forgejo.org/actions/cache/restore@v3
+      - uses: https://git.libre-chip.org/mirrors/cache/restore@v3
         id: restore-deps
         with:
           path: deps
@@ -58,19 +58,19 @@ jobs:
       - name: Get SymbiYosys
         if: steps.restore-deps.outputs.cache-hit != 'true'
         run: |
-          git clone --depth=1 --branch=yosys-0.45 https://github.com/YosysHQ/sby.git deps/sby
+          git clone --depth=1 --branch=yosys-0.45 https://git.libre-chip.org/mirrors/sby deps/sby
       - name: Build Z3
         if: steps.restore-deps.outputs.cache-hit != 'true'
         run: |
-          git clone --depth=1 --recursive --branch=z3-4.13.3 https://github.com/Z3Prover/z3.git deps/z3
+          git clone --depth=1 --recursive --branch=z3-4.13.3 https://git.libre-chip.org/mirrors/z3 deps/z3
           (cd deps/z3; PYTHON=python3 ./configure --prefix=/usr/local)
           make -C deps/z3/build -j"$(nproc)"
       - name: Build Yosys
         if: steps.restore-deps.outputs.cache-hit != 'true'
         run: |
-          git clone --depth=1 --recursive --branch=0.45 https://github.com/YosysHQ/yosys.git deps/yosys
+          git clone --depth=1 --recursive --branch=0.45 https://git.libre-chip.org/mirrors/yosys deps/yosys
           make -C deps/yosys -j"$(nproc)"
-      - uses: https://code.forgejo.org/actions/cache/save@v3
+      - uses: https://git.libre-chip.org/mirrors/cache/save@v3
         if: steps.restore-deps.outputs.cache-hit != 'true'
         with:
           path: deps
diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index e83c668..49fb3e4 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -9,7 +9,7 @@ jobs:
     runs-on: debian-12
     needs: deps
     steps:
-      - uses: https://code.forgejo.org/actions/checkout@v3
+      - uses: https://git.libre-chip.org/mirrors/checkout@v3
         with:
           fetch-depth: 0
       - run: |
@@ -41,7 +41,7 @@ jobs:
           curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.82.0
           source "$HOME/.cargo/env"
           echo "$PATH" >> "$GITHUB_PATH"
-      - uses: https://code.forgejo.org/actions/cache/restore@v3
+      - uses: https://git.libre-chip.org/mirrors/cache/restore@v3
         with:
           path: deps
           key: ${{ needs.deps.outputs.cache-primary-key }}
@@ -52,7 +52,7 @@ jobs:
           make -C deps/yosys install
           export PATH="$(realpath deps/firtool/bin):$PATH"
           echo "$PATH" >> "$GITHUB_PATH"
-      - uses: https://github.com/Swatinem/rust-cache@v2
+      - uses: https://git.libre-chip.org/mirrors/rust-cache@v2
         with:
           save-if: ${{ github.ref == 'refs/heads/master' }}
       - run: cargo test

From 50c86e18dc2fda0622b471ddf55a4d28f1471eeb Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 2 Mar 2025 16:11:05 -0800
Subject: [PATCH 157/190] add Expr<ArrayType<T, Len>>: IntoIterator and
 Expr<Array<T>>: FromIterator<T>

---
 crates/fayalite/src/array.rs    | 139 ++++++++++++++++++++++++++------
 crates/fayalite/src/expr/ops.rs |  44 ++++++++++
 2 files changed, 159 insertions(+), 24 deletions(-)

diff --git a/crates/fayalite/src/array.rs b/crates/fayalite/src/array.rs
index 647b2e2..0d9b63f 100644
--- a/crates/fayalite/src/array.rs
+++ b/crates/fayalite/src/array.rs
@@ -3,7 +3,7 @@
 
 use crate::{
     expr::{
-        ops::{ArrayIndex, ArrayLiteral, ExprPartialEq},
+        ops::{ArrayLiteral, ExprFromIterator, ExprIntoIterator, ExprPartialEq},
         CastToBits, Expr, HdlPartialEq, ReduceBits, ToExpr,
     },
     int::{Bool, DynSize, KnownSize, Size, SizeType, DYN_SIZE},
@@ -15,7 +15,7 @@ use crate::{
     },
     util::ConstUsize,
 };
-use std::ops::Index;
+use std::{iter::FusedIterator, ops::Index};
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash)]
 pub struct ArrayType<T: Type = CanonicalType, Len: Size = DynSize> {
@@ -151,10 +151,8 @@ impl<T: Type, Len: Size> Type for ArrayType<T, Len> {
         this: Expr<Self>,
         source_location: SourceLocation,
     ) -> Self::MatchVariantsIter {
-        let base = Expr::as_dyn_array(this);
-        let base_ty = Expr::ty(base);
         let _ = source_location;
-        let retval = Vec::from_iter((0..base_ty.len()).map(|i| ArrayIndex::new(base, i).to_expr()));
+        let retval = Vec::from_iter(this);
         std::iter::once(MatchVariantWithoutScope(
             Len::ArrayMatch::<T>::try_from(retval)
                 .ok()
@@ -187,9 +185,7 @@ impl<T: Type, Len: Size> Type for ArrayType<T, Len> {
 
 impl<T: Type, Len: Size> TypeWithDeref for ArrayType<T, Len> {
     fn expr_deref(this: &Expr<Self>) -> &Self::MatchVariant {
-        let base = Expr::as_dyn_array(*this);
-        let base_ty = Expr::ty(base);
-        let retval = Vec::from_iter((0..base_ty.len()).map(|i| ArrayIndex::new(base, i).to_expr()));
+        let retval = Vec::from_iter(*this);
         Interned::into_inner(Intern::intern_sized(
             Len::ArrayMatch::<T>::try_from(retval)
                 .ok()
@@ -230,27 +226,122 @@ where
         let lhs_ty = Expr::ty(lhs);
         let rhs_ty = Expr::ty(rhs);
         assert_eq!(lhs_ty.len(), rhs_ty.len());
-        ArrayLiteral::<Bool, DynSize>::new(
-            Bool,
-            (0..lhs_ty.len())
-                .map(|i| Expr::canonical(lhs[i].cmp_eq(rhs[i])))
-                .collect(),
-        )
-        .cast_to_bits()
-        .all_one_bits()
+        lhs.into_iter()
+            .zip(rhs)
+            .map(|(l, r)| l.cmp_eq(r))
+            .collect::<Expr<Array<Bool>>>()
+            .cast_to_bits()
+            .all_one_bits()
     }
 
     fn cmp_ne(lhs: Expr<Self>, rhs: Expr<ArrayType<Rhs, Len>>) -> Expr<Bool> {
         let lhs_ty = Expr::ty(lhs);
         let rhs_ty = Expr::ty(rhs);
         assert_eq!(lhs_ty.len(), rhs_ty.len());
-        ArrayLiteral::<Bool, DynSize>::new(
-            Bool,
-            (0..lhs_ty.len())
-                .map(|i| Expr::canonical(lhs[i].cmp_ne(rhs[i])))
-                .collect(),
-        )
-        .cast_to_bits()
-        .any_one_bits()
+        lhs.into_iter()
+            .zip(rhs)
+            .map(|(l, r)| l.cmp_ne(r))
+            .collect::<Expr<Array<Bool>>>()
+            .cast_to_bits()
+            .any_one_bits()
+    }
+}
+
+impl<T: Type, Len: Size> ExprIntoIterator for ArrayType<T, Len> {
+    type Item = T;
+    type ExprIntoIter = ExprArrayIter<T, Len>;
+
+    fn expr_into_iter(e: Expr<Self>) -> Self::ExprIntoIter {
+        ExprArrayIter {
+            base: e,
+            indexes: 0..Expr::ty(e).len(),
+        }
+    }
+}
+
+#[derive(Clone, Debug)]
+pub struct ExprArrayIter<T: Type, Len: Size> {
+    base: Expr<ArrayType<T, Len>>,
+    indexes: std::ops::Range<usize>,
+}
+
+impl<T: Type, Len: Size> ExprArrayIter<T, Len> {
+    pub fn base(&self) -> Expr<ArrayType<T, Len>> {
+        self.base
+    }
+    pub fn indexes(&self) -> std::ops::Range<usize> {
+        self.indexes.clone()
+    }
+}
+
+impl<T: Type, Len: Size> Iterator for ExprArrayIter<T, Len> {
+    type Item = Expr<T>;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        self.indexes.next().map(|i| self.base[i])
+    }
+
+    fn size_hint(&self) -> (usize, Option<usize>) {
+        self.indexes.size_hint()
+    }
+
+    fn count(self) -> usize {
+        self.indexes.count()
+    }
+
+    fn last(mut self) -> Option<Self::Item> {
+        self.next_back()
+    }
+
+    fn nth(&mut self, n: usize) -> Option<Self::Item> {
+        self.indexes.nth(n).map(|i| self.base[i])
+    }
+
+    fn fold<B, F>(self, init: B, mut f: F) -> B
+    where
+        F: FnMut(B, Self::Item) -> B,
+    {
+        self.indexes.fold(init, |b, i| f(b, self.base[i]))
+    }
+}
+
+impl<T: Type, Len: Size> DoubleEndedIterator for ExprArrayIter<T, Len> {
+    fn next_back(&mut self) -> Option<Self::Item> {
+        self.indexes.next_back().map(|i| self.base[i])
+    }
+
+    fn nth_back(&mut self, n: usize) -> Option<Self::Item> {
+        self.indexes.nth_back(n).map(|i| self.base[i])
+    }
+
+    fn rfold<B, F>(self, init: B, mut f: F) -> B
+    where
+        F: FnMut(B, Self::Item) -> B,
+    {
+        self.indexes.rfold(init, |b, i| f(b, self.base[i]))
+    }
+}
+
+impl<T: Type, Len: Size> ExactSizeIterator for ExprArrayIter<T, Len> {
+    fn len(&self) -> usize {
+        self.indexes.len()
+    }
+}
+
+impl<T: Type, Len: Size> FusedIterator for ExprArrayIter<T, Len> {}
+
+impl<A: StaticType> ExprFromIterator<Expr<A>> for Array<A> {
+    fn expr_from_iter<T: IntoIterator<Item = Expr<A>>>(iter: T) -> Expr<Self> {
+        ArrayLiteral::new(
+            A::TYPE,
+            iter.into_iter().map(|v| Expr::canonical(v)).collect(),
+        )
+        .to_expr()
+    }
+}
+
+impl<'a, A: StaticType> ExprFromIterator<&'a Expr<A>> for Array<A> {
+    fn expr_from_iter<T: IntoIterator<Item = &'a Expr<A>>>(iter: T) -> Expr<Self> {
+        iter.into_iter().copied().collect()
     }
 }
diff --git a/crates/fayalite/src/expr/ops.rs b/crates/fayalite/src/expr/ops.rs
index 15c195e..c502fd5 100644
--- a/crates/fayalite/src/expr/ops.rs
+++ b/crates/fayalite/src/expr/ops.rs
@@ -2708,3 +2708,47 @@ impl<T: Type> ToExpr for Uninit<T> {
         }
     }
 }
+
+pub trait ExprIntoIterator: Type {
+    type Item: Type;
+    type ExprIntoIter: Iterator<Item = Expr<Self::Item>>;
+
+    fn expr_into_iter(e: Expr<Self>) -> Self::ExprIntoIter;
+}
+
+impl<T: ExprIntoIterator> IntoIterator for Expr<T> {
+    type Item = Expr<T::Item>;
+    type IntoIter = T::ExprIntoIter;
+
+    fn into_iter(self) -> Self::IntoIter {
+        T::expr_into_iter(self)
+    }
+}
+
+impl<T: ExprIntoIterator> IntoIterator for &'_ Expr<T> {
+    type Item = Expr<T::Item>;
+    type IntoIter = T::ExprIntoIter;
+
+    fn into_iter(self) -> Self::IntoIter {
+        T::expr_into_iter(*self)
+    }
+}
+
+impl<T: ExprIntoIterator> IntoIterator for &'_ mut Expr<T> {
+    type Item = Expr<T::Item>;
+    type IntoIter = T::ExprIntoIter;
+
+    fn into_iter(self) -> Self::IntoIter {
+        T::expr_into_iter(*self)
+    }
+}
+
+pub trait ExprFromIterator<A>: Type {
+    fn expr_from_iter<T: IntoIterator<Item = A>>(iter: T) -> Expr<Self>;
+}
+
+impl<This: ExprFromIterator<A>, A> FromIterator<A> for Expr<This> {
+    fn from_iter<T: IntoIterator<Item = A>>(iter: T) -> Self {
+        This::expr_from_iter(iter)
+    }
+}

From bd75fdfefd642f6dd2210cfb003fa63f9dce114e Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 2 Mar 2025 23:04:17 -0800
Subject: [PATCH 158/190] add efficient prefix-sums and reductions

---
 crates/fayalite/src/util.rs            |   1 +
 crates/fayalite/src/util/prefix_sum.rs | 839 +++++++++++++++++++++++++
 2 files changed, 840 insertions(+)
 create mode 100644 crates/fayalite/src/util/prefix_sum.rs

diff --git a/crates/fayalite/src/util.rs b/crates/fayalite/src/util.rs
index fadc7af..66fc921 100644
--- a/crates/fayalite/src/util.rs
+++ b/crates/fayalite/src/util.rs
@@ -29,4 +29,5 @@ pub use misc::{
 };
 
 pub mod job_server;
+pub mod prefix_sum;
 pub mod ready_valid;
diff --git a/crates/fayalite/src/util/prefix_sum.rs b/crates/fayalite/src/util/prefix_sum.rs
new file mode 100644
index 0000000..758d89c
--- /dev/null
+++ b/crates/fayalite/src/util/prefix_sum.rs
@@ -0,0 +1,839 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+// code derived from:
+// https://web.archive.org/web/20250303054010/https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/prefix_sum.py;hb=effeb28e5848392adddcdad1f6e7a098f2a44c9c
+
+use crate::intern::{Intern, Interned, Memoize};
+use std::{borrow::Cow, num::NonZeroUsize};
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
+pub struct PrefixSumOp {
+    pub lhs_index: usize,
+    pub rhs_and_dest_index: NonZeroUsize,
+    pub row: u32,
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+#[non_exhaustive]
+pub struct DiagramConfig {
+    pub space: Cow<'static, str>,
+    pub vertical_bar: Cow<'static, str>,
+    pub plus: Cow<'static, str>,
+    pub slant: Cow<'static, str>,
+    pub connect: Cow<'static, str>,
+    pub no_connect: Cow<'static, str>,
+    pub padding: usize,
+}
+
+impl DiagramConfig {
+    pub const fn new() -> Self {
+        Self {
+            space: Cow::Borrowed(" "),
+            vertical_bar: Cow::Borrowed("|"),
+            plus: Cow::Borrowed("\u{2295}"), // ⊕
+            slant: Cow::Borrowed(r"\"),
+            connect: Cow::Borrowed("\u{25CF}"), // ●
+            no_connect: Cow::Borrowed("X"),
+            padding: 1,
+        }
+    }
+    pub fn draw(self, ops: impl IntoIterator<Item = PrefixSumOp>, item_count: usize) -> String {
+        #[derive(Copy, Clone, Debug)]
+        struct DiagramCell {
+            slant: bool,
+            plus: bool,
+            tee: bool,
+        }
+        let mut ops_by_row: Vec<Vec<PrefixSumOp>> = Vec::new();
+        let mut last_row = 0;
+        ops.into_iter().for_each(|op| {
+            assert!(
+                op.lhs_index < op.rhs_and_dest_index.get(),
+                "invalid PrefixSumOp! lhs_index must be less \
+                than rhs_and_dest_index: {op:?}",
+            );
+            assert!(
+                op.row >= last_row,
+                "invalid PrefixSumOp! row must \
+                not decrease (row last was: {last_row}): {op:?}",
+            );
+            let ops = if op.row > last_row || ops_by_row.is_empty() {
+                ops_by_row.push(vec![]);
+                ops_by_row.last_mut().expect("just pushed")
+            } else {
+                ops_by_row
+                    .last_mut()
+                    .expect("just checked if ops_by_row is empty")
+            };
+            if let Some(last) = ops.last() {
+                assert!(
+                    op.rhs_and_dest_index < last.rhs_and_dest_index,
+                    "invalid PrefixSumOp! rhs_and_dest_index must strictly \
+                    decrease in a row:\nthis op: {op:?}\nlast op: {last:?}",
+                );
+            }
+            ops.push(op);
+            last_row = op.row;
+        });
+        let blank_row = || {
+            vec![
+                DiagramCell {
+                    slant: false,
+                    plus: false,
+                    tee: false
+                };
+                item_count
+            ]
+        };
+        let mut cells = vec![blank_row()];
+        for ops in ops_by_row {
+            let max_distance = ops
+                .iter()
+                .map(
+                    |&PrefixSumOp {
+                         lhs_index,
+                         rhs_and_dest_index,
+                         ..
+                     }| { rhs_and_dest_index.get() - lhs_index },
+                )
+                .max()
+                .expect("ops is known to be non-empty");
+            cells.extend((0..max_distance).map(|_| blank_row()));
+            for op in ops {
+                let mut y = cells.len() - 1;
+                assert!(
+                    op.rhs_and_dest_index.get() < item_count,
+                    "invalid PrefixSumOp! rhs_and_dest_index must be \
+                    less than item_count ({item_count}): {op:?}",
+                );
+                let mut x = op.rhs_and_dest_index.get();
+                cells[y][x].plus = true;
+                x -= 1;
+                y -= 1;
+                while op.lhs_index < x {
+                    cells[y][x].slant = true;
+                    x -= 1;
+                    y -= 1;
+                }
+                cells[y][x].tee = true;
+            }
+        }
+        let mut retval = String::new();
+        let mut row_text = vec![String::new(); 2 * self.padding + 1];
+        for cells_row in cells {
+            for cell in cells_row {
+                // top padding
+                for y in 0..self.padding {
+                    // top left padding
+                    for x in 0..self.padding {
+                        row_text[y] += if x == y && (cell.plus || cell.slant) {
+                            &self.slant
+                        } else {
+                            &self.space
+                        };
+                    }
+                    // top vertical bar
+                    row_text[y] += &self.vertical_bar;
+                    // top right padding
+                    for _ in 0..self.padding {
+                        row_text[y] += &self.space;
+                    }
+                }
+                // center left padding
+                for _ in 0..self.padding {
+                    row_text[self.padding] += &self.space;
+                }
+                // center
+                row_text[self.padding] += if cell.plus {
+                    &self.plus
+                } else if cell.tee {
+                    &self.connect
+                } else if cell.slant {
+                    &self.no_connect
+                } else {
+                    &self.vertical_bar
+                };
+                // center right padding
+                for _ in 0..self.padding {
+                    row_text[self.padding] += &self.space;
+                }
+                let bottom_padding_start = self.padding + 1;
+                let bottom_padding_last = self.padding * 2;
+                // bottom padding
+                for y in bottom_padding_start..=bottom_padding_last {
+                    // bottom left padding
+                    for _ in 0..self.padding {
+                        row_text[y] += &self.space;
+                    }
+                    // bottom vertical bar
+                    row_text[y] += &self.vertical_bar;
+                    // bottom right padding
+                    for x in bottom_padding_start..=bottom_padding_last {
+                        row_text[y] += if x == y && (cell.tee || cell.slant) {
+                            &self.slant
+                        } else {
+                            &self.space
+                        };
+                    }
+                }
+            }
+            for line in &mut row_text {
+                retval += line.trim_end();
+                retval += "\n";
+                line.clear();
+            }
+        }
+        retval
+    }
+}
+
+impl Default for DiagramConfig {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+impl PrefixSumOp {
+    pub fn diagram(ops: impl IntoIterator<Item = Self>, item_count: usize) -> String {
+        Self::diagram_with_config(ops, item_count, DiagramConfig::new())
+    }
+    pub fn diagram_with_config(
+        ops: impl IntoIterator<Item = Self>,
+        item_count: usize,
+        config: DiagramConfig,
+    ) -> String {
+        config.draw(ops, item_count)
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+pub enum PrefixSumAlgorithm {
+    /// Uses the algorithm from:
+    /// https://en.wikipedia.org/wiki/Prefix_sum#Algorithm_1:_Shorter_span,_more_parallel
+    LowLatency,
+    /// Uses the algorithm from:
+    /// https://en.wikipedia.org/wiki/Prefix_sum#Algorithm_2:_Work-efficient
+    WorkEfficient,
+}
+
+impl PrefixSumAlgorithm {
+    fn ops_impl(self, item_count: usize) -> Vec<PrefixSumOp> {
+        let mut retval = Vec::new();
+        let mut distance = 1;
+        let mut row = 0;
+        while distance < item_count {
+            let double_distance = distance
+                .checked_mul(2)
+                .expect("prefix-sum item_count is too big");
+            let (start, step) = match self {
+                Self::LowLatency => (distance, 1),
+                Self::WorkEfficient => (double_distance - 1, double_distance),
+            };
+            for rhs_and_dest_index in (start..item_count).step_by(step).rev() {
+                let Some(rhs_and_dest_index) = NonZeroUsize::new(rhs_and_dest_index) else {
+                    unreachable!();
+                };
+                let lhs_index = rhs_and_dest_index.get() - distance;
+                retval.push(PrefixSumOp {
+                    lhs_index,
+                    rhs_and_dest_index,
+                    row,
+                });
+            }
+            distance = double_distance;
+            row += 1;
+        }
+        match self {
+            Self::LowLatency => {}
+            Self::WorkEfficient => {
+                distance /= 2;
+                while distance >= 1 {
+                    let start = distance
+                        .checked_mul(3)
+                        .expect("prefix-sum item_count is too big")
+                        - 1;
+                    for rhs_and_dest_index in (start..item_count).step_by(distance * 2).rev() {
+                        let Some(rhs_and_dest_index) = NonZeroUsize::new(rhs_and_dest_index) else {
+                            unreachable!();
+                        };
+                        let lhs_index = rhs_and_dest_index.get() - distance;
+                        retval.push(PrefixSumOp {
+                            lhs_index,
+                            rhs_and_dest_index,
+                            row,
+                        });
+                    }
+                    row += 1;
+                    distance /= 2;
+                }
+            }
+        }
+        retval
+    }
+    pub fn ops(self, item_count: usize) -> Interned<[PrefixSumOp]> {
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        struct MyMemoize(PrefixSumAlgorithm);
+        impl Memoize for MyMemoize {
+            type Input = usize;
+            type InputOwned = usize;
+            type Output = Interned<[PrefixSumOp]>;
+
+            fn inner(self, item_count: &Self::Input) -> Self::Output {
+                Intern::intern_owned(self.0.ops_impl(*item_count))
+            }
+        }
+        MyMemoize(self).get_owned(item_count)
+    }
+    pub fn run<T>(self, items: impl IntoIterator<Item = T>, f: impl FnMut(&T, &T) -> T) -> Vec<T> {
+        let mut items = Vec::from_iter(items);
+        self.run_on_slice(&mut items, f);
+        items
+    }
+    pub fn run_on_slice<T>(self, items: &mut [T], mut f: impl FnMut(&T, &T) -> T) -> &mut [T] {
+        self.ops(items.len()).into_iter().for_each(
+            |PrefixSumOp {
+                 lhs_index,
+                 rhs_and_dest_index,
+                 row: _,
+             }| {
+                items[rhs_and_dest_index.get()] =
+                    f(&items[lhs_index], &items[rhs_and_dest_index.get()]);
+            },
+        );
+        items
+    }
+    pub fn filtered_ops(
+        self,
+        item_live_out_flags: impl IntoIterator<Item = bool>,
+    ) -> Vec<PrefixSumOp> {
+        let mut item_live_out_flags = Vec::from_iter(item_live_out_flags);
+        let prefix_sum_ops = self.ops(item_live_out_flags.len());
+        let mut ops_live_flags = vec![false; prefix_sum_ops.len()];
+        for (
+            op_index,
+            &PrefixSumOp {
+                lhs_index,
+                rhs_and_dest_index,
+                row: _,
+            },
+        ) in prefix_sum_ops.iter().enumerate().rev()
+        {
+            let live = item_live_out_flags[rhs_and_dest_index.get()];
+            item_live_out_flags[lhs_index] |= live;
+            ops_live_flags[op_index] = live;
+        }
+        prefix_sum_ops
+            .into_iter()
+            .zip(ops_live_flags)
+            .filter_map(|(op, live)| live.then_some(op))
+            .collect()
+    }
+    pub fn reduce_ops(self, item_count: usize) -> Interned<[PrefixSumOp]> {
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        struct MyMemoize(PrefixSumAlgorithm);
+        impl Memoize for MyMemoize {
+            type Input = usize;
+            type InputOwned = usize;
+            type Output = Interned<[PrefixSumOp]>;
+
+            fn inner(self, item_count: &Self::Input) -> Self::Output {
+                let mut item_live_out_flags = vec![false; *item_count];
+                let Some(last_item_live_out_flag) = item_live_out_flags.last_mut() else {
+                    return Interned::default();
+                };
+                *last_item_live_out_flag = true;
+                Intern::intern_owned(self.0.filtered_ops(item_live_out_flags))
+            }
+        }
+        MyMemoize(self).get_owned(item_count)
+    }
+}
+
+pub fn reduce_ops(item_count: usize) -> Interned<[PrefixSumOp]> {
+    PrefixSumAlgorithm::LowLatency.reduce_ops(item_count)
+}
+
+pub fn reduce<T>(items: impl IntoIterator<Item = T>, mut f: impl FnMut(T, T) -> T) -> Option<T> {
+    let mut items: Vec<_> = items.into_iter().map(Some).collect();
+    for op in reduce_ops(items.len()) {
+        let (Some(lhs), Some(rhs)) = (
+            items[op.lhs_index].take(),
+            items[op.rhs_and_dest_index.get()].take(),
+        ) else {
+            unreachable!();
+        };
+        items[op.rhs_and_dest_index.get()] = Some(f(lhs, rhs));
+    }
+    items.last_mut().and_then(Option::take)
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    fn input_strings() -> [String; 9] {
+        std::array::from_fn(|i| String::from_utf8(vec![b'a' + i as u8]).unwrap())
+    }
+
+    #[test]
+    fn test_prefix_sum_strings() {
+        let input = input_strings();
+        let expected: Vec<String> = input
+            .iter()
+            .scan(String::new(), |l, r| {
+                *l += r;
+                Some(l.clone())
+            })
+            .collect();
+        println!("expected: {expected:?}");
+        assert_eq!(
+            *PrefixSumAlgorithm::WorkEfficient
+                .run_on_slice(&mut input.clone(), |l, r| l.to_string() + r),
+            *expected
+        );
+        assert_eq!(
+            *PrefixSumAlgorithm::LowLatency
+                .run_on_slice(&mut input.clone(), |l, r| l.to_string() + r),
+            *expected
+        );
+    }
+
+    #[test]
+    fn test_reduce_string() {
+        let input = input_strings();
+        let expected = input.clone().into_iter().reduce(|l, r| l + &r);
+        assert_eq!(reduce(input, |l, r| l + &r), expected);
+    }
+
+    fn op(lhs_index: usize, rhs_and_dest_index: usize, row: u32) -> PrefixSumOp {
+        PrefixSumOp {
+            lhs_index,
+            rhs_and_dest_index: NonZeroUsize::new(rhs_and_dest_index).expect("should be non-zero"),
+            row,
+        }
+    }
+
+    #[test]
+    fn test_reduce_ops_9() {
+        let expected = vec![
+            op(7, 8, 0),
+            op(5, 6, 0),
+            op(3, 4, 0),
+            op(1, 2, 0),
+            op(6, 8, 1),
+            op(2, 4, 1),
+            op(4, 8, 2),
+            op(0, 8, 3),
+        ];
+        println!("expected: {expected:#?}");
+        let ops = reduce_ops(9);
+        println!("ops: {ops:#?}");
+        assert_eq!(*ops, *expected);
+    }
+
+    #[test]
+    fn test_reduce_ops_8() {
+        let expected = vec![
+            op(6, 7, 0),
+            op(4, 5, 0),
+            op(2, 3, 0),
+            op(0, 1, 0),
+            op(5, 7, 1),
+            op(1, 3, 1),
+            op(3, 7, 2),
+        ];
+        println!("expected: {expected:#?}");
+        let ops = reduce_ops(8);
+        println!("ops: {ops:#?}");
+        assert_eq!(*ops, *expected);
+    }
+
+    #[test]
+    fn test_count_ones() {
+        for width in 0..=10u32 {
+            for v in 0..1u32 << width {
+                let expected = v.count_ones();
+                assert_eq!(
+                    reduce((0..width).map(|i| (v >> i) & 1), |l, r| l + r).unwrap_or(0),
+                    expected,
+                    "v={v:#X}"
+                );
+            }
+        }
+    }
+
+    #[track_caller]
+    fn test_diagram(ops: impl IntoIterator<Item = PrefixSumOp>, item_count: usize, expected: &str) {
+        let text = PrefixSumOp::diagram_with_config(
+            ops,
+            item_count,
+            DiagramConfig {
+                plus: Cow::Borrowed("@"),
+                ..Default::default()
+            },
+        );
+        println!("text:\n{text}\n");
+        assert_eq!(text, expected);
+    }
+
+    #[test]
+    fn test_work_efficient_diagram_16() {
+        let item_count = 16;
+        test_diagram(
+            PrefixSumAlgorithm::WorkEfficient.ops(item_count),
+            item_count,
+            &r"
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
+ ●  |  ●  |  ●  |  ●  |  ●  |  ●  |  ●  |  ●  |
+ |\ |  |\ |  |\ |  |\ |  |\ |  |\ |  |\ |  |\ |
+ | \|  | \|  | \|  | \|  | \|  | \|  | \|  | \|
+ |  @  |  @  |  @  |  @  |  @  |  @  |  @  |  @
+ |  |\ |  |  |  |\ |  |  |  |\ |  |  |  |\ |  |
+ |  | \|  |  |  | \|  |  |  | \|  |  |  | \|  |
+ |  |  X  |  |  |  X  |  |  |  X  |  |  |  X  |
+ |  |  |\ |  |  |  |\ |  |  |  |\ |  |  |  |\ |
+ |  |  | \|  |  |  | \|  |  |  | \|  |  |  | \|
+ |  |  |  @  |  |  |  @  |  |  |  @  |  |  |  @
+ |  |  |  |\ |  |  |  |  |  |  |  |\ |  |  |  |
+ |  |  |  | \|  |  |  |  |  |  |  | \|  |  |  |
+ |  |  |  |  X  |  |  |  |  |  |  |  X  |  |  |
+ |  |  |  |  |\ |  |  |  |  |  |  |  |\ |  |  |
+ |  |  |  |  | \|  |  |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  X  |  |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |\ |  |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  | \|  |  |  |  |  |  |  | \|  |
+ |  |  |  |  |  |  X  |  |  |  |  |  |  |  X  |
+ |  |  |  |  |  |  |\ |  |  |  |  |  |  |  |\ |
+ |  |  |  |  |  |  | \|  |  |  |  |  |  |  | \|
+ |  |  |  |  |  |  |  @  |  |  |  |  |  |  |  @
+ |  |  |  |  |  |  |  |\ |  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  | \|  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  X  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |\ |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  | \|  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  X  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |\ |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  | \|  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  X  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |\ |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  | \|  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  X  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |\ |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  | \|  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  X  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |\ |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  | \|  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  X  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |\ |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  | \|
+ |  |  |  |  |  |  |  ●  |  |  |  |  |  |  |  @
+ |  |  |  |  |  |  |  |\ |  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  | \|  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  X  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |\ |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  | \|  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  X  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |\ |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  | \|  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  X  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |\ |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  | \|  |  |  |  |
+ |  |  |  ●  |  |  |  ●  |  |  |  @  |  |  |  |
+ |  |  |  |\ |  |  |  |\ |  |  |  |\ |  |  |  |
+ |  |  |  | \|  |  |  | \|  |  |  | \|  |  |  |
+ |  |  |  |  X  |  |  |  X  |  |  |  X  |  |  |
+ |  |  |  |  |\ |  |  |  |\ |  |  |  |\ |  |  |
+ |  |  |  |  | \|  |  |  | \|  |  |  | \|  |  |
+ |  ●  |  ●  |  @  |  ●  |  @  |  ●  |  @  |  |
+ |  |\ |  |\ |  |\ |  |\ |  |\ |  |\ |  |\ |  |
+ |  | \|  | \|  | \|  | \|  | \|  | \|  | \|  |
+ |  |  @  |  @  |  @  |  @  |  @  |  @  |  @  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
+"[1..], // trim newline at start
+        );
+    }
+
+    #[test]
+    fn test_low_latency_diagram_16() {
+        let item_count = 16;
+        test_diagram(
+            PrefixSumAlgorithm::LowLatency.ops(item_count),
+            item_count,
+            &r"
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
+ ●  ●  ●  ●  ●  ●  ●  ●  ●  ●  ●  ●  ●  ●  ●  |
+ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |
+ | \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|
+ ●  @  @  @  @  @  @  @  @  @  @  @  @  @  @  @
+ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |  |
+ | \| \| \| \| \| \| \| \| \| \| \| \| \| \|  |
+ |  X  X  X  X  X  X  X  X  X  X  X  X  X  X  |
+ |  |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |
+ |  | \| \| \| \| \| \| \| \| \| \| \| \| \| \|
+ ●  ●  @  @  @  @  @  @  @  @  @  @  @  @  @  @
+ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |  |  |  |
+ | \| \| \| \| \| \| \| \| \| \| \| \|  |  |  |
+ |  X  X  X  X  X  X  X  X  X  X  X  X  |  |  |
+ |  |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |  |  |
+ |  | \| \| \| \| \| \| \| \| \| \| \| \|  |  |
+ |  |  X  X  X  X  X  X  X  X  X  X  X  X  |  |
+ |  |  |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |  |
+ |  |  | \| \| \| \| \| \| \| \| \| \| \| \|  |
+ |  |  |  X  X  X  X  X  X  X  X  X  X  X  X  |
+ |  |  |  |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |\ |
+ |  |  |  | \| \| \| \| \| \| \| \| \| \| \| \|
+ ●  ●  ●  ●  @  @  @  @  @  @  @  @  @  @  @  @
+ |\ |\ |\ |\ |\ |\ |\ |\ |  |  |  |  |  |  |  |
+ | \| \| \| \| \| \| \| \|  |  |  |  |  |  |  |
+ |  X  X  X  X  X  X  X  X  |  |  |  |  |  |  |
+ |  |\ |\ |\ |\ |\ |\ |\ |\ |  |  |  |  |  |  |
+ |  | \| \| \| \| \| \| \| \|  |  |  |  |  |  |
+ |  |  X  X  X  X  X  X  X  X  |  |  |  |  |  |
+ |  |  |\ |\ |\ |\ |\ |\ |\ |\ |  |  |  |  |  |
+ |  |  | \| \| \| \| \| \| \| \|  |  |  |  |  |
+ |  |  |  X  X  X  X  X  X  X  X  |  |  |  |  |
+ |  |  |  |\ |\ |\ |\ |\ |\ |\ |\ |  |  |  |  |
+ |  |  |  | \| \| \| \| \| \| \| \|  |  |  |  |
+ |  |  |  |  X  X  X  X  X  X  X  X  |  |  |  |
+ |  |  |  |  |\ |\ |\ |\ |\ |\ |\ |\ |  |  |  |
+ |  |  |  |  | \| \| \| \| \| \| \| \|  |  |  |
+ |  |  |  |  |  X  X  X  X  X  X  X  X  |  |  |
+ |  |  |  |  |  |\ |\ |\ |\ |\ |\ |\ |\ |  |  |
+ |  |  |  |  |  | \| \| \| \| \| \| \| \|  |  |
+ |  |  |  |  |  |  X  X  X  X  X  X  X  X  |  |
+ |  |  |  |  |  |  |\ |\ |\ |\ |\ |\ |\ |\ |  |
+ |  |  |  |  |  |  | \| \| \| \| \| \| \| \|  |
+ |  |  |  |  |  |  |  X  X  X  X  X  X  X  X  |
+ |  |  |  |  |  |  |  |\ |\ |\ |\ |\ |\ |\ |\ |
+ |  |  |  |  |  |  |  | \| \| \| \| \| \| \| \|
+ |  |  |  |  |  |  |  |  @  @  @  @  @  @  @  @
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
+"[1..], // trim newline at start
+        );
+    }
+
+    #[test]
+    fn test_work_efficient_diagram_9() {
+        let item_count = 9;
+        test_diagram(
+            PrefixSumAlgorithm::WorkEfficient.ops(item_count),
+            item_count,
+            &r"
+ |  |  |  |  |  |  |  |  |
+ ●  |  ●  |  ●  |  ●  |  |
+ |\ |  |\ |  |\ |  |\ |  |
+ | \|  | \|  | \|  | \|  |
+ |  @  |  @  |  @  |  @  |
+ |  |\ |  |  |  |\ |  |  |
+ |  | \|  |  |  | \|  |  |
+ |  |  X  |  |  |  X  |  |
+ |  |  |\ |  |  |  |\ |  |
+ |  |  | \|  |  |  | \|  |
+ |  |  |  @  |  |  |  @  |
+ |  |  |  |\ |  |  |  |  |
+ |  |  |  | \|  |  |  |  |
+ |  |  |  |  X  |  |  |  |
+ |  |  |  |  |\ |  |  |  |
+ |  |  |  |  | \|  |  |  |
+ |  |  |  |  |  X  |  |  |
+ |  |  |  |  |  |\ |  |  |
+ |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  |  | \|  |
+ |  |  |  ●  |  |  |  @  |
+ |  |  |  |\ |  |  |  |  |
+ |  |  |  | \|  |  |  |  |
+ |  |  |  |  X  |  |  |  |
+ |  |  |  |  |\ |  |  |  |
+ |  |  |  |  | \|  |  |  |
+ |  ●  |  ●  |  @  |  ●  |
+ |  |\ |  |\ |  |\ |  |\ |
+ |  | \|  | \|  | \|  | \|
+ |  |  @  |  @  |  @  |  @
+ |  |  |  |  |  |  |  |  |
+"[1..], // trim newline at start
+        );
+    }
+
+    #[test]
+    fn test_low_latency_diagram_9() {
+        let item_count = 9;
+        test_diagram(
+            PrefixSumAlgorithm::LowLatency.ops(item_count),
+            item_count,
+            &r"
+ |  |  |  |  |  |  |  |  |
+ ●  ●  ●  ●  ●  ●  ●  ●  |
+ |\ |\ |\ |\ |\ |\ |\ |\ |
+ | \| \| \| \| \| \| \| \|
+ ●  @  @  @  @  @  @  @  @
+ |\ |\ |\ |\ |\ |\ |\ |  |
+ | \| \| \| \| \| \| \|  |
+ |  X  X  X  X  X  X  X  |
+ |  |\ |\ |\ |\ |\ |\ |\ |
+ |  | \| \| \| \| \| \| \|
+ ●  ●  @  @  @  @  @  @  @
+ |\ |\ |\ |\ |\ |  |  |  |
+ | \| \| \| \| \|  |  |  |
+ |  X  X  X  X  X  |  |  |
+ |  |\ |\ |\ |\ |\ |  |  |
+ |  | \| \| \| \| \|  |  |
+ |  |  X  X  X  X  X  |  |
+ |  |  |\ |\ |\ |\ |\ |  |
+ |  |  | \| \| \| \| \|  |
+ |  |  |  X  X  X  X  X  |
+ |  |  |  |\ |\ |\ |\ |\ |
+ |  |  |  | \| \| \| \| \|
+ ●  |  |  |  @  @  @  @  @
+ |\ |  |  |  |  |  |  |  |
+ | \|  |  |  |  |  |  |  |
+ |  X  |  |  |  |  |  |  |
+ |  |\ |  |  |  |  |  |  |
+ |  | \|  |  |  |  |  |  |
+ |  |  X  |  |  |  |  |  |
+ |  |  |\ |  |  |  |  |  |
+ |  |  | \|  |  |  |  |  |
+ |  |  |  X  |  |  |  |  |
+ |  |  |  |\ |  |  |  |  |
+ |  |  |  | \|  |  |  |  |
+ |  |  |  |  X  |  |  |  |
+ |  |  |  |  |\ |  |  |  |
+ |  |  |  |  | \|  |  |  |
+ |  |  |  |  |  X  |  |  |
+ |  |  |  |  |  |\ |  |  |
+ |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  |  | \|  |
+ |  |  |  |  |  |  |  X  |
+ |  |  |  |  |  |  |  |\ |
+ |  |  |  |  |  |  |  | \|
+ |  |  |  |  |  |  |  |  @
+ |  |  |  |  |  |  |  |  |
+"[1..], // trim newline at start
+        );
+    }
+
+    #[test]
+    fn test_reduce_diagram_16() {
+        let item_count = 16;
+        test_diagram(
+            reduce_ops(item_count),
+            item_count,
+            &r"
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
+ ●  |  ●  |  ●  |  ●  |  ●  |  ●  |  ●  |  ●  |
+ |\ |  |\ |  |\ |  |\ |  |\ |  |\ |  |\ |  |\ |
+ | \|  | \|  | \|  | \|  | \|  | \|  | \|  | \|
+ |  @  |  @  |  @  |  @  |  @  |  @  |  @  |  @
+ |  |\ |  |  |  |\ |  |  |  |\ |  |  |  |\ |  |
+ |  | \|  |  |  | \|  |  |  | \|  |  |  | \|  |
+ |  |  X  |  |  |  X  |  |  |  X  |  |  |  X  |
+ |  |  |\ |  |  |  |\ |  |  |  |\ |  |  |  |\ |
+ |  |  | \|  |  |  | \|  |  |  | \|  |  |  | \|
+ |  |  |  @  |  |  |  @  |  |  |  @  |  |  |  @
+ |  |  |  |\ |  |  |  |  |  |  |  |\ |  |  |  |
+ |  |  |  | \|  |  |  |  |  |  |  | \|  |  |  |
+ |  |  |  |  X  |  |  |  |  |  |  |  X  |  |  |
+ |  |  |  |  |\ |  |  |  |  |  |  |  |\ |  |  |
+ |  |  |  |  | \|  |  |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  X  |  |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |\ |  |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  | \|  |  |  |  |  |  |  | \|  |
+ |  |  |  |  |  |  X  |  |  |  |  |  |  |  X  |
+ |  |  |  |  |  |  |\ |  |  |  |  |  |  |  |\ |
+ |  |  |  |  |  |  | \|  |  |  |  |  |  |  | \|
+ |  |  |  |  |  |  |  @  |  |  |  |  |  |  |  @
+ |  |  |  |  |  |  |  |\ |  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  | \|  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  X  |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |\ |  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  | \|  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  X  |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |\ |  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  | \|  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  X  |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |\ |  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  | \|  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  X  |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |\ |  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  | \|  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  X  |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |\ |  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  | \|  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  X  |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |\ |
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  | \|
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  @
+ |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
+"[1..], // trim newline at start
+        );
+    }
+
+    #[test]
+    fn test_reduce_diagram_9() {
+        let item_count = 9;
+        test_diagram(
+            reduce_ops(item_count),
+            item_count,
+            &r"
+ |  |  |  |  |  |  |  |  |
+ |  ●  |  ●  |  ●  |  ●  |
+ |  |\ |  |\ |  |\ |  |\ |
+ |  | \|  | \|  | \|  | \|
+ |  |  @  |  @  |  @  |  @
+ |  |  |\ |  |  |  |\ |  |
+ |  |  | \|  |  |  | \|  |
+ |  |  |  X  |  |  |  X  |
+ |  |  |  |\ |  |  |  |\ |
+ |  |  |  | \|  |  |  | \|
+ |  |  |  |  @  |  |  |  @
+ |  |  |  |  |\ |  |  |  |
+ |  |  |  |  | \|  |  |  |
+ |  |  |  |  |  X  |  |  |
+ |  |  |  |  |  |\ |  |  |
+ |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  |  | \|  |
+ |  |  |  |  |  |  |  X  |
+ |  |  |  |  |  |  |  |\ |
+ |  |  |  |  |  |  |  | \|
+ ●  |  |  |  |  |  |  |  @
+ |\ |  |  |  |  |  |  |  |
+ | \|  |  |  |  |  |  |  |
+ |  X  |  |  |  |  |  |  |
+ |  |\ |  |  |  |  |  |  |
+ |  | \|  |  |  |  |  |  |
+ |  |  X  |  |  |  |  |  |
+ |  |  |\ |  |  |  |  |  |
+ |  |  | \|  |  |  |  |  |
+ |  |  |  X  |  |  |  |  |
+ |  |  |  |\ |  |  |  |  |
+ |  |  |  | \|  |  |  |  |
+ |  |  |  |  X  |  |  |  |
+ |  |  |  |  |\ |  |  |  |
+ |  |  |  |  | \|  |  |  |
+ |  |  |  |  |  X  |  |  |
+ |  |  |  |  |  |\ |  |  |
+ |  |  |  |  |  | \|  |  |
+ |  |  |  |  |  |  X  |  |
+ |  |  |  |  |  |  |\ |  |
+ |  |  |  |  |  |  | \|  |
+ |  |  |  |  |  |  |  X  |
+ |  |  |  |  |  |  |  |\ |
+ |  |  |  |  |  |  |  | \|
+ |  |  |  |  |  |  |  |  @
+ |  |  |  |  |  |  |  |  |
+"[1..], // trim newline at start
+        );
+    }
+}

From 2fa0ea61920590dcc331d9740a25720e025b9d66 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 9 Mar 2025 20:59:21 -0700
Subject: [PATCH 159/190] make FillInDefaultedGenerics work with `Size`s and
 not just `Type`s

---
 crates/fayalite/src/ty.rs | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite/src/ty.rs b/crates/fayalite/src/ty.rs
index 69080c9..55c7e8f 100644
--- a/crates/fayalite/src/ty.rs
+++ b/crates/fayalite/src/ty.rs
@@ -11,6 +11,7 @@ use crate::{
     intern::{Intern, Interned},
     reset::{AsyncReset, Reset, SyncReset},
     source_location::SourceLocation,
+    util::ConstUsize,
 };
 use std::{fmt, hash::Hash, iter::FusedIterator, ops::Index};
 
@@ -166,7 +167,7 @@ impl<T: 'static + Send + Sync> MatchVariantAndInactiveScope for MatchVariantWith
 }
 
 pub trait FillInDefaultedGenerics {
-    type Type: Type;
+    type Type;
     fn fill_in_defaulted_generics(self) -> Self::Type;
 }
 
@@ -178,6 +179,22 @@ impl<T: Type> FillInDefaultedGenerics for T {
     }
 }
 
+impl FillInDefaultedGenerics for usize {
+    type Type = usize;
+
+    fn fill_in_defaulted_generics(self) -> Self::Type {
+        self
+    }
+}
+
+impl<const V: usize> FillInDefaultedGenerics for ConstUsize<V> {
+    type Type = ConstUsize<V>;
+
+    fn fill_in_defaulted_generics(self) -> Self::Type {
+        self
+    }
+}
+
 mod sealed {
     pub trait TypeOrDefaultSealed {}
     pub trait BaseTypeSealed {}

From c0c5b550bc1ca2ddbb2917084211cf420091df75 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 9 Mar 2025 21:03:47 -0700
Subject: [PATCH 160/190] add PhantomConst

---
 crates/fayalite/src/expr.rs                   |  26 ++
 crates/fayalite/src/expr/ops.rs               |  25 +-
 crates/fayalite/src/firrtl.rs                 |  15 +-
 crates/fayalite/src/lib.rs                    |   1 +
 crates/fayalite/src/memory.rs                 |   1 +
 crates/fayalite/src/module.rs                 |   3 +
 .../src/module/transform/deduce_resets.rs     |  13 +-
 .../src/module/transform/simplify_enums.rs    |  13 +-
 .../src/module/transform/simplify_memories.rs |  14 +-
 crates/fayalite/src/module/transform/visit.rs |   1 +
 crates/fayalite/src/phantom_const.rs          | 273 ++++++++++++++++++
 crates/fayalite/src/prelude.rs                |   1 +
 crates/fayalite/src/sim.rs                    |  36 ++-
 crates/fayalite/src/ty.rs                     |  12 +
 crates/fayalite/visit_types.json              |   9 +-
 15 files changed, 428 insertions(+), 15 deletions(-)
 create mode 100644 crates/fayalite/src/phantom_const.rs

diff --git a/crates/fayalite/src/expr.rs b/crates/fayalite/src/expr.rs
index f0008f4..016ec8e 100644
--- a/crates/fayalite/src/expr.rs
+++ b/crates/fayalite/src/expr.rs
@@ -16,6 +16,7 @@ use crate::{
         transform::visit::{Fold, Folder, Visit, Visitor},
         Instance, ModuleIO,
     },
+    phantom_const::PhantomConst,
     reg::Reg,
     reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
     ty::{CanonicalType, StaticType, Type, TypeWithDeref},
@@ -109,6 +110,7 @@ expr_enum! {
         UIntLiteral(Interned<UIntValue>),
         SIntLiteral(Interned<SIntValue>),
         BoolLiteral(bool),
+        PhantomConst(PhantomConst),
         BundleLiteral(ops::BundleLiteral),
         ArrayLiteral(ops::ArrayLiteral<CanonicalType, DynSize>),
         EnumLiteral(ops::EnumLiteral),
@@ -755,3 +757,27 @@ pub fn repeat<T: Type, L: SizeType>(
     )
     .to_expr()
 }
+
+impl<T: ?Sized + crate::phantom_const::PhantomConstValue> ToExpr for PhantomConst<T> {
+    type Type = Self;
+
+    fn to_expr(&self) -> Expr<Self::Type> {
+        Expr {
+            __enum: ExprEnum::PhantomConst(self.canonical_phantom_const()).intern_sized(),
+            __ty: *self,
+            __flow: Flow::Source,
+        }
+    }
+}
+
+impl<T: ?Sized + crate::phantom_const::PhantomConstValue> GetTarget for PhantomConst<T> {
+    fn target(&self) -> Option<Interned<Target>> {
+        None
+    }
+}
+
+impl<T: ?Sized + crate::phantom_const::PhantomConstValue> ToLiteralBits for PhantomConst<T> {
+    fn to_literal_bits(&self) -> Result<Interned<BitSlice>, NotALiteralExpr> {
+        Ok(Interned::default())
+    }
+}
diff --git a/crates/fayalite/src/expr/ops.rs b/crates/fayalite/src/expr/ops.rs
index c502fd5..e794a68 100644
--- a/crates/fayalite/src/expr/ops.rs
+++ b/crates/fayalite/src/expr/ops.rs
@@ -11,14 +11,15 @@ use crate::{
             GetTarget, Target, TargetPathArrayElement, TargetPathBundleField,
             TargetPathDynArrayElement, TargetPathElement,
         },
-        CastTo, Expr, ExprEnum, Flow, HdlPartialEq, HdlPartialOrd, NotALiteralExpr, ReduceBits,
-        ToExpr, ToLiteralBits,
+        CastBitsTo as _, CastTo, CastToBits as _, Expr, ExprEnum, Flow, HdlPartialEq,
+        HdlPartialOrd, NotALiteralExpr, ReduceBits, ToExpr, ToLiteralBits,
     },
     int::{
         Bool, BoolOrIntType, DynSize, IntType, KnownSize, SInt, SIntType, SIntValue, Size, UInt,
         UIntType, UIntValue,
     },
     intern::{Intern, Interned},
+    phantom_const::{PhantomConst, PhantomConstValue},
     reset::{
         AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset, ToAsyncReset, ToReset,
         ToSyncReset,
@@ -1892,6 +1893,26 @@ impl ExprCastTo<Clock> for Clock {
     }
 }
 
+impl<T: ?Sized + PhantomConstValue> ExprCastTo<()> for PhantomConst<T> {
+    fn cast_to(src: Expr<Self>, to_type: ()) -> Expr<()> {
+        src.cast_to_bits().cast_bits_to(to_type)
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> ExprCastTo<PhantomConst<T>> for () {
+    fn cast_to(src: Expr<Self>, to_type: PhantomConst<T>) -> Expr<PhantomConst<T>> {
+        src.cast_to_bits().cast_bits_to(to_type)
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue, U: ?Sized + PhantomConstValue> ExprCastTo<PhantomConst<T>>
+    for PhantomConst<U>
+{
+    fn cast_to(src: Expr<Self>, to_type: PhantomConst<T>) -> Expr<PhantomConst<T>> {
+        src.cast_to_bits().cast_bits_to(to_type)
+    }
+}
+
 #[derive(Copy, Clone, PartialEq, Eq, Hash)]
 pub struct FieldAccess<FieldType: Type = CanonicalType> {
     base: Expr<Bundle>,
diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index ea76cf8..dd5fc2e 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -15,7 +15,7 @@ use crate::{
         target::{
             Target, TargetBase, TargetPathArrayElement, TargetPathBundleField, TargetPathElement,
         },
-        Expr, ExprEnum,
+        CastBitsTo, Expr, ExprEnum,
     },
     formal::FormalKind,
     int::{Bool, DynSize, IntType, SIntValue, UInt, UIntValue},
@@ -447,6 +447,7 @@ impl TypeState {
             CanonicalType::AsyncReset(AsyncReset {}) => "AsyncReset".into(),
             CanonicalType::SyncReset(SyncReset {}) => "UInt<1>".into(),
             CanonicalType::Reset(Reset {}) => "Reset".into(),
+            CanonicalType::PhantomConst(_) => "{}".into(),
         }
     }
 }
@@ -1152,6 +1153,7 @@ impl<'a> Exporter<'a> {
             | CanonicalType::Clock(_)
             | CanonicalType::AsyncReset(_)
             | CanonicalType::Reset(_) => format!("asUInt({value_str})"),
+            CanonicalType::PhantomConst(_) => "UInt<0>(0)".into(),
         }
     }
     fn expr_cast_bits_to_bundle(
@@ -1357,6 +1359,12 @@ impl<'a> Exporter<'a> {
             CanonicalType::AsyncReset(_) => format!("asAsyncReset({value_str})"),
             CanonicalType::SyncReset(_) => value_str,
             CanonicalType::Reset(_) => unreachable!("Reset is not bit castable to"),
+            CanonicalType::PhantomConst(_) => {
+                let retval = self.module.ns.make_new("_cast_bits_to_phantom_const_expr");
+                definitions.add_definition_line(format_args!("{extra_indent}wire {retval}: {{}}"));
+                definitions.add_definition_line(format_args!("{extra_indent}invalidate {retval}"));
+                return retval.to_string();
+            }
         }
     }
     fn expr_unary<T: Type>(
@@ -1395,6 +1403,11 @@ impl<'a> Exporter<'a> {
             ExprEnum::UIntLiteral(literal) => self.uint_literal(&literal),
             ExprEnum::SIntLiteral(literal) => self.sint_literal(&literal),
             ExprEnum::BoolLiteral(literal) => self.bool_literal(literal),
+            ExprEnum::PhantomConst(ty) => self.expr(
+                UInt[0].zero().cast_bits_to(ty.canonical()),
+                definitions,
+                const_ty,
+            ),
             ExprEnum::ArrayLiteral(array_literal) => {
                 self.array_literal_expr(array_literal, definitions, const_ty)
             }
diff --git a/crates/fayalite/src/lib.rs b/crates/fayalite/src/lib.rs
index 88fe169..512572d 100644
--- a/crates/fayalite/src/lib.rs
+++ b/crates/fayalite/src/lib.rs
@@ -96,6 +96,7 @@ pub mod int;
 pub mod intern;
 pub mod memory;
 pub mod module;
+pub mod phantom_const;
 pub mod prelude;
 pub mod reg;
 pub mod reset;
diff --git a/crates/fayalite/src/memory.rs b/crates/fayalite/src/memory.rs
index 2f0ec47..1101157 100644
--- a/crates/fayalite/src/memory.rs
+++ b/crates/fayalite/src/memory.rs
@@ -1082,6 +1082,7 @@ pub fn splat_mask<T: Type>(ty: T, value: Expr<Bool>) -> Expr<AsMask<T>> {
             )
             .to_expr(),
         )),
+        CanonicalType::PhantomConst(_) => Expr::from_canonical(Expr::canonical(().to_expr())),
     }
 }
 
diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index 5a18ac9..446746a 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -1490,6 +1490,9 @@ impl TargetState {
                         })
                         .collect(),
                 },
+                CanonicalType::PhantomConst(_) => TargetStateInner::Decomposed {
+                    subtargets: HashMap::new(),
+                },
                 CanonicalType::Array(ty) => TargetStateInner::Decomposed {
                     subtargets: (0..ty.len())
                         .map(|index| {
diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs
index fe518a5..a70dc33 100644
--- a/crates/fayalite/src/module/transform/deduce_resets.rs
+++ b/crates/fayalite/src/module/transform/deduce_resets.rs
@@ -155,6 +155,7 @@ impl ResetsLayout {
                     CanonicalType::SyncReset(_) => ResetsLayout::SyncReset,
                     CanonicalType::Reset(_) => ResetsLayout::Reset,
                     CanonicalType::Clock(_) => ResetsLayout::NoResets,
+                    CanonicalType::PhantomConst(_) => ResetsLayout::NoResets,
                 }
             }
         }
@@ -407,7 +408,8 @@ impl Resets {
             | CanonicalType::Bool(_)
             | CanonicalType::AsyncReset(_)
             | CanonicalType::SyncReset(_)
-            | CanonicalType::Clock(_) => Ok(self.ty),
+            | CanonicalType::Clock(_)
+            | CanonicalType::PhantomConst(_) => Ok(self.ty),
             CanonicalType::Array(ty) => Ok(CanonicalType::Array(Array::new_dyn(
                 self.array_elements().substituted_type(
                     reset_graph,
@@ -998,7 +1000,8 @@ fn cast_bit_op<P: Pass, T: Type, A: Type>(
                             CanonicalType::Array(_)
                             | CanonicalType::Enum(_)
                             | CanonicalType::Bundle(_)
-                            | CanonicalType::Reset(_) => unreachable!(),
+                            | CanonicalType::Reset(_)
+                            | CanonicalType::PhantomConst(_) => unreachable!(),
                             $(CanonicalType::$Variant(ty) => Expr::expr_enum($arg.cast_to(ty)),)*
                         }
                     };
@@ -1010,6 +1013,7 @@ fn cast_bit_op<P: Pass, T: Type, A: Type>(
                             | CanonicalType::Enum(_)
                             | CanonicalType::Bundle(_)
                             | CanonicalType::Reset(_) => unreachable!(),
+                            CanonicalType::PhantomConst(_) => Expr::expr_enum(arg),
                             $(CanonicalType::$Variant(_) => {
                                 let arg = Expr::<$Variant>::from_canonical(arg);
                                 match_expr_ty!(arg, UInt, SInt, Bool, AsyncReset, SyncReset, Clock)
@@ -1040,6 +1044,7 @@ impl<P: Pass> RunPass<P> for ExprEnum {
             ExprEnum::UIntLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
             ExprEnum::SIntLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
             ExprEnum::BoolLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
+            ExprEnum::PhantomConst(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
             ExprEnum::BundleLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
             ExprEnum::ArrayLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
             ExprEnum::EnumLiteral(expr) => Ok(expr.run_pass(pass_args)?.map(ExprEnum::from)),
@@ -1670,7 +1675,8 @@ impl RunPassDispatch for AnyReg {
                 | CanonicalType::Enum(_)
                 | CanonicalType::Bundle(_)
                 | CanonicalType::Reset(_)
-                | CanonicalType::Clock(_) => unreachable!(),
+                | CanonicalType::Clock(_)
+                | CanonicalType::PhantomConst(_) => unreachable!(),
             }
         })
     }
@@ -1769,6 +1775,7 @@ impl_run_pass_copy!([] SVAttributeAnnotation);
 impl_run_pass_copy!([] UInt);
 impl_run_pass_copy!([] usize);
 impl_run_pass_copy!([] FormalKind);
+impl_run_pass_copy!([] PhantomConst);
 
 macro_rules! impl_run_pass_for_struct {
     (
diff --git a/crates/fayalite/src/module/transform/simplify_enums.rs b/crates/fayalite/src/module/transform/simplify_enums.rs
index 4eb0d0c..e8b6168 100644
--- a/crates/fayalite/src/module/transform/simplify_enums.rs
+++ b/crates/fayalite/src/module/transform/simplify_enums.rs
@@ -69,7 +69,8 @@ fn contains_any_enum_types(ty: CanonicalType) -> bool {
                 | CanonicalType::AsyncReset(_)
                 | CanonicalType::SyncReset(_)
                 | CanonicalType::Reset(_)
-                | CanonicalType::Clock(_) => false,
+                | CanonicalType::Clock(_)
+                | CanonicalType::PhantomConst(_) => false,
             }
         }
     }
@@ -512,7 +513,8 @@ impl State {
             | CanonicalType::AsyncReset(_)
             | CanonicalType::SyncReset(_)
             | CanonicalType::Reset(_)
-            | CanonicalType::Clock(_) => unreachable!(),
+            | CanonicalType::Clock(_)
+            | CanonicalType::PhantomConst(_) => unreachable!(),
         }
     }
 }
@@ -577,7 +579,8 @@ fn connect_port(
         | (CanonicalType::Clock(_), _)
         | (CanonicalType::AsyncReset(_), _)
         | (CanonicalType::SyncReset(_), _)
-        | (CanonicalType::Reset(_), _) => unreachable!(
+        | (CanonicalType::Reset(_), _)
+        | (CanonicalType::PhantomConst(_), _) => unreachable!(
             "trying to connect memory ports:\n{:?}\n{:?}",
             Expr::ty(lhs),
             Expr::ty(rhs),
@@ -665,6 +668,7 @@ impl Folder for State {
             ExprEnum::UIntLiteral(_)
             | ExprEnum::SIntLiteral(_)
             | ExprEnum::BoolLiteral(_)
+            | ExprEnum::PhantomConst(_)
             | ExprEnum::BundleLiteral(_)
             | ExprEnum::ArrayLiteral(_)
             | ExprEnum::Uninit(_)
@@ -923,7 +927,8 @@ impl Folder for State {
             | CanonicalType::Clock(_)
             | CanonicalType::AsyncReset(_)
             | CanonicalType::SyncReset(_)
-            | CanonicalType::Reset(_) => canonical_type.default_fold(self),
+            | CanonicalType::Reset(_)
+            | CanonicalType::PhantomConst(_) => canonical_type.default_fold(self),
         }
     }
 
diff --git a/crates/fayalite/src/module/transform/simplify_memories.rs b/crates/fayalite/src/module/transform/simplify_memories.rs
index e8f9cbf..101385e 100644
--- a/crates/fayalite/src/module/transform/simplify_memories.rs
+++ b/crates/fayalite/src/module/transform/simplify_memories.rs
@@ -62,6 +62,7 @@ enum MemSplit {
     Bundle {
         fields: Rc<[MemSplit]>,
     },
+    PhantomConst,
     Single {
         output_mem: Option<Mem>,
         element_type: SingleType,
@@ -76,6 +77,7 @@ impl MemSplit {
     fn mark_changed_element_type(self) -> Self {
         match self {
             MemSplit::Bundle { fields: _ } => self,
+            MemSplit::PhantomConst => self,
             MemSplit::Single {
                 output_mem,
                 element_type,
@@ -97,6 +99,7 @@ impl MemSplit {
                     .map(|field| Self::new(field.ty).mark_changed_element_type())
                     .collect(),
             },
+            CanonicalType::PhantomConst(_) => MemSplit::PhantomConst,
             CanonicalType::Array(ty) => {
                 let element = MemSplit::new(ty.element());
                 if let Self::Single {
@@ -339,6 +342,7 @@ impl SplitMemState<'_, '_> {
                     self.split_state_stack.pop();
                 }
             }
+            MemSplit::PhantomConst => {}
             MemSplit::Single {
                 output_mem,
                 element_type: single_type,
@@ -538,7 +542,12 @@ impl ModuleState {
             };
         loop {
             match input_element_type {
-                CanonicalType::Bundle(_) => unreachable!("bundle types are always split"),
+                CanonicalType::Bundle(_) => {
+                    unreachable!("bundle types are always split")
+                }
+                CanonicalType::PhantomConst(_) => {
+                    unreachable!("PhantomConst are always removed")
+                }
                 CanonicalType::Enum(_)
                     if input_array_types
                         .first()
@@ -743,7 +752,8 @@ impl ModuleState {
                 ..
             }
             | MemSplit::Bundle { .. }
-            | MemSplit::Array { .. } => {
+            | MemSplit::Array { .. }
+            | MemSplit::PhantomConst => {
                 let mut replacement_ports = Vec::with_capacity(input_mem.ports().len());
                 let mut wire_port_rdata = Vec::with_capacity(input_mem.ports().len());
                 let mut wire_port_wdata = Vec::with_capacity(input_mem.ports().len());
diff --git a/crates/fayalite/src/module/transform/visit.rs b/crates/fayalite/src/module/transform/visit.rs
index 97de4fc..662a578 100644
--- a/crates/fayalite/src/module/transform/visit.rs
+++ b/crates/fayalite/src/module/transform/visit.rs
@@ -28,6 +28,7 @@ use crate::{
         NormalModuleBody, ScopedNameId, Stmt, StmtConnect, StmtDeclaration, StmtFormal, StmtIf,
         StmtInstance, StmtMatch, StmtReg, StmtWire,
     },
+    phantom_const::PhantomConst,
     reg::Reg,
     reset::{AsyncReset, Reset, ResetType, SyncReset},
     source_location::SourceLocation,
diff --git a/crates/fayalite/src/phantom_const.rs b/crates/fayalite/src/phantom_const.rs
new file mode 100644
index 0000000..81f5d6f
--- /dev/null
+++ b/crates/fayalite/src/phantom_const.rs
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use serde::{de::DeserializeOwned, Deserialize, Serialize};
+
+use crate::{
+    intern::{Intern, Interned, InternedCompare, LazyInterned, Memoize},
+    source_location::SourceLocation,
+    ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
+};
+use std::{
+    any::Any,
+    fmt,
+    hash::{Hash, Hasher},
+    marker::PhantomData,
+};
+
+#[derive(Clone)]
+pub struct PhantomConstCanonicalValue {
+    parsed: serde_json::Value,
+    serialized: Interned<str>,
+}
+
+impl PhantomConstCanonicalValue {
+    pub fn from_json_value(parsed: serde_json::Value) -> Self {
+        let serialized = Intern::intern_owned(
+            serde_json::to_string(&parsed)
+                .expect("conversion from json value to text shouldn't fail"),
+        );
+        Self { parsed, serialized }
+    }
+    pub fn as_json_value(&self) -> &serde_json::Value {
+        &self.parsed
+    }
+    pub fn as_str(&self) -> Interned<str> {
+        self.serialized
+    }
+}
+
+impl fmt::Debug for PhantomConstCanonicalValue {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.write_str(&self.serialized)
+    }
+}
+
+impl fmt::Display for PhantomConstCanonicalValue {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.write_str(&self.serialized)
+    }
+}
+
+impl PartialEq for PhantomConstCanonicalValue {
+    fn eq(&self, other: &Self) -> bool {
+        self.serialized == other.serialized
+    }
+}
+
+impl Eq for PhantomConstCanonicalValue {}
+
+impl Hash for PhantomConstCanonicalValue {
+    fn hash<H: Hasher>(&self, state: &mut H) {
+        self.serialized.hash(state);
+    }
+}
+
+impl Serialize for PhantomConstCanonicalValue {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: serde::Serializer,
+    {
+        self.parsed.serialize(serializer)
+    }
+}
+
+impl<'de> Deserialize<'de> for PhantomConstCanonicalValue {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: serde::Deserializer<'de>,
+    {
+        Ok(Self::from_json_value(serde_json::Value::deserialize(
+            deserializer,
+        )?))
+    }
+}
+
+pub trait PhantomConstValue: Intern + InternedCompare + Serialize + fmt::Debug {
+    fn deserialize<'de, D>(deserializer: D) -> Result<Interned<Self>, D::Error>
+    where
+        D: serde::Deserializer<'de>;
+}
+
+impl<T> PhantomConstValue for T
+where
+    T: ?Sized + Intern + InternedCompare + Serialize + fmt::Debug,
+    Interned<T>: DeserializeOwned,
+{
+    fn deserialize<'de, D>(deserializer: D) -> Result<Interned<Self>, D::Error>
+    where
+        D: serde::Deserializer<'de>,
+    {
+        <Interned<T> as Deserialize<'de>>::deserialize(deserializer)
+    }
+}
+
+/// Wrapper type that allows any Rust value to be smuggled as a HDL [`Type`].
+/// This only works for values that can be [serialized][Serialize] to and [deserialized][Deserialize] from [JSON][serde_json].
+pub struct PhantomConst<T: ?Sized + PhantomConstValue = PhantomConstCanonicalValue> {
+    value: LazyInterned<T>,
+}
+
+impl<T: ?Sized + PhantomConstValue> fmt::Debug for PhantomConst<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_tuple("PhantomConst").field(&self.get()).finish()
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> Clone for PhantomConst<T> {
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> Copy for PhantomConst<T> {}
+
+impl<T: ?Sized + PhantomConstValue> PartialEq for PhantomConst<T> {
+    fn eq(&self, other: &Self) -> bool {
+        self.get() == other.get()
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> Eq for PhantomConst<T> {}
+
+impl<T: ?Sized + PhantomConstValue> Hash for PhantomConst<T> {
+    fn hash<H: Hasher>(&self, state: &mut H) {
+        self.get().hash(state);
+    }
+}
+
+struct PhantomConstCanonicalMemoize<T: ?Sized, const IS_FROM_CANONICAL: bool>(PhantomData<T>);
+
+impl<T: ?Sized, const IS_FROM_CANONICAL: bool> Copy
+    for PhantomConstCanonicalMemoize<T, IS_FROM_CANONICAL>
+{
+}
+
+impl<T: ?Sized, const IS_FROM_CANONICAL: bool> Clone
+    for PhantomConstCanonicalMemoize<T, IS_FROM_CANONICAL>
+{
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+impl<T: ?Sized, const IS_FROM_CANONICAL: bool> Eq
+    for PhantomConstCanonicalMemoize<T, IS_FROM_CANONICAL>
+{
+}
+
+impl<T: ?Sized, const IS_FROM_CANONICAL: bool> PartialEq
+    for PhantomConstCanonicalMemoize<T, IS_FROM_CANONICAL>
+{
+    fn eq(&self, _other: &Self) -> bool {
+        true
+    }
+}
+
+impl<T: ?Sized, const IS_FROM_CANONICAL: bool> Hash
+    for PhantomConstCanonicalMemoize<T, IS_FROM_CANONICAL>
+{
+    fn hash<H: Hasher>(&self, _state: &mut H) {}
+}
+
+impl<T: ?Sized + PhantomConstValue> Memoize for PhantomConstCanonicalMemoize<T, false> {
+    type Input = Interned<T>;
+    type InputOwned = Interned<T>;
+    type Output = Interned<PhantomConstCanonicalValue>;
+
+    fn inner(self, input: &Self::Input) -> Self::Output {
+        Intern::intern_sized(PhantomConstCanonicalValue::from_json_value(
+            serde_json::to_value(input)
+                .expect("serialization failed when constructing a canonical PhantomConst"),
+        ))
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> Memoize for PhantomConstCanonicalMemoize<T, true> {
+    type Input = Interned<PhantomConstCanonicalValue>;
+    type InputOwned = Interned<PhantomConstCanonicalValue>;
+    type Output = Interned<T>;
+
+    fn inner(self, input: &Self::Input) -> Self::Output {
+        PhantomConstValue::deserialize(input.as_json_value()).expect("deserialization failed ")
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> PhantomConst<T>
+where
+    Interned<T>: Default,
+{
+    pub const fn default() -> Self {
+        PhantomConst {
+            value: LazyInterned::new_lazy(&Interned::<T>::default),
+        }
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> PhantomConst<T> {
+    pub fn new(value: Interned<T>) -> Self {
+        Self {
+            value: LazyInterned::Interned(value),
+        }
+    }
+    pub fn get(self) -> Interned<T> {
+        self.value.interned()
+    }
+    pub fn type_properties(self) -> TypeProperties {
+        <()>::TYPE_PROPERTIES
+    }
+    pub fn can_connect(self, other: Self) -> bool {
+        self == other
+    }
+    pub fn canonical_phantom_const(self) -> PhantomConst {
+        if let Some(&retval) = <dyn Any>::downcast_ref::<PhantomConst>(&self) {
+            return retval;
+        }
+        <PhantomConst>::new(
+            PhantomConstCanonicalMemoize::<T, false>(PhantomData).get_owned(self.get()),
+        )
+    }
+    pub fn from_canonical_phantom_const(canonical_type: PhantomConst) -> Self {
+        if let Some(&retval) = <dyn Any>::downcast_ref::<Self>(&canonical_type) {
+            return retval;
+        }
+        Self::new(
+            PhantomConstCanonicalMemoize::<T, true>(PhantomData).get_owned(canonical_type.get()),
+        )
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> Type for PhantomConst<T> {
+    type BaseType = PhantomConst;
+    type MaskType = ();
+    impl_match_variant_as_self!();
+
+    fn mask_type(&self) -> Self::MaskType {
+        ()
+    }
+
+    fn canonical(&self) -> CanonicalType {
+        CanonicalType::PhantomConst(self.canonical_phantom_const())
+    }
+
+    fn from_canonical(canonical_type: CanonicalType) -> Self {
+        let CanonicalType::PhantomConst(phantom_const) = canonical_type else {
+            panic!("expected PhantomConst");
+        };
+        Self::from_canonical_phantom_const(phantom_const)
+    }
+
+    fn source_location() -> SourceLocation {
+        SourceLocation::builtin()
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> StaticType for PhantomConst<T>
+where
+    Interned<T>: Default,
+{
+    const TYPE: Self = Self::default();
+    const MASK_TYPE: Self::MaskType = ();
+    const TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES;
+    const MASK_TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES;
+}
diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs
index 9e7a85e..39fa143 100644
--- a/crates/fayalite/src/prelude.rs
+++ b/crates/fayalite/src/prelude.rs
@@ -26,6 +26,7 @@ pub use crate::{
         annotate, connect, connect_any, incomplete_wire, instance, memory, memory_array,
         memory_with_init, reg_builder, wire, Instance, Module, ModuleBuilder,
     },
+    phantom_const::PhantomConst,
     reg::Reg,
     reset::{AsyncReset, Reset, SyncReset, ToAsyncReset, ToReset, ToSyncReset},
     source_location::SourceLocation,
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index f630f5a..96f6dd9 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -167,6 +167,14 @@ impl<T: Type> CompiledTypeLayout<T> {
                             body: CompiledTypeLayoutBody::Array { element },
                         }
                     }
+                    CanonicalType::PhantomConst(_) => {
+                        let unit_layout = CompiledTypeLayout::get(());
+                        CompiledTypeLayout {
+                            ty: *input,
+                            layout: unit_layout.layout,
+                            body: unit_layout.body,
+                        }
+                    }
                     CanonicalType::Bundle(bundle) => {
                         let mut layout = TypeLayout::empty();
                         let fields = bundle
@@ -1792,7 +1800,7 @@ impl Compiler {
                 }
                 .into()
             }
-            CanonicalType::Bundle(_) => unreachable!(),
+            CanonicalType::Bundle(_) | CanonicalType::PhantomConst(_) => unreachable!(),
             CanonicalType::AsyncReset(_) => TraceAsyncReset {
                 location: self.make_trace_scalar_helper(
                     instantiated_module,
@@ -2009,6 +2017,13 @@ impl Compiler {
             | CanonicalType::Clock(_) => {
                 self.make_trace_scalar(instantiated_module, target, name, source_location)
             }
+            CanonicalType::PhantomConst(_) => TraceBundle {
+                name,
+                fields: Interned::default(),
+                ty: Bundle::new(Interned::default()),
+                flow: target.flow(),
+            }
+            .into(),
         }
     }
     fn make_trace_decl(
@@ -2469,6 +2484,9 @@ impl Compiler {
                     Expr::field(Expr::<Bundle>::from_canonical(expr.arg()), &field.name)
                 }),
             ),
+            CanonicalType::PhantomConst(_) => {
+                self.compile_cast_aggregate_to_bits(instantiated_module, [])
+            }
         }
     }
     fn compile_cast_bits_to(
@@ -2518,6 +2536,10 @@ impl Compiler {
             CanonicalType::SyncReset(ty) => Expr::canonical(expr.arg().cast_to(ty)),
             CanonicalType::Reset(_) => unreachable!(),
             CanonicalType::Clock(ty) => Expr::canonical(expr.arg().cast_to(ty)),
+            CanonicalType::PhantomConst(ty) => {
+                let _ = self.compile_expr(instantiated_module, Expr::canonical(expr.arg()));
+                Expr::canonical(ty.to_expr())
+            }
         };
         let retval = self.compile_expr(instantiated_module, Expr::canonical(retval));
         self.compiled_expr_to_value(retval, instantiated_module.leaf_module().source_location())
@@ -2567,6 +2589,7 @@ impl Compiler {
                 CanonicalType::SyncReset(_) => false,
                 CanonicalType::Reset(_) => false,
                 CanonicalType::Clock(_) => false,
+                CanonicalType::PhantomConst(_) => unreachable!(),
             };
             let dest_signed = match Expr::ty(expr) {
                 CanonicalType::UInt(_) => false,
@@ -2579,6 +2602,7 @@ impl Compiler {
                 CanonicalType::SyncReset(_) => false,
                 CanonicalType::Reset(_) => false,
                 CanonicalType::Clock(_) => false,
+                CanonicalType::PhantomConst(_) => unreachable!(),
             };
             self.simple_nary_big_expr(instantiated_module, Expr::ty(expr), [arg], |dest, [src]| {
                 match (src_signed, dest_signed) {
@@ -2634,6 +2658,9 @@ impl Compiler {
                     }]
                 })
                 .into(),
+            ExprEnum::PhantomConst(_) => self
+                .compile_aggregate_literal(instantiated_module, Expr::ty(expr), Interned::default())
+                .into(),
             ExprEnum::BundleLiteral(literal) => self
                 .compile_aggregate_literal(
                     instantiated_module,
@@ -3537,6 +3564,7 @@ impl Compiler {
                 CanonicalType::SyncReset(_) => unreachable!(),
                 CanonicalType::Reset(_) => unreachable!(),
                 CanonicalType::Clock(_) => unreachable!(),
+                CanonicalType::PhantomConst(_) => unreachable!("PhantomConst mismatch"),
             }
         }
         let Some(target) = lhs.target() else {
@@ -3901,6 +3929,7 @@ impl Compiler {
                     CanonicalType::SyncReset(_) => false,
                     CanonicalType::Reset(_) => false,
                     CanonicalType::Clock(_) => false,
+                    CanonicalType::PhantomConst(_) => unreachable!(),
                 };
                 let width = data_layout.ty.bit_width();
                 if let Some(MemoryPortReadInsns {
@@ -5909,6 +5938,7 @@ impl SimValue<CanonicalType> {
             CanonicalType::Clock(ty) => {
                 Expr::canonical(Bool::bits_to_expr(Cow::Borrowed(bits)).cast_to(ty))
             }
+            CanonicalType::PhantomConst(ty) => Expr::canonical(ty.to_expr()),
         }
     }
 }
@@ -6312,7 +6342,8 @@ impl ToSimValue<CanonicalType> for bool {
             | CanonicalType::SInt(_)
             | CanonicalType::Array(_)
             | CanonicalType::Enum(_)
-            | CanonicalType::Bundle(_) => {
+            | CanonicalType::Bundle(_)
+            | CanonicalType::PhantomConst(_) => {
                 panic!("can't create SimValue from bool: expected value of type: {ty:?}");
             }
             CanonicalType::Bool(_)
@@ -6977,6 +7008,7 @@ impl SimulationImpl {
                     CanonicalType::SyncReset(_) => false,
                     CanonicalType::Reset(_) => false,
                     CanonicalType::Clock(_) => false,
+                    CanonicalType::PhantomConst(_) => unreachable!(),
                 };
                 match compiled_value.range.len() {
                     TypeLen::A_SMALL_SLOT => read_write_small_scalar(
diff --git a/crates/fayalite/src/ty.rs b/crates/fayalite/src/ty.rs
index 55c7e8f..2786782 100644
--- a/crates/fayalite/src/ty.rs
+++ b/crates/fayalite/src/ty.rs
@@ -9,6 +9,7 @@ use crate::{
     expr::Expr,
     int::{Bool, SInt, UInt},
     intern::{Intern, Interned},
+    phantom_const::PhantomConst,
     reset::{AsyncReset, Reset, SyncReset},
     source_location::SourceLocation,
     util::ConstUsize,
@@ -36,6 +37,7 @@ pub enum CanonicalType {
     SyncReset(SyncReset),
     Reset(Reset),
     Clock(Clock),
+    PhantomConst(PhantomConst),
 }
 
 impl fmt::Debug for CanonicalType {
@@ -51,6 +53,7 @@ impl fmt::Debug for CanonicalType {
             Self::SyncReset(v) => v.fmt(f),
             Self::Reset(v) => v.fmt(f),
             Self::Clock(v) => v.fmt(f),
+            Self::PhantomConst(v) => v.fmt(f),
         }
     }
 }
@@ -68,6 +71,7 @@ impl CanonicalType {
             CanonicalType::SyncReset(v) => v.type_properties(),
             CanonicalType::Reset(v) => v.type_properties(),
             CanonicalType::Clock(v) => v.type_properties(),
+            CanonicalType::PhantomConst(v) => v.type_properties(),
         }
     }
     pub fn is_passive(self) -> bool {
@@ -144,6 +148,12 @@ impl CanonicalType {
                 };
                 lhs.can_connect(rhs)
             }
+            CanonicalType::PhantomConst(lhs) => {
+                let CanonicalType::PhantomConst(rhs) = rhs else {
+                    return false;
+                };
+                lhs.can_connect(rhs)
+            }
         }
     }
 }
@@ -222,6 +232,7 @@ impl_base_type!(AsyncReset);
 impl_base_type!(SyncReset);
 impl_base_type!(Reset);
 impl_base_type!(Clock);
+impl_base_type!(PhantomConst);
 
 impl sealed::BaseTypeSealed for CanonicalType {}
 
@@ -316,6 +327,7 @@ impl Type for CanonicalType {
             CanonicalType::SyncReset(v) => v.mask_type().canonical(),
             CanonicalType::Reset(v) => v.mask_type().canonical(),
             CanonicalType::Clock(v) => v.mask_type().canonical(),
+            CanonicalType::PhantomConst(v) => v.mask_type().canonical(),
         }
     }
     fn canonical(&self) -> CanonicalType {
diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json
index 3eff1f5..b284372 100644
--- a/crates/fayalite/visit_types.json
+++ b/crates/fayalite/visit_types.json
@@ -49,7 +49,8 @@
                 "AsyncReset": "Visible",
                 "SyncReset": "Visible",
                 "Reset": "Visible",
-                "Clock": "Visible"
+                "Clock": "Visible",
+                "PhantomConst": "Visible"
             }
         },
         "Bundle": {
@@ -1262,6 +1263,12 @@
                 "ArrayElement": "Visible",
                 "DynArrayElement": "Visible"
             }
+        },
+        "PhantomConst": {
+            "data": {
+                "$kind": "Opaque"
+            },
+            "generics": "<T: ?Sized + crate::phantom_const::PhantomConstValue>"
         }
     }
 }
\ No newline at end of file

From 450e1004b6eef6fcdce74a94e3bded3e0268610d Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 9 Mar 2025 23:14:14 -0700
Subject: [PATCH 161/190] fix using fayalite as a dependency

---
 crates/fayalite/src/phantom_const.rs | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/crates/fayalite/src/phantom_const.rs b/crates/fayalite/src/phantom_const.rs
index 81f5d6f..b8f3f09 100644
--- a/crates/fayalite/src/phantom_const.rs
+++ b/crates/fayalite/src/phantom_const.rs
@@ -84,7 +84,7 @@ impl<'de> Deserialize<'de> for PhantomConstCanonicalValue {
 }
 
 pub trait PhantomConstValue: Intern + InternedCompare + Serialize + fmt::Debug {
-    fn deserialize<'de, D>(deserializer: D) -> Result<Interned<Self>, D::Error>
+    fn deserialize_value<'de, D>(deserializer: D) -> Result<Interned<Self>, D::Error>
     where
         D: serde::Deserializer<'de>;
 }
@@ -94,7 +94,7 @@ where
     T: ?Sized + Intern + InternedCompare + Serialize + fmt::Debug,
     Interned<T>: DeserializeOwned,
 {
-    fn deserialize<'de, D>(deserializer: D) -> Result<Interned<Self>, D::Error>
+    fn deserialize_value<'de, D>(deserializer: D) -> Result<Interned<Self>, D::Error>
     where
         D: serde::Deserializer<'de>,
     {
@@ -189,7 +189,8 @@ impl<T: ?Sized + PhantomConstValue> Memoize for PhantomConstCanonicalMemoize<T,
     type Output = Interned<T>;
 
     fn inner(self, input: &Self::Input) -> Self::Output {
-        PhantomConstValue::deserialize(input.as_json_value()).expect("deserialization failed ")
+        PhantomConstValue::deserialize_value(input.as_json_value())
+            .expect("deserialization failed ")
     }
 }
 

From d453755bb2cd0b6f2340f3e49058d29a2ee279e8 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 10 Mar 2025 19:40:03 -0700
Subject: [PATCH 162/190] add ExprPartialEq/ExprPartialOrd impls for
 PhantomConst

---
 crates/fayalite/src/phantom_const.rs | 39 ++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/crates/fayalite/src/phantom_const.rs b/crates/fayalite/src/phantom_const.rs
index b8f3f09..dd6cff6 100644
--- a/crates/fayalite/src/phantom_const.rs
+++ b/crates/fayalite/src/phantom_const.rs
@@ -4,6 +4,11 @@
 use serde::{de::DeserializeOwned, Deserialize, Serialize};
 
 use crate::{
+    expr::{
+        ops::{ExprPartialEq, ExprPartialOrd},
+        Expr, ToExpr,
+    },
+    int::Bool,
     intern::{Intern, Interned, InternedCompare, LazyInterned, Memoize},
     source_location::SourceLocation,
     ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
@@ -272,3 +277,37 @@ where
     const TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES;
     const MASK_TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES;
 }
+
+impl<T: ?Sized + PhantomConstValue> ExprPartialEq<Self> for PhantomConst<T> {
+    fn cmp_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        assert_eq!(Expr::ty(lhs), Expr::ty(rhs));
+        true.to_expr()
+    }
+
+    fn cmp_ne(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        assert_eq!(Expr::ty(lhs), Expr::ty(rhs));
+        false.to_expr()
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> ExprPartialOrd<Self> for PhantomConst<T> {
+    fn cmp_lt(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        assert_eq!(Expr::ty(lhs), Expr::ty(rhs));
+        false.to_expr()
+    }
+
+    fn cmp_le(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        assert_eq!(Expr::ty(lhs), Expr::ty(rhs));
+        true.to_expr()
+    }
+
+    fn cmp_gt(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        assert_eq!(Expr::ty(lhs), Expr::ty(rhs));
+        false.to_expr()
+    }
+
+    fn cmp_ge(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        assert_eq!(Expr::ty(lhs), Expr::ty(rhs));
+        true.to_expr()
+    }
+}

From 920d8d875f80b970a996b4d45f06b145a07fba84 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 19 Mar 2025 17:10:51 -0700
Subject: [PATCH 163/190] add some missing #[track_caller]

---
 crates/fayalite/src/module.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index 446746a..d26dc7b 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -2174,6 +2174,7 @@ impl ModuleBuilder {
             .builder_extern_body()
             .verilog_name = name.intern();
     }
+    #[track_caller]
     pub fn parameter(&self, name: impl AsRef<str>, value: ExternModuleParameterValue) {
         let name = name.as_ref();
         self.impl_
@@ -2186,6 +2187,7 @@ impl ModuleBuilder {
                 value,
             });
     }
+    #[track_caller]
     pub fn parameter_int(&self, name: impl AsRef<str>, value: impl Into<BigInt>) {
         let name = name.as_ref();
         let value = value.into();
@@ -2199,6 +2201,7 @@ impl ModuleBuilder {
                 value: ExternModuleParameterValue::Integer(value),
             });
     }
+    #[track_caller]
     pub fn parameter_str(&self, name: impl AsRef<str>, value: impl AsRef<str>) {
         let name = name.as_ref();
         let value = value.as_ref();
@@ -2212,6 +2215,7 @@ impl ModuleBuilder {
                 value: ExternModuleParameterValue::String(value.intern()),
             });
     }
+    #[track_caller]
     pub fn parameter_raw_verilog(&self, name: impl AsRef<str>, raw_verilog: impl AsRef<str>) {
         let name = name.as_ref();
         let raw_verilog = raw_verilog.as_ref();

From d1bd176b288ab84e58e6f44bce432d13fa105452 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 19 Mar 2025 17:11:41 -0700
Subject: [PATCH 164/190] implement simulation of extern modules

---
 crates/fayalite/src/firrtl.rs                 |    1 +
 crates/fayalite/src/module.rs                 |   25 +-
 crates/fayalite/src/module/transform/visit.rs |    1 +
 crates/fayalite/src/sim.rs                    | 1453 ++++++++---
 crates/fayalite/tests/sim.rs                  |   65 +-
 .../fayalite/tests/sim/expected/array_rw.txt  | 1819 +++-----------
 .../expected/conditional_assignment_last.txt  |   57 +-
 .../tests/sim/expected/connect_const.txt      |   57 +-
 .../sim/expected/connect_const_reset.txt      |  103 +-
 .../tests/sim/expected/counter_async.txt      |  249 +-
 .../tests/sim/expected/counter_sync.txt       |  249 +-
 .../tests/sim/expected/duplicate_names.txt    |   12 +-
 crates/fayalite/tests/sim/expected/enums.txt  |  497 +---
 .../tests/sim/expected/extern_module.txt      |  224 ++
 .../tests/sim/expected/extern_module.vcd      |   51 +
 .../fayalite/tests/sim/expected/memories.txt  | 1436 ++---------
 .../fayalite/tests/sim/expected/memories2.txt |  571 +----
 .../fayalite/tests/sim/expected/memories3.txt | 2135 ++---------------
 crates/fayalite/tests/sim/expected/mod1.txt   |  349 +--
 .../tests/sim/expected/shift_register.txt     |  297 +--
 crates/fayalite/visit_types.json              |    9 +-
 21 files changed, 2702 insertions(+), 6958 deletions(-)
 create mode 100644 crates/fayalite/tests/sim/expected/extern_module.txt
 create mode 100644 crates/fayalite/tests/sim/expected/extern_module.vcd

diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index dd5fc2e..d082187 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -2258,6 +2258,7 @@ impl<'a> Exporter<'a> {
             ModuleBody::Extern(ExternModuleBody {
                 verilog_name,
                 parameters,
+                simulation: _,
             }) => {
                 let verilog_name = Ident(verilog_name);
                 writeln!(body, "{indent}defname = {verilog_name}").unwrap();
diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index d26dc7b..87f86cc 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -21,6 +21,7 @@ use crate::{
     memory::{Mem, MemBuilder, MemBuilderTarget, PortName},
     reg::Reg,
     reset::{AsyncReset, Reset, ResetType, ResetTypeDispatch, SyncReset},
+    sim::{ExternModuleSimGenerator, ExternModuleSimulation},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
     util::ScopedRef,
@@ -1081,6 +1082,7 @@ pub struct ExternModuleBody<
 > {
     pub verilog_name: Interned<str>,
     pub parameters: P,
+    pub simulation: Option<ExternModuleSimulation<Bundle>>,
 }
 
 impl From<ExternModuleBody<Vec<ExternModuleParameter>>> for ExternModuleBody {
@@ -1088,11 +1090,13 @@ impl From<ExternModuleBody<Vec<ExternModuleParameter>>> for ExternModuleBody {
         let ExternModuleBody {
             verilog_name,
             parameters,
+            simulation,
         } = value;
         let parameters = Intern::intern_owned(parameters);
         Self {
             verilog_name,
             parameters,
+            simulation,
         }
     }
 }
@@ -1283,10 +1287,12 @@ impl<T: BundleType> fmt::Debug for DebugModuleBody<T> {
             ModuleBody::Extern(ExternModuleBody {
                 verilog_name,
                 parameters,
+                simulation,
             }) => {
                 debug_struct
                     .field("verilog_name", verilog_name)
-                    .field("parameters", parameters);
+                    .field("parameters", parameters)
+                    .field("simulation", simulation);
             }
         }
         debug_struct.finish_non_exhaustive()
@@ -1761,7 +1767,12 @@ impl AssertValidityState {
             ModuleBody::Extern(ExternModuleBody {
                 verilog_name: _,
                 parameters: _,
-            }) => {}
+                simulation,
+            }) => {
+                if let Some(simulation) = simulation {
+                    simulation.check_io_ty(self.module.io_ty);
+                }
+            }
             ModuleBody::Normal(NormalModuleBody { body }) => {
                 let body = self.make_block_index(body);
                 assert_eq!(body, 0);
@@ -2108,6 +2119,7 @@ impl ModuleBuilder {
             ModuleKind::Extern => ModuleBody::Extern(ExternModuleBody {
                 verilog_name: name.0,
                 parameters: vec![],
+                simulation: None,
             }),
             ModuleKind::Normal => ModuleBody::Normal(NormalModuleBody {
                 body: BuilderModuleBody {
@@ -2229,6 +2241,15 @@ impl ModuleBuilder {
                 value: ExternModuleParameterValue::RawVerilog(raw_verilog.intern()),
             });
     }
+    #[track_caller]
+    pub fn extern_module_simulation<G: ExternModuleSimGenerator>(&self, generator: G) {
+        let mut impl_ = self.impl_.borrow_mut();
+        let simulation = &mut impl_.body.builder_extern_body().simulation;
+        if simulation.is_some() {
+            panic!("already added an extern module simulation");
+        }
+        *simulation = Some(ExternModuleSimulation::new(generator));
+    }
 }
 
 #[track_caller]
diff --git a/crates/fayalite/src/module/transform/visit.rs b/crates/fayalite/src/module/transform/visit.rs
index 662a578..526a62c 100644
--- a/crates/fayalite/src/module/transform/visit.rs
+++ b/crates/fayalite/src/module/transform/visit.rs
@@ -31,6 +31,7 @@ use crate::{
     phantom_const::PhantomConst,
     reg::Reg,
     reset::{AsyncReset, Reset, ResetType, SyncReset},
+    sim::ExternModuleSimulation,
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
     wire::Wire,
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 96f6dd9..a5d7d13 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -15,12 +15,15 @@ use crate::{
         ExprEnum, Flow, ToLiteralBits,
     },
     int::{BoolOrIntType, IntType, SIntValue, UIntValue},
-    intern::{Intern, Interned, Memoize},
+    intern::{
+        Intern, Interned, InternedCompare, Memoize, PtrEqWithTypeId, SupportsPtrEqWithTypeId,
+    },
     memory::PortKind,
     module::{
-        transform::deduce_resets::deduce_resets, AnnotatedModuleIO, Block, Id, InstantiatedModule,
-        ModuleBody, NameId, NormalModuleBody, ScopedNameId, Stmt, StmtConnect, StmtDeclaration,
-        StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire, TargetInInstantiatedModule,
+        transform::deduce_resets::deduce_resets, AnnotatedModuleIO, Block, ExternModuleBody, Id,
+        InstantiatedModule, ModuleBody, NameId, NormalModuleBody, ScopedNameId, Stmt, StmtConnect,
+        StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg, StmtWire,
+        TargetInInstantiatedModule,
     },
     prelude::*,
     reset::{ResetType, ResetTypeDispatch},
@@ -51,7 +54,19 @@ use petgraph::{
     },
 };
 use std::{
-    borrow::Cow, collections::BTreeSet, fmt, marker::PhantomData, mem, ops::IndexMut, sync::Arc,
+    any::Any,
+    borrow::Cow,
+    cell::RefCell,
+    collections::BTreeSet,
+    fmt,
+    future::{Future, IntoFuture},
+    marker::PhantomData,
+    mem,
+    ops::IndexMut,
+    pin::Pin,
+    rc::Rc,
+    sync::Arc,
+    task::Poll,
 };
 
 mod interpreter;
@@ -1617,12 +1632,21 @@ impl<T> fmt::Debug for DebugOpaque<T> {
     }
 }
 
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+struct CompiledExternModule {
+    io_ty: Bundle,
+    module_io_targets: Interned<[Target]>,
+    module_io: Interned<[CompiledValue<CanonicalType>]>,
+    simulation: ExternModuleSimulation<Bundle>,
+}
+
 #[derive(Debug)]
 pub struct Compiler {
     insns: Insns<InsnsBuilding>,
     original_base_module: Interned<Module<Bundle>>,
     base_module: Interned<Module<Bundle>>,
     modules: HashMap<InstantiatedModule, CompiledModule>,
+    extern_modules: Vec<CompiledExternModule>,
     compiled_values: HashMap<TargetInInstantiatedModule, CompiledValue<CanonicalType>>,
     compiled_exprs: HashMap<Expr<CanonicalType>, CompiledExpr<CanonicalType>>,
     compiled_exprs_to_values: HashMap<CompiledExpr<CanonicalType>, CompiledValue<CanonicalType>>,
@@ -1651,6 +1675,7 @@ impl Compiler {
             original_base_module,
             base_module,
             modules: HashMap::new(),
+            extern_modules: Vec::new(),
             compiled_values: HashMap::new(),
             compiled_exprs: HashMap::new(),
             compiled_exprs_to_values: HashMap::new(),
@@ -4676,8 +4701,28 @@ impl Compiler {
             ModuleBody::Normal(NormalModuleBody { body }) => {
                 self.compile_block(module, body, Interned::default(), &mut trace_decls);
             }
-            ModuleBody::Extern(_extern_module_body) => {
-                todo!("simulating extern module: {:?}", module);
+            ModuleBody::Extern(ExternModuleBody {
+                verilog_name: _,
+                parameters: _,
+                simulation,
+            }) => {
+                let Some(simulation) = simulation else {
+                    panic!(
+                        "can't simulate extern module without extern_module_simulation: {}",
+                        module.leaf_module().source_location()
+                    );
+                };
+                self.extern_modules.push(CompiledExternModule {
+                    io_ty: module.leaf_module().io_ty(),
+                    module_io_targets: module
+                        .leaf_module()
+                        .module_io()
+                        .iter()
+                        .map(|v| Target::from(v.module_io))
+                        .collect(),
+                    module_io,
+                    simulation,
+                });
             }
         }
         let hashbrown::hash_map::Entry::Vacant(entry) = self.modules.entry(*module) else {
@@ -4958,6 +5003,7 @@ impl Compiler {
         Compiled {
             insns: Insns::from(self.insns).intern_sized(),
             base_module,
+            extern_modules: Intern::intern_owned(self.extern_modules),
             io: Instance::new_unchecked(
                 ScopedNameId(
                     NameId("<simulator>".intern(), Id::new()),
@@ -4990,6 +5036,7 @@ struct CompiledModule {
 pub struct Compiled<T: BundleType> {
     insns: Interned<Insns<InsnsBuildingDone>>,
     base_module: CompiledModule,
+    extern_modules: Interned<[CompiledExternModule]>,
     io: Instance<T>,
     traces: SimTraces<Interned<[SimTrace<SimTraceKind, ()>]>>,
     trace_memories: Interned<[(StatePartIndex<StatePartKindMemories>, TraceMem)]>,
@@ -5004,6 +5051,7 @@ impl<T: BundleType> Compiled<T> {
         let Self {
             insns,
             base_module,
+            extern_modules,
             io,
             traces,
             trace_memories,
@@ -5012,6 +5060,7 @@ impl<T: BundleType> Compiled<T> {
         Compiled {
             insns,
             base_module,
+            extern_modules,
             io: Instance::from_canonical(io.canonical()),
             traces,
             trace_memories,
@@ -5022,6 +5071,7 @@ impl<T: BundleType> Compiled<T> {
         let Compiled {
             insns,
             base_module,
+            extern_modules,
             io,
             traces,
             trace_memories,
@@ -5030,6 +5080,7 @@ impl<T: BundleType> Compiled<T> {
         Self {
             insns,
             base_module,
+            extern_modules,
             io: Instance::from_canonical(io.canonical()),
             traces,
             trace_memories,
@@ -6474,62 +6525,85 @@ macro_rules! impl_to_sim_value_for_int_value {
 impl_to_sim_value_for_int_value!(UIntValue, UInt, UIntType);
 impl_to_sim_value_for_int_value!(SIntValue, SInt, SIntType);
 
-struct SimulationImpl {
-    state: interpreter::State,
-    io: Expr<Bundle>,
-    uninitialized_inputs: HashMap<Target, Vec<Target>>,
-    io_targets: HashMap<Target, CompiledValue<CanonicalType>>,
-    made_initial_step: bool,
-    needs_settle: bool,
-    trace_decls: TraceModule,
-    traces: SimTraces<Box<[SimTrace<SimTraceKind, BitVec>]>>,
-    trace_memories: HashMap<StatePartIndex<StatePartKindMemories>, TraceMem>,
-    trace_writers: Vec<TraceWriterState<DynTraceWriterDecls>>,
-    instant: SimInstant,
-    clocks_triggered: Interned<[StatePartIndex<StatePartKindSmallSlots>]>,
-    breakpoints: Option<BreakpointsSet>,
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+enum MaybeNeedsSettle<S, N = S> {
+    NeedsSettle(S),
+    NoSettleNeeded(N),
 }
 
-impl fmt::Debug for SimulationImpl {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.debug_fmt(None, f)
+impl<T> MaybeNeedsSettle<T> {
+    fn map<U>(self, f: impl FnOnce(T) -> U) -> MaybeNeedsSettle<U> {
+        match self {
+            MaybeNeedsSettle::NeedsSettle(v) => MaybeNeedsSettle::NeedsSettle(f(v)),
+            MaybeNeedsSettle::NoSettleNeeded(v) => MaybeNeedsSettle::NoSettleNeeded(f(v)),
+        }
     }
 }
 
-impl SimulationImpl {
-    fn debug_fmt(&self, io: Option<&dyn fmt::Debug>, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+// workaround implementing FnOnce not being stable
+trait MaybeNeedsSettleFn<A> {
+    type Output;
+
+    fn call(self, arg: A) -> Self::Output;
+}
+
+impl<T: FnOnce(A) -> O, A, O> MaybeNeedsSettleFn<A> for T {
+    type Output = O;
+
+    fn call(self, arg: A) -> Self::Output {
+        self(arg)
+    }
+}
+
+impl<S, N> MaybeNeedsSettle<S, N> {
+    fn apply_no_settle<T>(self, arg: T) -> MaybeNeedsSettle<S, N::Output>
+    where
+        N: MaybeNeedsSettleFn<T>,
+    {
+        match self {
+            MaybeNeedsSettle::NeedsSettle(v) => MaybeNeedsSettle::NeedsSettle(v),
+            MaybeNeedsSettle::NoSettleNeeded(v) => MaybeNeedsSettle::NoSettleNeeded(v.call(arg)),
+        }
+    }
+}
+
+struct SimulationModuleState {
+    base_targets: Vec<Target>,
+    uninitialized_ios: HashMap<Target, Vec<Target>>,
+    io_targets: HashMap<Target, CompiledValue<CanonicalType>>,
+    did_initial_settle: bool,
+}
+
+impl fmt::Debug for SimulationModuleState {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
-            state,
-            io: self_io,
-            uninitialized_inputs,
+            base_targets,
+            uninitialized_ios,
             io_targets,
-            made_initial_step,
-            needs_settle,
-            trace_decls,
-            traces,
-            trace_memories,
-            trace_writers,
-            instant,
-            clocks_triggered,
-            breakpoints: _,
+            did_initial_settle,
         } = self;
-        f.debug_struct("Simulation")
-            .field("state", state)
-            .field("io", io.unwrap_or(self_io))
-            .field(
-                "uninitialized_inputs",
-                &SortedSetDebug(uninitialized_inputs),
-            )
-            .field("io_targets", &SortedMapDebug(io_targets))
-            .field("made_initial_step", made_initial_step)
-            .field("needs_settle", needs_settle)
-            .field("trace_decls", trace_decls)
-            .field("traces", traces)
-            .field("trace_memories", trace_memories)
-            .field("trace_writers", trace_writers)
-            .field("instant", instant)
-            .field("clocks_triggered", clocks_triggered)
-            .finish_non_exhaustive()
+        f.debug_struct("SimulationModuleState")
+            .field("base_targets", base_targets)
+            .field("uninitialized_ios", &SortedSetDebug(uninitialized_ios))
+            .field("io_targets", &SortedSetDebug(io_targets))
+            .field("did_initial_settle", did_initial_settle)
+            .finish()
+    }
+}
+
+impl SimulationModuleState {
+    fn new(base_targets: impl IntoIterator<Item = (Target, CompiledValue<CanonicalType>)>) -> Self {
+        let mut retval = Self {
+            base_targets: Vec::new(),
+            uninitialized_ios: HashMap::new(),
+            io_targets: HashMap::new(),
+            did_initial_settle: false,
+        };
+        for (base_target, value) in base_targets {
+            retval.base_targets.push(base_target);
+            retval.parse_io(base_target, value);
+        }
+        retval
     }
     /// returns `true` if `target` or any sub-targets are uninitialized inputs
     fn parse_io(&mut self, target: Target, value: CompiledValue<CanonicalType>) -> bool {
@@ -6538,7 +6612,7 @@ impl SimulationImpl {
             CompiledTypeLayoutBody::Scalar => match target.flow() {
                 Flow::Source => false,
                 Flow::Sink => {
-                    self.uninitialized_inputs.insert(target, vec![]);
+                    self.uninitialized_ios.insert(target, vec![]);
                     true
                 }
                 Flow::Duplex => unreachable!(),
@@ -6557,7 +6631,7 @@ impl SimulationImpl {
                 if sub_targets.is_empty() {
                     false
                 } else {
-                    self.uninitialized_inputs.insert(target, sub_targets);
+                    self.uninitialized_ios.insert(target, sub_targets);
                     true
                 }
             }
@@ -6575,20 +6649,406 @@ impl SimulationImpl {
                 if sub_targets.is_empty() {
                     false
                 } else {
-                    self.uninitialized_inputs.insert(target, sub_targets);
+                    self.uninitialized_ios.insert(target, sub_targets);
                     true
                 }
             }
         }
     }
+    fn mark_target_as_initialized(&mut self, mut target: Target) {
+        fn remove_target_and_children(
+            uninitialized_ios: &mut HashMap<Target, Vec<Target>>,
+            target: Target,
+        ) {
+            let Some(children) = uninitialized_ios.remove(&target) else {
+                return;
+            };
+            for child in children {
+                remove_target_and_children(uninitialized_ios, child);
+            }
+        }
+        remove_target_and_children(&mut self.uninitialized_ios, target);
+        while let Some(target_child) = target.child() {
+            let parent = target_child.parent();
+            for child in self
+                .uninitialized_ios
+                .get(&*parent)
+                .map(|v| &**v)
+                .unwrap_or(&[])
+            {
+                if self.uninitialized_ios.contains_key(child) {
+                    return;
+                }
+            }
+            target = *parent;
+            self.uninitialized_ios.remove(&target);
+        }
+    }
+    #[track_caller]
+    fn get_io(
+        &self,
+        mut target: Target,
+        which_module: WhichModule,
+    ) -> CompiledValue<CanonicalType> {
+        if let Some(&retval) = self.io_targets.get(&target) {
+            return retval;
+        }
+        loop {
+            target = match target {
+                Target::Base(_) => break,
+                Target::Child(child) => {
+                    match *child.path_element() {
+                        TargetPathElement::BundleField(_) | TargetPathElement::ArrayElement(_) => {}
+                        TargetPathElement::DynArrayElement(_) => panic!(
+                            "simulator read/write expression must not have dynamic array indexes"
+                        ),
+                    }
+                    *child.parent()
+                }
+            };
+        }
+        match which_module {
+            WhichModule::Main => panic!(
+                "simulator read/write expression must be \
+                an array element/field of `Simulation::io()`"
+            ),
+            WhichModule::Extern { .. } => panic!(
+                "simulator read/write expression must be \
+                one of this module's inputs/outputs or an \
+                array element/field of one of this module's inputs/outputs"
+            ),
+        }
+    }
+    #[track_caller]
+    fn read_helper(
+        &self,
+        io: Expr<CanonicalType>,
+        which_module: WhichModule,
+    ) -> MaybeNeedsSettle<CompiledValue<CanonicalType>> {
+        let Some(target) = io.target() else {
+            match which_module {
+                WhichModule::Main => panic!(
+                    "can't read from an expression that's not a field/element of `Simulation::io()`"
+                ),
+                WhichModule::Extern { .. } => panic!(
+                    "can't read from an expression that's not based on one of this module's inputs/outputs"
+                ),
+            }
+        };
+        let compiled_value = self.get_io(*target, which_module);
+        match target.flow() {
+            Flow::Source => {
+                if !self.uninitialized_ios.is_empty() {
+                    match which_module {
+                        WhichModule::Main => {
+                            panic!("can't read from an output before initializing all inputs");
+                        }
+                        WhichModule::Extern { .. } => {
+                            panic!("can't read from an input before initializing all outputs");
+                        }
+                    }
+                }
+                MaybeNeedsSettle::NeedsSettle(compiled_value)
+            }
+            Flow::Sink => {
+                if self.uninitialized_ios.contains_key(&*target) {
+                    match which_module {
+                        WhichModule::Main => panic!("can't read from an uninitialized input"),
+                        WhichModule::Extern { .. } => {
+                            panic!("can't read from an uninitialized output");
+                        }
+                    }
+                }
+                MaybeNeedsSettle::NoSettleNeeded(compiled_value)
+            }
+            Flow::Duplex => unreachable!(),
+        }
+    }
+    #[track_caller]
+    fn write_helper(
+        &mut self,
+        io: Expr<CanonicalType>,
+        which_module: WhichModule,
+    ) -> CompiledValue<CanonicalType> {
+        let Some(target) = io.target() else {
+            match which_module {
+                WhichModule::Main => panic!(
+                    "can't write to an expression that's not a field/element of `Simulation::io()`"
+                ),
+                WhichModule::Extern { .. } => panic!(
+                    "can't write to an expression that's not based on one of this module's outputs"
+                ),
+            }
+        };
+        let compiled_value = self.get_io(*target, which_module);
+        match target.flow() {
+            Flow::Source => match which_module {
+                WhichModule::Main => panic!("can't write to an output"),
+                WhichModule::Extern { .. } => panic!("can't write to an input"),
+            },
+            Flow::Sink => {}
+            Flow::Duplex => unreachable!(),
+        }
+        if !self.did_initial_settle {
+            self.mark_target_as_initialized(*target);
+        }
+        compiled_value
+    }
+}
+
+#[derive(Copy, Clone, Debug, Eq, PartialEq)]
+enum WaitTarget {
+    /// Settle is less than Instant
+    Settle,
+    Instant(SimInstant),
+}
+
+impl PartialOrd for WaitTarget {
+    fn partial_cmp(&self, other: &Self) -> Option<std::cmp::Ordering> {
+        Some(self.cmp(other))
+    }
+}
+
+impl Ord for WaitTarget {
+    fn cmp(&self, other: &Self) -> std::cmp::Ordering {
+        match (self, other) {
+            (WaitTarget::Settle, WaitTarget::Settle) => std::cmp::Ordering::Equal,
+            (WaitTarget::Settle, WaitTarget::Instant(_)) => std::cmp::Ordering::Less,
+            (WaitTarget::Instant(_), WaitTarget::Settle) => std::cmp::Ordering::Greater,
+            (WaitTarget::Instant(l), WaitTarget::Instant(r)) => l.cmp(r),
+        }
+    }
+}
+
+struct SimulationExternModuleState {
+    module_state: SimulationModuleState,
+    io_ty: Bundle,
+    sim: ExternModuleSimulation<Bundle>,
+    running_generator: Option<Pin<Box<dyn Future<Output = ()> + 'static>>>,
+    wait_target: Option<WaitTarget>,
+}
+
+impl fmt::Debug for SimulationExternModuleState {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            module_state,
+            io_ty,
+            sim,
+            running_generator,
+            wait_target,
+        } = self;
+        f.debug_struct("SimulationExternModuleState")
+            .field("module_state", module_state)
+            .field("io_ty", io_ty)
+            .field("sim", sim)
+            .field(
+                "running_generator",
+                &running_generator.as_ref().map(|_| DebugAsDisplay("...")),
+            )
+            .field("wait_target", wait_target)
+            .finish()
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+enum WhichModule {
+    Main,
+    Extern { module_index: usize },
+}
+
+struct ReadBitFn {
+    compiled_value: CompiledValue<CanonicalType>,
+}
+
+impl MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadBitFn {
+    type Output = bool;
+
+    fn call(self, state: &mut interpreter::State) -> Self::Output {
+        match self.compiled_value.range.len() {
+            TypeLen::A_SMALL_SLOT => {
+                state.small_slots[self.compiled_value.range.small_slots.start] != 0
+            }
+            TypeLen::A_BIG_SLOT => !state.big_slots[self.compiled_value.range.big_slots.start]
+                .clone()
+                .is_zero(),
+            _ => unreachable!(),
+        }
+    }
+}
+
+struct ReadBoolOrIntFn<I: BoolOrIntType> {
+    compiled_value: CompiledValue<CanonicalType>,
+    io: Expr<I>,
+}
+
+impl<I: BoolOrIntType> MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadBoolOrIntFn<I> {
+    type Output = I::Value;
+
+    fn call(self, state: &mut interpreter::State) -> Self::Output {
+        let Self { compiled_value, io } = self;
+        match compiled_value.range.len() {
+            TypeLen::A_SMALL_SLOT => Expr::ty(io)
+                .value_from_int_wrapping(state.small_slots[compiled_value.range.small_slots.start]),
+            TypeLen::A_BIG_SLOT => Expr::ty(io).value_from_int_wrapping(
+                state.big_slots[compiled_value.range.big_slots.start].clone(),
+            ),
+            _ => unreachable!(),
+        }
+    }
+}
+
+struct ReadFn {
+    compiled_value: CompiledValue<CanonicalType>,
+    io: Expr<CanonicalType>,
+}
+
+impl MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadFn {
+    type Output = SimValue<CanonicalType>;
+
+    fn call(self, state: &mut interpreter::State) -> Self::Output {
+        let Self { compiled_value, io } = self;
+        let mut bits = BitVec::repeat(false, compiled_value.layout.ty.bit_width());
+        SimulationImpl::read_write_sim_value_helper(
+            state,
+            compiled_value,
+            &mut bits,
+            |_signed, bits, value| <UInt>::copy_bits_from_bigint_wrapping(value, bits),
+            |_signed, bits, value| {
+                let bytes = value.to_le_bytes();
+                let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
+                bits.clone_from_bitslice(&bitslice[..bits.len()]);
+            },
+        );
+        SimValue {
+            ty: Expr::ty(io),
+            bits,
+        }
+    }
+}
+
+struct GeneratorWaker;
+
+impl std::task::Wake for GeneratorWaker {
+    fn wake(self: Arc<Self>) {
+        panic!("can't await other kinds of futures in function passed to ExternalModuleSimulation");
+    }
+}
+
+#[derive(Default)]
+struct ReadyToRunSet {
+    state_ready_to_run: bool,
+    extern_modules_ready_to_run: Vec<usize>,
+}
+
+impl ReadyToRunSet {
+    fn clear(&mut self) {
+        let Self {
+            state_ready_to_run,
+            extern_modules_ready_to_run,
+        } = self;
+        *state_ready_to_run = false;
+        extern_modules_ready_to_run.clear();
+    }
+}
+
+struct SimulationImpl {
+    state: interpreter::State,
+    io: Expr<Bundle>,
+    main_module: SimulationModuleState,
+    extern_modules: Box<[SimulationExternModuleState]>,
+    state_ready_to_run: bool,
+    trace_decls: TraceModule,
+    traces: SimTraces<Box<[SimTrace<SimTraceKind, BitVec>]>>,
+    trace_memories: HashMap<StatePartIndex<StatePartKindMemories>, TraceMem>,
+    trace_writers: Vec<TraceWriterState<DynTraceWriterDecls>>,
+    instant: SimInstant,
+    clocks_triggered: Interned<[StatePartIndex<StatePartKindSmallSlots>]>,
+    breakpoints: Option<BreakpointsSet>,
+    generator_waker: std::task::Waker,
+}
+
+impl fmt::Debug for SimulationImpl {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.debug_fmt(None, f)
+    }
+}
+
+impl SimulationImpl {
+    fn debug_fmt(&self, io: Option<&dyn fmt::Debug>, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            state,
+            io: self_io,
+            main_module,
+            extern_modules,
+            state_ready_to_run,
+            trace_decls,
+            traces,
+            trace_memories,
+            trace_writers,
+            instant,
+            clocks_triggered,
+            breakpoints: _,
+            generator_waker: _,
+        } = self;
+        f.debug_struct("Simulation")
+            .field("state", state)
+            .field("io", io.unwrap_or(self_io))
+            .field("main_module", main_module)
+            .field("extern_modules", extern_modules)
+            .field("state_ready_to_run", state_ready_to_run)
+            .field("trace_decls", trace_decls)
+            .field("traces", traces)
+            .field("trace_memories", trace_memories)
+            .field("trace_writers", trace_writers)
+            .field("instant", instant)
+            .field("clocks_triggered", clocks_triggered)
+            .finish_non_exhaustive()
+    }
     fn new(compiled: Compiled<Bundle>) -> Self {
-        let mut retval = Self {
+        let io_target = Target::from(compiled.io);
+        let extern_modules = Box::from_iter(compiled.extern_modules.iter().map(
+            |&CompiledExternModule {
+                 io_ty,
+                 module_io_targets,
+                 module_io,
+                 simulation,
+             }| {
+                SimulationExternModuleState {
+                    module_state: SimulationModuleState::new(
+                        module_io_targets
+                            .iter()
+                            .copied()
+                            .zip(module_io.iter().copied()),
+                    ),
+                    io_ty,
+                    sim: simulation,
+                    running_generator: None,
+                    wait_target: Some(WaitTarget::Settle),
+                }
+            },
+        ));
+        Self {
             state: State::new(compiled.insns),
             io: compiled.io.to_expr(),
-            uninitialized_inputs: HashMap::new(),
-            io_targets: HashMap::new(),
-            made_initial_step: false,
-            needs_settle: true,
+            main_module: SimulationModuleState::new(
+                compiled
+                    .io
+                    .ty()
+                    .fields()
+                    .into_iter()
+                    .zip(compiled.base_module.module_io)
+                    .map(|(BundleField { name, .. }, value)| {
+                        (
+                            io_target.join(
+                                TargetPathElement::from(TargetPathBundleField { name })
+                                    .intern_sized(),
+                            ),
+                            value,
+                        )
+                    }),
+            ),
+            extern_modules,
+            state_ready_to_run: true,
             trace_decls: compiled.base_module.trace_decls,
             traces: SimTraces(Box::from_iter(compiled.traces.0.iter().map(
                 |&SimTrace {
@@ -6606,22 +7066,8 @@ impl SimulationImpl {
             instant: SimInstant::START,
             clocks_triggered: compiled.clocks_triggered,
             breakpoints: None,
-        };
-        let io_target = Target::from(compiled.io);
-        for (BundleField { name, .. }, value) in compiled
-            .io
-            .ty()
-            .fields()
-            .into_iter()
-            .zip(compiled.base_module.module_io)
-        {
-            retval.parse_io(
-                io_target
-                    .join(TargetPathElement::from(TargetPathBundleField { name }).intern_sized()),
-                value,
-            );
+            generator_waker: Arc::new(GeneratorWaker).into(),
         }
-        retval
     }
     fn write_traces<const ONLY_IF_CHANGED: bool>(
         &mut self,
@@ -6759,9 +7205,92 @@ impl SimulationImpl {
         }
     }
     #[track_caller]
-    fn advance_time(&mut self, duration: SimDuration) {
-        self.settle();
-        self.instant += duration;
+    fn advance_time(this_ref: &Rc<RefCell<Self>>, duration: SimDuration) {
+        let instant = this_ref.borrow().instant + duration;
+        Self::run_until(this_ref, WaitTarget::Instant(instant));
+    }
+    #[must_use]
+    fn yield_advance_time_or_settle(
+        this: Rc<RefCell<Self>>,
+        module_index: usize,
+        duration: Option<SimDuration>,
+    ) -> impl Future<Output = ()> + 'static {
+        struct MyGenerator {
+            sim: Rc<RefCell<SimulationImpl>>,
+            yielded_at_all: bool,
+            module_index: usize,
+            target: WaitTarget,
+        }
+        impl Future for MyGenerator {
+            type Output = ();
+
+            fn poll(
+                mut self: Pin<&mut Self>,
+                cx: &mut std::task::Context<'_>,
+            ) -> Poll<Self::Output> {
+                let this = &mut *self;
+                let yielded_at_all = mem::replace(&mut this.yielded_at_all, true);
+                let mut sim = this.sim.borrow_mut();
+                let sim = &mut *sim;
+                assert!(cx.waker().will_wake(&sim.generator_waker), "can't use ExternModuleSimulationState's methods outside of ExternModuleSimulation");
+                if let WaitTarget::Instant(target) = this.target {
+                    if target < sim.instant {
+                        this.target = WaitTarget::Settle;
+                    } else if yielded_at_all && target == sim.instant {
+                        this.target = WaitTarget::Settle;
+                    }
+                }
+                if let WaitTarget::Settle = this.target {
+                    if yielded_at_all {
+                        return Poll::Ready(());
+                    }
+                }
+                let wait_target = sim.extern_modules[this.module_index]
+                    .wait_target
+                    .get_or_insert(this.target);
+                *wait_target = (*wait_target).min(this.target);
+                Poll::Pending
+            }
+        }
+        let target = duration.map_or(WaitTarget::Settle, |duration| {
+            WaitTarget::Instant(this.borrow().instant + duration)
+        });
+        MyGenerator {
+            sim: this,
+            yielded_at_all: false,
+            module_index,
+            target,
+        }
+    }
+    /// returns the next `WaitTarget` and the set of things ready to run then.
+    fn get_ready_to_run_set(&self, ready_to_run_set: &mut ReadyToRunSet) -> Option<WaitTarget> {
+        ready_to_run_set.clear();
+        let mut wait_target = None;
+        if self.state_ready_to_run {
+            ready_to_run_set.state_ready_to_run = true;
+            wait_target = Some(WaitTarget::Settle);
+        }
+        for (module_index, extern_module) in self.extern_modules.iter().enumerate() {
+            let Some(extern_module_wait_target) = extern_module.wait_target else {
+                continue;
+            };
+            if let Some(wait_target) = &mut wait_target {
+                match extern_module_wait_target.cmp(wait_target) {
+                    std::cmp::Ordering::Less => ready_to_run_set.clear(),
+                    std::cmp::Ordering::Equal => {}
+                    std::cmp::Ordering::Greater => continue,
+                }
+            } else {
+                wait_target = Some(extern_module_wait_target);
+            }
+            ready_to_run_set
+                .extern_modules_ready_to_run
+                .push(module_index);
+        }
+        wait_target
+    }
+    fn set_instant_no_sim(&mut self, instant: SimInstant) {
+        self.instant = instant;
         self.for_each_trace_writer_storing_error(|this, mut trace_writer_state| {
             match &mut trace_writer_state {
                 TraceWriterState::Decls(_) | TraceWriterState::Init(_) => unreachable!(),
@@ -6774,53 +7303,126 @@ impl SimulationImpl {
         });
     }
     #[track_caller]
-    fn settle(&mut self) {
+    fn run_until(this_ref: &Rc<RefCell<Self>>, run_target: WaitTarget) {
+        let mut this = this_ref.borrow_mut();
+        let mut ready_to_run_set = ReadyToRunSet::default();
+        let generator_waker = this.generator_waker.clone();
         assert!(
-            self.uninitialized_inputs.is_empty(),
+            this.main_module.uninitialized_ios.is_empty(),
             "didn't initialize all inputs",
         );
-        for _ in 0..100000 {
-            if !self.needs_settle {
-                return;
-            }
-            self.state.setup_call(0);
-            if self.breakpoints.is_some() {
-                loop {
-                    match self
-                        .state
-                        .run(self.breakpoints.as_mut().expect("just checked"))
-                    {
-                        RunResult::Break(break_action) => {
-                            println!(
-                                "hit breakpoint at:\n{:?}",
-                                self.state.debug_insn_at(self.state.pc),
-                            );
-                            match break_action {
-                                BreakAction::DumpStateAndContinue => {
-                                    println!("{self:#?}");
-                                }
-                                BreakAction::Continue => {}
-                            }
-                        }
-                        RunResult::Return(()) => break,
-                    }
+        match run_target {
+            WaitTarget::Settle => {}
+            WaitTarget::Instant(run_target) => assert!(run_target >= this.instant),
+        }
+        let mut settle_cycle = 0;
+        let mut run_extern_modules = true;
+        loop {
+            assert!(settle_cycle < 100000, "settle(): took too many steps");
+            settle_cycle += 1;
+            let next_wait_target = match this.get_ready_to_run_set(&mut ready_to_run_set) {
+                Some(next_wait_target) if next_wait_target <= run_target => next_wait_target,
+                _ => break,
+            };
+            match next_wait_target {
+                WaitTarget::Settle => {}
+                WaitTarget::Instant(instant) => {
+                    settle_cycle = 0;
+                    this.set_instant_no_sim(instant);
                 }
-            } else {
-                let RunResult::Return(()) = self.state.run(());
             }
-            if self.made_initial_step {
-                self.read_traces::<false>();
-            } else {
-                self.read_traces::<true>();
+            if run_extern_modules {
+                for module_index in ready_to_run_set.extern_modules_ready_to_run.drain(..) {
+                    let extern_module = &mut this.extern_modules[module_index];
+                    extern_module.wait_target = None;
+                    let mut generator = if !extern_module.module_state.did_initial_settle {
+                        let sim = extern_module.sim;
+                        let io_ty = extern_module.io_ty;
+                        drop(this);
+                        Box::into_pin(sim.run(ExternModuleSimulationState {
+                            sim_impl: this_ref.clone(),
+                            module_index,
+                            io_ty,
+                        }))
+                    } else if let Some(generator) = extern_module.running_generator.take() {
+                        drop(this);
+                        generator
+                    } else {
+                        continue;
+                    };
+                    let generator = match generator
+                        .as_mut()
+                        .poll(&mut std::task::Context::from_waker(&generator_waker))
+                    {
+                        Poll::Ready(()) => None,
+                        Poll::Pending => Some(generator),
+                    };
+                    this = this_ref.borrow_mut();
+                    this.extern_modules[module_index]
+                        .module_state
+                        .did_initial_settle = true;
+                    if !this.extern_modules[module_index]
+                        .module_state
+                        .uninitialized_ios
+                        .is_empty()
+                    {
+                        panic!(
+                            "extern module didn't initialize all outputs before \
+                            waiting, settling, or reading any inputs: {}",
+                            this.extern_modules[module_index].sim.source_location
+                        );
+                    }
+                    this.extern_modules[module_index].running_generator = generator;
+                }
             }
-            self.state.memory_write_log.sort_unstable();
-            self.state.memory_write_log.dedup();
-            self.made_initial_step = true;
-            self.needs_settle = self
-                .clocks_triggered
-                .iter()
-                .any(|i| self.state.small_slots[*i] != 0);
-            self.for_each_trace_writer_storing_error(|this, trace_writer_state| {
+            if ready_to_run_set.state_ready_to_run {
+                this.state_ready_to_run = false;
+                run_extern_modules = true;
+                this.state.setup_call(0);
+                if this.breakpoints.is_some() {
+                    loop {
+                        let this = &mut *this;
+                        match this
+                            .state
+                            .run(this.breakpoints.as_mut().expect("just checked"))
+                        {
+                            RunResult::Break(break_action) => {
+                                println!(
+                                    "hit breakpoint at:\n{:?}",
+                                    this.state.debug_insn_at(this.state.pc),
+                                );
+                                match break_action {
+                                    BreakAction::DumpStateAndContinue => {
+                                        println!("{this:#?}");
+                                    }
+                                    BreakAction::Continue => {}
+                                }
+                            }
+                            RunResult::Return(()) => break,
+                        }
+                    }
+                } else {
+                    let RunResult::Return(()) = this.state.run(());
+                }
+                if this
+                    .clocks_triggered
+                    .iter()
+                    .any(|i| this.state.small_slots[*i] != 0)
+                {
+                    this.state_ready_to_run = true;
+                    // wait for clocks to settle before running extern modules again
+                    run_extern_modules = false;
+                }
+            }
+            if this.main_module.did_initial_settle {
+                this.read_traces::<false>();
+            } else {
+                this.read_traces::<true>();
+            }
+            this.state.memory_write_log.sort_unstable();
+            this.state.memory_write_log.dedup();
+            this.main_module.did_initial_settle = true;
+            this.for_each_trace_writer_storing_error(|this, trace_writer_state| {
                 Ok(match trace_writer_state {
                     TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running(
                         this.init_trace_writer(trace_writer_decls.write_decls(
@@ -6838,114 +7440,48 @@ impl SimulationImpl {
                     TraceWriterState::Errored(e) => TraceWriterState::Errored(e),
                 })
             });
-            self.state.memory_write_log.clear();
+            this.state.memory_write_log.clear();
         }
-        panic!("settle(): took too many steps");
-    }
-    #[track_caller]
-    fn get_io(&self, target: Target) -> CompiledValue<CanonicalType> {
-        if let Some(&retval) = self.io_targets.get(&target) {
-            return retval;
-        }
-        if Some(&target) == self.io.target().as_deref()
-            || Some(target.base()) != self.io.target().map(|v| v.base())
-        {
-            panic!("simulator read/write expression must be an array element/field of `Simulation::io()`");
-        };
-        panic!("simulator read/write expression must not have dynamic array indexes");
-    }
-    fn mark_target_as_initialized(&mut self, mut target: Target) {
-        fn remove_target_and_children(
-            uninitialized_inputs: &mut HashMap<Target, Vec<Target>>,
-            target: Target,
-        ) {
-            let Some(children) = uninitialized_inputs.remove(&target) else {
-                return;
-            };
-            for child in children {
-                remove_target_and_children(uninitialized_inputs, child);
-            }
-        }
-        remove_target_and_children(&mut self.uninitialized_inputs, target);
-        while let Some(target_child) = target.child() {
-            let parent = target_child.parent();
-            for child in self
-                .uninitialized_inputs
-                .get(&*parent)
-                .map(|v| &**v)
-                .unwrap_or(&[])
-            {
-                if self.uninitialized_inputs.contains_key(child) {
-                    return;
-                }
-            }
-            target = *parent;
-            self.uninitialized_inputs.remove(&target);
+        match run_target {
+            WaitTarget::Settle => {}
+            WaitTarget::Instant(instant) => this.set_instant_no_sim(instant),
         }
     }
     #[track_caller]
-    fn read_helper(&mut self, io: Expr<CanonicalType>) -> CompiledValue<CanonicalType> {
-        let Some(target) = io.target() else {
-            panic!("can't read from expression that's not a field/element of `Simulation::io()`");
-        };
-        let compiled_value = self.get_io(*target);
-        if self.made_initial_step {
-            self.settle();
-        } else {
-            match target.flow() {
-                Flow::Source => {
-                    if !self.uninitialized_inputs.is_empty() {
-                        panic!(
-                            "can't read from an output before the simulation has made any steps"
-                        );
-                    }
-                    self.settle();
-                }
-                Flow::Sink => {
-                    if self.uninitialized_inputs.contains_key(&*target) {
-                        panic!("can't read from an uninitialized input");
-                    }
-                }
-                Flow::Duplex => unreachable!(),
-            }
-        }
-        compiled_value
+    fn settle(this_ref: &Rc<RefCell<Self>>) {
+        Self::run_until(this_ref, WaitTarget::Settle);
     }
-    #[track_caller]
-    fn write_helper(&mut self, io: Expr<CanonicalType>) -> CompiledValue<CanonicalType> {
-        let Some(target) = io.target() else {
-            panic!("can't write to an expression that's not a field/element of `Simulation::io()`");
-        };
-        let compiled_value = self.get_io(*target);
-        match target.flow() {
-            Flow::Source => {
-                panic!("can't write to an output");
-            }
-            Flow::Sink => {}
-            Flow::Duplex => unreachable!(),
+    fn get_module(&self, which_module: WhichModule) -> &SimulationModuleState {
+        match which_module {
+            WhichModule::Main => &self.main_module,
+            WhichModule::Extern { module_index } => &self.extern_modules[module_index].module_state,
         }
-        if !self.made_initial_step {
-            self.mark_target_as_initialized(*target);
-        }
-        self.needs_settle = true;
-        compiled_value
     }
-    #[track_caller]
-    fn read_bit(&mut self, io: Expr<CanonicalType>) -> bool {
-        let compiled_value = self.read_helper(Expr::canonical(io));
-        match compiled_value.range.len() {
-            TypeLen::A_SMALL_SLOT => {
-                self.state.small_slots[compiled_value.range.small_slots.start] != 0
+    fn get_module_mut(&mut self, which_module: WhichModule) -> &mut SimulationModuleState {
+        match which_module {
+            WhichModule::Main => &mut self.main_module,
+            WhichModule::Extern { module_index } => {
+                &mut self.extern_modules[module_index].module_state
             }
-            TypeLen::A_BIG_SLOT => !self.state.big_slots[compiled_value.range.big_slots.start]
-                .clone()
-                .is_zero(),
-            _ => unreachable!(),
         }
     }
     #[track_caller]
-    fn write_bit(&mut self, io: Expr<CanonicalType>, value: bool) {
-        let compiled_value = self.write_helper(io);
+    fn read_bit(
+        &mut self,
+        io: Expr<CanonicalType>,
+        which_module: WhichModule,
+    ) -> MaybeNeedsSettle<ReadBitFn, bool> {
+        self.get_module(which_module)
+            .read_helper(Expr::canonical(io), which_module)
+            .map(|compiled_value| ReadBitFn { compiled_value })
+            .apply_no_settle(&mut self.state)
+    }
+    #[track_caller]
+    fn write_bit(&mut self, io: Expr<CanonicalType>, value: bool, which_module: WhichModule) {
+        let compiled_value = self
+            .get_module_mut(which_module)
+            .write_helper(io, which_module);
+        self.state_ready_to_run = true;
         match compiled_value.range.len() {
             TypeLen::A_SMALL_SLOT => {
                 self.state.small_slots[compiled_value.range.small_slots.start] = value as _;
@@ -6957,21 +7493,27 @@ impl SimulationImpl {
         }
     }
     #[track_caller]
-    fn read_bool_or_int<I: BoolOrIntType>(&mut self, io: Expr<I>) -> I::Value {
-        let compiled_value = self.read_helper(Expr::canonical(io));
-        match compiled_value.range.len() {
-            TypeLen::A_SMALL_SLOT => Expr::ty(io).value_from_int_wrapping(
-                self.state.small_slots[compiled_value.range.small_slots.start],
-            ),
-            TypeLen::A_BIG_SLOT => Expr::ty(io).value_from_int_wrapping(
-                self.state.big_slots[compiled_value.range.big_slots.start].clone(),
-            ),
-            _ => unreachable!(),
-        }
+    fn read_bool_or_int<I: BoolOrIntType>(
+        &mut self,
+        io: Expr<I>,
+        which_module: WhichModule,
+    ) -> MaybeNeedsSettle<ReadBoolOrIntFn<I>, I::Value> {
+        self.get_module(which_module)
+            .read_helper(Expr::canonical(io), which_module)
+            .map(|compiled_value| ReadBoolOrIntFn { compiled_value, io })
+            .apply_no_settle(&mut self.state)
     }
     #[track_caller]
-    fn write_bool_or_int<I: BoolOrIntType>(&mut self, io: Expr<I>, value: I::Value) {
-        let compiled_value = self.write_helper(Expr::canonical(io));
+    fn write_bool_or_int<I: BoolOrIntType>(
+        &mut self,
+        io: Expr<I>,
+        value: I::Value,
+        which_module: WhichModule,
+    ) {
+        let compiled_value = self
+            .get_module_mut(which_module)
+            .write_helper(Expr::canonical(io), which_module);
+        self.state_ready_to_run = true;
         let value: BigInt = value.into();
         match compiled_value.range.len() {
             TypeLen::A_SMALL_SLOT => {
@@ -6989,7 +7531,7 @@ impl SimulationImpl {
     }
     #[track_caller]
     fn read_write_sim_value_helper(
-        &mut self,
+        state: &mut interpreter::State,
         compiled_value: CompiledValue<CanonicalType>,
         bits: &mut BitSlice,
         read_write_big_scalar: impl Fn(bool, &mut BitSlice, &mut BigInt) + Copy,
@@ -7014,12 +7556,12 @@ impl SimulationImpl {
                     TypeLen::A_SMALL_SLOT => read_write_small_scalar(
                         signed,
                         bits,
-                        &mut self.state.small_slots[compiled_value.range.small_slots.start],
+                        &mut state.small_slots[compiled_value.range.small_slots.start],
                     ),
                     TypeLen::A_BIG_SLOT => read_write_big_scalar(
                         signed,
                         bits,
-                        &mut self.state.big_slots[compiled_value.range.big_slots.start],
+                        &mut state.big_slots[compiled_value.range.big_slots.start],
                     ),
                     _ => unreachable!(),
                 }
@@ -7028,7 +7570,8 @@ impl SimulationImpl {
                 let ty = <Array>::from_canonical(compiled_value.layout.ty);
                 let element_bit_width = ty.element().bit_width();
                 for element_index in 0..ty.len() {
-                    self.read_write_sim_value_helper(
+                    Self::read_write_sim_value_helper(
+                        state,
                         CompiledValue {
                             layout: *element,
                             range: compiled_value
@@ -7052,7 +7595,8 @@ impl SimulationImpl {
                     },
                 ) in ty.fields().iter().zip(ty.field_offsets()).zip(fields)
                 {
-                    self.read_write_sim_value_helper(
+                    Self::read_write_sim_value_helper(
+                        state,
                         CompiledValue {
                             layout: field_layout,
                             range: compiled_value.range.slice(TypeIndexRange::new(
@@ -7070,29 +7614,30 @@ impl SimulationImpl {
         }
     }
     #[track_caller]
-    fn read(&mut self, io: Expr<CanonicalType>) -> SimValue<CanonicalType> {
-        let compiled_value = self.read_helper(io);
-        let mut bits = BitVec::repeat(false, compiled_value.layout.ty.bit_width());
-        self.read_write_sim_value_helper(
-            compiled_value,
-            &mut bits,
-            |_signed, bits, value| <UInt>::copy_bits_from_bigint_wrapping(value, bits),
-            |_signed, bits, value| {
-                let bytes = value.to_le_bytes();
-                let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
-                bits.clone_from_bitslice(&bitslice[..bits.len()]);
-            },
-        );
-        SimValue {
-            ty: Expr::ty(io),
-            bits,
-        }
+    fn read(
+        &mut self,
+        io: Expr<CanonicalType>,
+        which_module: WhichModule,
+    ) -> MaybeNeedsSettle<ReadFn, SimValue<CanonicalType>> {
+        self.get_module(which_module)
+            .read_helper(io, which_module)
+            .map(|compiled_value| ReadFn { compiled_value, io })
+            .apply_no_settle(&mut self.state)
     }
     #[track_caller]
-    fn write(&mut self, io: Expr<CanonicalType>, value: SimValue<CanonicalType>) {
-        let compiled_value = self.write_helper(io);
+    fn write(
+        &mut self,
+        io: Expr<CanonicalType>,
+        value: SimValue<CanonicalType>,
+        which_module: WhichModule,
+    ) {
+        let compiled_value = self
+            .get_module_mut(which_module)
+            .write_helper(io, which_module);
+        self.state_ready_to_run = true;
         assert_eq!(Expr::ty(io), value.ty());
-        self.read_write_sim_value_helper(
+        Self::read_write_sim_value_helper(
+            &mut self.state,
             compiled_value,
             &mut value.into_bits(),
             |signed, bits, value| {
@@ -7112,6 +7657,35 @@ impl SimulationImpl {
             },
         );
     }
+    #[track_caller]
+    fn settle_if_needed<F, O>(this_ref: &Rc<RefCell<Self>>, v: MaybeNeedsSettle<F, O>) -> O
+    where
+        for<'a> F: MaybeNeedsSettleFn<&'a mut interpreter::State, Output = O>,
+    {
+        match v {
+            MaybeNeedsSettle::NeedsSettle(v) => {
+                Self::settle(this_ref);
+                v.call(&mut this_ref.borrow_mut().state)
+            }
+            MaybeNeedsSettle::NoSettleNeeded(v) => v,
+        }
+    }
+    async fn yield_settle_if_needed<F, O>(
+        this_ref: &Rc<RefCell<Self>>,
+        module_index: usize,
+        v: MaybeNeedsSettle<F, O>,
+    ) -> O
+    where
+        for<'a> F: MaybeNeedsSettleFn<&'a mut interpreter::State, Output = O>,
+    {
+        match v {
+            MaybeNeedsSettle::NeedsSettle(v) => {
+                Self::yield_advance_time_or_settle(this_ref.clone(), module_index, None).await;
+                v.call(&mut this_ref.borrow_mut().state)
+            }
+            MaybeNeedsSettle::NoSettleNeeded(v) => v,
+        }
+    }
     fn close_all_trace_writers(&mut self) -> std::io::Result<()> {
         let trace_writers = mem::take(&mut self.trace_writers);
         let mut retval = Ok(());
@@ -7181,17 +7755,17 @@ impl SimulationImpl {
         self.trace_writers = trace_writers;
         retval
     }
-    fn close(mut self) -> std::io::Result<()> {
-        if self.made_initial_step {
-            self.settle();
+    fn close(this: Rc<RefCell<Self>>) -> std::io::Result<()> {
+        if this.borrow().main_module.did_initial_settle {
+            Self::settle(&this);
         }
-        self.close_all_trace_writers()
+        this.borrow_mut().close_all_trace_writers()
     }
-    fn flush_traces(&mut self) -> std::io::Result<()> {
-        if self.made_initial_step {
-            self.settle();
+    fn flush_traces(this_ref: &Rc<RefCell<Self>>) -> std::io::Result<()> {
+        if this_ref.borrow().main_module.did_initial_settle {
+            Self::settle(this_ref);
         }
-        self.for_each_trace_writer_getting_error(
+        this_ref.borrow_mut().for_each_trace_writer_getting_error(
             |this, trace_writer: TraceWriterState<DynTraceWriterDecls>| match trace_writer {
                 TraceWriterState::Decls(v) => {
                     let mut v = v.write_decls(
@@ -7225,7 +7799,7 @@ impl Drop for SimulationImpl {
 }
 
 pub struct Simulation<T: BundleType> {
-    sim_impl: SimulationImpl,
+    sim_impl: Rc<RefCell<SimulationImpl>>,
     io: Expr<T>,
 }
 
@@ -7272,24 +7846,117 @@ impl<K: fmt::Debug, V: fmt::Debug> fmt::Debug for SortedMapDebug<'_, K, V> {
 impl<T: BundleType> fmt::Debug for Simulation<T> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self { sim_impl, io } = self;
-        sim_impl.debug_fmt(Some(io), f)
+        sim_impl.borrow().debug_fmt(Some(io), f)
     }
 }
 
+macro_rules! impl_simulation_methods {
+    (
+        async_await = ($($async:tt, $await:tt)?),
+        track_caller = ($(#[$track_caller:tt])?),
+        which_module = |$self:ident| $which_module:expr,
+    ) => {
+        $(#[$track_caller])?
+        pub $($async)? fn read_bool_or_int<I: BoolOrIntType>(&mut $self, io: Expr<I>) -> I::Value {
+            let retval = $self
+                .sim_impl
+                .borrow_mut()
+                .read_bool_or_int(io, $which_module);
+            $self.settle_if_needed(retval)$(.$await)?
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn write_bool_or_int<I: BoolOrIntType>(
+            &mut $self,
+            io: Expr<I>,
+            value: impl ToExpr<Type = I>,
+        ) {
+            let value = value.to_expr();
+            assert_eq!(Expr::ty(io), Expr::ty(value), "type mismatch");
+            let value = value
+                .to_literal_bits()
+                .expect("the value that is being written to an input must be a literal");
+            $self.sim_impl.borrow_mut().write_bool_or_int(
+                io,
+                I::bits_to_value(Cow::Borrowed(&value)),
+                $which_module,
+            );
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn write_clock(&mut $self, io: Expr<Clock>, value: bool) {
+            $self.sim_impl
+                .borrow_mut()
+                .write_bit(Expr::canonical(io), value, $which_module);
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn read_clock(&mut $self, io: Expr<Clock>) -> bool {
+            let retval = $self
+                .sim_impl
+                .borrow_mut()
+                .read_bit(Expr::canonical(io), $which_module);
+            $self.settle_if_needed(retval)$(.$await)?
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn write_bool(&mut $self, io: Expr<Bool>, value: bool) {
+            $self.sim_impl
+                .borrow_mut()
+                .write_bit(Expr::canonical(io), value, $which_module);
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn read_bool(&mut $self, io: Expr<Bool>) -> bool {
+            let retval = $self
+                .sim_impl
+                .borrow_mut()
+                .read_bit(Expr::canonical(io), $which_module);
+            $self.settle_if_needed(retval)$(.$await)?
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn write_reset<R: ResetType>(&mut $self, io: Expr<R>, value: bool) {
+            $self.sim_impl
+                .borrow_mut()
+                .write_bit(Expr::canonical(io), value, $which_module);
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn read_reset<R: ResetType>(&mut $self, io: Expr<R>) -> bool {
+            let retval = $self
+                .sim_impl
+                .borrow_mut()
+                .read_bit(Expr::canonical(io), $which_module);
+            $self.settle_if_needed(retval)$(.$await)?
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn read<IO: Type>(&mut $self, io: Expr<IO>) -> SimValue<IO> {
+            let retval = $self
+                .sim_impl
+                .borrow_mut()
+                .read(Expr::canonical(io), $which_module);
+            SimValue::from_canonical($self.settle_if_needed(retval)$(.$await)?)
+        }
+        $(#[$track_caller])?
+        pub $($async)? fn write<IO: Type, V: ToSimValue<IO>>(&mut $self, io: Expr<IO>, value: V) {
+            $self.sim_impl.borrow_mut().write(
+                Expr::canonical(io),
+                value.into_sim_value(Expr::ty(io)).into_canonical(),
+                $which_module,
+            );
+        }
+    };
+}
+
 impl<T: BundleType> Simulation<T> {
     pub fn new(module: Interned<Module<T>>) -> Self {
         Self::from_compiled(Compiled::new(module))
     }
     pub fn add_trace_writer<W: TraceWriterDecls>(&mut self, writer: W) {
         self.sim_impl
+            .borrow_mut()
             .trace_writers
             .push(TraceWriterState::Decls(DynTraceWriterDecls::new(writer)));
     }
     pub fn flush_traces(&mut self) -> std::io::Result<()> {
-        self.sim_impl.flush_traces()
+        SimulationImpl::flush_traces(&self.sim_impl)
     }
     pub fn close(self) -> std::io::Result<()> {
-        self.sim_impl.close()
+        SimulationImpl::close(self.sim_impl)
     }
     pub fn canonical(self) -> Simulation<Bundle> {
         let Self { sim_impl, io } = self;
@@ -7312,77 +7979,215 @@ impl<T: BundleType> Simulation<T> {
         let sim_impl = SimulationImpl::new(compiled.canonical());
         Self {
             io: Expr::from_bundle(sim_impl.io),
-            sim_impl,
+            sim_impl: Rc::new(RefCell::new(sim_impl)),
         }
     }
     #[track_caller]
     pub fn settle(&mut self) {
-        self.sim_impl.settle();
+        SimulationImpl::settle(&self.sim_impl);
     }
     #[track_caller]
     pub fn advance_time(&mut self, duration: SimDuration) {
-        self.sim_impl.advance_time(duration);
+        SimulationImpl::advance_time(&self.sim_impl, duration);
     }
     #[track_caller]
-    pub fn read_bool_or_int<I: BoolOrIntType>(&mut self, io: Expr<I>) -> I::Value {
-        self.sim_impl.read_bool_or_int(io)
-    }
-    #[track_caller]
-    pub fn write_bool_or_int<I: BoolOrIntType>(
-        &mut self,
-        io: Expr<I>,
-        value: impl ToExpr<Type = I>,
-    ) {
-        let value = value.to_expr();
-        assert_eq!(Expr::ty(io), Expr::ty(value), "type mismatch");
-        let value = value
-            .to_literal_bits()
-            .expect("the value that is being written to an input must be a literal");
-        self.sim_impl
-            .write_bool_or_int(io, I::bits_to_value(Cow::Borrowed(&value)));
-    }
-    #[track_caller]
-    pub fn write_clock(&mut self, io: Expr<Clock>, value: bool) {
-        self.sim_impl.write_bit(Expr::canonical(io), value);
-    }
-    #[track_caller]
-    pub fn read_clock(&mut self, io: Expr<Clock>) -> bool {
-        self.sim_impl.read_bit(Expr::canonical(io))
-    }
-    #[track_caller]
-    pub fn write_bool(&mut self, io: Expr<Bool>, value: bool) {
-        self.sim_impl.write_bit(Expr::canonical(io), value);
-    }
-    #[track_caller]
-    pub fn read_bool(&mut self, io: Expr<Bool>) -> bool {
-        self.sim_impl.read_bit(Expr::canonical(io))
-    }
-    #[track_caller]
-    pub fn write_reset<R: ResetType>(&mut self, io: Expr<R>, value: bool) {
-        self.sim_impl.write_bit(Expr::canonical(io), value);
-    }
-    #[track_caller]
-    pub fn read_reset<R: ResetType>(&mut self, io: Expr<R>) -> bool {
-        self.sim_impl.read_bit(Expr::canonical(io))
-    }
-    #[track_caller]
-    pub fn read<IO: Type>(&mut self, io: Expr<IO>) -> SimValue<IO> {
-        SimValue::from_canonical(self.sim_impl.read(Expr::canonical(io)))
-    }
-    #[track_caller]
-    pub fn write<IO: Type, V: ToSimValue<IO>>(&mut self, io: Expr<IO>, value: V) {
-        self.sim_impl.write(
-            Expr::canonical(io),
-            value.into_sim_value(Expr::ty(io)).into_canonical(),
-        );
+    fn settle_if_needed<F, O>(&mut self, v: MaybeNeedsSettle<F, O>) -> O
+    where
+        for<'a> F: MaybeNeedsSettleFn<&'a mut interpreter::State, Output = O>,
+    {
+        SimulationImpl::settle_if_needed(&self.sim_impl, v)
     }
+    impl_simulation_methods!(
+        async_await = (),
+        track_caller = (#[track_caller]),
+        which_module = |self| WhichModule::Main,
+    );
     #[doc(hidden)]
     /// This is explicitly unstable and may be changed/removed at any time
     pub fn set_breakpoints_unstable(&mut self, pcs: HashSet<usize>, trace: bool) {
-        self.sim_impl.breakpoints = Some(BreakpointsSet {
+        self.sim_impl.borrow_mut().breakpoints = Some(BreakpointsSet {
             last_was_break: false,
             set: pcs,
             trace,
         });
     }
 }
+
+pub struct ExternModuleSimulationState<T: BundleType> {
+    sim_impl: Rc<RefCell<SimulationImpl>>,
+    module_index: usize,
+    io_ty: T,
+}
+
+impl<T: BundleType> fmt::Debug for ExternModuleSimulationState<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self {
+            sim_impl: _,
+            module_index,
+            io_ty,
+        } = self;
+        f.debug_struct("ExternModuleSimulationState")
+            .field("sim_impl", &DebugAsDisplay("..."))
+            .field("module_index", module_index)
+            .field("io_ty", io_ty)
+            .finish()
+    }
+}
+
+impl<T: BundleType> ExternModuleSimulationState<T> {
+    pub fn canonical(self) -> ExternModuleSimulationState<Bundle> {
+        let Self {
+            sim_impl,
+            module_index,
+            io_ty,
+        } = self;
+        ExternModuleSimulationState {
+            sim_impl,
+            module_index,
+            io_ty: Bundle::from_canonical(io_ty.canonical()),
+        }
+    }
+    pub fn from_canonical(sim: ExternModuleSimulationState<Bundle>) -> Self {
+        let ExternModuleSimulationState {
+            sim_impl,
+            module_index,
+            io_ty,
+        } = sim;
+        Self {
+            sim_impl,
+            module_index,
+            io_ty: T::from_canonical(io_ty.canonical()),
+        }
+    }
+    pub async fn settle(&mut self) {
+        SimulationImpl::yield_advance_time_or_settle(self.sim_impl.clone(), self.module_index, None)
+            .await
+    }
+    pub async fn advance_time(&mut self, duration: SimDuration) {
+        SimulationImpl::yield_advance_time_or_settle(
+            self.sim_impl.clone(),
+            self.module_index,
+            Some(duration),
+        )
+        .await
+    }
+    async fn settle_if_needed<F, O>(&mut self, v: MaybeNeedsSettle<F, O>) -> O
+    where
+        for<'a> F: MaybeNeedsSettleFn<&'a mut interpreter::State, Output = O>,
+    {
+        SimulationImpl::yield_settle_if_needed(&self.sim_impl, self.module_index, v).await
+    }
+    impl_simulation_methods!(
+        async_await = (async, await),
+        track_caller = (),
+        which_module = |self| WhichModule::Extern { module_index: self.module_index },
+    );
+}
+
+pub trait ExternModuleSimGenerator:
+    Clone + Eq + std::hash::Hash + Any + Send + Sync + fmt::Debug
+{
+    type IOType: BundleType;
+
+    fn run<'a>(
+        &'a self,
+        sim: ExternModuleSimulationState<Self::IOType>,
+    ) -> impl IntoFuture<Output = ()> + 'a;
+}
+
+trait DynExternModuleSimGenerator: Any + Send + Sync + SupportsPtrEqWithTypeId + fmt::Debug {
+    fn dyn_run<'a>(
+        &'a self,
+        sim: ExternModuleSimulationState<Bundle>,
+    ) -> Box<dyn Future<Output = ()> + 'a>;
+    #[track_caller]
+    fn check_io_ty(&self, io_ty: Bundle);
+}
+
+impl<T: ExternModuleSimGenerator> DynExternModuleSimGenerator for T {
+    fn dyn_run<'a>(
+        &'a self,
+        sim: ExternModuleSimulationState<Bundle>,
+    ) -> Box<dyn Future<Output = ()> + 'a> {
+        Box::new(
+            self.run(ExternModuleSimulationState::from_canonical(sim))
+                .into_future(),
+        )
+    }
+    #[track_caller]
+    fn check_io_ty(&self, io_ty: Bundle) {
+        T::IOType::from_canonical(io_ty.canonical());
+    }
+}
+
+impl InternedCompare for dyn DynExternModuleSimGenerator {
+    type InternedCompareKey = PtrEqWithTypeId;
+
+    fn interned_compare_key_ref(this: &Self) -> Self::InternedCompareKey {
+        this.get_ptr_eq_with_type_id()
+    }
+}
+
+#[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)]
+pub struct ExternModuleSimulation<T: BundleType> {
+    generator: Interned<dyn DynExternModuleSimGenerator>,
+    source_location: SourceLocation,
+    _phantom: PhantomData<T>,
+}
+
+impl<T: BundleType> ExternModuleSimulation<T> {
+    pub fn new_with_loc<G: ExternModuleSimGenerator>(
+        source_location: SourceLocation,
+        generator: G,
+    ) -> Self {
+        Self {
+            generator: Interned::cast_unchecked(
+                generator.intern(),
+                |v| -> &dyn DynExternModuleSimGenerator { v },
+            ),
+            source_location,
+            _phantom: PhantomData,
+        }
+    }
+    #[track_caller]
+    pub fn new<G: ExternModuleSimGenerator>(generator: G) -> Self {
+        Self::new_with_loc(SourceLocation::caller(), generator)
+    }
+    pub fn canonical(self) -> ExternModuleSimulation<Bundle> {
+        let Self {
+            generator,
+            source_location,
+            _phantom: _,
+        } = self;
+        ExternModuleSimulation {
+            generator,
+            source_location,
+            _phantom: PhantomData,
+        }
+    }
+    pub fn from_canonical(v: ExternModuleSimulation<Bundle>) -> Self {
+        let ExternModuleSimulation {
+            generator,
+            source_location,
+            _phantom: _,
+        } = v;
+        Self {
+            generator,
+            source_location,
+            _phantom: PhantomData,
+        }
+    }
+}
+
+impl ExternModuleSimulation<Bundle> {
+    fn run(
+        &self,
+        sim: ExternModuleSimulationState<Bundle>,
+    ) -> Box<dyn Future<Output = ()> + 'static> {
+        Interned::into_inner(self.generator).dyn_run(sim)
+    }
+    #[track_caller]
+    pub fn check_io_ty(self, io_ty: Bundle) {
+        self.generator.check_io_ty(io_ty);
+    }
+}
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 8c8a10f..0265a7a 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -5,11 +5,14 @@ use fayalite::{
     int::UIntValue,
     prelude::*,
     reset::ResetType,
-    sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation, ToSimValue},
+    sim::{
+        time::SimDuration, vcd::VcdWriterDecls, ExternModuleSimGenerator,
+        ExternModuleSimulationState, Simulation, ToSimValue,
+    },
     ty::StaticType,
     util::RcWriter,
 };
-use std::num::NonZeroUsize;
+use std::{future::IntoFuture, num::NonZeroUsize};
 
 #[hdl_module(outline_generated)]
 pub fn connect_const() {
@@ -1443,3 +1446,61 @@ fn test_conditional_assignment_last() {
         panic!();
     }
 }
+
+#[hdl_module(outline_generated, extern)]
+pub fn extern_module() {
+    #[hdl]
+    let i: Bool = m.input();
+    #[hdl]
+    let o: Bool = m.output();
+    #[derive(Clone, Eq, PartialEq, Hash, Debug)]
+    struct Sim {
+        i: Expr<Bool>,
+        o: Expr<Bool>,
+    }
+    impl ExternModuleSimGenerator for Sim {
+        type IOType = extern_module;
+
+        fn run<'a>(
+            &'a self,
+            mut sim: ExternModuleSimulationState<Self::IOType>,
+        ) -> impl IntoFuture<Output = ()> + 'a {
+            let Self { i, o } = *self;
+            async move {
+                sim.write(o, true).await;
+                sim.advance_time(SimDuration::from_nanos(500)).await;
+                let mut invert = false;
+                loop {
+                    sim.advance_time(SimDuration::from_micros(1)).await;
+                    let v = sim.read_bool(i).await;
+                    sim.write(o, v ^ invert).await;
+                    invert = !invert;
+                }
+            }
+        }
+    }
+    m.extern_module_simulation(Sim { i, o });
+}
+
+#[test]
+fn test_extern_module() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(extern_module());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write(sim.io().i, false);
+    sim.advance_time(SimDuration::from_micros(10));
+    sim.write(sim.io().i, true);
+    sim.advance_time(SimDuration::from_micros(10));
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/extern_module.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/extern_module.txt") {
+        panic!();
+    }
+}
diff --git a/crates/fayalite/tests/sim/expected/array_rw.txt b/crates/fayalite/tests/sim/expected/array_rw.txt
index f016e72..34643f2 100644
--- a/crates/fayalite/tests/sim/expected/array_rw.txt
+++ b/crates/fayalite/tests/sim/expected/array_rw.txt
@@ -488,1501 +488,338 @@ Simulation {
             ..
         },
     },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Array<UInt<8>, 16>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 16,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[0]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[1]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[2]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[3]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[4]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[5]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[6]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[7]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[8]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[9]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[10]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[11]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[12]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[13]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[14]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[15]",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
                 },
-                body: Array {
-                    element: CompiledTypeLayout {
-                        ty: UInt<8>,
-                        layout: TypeLayout {
-                            small_slots: StatePartLayout<SmallSlots> {
-                                len: 0,
-                                debug_data: [],
-                                ..
-                            },
-                            big_slots: StatePartLayout<BigSlots> {
-                                len: 1,
-                                debug_data: [
-                                    SlotDebugData {
-                                        name: "",
-                                        ty: UInt<8>,
-                                    },
-                                ],
-                                ..
-                            },
-                        },
-                        body: Scalar,
-                    },
+            }.array_in,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
                 },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 16 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[0]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[10]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 10, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[11]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 11, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[12]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 12, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[13]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 13, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[14]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 14, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[15]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 15, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[1]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[2]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[3]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[4]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[5]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[6]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 6, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[7]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 7, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[8]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 8, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_in[9]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 9, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Array<UInt<8>, 16>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 16,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[0]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[1]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[2]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[3]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[4]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[5]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[6]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[7]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[8]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[9]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[10]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[11]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[12]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[13]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[14]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[15]",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Array {
-                    element: CompiledTypeLayout {
-                        ty: UInt<8>,
-                        layout: TypeLayout {
-                            small_slots: StatePartLayout<SmallSlots> {
-                                len: 0,
-                                debug_data: [],
-                                ..
-                            },
-                            big_slots: StatePartLayout<BigSlots> {
-                                len: 1,
-                                debug_data: [
-                                    SlotDebugData {
-                                        name: "",
-                                        ty: UInt<8>,
-                                    },
-                                ],
-                                ..
-                            },
-                        },
-                        body: Scalar,
-                    },
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 16, len: 16 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[0]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 16, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[10]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 26, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[11]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 27, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[12]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 28, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[13]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 29, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[14]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 30, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[15]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 31, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[1]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 17, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[2]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 18, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[3]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 19, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[4]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 20, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[5]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 21, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[6]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 22, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[7]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 23, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[8]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 24, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.array_out[9]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 25, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.read_data: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::read_data",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 33, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.read_index: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::read_index",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 32, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.write_data: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::write_data",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 35, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.write_en: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::write_en",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 36, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::array_rw,
-            instantiated: Module {
-                name: array_rw,
-                ..
-            },
-        }.write_index: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(array_rw: array_rw).array_rw::write_index",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 34, len: 1 },
-            },
-            write: None,
+            }.array_out,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.read_index,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.read_data,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.write_index,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.write_data,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.write_en,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[0],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[10],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[11],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[12],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[13],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[14],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[15],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[1],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[2],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[3],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[4],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[5],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[6],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[7],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[8],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_in[9],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[0],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[10],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[11],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[12],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[13],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[14],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[15],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[1],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[2],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[3],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[4],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[5],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[6],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[7],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[8],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.array_out[9],
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.read_data,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.read_index,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.write_data,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.write_en,
+            Instance {
+                name: <simulator>::array_rw,
+                instantiated: Module {
+                    name: array_rw,
+                    ..
+                },
+            }.write_index,
         },
+        did_initial_settle: true,
     },
-    made_initial_step: true,
-    needs_settle: false,
+    extern_modules: [],
+    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "array_rw",
         children: [
diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt
index 186e5a5..c4242c4 100644
--- a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt
+++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt
@@ -92,45 +92,30 @@ Simulation {
             ..
         },
     },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::conditional_assignment_last,
-            instantiated: Module {
-                name: conditional_assignment_last,
-                ..
-            },
-        }.i: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::i",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::conditional_assignment_last,
+                instantiated: Module {
+                    name: conditional_assignment_last,
+                    ..
                 },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
+            }.i,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::conditional_assignment_last,
+                instantiated: Module {
+                    name: conditional_assignment_last,
+                    ..
+                },
+            }.i,
         },
+        did_initial_settle: true,
     },
-    made_initial_step: true,
-    needs_settle: false,
+    extern_modules: [],
+    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "conditional_assignment_last",
         children: [
diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt
index e44c50d..d357741 100644
--- a/crates/fayalite/tests/sim/expected/connect_const.txt
+++ b/crates/fayalite/tests/sim/expected/connect_const.txt
@@ -68,45 +68,30 @@ Simulation {
             ..
         },
     },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::connect_const,
-            instantiated: Module {
-                name: connect_const,
-                ..
-            },
-        }.o: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(connect_const: connect_const).connect_const::o",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::connect_const,
+                instantiated: Module {
+                    name: connect_const,
+                    ..
                 },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
+            }.o,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::connect_const,
+                instantiated: Module {
+                    name: connect_const,
+                    ..
+                },
+            }.o,
         },
+        did_initial_settle: true,
     },
-    made_initial_step: true,
-    needs_settle: false,
+    extern_modules: [],
+    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "connect_const",
         children: [
diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
index d1ab998..b3eb3ea 100644
--- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt
+++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
@@ -97,79 +97,44 @@ Simulation {
             ..
         },
     },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::connect_const_reset,
-            instantiated: Module {
-                name: connect_const_reset,
-                ..
-            },
-        }.bit_out: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::connect_const_reset,
+                instantiated: Module {
+                    name: connect_const_reset,
+                    ..
                 },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::connect_const_reset,
-            instantiated: Module {
-                name: connect_const_reset,
-                ..
-            },
-        }.reset_out: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: AsyncReset,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
-                                ty: AsyncReset,
-                            },
-                        ],
-                        ..
-                    },
+            }.reset_out,
+            Instance {
+                name: <simulator>::connect_const_reset,
+                instantiated: Module {
+                    name: connect_const_reset,
+                    ..
                 },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
+            }.bit_out,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::connect_const_reset,
+                instantiated: Module {
+                    name: connect_const_reset,
+                    ..
+                },
+            }.bit_out,
+            Instance {
+                name: <simulator>::connect_const_reset,
+                instantiated: Module {
+                    name: connect_const_reset,
+                    ..
+                },
+            }.reset_out,
         },
+        did_initial_settle: true,
     },
-    made_initial_step: true,
-    needs_settle: false,
+    extern_modules: [],
+    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "connect_const_reset",
         children: [
diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt
index 2e005a0..558d943 100644
--- a/crates/fayalite/tests/sim/expected/counter_async.txt
+++ b/crates/fayalite/tests/sim/expected/counter_async.txt
@@ -203,213 +203,58 @@ Simulation {
             ..
         },
     },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: AsyncReset,
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
                 },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
-                                ty: AsyncReset,
-                            },
-                        ],
-                        ..
-                    },
+            }.cd,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
                 },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: AsyncReset,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: AsyncReset,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
+            }.count,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
                 },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd.rst: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: AsyncReset,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: AsyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.count: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
+            }.cd,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.cd.clk,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.cd.rst,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.count,
         },
+        did_initial_settle: true,
     },
-    made_initial_step: true,
-    needs_settle: false,
+    extern_modules: [],
+    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "counter",
         children: [
diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt
index 78fc200..d31db25 100644
--- a/crates/fayalite/tests/sim/expected/counter_sync.txt
+++ b/crates/fayalite/tests/sim/expected/counter_sync.txt
@@ -184,213 +184,58 @@ Simulation {
             ..
         },
     },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: SyncReset,
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
                 },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::cd.rst",
-                                ty: SyncReset,
-                            },
-                        ],
-                        ..
-                    },
+            }.cd,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
                 },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SyncReset,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SyncReset,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
+            }.count,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
                 },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.cd.rst: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SyncReset,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::counter,
-            instantiated: Module {
-                name: counter,
-                ..
-            },
-        }.count: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(counter: counter).counter::count",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
+            }.cd,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.cd.clk,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.cd.rst,
+            Instance {
+                name: <simulator>::counter,
+                instantiated: Module {
+                    name: counter,
+                    ..
+                },
+            }.count,
         },
+        did_initial_settle: true,
     },
-    made_initial_step: true,
-    needs_settle: false,
+    extern_modules: [],
+    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "counter",
         children: [
diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.txt b/crates/fayalite/tests/sim/expected/duplicate_names.txt
index 8a59861..5c6c18a 100644
--- a/crates/fayalite/tests/sim/expected/duplicate_names.txt
+++ b/crates/fayalite/tests/sim/expected/duplicate_names.txt
@@ -88,10 +88,14 @@ Simulation {
             ..
         },
     },
-    uninitialized_inputs: {},
-    io_targets: {},
-    made_initial_step: true,
-    needs_settle: false,
+    main_module: SimulationModuleState {
+        base_targets: [],
+        uninitialized_ios: {},
+        io_targets: {},
+        did_initial_settle: true,
+    },
+    extern_modules: [],
+    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "duplicate_names",
         children: [
diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt
index ebfae3e..089ea31 100644
--- a/crates/fayalite/tests/sim/expected/enums.txt
+++ b/crates/fayalite/tests/sim/expected/enums.txt
@@ -1215,389 +1215,128 @@ Simulation {
             ..
         },
     },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::enums,
-            instantiated: Module {
-                name: enums,
-                ..
-            },
-        }.b_out: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Enum {
-                    HdlNone,
-                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
                 },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(enums: enums).enums::b_out",
-                                ty: Enum {
-                                    HdlNone,
-                                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
-                                },
-                            },
-                        ],
-                        ..
-                    },
+            }.cd,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
                 },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 7, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::enums,
-            instantiated: Module {
-                name: enums,
-                ..
-            },
-        }.cd: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: SyncReset,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(enums: enums).enums::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(enums: enums).enums::cd.rst",
-                                ty: SyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SyncReset,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SyncReset,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::enums,
-            instantiated: Module {
-                name: enums,
-                ..
-            },
-        }.cd.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::enums,
-            instantiated: Module {
-                name: enums,
-                ..
-            },
-        }.cd.rst: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SyncReset,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::enums,
-            instantiated: Module {
-                name: enums,
-                ..
-            },
-        }.data_in: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(enums: enums).enums::data_in",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::enums,
-            instantiated: Module {
-                name: enums,
-                ..
-            },
-        }.data_out: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(enums: enums).enums::data_out",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 6, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::enums,
-            instantiated: Module {
-                name: enums,
-                ..
-            },
-        }.en: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(enums: enums).enums::en",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::enums,
-            instantiated: Module {
-                name: enums,
-                ..
-            },
-        }.which_in: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<2>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(enums: enums).enums::which_in",
-                                ty: UInt<2>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::enums,
-            instantiated: Module {
-                name: enums,
-                ..
-            },
-        }.which_out: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<2>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(enums: enums).enums::which_out",
-                                ty: UInt<2>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 1 },
-            },
-            write: None,
+            }.en,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.which_in,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.data_in,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.which_out,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.data_out,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.b_out,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.b_out,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.cd,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.cd.clk,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.cd.rst,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.data_in,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.data_out,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.en,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.which_in,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.which_out,
         },
+        did_initial_settle: true,
     },
-    made_initial_step: true,
-    needs_settle: false,
+    extern_modules: [],
+    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "enums",
         children: [
diff --git a/crates/fayalite/tests/sim/expected/extern_module.txt b/crates/fayalite/tests/sim/expected/extern_module.txt
new file mode 100644
index 0000000..cb575a5
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/extern_module.txt
@@ -0,0 +1,224 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 2,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(extern_module: extern_module).extern_module::i",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(extern_module: extern_module).extern_module::o",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: Return,
+            ],
+            ..
+        },
+        pc: 0,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                1,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::extern_module,
+        instantiated: Module {
+            name: extern_module,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::extern_module,
+                instantiated: Module {
+                    name: extern_module,
+                    ..
+                },
+            }.i,
+            Instance {
+                name: <simulator>::extern_module,
+                instantiated: Module {
+                    name: extern_module,
+                    ..
+                },
+            }.o,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::extern_module,
+                instantiated: Module {
+                    name: extern_module,
+                    ..
+                },
+            }.i,
+            Instance {
+                name: <simulator>::extern_module,
+                instantiated: Module {
+                    name: extern_module,
+                    ..
+                },
+            }.o,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [
+        SimulationExternModuleState {
+            module_state: SimulationModuleState {
+                base_targets: [
+                    ModuleIO {
+                        name: extern_module::i,
+                        is_input: true,
+                        ty: Bool,
+                        ..
+                    },
+                    ModuleIO {
+                        name: extern_module::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                ],
+                uninitialized_ios: {},
+                io_targets: {
+                    ModuleIO {
+                        name: extern_module::i,
+                        is_input: true,
+                        ty: Bool,
+                        ..
+                    },
+                    ModuleIO {
+                        name: extern_module::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                },
+                did_initial_settle: true,
+            },
+            io_ty: Bundle {
+                #[hdl(flip)] /* offset = 0 */
+                i: Bool,
+                /* offset = 1 */
+                o: Bool,
+            },
+            sim: ExternModuleSimulation {
+                generator: Sim {
+                    i: ModuleIO {
+                        name: extern_module::i,
+                        is_input: true,
+                        ty: Bool,
+                        ..
+                    },
+                    o: ModuleIO {
+                        name: extern_module::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                },
+                source_location: SourceLocation(
+                    module-XXXXXXXXXX.rs:4:1,
+                ),
+                _phantom: PhantomData<fayalite::bundle::Bundle>,
+            },
+            running_generator: Some(
+                ...,
+            ),
+            wait_target: Some(
+                Instant(
+                    20.500000000000 μs,
+                ),
+            ),
+        },
+    ],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "extern_module",
+        children: [
+            TraceModuleIO {
+                name: "i",
+                child: TraceBool {
+                    location: TraceScalarId(0),
+                    name: "i",
+                    flow: Source,
+                },
+                ty: Bool,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "o",
+                child: TraceBool {
+                    location: TraceScalarId(1),
+                    name: "o",
+                    flow: Sink,
+                },
+                ty: Bool,
+                flow: Sink,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 20 μs,
+    clocks_triggered: [],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/extern_module.vcd b/crates/fayalite/tests/sim/expected/extern_module.vcd
new file mode 100644
index 0000000..e026a50
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/extern_module.vcd
@@ -0,0 +1,51 @@
+$timescale 1 ps $end
+$scope module extern_module $end
+$var wire 1 ! i $end
+$var wire 1 " o $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+1"
+$end
+#500000
+#1500000
+0"
+#2500000
+1"
+#3500000
+0"
+#4500000
+1"
+#5500000
+0"
+#6500000
+1"
+#7500000
+0"
+#8500000
+1"
+#9500000
+0"
+#10000000
+1!
+#10500000
+#11500000
+1"
+#12500000
+0"
+#13500000
+1"
+#14500000
+0"
+#15500000
+1"
+#16500000
+0"
+#17500000
+1"
+#18500000
+0"
+#19500000
+1"
+#20000000
diff --git a/crates/fayalite/tests/sim/expected/memories.txt b/crates/fayalite/tests/sim/expected/memories.txt
index afccd8a..cd778d4 100644
--- a/crates/fayalite/tests/sim/expected/memories.txt
+++ b/crates/fayalite/tests/sim/expected/memories.txt
@@ -570,1309 +570,149 @@ Simulation {
             ..
         },
     },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.r: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    addr: UInt<4>,
-                    /* offset = 4 */
-                    en: Bool,
-                    /* offset = 5 */
-                    clk: Clock,
-                    #[hdl(flip)] /* offset = 6 */
-                    data: Bundle {
-                        /* offset = 0 */
-                        0: UInt<8>,
-                        /* offset = 8 */
-                        1: SInt<8>,
-                    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
                 },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 5,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::r.addr",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::r.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::r.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::r.data.0",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::r.data.1",
-                                ty: SInt<8>,
-                            },
-                        ],
-                        ..
-                    },
+            }.r,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
                 },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<4>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<4>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bool,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Bool,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(2),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(3),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bundle {
-                                    /* offset = 0 */
-                                    0: UInt<8>,
-                                    /* offset = 8 */
-                                    1: SInt<8>,
-                                },
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 2,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: ".0",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: ".1",
-                                                ty: SInt<8>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Bundle {
-                                    fields: [
-                                        CompiledBundleField {
-                                            offset: TypeIndex {
-                                                small_slots: StatePartIndex<SmallSlots>(0),
-                                                big_slots: StatePartIndex<BigSlots>(0),
-                                            },
-                                            ty: CompiledTypeLayout {
-                                                ty: UInt<8>,
-                                                layout: TypeLayout {
-                                                    small_slots: StatePartLayout<SmallSlots> {
-                                                        len: 0,
-                                                        debug_data: [],
-                                                        ..
-                                                    },
-                                                    big_slots: StatePartLayout<BigSlots> {
-                                                        len: 1,
-                                                        debug_data: [
-                                                            SlotDebugData {
-                                                                name: "",
-                                                                ty: UInt<8>,
-                                                            },
-                                                        ],
-                                                        ..
-                                                    },
-                                                },
-                                                body: Scalar,
-                                            },
-                                        },
-                                        CompiledBundleField {
-                                            offset: TypeIndex {
-                                                small_slots: StatePartIndex<SmallSlots>(0),
-                                                big_slots: StatePartIndex<BigSlots>(1),
-                                            },
-                                            ty: CompiledTypeLayout {
-                                                ty: SInt<8>,
-                                                layout: TypeLayout {
-                                                    small_slots: StatePartLayout<SmallSlots> {
-                                                        len: 0,
-                                                        debug_data: [],
-                                                        ..
-                                                    },
-                                                    big_slots: StatePartLayout<BigSlots> {
-                                                        len: 1,
-                                                        debug_data: [
-                                                            SlotDebugData {
-                                                                name: "",
-                                                                ty: SInt<8>,
-                                                            },
-                                                        ],
-                                                        ..
-                                                    },
-                                                },
-                                                body: Scalar,
-                                            },
-                                        },
-                                    ],
-                                },
-                            },
-                        },
-                    ],
+            }.w,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
                 },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 5 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.r.addr: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.r.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.r.data: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    0: UInt<8>,
-                    /* offset = 8 */
-                    1: SInt<8>,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: ".0",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: ".1",
-                                ty: SInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<8>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<8>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SInt<8>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SInt<8>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 2 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.r.data.0: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.r.data.1: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.r.en: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.w: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    addr: UInt<4>,
-                    /* offset = 4 */
-                    en: Bool,
-                    /* offset = 5 */
-                    clk: Clock,
-                    /* offset = 6 */
-                    data: Bundle {
-                        /* offset = 0 */
-                        0: UInt<8>,
-                        /* offset = 8 */
-                        1: SInt<8>,
-                    },
-                    /* offset = 22 */
-                    mask: Bundle {
-                        /* offset = 0 */
-                        0: Bool,
-                        /* offset = 1 */
-                        1: Bool,
-                    },
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 7,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.addr",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.data.0",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.data.1",
-                                ty: SInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.mask.0",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.mask.1",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<4>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<4>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bool,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Bool,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(2),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(3),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bundle {
-                                    /* offset = 0 */
-                                    0: UInt<8>,
-                                    /* offset = 8 */
-                                    1: SInt<8>,
-                                },
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 2,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: ".0",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: ".1",
-                                                ty: SInt<8>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Bundle {
-                                    fields: [
-                                        CompiledBundleField {
-                                            offset: TypeIndex {
-                                                small_slots: StatePartIndex<SmallSlots>(0),
-                                                big_slots: StatePartIndex<BigSlots>(0),
-                                            },
-                                            ty: CompiledTypeLayout {
-                                                ty: UInt<8>,
-                                                layout: TypeLayout {
-                                                    small_slots: StatePartLayout<SmallSlots> {
-                                                        len: 0,
-                                                        debug_data: [],
-                                                        ..
-                                                    },
-                                                    big_slots: StatePartLayout<BigSlots> {
-                                                        len: 1,
-                                                        debug_data: [
-                                                            SlotDebugData {
-                                                                name: "",
-                                                                ty: UInt<8>,
-                                                            },
-                                                        ],
-                                                        ..
-                                                    },
-                                                },
-                                                body: Scalar,
-                                            },
-                                        },
-                                        CompiledBundleField {
-                                            offset: TypeIndex {
-                                                small_slots: StatePartIndex<SmallSlots>(0),
-                                                big_slots: StatePartIndex<BigSlots>(1),
-                                            },
-                                            ty: CompiledTypeLayout {
-                                                ty: SInt<8>,
-                                                layout: TypeLayout {
-                                                    small_slots: StatePartLayout<SmallSlots> {
-                                                        len: 0,
-                                                        debug_data: [],
-                                                        ..
-                                                    },
-                                                    big_slots: StatePartLayout<BigSlots> {
-                                                        len: 1,
-                                                        debug_data: [
-                                                            SlotDebugData {
-                                                                name: "",
-                                                                ty: SInt<8>,
-                                                            },
-                                                        ],
-                                                        ..
-                                                    },
-                                                },
-                                                body: Scalar,
-                                            },
-                                        },
-                                    ],
-                                },
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(5),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bundle {
-                                    /* offset = 0 */
-                                    0: Bool,
-                                    /* offset = 1 */
-                                    1: Bool,
-                                },
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 2,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: ".0",
-                                                ty: Bool,
-                                            },
-                                            SlotDebugData {
-                                                name: ".1",
-                                                ty: Bool,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Bundle {
-                                    fields: [
-                                        CompiledBundleField {
-                                            offset: TypeIndex {
-                                                small_slots: StatePartIndex<SmallSlots>(0),
-                                                big_slots: StatePartIndex<BigSlots>(0),
-                                            },
-                                            ty: CompiledTypeLayout {
-                                                ty: Bool,
-                                                layout: TypeLayout {
-                                                    small_slots: StatePartLayout<SmallSlots> {
-                                                        len: 0,
-                                                        debug_data: [],
-                                                        ..
-                                                    },
-                                                    big_slots: StatePartLayout<BigSlots> {
-                                                        len: 1,
-                                                        debug_data: [
-                                                            SlotDebugData {
-                                                                name: "",
-                                                                ty: Bool,
-                                                            },
-                                                        ],
-                                                        ..
-                                                    },
-                                                },
-                                                body: Scalar,
-                                            },
-                                        },
-                                        CompiledBundleField {
-                                            offset: TypeIndex {
-                                                small_slots: StatePartIndex<SmallSlots>(0),
-                                                big_slots: StatePartIndex<BigSlots>(1),
-                                            },
-                                            ty: CompiledTypeLayout {
-                                                ty: Bool,
-                                                layout: TypeLayout {
-                                                    small_slots: StatePartLayout<SmallSlots> {
-                                                        len: 0,
-                                                        debug_data: [],
-                                                        ..
-                                                    },
-                                                    big_slots: StatePartLayout<BigSlots> {
-                                                        len: 1,
-                                                        debug_data: [
-                                                            SlotDebugData {
-                                                                name: "",
-                                                                ty: Bool,
-                                                            },
-                                                        ],
-                                                        ..
-                                                    },
-                                                },
-                                                body: Scalar,
-                                            },
-                                        },
-                                    ],
-                                },
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 7 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.w.addr: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.w.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 7, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.w.data: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    0: UInt<8>,
-                    /* offset = 8 */
-                    1: SInt<8>,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: ".0",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: ".1",
-                                ty: SInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<8>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<8>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SInt<8>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SInt<8>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 8, len: 2 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.w.data.0: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 8, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.w.data.1: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 9, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.w.en: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 6, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.w.mask: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    0: Bool,
-                    /* offset = 1 */
-                    1: Bool,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: ".0",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: ".1",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bool,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Bool,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bool,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Bool,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 10, len: 2 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.w.mask.0: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 10, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.w.mask.1: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 11, len: 1 },
-            },
-            write: None,
+            }.r,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.r.addr,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.r.clk,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.r.data,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.r.data.0,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.r.data.1,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.r.en,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.addr,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.clk,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.data,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.data.0,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.data.1,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.en,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.mask,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.mask.0,
+            Instance {
+                name: <simulator>::memories,
+                instantiated: Module {
+                    name: memories,
+                    ..
+                },
+            }.w.mask.1,
         },
+        did_initial_settle: true,
     },
-    made_initial_step: true,
-    needs_settle: false,
+    extern_modules: [],
+    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "memories",
         children: [
diff --git a/crates/fayalite/tests/sim/expected/memories2.txt b/crates/fayalite/tests/sim/expected/memories2.txt
index 5d90815..2359749 100644
--- a/crates/fayalite/tests/sim/expected/memories2.txt
+++ b/crates/fayalite/tests/sim/expected/memories2.txt
@@ -598,514 +598,79 @@ Simulation {
             ..
         },
     },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    addr: UInt<3>,
-                    /* offset = 3 */
-                    en: Bool,
-                    /* offset = 4 */
-                    clk: Clock,
-                    #[hdl(flip)] /* offset = 5 */
-                    rdata: UInt<2>,
-                    /* offset = 7 */
-                    wmode: Bool,
-                    /* offset = 8 */
-                    wdata: UInt<2>,
-                    /* offset = 10 */
-                    wmask: Bool,
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
                 },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 7,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.addr",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
+            }.rw,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
                 },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<3>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<3>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bool,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Bool,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(2),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(3),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<2>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<2>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(4),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bool,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Bool,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(5),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<2>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<2>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(6),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bool,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Bool,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
+            }.rw,
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
                 },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 7 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw.addr: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<3>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<3>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw.en: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw.rdata: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<2>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw.wdata: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<2>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw.wmask: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 6, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw.wmode: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
-            },
-            write: None,
+            }.rw.addr,
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
+                },
+            }.rw.clk,
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
+                },
+            }.rw.en,
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
+                },
+            }.rw.rdata,
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
+                },
+            }.rw.wdata,
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
+                },
+            }.rw.wmask,
+            Instance {
+                name: <simulator>::memories2,
+                instantiated: Module {
+                    name: memories2,
+                    ..
+                },
+            }.rw.wmode,
         },
+        did_initial_settle: true,
     },
-    made_initial_step: true,
-    needs_settle: false,
+    extern_modules: [],
+    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "memories2",
         children: [
diff --git a/crates/fayalite/tests/sim/expected/memories3.txt b/crates/fayalite/tests/sim/expected/memories3.txt
index 7860bc5..ad12aa4 100644
--- a/crates/fayalite/tests/sim/expected/memories3.txt
+++ b/crates/fayalite/tests/sim/expected/memories3.txt
@@ -1486,1882 +1486,275 @@ Simulation {
             ..
         },
     },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.r: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    addr: UInt<3>,
-                    /* offset = 3 */
-                    en: Bool,
-                    /* offset = 4 */
-                    clk: Clock,
-                    #[hdl(flip)] /* offset = 5 */
-                    data: Array<UInt<8>, 8>,
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
                 },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 11,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.addr",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[0]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[1]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[2]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[3]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[4]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[5]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[6]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[7]",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
+            }.r,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
                 },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<3>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<3>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bool,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Bool,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(2),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(3),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Array<UInt<8>, 8>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 8,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "[0]",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: "[1]",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: "[2]",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: "[3]",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: "[4]",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: "[5]",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: "[6]",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: "[7]",
-                                                ty: UInt<8>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Array {
-                                    element: CompiledTypeLayout {
-                                        ty: UInt<8>,
-                                        layout: TypeLayout {
-                                            small_slots: StatePartLayout<SmallSlots> {
-                                                len: 0,
-                                                debug_data: [],
-                                                ..
-                                            },
-                                            big_slots: StatePartLayout<BigSlots> {
-                                                len: 1,
-                                                debug_data: [
-                                                    SlotDebugData {
-                                                        name: "",
-                                                        ty: UInt<8>,
-                                                    },
-                                                ],
-                                                ..
-                                            },
-                                        },
-                                        body: Scalar,
-                                    },
-                                },
-                            },
-                        },
-                    ],
+            }.w,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
                 },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 11 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.r.addr: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<3>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<3>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.r.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.r.data: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Array<UInt<8>, 8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 8,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "[0]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[1]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[2]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[3]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[4]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[5]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[6]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[7]",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Array {
-                    element: CompiledTypeLayout {
-                        ty: UInt<8>,
-                        layout: TypeLayout {
-                            small_slots: StatePartLayout<SmallSlots> {
-                                len: 0,
-                                debug_data: [],
-                                ..
-                            },
-                            big_slots: StatePartLayout<BigSlots> {
-                                len: 1,
-                                debug_data: [
-                                    SlotDebugData {
-                                        name: "",
-                                        ty: UInt<8>,
-                                    },
-                                ],
-                                ..
-                            },
-                        },
-                        body: Scalar,
-                    },
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 8 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.r.data[0]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.r.data[1]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.r.data[2]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.r.data[3]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 6, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.r.data[4]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 7, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.r.data[5]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 8, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.r.data[6]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 9, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.r.data[7]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 10, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.r.en: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    addr: UInt<3>,
-                    /* offset = 3 */
-                    en: Bool,
-                    /* offset = 4 */
-                    clk: Clock,
-                    /* offset = 5 */
-                    data: Array<UInt<8>, 8>,
-                    /* offset = 69 */
-                    mask: Array<Bool, 8>,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 19,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.addr",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[0]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[1]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[2]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[3]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[4]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[5]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[6]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[7]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[0]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[1]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[2]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[3]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[4]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[5]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[6]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[7]",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<3>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<3>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bool,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Bool,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(2),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(3),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Array<UInt<8>, 8>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 8,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "[0]",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: "[1]",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: "[2]",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: "[3]",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: "[4]",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: "[5]",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: "[6]",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: "[7]",
-                                                ty: UInt<8>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Array {
-                                    element: CompiledTypeLayout {
-                                        ty: UInt<8>,
-                                        layout: TypeLayout {
-                                            small_slots: StatePartLayout<SmallSlots> {
-                                                len: 0,
-                                                debug_data: [],
-                                                ..
-                                            },
-                                            big_slots: StatePartLayout<BigSlots> {
-                                                len: 1,
-                                                debug_data: [
-                                                    SlotDebugData {
-                                                        name: "",
-                                                        ty: UInt<8>,
-                                                    },
-                                                ],
-                                                ..
-                                            },
-                                        },
-                                        body: Scalar,
-                                    },
-                                },
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(11),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Array<Bool, 8>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 8,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "[0]",
-                                                ty: Bool,
-                                            },
-                                            SlotDebugData {
-                                                name: "[1]",
-                                                ty: Bool,
-                                            },
-                                            SlotDebugData {
-                                                name: "[2]",
-                                                ty: Bool,
-                                            },
-                                            SlotDebugData {
-                                                name: "[3]",
-                                                ty: Bool,
-                                            },
-                                            SlotDebugData {
-                                                name: "[4]",
-                                                ty: Bool,
-                                            },
-                                            SlotDebugData {
-                                                name: "[5]",
-                                                ty: Bool,
-                                            },
-                                            SlotDebugData {
-                                                name: "[6]",
-                                                ty: Bool,
-                                            },
-                                            SlotDebugData {
-                                                name: "[7]",
-                                                ty: Bool,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Array {
-                                    element: CompiledTypeLayout {
-                                        ty: Bool,
-                                        layout: TypeLayout {
-                                            small_slots: StatePartLayout<SmallSlots> {
-                                                len: 0,
-                                                debug_data: [],
-                                                ..
-                                            },
-                                            big_slots: StatePartLayout<BigSlots> {
-                                                len: 1,
-                                                debug_data: [
-                                                    SlotDebugData {
-                                                        name: "",
-                                                        ty: Bool,
-                                                    },
-                                                ],
-                                                ..
-                                            },
-                                        },
-                                        body: Scalar,
-                                    },
-                                },
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 11, len: 19 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.addr: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<3>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<3>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 11, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 13, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.data: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Array<UInt<8>, 8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 8,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "[0]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[1]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[2]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[3]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[4]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[5]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[6]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[7]",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Array {
-                    element: CompiledTypeLayout {
-                        ty: UInt<8>,
-                        layout: TypeLayout {
-                            small_slots: StatePartLayout<SmallSlots> {
-                                len: 0,
-                                debug_data: [],
-                                ..
-                            },
-                            big_slots: StatePartLayout<BigSlots> {
-                                len: 1,
-                                debug_data: [
-                                    SlotDebugData {
-                                        name: "",
-                                        ty: UInt<8>,
-                                    },
-                                ],
-                                ..
-                            },
-                        },
-                        body: Scalar,
-                    },
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 14, len: 8 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.data[0]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 14, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.data[1]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 15, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.data[2]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 16, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.data[3]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 17, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.data[4]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 18, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.data[5]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 19, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.data[6]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 20, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.data[7]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 21, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.en: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 12, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.mask: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Array<Bool, 8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 8,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "[0]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[1]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[2]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[3]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[4]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[5]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[6]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[7]",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Array {
-                    element: CompiledTypeLayout {
-                        ty: Bool,
-                        layout: TypeLayout {
-                            small_slots: StatePartLayout<SmallSlots> {
-                                len: 0,
-                                debug_data: [],
-                                ..
-                            },
-                            big_slots: StatePartLayout<BigSlots> {
-                                len: 1,
-                                debug_data: [
-                                    SlotDebugData {
-                                        name: "",
-                                        ty: Bool,
-                                    },
-                                ],
-                                ..
-                            },
-                        },
-                        body: Scalar,
-                    },
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 22, len: 8 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.mask[0]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 22, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.mask[1]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 23, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.mask[2]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 24, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.mask[3]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 25, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.mask[4]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 26, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.mask[5]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 27, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.mask[6]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 28, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.w.mask[7]: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 29, len: 1 },
-            },
-            write: None,
+            }.r,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.addr,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.clk,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[0],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[1],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[2],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[3],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[4],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[5],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[6],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.data[7],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.r.en,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.addr,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.clk,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[0],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[1],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[2],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[3],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[4],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[5],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[6],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.data[7],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.en,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask,
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[0],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[1],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[2],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[3],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[4],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[5],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[6],
+            Instance {
+                name: <simulator>::memories3,
+                instantiated: Module {
+                    name: memories3,
+                    ..
+                },
+            }.w.mask[7],
         },
+        did_initial_settle: true,
     },
-    made_initial_step: true,
-    needs_settle: false,
+    extern_modules: [],
+    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "memories3",
         children: [
diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt
index 5c2b7eb..3656247 100644
--- a/crates/fayalite/tests/sim/expected/mod1.txt
+++ b/crates/fayalite/tests/sim/expected/mod1.txt
@@ -216,313 +216,58 @@ Simulation {
             ..
         },
     },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::mod1,
-            instantiated: Module {
-                name: mod1,
-                ..
-            },
-        }.o: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    #[hdl(flip)] /* offset = 0 */
-                    i: UInt<4>,
-                    /* offset = 4 */
-                    o: SInt<2>,
-                    #[hdl(flip)] /* offset = 6 */
-                    i2: SInt<2>,
-                    /* offset = 8 */
-                    o2: UInt<4>,
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::mod1,
+                instantiated: Module {
+                    name: mod1,
+                    ..
                 },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 4,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.i",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.o",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
-                                ty: SInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
+            }.o,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::mod1,
+                instantiated: Module {
+                    name: mod1,
+                    ..
                 },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<4>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<4>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SInt<2>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SInt<2>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(2),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SInt<2>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SInt<2>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(3),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<4>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<4>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
+            }.o,
+            Instance {
+                name: <simulator>::mod1,
+                instantiated: Module {
+                    name: mod1,
+                    ..
                 },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 4 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::mod1,
-            instantiated: Module {
-                name: mod1,
-                ..
-            },
-        }.o.i: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::mod1,
-            instantiated: Module {
-                name: mod1,
-                ..
-            },
-        }.o.i2: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SInt<2>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SInt<2>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::mod1,
-            instantiated: Module {
-                name: mod1,
-                ..
-            },
-        }.o.o: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SInt<2>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SInt<2>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::mod1,
-            instantiated: Module {
-                name: mod1,
-                ..
-            },
-        }.o.o2: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
-            },
-            write: None,
+            }.o.i,
+            Instance {
+                name: <simulator>::mod1,
+                instantiated: Module {
+                    name: mod1,
+                    ..
+                },
+            }.o.i2,
+            Instance {
+                name: <simulator>::mod1,
+                instantiated: Module {
+                    name: mod1,
+                    ..
+                },
+            }.o.o,
+            Instance {
+                name: <simulator>::mod1,
+                instantiated: Module {
+                    name: mod1,
+                    ..
+                },
+            }.o.o2,
         },
+        did_initial_settle: true,
     },
-    made_initial_step: true,
-    needs_settle: false,
+    extern_modules: [],
+    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "mod1",
         children: [
diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt
index 73f6263..901cf70 100644
--- a/crates/fayalite/tests/sim/expected/shift_register.txt
+++ b/crates/fayalite/tests/sim/expected/shift_register.txt
@@ -265,247 +265,72 @@ Simulation {
             ..
         },
     },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::shift_register,
-            instantiated: Module {
-                name: shift_register,
-                ..
-            },
-        }.cd: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    clk: Clock,
-                    /* offset = 1 */
-                    rst: SyncReset,
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
                 },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst",
-                                ty: SyncReset,
-                            },
-                        ],
-                        ..
-                    },
+            }.cd,
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
                 },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SyncReset,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SyncReset,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
+            }.d,
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
                 },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::shift_register,
-            instantiated: Module {
-                name: shift_register,
-                ..
-            },
-        }.cd.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::shift_register,
-            instantiated: Module {
-                name: shift_register,
-                ..
-            },
-        }.cd.rst: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SyncReset,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SyncReset,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::shift_register,
-            instantiated: Module {
-                name: shift_register,
-                ..
-            },
-        }.d: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::d",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::shift_register,
-            instantiated: Module {
-                name: shift_register,
-                ..
-            },
-        }.q: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(shift_register: shift_register).shift_register::q",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
-            },
-            write: None,
+            }.q,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
+                },
+            }.cd,
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
+                },
+            }.cd.clk,
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
+                },
+            }.cd.rst,
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
+                },
+            }.d,
+            Instance {
+                name: <simulator>::shift_register,
+                instantiated: Module {
+                    name: shift_register,
+                    ..
+                },
+            }.q,
         },
+        did_initial_settle: true,
     },
-    made_initial_step: true,
-    needs_settle: false,
+    extern_modules: [],
+    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "shift_register",
         children: [
diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json
index b284372..451dc90 100644
--- a/crates/fayalite/visit_types.json
+++ b/crates/fayalite/visit_types.json
@@ -160,7 +160,8 @@
             "data": {
                 "$kind": "Struct",
                 "verilog_name": "Visible",
-                "parameters": "Visible"
+                "parameters": "Visible",
+                "simulation": "Visible"
             }
         },
         "ExternModuleParameter": {
@@ -1269,6 +1270,12 @@
                 "$kind": "Opaque"
             },
             "generics": "<T: ?Sized + crate::phantom_const::PhantomConstValue>"
+        },
+        "ExternModuleSimulation": {
+            "data": {
+                "$kind": "Opaque"
+            },
+            "generics": "<T: BundleType>"
         }
     }
 }
\ No newline at end of file

From ab9ff4f2db235fb605d0ec9ea7568d78f54f2575 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 21 Mar 2025 17:08:29 -0700
Subject: [PATCH 165/190] simplify setting an extern module simulation

---
 crates/fayalite/src/module.rs                 |  22 ++-
 crates/fayalite/src/sim.rs                    | 170 +++++++-----------
 crates/fayalite/tests/sim.rs                  |  43 ++---
 .../tests/sim/expected/extern_module.txt      |  36 ++--
 crates/fayalite/visit_types.json              |   3 +-
 5 files changed, 111 insertions(+), 163 deletions(-)

diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index 87f86cc..1fcb529 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -34,6 +34,7 @@ use std::{
     collections::VecDeque,
     convert::Infallible,
     fmt,
+    future::IntoFuture,
     hash::{Hash, Hasher},
     iter::FusedIterator,
     marker::PhantomData,
@@ -1082,7 +1083,7 @@ pub struct ExternModuleBody<
 > {
     pub verilog_name: Interned<str>,
     pub parameters: P,
-    pub simulation: Option<ExternModuleSimulation<Bundle>>,
+    pub simulation: Option<ExternModuleSimulation>,
 }
 
 impl From<ExternModuleBody<Vec<ExternModuleParameter>>> for ExternModuleBody {
@@ -1767,12 +1768,8 @@ impl AssertValidityState {
             ModuleBody::Extern(ExternModuleBody {
                 verilog_name: _,
                 parameters: _,
-                simulation,
-            }) => {
-                if let Some(simulation) = simulation {
-                    simulation.check_io_ty(self.module.io_ty);
-                }
-            }
+                simulation: _,
+            }) => {}
             ModuleBody::Normal(NormalModuleBody { body }) => {
                 let body = self.make_block_index(body);
                 assert_eq!(body, 0);
@@ -2250,6 +2247,17 @@ impl ModuleBuilder {
         }
         *simulation = Some(ExternModuleSimulation::new(generator));
     }
+    #[track_caller]
+    pub fn extern_module_simulation_fn<
+        Args: fmt::Debug + Clone + Hash + Eq + Send + Sync + 'static,
+        Fut: IntoFuture<Output = ()> + 'static,
+    >(
+        &self,
+        args: Args,
+        f: fn(Args, crate::sim::ExternModuleSimulationState) -> Fut,
+    ) {
+        self.extern_module_simulation(crate::sim::SimGeneratorFn { args, f });
+    }
 }
 
 #[track_caller]
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index a5d7d13..b12e9a8 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -60,6 +60,7 @@ use std::{
     collections::BTreeSet,
     fmt,
     future::{Future, IntoFuture},
+    hash::Hash,
     marker::PhantomData,
     mem,
     ops::IndexMut,
@@ -1634,10 +1635,9 @@ impl<T> fmt::Debug for DebugOpaque<T> {
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
 struct CompiledExternModule {
-    io_ty: Bundle,
     module_io_targets: Interned<[Target]>,
     module_io: Interned<[CompiledValue<CanonicalType>]>,
-    simulation: ExternModuleSimulation<Bundle>,
+    simulation: ExternModuleSimulation,
 }
 
 #[derive(Debug)]
@@ -4713,7 +4713,6 @@ impl Compiler {
                     );
                 };
                 self.extern_modules.push(CompiledExternModule {
-                    io_ty: module.leaf_module().io_ty(),
                     module_io_targets: module
                         .leaf_module()
                         .module_io()
@@ -6822,8 +6821,7 @@ impl Ord for WaitTarget {
 
 struct SimulationExternModuleState {
     module_state: SimulationModuleState,
-    io_ty: Bundle,
-    sim: ExternModuleSimulation<Bundle>,
+    sim: ExternModuleSimulation,
     running_generator: Option<Pin<Box<dyn Future<Output = ()> + 'static>>>,
     wait_target: Option<WaitTarget>,
 }
@@ -6832,14 +6830,12 @@ impl fmt::Debug for SimulationExternModuleState {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
             module_state,
-            io_ty,
             sim,
             running_generator,
             wait_target,
         } = self;
         f.debug_struct("SimulationExternModuleState")
             .field("module_state", module_state)
-            .field("io_ty", io_ty)
             .field("sim", sim)
             .field(
                 "running_generator",
@@ -7008,7 +7004,6 @@ impl SimulationImpl {
         let io_target = Target::from(compiled.io);
         let extern_modules = Box::from_iter(compiled.extern_modules.iter().map(
             |&CompiledExternModule {
-                 io_ty,
                  module_io_targets,
                  module_io,
                  simulation,
@@ -7020,7 +7015,6 @@ impl SimulationImpl {
                             .copied()
                             .zip(module_io.iter().copied()),
                     ),
-                    io_ty,
                     sim: simulation,
                     running_generator: None,
                     wait_target: Some(WaitTarget::Settle),
@@ -7337,12 +7331,10 @@ impl SimulationImpl {
                     extern_module.wait_target = None;
                     let mut generator = if !extern_module.module_state.did_initial_settle {
                         let sim = extern_module.sim;
-                        let io_ty = extern_module.io_ty;
                         drop(this);
                         Box::into_pin(sim.run(ExternModuleSimulationState {
                             sim_impl: this_ref.clone(),
                             module_index,
-                            io_ty,
                         }))
                     } else if let Some(generator) = extern_module.running_generator.take() {
                         drop(this);
@@ -8013,52 +8005,25 @@ impl<T: BundleType> Simulation<T> {
     }
 }
 
-pub struct ExternModuleSimulationState<T: BundleType> {
+pub struct ExternModuleSimulationState {
     sim_impl: Rc<RefCell<SimulationImpl>>,
     module_index: usize,
-    io_ty: T,
 }
 
-impl<T: BundleType> fmt::Debug for ExternModuleSimulationState<T> {
+impl fmt::Debug for ExternModuleSimulationState {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
             sim_impl: _,
             module_index,
-            io_ty,
         } = self;
         f.debug_struct("ExternModuleSimulationState")
             .field("sim_impl", &DebugAsDisplay("..."))
             .field("module_index", module_index)
-            .field("io_ty", io_ty)
             .finish()
     }
 }
 
-impl<T: BundleType> ExternModuleSimulationState<T> {
-    pub fn canonical(self) -> ExternModuleSimulationState<Bundle> {
-        let Self {
-            sim_impl,
-            module_index,
-            io_ty,
-        } = self;
-        ExternModuleSimulationState {
-            sim_impl,
-            module_index,
-            io_ty: Bundle::from_canonical(io_ty.canonical()),
-        }
-    }
-    pub fn from_canonical(sim: ExternModuleSimulationState<Bundle>) -> Self {
-        let ExternModuleSimulationState {
-            sim_impl,
-            module_index,
-            io_ty,
-        } = sim;
-        Self {
-            sim_impl,
-            module_index,
-            io_ty: T::from_canonical(io_ty.canonical()),
-        }
-    }
+impl ExternModuleSimulationState {
     pub async fn settle(&mut self) {
         SimulationImpl::yield_advance_time_or_settle(self.sim_impl.clone(), self.module_index, None)
             .await
@@ -8084,39 +8049,74 @@ impl<T: BundleType> ExternModuleSimulationState<T> {
     );
 }
 
-pub trait ExternModuleSimGenerator:
-    Clone + Eq + std::hash::Hash + Any + Send + Sync + fmt::Debug
-{
-    type IOType: BundleType;
+pub trait ExternModuleSimGenerator: Clone + Eq + Hash + Any + Send + Sync + fmt::Debug {
+    fn run<'a>(&'a self, sim: ExternModuleSimulationState) -> impl IntoFuture<Output = ()> + 'a;
+}
 
-    fn run<'a>(
-        &'a self,
-        sim: ExternModuleSimulationState<Self::IOType>,
-    ) -> impl IntoFuture<Output = ()> + 'a;
+pub struct SimGeneratorFn<Args, Fut> {
+    pub args: Args,
+    pub f: fn(Args, ExternModuleSimulationState) -> Fut,
+}
+
+impl<Args: fmt::Debug, Fut> fmt::Debug for SimGeneratorFn<Args, Fut> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let Self { args, f: _ } = self;
+        f.debug_struct("SimGeneratorFn")
+            .field("args", args)
+            .field("f", &DebugAsDisplay("..."))
+            .finish()
+    }
+}
+
+impl<Args: Hash, Fut> Hash for SimGeneratorFn<Args, Fut> {
+    fn hash<H: std::hash::Hasher>(&self, state: &mut H) {
+        let Self { args, f } = self;
+        args.hash(state);
+        f.hash(state);
+    }
+}
+
+impl<Args: Eq, Fut> Eq for SimGeneratorFn<Args, Fut> {}
+
+impl<Args: PartialEq, Fut> PartialEq for SimGeneratorFn<Args, Fut> {
+    fn eq(&self, other: &Self) -> bool {
+        let Self { args, f } = self;
+        *args == other.args && *f == other.f
+    }
+}
+
+impl<Args: Clone, Fut> Clone for SimGeneratorFn<Args, Fut> {
+    fn clone(&self) -> Self {
+        Self {
+            args: self.args.clone(),
+            f: self.f,
+        }
+    }
+}
+
+impl<Args: Copy, Fut> Copy for SimGeneratorFn<Args, Fut> {}
+
+impl<
+        T: fmt::Debug + Clone + Eq + Hash + Send + Sync + 'static,
+        Fut: IntoFuture<Output = ()> + 'static,
+    > ExternModuleSimGenerator for SimGeneratorFn<T, Fut>
+{
+    fn run<'a>(&'a self, sim: ExternModuleSimulationState) -> impl IntoFuture<Output = ()> + 'a {
+        (self.f)(self.args.clone(), sim)
+    }
 }
 
 trait DynExternModuleSimGenerator: Any + Send + Sync + SupportsPtrEqWithTypeId + fmt::Debug {
-    fn dyn_run<'a>(
-        &'a self,
-        sim: ExternModuleSimulationState<Bundle>,
-    ) -> Box<dyn Future<Output = ()> + 'a>;
-    #[track_caller]
-    fn check_io_ty(&self, io_ty: Bundle);
+    fn dyn_run<'a>(&'a self, sim: ExternModuleSimulationState)
+        -> Box<dyn Future<Output = ()> + 'a>;
 }
 
 impl<T: ExternModuleSimGenerator> DynExternModuleSimGenerator for T {
     fn dyn_run<'a>(
         &'a self,
-        sim: ExternModuleSimulationState<Bundle>,
+        sim: ExternModuleSimulationState,
     ) -> Box<dyn Future<Output = ()> + 'a> {
-        Box::new(
-            self.run(ExternModuleSimulationState::from_canonical(sim))
-                .into_future(),
-        )
-    }
-    #[track_caller]
-    fn check_io_ty(&self, io_ty: Bundle) {
-        T::IOType::from_canonical(io_ty.canonical());
+        Box::new(self.run(sim).into_future())
     }
 }
 
@@ -8129,13 +8129,12 @@ impl InternedCompare for dyn DynExternModuleSimGenerator {
 }
 
 #[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)]
-pub struct ExternModuleSimulation<T: BundleType> {
+pub struct ExternModuleSimulation {
     generator: Interned<dyn DynExternModuleSimGenerator>,
     source_location: SourceLocation,
-    _phantom: PhantomData<T>,
 }
 
-impl<T: BundleType> ExternModuleSimulation<T> {
+impl ExternModuleSimulation {
     pub fn new_with_loc<G: ExternModuleSimGenerator>(
         source_location: SourceLocation,
         generator: G,
@@ -8146,48 +8145,13 @@ impl<T: BundleType> ExternModuleSimulation<T> {
                 |v| -> &dyn DynExternModuleSimGenerator { v },
             ),
             source_location,
-            _phantom: PhantomData,
         }
     }
     #[track_caller]
     pub fn new<G: ExternModuleSimGenerator>(generator: G) -> Self {
         Self::new_with_loc(SourceLocation::caller(), generator)
     }
-    pub fn canonical(self) -> ExternModuleSimulation<Bundle> {
-        let Self {
-            generator,
-            source_location,
-            _phantom: _,
-        } = self;
-        ExternModuleSimulation {
-            generator,
-            source_location,
-            _phantom: PhantomData,
-        }
-    }
-    pub fn from_canonical(v: ExternModuleSimulation<Bundle>) -> Self {
-        let ExternModuleSimulation {
-            generator,
-            source_location,
-            _phantom: _,
-        } = v;
-        Self {
-            generator,
-            source_location,
-            _phantom: PhantomData,
-        }
-    }
-}
-
-impl ExternModuleSimulation<Bundle> {
-    fn run(
-        &self,
-        sim: ExternModuleSimulationState<Bundle>,
-    ) -> Box<dyn Future<Output = ()> + 'static> {
+    fn run(&self, sim: ExternModuleSimulationState) -> Box<dyn Future<Output = ()> + 'static> {
         Interned::into_inner(self.generator).dyn_run(sim)
     }
-    #[track_caller]
-    pub fn check_io_ty(self, io_ty: Bundle) {
-        self.generator.check_io_ty(io_ty);
-    }
 }
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 0265a7a..e516f22 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -5,14 +5,11 @@ use fayalite::{
     int::UIntValue,
     prelude::*,
     reset::ResetType,
-    sim::{
-        time::SimDuration, vcd::VcdWriterDecls, ExternModuleSimGenerator,
-        ExternModuleSimulationState, Simulation, ToSimValue,
-    },
+    sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation, ToSimValue},
     ty::StaticType,
     util::RcWriter,
 };
-use std::{future::IntoFuture, num::NonZeroUsize};
+use std::num::NonZeroUsize;
 
 #[hdl_module(outline_generated)]
 pub fn connect_const() {
@@ -1453,33 +1450,17 @@ pub fn extern_module() {
     let i: Bool = m.input();
     #[hdl]
     let o: Bool = m.output();
-    #[derive(Clone, Eq, PartialEq, Hash, Debug)]
-    struct Sim {
-        i: Expr<Bool>,
-        o: Expr<Bool>,
-    }
-    impl ExternModuleSimGenerator for Sim {
-        type IOType = extern_module;
-
-        fn run<'a>(
-            &'a self,
-            mut sim: ExternModuleSimulationState<Self::IOType>,
-        ) -> impl IntoFuture<Output = ()> + 'a {
-            let Self { i, o } = *self;
-            async move {
-                sim.write(o, true).await;
-                sim.advance_time(SimDuration::from_nanos(500)).await;
-                let mut invert = false;
-                loop {
-                    sim.advance_time(SimDuration::from_micros(1)).await;
-                    let v = sim.read_bool(i).await;
-                    sim.write(o, v ^ invert).await;
-                    invert = !invert;
-                }
-            }
+    m.extern_module_simulation_fn((i, o), |(i, o), mut sim| async move {
+        sim.write(o, true).await;
+        sim.advance_time(SimDuration::from_nanos(500)).await;
+        let mut invert = false;
+        loop {
+            sim.advance_time(SimDuration::from_micros(1)).await;
+            let v = sim.read_bool(i).await;
+            sim.write(o, v ^ invert).await;
+            invert = !invert;
         }
-    }
-    m.extern_module_simulation(Sim { i, o });
+    });
 }
 
 #[test]
diff --git a/crates/fayalite/tests/sim/expected/extern_module.txt b/crates/fayalite/tests/sim/expected/extern_module.txt
index cb575a5..23af0b2 100644
--- a/crates/fayalite/tests/sim/expected/extern_module.txt
+++ b/crates/fayalite/tests/sim/expected/extern_module.txt
@@ -128,31 +128,27 @@ Simulation {
                 },
                 did_initial_settle: true,
             },
-            io_ty: Bundle {
-                #[hdl(flip)] /* offset = 0 */
-                i: Bool,
-                /* offset = 1 */
-                o: Bool,
-            },
             sim: ExternModuleSimulation {
-                generator: Sim {
-                    i: ModuleIO {
-                        name: extern_module::i,
-                        is_input: true,
-                        ty: Bool,
-                        ..
-                    },
-                    o: ModuleIO {
-                        name: extern_module::o,
-                        is_input: false,
-                        ty: Bool,
-                        ..
-                    },
+                generator: SimGeneratorFn {
+                    args: (
+                        ModuleIO {
+                            name: extern_module::i,
+                            is_input: true,
+                            ty: Bool,
+                            ..
+                        },
+                        ModuleIO {
+                            name: extern_module::o,
+                            is_input: false,
+                            ty: Bool,
+                            ..
+                        },
+                    ),
+                    f: ...,
                 },
                 source_location: SourceLocation(
                     module-XXXXXXXXXX.rs:4:1,
                 ),
-                _phantom: PhantomData<fayalite::bundle::Bundle>,
             },
             running_generator: Some(
                 ...,
diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json
index 451dc90..ff2050a 100644
--- a/crates/fayalite/visit_types.json
+++ b/crates/fayalite/visit_types.json
@@ -1274,8 +1274,7 @@
         "ExternModuleSimulation": {
             "data": {
                 "$kind": "Opaque"
-            },
-            "generics": "<T: BundleType>"
+            }
         }
     }
 }
\ No newline at end of file

From a115585d5a7c20742bfcdd64d09416bb7fdf3a54 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 25 Mar 2025 18:26:48 -0700
Subject: [PATCH 166/190] simulator: allow external module generators to wait
 for value changes and/or clock edges

---
 crates/fayalite/src/int.rs                    |   6 +
 crates/fayalite/src/sim.rs                    | 636 +++++++++++++-----
 crates/fayalite/tests/sim.rs                  |  47 ++
 .../tests/sim/expected/extern_module.txt      |   4 +-
 .../tests/sim/expected/extern_module2.txt     | 308 +++++++++
 .../tests/sim/expected/extern_module2.vcd     | 150 +++++
 6 files changed, 969 insertions(+), 182 deletions(-)
 create mode 100644 crates/fayalite/tests/sim/expected/extern_module2.txt
 create mode 100644 crates/fayalite/tests/sim/expected/extern_module2.vcd

diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index 5d10b29..236f240 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -621,6 +621,12 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
         let bitslice = &BitSlice::<u8, Lsb0>::from_slice(&bytes)[..width];
         bits.clone_from_bitslice(bitslice);
     }
+    fn bits_equal_bigint_wrapping(v: &BigInt, bits: &BitSlice) -> bool {
+        bits.iter()
+            .by_vals()
+            .enumerate()
+            .all(|(bit_index, bit): (usize, bool)| v.bit(bit_index as u64) == bit)
+    }
     fn bits_to_bigint(bits: &BitSlice) -> BigInt {
         let sign_byte = if Self::Signed::VALUE && bits.last().as_deref().copied().unwrap_or(false) {
             0xFF
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index b12e9a8..275b106 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -5904,12 +5904,21 @@ impl SimTraceKind {
     }
 }
 
-#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+#[derive(Clone, PartialEq, Eq, Hash)]
 pub struct SimValue<T: Type> {
     ty: T,
     bits: BitVec,
 }
 
+impl<T: Type> fmt::Debug for SimValue<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_struct("SimValue")
+            .field("ty", &self.ty)
+            .field("bits", &BitSliceWriteWithBase(&self.bits))
+            .finish()
+    }
+}
+
 impl SimValue<CanonicalType> {
     #[track_caller]
     fn to_expr_impl(ty: CanonicalType, bits: &BitSlice) -> Expr<CanonicalType> {
@@ -6795,35 +6804,149 @@ impl SimulationModuleState {
     }
 }
 
-#[derive(Copy, Clone, Debug, Eq, PartialEq)]
-enum WaitTarget {
-    /// Settle is less than Instant
+#[derive(Copy, Clone, Debug)]
+enum WaitTarget<ChangeKey, ChangeValue> {
     Settle,
     Instant(SimInstant),
+    Change { key: ChangeKey, value: ChangeValue },
 }
 
-impl PartialOrd for WaitTarget {
-    fn partial_cmp(&self, other: &Self) -> Option<std::cmp::Ordering> {
-        Some(self.cmp(other))
+#[derive(Clone)]
+struct EarliestWaitTargets {
+    settle: bool,
+    instant: Option<SimInstant>,
+    changes: HashMap<CompiledValue<CanonicalType>, SimValue<CanonicalType>>,
+}
+
+impl fmt::Debug for EarliestWaitTargets {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_set().entries(self.iter()).finish()
     }
 }
 
-impl Ord for WaitTarget {
-    fn cmp(&self, other: &Self) -> std::cmp::Ordering {
-        match (self, other) {
-            (WaitTarget::Settle, WaitTarget::Settle) => std::cmp::Ordering::Equal,
-            (WaitTarget::Settle, WaitTarget::Instant(_)) => std::cmp::Ordering::Less,
-            (WaitTarget::Instant(_), WaitTarget::Settle) => std::cmp::Ordering::Greater,
-            (WaitTarget::Instant(l), WaitTarget::Instant(r)) => l.cmp(r),
+impl Default for EarliestWaitTargets {
+    fn default() -> Self {
+        Self {
+            settle: false,
+            instant: None,
+            changes: HashMap::new(),
         }
     }
 }
 
+impl EarliestWaitTargets {
+    fn settle() -> Self {
+        Self {
+            settle: true,
+            instant: None,
+            changes: HashMap::new(),
+        }
+    }
+    fn instant(instant: SimInstant) -> Self {
+        Self {
+            settle: false,
+            instant: Some(instant),
+            changes: HashMap::new(),
+        }
+    }
+    fn len(&self) -> usize {
+        self.settle as usize + self.instant.is_some() as usize + self.changes.len()
+    }
+    fn is_empty(&self) -> bool {
+        self.len() == 0
+    }
+    fn clear(&mut self) {
+        let Self {
+            settle,
+            instant,
+            changes,
+        } = self;
+        *settle = false;
+        *instant = None;
+        changes.clear();
+    }
+    fn insert<ChangeValue>(
+        &mut self,
+        value: impl std::borrow::Borrow<WaitTarget<CompiledValue<CanonicalType>, ChangeValue>>,
+    ) where
+        ChangeValue: std::borrow::Borrow<SimValue<CanonicalType>>,
+    {
+        let value = value.borrow();
+        match value {
+            WaitTarget::Settle => self.settle = true,
+            WaitTarget::Instant(instant) => {
+                if self.instant.is_none_or(|v| v > *instant) {
+                    self.instant = Some(*instant);
+                }
+            }
+            WaitTarget::Change { key, value } => {
+                self.changes
+                    .entry(*key)
+                    .or_insert_with(|| value.borrow().clone());
+            }
+        }
+    }
+    fn convert_earlier_instants_to_settle(&mut self, instant: SimInstant) {
+        if self.instant.is_some_and(|v| v <= instant) {
+            self.settle = true;
+            self.instant = None;
+        }
+    }
+    fn iter<'a>(
+        &'a self,
+    ) -> impl Clone
+           + Iterator<Item = WaitTarget<CompiledValue<CanonicalType>, &'a SimValue<CanonicalType>>>
+           + 'a {
+        self.settle
+            .then_some(WaitTarget::Settle)
+            .into_iter()
+            .chain(self.instant.map(|instant| WaitTarget::Instant(instant)))
+            .chain(
+                self.changes
+                    .iter()
+                    .map(|(&key, value)| WaitTarget::Change { key, value }),
+            )
+    }
+}
+
+impl<ChangeValue: std::borrow::Borrow<SimValue<CanonicalType>>>
+    Extend<WaitTarget<CompiledValue<CanonicalType>, ChangeValue>> for EarliestWaitTargets
+{
+    fn extend<T: IntoIterator<Item = WaitTarget<CompiledValue<CanonicalType>, ChangeValue>>>(
+        &mut self,
+        iter: T,
+    ) {
+        iter.into_iter().for_each(|v| self.insert(v))
+    }
+}
+
+impl<'a, ChangeValue: std::borrow::Borrow<SimValue<CanonicalType>>>
+    Extend<&'a WaitTarget<CompiledValue<CanonicalType>, ChangeValue>> for EarliestWaitTargets
+{
+    fn extend<T: IntoIterator<Item = &'a WaitTarget<CompiledValue<CanonicalType>, ChangeValue>>>(
+        &mut self,
+        iter: T,
+    ) {
+        iter.into_iter().for_each(|v| self.insert(v))
+    }
+}
+
+impl<A> FromIterator<A> for EarliestWaitTargets
+where
+    Self: Extend<A>,
+{
+    fn from_iter<T: IntoIterator<Item = A>>(iter: T) -> Self {
+        let mut retval = Self::default();
+        retval.extend(iter);
+        retval
+    }
+}
+
 struct SimulationExternModuleState {
     module_state: SimulationModuleState,
     sim: ExternModuleSimulation,
     running_generator: Option<Pin<Box<dyn Future<Output = ()> + 'static>>>,
-    wait_target: Option<WaitTarget>,
+    wait_targets: EarliestWaitTargets,
 }
 
 impl fmt::Debug for SimulationExternModuleState {
@@ -6832,7 +6955,7 @@ impl fmt::Debug for SimulationExternModuleState {
             module_state,
             sim,
             running_generator,
-            wait_target,
+            wait_targets,
         } = self;
         f.debug_struct("SimulationExternModuleState")
             .field("module_state", module_state)
@@ -6841,7 +6964,7 @@ impl fmt::Debug for SimulationExternModuleState {
                 "running_generator",
                 &running_generator.as_ref().map(|_| DebugAsDisplay("...")),
             )
-            .field("wait_target", wait_target)
+            .field("wait_targets", wait_targets)
             .finish()
     }
 }
@@ -6896,29 +7019,19 @@ impl<I: BoolOrIntType> MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadBo
 struct ReadFn {
     compiled_value: CompiledValue<CanonicalType>,
     io: Expr<CanonicalType>,
+    bits: BitVec,
 }
 
 impl MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadFn {
     type Output = SimValue<CanonicalType>;
 
     fn call(self, state: &mut interpreter::State) -> Self::Output {
-        let Self { compiled_value, io } = self;
-        let mut bits = BitVec::repeat(false, compiled_value.layout.ty.bit_width());
-        SimulationImpl::read_write_sim_value_helper(
-            state,
+        let Self {
             compiled_value,
-            &mut bits,
-            |_signed, bits, value| <UInt>::copy_bits_from_bigint_wrapping(value, bits),
-            |_signed, bits, value| {
-                let bytes = value.to_le_bytes();
-                let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
-                bits.clone_from_bitslice(&bitslice[..bits.len()]);
-            },
-        );
-        SimValue {
-            ty: Expr::ty(io),
+            io,
             bits,
-        }
+        } = self;
+        SimulationImpl::read_no_settle_helper(state, io, compiled_value, bits)
     }
 }
 
@@ -7017,7 +7130,7 @@ impl SimulationImpl {
                     ),
                     sim: simulation,
                     running_generator: None,
-                    wait_target: Some(WaitTarget::Settle),
+                    wait_targets: EarliestWaitTargets::settle(),
                 }
             },
         ));
@@ -7200,22 +7313,23 @@ impl SimulationImpl {
     }
     #[track_caller]
     fn advance_time(this_ref: &Rc<RefCell<Self>>, duration: SimDuration) {
-        let instant = this_ref.borrow().instant + duration;
-        Self::run_until(this_ref, WaitTarget::Instant(instant));
+        let run_target = this_ref.borrow().instant + duration;
+        Self::run_until(this_ref, run_target);
     }
+    /// clears `targets`
     #[must_use]
-    fn yield_advance_time_or_settle(
+    fn yield_wait<'a>(
         this: Rc<RefCell<Self>>,
         module_index: usize,
-        duration: Option<SimDuration>,
-    ) -> impl Future<Output = ()> + 'static {
-        struct MyGenerator {
+        targets: &'a mut EarliestWaitTargets,
+    ) -> impl Future<Output = ()> + 'a {
+        struct MyGenerator<'a> {
             sim: Rc<RefCell<SimulationImpl>>,
             yielded_at_all: bool,
             module_index: usize,
-            target: WaitTarget,
+            targets: &'a mut EarliestWaitTargets,
         }
-        impl Future for MyGenerator {
+        impl Future for MyGenerator<'_> {
             type Output = ();
 
             fn poll(
@@ -7223,65 +7337,92 @@ impl SimulationImpl {
                 cx: &mut std::task::Context<'_>,
             ) -> Poll<Self::Output> {
                 let this = &mut *self;
-                let yielded_at_all = mem::replace(&mut this.yielded_at_all, true);
                 let mut sim = this.sim.borrow_mut();
                 let sim = &mut *sim;
                 assert!(cx.waker().will_wake(&sim.generator_waker), "can't use ExternModuleSimulationState's methods outside of ExternModuleSimulation");
-                if let WaitTarget::Instant(target) = this.target {
-                    if target < sim.instant {
-                        this.target = WaitTarget::Settle;
-                    } else if yielded_at_all && target == sim.instant {
-                        this.target = WaitTarget::Settle;
-                    }
+                this.targets.convert_earlier_instants_to_settle(sim.instant);
+                if this.targets.is_empty() {
+                    this.targets.settle = true;
                 }
-                if let WaitTarget::Settle = this.target {
-                    if yielded_at_all {
+                if this.targets.settle {
+                    if this.yielded_at_all {
+                        this.targets.clear();
                         return Poll::Ready(());
                     }
                 }
-                let wait_target = sim.extern_modules[this.module_index]
-                    .wait_target
-                    .get_or_insert(this.target);
-                *wait_target = (*wait_target).min(this.target);
+                sim.extern_modules[this.module_index]
+                    .wait_targets
+                    .extend(this.targets.iter());
+                this.targets.clear();
+                this.yielded_at_all = true;
                 Poll::Pending
             }
         }
-        let target = duration.map_or(WaitTarget::Settle, |duration| {
-            WaitTarget::Instant(this.borrow().instant + duration)
-        });
         MyGenerator {
             sim: this,
             yielded_at_all: false,
             module_index,
-            target,
+            targets,
         }
     }
-    /// returns the next `WaitTarget` and the set of things ready to run then.
-    fn get_ready_to_run_set(&self, ready_to_run_set: &mut ReadyToRunSet) -> Option<WaitTarget> {
+    async fn yield_advance_time_or_settle(
+        this: Rc<RefCell<Self>>,
+        module_index: usize,
+        duration: Option<SimDuration>,
+    ) {
+        let mut targets = duration.map_or(EarliestWaitTargets::settle(), |duration| {
+            EarliestWaitTargets::instant(this.borrow().instant + duration)
+        });
+        Self::yield_wait(this, module_index, &mut targets).await;
+    }
+    fn is_extern_module_ready_to_run(&mut self, module_index: usize) -> Option<SimInstant> {
+        let module = &self.extern_modules[module_index];
+        let mut retval = None;
+        for wait_target in module.wait_targets.iter() {
+            retval = match (wait_target, retval) {
+                (WaitTarget::Settle, _) => Some(self.instant),
+                (WaitTarget::Instant(instant), _) if instant <= self.instant => Some(self.instant),
+                (WaitTarget::Instant(instant), None) => Some(instant),
+                (WaitTarget::Instant(instant), Some(retval)) => Some(instant.min(retval)),
+                (WaitTarget::Change { key, value }, retval) => {
+                    if Self::value_changed(&mut self.state, key, &value.bits) {
+                        Some(self.instant)
+                    } else {
+                        retval
+                    }
+                }
+            };
+            if retval == Some(self.instant) {
+                break;
+            }
+        }
+        retval
+    }
+    fn get_ready_to_run_set(&mut self, ready_to_run_set: &mut ReadyToRunSet) -> Option<SimInstant> {
         ready_to_run_set.clear();
-        let mut wait_target = None;
+        let mut retval = None;
         if self.state_ready_to_run {
             ready_to_run_set.state_ready_to_run = true;
-            wait_target = Some(WaitTarget::Settle);
+            retval = Some(self.instant);
         }
-        for (module_index, extern_module) in self.extern_modules.iter().enumerate() {
-            let Some(extern_module_wait_target) = extern_module.wait_target else {
+        for module_index in 0..self.extern_modules.len() {
+            let Some(instant) = self.is_extern_module_ready_to_run(module_index) else {
                 continue;
             };
-            if let Some(wait_target) = &mut wait_target {
-                match extern_module_wait_target.cmp(wait_target) {
+            if let Some(retval) = &mut retval {
+                match instant.cmp(retval) {
                     std::cmp::Ordering::Less => ready_to_run_set.clear(),
                     std::cmp::Ordering::Equal => {}
                     std::cmp::Ordering::Greater => continue,
                 }
             } else {
-                wait_target = Some(extern_module_wait_target);
+                retval = Some(instant);
             }
             ready_to_run_set
                 .extern_modules_ready_to_run
                 .push(module_index);
         }
-        wait_target
+        retval
     }
     fn set_instant_no_sim(&mut self, instant: SimInstant) {
         self.instant = instant;
@@ -7296,8 +7437,98 @@ impl SimulationImpl {
             Ok(trace_writer_state)
         });
     }
+    #[must_use]
     #[track_caller]
-    fn run_until(this_ref: &Rc<RefCell<Self>>, run_target: WaitTarget) {
+    fn run_state_settle_cycle(&mut self) -> bool {
+        self.state_ready_to_run = false;
+        self.state.setup_call(0);
+        if self.breakpoints.is_some() {
+            loop {
+                match self
+                    .state
+                    .run(self.breakpoints.as_mut().expect("just checked"))
+                {
+                    RunResult::Break(break_action) => {
+                        println!(
+                            "hit breakpoint at:\n{:?}",
+                            self.state.debug_insn_at(self.state.pc),
+                        );
+                        match break_action {
+                            BreakAction::DumpStateAndContinue => {
+                                println!("{self:#?}");
+                            }
+                            BreakAction::Continue => {}
+                        }
+                    }
+                    RunResult::Return(()) => break,
+                }
+            }
+        } else {
+            let RunResult::Return(()) = self.state.run(());
+        }
+        if self
+            .clocks_triggered
+            .iter()
+            .any(|i| self.state.small_slots[*i] != 0)
+        {
+            self.state_ready_to_run = true;
+            true
+        } else {
+            false
+        }
+    }
+    #[track_caller]
+    fn run_extern_modules_cycle(
+        this_ref: &Rc<RefCell<Self>>,
+        generator_waker: &std::task::Waker,
+        extern_modules_ready_to_run: &[usize],
+    ) {
+        let mut this = this_ref.borrow_mut();
+        for module_index in extern_modules_ready_to_run.iter().copied() {
+            let extern_module = &mut this.extern_modules[module_index];
+            extern_module.wait_targets.clear();
+            let mut generator = if !extern_module.module_state.did_initial_settle {
+                let sim = extern_module.sim;
+                drop(this);
+                Box::into_pin(sim.run(ExternModuleSimulationState {
+                    sim_impl: this_ref.clone(),
+                    module_index,
+                    wait_for_changes_wait_targets: EarliestWaitTargets::default(),
+                }))
+            } else if let Some(generator) = extern_module.running_generator.take() {
+                drop(this);
+                generator
+            } else {
+                continue;
+            };
+            let generator = match generator
+                .as_mut()
+                .poll(&mut std::task::Context::from_waker(generator_waker))
+            {
+                Poll::Ready(()) => None,
+                Poll::Pending => Some(generator),
+            };
+            this = this_ref.borrow_mut();
+            this.extern_modules[module_index]
+                .module_state
+                .did_initial_settle = true;
+            if !this.extern_modules[module_index]
+                .module_state
+                .uninitialized_ios
+                .is_empty()
+            {
+                panic!(
+                    "extern module didn't initialize all outputs before \
+                    waiting, settling, or reading any inputs: {}",
+                    this.extern_modules[module_index].sim.source_location
+                );
+            }
+            this.extern_modules[module_index].running_generator = generator;
+        }
+    }
+    /// clears `targets`
+    #[track_caller]
+    fn run_until(this_ref: &Rc<RefCell<Self>>, run_target: SimInstant) {
         let mut this = this_ref.borrow_mut();
         let mut ready_to_run_set = ReadyToRunSet::default();
         let generator_waker = this.generator_waker.clone();
@@ -7305,10 +7536,7 @@ impl SimulationImpl {
             this.main_module.uninitialized_ios.is_empty(),
             "didn't initialize all inputs",
         );
-        match run_target {
-            WaitTarget::Settle => {}
-            WaitTarget::Instant(run_target) => assert!(run_target >= this.instant),
-        }
+        let run_target = run_target.max(this.instant);
         let mut settle_cycle = 0;
         let mut run_extern_modules = true;
         loop {
@@ -7318,92 +7546,25 @@ impl SimulationImpl {
                 Some(next_wait_target) if next_wait_target <= run_target => next_wait_target,
                 _ => break,
             };
-            match next_wait_target {
-                WaitTarget::Settle => {}
-                WaitTarget::Instant(instant) => {
-                    settle_cycle = 0;
-                    this.set_instant_no_sim(instant);
-                }
+            if next_wait_target > this.instant {
+                settle_cycle = 0;
+                this.set_instant_no_sim(next_wait_target);
             }
             if run_extern_modules {
-                for module_index in ready_to_run_set.extern_modules_ready_to_run.drain(..) {
-                    let extern_module = &mut this.extern_modules[module_index];
-                    extern_module.wait_target = None;
-                    let mut generator = if !extern_module.module_state.did_initial_settle {
-                        let sim = extern_module.sim;
-                        drop(this);
-                        Box::into_pin(sim.run(ExternModuleSimulationState {
-                            sim_impl: this_ref.clone(),
-                            module_index,
-                        }))
-                    } else if let Some(generator) = extern_module.running_generator.take() {
-                        drop(this);
-                        generator
-                    } else {
-                        continue;
-                    };
-                    let generator = match generator
-                        .as_mut()
-                        .poll(&mut std::task::Context::from_waker(&generator_waker))
-                    {
-                        Poll::Ready(()) => None,
-                        Poll::Pending => Some(generator),
-                    };
-                    this = this_ref.borrow_mut();
-                    this.extern_modules[module_index]
-                        .module_state
-                        .did_initial_settle = true;
-                    if !this.extern_modules[module_index]
-                        .module_state
-                        .uninitialized_ios
-                        .is_empty()
-                    {
-                        panic!(
-                            "extern module didn't initialize all outputs before \
-                            waiting, settling, or reading any inputs: {}",
-                            this.extern_modules[module_index].sim.source_location
-                        );
-                    }
-                    this.extern_modules[module_index].running_generator = generator;
-                }
+                drop(this);
+                Self::run_extern_modules_cycle(
+                    this_ref,
+                    &generator_waker,
+                    &ready_to_run_set.extern_modules_ready_to_run,
+                );
+                this = this_ref.borrow_mut();
             }
             if ready_to_run_set.state_ready_to_run {
-                this.state_ready_to_run = false;
-                run_extern_modules = true;
-                this.state.setup_call(0);
-                if this.breakpoints.is_some() {
-                    loop {
-                        let this = &mut *this;
-                        match this
-                            .state
-                            .run(this.breakpoints.as_mut().expect("just checked"))
-                        {
-                            RunResult::Break(break_action) => {
-                                println!(
-                                    "hit breakpoint at:\n{:?}",
-                                    this.state.debug_insn_at(this.state.pc),
-                                );
-                                match break_action {
-                                    BreakAction::DumpStateAndContinue => {
-                                        println!("{this:#?}");
-                                    }
-                                    BreakAction::Continue => {}
-                                }
-                            }
-                            RunResult::Return(()) => break,
-                        }
-                    }
-                } else {
-                    let RunResult::Return(()) = this.state.run(());
-                }
-                if this
-                    .clocks_triggered
-                    .iter()
-                    .any(|i| this.state.small_slots[*i] != 0)
-                {
-                    this.state_ready_to_run = true;
+                if this.run_state_settle_cycle() {
                     // wait for clocks to settle before running extern modules again
                     run_extern_modules = false;
+                } else {
+                    run_extern_modules = true;
                 }
             }
             if this.main_module.did_initial_settle {
@@ -7434,14 +7595,14 @@ impl SimulationImpl {
             });
             this.state.memory_write_log.clear();
         }
-        match run_target {
-            WaitTarget::Settle => {}
-            WaitTarget::Instant(instant) => this.set_instant_no_sim(instant),
+        if run_target > this.instant {
+            this.set_instant_no_sim(run_target);
         }
     }
     #[track_caller]
     fn settle(this_ref: &Rc<RefCell<Self>>) {
-        Self::run_until(this_ref, WaitTarget::Settle);
+        let run_target = this_ref.borrow().instant;
+        Self::run_until(this_ref, run_target);
     }
     fn get_module(&self, which_module: WhichModule) -> &SimulationModuleState {
         match which_module {
@@ -7522,12 +7683,13 @@ impl SimulationImpl {
         }
     }
     #[track_caller]
-    fn read_write_sim_value_helper(
+    fn read_write_sim_value_helper<Bits>(
         state: &mut interpreter::State,
         compiled_value: CompiledValue<CanonicalType>,
-        bits: &mut BitSlice,
-        read_write_big_scalar: impl Fn(bool, &mut BitSlice, &mut BigInt) + Copy,
-        read_write_small_scalar: impl Fn(bool, &mut BitSlice, &mut SmallUInt) + Copy,
+        start_bit_index: usize,
+        bits: &mut Bits,
+        read_write_big_scalar: impl Fn(bool, std::ops::Range<usize>, &mut Bits, &mut BigInt) + Copy,
+        read_write_small_scalar: impl Fn(bool, std::ops::Range<usize>, &mut Bits, &mut SmallUInt) + Copy,
     ) {
         match compiled_value.layout.body {
             CompiledTypeLayoutBody::Scalar => {
@@ -7544,14 +7706,18 @@ impl SimulationImpl {
                     CanonicalType::Clock(_) => false,
                     CanonicalType::PhantomConst(_) => unreachable!(),
                 };
+                let bit_indexes =
+                    start_bit_index..start_bit_index + compiled_value.layout.ty.bit_width();
                 match compiled_value.range.len() {
                     TypeLen::A_SMALL_SLOT => read_write_small_scalar(
                         signed,
+                        bit_indexes,
                         bits,
                         &mut state.small_slots[compiled_value.range.small_slots.start],
                     ),
                     TypeLen::A_BIG_SLOT => read_write_big_scalar(
                         signed,
+                        bit_indexes,
                         bits,
                         &mut state.big_slots[compiled_value.range.big_slots.start],
                     ),
@@ -7571,7 +7737,8 @@ impl SimulationImpl {
                                 .index_array(element.layout.len(), element_index),
                             write: None,
                         },
-                        &mut bits[element_index * element_bit_width..][..element_bit_width],
+                        start_bit_index + element_index * element_bit_width,
+                        bits,
                         read_write_big_scalar,
                         read_write_small_scalar,
                     );
@@ -7580,7 +7747,7 @@ impl SimulationImpl {
             CompiledTypeLayoutBody::Bundle { fields } => {
                 let ty = Bundle::from_canonical(compiled_value.layout.ty);
                 for (
-                    (field, offset),
+                    (_field, offset),
                     CompiledBundleField {
                         offset: layout_offset,
                         ty: field_layout,
@@ -7597,7 +7764,8 @@ impl SimulationImpl {
                             )),
                             write: None,
                         },
-                        &mut bits[offset..][..field.ty.bit_width()],
+                        start_bit_index + offset,
+                        bits,
                         read_write_big_scalar,
                         read_write_small_scalar,
                     );
@@ -7606,21 +7774,89 @@ impl SimulationImpl {
         }
     }
     #[track_caller]
+    fn read_no_settle_helper(
+        state: &mut interpreter::State,
+        io: Expr<CanonicalType>,
+        compiled_value: CompiledValue<CanonicalType>,
+        mut bits: BitVec,
+    ) -> SimValue<CanonicalType> {
+        bits.clear();
+        bits.resize(compiled_value.layout.ty.bit_width(), false);
+        SimulationImpl::read_write_sim_value_helper(
+            state,
+            compiled_value,
+            0,
+            &mut bits,
+            |_signed, bit_range, bits, value| {
+                <UInt>::copy_bits_from_bigint_wrapping(value, &mut bits[bit_range]);
+            },
+            |_signed, bit_range, bits, value| {
+                let bytes = value.to_le_bytes();
+                let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
+                let bitslice = &bitslice[..bit_range.len()];
+                bits[bit_range].clone_from_bitslice(bitslice);
+            },
+        );
+        SimValue {
+            ty: Expr::ty(io),
+            bits,
+        }
+    }
+    /// doesn't modify `bits`
+    fn value_changed(
+        state: &mut interpreter::State,
+        compiled_value: CompiledValue<CanonicalType>,
+        mut bits: &BitSlice,
+    ) -> bool {
+        assert_eq!(bits.len(), compiled_value.layout.ty.bit_width());
+        let any_change = std::cell::Cell::new(false);
+        SimulationImpl::read_write_sim_value_helper(
+            state,
+            compiled_value,
+            0,
+            &mut bits,
+            |_signed, bit_range, bits, value| {
+                if !<UInt>::bits_equal_bigint_wrapping(value, &bits[bit_range]) {
+                    any_change.set(true);
+                }
+            },
+            |_signed, bit_range, bits, value| {
+                let bytes = value.to_le_bytes();
+                let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
+                let bitslice = &bitslice[..bit_range.len()];
+                if bits[bit_range] != *bitslice {
+                    any_change.set(true);
+                }
+            },
+        );
+        any_change.get()
+    }
+    #[track_caller]
     fn read(
         &mut self,
         io: Expr<CanonicalType>,
         which_module: WhichModule,
-    ) -> MaybeNeedsSettle<ReadFn, SimValue<CanonicalType>> {
-        self.get_module(which_module)
-            .read_helper(io, which_module)
-            .map(|compiled_value| ReadFn { compiled_value, io })
-            .apply_no_settle(&mut self.state)
+    ) -> (
+        CompiledValue<CanonicalType>,
+        MaybeNeedsSettle<ReadFn, SimValue<CanonicalType>>,
+    ) {
+        let compiled_value = self.get_module(which_module).read_helper(io, which_module);
+        let value = compiled_value
+            .map(|compiled_value| ReadFn {
+                compiled_value,
+                io,
+                bits: BitVec::new(),
+            })
+            .apply_no_settle(&mut self.state);
+        let (MaybeNeedsSettle::NeedsSettle(compiled_value)
+        | MaybeNeedsSettle::NoSettleNeeded(compiled_value)) = compiled_value;
+        (compiled_value, value)
     }
     #[track_caller]
     fn write(
         &mut self,
         io: Expr<CanonicalType>,
-        value: SimValue<CanonicalType>,
+        value: &SimValue<CanonicalType>,
         which_module: WhichModule,
     ) {
         let compiled_value = self
@@ -7631,20 +7867,22 @@ impl SimulationImpl {
         Self::read_write_sim_value_helper(
             &mut self.state,
             compiled_value,
-            &mut value.into_bits(),
-            |signed, bits, value| {
+            0,
+            &mut value.bits(),
+            |signed, bit_range, bits, value| {
                 if signed {
-                    *value = SInt::bits_to_bigint(bits);
+                    *value = SInt::bits_to_bigint(&bits[bit_range]);
                 } else {
-                    *value = UInt::bits_to_bigint(bits);
+                    *value = UInt::bits_to_bigint(&bits[bit_range]);
                 }
             },
-            |signed, bits, value| {
+            |signed, bit_range, bits, value| {
                 let mut small_value = [0; mem::size_of::<SmallUInt>()];
-                if signed && bits.last().as_deref().copied() == Some(true) {
+                if signed && bits[bit_range.clone()].last().as_deref().copied() == Some(true) {
                     small_value.fill(u8::MAX);
                 }
-                small_value.view_bits_mut::<Lsb0>()[0..bits.len()].clone_from_bitslice(bits);
+                small_value.view_bits_mut::<Lsb0>()[0..bit_range.len()]
+                    .clone_from_bitslice(&bits[bit_range]);
                 *value = SmallUInt::from_le_bytes(small_value);
             },
         );
@@ -7920,14 +8158,14 @@ macro_rules! impl_simulation_methods {
             let retval = $self
                 .sim_impl
                 .borrow_mut()
-                .read(Expr::canonical(io), $which_module);
+                .read(Expr::canonical(io), $which_module).1;
             SimValue::from_canonical($self.settle_if_needed(retval)$(.$await)?)
         }
         $(#[$track_caller])?
         pub $($async)? fn write<IO: Type, V: ToSimValue<IO>>(&mut $self, io: Expr<IO>, value: V) {
             $self.sim_impl.borrow_mut().write(
                 Expr::canonical(io),
-                value.into_sim_value(Expr::ty(io)).into_canonical(),
+                &value.into_sim_value(Expr::ty(io)).into_canonical(),
                 $which_module,
             );
         }
@@ -8008,6 +8246,7 @@ impl<T: BundleType> Simulation<T> {
 pub struct ExternModuleSimulationState {
     sim_impl: Rc<RefCell<SimulationImpl>>,
     module_index: usize,
+    wait_for_changes_wait_targets: EarliestWaitTargets,
 }
 
 impl fmt::Debug for ExternModuleSimulationState {
@@ -8015,11 +8254,12 @@ impl fmt::Debug for ExternModuleSimulationState {
         let Self {
             sim_impl: _,
             module_index,
+            wait_for_changes_wait_targets: _,
         } = self;
         f.debug_struct("ExternModuleSimulationState")
             .field("sim_impl", &DebugAsDisplay("..."))
             .field("module_index", module_index)
-            .finish()
+            .finish_non_exhaustive()
     }
 }
 
@@ -8036,6 +8276,42 @@ impl ExternModuleSimulationState {
         )
         .await
     }
+    pub async fn wait_for_changes<I: IntoIterator<Item: ToExpr>>(
+        &mut self,
+        iter: I,
+        timeout: Option<SimDuration>,
+    ) {
+        self.wait_for_changes_wait_targets.clear();
+        let which_module = WhichModule::Extern {
+            module_index: self.module_index,
+        };
+        for io in iter {
+            let io = Expr::canonical(io.to_expr());
+            let (key, value) = self.sim_impl.borrow_mut().read(io, which_module);
+            let value = self.settle_if_needed(value).await;
+            self.wait_for_changes_wait_targets
+                .insert(WaitTarget::Change { key, value });
+        }
+        if let Some(timeout) = timeout {
+            self.wait_for_changes_wait_targets.instant =
+                Some(self.sim_impl.borrow().instant + timeout);
+        }
+        SimulationImpl::yield_wait(
+            self.sim_impl.clone(),
+            self.module_index,
+            &mut self.wait_for_changes_wait_targets,
+        )
+        .await;
+    }
+    pub async fn wait_for_clock_edge(&mut self, clk: impl ToExpr<Type = Clock>) {
+        let clk = clk.to_expr();
+        while self.read_clock(clk).await {
+            self.wait_for_changes([clk], None).await;
+        }
+        while !self.read_clock(clk).await {
+            self.wait_for_changes([clk], None).await;
+        }
+    }
     async fn settle_if_needed<F, O>(&mut self, v: MaybeNeedsSettle<F, O>) -> O
     where
         for<'a> F: MaybeNeedsSettleFn<&'a mut interpreter::State, Output = O>,
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index e516f22..6d20715 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -1485,3 +1485,50 @@ fn test_extern_module() {
         panic!();
     }
 }
+
+#[hdl_module(outline_generated, extern)]
+pub fn extern_module2() {
+    #[hdl]
+    let en: Bool = m.input();
+    #[hdl]
+    let clk: Clock = m.input();
+    #[hdl]
+    let o: UInt<8> = m.output();
+    m.extern_module_simulation_fn((en, clk, o), |(en, clk, o), mut sim| async move {
+        for b in "Hello, World!\n".bytes().cycle() {
+            sim.write(o, b).await;
+            loop {
+                sim.wait_for_clock_edge(clk).await;
+                if sim.read_bool(en).await {
+                    break;
+                }
+            }
+        }
+    });
+}
+
+#[test]
+fn test_extern_module2() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(extern_module2());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    for i in 0..30 {
+        sim.write(sim.io().en, i % 10 < 5);
+        sim.write(sim.io().clk, false);
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write(sim.io().clk, true);
+        sim.advance_time(SimDuration::from_micros(1));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/extern_module2.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/extern_module2.txt") {
+        panic!();
+    }
+}
diff --git a/crates/fayalite/tests/sim/expected/extern_module.txt b/crates/fayalite/tests/sim/expected/extern_module.txt
index 23af0b2..6cce70b 100644
--- a/crates/fayalite/tests/sim/expected/extern_module.txt
+++ b/crates/fayalite/tests/sim/expected/extern_module.txt
@@ -153,11 +153,11 @@ Simulation {
             running_generator: Some(
                 ...,
             ),
-            wait_target: Some(
+            wait_targets: {
                 Instant(
                     20.500000000000 μs,
                 ),
-            ),
+            },
         },
     ],
     state_ready_to_run: false,
diff --git a/crates/fayalite/tests/sim/expected/extern_module2.txt b/crates/fayalite/tests/sim/expected/extern_module2.txt
new file mode 100644
index 0000000..96710fb
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/extern_module2.txt
@@ -0,0 +1,308 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 3,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::en",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::o",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: Return,
+            ],
+            ..
+        },
+        pc: 0,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                0,
+                1,
+                101,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::extern_module2,
+        instantiated: Module {
+            name: extern_module2,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::extern_module2,
+                instantiated: Module {
+                    name: extern_module2,
+                    ..
+                },
+            }.en,
+            Instance {
+                name: <simulator>::extern_module2,
+                instantiated: Module {
+                    name: extern_module2,
+                    ..
+                },
+            }.clk,
+            Instance {
+                name: <simulator>::extern_module2,
+                instantiated: Module {
+                    name: extern_module2,
+                    ..
+                },
+            }.o,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::extern_module2,
+                instantiated: Module {
+                    name: extern_module2,
+                    ..
+                },
+            }.clk,
+            Instance {
+                name: <simulator>::extern_module2,
+                instantiated: Module {
+                    name: extern_module2,
+                    ..
+                },
+            }.en,
+            Instance {
+                name: <simulator>::extern_module2,
+                instantiated: Module {
+                    name: extern_module2,
+                    ..
+                },
+            }.o,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [
+        SimulationExternModuleState {
+            module_state: SimulationModuleState {
+                base_targets: [
+                    ModuleIO {
+                        name: extern_module2::en,
+                        is_input: true,
+                        ty: Bool,
+                        ..
+                    },
+                    ModuleIO {
+                        name: extern_module2::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: extern_module2::o,
+                        is_input: false,
+                        ty: UInt<8>,
+                        ..
+                    },
+                ],
+                uninitialized_ios: {},
+                io_targets: {
+                    ModuleIO {
+                        name: extern_module2::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: extern_module2::en,
+                        is_input: true,
+                        ty: Bool,
+                        ..
+                    },
+                    ModuleIO {
+                        name: extern_module2::o,
+                        is_input: false,
+                        ty: UInt<8>,
+                        ..
+                    },
+                },
+                did_initial_settle: true,
+            },
+            sim: ExternModuleSimulation {
+                generator: SimGeneratorFn {
+                    args: (
+                        ModuleIO {
+                            name: extern_module2::en,
+                            is_input: true,
+                            ty: Bool,
+                            ..
+                        },
+                        ModuleIO {
+                            name: extern_module2::clk,
+                            is_input: true,
+                            ty: Clock,
+                            ..
+                        },
+                        ModuleIO {
+                            name: extern_module2::o,
+                            is_input: false,
+                            ty: UInt<8>,
+                            ..
+                        },
+                    ),
+                    f: ...,
+                },
+                source_location: SourceLocation(
+                    module-XXXXXXXXXX.rs:5:1,
+                ),
+            },
+            running_generator: Some(
+                ...,
+            ),
+            wait_targets: {
+                Change {
+                    key: CompiledValue {
+                        layout: CompiledTypeLayout {
+                            ty: Clock,
+                            layout: TypeLayout {
+                                small_slots: StatePartLayout<SmallSlots> {
+                                    len: 0,
+                                    debug_data: [],
+                                    ..
+                                },
+                                big_slots: StatePartLayout<BigSlots> {
+                                    len: 1,
+                                    debug_data: [
+                                        SlotDebugData {
+                                            name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk",
+                                            ty: Clock,
+                                        },
+                                    ],
+                                    ..
+                                },
+                            },
+                            body: Scalar,
+                        },
+                        range: TypeIndexRange {
+                            small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                            big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+                        },
+                        write: None,
+                    },
+                    value: SimValue {
+                        ty: Clock,
+                        bits: 0x1,
+                    },
+                },
+            },
+        },
+    ],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "extern_module2",
+        children: [
+            TraceModuleIO {
+                name: "en",
+                child: TraceBool {
+                    location: TraceScalarId(0),
+                    name: "en",
+                    flow: Source,
+                },
+                ty: Bool,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "clk",
+                child: TraceClock {
+                    location: TraceScalarId(1),
+                    name: "clk",
+                    flow: Source,
+                },
+                ty: Clock,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "o",
+                child: TraceUInt {
+                    location: TraceScalarId(2),
+                    name: "o",
+                    ty: UInt<8>,
+                    flow: Sink,
+                },
+                ty: UInt<8>,
+                flow: Sink,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(2),
+                ty: UInt<8>,
+            },
+            state: 0x65,
+            last_state: 0x65,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 60 μs,
+    clocks_triggered: [],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/extern_module2.vcd b/crates/fayalite/tests/sim/expected/extern_module2.vcd
new file mode 100644
index 0000000..464f4bd
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/extern_module2.vcd
@@ -0,0 +1,150 @@
+$timescale 1 ps $end
+$scope module extern_module2 $end
+$var wire 1 ! en $end
+$var wire 1 " clk $end
+$var wire 8 # o $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+1!
+0"
+b1001000 #
+$end
+#1000000
+1"
+b1100101 #
+#2000000
+0"
+#3000000
+1"
+b1101100 #
+#4000000
+0"
+#5000000
+1"
+#6000000
+0"
+#7000000
+1"
+b1101111 #
+#8000000
+0"
+#9000000
+1"
+b101100 #
+#10000000
+0!
+0"
+#11000000
+1"
+#12000000
+0"
+#13000000
+1"
+#14000000
+0"
+#15000000
+1"
+#16000000
+0"
+#17000000
+1"
+#18000000
+0"
+#19000000
+1"
+#20000000
+1!
+0"
+#21000000
+1"
+b100000 #
+#22000000
+0"
+#23000000
+1"
+b1010111 #
+#24000000
+0"
+#25000000
+1"
+b1101111 #
+#26000000
+0"
+#27000000
+1"
+b1110010 #
+#28000000
+0"
+#29000000
+1"
+b1101100 #
+#30000000
+0!
+0"
+#31000000
+1"
+#32000000
+0"
+#33000000
+1"
+#34000000
+0"
+#35000000
+1"
+#36000000
+0"
+#37000000
+1"
+#38000000
+0"
+#39000000
+1"
+#40000000
+1!
+0"
+#41000000
+1"
+b1100100 #
+#42000000
+0"
+#43000000
+1"
+b100001 #
+#44000000
+0"
+#45000000
+1"
+b1010 #
+#46000000
+0"
+#47000000
+1"
+b1001000 #
+#48000000
+0"
+#49000000
+1"
+b1100101 #
+#50000000
+0!
+0"
+#51000000
+1"
+#52000000
+0"
+#53000000
+1"
+#54000000
+0"
+#55000000
+1"
+#56000000
+0"
+#57000000
+1"
+#58000000
+0"
+#59000000
+1"
+#60000000

From fdc73b5f3b1d708cded491a1a16292e77a1f3daf Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 25 Mar 2025 18:53:46 -0700
Subject: [PATCH 167/190] add ripple counter test to test simulating
 alternating circuits and extern modules

---
 crates/fayalite/tests/sim.rs                  |   81 +
 .../tests/sim/expected/ripple_counter.txt     | 1492 ++++++++++++++
 .../tests/sim/expected/ripple_counter.vcd     | 1753 +++++++++++++++++
 3 files changed, 3326 insertions(+)
 create mode 100644 crates/fayalite/tests/sim/expected/ripple_counter.txt
 create mode 100644 crates/fayalite/tests/sim/expected/ripple_counter.vcd

diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 6d20715..450be54 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -3,6 +3,7 @@
 
 use fayalite::{
     int::UIntValue,
+    module::{instance_with_loc, reg_builder_with_loc},
     prelude::*,
     reset::ResetType,
     sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation, ToSimValue},
@@ -1532,3 +1533,83 @@ fn test_extern_module2() {
         panic!();
     }
 }
+
+// use an extern module to simulate a register to test that the
+// simulator can handle chains of alternating circuits and extern modules.
+#[hdl_module(outline_generated, extern)]
+pub fn sw_reg() {
+    #[hdl]
+    let clk: Clock = m.input();
+    #[hdl]
+    let o: Bool = m.output();
+    m.extern_module_simulation_fn((clk, o), |(clk, o), mut sim| async move {
+        let mut state = false;
+        loop {
+            sim.write(o, state).await;
+            sim.wait_for_clock_edge(clk).await;
+            state = !state;
+        }
+    });
+}
+
+#[hdl_module(outline_generated)]
+pub fn ripple_counter() {
+    #[hdl]
+    let clk: Clock = m.input();
+    #[hdl]
+    let o: UInt<6> = m.output();
+
+    #[hdl]
+    let bits: Array<Bool, 6> = wire();
+
+    connect_any(o, bits.cast_to_bits());
+
+    let mut clk_in = clk;
+    for (i, bit) in bits.into_iter().enumerate() {
+        if i % 2 == 0 {
+            let bit_reg = reg_builder_with_loc(&format!("bit_reg_{i}"), SourceLocation::caller())
+                .clock_domain(
+                    #[hdl]
+                    ClockDomain {
+                        clk: clk_in,
+                        rst: false.to_sync_reset(),
+                    },
+                )
+                .no_reset(Bool)
+                .build();
+            connect(bit, bit_reg);
+            connect(bit_reg, !bit_reg);
+        } else {
+            let bit_reg =
+                instance_with_loc(&format!("bit_reg_{i}"), sw_reg(), SourceLocation::caller());
+            connect(bit_reg.clk, clk_in);
+            connect(bit, bit_reg.o);
+        }
+        clk_in = bit.to_clock();
+    }
+}
+
+#[test]
+fn test_ripple_counter() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut sim = Simulation::new(ripple_counter());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    for _ in 0..0x80 {
+        sim.write(sim.io().clk, false);
+        sim.advance_time(SimDuration::from_micros(1));
+        sim.write(sim.io().clk, true);
+        sim.advance_time(SimDuration::from_micros(1));
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/ripple_counter.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/ripple_counter.txt") {
+        panic!();
+    }
+}
diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.txt b/crates/fayalite/tests/sim/expected/ripple_counter.txt
new file mode 100644
index 0000000..e290ace
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/ripple_counter.txt
@@ -0,0 +1,1492 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 9,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                        ],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 58,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::o",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<4>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<5>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<5>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<6>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: ".rst",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::o",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: ".rst",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::o",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: ".clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: ".rst",
+                                ty: SyncReset,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.o",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::o",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:9:1
+                0: Copy {
+                    dest: StatePartIndex<BigSlots>(54), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.o", ty: Bool },
+                    src: StatePartIndex<BigSlots>(56), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::o", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                1: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(54), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.o", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                2: NotU {
+                    dest: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
+                    width: 1,
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                3: Copy {
+                    dest: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:7:1
+                4: Copy {
+                    dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                5: Copy {
+                    dest: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "", ty: Clock },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                6: Copy {
+                    dest: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "", ty: Clock },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                7: Copy {
+                    dest: StatePartIndex<BigSlots>(55), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock },
+                },
+                8: Copy {
+                    dest: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool },
+                    src: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::o", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                9: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                10: Copy {
+                    dest: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "", ty: Clock },
+                    src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
+                },
+                11: NotU {
+                    dest: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
+                    width: 1,
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                12: Copy {
+                    dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:7:1
+                13: Copy {
+                    dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                14: Copy {
+                    dest: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Clock },
+                    src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                15: Copy {
+                    dest: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Clock },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                16: Copy {
+                    dest: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk", ty: Clock },
+                },
+                17: Copy {
+                    dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool },
+                    src: StatePartIndex<BigSlots>(34), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::o", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                18: Copy {
+                    dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                19: Copy {
+                    dest: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Clock },
+                    src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
+                },
+                20: NotU {
+                    dest: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
+                    width: 1,
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                21: Copy {
+                    dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:7:1
+                22: Copy {
+                    dest: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
+                    src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                23: Copy {
+                    dest: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "", ty: Clock },
+                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                24: Copy {
+                    dest: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "", ty: Clock },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                25: Copy {
+                    dest: StatePartIndex<BigSlots>(33), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                26: Const {
+                    dest: StatePartIndex<BigSlots>(28), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    value: 0x0,
+                },
+                27: Copy {
+                    dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
+                    src: StatePartIndex<BigSlots>(28), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                28: Copy {
+                    dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::clk", ty: Clock },
+                },
+                29: Copy {
+                    dest: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
+                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                30: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock },
+                },
+                31: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                32: Copy {
+                    dest: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Clock },
+                },
+                33: Copy {
+                    dest: StatePartIndex<BigSlots>(39), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
+                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                34: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
+                },
+                35: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                36: Copy {
+                    dest: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
+                    src: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "", ty: Clock },
+                },
+                37: Copy {
+                    dest: StatePartIndex<BigSlots>(50), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset },
+                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: SyncReset },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                38: IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock },
+                },
+                39: AndSmall {
+                    dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(6), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                40: Copy {
+                    dest: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]", ty: Bool },
+                },
+                41: Shl {
+                    dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 5,
+                },
+                42: Copy {
+                    dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool },
+                },
+                43: Shl {
+                    dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
+                    lhs: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 4,
+                },
+                44: Copy {
+                    dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool },
+                },
+                45: Shl {
+                    dest: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 3,
+                },
+                46: Copy {
+                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool },
+                },
+                47: Shl {
+                    dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    lhs: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 2,
+                },
+                48: Copy {
+                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool },
+                },
+                49: Shl {
+                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 1,
+                },
+                50: Copy {
+                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool },
+                },
+                51: Or {
+                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                52: Or {
+                    dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    lhs: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                },
+                53: Or {
+                    dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    rhs: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                54: Or {
+                    dest: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
+                    lhs: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
+                },
+                55: Or {
+                    dest: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> },
+                    rhs: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
+                },
+                // at: module-XXXXXXXXXX.rs:5:1
+                56: Copy {
+                    dest: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::o", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
+                },
+                // at: module-XXXXXXXXXX.rs:6:1
+                57: BranchIfSmallZero {
+                    target: 59,
+                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                58: Copy {
+                    dest: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool },
+                },
+                59: BranchIfSmallZero {
+                    target: 61,
+                    value: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                60: Copy {
+                    dest: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool },
+                    src: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool },
+                },
+                61: BranchIfSmallZero {
+                    target: 63,
+                    value: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                62: Copy {
+                    dest: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool },
+                    src: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool },
+                },
+                63: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                64: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                65: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(6), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                66: Return,
+            ],
+            ..
+        },
+        pc: 66,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [
+                0,
+                0,
+                1,
+                1,
+                0,
+                0,
+                1,
+                0,
+                0,
+            ],
+        },
+        big_slots: StatePart {
+            value: [
+                1,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                1,
+                1,
+                0,
+                0,
+                0,
+                1,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                1,
+                0,
+                0,
+                0,
+                1,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                1,
+                0,
+                0,
+                0,
+                1,
+                0,
+                0,
+                0,
+                0,
+                0,
+            ],
+        },
+    },
+    io: Instance {
+        name: <simulator>::ripple_counter,
+        instantiated: Module {
+            name: ripple_counter,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::ripple_counter,
+                instantiated: Module {
+                    name: ripple_counter,
+                    ..
+                },
+            }.clk,
+            Instance {
+                name: <simulator>::ripple_counter,
+                instantiated: Module {
+                    name: ripple_counter,
+                    ..
+                },
+            }.o,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::ripple_counter,
+                instantiated: Module {
+                    name: ripple_counter,
+                    ..
+                },
+            }.clk,
+            Instance {
+                name: <simulator>::ripple_counter,
+                instantiated: Module {
+                    name: ripple_counter,
+                    ..
+                },
+            }.o,
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [
+        SimulationExternModuleState {
+            module_state: SimulationModuleState {
+                base_targets: [
+                    ModuleIO {
+                        name: sw_reg::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sw_reg::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                ],
+                uninitialized_ios: {},
+                io_targets: {
+                    ModuleIO {
+                        name: sw_reg::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sw_reg::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                },
+                did_initial_settle: true,
+            },
+            sim: ExternModuleSimulation {
+                generator: SimGeneratorFn {
+                    args: (
+                        ModuleIO {
+                            name: sw_reg::clk,
+                            is_input: true,
+                            ty: Clock,
+                            ..
+                        },
+                        ModuleIO {
+                            name: sw_reg::o,
+                            is_input: false,
+                            ty: Bool,
+                            ..
+                        },
+                    ),
+                    f: ...,
+                },
+                source_location: SourceLocation(
+                    module-XXXXXXXXXX-2.rs:4:1,
+                ),
+            },
+            running_generator: Some(
+                ...,
+            ),
+            wait_targets: {
+                Change {
+                    key: CompiledValue {
+                        layout: CompiledTypeLayout {
+                            ty: Clock,
+                            layout: TypeLayout {
+                                small_slots: StatePartLayout<SmallSlots> {
+                                    len: 0,
+                                    debug_data: [],
+                                    ..
+                                },
+                                big_slots: StatePartLayout<BigSlots> {
+                                    len: 1,
+                                    debug_data: [
+                                        SlotDebugData {
+                                            name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk",
+                                            ty: Clock,
+                                        },
+                                    ],
+                                    ..
+                                },
+                            },
+                            body: Scalar,
+                        },
+                        range: TypeIndexRange {
+                            small_slots: StatePartIndexRange<SmallSlots> { start: 3, len: 0 },
+                            big_slots: StatePartIndexRange<BigSlots> { start: 33, len: 1 },
+                        },
+                        write: None,
+                    },
+                    value: SimValue {
+                        ty: Clock,
+                        bits: 0x0,
+                    },
+                },
+            },
+        },
+        SimulationExternModuleState {
+            module_state: SimulationModuleState {
+                base_targets: [
+                    ModuleIO {
+                        name: sw_reg::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sw_reg::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                ],
+                uninitialized_ios: {},
+                io_targets: {
+                    ModuleIO {
+                        name: sw_reg::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sw_reg::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                },
+                did_initial_settle: true,
+            },
+            sim: ExternModuleSimulation {
+                generator: SimGeneratorFn {
+                    args: (
+                        ModuleIO {
+                            name: sw_reg::clk,
+                            is_input: true,
+                            ty: Clock,
+                            ..
+                        },
+                        ModuleIO {
+                            name: sw_reg::o,
+                            is_input: false,
+                            ty: Bool,
+                            ..
+                        },
+                    ),
+                    f: ...,
+                },
+                source_location: SourceLocation(
+                    module-XXXXXXXXXX-2.rs:4:1,
+                ),
+            },
+            running_generator: Some(
+                ...,
+            ),
+            wait_targets: {
+                Change {
+                    key: CompiledValue {
+                        layout: CompiledTypeLayout {
+                            ty: Clock,
+                            layout: TypeLayout {
+                                small_slots: StatePartLayout<SmallSlots> {
+                                    len: 0,
+                                    debug_data: [],
+                                    ..
+                                },
+                                big_slots: StatePartLayout<BigSlots> {
+                                    len: 1,
+                                    debug_data: [
+                                        SlotDebugData {
+                                            name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk",
+                                            ty: Clock,
+                                        },
+                                    ],
+                                    ..
+                                },
+                            },
+                            body: Scalar,
+                        },
+                        range: TypeIndexRange {
+                            small_slots: StatePartIndexRange<SmallSlots> { start: 6, len: 0 },
+                            big_slots: StatePartIndexRange<BigSlots> { start: 44, len: 1 },
+                        },
+                        write: None,
+                    },
+                    value: SimValue {
+                        ty: Clock,
+                        bits: 0x0,
+                    },
+                },
+            },
+        },
+        SimulationExternModuleState {
+            module_state: SimulationModuleState {
+                base_targets: [
+                    ModuleIO {
+                        name: sw_reg::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sw_reg::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                ],
+                uninitialized_ios: {},
+                io_targets: {
+                    ModuleIO {
+                        name: sw_reg::clk,
+                        is_input: true,
+                        ty: Clock,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sw_reg::o,
+                        is_input: false,
+                        ty: Bool,
+                        ..
+                    },
+                },
+                did_initial_settle: true,
+            },
+            sim: ExternModuleSimulation {
+                generator: SimGeneratorFn {
+                    args: (
+                        ModuleIO {
+                            name: sw_reg::clk,
+                            is_input: true,
+                            ty: Clock,
+                            ..
+                        },
+                        ModuleIO {
+                            name: sw_reg::o,
+                            is_input: false,
+                            ty: Bool,
+                            ..
+                        },
+                    ),
+                    f: ...,
+                },
+                source_location: SourceLocation(
+                    module-XXXXXXXXXX-2.rs:4:1,
+                ),
+            },
+            running_generator: Some(
+                ...,
+            ),
+            wait_targets: {
+                Change {
+                    key: CompiledValue {
+                        layout: CompiledTypeLayout {
+                            ty: Clock,
+                            layout: TypeLayout {
+                                small_slots: StatePartLayout<SmallSlots> {
+                                    len: 0,
+                                    debug_data: [],
+                                    ..
+                                },
+                                big_slots: StatePartLayout<BigSlots> {
+                                    len: 1,
+                                    debug_data: [
+                                        SlotDebugData {
+                                            name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk",
+                                            ty: Clock,
+                                        },
+                                    ],
+                                    ..
+                                },
+                            },
+                            body: Scalar,
+                        },
+                        range: TypeIndexRange {
+                            small_slots: StatePartIndexRange<SmallSlots> { start: 9, len: 0 },
+                            big_slots: StatePartIndexRange<BigSlots> { start: 55, len: 1 },
+                        },
+                        write: None,
+                    },
+                    value: SimValue {
+                        ty: Clock,
+                        bits: 0x0,
+                    },
+                },
+            },
+        },
+    ],
+    state_ready_to_run: false,
+    trace_decls: TraceModule {
+        name: "ripple_counter",
+        children: [
+            TraceModuleIO {
+                name: "clk",
+                child: TraceClock {
+                    location: TraceScalarId(0),
+                    name: "clk",
+                    flow: Source,
+                },
+                ty: Clock,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "o",
+                child: TraceUInt {
+                    location: TraceScalarId(1),
+                    name: "o",
+                    ty: UInt<6>,
+                    flow: Sink,
+                },
+                ty: UInt<6>,
+                flow: Sink,
+            },
+            TraceWire {
+                name: "bits",
+                child: TraceArray {
+                    name: "bits",
+                    elements: [
+                        TraceBool {
+                            location: TraceScalarId(2),
+                            name: "[0]",
+                            flow: Duplex,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(3),
+                            name: "[1]",
+                            flow: Duplex,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(4),
+                            name: "[2]",
+                            flow: Duplex,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(5),
+                            name: "[3]",
+                            flow: Duplex,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(6),
+                            name: "[4]",
+                            flow: Duplex,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(7),
+                            name: "[5]",
+                            flow: Duplex,
+                        },
+                    ],
+                    ty: Array<Bool, 6>,
+                    flow: Duplex,
+                },
+                ty: Array<Bool, 6>,
+            },
+            TraceReg {
+                name: "bit_reg_0",
+                child: TraceBool {
+                    location: TraceScalarId(8),
+                    name: "bit_reg_0",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+            TraceInstance {
+                name: "bit_reg_1",
+                instance_io: TraceBundle {
+                    name: "bit_reg_1",
+                    fields: [
+                        TraceClock {
+                            location: TraceScalarId(11),
+                            name: "clk",
+                            flow: Sink,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(12),
+                            name: "o",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        #[hdl(flip)] /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        o: Bool,
+                    },
+                    flow: Source,
+                },
+                module: TraceModule {
+                    name: "sw_reg",
+                    children: [
+                        TraceModuleIO {
+                            name: "clk",
+                            child: TraceClock {
+                                location: TraceScalarId(9),
+                                name: "clk",
+                                flow: Source,
+                            },
+                            ty: Clock,
+                            flow: Source,
+                        },
+                        TraceModuleIO {
+                            name: "o",
+                            child: TraceBool {
+                                location: TraceScalarId(10),
+                                name: "o",
+                                flow: Sink,
+                            },
+                            ty: Bool,
+                            flow: Sink,
+                        },
+                    ],
+                },
+                ty: Bundle {
+                    #[hdl(flip)] /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    o: Bool,
+                },
+            },
+            TraceReg {
+                name: "bit_reg_2",
+                child: TraceBool {
+                    location: TraceScalarId(13),
+                    name: "bit_reg_2",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+            TraceInstance {
+                name: "bit_reg_3",
+                instance_io: TraceBundle {
+                    name: "bit_reg_3",
+                    fields: [
+                        TraceClock {
+                            location: TraceScalarId(16),
+                            name: "clk",
+                            flow: Sink,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(17),
+                            name: "o",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        #[hdl(flip)] /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        o: Bool,
+                    },
+                    flow: Source,
+                },
+                module: TraceModule {
+                    name: "sw_reg",
+                    children: [
+                        TraceModuleIO {
+                            name: "clk",
+                            child: TraceClock {
+                                location: TraceScalarId(14),
+                                name: "clk",
+                                flow: Source,
+                            },
+                            ty: Clock,
+                            flow: Source,
+                        },
+                        TraceModuleIO {
+                            name: "o",
+                            child: TraceBool {
+                                location: TraceScalarId(15),
+                                name: "o",
+                                flow: Sink,
+                            },
+                            ty: Bool,
+                            flow: Sink,
+                        },
+                    ],
+                },
+                ty: Bundle {
+                    #[hdl(flip)] /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    o: Bool,
+                },
+            },
+            TraceReg {
+                name: "bit_reg_4",
+                child: TraceBool {
+                    location: TraceScalarId(18),
+                    name: "bit_reg_4",
+                    flow: Duplex,
+                },
+                ty: Bool,
+            },
+            TraceInstance {
+                name: "bit_reg_5",
+                instance_io: TraceBundle {
+                    name: "bit_reg_5",
+                    fields: [
+                        TraceClock {
+                            location: TraceScalarId(21),
+                            name: "clk",
+                            flow: Sink,
+                        },
+                        TraceBool {
+                            location: TraceScalarId(22),
+                            name: "o",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Bundle {
+                        #[hdl(flip)] /* offset = 0 */
+                        clk: Clock,
+                        /* offset = 1 */
+                        o: Bool,
+                    },
+                    flow: Source,
+                },
+                module: TraceModule {
+                    name: "sw_reg",
+                    children: [
+                        TraceModuleIO {
+                            name: "clk",
+                            child: TraceClock {
+                                location: TraceScalarId(19),
+                                name: "clk",
+                                flow: Source,
+                            },
+                            ty: Clock,
+                            flow: Source,
+                        },
+                        TraceModuleIO {
+                            name: "o",
+                            child: TraceBool {
+                                location: TraceScalarId(20),
+                                name: "o",
+                                flow: Sink,
+                            },
+                            ty: Bool,
+                            flow: Sink,
+                        },
+                    ],
+                },
+                ty: Bundle {
+                    #[hdl(flip)] /* offset = 0 */
+                    clk: Clock,
+                    /* offset = 1 */
+                    o: Bool,
+                },
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(1),
+                ty: UInt<6>,
+            },
+            state: 0x00,
+            last_state: 0x00,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(3),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(4),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(5),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(6),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(6),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(7),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(7),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(24),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(33),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(34),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(31),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(12),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(32),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(13),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(36),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(14),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(44),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(15),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(45),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(16),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(42),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(17),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(43),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(18),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(47),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(19),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(55),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(20),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(56),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(21),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(53),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(22),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(54),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    instant: 256 μs,
+    clocks_triggered: [
+        StatePartIndex<SmallSlots>(1),
+        StatePartIndex<SmallSlots>(4),
+        StatePartIndex<SmallSlots>(7),
+    ],
+    ..
+}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.vcd b/crates/fayalite/tests/sim/expected/ripple_counter.vcd
new file mode 100644
index 0000000..6f14a8e
--- /dev/null
+++ b/crates/fayalite/tests/sim/expected/ripple_counter.vcd
@@ -0,0 +1,1753 @@
+$timescale 1 ps $end
+$scope module ripple_counter $end
+$var wire 1 ! clk $end
+$var wire 6 " o $end
+$scope struct bits $end
+$var wire 1 # \[0] $end
+$var wire 1 $ \[1] $end
+$var wire 1 % \[2] $end
+$var wire 1 & \[3] $end
+$var wire 1 ' \[4] $end
+$var wire 1 ( \[5] $end
+$upscope $end
+$var reg 1 ) bit_reg_0 $end
+$scope struct bit_reg_1 $end
+$var wire 1 , clk $end
+$var wire 1 - o $end
+$upscope $end
+$scope module sw_reg $end
+$var wire 1 * clk $end
+$var wire 1 + o $end
+$upscope $end
+$var reg 1 . bit_reg_2 $end
+$scope struct bit_reg_3 $end
+$var wire 1 1 clk $end
+$var wire 1 2 o $end
+$upscope $end
+$scope module sw_reg_2 $end
+$var wire 1 / clk $end
+$var wire 1 0 o $end
+$upscope $end
+$var reg 1 3 bit_reg_4 $end
+$scope struct bit_reg_5 $end
+$var wire 1 6 clk $end
+$var wire 1 7 o $end
+$upscope $end
+$scope module sw_reg_3 $end
+$var wire 1 4 clk $end
+$var wire 1 5 o $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+b0 "
+0#
+0$
+0%
+0&
+0'
+0(
+0)
+0*
+0+
+0,
+0-
+0.
+0/
+00
+01
+02
+03
+04
+05
+06
+07
+$end
+#1000000
+1!
+1)
+b1 "
+1#
+1*
+1,
+1+
+b11 "
+1$
+1-
+1.
+b111 "
+1%
+1/
+11
+10
+b1111 "
+1&
+12
+13
+b11111 "
+1'
+14
+16
+15
+b111111 "
+1(
+17
+#2000000
+0!
+#3000000
+1!
+0)
+b111110 "
+0#
+0*
+0,
+#4000000
+0!
+#5000000
+1!
+1)
+b111111 "
+1#
+1*
+1,
+0+
+b111101 "
+0$
+0-
+#6000000
+0!
+#7000000
+1!
+0)
+b111100 "
+0#
+0*
+0,
+#8000000
+0!
+#9000000
+1!
+1)
+b111101 "
+1#
+1*
+1,
+1+
+b111111 "
+1$
+1-
+0.
+b111011 "
+0%
+0/
+01
+#10000000
+0!
+#11000000
+1!
+0)
+b111010 "
+0#
+0*
+0,
+#12000000
+0!
+#13000000
+1!
+1)
+b111011 "
+1#
+1*
+1,
+0+
+b111001 "
+0$
+0-
+#14000000
+0!
+#15000000
+1!
+0)
+b111000 "
+0#
+0*
+0,
+#16000000
+0!
+#17000000
+1!
+1)
+b111001 "
+1#
+1*
+1,
+1+
+b111011 "
+1$
+1-
+1.
+b111111 "
+1%
+1/
+11
+00
+b110111 "
+0&
+02
+#18000000
+0!
+#19000000
+1!
+0)
+b110110 "
+0#
+0*
+0,
+#20000000
+0!
+#21000000
+1!
+1)
+b110111 "
+1#
+1*
+1,
+0+
+b110101 "
+0$
+0-
+#22000000
+0!
+#23000000
+1!
+0)
+b110100 "
+0#
+0*
+0,
+#24000000
+0!
+#25000000
+1!
+1)
+b110101 "
+1#
+1*
+1,
+1+
+b110111 "
+1$
+1-
+0.
+b110011 "
+0%
+0/
+01
+#26000000
+0!
+#27000000
+1!
+0)
+b110010 "
+0#
+0*
+0,
+#28000000
+0!
+#29000000
+1!
+1)
+b110011 "
+1#
+1*
+1,
+0+
+b110001 "
+0$
+0-
+#30000000
+0!
+#31000000
+1!
+0)
+b110000 "
+0#
+0*
+0,
+#32000000
+0!
+#33000000
+1!
+1)
+b110001 "
+1#
+1*
+1,
+1+
+b110011 "
+1$
+1-
+1.
+b110111 "
+1%
+1/
+11
+10
+b111111 "
+1&
+12
+03
+b101111 "
+0'
+04
+06
+#34000000
+0!
+#35000000
+1!
+0)
+b101110 "
+0#
+0*
+0,
+#36000000
+0!
+#37000000
+1!
+1)
+b101111 "
+1#
+1*
+1,
+0+
+b101101 "
+0$
+0-
+#38000000
+0!
+#39000000
+1!
+0)
+b101100 "
+0#
+0*
+0,
+#40000000
+0!
+#41000000
+1!
+1)
+b101101 "
+1#
+1*
+1,
+1+
+b101111 "
+1$
+1-
+0.
+b101011 "
+0%
+0/
+01
+#42000000
+0!
+#43000000
+1!
+0)
+b101010 "
+0#
+0*
+0,
+#44000000
+0!
+#45000000
+1!
+1)
+b101011 "
+1#
+1*
+1,
+0+
+b101001 "
+0$
+0-
+#46000000
+0!
+#47000000
+1!
+0)
+b101000 "
+0#
+0*
+0,
+#48000000
+0!
+#49000000
+1!
+1)
+b101001 "
+1#
+1*
+1,
+1+
+b101011 "
+1$
+1-
+1.
+b101111 "
+1%
+1/
+11
+00
+b100111 "
+0&
+02
+#50000000
+0!
+#51000000
+1!
+0)
+b100110 "
+0#
+0*
+0,
+#52000000
+0!
+#53000000
+1!
+1)
+b100111 "
+1#
+1*
+1,
+0+
+b100101 "
+0$
+0-
+#54000000
+0!
+#55000000
+1!
+0)
+b100100 "
+0#
+0*
+0,
+#56000000
+0!
+#57000000
+1!
+1)
+b100101 "
+1#
+1*
+1,
+1+
+b100111 "
+1$
+1-
+0.
+b100011 "
+0%
+0/
+01
+#58000000
+0!
+#59000000
+1!
+0)
+b100010 "
+0#
+0*
+0,
+#60000000
+0!
+#61000000
+1!
+1)
+b100011 "
+1#
+1*
+1,
+0+
+b100001 "
+0$
+0-
+#62000000
+0!
+#63000000
+1!
+0)
+b100000 "
+0#
+0*
+0,
+#64000000
+0!
+#65000000
+1!
+1)
+b100001 "
+1#
+1*
+1,
+1+
+b100011 "
+1$
+1-
+1.
+b100111 "
+1%
+1/
+11
+10
+b101111 "
+1&
+12
+13
+b111111 "
+1'
+14
+16
+05
+b11111 "
+0(
+07
+#66000000
+0!
+#67000000
+1!
+0)
+b11110 "
+0#
+0*
+0,
+#68000000
+0!
+#69000000
+1!
+1)
+b11111 "
+1#
+1*
+1,
+0+
+b11101 "
+0$
+0-
+#70000000
+0!
+#71000000
+1!
+0)
+b11100 "
+0#
+0*
+0,
+#72000000
+0!
+#73000000
+1!
+1)
+b11101 "
+1#
+1*
+1,
+1+
+b11111 "
+1$
+1-
+0.
+b11011 "
+0%
+0/
+01
+#74000000
+0!
+#75000000
+1!
+0)
+b11010 "
+0#
+0*
+0,
+#76000000
+0!
+#77000000
+1!
+1)
+b11011 "
+1#
+1*
+1,
+0+
+b11001 "
+0$
+0-
+#78000000
+0!
+#79000000
+1!
+0)
+b11000 "
+0#
+0*
+0,
+#80000000
+0!
+#81000000
+1!
+1)
+b11001 "
+1#
+1*
+1,
+1+
+b11011 "
+1$
+1-
+1.
+b11111 "
+1%
+1/
+11
+00
+b10111 "
+0&
+02
+#82000000
+0!
+#83000000
+1!
+0)
+b10110 "
+0#
+0*
+0,
+#84000000
+0!
+#85000000
+1!
+1)
+b10111 "
+1#
+1*
+1,
+0+
+b10101 "
+0$
+0-
+#86000000
+0!
+#87000000
+1!
+0)
+b10100 "
+0#
+0*
+0,
+#88000000
+0!
+#89000000
+1!
+1)
+b10101 "
+1#
+1*
+1,
+1+
+b10111 "
+1$
+1-
+0.
+b10011 "
+0%
+0/
+01
+#90000000
+0!
+#91000000
+1!
+0)
+b10010 "
+0#
+0*
+0,
+#92000000
+0!
+#93000000
+1!
+1)
+b10011 "
+1#
+1*
+1,
+0+
+b10001 "
+0$
+0-
+#94000000
+0!
+#95000000
+1!
+0)
+b10000 "
+0#
+0*
+0,
+#96000000
+0!
+#97000000
+1!
+1)
+b10001 "
+1#
+1*
+1,
+1+
+b10011 "
+1$
+1-
+1.
+b10111 "
+1%
+1/
+11
+10
+b11111 "
+1&
+12
+03
+b1111 "
+0'
+04
+06
+#98000000
+0!
+#99000000
+1!
+0)
+b1110 "
+0#
+0*
+0,
+#100000000
+0!
+#101000000
+1!
+1)
+b1111 "
+1#
+1*
+1,
+0+
+b1101 "
+0$
+0-
+#102000000
+0!
+#103000000
+1!
+0)
+b1100 "
+0#
+0*
+0,
+#104000000
+0!
+#105000000
+1!
+1)
+b1101 "
+1#
+1*
+1,
+1+
+b1111 "
+1$
+1-
+0.
+b1011 "
+0%
+0/
+01
+#106000000
+0!
+#107000000
+1!
+0)
+b1010 "
+0#
+0*
+0,
+#108000000
+0!
+#109000000
+1!
+1)
+b1011 "
+1#
+1*
+1,
+0+
+b1001 "
+0$
+0-
+#110000000
+0!
+#111000000
+1!
+0)
+b1000 "
+0#
+0*
+0,
+#112000000
+0!
+#113000000
+1!
+1)
+b1001 "
+1#
+1*
+1,
+1+
+b1011 "
+1$
+1-
+1.
+b1111 "
+1%
+1/
+11
+00
+b111 "
+0&
+02
+#114000000
+0!
+#115000000
+1!
+0)
+b110 "
+0#
+0*
+0,
+#116000000
+0!
+#117000000
+1!
+1)
+b111 "
+1#
+1*
+1,
+0+
+b101 "
+0$
+0-
+#118000000
+0!
+#119000000
+1!
+0)
+b100 "
+0#
+0*
+0,
+#120000000
+0!
+#121000000
+1!
+1)
+b101 "
+1#
+1*
+1,
+1+
+b111 "
+1$
+1-
+0.
+b11 "
+0%
+0/
+01
+#122000000
+0!
+#123000000
+1!
+0)
+b10 "
+0#
+0*
+0,
+#124000000
+0!
+#125000000
+1!
+1)
+b11 "
+1#
+1*
+1,
+0+
+b1 "
+0$
+0-
+#126000000
+0!
+#127000000
+1!
+0)
+b0 "
+0#
+0*
+0,
+#128000000
+0!
+#129000000
+1!
+1)
+b1 "
+1#
+1*
+1,
+1+
+b11 "
+1$
+1-
+1.
+b111 "
+1%
+1/
+11
+10
+b1111 "
+1&
+12
+13
+b11111 "
+1'
+14
+16
+15
+b111111 "
+1(
+17
+#130000000
+0!
+#131000000
+1!
+0)
+b111110 "
+0#
+0*
+0,
+#132000000
+0!
+#133000000
+1!
+1)
+b111111 "
+1#
+1*
+1,
+0+
+b111101 "
+0$
+0-
+#134000000
+0!
+#135000000
+1!
+0)
+b111100 "
+0#
+0*
+0,
+#136000000
+0!
+#137000000
+1!
+1)
+b111101 "
+1#
+1*
+1,
+1+
+b111111 "
+1$
+1-
+0.
+b111011 "
+0%
+0/
+01
+#138000000
+0!
+#139000000
+1!
+0)
+b111010 "
+0#
+0*
+0,
+#140000000
+0!
+#141000000
+1!
+1)
+b111011 "
+1#
+1*
+1,
+0+
+b111001 "
+0$
+0-
+#142000000
+0!
+#143000000
+1!
+0)
+b111000 "
+0#
+0*
+0,
+#144000000
+0!
+#145000000
+1!
+1)
+b111001 "
+1#
+1*
+1,
+1+
+b111011 "
+1$
+1-
+1.
+b111111 "
+1%
+1/
+11
+00
+b110111 "
+0&
+02
+#146000000
+0!
+#147000000
+1!
+0)
+b110110 "
+0#
+0*
+0,
+#148000000
+0!
+#149000000
+1!
+1)
+b110111 "
+1#
+1*
+1,
+0+
+b110101 "
+0$
+0-
+#150000000
+0!
+#151000000
+1!
+0)
+b110100 "
+0#
+0*
+0,
+#152000000
+0!
+#153000000
+1!
+1)
+b110101 "
+1#
+1*
+1,
+1+
+b110111 "
+1$
+1-
+0.
+b110011 "
+0%
+0/
+01
+#154000000
+0!
+#155000000
+1!
+0)
+b110010 "
+0#
+0*
+0,
+#156000000
+0!
+#157000000
+1!
+1)
+b110011 "
+1#
+1*
+1,
+0+
+b110001 "
+0$
+0-
+#158000000
+0!
+#159000000
+1!
+0)
+b110000 "
+0#
+0*
+0,
+#160000000
+0!
+#161000000
+1!
+1)
+b110001 "
+1#
+1*
+1,
+1+
+b110011 "
+1$
+1-
+1.
+b110111 "
+1%
+1/
+11
+10
+b111111 "
+1&
+12
+03
+b101111 "
+0'
+04
+06
+#162000000
+0!
+#163000000
+1!
+0)
+b101110 "
+0#
+0*
+0,
+#164000000
+0!
+#165000000
+1!
+1)
+b101111 "
+1#
+1*
+1,
+0+
+b101101 "
+0$
+0-
+#166000000
+0!
+#167000000
+1!
+0)
+b101100 "
+0#
+0*
+0,
+#168000000
+0!
+#169000000
+1!
+1)
+b101101 "
+1#
+1*
+1,
+1+
+b101111 "
+1$
+1-
+0.
+b101011 "
+0%
+0/
+01
+#170000000
+0!
+#171000000
+1!
+0)
+b101010 "
+0#
+0*
+0,
+#172000000
+0!
+#173000000
+1!
+1)
+b101011 "
+1#
+1*
+1,
+0+
+b101001 "
+0$
+0-
+#174000000
+0!
+#175000000
+1!
+0)
+b101000 "
+0#
+0*
+0,
+#176000000
+0!
+#177000000
+1!
+1)
+b101001 "
+1#
+1*
+1,
+1+
+b101011 "
+1$
+1-
+1.
+b101111 "
+1%
+1/
+11
+00
+b100111 "
+0&
+02
+#178000000
+0!
+#179000000
+1!
+0)
+b100110 "
+0#
+0*
+0,
+#180000000
+0!
+#181000000
+1!
+1)
+b100111 "
+1#
+1*
+1,
+0+
+b100101 "
+0$
+0-
+#182000000
+0!
+#183000000
+1!
+0)
+b100100 "
+0#
+0*
+0,
+#184000000
+0!
+#185000000
+1!
+1)
+b100101 "
+1#
+1*
+1,
+1+
+b100111 "
+1$
+1-
+0.
+b100011 "
+0%
+0/
+01
+#186000000
+0!
+#187000000
+1!
+0)
+b100010 "
+0#
+0*
+0,
+#188000000
+0!
+#189000000
+1!
+1)
+b100011 "
+1#
+1*
+1,
+0+
+b100001 "
+0$
+0-
+#190000000
+0!
+#191000000
+1!
+0)
+b100000 "
+0#
+0*
+0,
+#192000000
+0!
+#193000000
+1!
+1)
+b100001 "
+1#
+1*
+1,
+1+
+b100011 "
+1$
+1-
+1.
+b100111 "
+1%
+1/
+11
+10
+b101111 "
+1&
+12
+13
+b111111 "
+1'
+14
+16
+05
+b11111 "
+0(
+07
+#194000000
+0!
+#195000000
+1!
+0)
+b11110 "
+0#
+0*
+0,
+#196000000
+0!
+#197000000
+1!
+1)
+b11111 "
+1#
+1*
+1,
+0+
+b11101 "
+0$
+0-
+#198000000
+0!
+#199000000
+1!
+0)
+b11100 "
+0#
+0*
+0,
+#200000000
+0!
+#201000000
+1!
+1)
+b11101 "
+1#
+1*
+1,
+1+
+b11111 "
+1$
+1-
+0.
+b11011 "
+0%
+0/
+01
+#202000000
+0!
+#203000000
+1!
+0)
+b11010 "
+0#
+0*
+0,
+#204000000
+0!
+#205000000
+1!
+1)
+b11011 "
+1#
+1*
+1,
+0+
+b11001 "
+0$
+0-
+#206000000
+0!
+#207000000
+1!
+0)
+b11000 "
+0#
+0*
+0,
+#208000000
+0!
+#209000000
+1!
+1)
+b11001 "
+1#
+1*
+1,
+1+
+b11011 "
+1$
+1-
+1.
+b11111 "
+1%
+1/
+11
+00
+b10111 "
+0&
+02
+#210000000
+0!
+#211000000
+1!
+0)
+b10110 "
+0#
+0*
+0,
+#212000000
+0!
+#213000000
+1!
+1)
+b10111 "
+1#
+1*
+1,
+0+
+b10101 "
+0$
+0-
+#214000000
+0!
+#215000000
+1!
+0)
+b10100 "
+0#
+0*
+0,
+#216000000
+0!
+#217000000
+1!
+1)
+b10101 "
+1#
+1*
+1,
+1+
+b10111 "
+1$
+1-
+0.
+b10011 "
+0%
+0/
+01
+#218000000
+0!
+#219000000
+1!
+0)
+b10010 "
+0#
+0*
+0,
+#220000000
+0!
+#221000000
+1!
+1)
+b10011 "
+1#
+1*
+1,
+0+
+b10001 "
+0$
+0-
+#222000000
+0!
+#223000000
+1!
+0)
+b10000 "
+0#
+0*
+0,
+#224000000
+0!
+#225000000
+1!
+1)
+b10001 "
+1#
+1*
+1,
+1+
+b10011 "
+1$
+1-
+1.
+b10111 "
+1%
+1/
+11
+10
+b11111 "
+1&
+12
+03
+b1111 "
+0'
+04
+06
+#226000000
+0!
+#227000000
+1!
+0)
+b1110 "
+0#
+0*
+0,
+#228000000
+0!
+#229000000
+1!
+1)
+b1111 "
+1#
+1*
+1,
+0+
+b1101 "
+0$
+0-
+#230000000
+0!
+#231000000
+1!
+0)
+b1100 "
+0#
+0*
+0,
+#232000000
+0!
+#233000000
+1!
+1)
+b1101 "
+1#
+1*
+1,
+1+
+b1111 "
+1$
+1-
+0.
+b1011 "
+0%
+0/
+01
+#234000000
+0!
+#235000000
+1!
+0)
+b1010 "
+0#
+0*
+0,
+#236000000
+0!
+#237000000
+1!
+1)
+b1011 "
+1#
+1*
+1,
+0+
+b1001 "
+0$
+0-
+#238000000
+0!
+#239000000
+1!
+0)
+b1000 "
+0#
+0*
+0,
+#240000000
+0!
+#241000000
+1!
+1)
+b1001 "
+1#
+1*
+1,
+1+
+b1011 "
+1$
+1-
+1.
+b1111 "
+1%
+1/
+11
+00
+b111 "
+0&
+02
+#242000000
+0!
+#243000000
+1!
+0)
+b110 "
+0#
+0*
+0,
+#244000000
+0!
+#245000000
+1!
+1)
+b111 "
+1#
+1*
+1,
+0+
+b101 "
+0$
+0-
+#246000000
+0!
+#247000000
+1!
+0)
+b100 "
+0#
+0*
+0,
+#248000000
+0!
+#249000000
+1!
+1)
+b101 "
+1#
+1*
+1,
+1+
+b111 "
+1$
+1-
+0.
+b11 "
+0%
+0/
+01
+#250000000
+0!
+#251000000
+1!
+0)
+b10 "
+0#
+0*
+0,
+#252000000
+0!
+#253000000
+1!
+1)
+b11 "
+1#
+1*
+1,
+0+
+b1 "
+0$
+0-
+#254000000
+0!
+#255000000
+1!
+0)
+b0 "
+0#
+0*
+0,
+#256000000

From ec3a61513ba0b3a4b8db7026bac7bc6beb0a1eaa Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 27 Mar 2025 23:03:44 -0700
Subject: [PATCH 168/190] simulator read/write types must be passive

---
 crates/fayalite/src/sim.rs | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 275b106..b508756 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -6698,6 +6698,11 @@ impl SimulationModuleState {
         mut target: Target,
         which_module: WhichModule,
     ) -> CompiledValue<CanonicalType> {
+        assert!(
+            target.canonical_ty().is_passive(),
+            "simulator read/write expression must have a passive type \
+            (recursively contains no fields with `#[hdl(flip)]`)"
+        );
         if let Some(&retval) = self.io_targets.get(&target) {
             return retval;
         }

From e0f978fbb6b9ce19876489d0bbe5fcdae57175a3 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 27 Mar 2025 23:17:28 -0700
Subject: [PATCH 169/190] silence unused `m` variable warning in #[hdl_module]
 with an empty body.

---
 crates/fayalite-proc-macros-impl/src/module.rs | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/crates/fayalite-proc-macros-impl/src/module.rs b/crates/fayalite-proc-macros-impl/src/module.rs
index 0852f58..62b7837 100644
--- a/crates/fayalite-proc-macros-impl/src/module.rs
+++ b/crates/fayalite-proc-macros-impl/src/module.rs
@@ -377,7 +377,7 @@ impl ModuleFn {
             module_kind,
             vis,
             sig,
-            block,
+            mut block,
             struct_generics,
             the_struct,
         } = match self.0 {
@@ -439,6 +439,12 @@ impl ModuleFn {
         body_sig
             .inputs
             .insert(0, parse_quote! { m: &::fayalite::module::ModuleBuilder });
+        block.stmts.insert(
+            0,
+            parse_quote! {
+                let _ = m;
+            },
+        );
         let body_fn = ItemFn {
             attrs: vec![],
             vis: Visibility::Inherited,

From 5028401a5adad671f31ab754a958a692debdb062 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 27 Mar 2025 23:44:36 -0700
Subject: [PATCH 170/190] change SimValue to contain and deref to a value and
 not just contain bits

---
 .../src/hdl_bundle.rs                         | 171 ++++-
 .../fayalite-proc-macros-impl/src/hdl_enum.rs | 269 +++++++
 crates/fayalite/src/array.rs                  |  55 ++
 crates/fayalite/src/bundle.rs                 | 191 ++++-
 crates/fayalite/src/clock.rs                  |  17 +
 crates/fayalite/src/enum_.rs                  | 327 ++++++++-
 crates/fayalite/src/expr.rs                   |   1 +
 crates/fayalite/src/int.rs                    |  68 +-
 crates/fayalite/src/lib.rs                    |   2 +
 crates/fayalite/src/phantom_const.rs          |  23 +
 crates/fayalite/src/reset.rs                  |  17 +
 crates/fayalite/src/sim.rs                    | 674 +-----------------
 crates/fayalite/src/sim/value.rs              | 665 +++++++++++++++++
 crates/fayalite/src/ty.rs                     |  52 +-
 crates/fayalite/src/util.rs                   |   1 +
 crates/fayalite/src/util/alternating_cell.rs  | 122 ++++
 crates/fayalite/tests/sim.rs                  | 214 +++---
 .../tests/sim/expected/extern_module2.txt     |   4 +-
 .../tests/sim/expected/ripple_counter.txt     |  12 +-
 19 files changed, 2065 insertions(+), 820 deletions(-)
 create mode 100644 crates/fayalite/src/sim/value.rs
 create mode 100644 crates/fayalite/src/util/alternating_cell.rs

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
index b0fe498..a083def 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
@@ -30,7 +30,9 @@ pub(crate) struct ParsedBundle {
     pub(crate) field_flips: Vec<Option<HdlAttr<kw::flip, kw::hdl>>>,
     pub(crate) mask_type_ident: Ident,
     pub(crate) mask_type_match_variant_ident: Ident,
+    pub(crate) mask_type_sim_value_ident: Ident,
     pub(crate) match_variant_ident: Ident,
+    pub(crate) sim_value_ident: Ident,
     pub(crate) builder_ident: Ident,
     pub(crate) mask_type_builder_ident: Ident,
 }
@@ -125,7 +127,9 @@ impl ParsedBundle {
             field_flips,
             mask_type_ident: format_ident!("__{}__MaskType", ident),
             mask_type_match_variant_ident: format_ident!("__{}__MaskType__MatchVariant", ident),
+            mask_type_sim_value_ident: format_ident!("__{}__MaskType__SimValue", ident),
             match_variant_ident: format_ident!("__{}__MatchVariant", ident),
+            sim_value_ident: format_ident!("__{}__SimValue", ident),
             mask_type_builder_ident: format_ident!("__{}__MaskType__Builder", ident),
             builder_ident: format_ident!("__{}__Builder", ident),
             ident,
@@ -427,7 +431,9 @@ impl ToTokens for ParsedBundle {
             field_flips,
             mask_type_ident,
             mask_type_match_variant_ident,
+            mask_type_sim_value_ident,
             match_variant_ident,
+            sim_value_ident,
             builder_ident,
             mask_type_builder_ident,
         } = self;
@@ -523,7 +529,7 @@ impl ToTokens for ParsedBundle {
             semi_token: None,
         }
         .to_tokens(tokens);
-        let mut mask_type_match_variant_fields = mask_type_fields;
+        let mut mask_type_match_variant_fields = mask_type_fields.clone();
         for Field { ty, .. } in &mut mask_type_match_variant_fields.named {
             *ty = parse_quote_spanned! {span=>
                 ::fayalite::expr::Expr<#ty>
@@ -565,6 +571,58 @@ impl ToTokens for ParsedBundle {
             semi_token: None,
         }
         .to_tokens(tokens);
+        let mut mask_type_sim_value_fields = mask_type_fields;
+        for Field { ty, .. } in &mut mask_type_sim_value_fields.named {
+            *ty = parse_quote_spanned! {span=>
+                ::fayalite::sim::value::SimValue<#ty>
+            };
+        }
+        ItemStruct {
+            attrs: vec![
+                parse_quote_spanned! {span=>
+                    #[::fayalite::__std::prelude::v1::derive(
+                        ::fayalite::__std::fmt::Debug,
+                        ::fayalite::__std::clone::Clone,
+                    )]
+                },
+                parse_quote_spanned! {span=>
+                    #[allow(non_camel_case_types, dead_code)]
+                },
+            ],
+            vis: vis.clone(),
+            struct_token: *struct_token,
+            ident: mask_type_sim_value_ident.clone(),
+            generics: generics.into(),
+            fields: Fields::Named(mask_type_sim_value_fields),
+            semi_token: None,
+        }
+        .to_tokens(tokens);
+        let mut sim_value_fields = FieldsNamed::from(fields.clone());
+        for Field { ty, .. } in &mut sim_value_fields.named {
+            *ty = parse_quote_spanned! {span=>
+                ::fayalite::sim::value::SimValue<#ty>
+            };
+        }
+        ItemStruct {
+            attrs: vec![
+                parse_quote_spanned! {span=>
+                    #[::fayalite::__std::prelude::v1::derive(
+                        ::fayalite::__std::fmt::Debug,
+                        ::fayalite::__std::clone::Clone,
+                    )]
+                },
+                parse_quote_spanned! {span=>
+                    #[allow(non_camel_case_types, dead_code)]
+                },
+            ],
+            vis: vis.clone(),
+            struct_token: *struct_token,
+            ident: sim_value_ident.clone(),
+            generics: generics.into(),
+            fields: Fields::Named(sim_value_fields),
+            semi_token: None,
+        }
+        .to_tokens(tokens);
         let this_token = Ident::new("__this", span);
         let fields_token = Ident::new("__fields", span);
         let self_token = Token![self](span);
@@ -615,6 +673,25 @@ impl ToTokens for ParsedBundle {
                 }
             },
         ));
+        let sim_value_from_bits_fields = Vec::from_iter(fields.named().into_iter().map(|field| {
+            let ident: &Ident = field.ident().as_ref().unwrap();
+            quote_spanned! {span=>
+                #ident: v.field_from_bits(),
+            }
+        }));
+        let sim_value_clone_from_bits_fields =
+            Vec::from_iter(fields.named().into_iter().map(|field| {
+                let ident: &Ident = field.ident().as_ref().unwrap();
+                quote_spanned! {span=>
+                    v.field_clone_from_bits(&mut value.#ident);
+                }
+            }));
+        let sim_value_to_bits_fields = Vec::from_iter(fields.named().into_iter().map(|field| {
+            let ident: &Ident = field.ident().as_ref().unwrap();
+            quote_spanned! {span=>
+                v.field_to_bits(&value.#ident);
+            }
+        }));
         let fields_len = fields.named().into_iter().len();
         quote_spanned! {span=>
             #[automatically_derived]
@@ -623,6 +700,7 @@ impl ToTokens for ParsedBundle {
             {
                 type BaseType = ::fayalite::bundle::Bundle;
                 type MaskType = #mask_type_ident #type_generics;
+                type SimValue = #mask_type_sim_value_ident #type_generics;
                 type MatchVariant = #mask_type_match_variant_ident #type_generics;
                 type MatchActiveScope = ();
                 type MatchVariantAndInactiveScope = ::fayalite::ty::MatchVariantWithoutScope<
@@ -660,6 +738,34 @@ impl ToTokens for ParsedBundle {
                 fn source_location() -> ::fayalite::source_location::SourceLocation {
                     ::fayalite::source_location::SourceLocation::caller()
                 }
+                fn sim_value_from_bits(
+                    &self,
+                    bits: &::fayalite::__bitvec::slice::BitSlice,
+                ) -> <Self as ::fayalite::ty::Type>::SimValue {
+                    #![allow(unused_mut, unused_variables)]
+                    let mut v = ::fayalite::bundle::BundleSimValueFromBits::new(*self, bits);
+                    #mask_type_sim_value_ident {
+                        #(#sim_value_from_bits_fields)*
+                    }
+                }
+                fn sim_value_clone_from_bits(
+                    &self,
+                    value: &mut <Self as ::fayalite::ty::Type>::SimValue,
+                    bits: &::fayalite::__bitvec::slice::BitSlice,
+                ) {
+                    #![allow(unused_mut, unused_variables)]
+                    let mut v = ::fayalite::bundle::BundleSimValueFromBits::new(*self, bits);
+                    #(#sim_value_clone_from_bits_fields)*
+                }
+                fn sim_value_to_bits(
+                    &self,
+                    value: &<Self as ::fayalite::ty::Type>::SimValue,
+                    bits: &mut ::fayalite::__bitvec::slice::BitSlice,
+                ) {
+                    #![allow(unused_mut, unused_variables)]
+                    let mut v = ::fayalite::bundle::BundleSimValueToBits::new(*self, bits);
+                    #(#sim_value_to_bits_fields)*
+                }
             }
             #[automatically_derived]
             impl #impl_generics ::fayalite::bundle::BundleType for #mask_type_ident #type_generics
@@ -696,6 +802,7 @@ impl ToTokens for ParsedBundle {
             {
                 type BaseType = ::fayalite::bundle::Bundle;
                 type MaskType = #mask_type_ident #type_generics;
+                type SimValue = #sim_value_ident #type_generics;
                 type MatchVariant = #match_variant_ident #type_generics;
                 type MatchActiveScope = ();
                 type MatchVariantAndInactiveScope = ::fayalite::ty::MatchVariantWithoutScope<
@@ -735,6 +842,34 @@ impl ToTokens for ParsedBundle {
                 fn source_location() -> ::fayalite::source_location::SourceLocation {
                     ::fayalite::source_location::SourceLocation::caller()
                 }
+                fn sim_value_from_bits(
+                    &self,
+                    bits: &::fayalite::__bitvec::slice::BitSlice,
+                ) -> <Self as ::fayalite::ty::Type>::SimValue {
+                    #![allow(unused_mut, unused_variables)]
+                    let mut v = ::fayalite::bundle::BundleSimValueFromBits::new(*self, bits);
+                    #sim_value_ident {
+                        #(#sim_value_from_bits_fields)*
+                    }
+                }
+                fn sim_value_clone_from_bits(
+                    &self,
+                    value: &mut <Self as ::fayalite::ty::Type>::SimValue,
+                    bits: &::fayalite::__bitvec::slice::BitSlice,
+                ) {
+                    #![allow(unused_mut, unused_variables)]
+                    let mut v = ::fayalite::bundle::BundleSimValueFromBits::new(*self, bits);
+                    #(#sim_value_clone_from_bits_fields)*
+                }
+                fn sim_value_to_bits(
+                    &self,
+                    value: &<Self as ::fayalite::ty::Type>::SimValue,
+                    bits: &mut ::fayalite::__bitvec::slice::BitSlice,
+                ) {
+                    #![allow(unused_mut, unused_variables)]
+                    let mut v = ::fayalite::bundle::BundleSimValueToBits::new(*self, bits);
+                    #(#sim_value_to_bits_fields)*
+                }
             }
             #[automatically_derived]
             impl #impl_generics ::fayalite::bundle::BundleType for #target #type_generics
@@ -768,23 +903,33 @@ impl ToTokens for ParsedBundle {
         }
         .to_tokens(tokens);
         if let Some((cmp_eq,)) = cmp_eq {
-            let mut where_clause =
+            let mut expr_where_clause =
                 Generics::from(generics)
                     .where_clause
                     .unwrap_or_else(|| syn::WhereClause {
                         where_token: Token![where](span),
                         predicates: Punctuated::new(),
                     });
+            let mut sim_value_where_clause = expr_where_clause.clone();
+            let mut fields_sim_value_eq = vec![];
             let mut fields_cmp_eq = vec![];
             let mut fields_cmp_ne = vec![];
             for field in fields.named() {
                 let field_ident = field.ident();
                 let field_ty = field.ty();
-                where_clause
+                expr_where_clause
                     .predicates
                     .push(parse_quote_spanned! {cmp_eq.span=>
                         #field_ty: ::fayalite::expr::ops::ExprPartialEq<#field_ty>
                     });
+                sim_value_where_clause
+                    .predicates
+                    .push(parse_quote_spanned! {cmp_eq.span=>
+                        #field_ty: ::fayalite::sim::value::SimValuePartialEq<#field_ty>
+                    });
+                fields_sim_value_eq.push(quote_spanned! {span=>
+                    ::fayalite::sim::value::SimValuePartialEq::sim_value_eq(&__lhs.#field_ident, &__rhs.#field_ident)
+                });
                 fields_cmp_eq.push(quote_spanned! {span=>
                     ::fayalite::expr::ops::ExprPartialEq::cmp_eq(__lhs.#field_ident, __rhs.#field_ident)
                 });
@@ -792,9 +937,13 @@ impl ToTokens for ParsedBundle {
                     ::fayalite::expr::ops::ExprPartialEq::cmp_ne(__lhs.#field_ident, __rhs.#field_ident)
                 });
             }
+            let sim_value_eq_body;
             let cmp_eq_body;
             let cmp_ne_body;
             if fields_len == 0 {
+                sim_value_eq_body = quote_spanned! {span=>
+                    true
+                };
                 cmp_eq_body = quote_spanned! {span=>
                     ::fayalite::expr::ToExpr::to_expr(&true)
                 };
@@ -802,6 +951,9 @@ impl ToTokens for ParsedBundle {
                     ::fayalite::expr::ToExpr::to_expr(&false)
                 };
             } else {
+                sim_value_eq_body = quote_spanned! {span=>
+                    #(#fields_sim_value_eq)&&*
+                };
                 cmp_eq_body = quote_spanned! {span=>
                     #(#fields_cmp_eq)&*
                 };
@@ -812,7 +964,7 @@ impl ToTokens for ParsedBundle {
             quote_spanned! {span=>
                 #[automatically_derived]
                 impl #impl_generics ::fayalite::expr::ops::ExprPartialEq<Self> for #target #type_generics
-                #where_clause
+                #expr_where_clause
                 {
                     fn cmp_eq(
                         __lhs: ::fayalite::expr::Expr<Self>,
@@ -827,6 +979,17 @@ impl ToTokens for ParsedBundle {
                         #cmp_ne_body
                     }
                 }
+                #[automatically_derived]
+                impl #impl_generics ::fayalite::sim::value::SimValuePartialEq<Self> for #target #type_generics
+                #sim_value_where_clause
+                {
+                    fn sim_value_eq(
+                        __lhs: &::fayalite::sim::value::SimValue<Self>,
+                        __rhs: &::fayalite::sim::value::SimValue<Self>,
+                    ) -> bool {
+                        #sim_value_eq_body
+                    }
+                }
             }
             .to_tokens(tokens);
         }
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
index 9174566..0cdf85c 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
@@ -129,6 +129,7 @@ pub(crate) struct ParsedEnum {
     pub(crate) brace_token: Brace,
     pub(crate) variants: Punctuated<ParsedVariant, Token![,]>,
     pub(crate) match_variant_ident: Ident,
+    pub(crate) sim_value_ident: Ident,
 }
 
 impl ParsedEnum {
@@ -190,6 +191,7 @@ impl ParsedEnum {
             brace_token,
             variants,
             match_variant_ident: format_ident!("__{}__MatchVariant", ident),
+            sim_value_ident: format_ident!("__{}__SimValue", ident),
             ident,
         })
     }
@@ -207,6 +209,7 @@ impl ToTokens for ParsedEnum {
             brace_token,
             variants,
             match_variant_ident,
+            sim_value_ident,
         } = self;
         let span = ident.span();
         let ItemOptions {
@@ -409,6 +412,106 @@ impl ToTokens for ParsedEnum {
             )),
         }
         .to_tokens(tokens);
+        let mut enum_attrs = attrs.clone();
+        enum_attrs.push(parse_quote_spanned! {span=>
+            #[::fayalite::__std::prelude::v1::derive(
+                ::fayalite::__std::fmt::Debug,
+                ::fayalite::__std::clone::Clone,
+            )]
+        });
+        enum_attrs.push(parse_quote_spanned! {span=>
+            #[allow(dead_code, non_camel_case_types)]
+        });
+        let sim_value_has_unknown_variant = !variants.len().is_power_of_two();
+        let sim_value_unknown_variant_name = sim_value_has_unknown_variant.then(|| {
+            let mut name = String::new();
+            let unknown = "Unknown";
+            loop {
+                let orig_len = name.len();
+                name.push_str(unknown);
+                if variants.iter().all(|v| v.ident != name) {
+                    break Ident::new(&name, span);
+                }
+                name.truncate(orig_len);
+                name.push('_');
+            }
+        });
+        let sim_value_unknown_variant =
+            sim_value_unknown_variant_name
+                .as_ref()
+                .map(|unknown_variant_name| {
+                    Pair::End(parse_quote_spanned! {span=>
+                        #unknown_variant_name(::fayalite::enum_::UnknownVariantSimValue)
+                    })
+                });
+        ItemEnum {
+            attrs: enum_attrs,
+            vis: vis.clone(),
+            enum_token: *enum_token,
+            ident: sim_value_ident.clone(),
+            generics: generics.into(),
+            brace_token: *brace_token,
+            variants: Punctuated::from_iter(
+                variants
+                    .pairs()
+                    .map_pair_value_ref(
+                        |ParsedVariant {
+                             attrs,
+                             options: _,
+                             ident,
+                             field,
+                         }| Variant {
+                            attrs: attrs.clone(),
+                            ident: ident.clone(),
+                            fields: match field {
+                                Some(ParsedVariantField {
+                                    paren_token,
+                                    attrs,
+                                    options: _,
+                                    ty,
+                                    comma_token,
+                                }) => Fields::Unnamed(FieldsUnnamed {
+                                    paren_token: *paren_token,
+                                    unnamed: Punctuated::from_iter([
+                                        Pair::new(
+                                            Field {
+                                                attrs: attrs.clone(),
+                                                vis: Visibility::Inherited,
+                                                mutability: FieldMutability::None,
+                                                ident: None,
+                                                colon_token: None,
+                                                ty: parse_quote_spanned! {span=>
+                                                    ::fayalite::sim::value::SimValue<#ty>
+                                                },
+                                            },
+                                            Some(comma_token.unwrap_or(Token![,](ident.span()))),
+                                        ),
+                                        Pair::new(
+                                            Field {
+                                                attrs: vec![],
+                                                vis: Visibility::Inherited,
+                                                mutability: FieldMutability::None,
+                                                ident: None,
+                                                colon_token: None,
+                                                ty: parse_quote_spanned! {span=>
+                                                    ::fayalite::enum_::EnumPaddingSimValue
+                                                },
+                                            },
+                                            None,
+                                        ),
+                                    ]),
+                                }),
+                                None => Fields::Unnamed(parse_quote_spanned! {span=>
+                                    (::fayalite::enum_::EnumPaddingSimValue)
+                                }),
+                            },
+                            discriminant: None,
+                        },
+                    )
+                    .chain(sim_value_unknown_variant),
+            ),
+        }
+        .to_tokens(tokens);
         let self_token = Token![self](span);
         for (index, ParsedVariant { ident, field, .. }) in variants.iter().enumerate() {
             if let Some(ParsedVariantField { ty, .. }) = field {
@@ -534,6 +637,142 @@ impl ToTokens for ParsedEnum {
                 }
             },
         ));
+        let sim_value_from_bits_unknown_match_arm = if let Some(sim_value_unknown_variant_name) =
+            &sim_value_unknown_variant_name
+        {
+            quote_spanned! {span=>
+                _ => #sim_value_ident::#sim_value_unknown_variant_name(v.unknown_variant_from_bits()),
+            }
+        } else {
+            quote_spanned! {span=>
+                _ => ::fayalite::__std::unreachable!(),
+            }
+        };
+        let sim_value_from_bits_match_arms = Vec::from_iter(
+            variants
+                .iter()
+                .enumerate()
+                .map(
+                    |(
+                        index,
+                        ParsedVariant {
+                            attrs: _,
+                            options: _,
+                            ident,
+                            field,
+                        },
+                    )| {
+                        if let Some(_) = field {
+                            quote_spanned! {span=>
+                                #index => {
+                                    let (field, padding) = v.variant_with_field_from_bits();
+                                    #sim_value_ident::#ident(field, padding)
+                                }
+                            }
+                        } else {
+                            quote_spanned! {span=>
+                                #index => #sim_value_ident::#ident(
+                                    v.variant_no_field_from_bits(),
+                                ),
+                            }
+                        }
+                    },
+                )
+                .chain([sim_value_from_bits_unknown_match_arm]),
+        );
+        let sim_value_clone_from_bits_unknown_match_arm =
+            if let Some(sim_value_unknown_variant_name) = &sim_value_unknown_variant_name {
+                quote_spanned! {span=>
+                    _ => if let #sim_value_ident::#sim_value_unknown_variant_name(value) = value {
+                        v.unknown_variant_clone_from_bits(value);
+                    } else {
+                        *value = #sim_value_ident::#sim_value_unknown_variant_name(
+                            v.unknown_variant_from_bits(),
+                        );
+                    },
+                }
+            } else {
+                quote_spanned! {span=>
+                    _ => ::fayalite::__std::unreachable!(),
+                }
+            };
+        let sim_value_clone_from_bits_match_arms = Vec::from_iter(
+            variants
+                .iter()
+                .enumerate()
+                .map(
+                    |(
+                        index,
+                        ParsedVariant {
+                            attrs: _,
+                            options: _,
+                            ident,
+                            field,
+                        },
+                    )| {
+                        if let Some(_) = field {
+                            quote_spanned! {span=>
+                                #index => if let #sim_value_ident::#ident(field, padding) = value {
+                                    v.variant_with_field_clone_from_bits(field, padding);
+                                } else {
+                                    let (field, padding) = v.variant_with_field_from_bits();
+                                    *value = #sim_value_ident::#ident(field, padding);
+                                },
+                            }
+                        } else {
+                            quote_spanned! {span=>
+                                #index => if let #sim_value_ident::#ident(padding) = value {
+                                    v.variant_no_field_clone_from_bits(padding);
+                                } else {
+                                    *value = #sim_value_ident::#ident(
+                                        v.variant_no_field_from_bits(),
+                                    );
+                                },
+                            }
+                        }
+                    },
+                )
+                .chain([sim_value_clone_from_bits_unknown_match_arm]),
+        );
+        let sim_value_to_bits_match_arms = Vec::from_iter(
+            variants
+                .iter()
+                .enumerate()
+                .map(
+                    |(
+                        index,
+                        ParsedVariant {
+                            attrs: _,
+                            options: _,
+                            ident,
+                            field,
+                        },
+                    )| {
+                        if let Some(_) = field {
+                            quote_spanned! {span=>
+                                #sim_value_ident::#ident(field, padding) => {
+                                    v.variant_with_field_to_bits(#index, field, padding);
+                                }
+                            }
+                        } else {
+                            quote_spanned! {span=>
+                                #sim_value_ident::#ident(padding) => {
+                                    v.variant_no_field_to_bits(#index, padding);
+                                }
+                            }
+                        }
+                    },
+                )
+                .chain(sim_value_unknown_variant_name.as_ref().map(
+                    |sim_value_unknown_variant_name| {
+                        quote_spanned! {span=>
+                            #sim_value_ident::#sim_value_unknown_variant_name(value) => {
+                                v.unknown_variant_to_bits(value);
+                            }
+                        }
+                    },
+                )),
+        );
         let variants_len = variants.len();
         quote_spanned! {span=>
             #[automatically_derived]
@@ -542,6 +781,7 @@ impl ToTokens for ParsedEnum {
             {
                 type BaseType = ::fayalite::enum_::Enum;
                 type MaskType = ::fayalite::int::Bool;
+                type SimValue = #sim_value_ident #type_generics;
                 type MatchVariant = #match_variant_ident #type_generics;
                 type MatchActiveScope = ::fayalite::module::Scope;
                 type MatchVariantAndInactiveScope = ::fayalite::enum_::EnumMatchVariantAndInactiveScope<Self>;
@@ -574,6 +814,35 @@ impl ToTokens for ParsedEnum {
                 fn source_location() -> ::fayalite::source_location::SourceLocation {
                     ::fayalite::source_location::SourceLocation::caller()
                 }
+                fn sim_value_from_bits(
+                    &self,
+                    bits: &::fayalite::__bitvec::slice::BitSlice,
+                ) -> <Self as ::fayalite::ty::Type>::SimValue {
+                    let v = ::fayalite::enum_::EnumSimValueFromBits::new(*self, bits);
+                    match v.discriminant() {
+                        #(#sim_value_from_bits_match_arms)*
+                    }
+                }
+                fn sim_value_clone_from_bits(
+                    &self,
+                    value: &mut <Self as ::fayalite::ty::Type>::SimValue,
+                    bits: &::fayalite::__bitvec::slice::BitSlice,
+                ) {
+                    let v = ::fayalite::enum_::EnumSimValueFromBits::new(*self, bits);
+                    match v.discriminant() {
+                        #(#sim_value_clone_from_bits_match_arms)*
+                    }
+                }
+                fn sim_value_to_bits(
+                    &self,
+                    value: &<Self as ::fayalite::ty::Type>::SimValue,
+                    bits: &mut ::fayalite::__bitvec::slice::BitSlice,
+                ) {
+                    let v = ::fayalite::enum_::EnumSimValueToBits::new(*self, bits);
+                    match value {
+                        #(#sim_value_to_bits_match_arms)*
+                    }
+                }
             }
             #[automatically_derived]
             impl #impl_generics ::fayalite::enum_::EnumType for #target #type_generics
diff --git a/crates/fayalite/src/array.rs b/crates/fayalite/src/array.rs
index 0d9b63f..a2df6cf 100644
--- a/crates/fayalite/src/array.rs
+++ b/crates/fayalite/src/array.rs
@@ -1,6 +1,8 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 
+use bitvec::slice::BitSlice;
+
 use crate::{
     expr::{
         ops::{ArrayLiteral, ExprFromIterator, ExprIntoIterator, ExprPartialEq},
@@ -9,6 +11,7 @@ use crate::{
     int::{Bool, DynSize, KnownSize, Size, SizeType, DYN_SIZE},
     intern::{Intern, Interned, LazyInterned},
     module::transform::visit::{Fold, Folder, Visit, Visitor},
+    sim::value::{SimValue, SimValuePartialEq},
     source_location::SourceLocation,
     ty::{
         CanonicalType, MatchVariantWithoutScope, StaticType, Type, TypeProperties, TypeWithDeref,
@@ -142,6 +145,7 @@ impl<T: Type + Visit<State>, Len: Size, State: Visitor + ?Sized> Visit<State>
 impl<T: Type, Len: Size> Type for ArrayType<T, Len> {
     type BaseType = Array;
     type MaskType = ArrayType<T::MaskType, Len>;
+    type SimValue = Len::ArraySimValue<T>;
     type MatchVariant = Len::ArrayMatch<T>;
     type MatchActiveScope = ();
     type MatchVariantAndInactiveScope = MatchVariantWithoutScope<Len::ArrayMatch<T>>;
@@ -178,9 +182,48 @@ impl<T: Type, Len: Size> Type for ArrayType<T, Len> {
             Len::from_usize(array.len()),
         )
     }
+
     fn source_location() -> SourceLocation {
         SourceLocation::builtin()
     }
+
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert_eq!(bits.len(), self.type_properties.bit_width);
+        let element = self.element();
+        let element_bit_width = element.canonical().bit_width();
+        TryFrom::try_from(Vec::from_iter((0..self.len()).map(|i| {
+            SimValue::from_bitslice(element, &bits[i * element_bit_width..][..element_bit_width])
+        })))
+        .ok()
+        .expect("used correct length")
+    }
+
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+        assert_eq!(bits.len(), self.type_properties.bit_width);
+        let element_ty = self.element();
+        let element_bit_width = element_ty.canonical().bit_width();
+        let value: &mut [SimValue<T>] = value.as_mut();
+        assert_eq!(self.len(), value.len());
+        for (i, element_value) in value.iter_mut().enumerate() {
+            assert_eq!(SimValue::ty(element_value), element_ty);
+            SimValue::bits_mut(element_value)
+                .bits_mut()
+                .copy_from_bitslice(&bits[i * element_bit_width..][..element_bit_width]);
+        }
+    }
+
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+        assert_eq!(bits.len(), self.type_properties.bit_width);
+        let element_ty = self.element();
+        let element_bit_width = element_ty.canonical().bit_width();
+        let value: &[SimValue<T>] = value.as_ref();
+        assert_eq!(self.len(), value.len());
+        for (i, element_value) in value.iter().enumerate() {
+            assert_eq!(SimValue::ty(element_value), element_ty);
+            bits[i * element_bit_width..][..element_bit_width]
+                .copy_from_bitslice(SimValue::bits(element_value).bits());
+        }
+    }
 }
 
 impl<T: Type, Len: Size> TypeWithDeref for ArrayType<T, Len> {
@@ -247,6 +290,18 @@ where
     }
 }
 
+impl<Lhs: Type, Rhs: Type, Len: Size> SimValuePartialEq<ArrayType<Rhs, Len>> for ArrayType<Lhs, Len>
+where
+    Lhs: SimValuePartialEq<Rhs>,
+{
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<ArrayType<Rhs, Len>>) -> bool {
+        AsRef::<[_]>::as_ref(&**this)
+            .iter()
+            .zip(AsRef::<[_]>::as_ref(&**other))
+            .all(|(l, r)| SimValuePartialEq::sim_value_eq(l, r))
+    }
+}
+
 impl<T: Type, Len: Size> ExprIntoIterator for ArrayType<T, Len> {
     type Item = T;
     type ExprIntoIter = ExprArrayIter<T, Len>;
diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs
index 9807b92..06e0411 100644
--- a/crates/fayalite/src/bundle.rs
+++ b/crates/fayalite/src/bundle.rs
@@ -8,14 +8,14 @@ use crate::{
     },
     int::{Bool, DynSize},
     intern::{Intern, Interned},
-    sim::{SimValue, ToSimValue},
+    sim::value::{SimValue, SimValuePartialEq, ToSimValue},
     source_location::SourceLocation,
     ty::{
-        impl_match_variant_as_self, CanonicalType, MatchVariantWithoutScope, StaticType, Type,
-        TypeProperties, TypeWithDeref,
+        impl_match_variant_as_self, CanonicalType, MatchVariantWithoutScope, OpaqueSimValue,
+        StaticType, Type, TypeProperties, TypeWithDeref,
     },
 };
-use bitvec::vec::BitVec;
+use bitvec::{slice::BitSlice, vec::BitVec};
 use hashbrown::HashMap;
 use std::{fmt, marker::PhantomData};
 
@@ -216,6 +216,7 @@ impl Bundle {
 impl Type for Bundle {
     type BaseType = Bundle;
     type MaskType = Bundle;
+    type SimValue = OpaqueSimValue;
     impl_match_variant_as_self!();
     fn mask_type(&self) -> Self::MaskType {
         Self::new(Interned::from_iter(self.0.fields.into_iter().map(
@@ -239,6 +240,20 @@ impl Type for Bundle {
     fn source_location() -> SourceLocation {
         SourceLocation::builtin()
     }
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert_eq!(bits.len(), self.type_properties().bit_width);
+        OpaqueSimValue::from_bitslice(bits)
+    }
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+        assert_eq!(bits.len(), self.type_properties().bit_width);
+        assert_eq!(value.bit_width(), self.type_properties().bit_width);
+        value.bits_mut().bits_mut().copy_from_bitslice(bits);
+    }
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+        assert_eq!(bits.len(), self.type_properties().bit_width);
+        assert_eq!(value.bit_width(), self.type_properties().bit_width);
+        bits.copy_from_bitslice(value.bits().bits());
+    }
 }
 
 pub trait BundleType: Type<BaseType = Bundle> {
@@ -247,6 +262,93 @@ pub trait BundleType: Type<BaseType = Bundle> {
     fn fields(&self) -> Interned<[BundleField]>;
 }
 
+pub struct BundleSimValueFromBits<'a> {
+    fields: std::slice::Iter<'static, BundleField>,
+    bits: &'a BitSlice,
+}
+
+impl<'a> BundleSimValueFromBits<'a> {
+    #[track_caller]
+    pub fn new<T: BundleType>(bundle_ty: T, bits: &'a BitSlice) -> Self {
+        let fields = bundle_ty.fields();
+        assert_eq!(
+            bits.len(),
+            fields
+                .iter()
+                .map(|BundleField { ty, .. }| ty.bit_width())
+                .sum::<usize>()
+        );
+        Self {
+            fields: Interned::into_inner(fields).iter(),
+            bits,
+        }
+    }
+    #[track_caller]
+    fn field_ty_and_bits<T: Type>(&mut self) -> (T, &'a BitSlice) {
+        let Some(&BundleField {
+            name: _,
+            flipped: _,
+            ty,
+        }) = self.fields.next()
+        else {
+            panic!("tried to read too many fields from BundleSimValueFromBits");
+        };
+        let (field_bits, rest) = self.bits.split_at(ty.bit_width());
+        self.bits = rest;
+        (T::from_canonical(ty), field_bits)
+    }
+    #[track_caller]
+    pub fn field_from_bits<T: Type>(&mut self) -> SimValue<T> {
+        let (field_ty, field_bits) = self.field_ty_and_bits::<T>();
+        SimValue::from_bitslice(field_ty, field_bits)
+    }
+    #[track_caller]
+    pub fn field_clone_from_bits<T: Type>(&mut self, field_value: &mut SimValue<T>) {
+        let (field_ty, field_bits) = self.field_ty_and_bits::<T>();
+        assert_eq!(field_ty, SimValue::ty(field_value));
+        SimValue::bits_mut(field_value)
+            .bits_mut()
+            .copy_from_bitslice(field_bits);
+    }
+}
+
+pub struct BundleSimValueToBits<'a> {
+    fields: std::slice::Iter<'static, BundleField>,
+    bits: &'a mut BitSlice,
+}
+
+impl<'a> BundleSimValueToBits<'a> {
+    #[track_caller]
+    pub fn new<T: BundleType>(bundle_ty: T, bits: &'a mut BitSlice) -> Self {
+        let fields = bundle_ty.fields();
+        assert_eq!(
+            bits.len(),
+            fields
+                .iter()
+                .map(|BundleField { ty, .. }| ty.bit_width())
+                .sum::<usize>()
+        );
+        Self {
+            fields: Interned::into_inner(fields).iter(),
+            bits,
+        }
+    }
+    #[track_caller]
+    pub fn field_to_bits<T: Type>(&mut self, field_value: &SimValue<T>) {
+        let Some(&BundleField {
+            name: _,
+            flipped: _,
+            ty,
+        }) = self.fields.next()
+        else {
+            panic!("tried to read too many fields from BundleSimValueFromBits");
+        };
+        assert_eq!(T::from_canonical(ty), SimValue::ty(field_value));
+        self.bits[..ty.bit_width()].copy_from_bitslice(SimValue::bits(field_value).bits());
+        self.bits = &mut std::mem::take(&mut self.bits)[ty.bit_width()..];
+    }
+}
+
 #[derive(Default)]
 pub struct NoBuilder;
 
@@ -353,6 +455,7 @@ macro_rules! impl_tuples {
         impl<$($T: Type,)*> Type for ($($T,)*) {
             type BaseType = Bundle;
             type MaskType = ($($T::MaskType,)*);
+            type SimValue = ($(SimValue<$T>,)*);
             type MatchVariant = ($(Expr<$T>,)*);
             type MatchActiveScope = ();
             type MatchVariantAndInactiveScope = MatchVariantWithoutScope<Self::MatchVariant>;
@@ -391,6 +494,24 @@ macro_rules! impl_tuples {
             fn source_location() -> SourceLocation {
                 SourceLocation::builtin()
             }
+            fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+                #![allow(unused_mut, unused_variables)]
+                let mut v = BundleSimValueFromBits::new(*self, bits);
+                $(let $var = v.field_from_bits();)*
+                ($($var,)*)
+            }
+            fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+                #![allow(unused_mut, unused_variables)]
+                let mut v = BundleSimValueFromBits::new(*self, bits);
+                let ($($var,)*) = value;
+                $(v.field_clone_from_bits($var);)*
+            }
+            fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+                #![allow(unused_mut, unused_variables)]
+                let mut v = BundleSimValueToBits::new(*self, bits);
+                let ($($var,)*) = value;
+                $(v.field_to_bits($var);)*
+            }
         }
         impl<$($T: Type,)*> BundleType for ($($T,)*) {
             type Builder = TupleBuilder<($(Unfilled<$T>,)*)>;
@@ -444,16 +565,12 @@ macro_rules! impl_tuples {
         impl<$($T: ToSimValue<CanonicalType>,)*> ToSimValue<CanonicalType> for ($($T,)*) {
             #[track_caller]
             fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-                ToSimValue::<Bundle>::to_sim_value(self, Bundle::from_canonical(ty)).into_canonical()
+                SimValue::into_canonical(ToSimValue::<Bundle>::to_sim_value(self, Bundle::from_canonical(ty)))
             }
             #[track_caller]
             fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType>
             {
-                ToSimValue::<Bundle>::into_sim_value(self, Bundle::from_canonical(ty)).into_canonical()
-            }
-            #[track_caller]
-            fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
-                ToSimValue::<Bundle>::box_into_sim_value(self, Bundle::from_canonical(ty)).into_canonical()
+                SimValue::into_canonical(ToSimValue::<Bundle>::into_sim_value(self, Bundle::from_canonical(ty)))
             }
         }
         impl<$($T: ToSimValue<CanonicalType>,)*> ToSimValue<Bundle> for ($($T,)*) {
@@ -474,24 +591,12 @@ macro_rules! impl_tuples {
                 let [$($ty_var,)*] = *ty.fields() else {
                     panic!("bundle has wrong number of fields");
                 };
-                let mut bits: Option<BitVec> = None;
+                let mut bits = BitVec::new();
                 $(let $var = $var.into_sim_value($ty_var.ty);
-                assert_eq!($var.ty(), $ty_var.ty);
-                if !$var.bits().is_empty() {
-                    if let Some(bits) = &mut bits {
-                        bits.extend_from_bitslice($var.bits());
-                    } else {
-                        let mut $var = $var.into_bits();
-                        $var.reserve(ty.type_properties().bit_width - $var.len());
-                        bits = Some($var);
-                    }
-                }
+                assert_eq!(SimValue::ty(&$var), $ty_var.ty);
+                bits.extend_from_bitslice(SimValue::bits(&$var).bits());
                 )*
-                bits.unwrap_or_else(BitVec::new).into_sim_value(ty)
-            }
-            #[track_caller]
-            fn box_into_sim_value(self: Box<Self>, ty: Bundle) -> SimValue<Bundle> {
-                Self::into_sim_value(*self, ty)
+                bits.into_sim_value(ty)
             }
         }
         impl<$($T: ToSimValue<$Ty>, $Ty: Type,)*> ToSimValue<($($Ty,)*)> for ($($T,)*) {
@@ -499,19 +604,15 @@ macro_rules! impl_tuples {
             fn to_sim_value(&self, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
                 let ($($var,)*) = self;
                 let ($($ty_var,)*) = ty;
-                $(let $var = $var.to_sim_value($ty_var).into_canonical();)*
-                SimValue::from_canonical(ToSimValue::into_sim_value(($($var,)*), ty.canonical()))
+                $(let $var = $var.to_sim_value($ty_var);)*
+                SimValue::from_value(ty, ($($var,)*))
             }
             #[track_caller]
             fn into_sim_value(self, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
                 let ($($var,)*) = self;
                 let ($($ty_var,)*) = ty;
-                $(let $var = $var.into_sim_value($ty_var).into_canonical();)*
-                SimValue::from_canonical(ToSimValue::into_sim_value(($($var,)*), ty.canonical()))
-            }
-            #[track_caller]
-            fn box_into_sim_value(self: Box<Self>, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
-                Self::into_sim_value(*self, ty)
+                $(let $var = $var.into_sim_value($ty_var);)*
+                SimValue::from_value(ty, ($($var,)*))
             }
         }
         impl<$($Lhs: Type + ExprPartialEq<$Rhs>, $Rhs: Type,)*> ExprPartialEq<($($Rhs,)*)> for ($($Lhs,)*) {
@@ -537,6 +638,15 @@ macro_rules! impl_tuples {
                 .any_one_bits()
             }
         }
+        impl<$($Lhs: SimValuePartialEq<$Rhs>, $Rhs: Type,)*> SimValuePartialEq<($($Rhs,)*)> for ($($Lhs,)*) {
+            fn sim_value_eq(lhs: &SimValue<Self>, rhs: &SimValue<($($Rhs,)*)>) -> bool {
+                let ($($lhs_var,)*) = &**lhs;
+                let ($($rhs_var,)*) = &**rhs;
+                let retval = true;
+                $(let retval = retval && $lhs_var == $rhs_var;)*
+                retval
+            }
+        }
     };
     ([$($lhs:tt)*] [$rhs_first:tt $($rhs:tt)*]) => {
         impl_tuples!([$($lhs)*] []);
@@ -564,6 +674,7 @@ impl_tuples! {
 impl<T: ?Sized + Send + Sync + 'static> Type for PhantomData<T> {
     type BaseType = Bundle;
     type MaskType = ();
+    type SimValue = ();
     type MatchVariant = PhantomData<T>;
     type MatchActiveScope = ();
     type MatchVariantAndInactiveScope = MatchVariantWithoutScope<Self::MatchVariant>;
@@ -596,6 +707,16 @@ impl<T: ?Sized + Send + Sync + 'static> Type for PhantomData<T> {
     fn source_location() -> SourceLocation {
         SourceLocation::builtin()
     }
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert!(bits.is_empty());
+        ()
+    }
+    fn sim_value_clone_from_bits(&self, _value: &mut Self::SimValue, bits: &BitSlice) {
+        assert!(bits.is_empty());
+    }
+    fn sim_value_to_bits(&self, _value: &Self::SimValue, bits: &mut BitSlice) {
+        assert!(bits.is_empty());
+    }
 }
 
 pub struct PhantomDataBuilder<T: ?Sized + Send + Sync + 'static>(PhantomData<T>);
@@ -663,6 +784,6 @@ impl<T: ?Sized> ToSimValue<CanonicalType> for PhantomData<T> {
     fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
         let ty = Bundle::from_canonical(ty);
         assert!(ty.fields().is_empty());
-        ToSimValue::into_sim_value(BitVec::new(), ty).into_canonical()
+        SimValue::into_canonical(ToSimValue::into_sim_value(BitVec::new(), ty))
     }
 }
diff --git a/crates/fayalite/src/clock.rs b/crates/fayalite/src/clock.rs
index 711432b..f0623d4 100644
--- a/crates/fayalite/src/clock.rs
+++ b/crates/fayalite/src/clock.rs
@@ -8,6 +8,7 @@ use crate::{
     source_location::SourceLocation,
     ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
 };
+use bitvec::slice::BitSlice;
 
 #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Default)]
 pub struct Clock;
@@ -15,6 +16,7 @@ pub struct Clock;
 impl Type for Clock {
     type BaseType = Clock;
     type MaskType = Bool;
+    type SimValue = bool;
 
     impl_match_variant_as_self!();
 
@@ -36,6 +38,21 @@ impl Type for Clock {
         };
         retval
     }
+
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert_eq!(bits.len(), 1);
+        bits[0]
+    }
+
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+        assert_eq!(bits.len(), 1);
+        *value = bits[0];
+    }
+
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+        assert_eq!(bits.len(), 1);
+        bits.set(0, *value);
+    }
 }
 
 impl Clock {
diff --git a/crates/fayalite/src/enum_.rs b/crates/fayalite/src/enum_.rs
index 70c58c0..9fa38e9 100644
--- a/crates/fayalite/src/enum_.rs
+++ b/crates/fayalite/src/enum_.rs
@@ -7,17 +7,22 @@ use crate::{
         Expr, ToExpr,
     },
     hdl,
-    int::Bool,
+    int::{Bool, UIntValue},
     intern::{Intern, Interned},
     module::{
         connect, enum_match_variants_helper, incomplete_wire, wire,
         EnumMatchVariantAndInactiveScopeImpl, EnumMatchVariantsIterImpl, Scope,
     },
+    sim::value::{SimValue, SimValuePartialEq},
     source_location::SourceLocation,
-    ty::{CanonicalType, MatchVariantAndInactiveScope, StaticType, Type, TypeProperties},
+    ty::{
+        CanonicalType, MatchVariantAndInactiveScope, OpaqueSimValue, StaticType, Type,
+        TypeProperties,
+    },
 };
+use bitvec::{order::Lsb0, slice::BitSlice, view::BitView};
 use hashbrown::HashMap;
-use std::{convert::Infallible, fmt, iter::FusedIterator};
+use std::{convert::Infallible, fmt, iter::FusedIterator, sync::Arc};
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
 pub struct EnumVariant {
@@ -152,6 +157,12 @@ impl EnumTypePropertiesBuilder {
             variant_count: variant_count + 1,
         }
     }
+    #[must_use]
+    pub fn variants(self, variants: impl IntoIterator<Item = EnumVariant>) -> Self {
+        variants.into_iter().fold(self, |this, variant| {
+            this.variant(variant.ty.map(CanonicalType::type_properties))
+        })
+    }
     pub const fn finish(self) -> TypeProperties {
         assert!(
             self.variant_count != 0,
@@ -325,6 +336,7 @@ impl EnumType for Enum {
 impl Type for Enum {
     type BaseType = Enum;
     type MaskType = Bool;
+    type SimValue = OpaqueSimValue;
     type MatchVariant = Option<Expr<CanonicalType>>;
     type MatchActiveScope = Scope;
     type MatchVariantAndInactiveScope = EnumMatchVariantAndInactiveScope<Self>;
@@ -355,6 +367,296 @@ impl Type for Enum {
     fn source_location() -> SourceLocation {
         SourceLocation::builtin()
     }
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert_eq!(bits.len(), self.type_properties().bit_width);
+        OpaqueSimValue::from_bitslice(bits)
+    }
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+        assert_eq!(bits.len(), self.type_properties().bit_width);
+        assert_eq!(value.bit_width(), self.type_properties().bit_width);
+        value.bits_mut().bits_mut().copy_from_bitslice(bits);
+    }
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+        assert_eq!(bits.len(), self.type_properties().bit_width);
+        assert_eq!(value.bit_width(), self.type_properties().bit_width);
+        bits.copy_from_bitslice(value.bits().bits());
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug, Default)]
+pub struct EnumPaddingSimValue {
+    bits: Option<UIntValue>,
+}
+
+impl EnumPaddingSimValue {
+    pub fn bit_width(&self) -> Option<usize> {
+        self.bits.as_ref().map(UIntValue::width)
+    }
+    pub fn bits(&self) -> &Option<UIntValue> {
+        &self.bits
+    }
+    pub fn bits_mut(&mut self) -> &mut Option<UIntValue> {
+        &mut self.bits
+    }
+    pub fn into_bits(self) -> Option<UIntValue> {
+        self.bits
+    }
+    pub fn from_bits(bits: Option<UIntValue>) -> Self {
+        Self { bits }
+    }
+    pub fn from_bitslice(v: &BitSlice) -> Self {
+        Self {
+            bits: Some(UIntValue::new(Arc::new(v.to_bitvec()))),
+        }
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub struct UnknownVariantSimValue {
+    discriminant: usize,
+    body_bits: UIntValue,
+}
+
+impl UnknownVariantSimValue {
+    pub fn discriminant(&self) -> usize {
+        self.discriminant
+    }
+    pub fn body_bits(&self) -> &UIntValue {
+        &self.body_bits
+    }
+    pub fn body_bits_mut(&mut self) -> &mut UIntValue {
+        &mut self.body_bits
+    }
+    pub fn into_body_bits(self) -> UIntValue {
+        self.body_bits
+    }
+    pub fn into_parts(self) -> (usize, UIntValue) {
+        (self.discriminant, self.body_bits)
+    }
+    pub fn new(discriminant: usize, body_bits: UIntValue) -> Self {
+        Self {
+            discriminant,
+            body_bits,
+        }
+    }
+}
+
+pub struct EnumSimValueFromBits<'a> {
+    variants: Interned<[EnumVariant]>,
+    discriminant: usize,
+    body_bits: &'a BitSlice,
+}
+
+impl<'a> EnumSimValueFromBits<'a> {
+    #[track_caller]
+    pub fn new<T: EnumType>(ty: T, bits: &'a BitSlice) -> Self {
+        let variants = ty.variants();
+        let bit_width = EnumTypePropertiesBuilder::new()
+            .variants(variants)
+            .finish()
+            .bit_width;
+        assert_eq!(bit_width, bits.len());
+        let (discriminant_bits, body_bits) =
+            bits.split_at(discriminant_bit_width_impl(variants.len()));
+        let mut discriminant = 0usize;
+        discriminant.view_bits_mut::<Lsb0>()[..discriminant_bits.len()]
+            .copy_from_bitslice(discriminant_bits);
+        Self {
+            variants,
+            discriminant,
+            body_bits,
+        }
+    }
+    pub fn discriminant(&self) -> usize {
+        self.discriminant
+    }
+    #[track_caller]
+    #[cold]
+    fn usage_error(&self, clone: bool) -> ! {
+        let clone = if clone { "clone_" } else { "" };
+        match self.variants.get(self.discriminant) {
+            None => {
+                panic!("should have called EnumSimValueFromBits::unknown_variant_{clone}from_bits");
+            }
+            Some(EnumVariant { ty: None, .. }) => {
+                panic!(
+                    "should have called EnumSimValueFromBits::variant_no_field_{clone}from_bits"
+                );
+            }
+            Some(EnumVariant { ty: Some(_), .. }) => {
+                panic!(
+                    "should have called EnumSimValueFromBits::variant_with_field_{clone}from_bits"
+                );
+            }
+        }
+    }
+    #[track_caller]
+    fn known_variant(&self, clone: bool) -> (Option<CanonicalType>, &'a BitSlice, &'a BitSlice) {
+        let Some(EnumVariant { ty, .. }) = self.variants.get(self.discriminant) else {
+            self.usage_error(clone);
+        };
+        let variant_bit_width = ty.map_or(0, CanonicalType::bit_width);
+        let (variant_bits, padding_bits) = self.body_bits.split_at(variant_bit_width);
+        (*ty, variant_bits, padding_bits)
+    }
+    #[track_caller]
+    pub fn unknown_variant_from_bits(self) -> UnknownVariantSimValue {
+        let None = self.variants.get(self.discriminant) else {
+            self.usage_error(false);
+        };
+        UnknownVariantSimValue::new(
+            self.discriminant,
+            UIntValue::new(Arc::new(self.body_bits.to_bitvec())),
+        )
+    }
+    #[track_caller]
+    pub fn unknown_variant_clone_from_bits(self, value: &mut UnknownVariantSimValue) {
+        let None = self.variants.get(self.discriminant) else {
+            self.usage_error(true);
+        };
+        value.discriminant = self.discriminant;
+        assert_eq!(value.body_bits.width(), self.body_bits.len());
+        value
+            .body_bits
+            .bits_mut()
+            .copy_from_bitslice(self.body_bits);
+    }
+    #[track_caller]
+    pub fn variant_no_field_from_bits(self) -> EnumPaddingSimValue {
+        let (None, _variant_bits, padding_bits) = self.known_variant(false) else {
+            self.usage_error(false);
+        };
+        EnumPaddingSimValue::from_bitslice(padding_bits)
+    }
+    #[track_caller]
+    pub fn variant_with_field_from_bits<T: Type>(self) -> (SimValue<T>, EnumPaddingSimValue) {
+        let (Some(variant_ty), variant_bits, padding_bits) = self.known_variant(false) else {
+            self.usage_error(false);
+        };
+        (
+            SimValue::from_bitslice(T::from_canonical(variant_ty), variant_bits),
+            EnumPaddingSimValue::from_bitslice(padding_bits),
+        )
+    }
+    #[track_caller]
+    fn clone_padding_from_bits(padding: &mut EnumPaddingSimValue, padding_bits: &BitSlice) {
+        match padding.bits_mut() {
+            None => *padding = EnumPaddingSimValue::from_bitslice(padding_bits),
+            Some(padding) => {
+                assert_eq!(padding.width(), padding_bits.len());
+                padding.bits_mut().copy_from_bitslice(padding_bits);
+            }
+        }
+    }
+    #[track_caller]
+    pub fn variant_no_field_clone_from_bits(self, padding: &mut EnumPaddingSimValue) {
+        let (None, _variant_bits, padding_bits) = self.known_variant(true) else {
+            self.usage_error(true);
+        };
+        Self::clone_padding_from_bits(padding, padding_bits);
+    }
+    #[track_caller]
+    pub fn variant_with_field_clone_from_bits<T: Type>(
+        self,
+        value: &mut SimValue<T>,
+        padding: &mut EnumPaddingSimValue,
+    ) {
+        let (Some(variant_ty), variant_bits, padding_bits) = self.known_variant(true) else {
+            self.usage_error(true);
+        };
+        assert_eq!(SimValue::ty(value), T::from_canonical(variant_ty));
+        SimValue::bits_mut(value)
+            .bits_mut()
+            .copy_from_bitslice(variant_bits);
+        Self::clone_padding_from_bits(padding, padding_bits);
+    }
+}
+
+pub struct EnumSimValueToBits<'a> {
+    variants: Interned<[EnumVariant]>,
+    bit_width: usize,
+    discriminant_bit_width: usize,
+    bits: &'a mut BitSlice,
+}
+
+impl<'a> EnumSimValueToBits<'a> {
+    #[track_caller]
+    pub fn new<T: EnumType>(ty: T, bits: &'a mut BitSlice) -> Self {
+        let variants = ty.variants();
+        let bit_width = EnumTypePropertiesBuilder::new()
+            .variants(variants)
+            .finish()
+            .bit_width;
+        assert_eq!(bit_width, bits.len());
+        Self {
+            variants,
+            bit_width,
+            discriminant_bit_width: discriminant_bit_width_impl(variants.len()),
+            bits,
+        }
+    }
+    #[track_caller]
+    fn discriminant_to_bits(&mut self, mut discriminant: usize) {
+        let orig_discriminant = discriminant;
+        let discriminant_bits =
+            &mut discriminant.view_bits_mut::<Lsb0>()[..self.discriminant_bit_width];
+        self.bits[..self.discriminant_bit_width].copy_from_bitslice(discriminant_bits);
+        discriminant_bits.fill(false);
+        assert!(
+            discriminant == 0,
+            "{orig_discriminant:#x} is too big to fit in enum discriminant bits",
+        );
+    }
+    #[track_caller]
+    pub fn unknown_variant_to_bits(mut self, value: &UnknownVariantSimValue) {
+        self.discriminant_to_bits(value.discriminant);
+        let None = self.variants.get(value.discriminant) else {
+            panic!("can't use UnknownVariantSimValue to set known discriminant");
+        };
+        assert_eq!(
+            self.bit_width - self.discriminant_bit_width,
+            value.body_bits.width()
+        );
+        self.bits[self.discriminant_bit_width..].copy_from_bitslice(value.body_bits.bits());
+    }
+    #[track_caller]
+    fn known_variant(
+        mut self,
+        discriminant: usize,
+        padding: &EnumPaddingSimValue,
+    ) -> (Option<CanonicalType>, &'a mut BitSlice) {
+        self.discriminant_to_bits(discriminant);
+        let variant_ty = self.variants[discriminant].ty;
+        let variant_bit_width = variant_ty.map_or(0, CanonicalType::bit_width);
+        let padding_bits = &mut self.bits[self.discriminant_bit_width..][variant_bit_width..];
+        if let Some(padding) = padding.bits() {
+            assert_eq!(padding.width(), padding_bits.len());
+            padding_bits.copy_from_bitslice(padding.bits());
+        } else {
+            padding_bits.fill(false);
+        }
+        let variant_bits = &mut self.bits[self.discriminant_bit_width..][..variant_bit_width];
+        (variant_ty, variant_bits)
+    }
+    #[track_caller]
+    pub fn variant_no_field_to_bits(self, discriminant: usize, padding: &EnumPaddingSimValue) {
+        let (None, _variant_bits) = self.known_variant(discriminant, padding) else {
+            panic!("expected variant to have no field");
+        };
+    }
+    #[track_caller]
+    pub fn variant_with_field_to_bits<T: Type>(
+        self,
+        discriminant: usize,
+        value: &SimValue<T>,
+        padding: &EnumPaddingSimValue,
+    ) {
+        let (Some(variant_ty), variant_bits) = self.known_variant(discriminant, padding) else {
+            panic!("expected variant to have a field");
+        };
+        assert_eq!(SimValue::ty(value), T::from_canonical(variant_ty));
+        variant_bits.copy_from_bitslice(SimValue::bits(value).bits());
+    }
 }
 
 #[hdl]
@@ -417,6 +719,25 @@ impl<Lhs: Type + ExprPartialEq<Rhs>, Rhs: Type> ExprPartialEq<HdlOption<Rhs>> fo
     }
 }
 
+impl<Lhs: SimValuePartialEq<Rhs>, Rhs: Type> SimValuePartialEq<HdlOption<Rhs>> for HdlOption<Lhs> {
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<HdlOption<Rhs>>) -> bool {
+        type SimValueMatch<T> = <T as Type>::SimValue;
+        match (&**this, &**other) {
+            (SimValueMatch::<Self>::HdlNone(_), SimValueMatch::<HdlOption<Rhs>>::HdlNone(_)) => {
+                true
+            }
+            (SimValueMatch::<Self>::HdlSome(..), SimValueMatch::<HdlOption<Rhs>>::HdlNone(_))
+            | (SimValueMatch::<Self>::HdlNone(_), SimValueMatch::<HdlOption<Rhs>>::HdlSome(..)) => {
+                false
+            }
+            (
+                SimValueMatch::<Self>::HdlSome(l, _),
+                SimValueMatch::<HdlOption<Rhs>>::HdlSome(r, _),
+            ) => l == r,
+        }
+    }
+}
+
 #[allow(non_snake_case)]
 pub fn HdlNone<T: StaticType>() -> Expr<HdlOption<T>> {
     HdlOption[T::TYPE].HdlNone()
diff --git a/crates/fayalite/src/expr.rs b/crates/fayalite/src/expr.rs
index 016ec8e..f511c97 100644
--- a/crates/fayalite/src/expr.rs
+++ b/crates/fayalite/src/expr.rs
@@ -700,6 +700,7 @@ impl<T: ToExpr + ?Sized> CastToBits for T {
 }
 
 pub trait CastBitsTo {
+    #[track_caller]
     fn cast_bits_to<T: Type>(&self, ty: T) -> Expr<T>;
 }
 
diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index 236f240..a956dd5 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -7,6 +7,7 @@ use crate::{
         Expr, NotALiteralExpr, ToExpr, ToLiteralBits,
     },
     intern::{Intern, Interned, Memoize},
+    sim::value::SimValue,
     source_location::SourceLocation,
     ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
     util::{interned_bit, ConstBool, ConstUsize, GenericConstBool, GenericConstUsize},
@@ -49,6 +50,15 @@ pub trait KnownSize:
         + IntoIterator<Item = Expr<Element>>
         + TryFrom<Vec<Expr<Element>>>
         + Into<Vec<Expr<Element>>>;
+    type ArraySimValue<Element: Type>: AsRef<[SimValue<Element>]>
+        + AsMut<[SimValue<Element>]>
+        + BorrowMut<[SimValue<Element>]>
+        + 'static
+        + Clone
+        + std::fmt::Debug
+        + IntoIterator<Item = SimValue<Element>>
+        + TryFrom<Vec<SimValue<Element>>>
+        + Into<Vec<SimValue<Element>>>;
 }
 
 macro_rules! known_widths {
@@ -60,6 +70,7 @@ macro_rules! known_widths {
         }> {
             const SIZE: Self = Self;
             type ArrayMatch<Element: Type> = [Expr<Element>; Self::VALUE];
+            type ArraySimValue<Element: Type> = [SimValue<Element>; Self::VALUE];
         }
     };
     ([2 $($rest:tt)*] $($bits:literal)+) => {
@@ -72,6 +83,7 @@ macro_rules! known_widths {
         impl KnownSize for ConstUsize<{2 $(* $rest)*}> {
             const SIZE: Self = Self;
             type ArrayMatch<Element: Type> = [Expr<Element>; Self::VALUE];
+            type ArraySimValue<Element: Type> = [SimValue<Element>; Self::VALUE];
         }
     };
 }
@@ -100,6 +112,15 @@ pub trait Size:
         + IntoIterator<Item = Expr<Element>>
         + TryFrom<Vec<Expr<Element>>>
         + Into<Vec<Expr<Element>>>;
+    type ArraySimValue<Element: Type>: AsRef<[SimValue<Element>]>
+        + AsMut<[SimValue<Element>]>
+        + BorrowMut<[SimValue<Element>]>
+        + 'static
+        + Clone
+        + std::fmt::Debug
+        + IntoIterator<Item = SimValue<Element>>
+        + TryFrom<Vec<SimValue<Element>>>
+        + Into<Vec<SimValue<Element>>>;
     const KNOWN_VALUE: Option<usize>;
     type SizeType: SizeType<Size = Self>
         + Copy
@@ -125,6 +146,7 @@ impl SizeType for usize {
 
 impl Size for DynSize {
     type ArrayMatch<Element: Type> = Box<[Expr<Element>]>;
+    type ArraySimValue<Element: Type> = Box<[SimValue<Element>]>;
     const KNOWN_VALUE: Option<usize> = None;
     type SizeType = usize;
 
@@ -147,6 +169,7 @@ impl<T: KnownSize> SizeType for T {
 
 impl<T: KnownSize> Size for T {
     type ArrayMatch<Element: Type> = <T as KnownSize>::ArrayMatch<Element>;
+    type ArraySimValue<Element: Type> = <T as KnownSize>::ArraySimValue<Element>;
 
     const KNOWN_VALUE: Option<usize> = Some(T::VALUE);
 
@@ -287,6 +310,7 @@ macro_rules! impl_int {
         impl<Width: Size> Type for $name<Width> {
             type BaseType = $pretty_name;
             type MaskType = Bool;
+            type SimValue = $value<Width>;
             impl_match_variant_as_self!();
             fn mask_type(&self) -> Self::MaskType {
                 Bool
@@ -306,6 +330,20 @@ macro_rules! impl_int {
             fn source_location() -> SourceLocation {
                 SourceLocation::builtin()
             }
+            fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+                assert_eq!(bits.len(), self.width());
+                $value::new(Arc::new(bits.to_bitvec()))
+            }
+            fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+                assert_eq!(bits.len(), self.width());
+                assert_eq!(value.width(), self.width());
+                value.bits_mut().copy_from_bitslice(bits);
+            }
+            fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+                assert_eq!(bits.len(), self.width());
+                assert_eq!(value.width(), self.width());
+                bits.copy_from_bitslice(value.bits());
+            }
         }
 
         impl<Width: KnownSize> StaticType for $name<Width> {
@@ -331,7 +369,7 @@ macro_rules! impl_int {
             }
         }
 
-        #[derive(Clone, PartialEq, Eq, Hash)]
+        #[derive(Clone, Eq, Hash)]
         pub struct $value<Width: Size = DynSize> {
             bits: Arc<BitVec>,
             _phantom: PhantomData<Width>,
@@ -351,9 +389,15 @@ macro_rules! impl_int {
             }
         }
 
-        impl<Width: Size> PartialOrd for $value<Width> {
-            fn partial_cmp(&self, other: &Self) -> Option<std::cmp::Ordering> {
-                Some(self.cmp(other))
+        impl<LhsWidth: Size, RhsWidth: Size> PartialEq<$value<RhsWidth>> for $value<LhsWidth> {
+            fn eq(&self, other: &$value<RhsWidth>) -> bool {
+                self.to_bigint() == other.to_bigint()
+            }
+        }
+
+        impl<LhsWidth: Size, RhsWidth: Size> PartialOrd<$value<RhsWidth>> for $value<LhsWidth> {
+            fn partial_cmp(&self, other: &$value<RhsWidth>) -> Option<std::cmp::Ordering> {
+                Some(self.to_bigint().cmp(&other.to_bigint()))
             }
         }
 
@@ -401,6 +445,9 @@ macro_rules! impl_int {
             pub fn bits(&self) -> &Arc<BitVec> {
                 &self.bits
             }
+            pub fn bits_mut(&mut self) -> &mut BitSlice {
+                Arc::<BitVec>::make_mut(&mut self.bits)
+            }
         }
 
         impl<Width: Size> ToLiteralBits for $value<Width> {
@@ -748,6 +795,7 @@ impl Bool {
 impl Type for Bool {
     type BaseType = Bool;
     type MaskType = Bool;
+    type SimValue = bool;
     impl_match_variant_as_self!();
     fn mask_type(&self) -> Self::MaskType {
         Bool
@@ -765,6 +813,18 @@ impl Type for Bool {
     fn source_location() -> SourceLocation {
         SourceLocation::builtin()
     }
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert_eq!(bits.len(), 1);
+        bits[0]
+    }
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+        assert_eq!(bits.len(), 1);
+        *value = bits[0];
+    }
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+        assert_eq!(bits.len(), 1);
+        bits.set(0, *value);
+    }
 }
 
 impl StaticType for Bool {
diff --git a/crates/fayalite/src/lib.rs b/crates/fayalite/src/lib.rs
index 512572d..0843589 100644
--- a/crates/fayalite/src/lib.rs
+++ b/crates/fayalite/src/lib.rs
@@ -8,6 +8,8 @@
 
 extern crate self as fayalite;
 
+#[doc(hidden)]
+pub use bitvec as __bitvec;
 #[doc(hidden)]
 pub use std as __std;
 
diff --git a/crates/fayalite/src/phantom_const.rs b/crates/fayalite/src/phantom_const.rs
index dd6cff6..27bb04e 100644
--- a/crates/fayalite/src/phantom_const.rs
+++ b/crates/fayalite/src/phantom_const.rs
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 
+use bitvec::slice::BitSlice;
 use serde::{de::DeserializeOwned, Deserialize, Serialize};
 
 use crate::{
@@ -10,6 +11,7 @@ use crate::{
     },
     int::Bool,
     intern::{Intern, Interned, InternedCompare, LazyInterned, Memoize},
+    sim::value::{SimValue, SimValuePartialEq},
     source_location::SourceLocation,
     ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
 };
@@ -246,6 +248,7 @@ impl<T: ?Sized + PhantomConstValue> PhantomConst<T> {
 impl<T: ?Sized + PhantomConstValue> Type for PhantomConst<T> {
     type BaseType = PhantomConst;
     type MaskType = ();
+    type SimValue = ();
     impl_match_variant_as_self!();
 
     fn mask_type(&self) -> Self::MaskType {
@@ -266,6 +269,19 @@ impl<T: ?Sized + PhantomConstValue> Type for PhantomConst<T> {
     fn source_location() -> SourceLocation {
         SourceLocation::builtin()
     }
+
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert!(bits.is_empty());
+        ()
+    }
+
+    fn sim_value_clone_from_bits(&self, _value: &mut Self::SimValue, bits: &BitSlice) {
+        assert!(bits.is_empty());
+    }
+
+    fn sim_value_to_bits(&self, _value: &Self::SimValue, bits: &mut BitSlice) {
+        assert!(bits.is_empty());
+    }
 }
 
 impl<T: ?Sized + PhantomConstValue> StaticType for PhantomConst<T>
@@ -311,3 +327,10 @@ impl<T: ?Sized + PhantomConstValue> ExprPartialOrd<Self> for PhantomConst<T> {
         true.to_expr()
     }
 }
+
+impl<T: ?Sized + PhantomConstValue> SimValuePartialEq<Self> for PhantomConst<T> {
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<Self>) -> bool {
+        assert_eq!(SimValue::ty(this), SimValue::ty(other));
+        true
+    }
+}
diff --git a/crates/fayalite/src/reset.rs b/crates/fayalite/src/reset.rs
index 9328365..312a8ea 100644
--- a/crates/fayalite/src/reset.rs
+++ b/crates/fayalite/src/reset.rs
@@ -7,6 +7,7 @@ use crate::{
     source_location::SourceLocation,
     ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
 };
+use bitvec::slice::BitSlice;
 
 mod sealed {
     pub trait ResetTypeSealed {}
@@ -45,6 +46,7 @@ macro_rules! reset_type {
         impl Type for $name {
             type BaseType = $name;
             type MaskType = Bool;
+            type SimValue = bool;
 
             impl_match_variant_as_self!();
 
@@ -66,6 +68,21 @@ macro_rules! reset_type {
                 };
                 retval
             }
+
+            fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+                assert_eq!(bits.len(), 1);
+                bits[0]
+            }
+
+            fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+                assert_eq!(bits.len(), 1);
+                *value = bits[0];
+            }
+
+            fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+                assert_eq!(bits.len(), 1);
+                bits.set(0, *value);
+            }
         }
 
         impl $name {
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index b508756..9be4889 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -14,7 +14,7 @@ use crate::{
         },
         ExprEnum, Flow, ToLiteralBits,
     },
-    int::{BoolOrIntType, IntType, SIntValue, UIntValue},
+    int::{BoolOrIntType, UIntValue},
     intern::{
         Intern, Interned, InternedCompare, Memoize, PtrEqWithTypeId, SupportsPtrEqWithTypeId,
     },
@@ -38,6 +38,7 @@ use crate::{
             TypeIndexRange, TypeLayout, TypeLen, TypeParts,
         },
         time::{SimDuration, SimInstant},
+        value::SimValue,
     },
     ty::StaticType,
     util::{BitSliceWriteWithBase, DebugAsDisplay},
@@ -72,6 +73,7 @@ use std::{
 
 mod interpreter;
 pub mod time;
+pub mod value;
 pub mod vcd;
 
 #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)]
@@ -5904,635 +5906,6 @@ impl SimTraceKind {
     }
 }
 
-#[derive(Clone, PartialEq, Eq, Hash)]
-pub struct SimValue<T: Type> {
-    ty: T,
-    bits: BitVec,
-}
-
-impl<T: Type> fmt::Debug for SimValue<T> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        f.debug_struct("SimValue")
-            .field("ty", &self.ty)
-            .field("bits", &BitSliceWriteWithBase(&self.bits))
-            .finish()
-    }
-}
-
-impl SimValue<CanonicalType> {
-    #[track_caller]
-    fn to_expr_impl(ty: CanonicalType, bits: &BitSlice) -> Expr<CanonicalType> {
-        match ty {
-            CanonicalType::UInt(_) => Expr::canonical(<UInt>::bits_to_expr(Cow::Borrowed(bits))),
-            CanonicalType::SInt(_) => Expr::canonical(<SInt>::bits_to_expr(Cow::Borrowed(bits))),
-            CanonicalType::Bool(_) => Expr::canonical(Bool::bits_to_expr(Cow::Borrowed(bits))),
-            CanonicalType::Array(ty) => {
-                let element_bit_width = ty.element().bit_width();
-                Expr::<Array>::canonical(
-                    crate::expr::ops::ArrayLiteral::new(
-                        ty.element(),
-                        (0..ty.len())
-                            .map(|array_index| {
-                                let start = element_bit_width * array_index;
-                                let end = start + element_bit_width;
-                                Self::to_expr_impl(ty.element(), &bits[start..end])
-                            })
-                            .collect(),
-                    )
-                    .to_expr(),
-                )
-            }
-            CanonicalType::Enum(ty) => {
-                let discriminant_bit_width = ty.discriminant_bit_width();
-                let mut variant_index = [0; mem::size_of::<usize>()];
-                variant_index.view_bits_mut::<Lsb0>()[0..discriminant_bit_width]
-                    .clone_from_bitslice(&bits[..discriminant_bit_width]);
-                let variant_index = usize::from_le_bytes(variant_index);
-                if let Some(variant) = ty.variants().get(variant_index) {
-                    let data_bit_width = variant.ty.map_or(0, CanonicalType::bit_width);
-                    Expr::canonical(
-                        crate::expr::ops::EnumLiteral::new_by_index(
-                            ty,
-                            variant_index,
-                            variant.ty.map(|ty| {
-                                Self::to_expr_impl(
-                                    ty,
-                                    &bits[discriminant_bit_width
-                                        ..discriminant_bit_width + data_bit_width],
-                                )
-                            }),
-                        )
-                        .to_expr(),
-                    )
-                } else {
-                    Expr::canonical(<UInt>::bits_to_expr(Cow::Borrowed(bits)).cast_bits_to(ty))
-                }
-            }
-            CanonicalType::Bundle(ty) => Expr::canonical(
-                crate::expr::ops::BundleLiteral::new(
-                    ty,
-                    ty.fields()
-                        .iter()
-                        .zip(ty.field_offsets().iter())
-                        .map(|(field, &field_offset)| {
-                            Self::to_expr_impl(
-                                field.ty,
-                                &bits[field_offset..field_offset + field.ty.bit_width()],
-                            )
-                        })
-                        .collect(),
-                )
-                .to_expr(),
-            ),
-            CanonicalType::AsyncReset(ty) => {
-                Expr::canonical(Bool::bits_to_expr(Cow::Borrowed(bits)).cast_to(ty))
-            }
-            CanonicalType::SyncReset(ty) => {
-                Expr::canonical(Bool::bits_to_expr(Cow::Borrowed(bits)).cast_to(ty))
-            }
-            CanonicalType::Reset(_) => panic!(
-                "can't convert SimValue<Reset> to Expr<Reset> -- \
-                can't deduce whether reset value should be sync or async"
-            ),
-            CanonicalType::Clock(ty) => {
-                Expr::canonical(Bool::bits_to_expr(Cow::Borrowed(bits)).cast_to(ty))
-            }
-            CanonicalType::PhantomConst(ty) => Expr::canonical(ty.to_expr()),
-        }
-    }
-}
-
-impl<T: Type> ToExpr for SimValue<T> {
-    type Type = T;
-
-    #[track_caller]
-    fn to_expr(&self) -> Expr<Self::Type> {
-        Expr::from_canonical(SimValue::to_expr_impl(self.ty.canonical(), &self.bits))
-    }
-}
-
-impl<T: Type> ToSimValue<T> for SimValue<T> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        assert_eq!(self.ty, ty);
-        self.clone()
-    }
-
-    #[track_caller]
-    fn into_sim_value(self, ty: T) -> SimValue<T> {
-        assert_eq!(self.ty, ty);
-        self
-    }
-
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: T) -> SimValue<T> {
-        assert_eq!(self.ty, ty);
-        *self
-    }
-}
-
-impl<T: Type> ToSimValue<T> for BitVec {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        self.clone().into_sim_value(ty)
-    }
-
-    #[track_caller]
-    fn into_sim_value(self, ty: T) -> SimValue<T> {
-        assert_eq!(ty.canonical().bit_width(), self.len());
-        SimValue { ty, bits: self }
-    }
-
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: T) -> SimValue<T> {
-        Self::into_sim_value(*self, ty)
-    }
-}
-
-impl<T: Type> ToSimValue<T> for bitvec::boxed::BitBox {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        self.clone().into_sim_value(ty)
-    }
-
-    #[track_caller]
-    fn into_sim_value(self, ty: T) -> SimValue<T> {
-        assert_eq!(ty.canonical().bit_width(), self.len());
-        SimValue {
-            ty,
-            bits: self.into_bitvec(),
-        }
-    }
-
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: T) -> SimValue<T> {
-        Self::into_sim_value(*self, ty)
-    }
-}
-
-impl<T: Type> ToSimValue<T> for BitSlice {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        assert_eq!(ty.canonical().bit_width(), self.len());
-        SimValue {
-            ty,
-            bits: self.to_bitvec(),
-        }
-    }
-}
-
-impl<T: Type> SimValue<T> {
-    pub fn ty(&self) -> T {
-        self.ty
-    }
-    pub fn bits(&self) -> &BitSlice {
-        &self.bits
-    }
-    pub fn into_bits(self) -> BitVec {
-        self.bits
-    }
-    #[track_caller]
-    pub fn from_canonical(v: SimValue<CanonicalType>) -> Self {
-        Self {
-            ty: T::from_canonical(v.ty),
-            bits: v.bits,
-        }
-    }
-    pub fn into_canonical(self) -> SimValue<CanonicalType> {
-        SimValue {
-            ty: self.ty.canonical(),
-            bits: self.bits,
-        }
-    }
-    #[track_caller]
-    pub fn from_dyn_int(v: SimValue<T::Dyn>) -> Self
-    where
-        T: IntType,
-    {
-        Self {
-            ty: T::from_dyn_int(v.ty),
-            bits: v.bits,
-        }
-    }
-    pub fn into_dyn_int(self) -> SimValue<T::Dyn>
-    where
-        T: IntType,
-    {
-        SimValue {
-            ty: self.ty.as_dyn_int(),
-            bits: self.bits,
-        }
-    }
-    #[track_caller]
-    pub fn from_bundle(v: SimValue<Bundle>) -> Self
-    where
-        T: BundleType,
-    {
-        Self {
-            ty: T::from_canonical(CanonicalType::Bundle(v.ty)),
-            bits: v.bits,
-        }
-    }
-    pub fn into_bundle(self) -> SimValue<Bundle>
-    where
-        T: BundleType,
-    {
-        SimValue {
-            ty: Bundle::from_canonical(self.ty.canonical()),
-            bits: self.bits,
-        }
-    }
-    #[track_caller]
-    pub fn from_enum(v: SimValue<Enum>) -> Self
-    where
-        T: EnumType,
-    {
-        Self {
-            ty: T::from_canonical(CanonicalType::Enum(v.ty)),
-            bits: v.bits,
-        }
-    }
-    pub fn into_enum(self) -> SimValue<Enum>
-    where
-        T: EnumType,
-    {
-        SimValue {
-            ty: Enum::from_canonical(self.ty.canonical()),
-            bits: self.bits,
-        }
-    }
-}
-
-pub trait ToSimValue<T: Type> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T>;
-    #[track_caller]
-    fn into_sim_value(self, ty: T) -> SimValue<T>
-    where
-        Self: Sized,
-    {
-        self.to_sim_value(ty)
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: T) -> SimValue<T> {
-        self.to_sim_value(ty)
-    }
-}
-
-impl<This: ?Sized + ToSimValue<T>, T: Type> ToSimValue<T> for &'_ This {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        This::to_sim_value(self, ty)
-    }
-}
-
-impl<This: ?Sized + ToSimValue<T>, T: Type> ToSimValue<T> for &'_ mut This {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        This::to_sim_value(self, ty)
-    }
-}
-
-impl<This: ?Sized + ToSimValue<T>, T: Type> ToSimValue<T> for Box<This> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        This::to_sim_value(self, ty)
-    }
-    #[track_caller]
-    fn into_sim_value(self, ty: T) -> SimValue<T> {
-        This::box_into_sim_value(self, ty)
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: T) -> SimValue<T> {
-        This::box_into_sim_value(*self, ty)
-    }
-}
-
-impl<This: ?Sized + ToSimValue<T> + Send + Sync + 'static, T: Type> ToSimValue<T>
-    for Interned<This>
-{
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        This::to_sim_value(self, ty)
-    }
-}
-
-impl<T: Type, Len: Size> SimValue<ArrayType<T, Len>> {
-    #[track_caller]
-    pub fn from_array_elements<
-        I: IntoIterator<Item: ToSimValue<T>, IntoIter: ExactSizeIterator>,
-    >(
-        elements: I,
-        ty: ArrayType<T, Len>,
-    ) -> Self {
-        let mut iter = elements.into_iter();
-        assert_eq!(iter.len(), ty.len());
-        let Some(first) = iter.next() else {
-            return SimValue {
-                ty,
-                bits: BitVec::new(),
-            };
-        };
-        let SimValue {
-            ty: element_ty,
-            mut bits,
-        } = first.into_sim_value(ty.element());
-        assert_eq!(element_ty, ty.element());
-        bits.reserve(ty.type_properties().bit_width - bits.len());
-        for element in iter {
-            let SimValue {
-                ty: element_ty,
-                bits: element_bits,
-            } = element.into_sim_value(ty.element());
-            assert_eq!(element_ty, ty.element());
-            bits.extend_from_bitslice(&element_bits);
-        }
-        SimValue { ty, bits }
-    }
-}
-
-impl<Element: ToSimValue<T>, T: Type> ToSimValue<Array<T>> for [Element] {
-    #[track_caller]
-    fn to_sim_value(&self, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(self, ty)
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(self, ty)
-    }
-}
-
-impl<Element: ToSimValue<CanonicalType>> ToSimValue<CanonicalType> for [Element] {
-    #[track_caller]
-    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
-    }
-}
-
-impl<Element: ToSimValue<T>, T: Type, const N: usize> ToSimValue<Array<T, N>> for [Element; N]
-where
-    ConstUsize<N>: KnownSize,
-{
-    #[track_caller]
-    fn to_sim_value(&self, ty: Array<T, N>) -> SimValue<Array<T, N>> {
-        SimValue::from_array_elements(self, ty)
-    }
-    #[track_caller]
-    fn into_sim_value(self, ty: Array<T, N>) -> SimValue<Array<T, N>> {
-        SimValue::from_array_elements(self, ty)
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: Array<T, N>) -> SimValue<Array<T, N>> {
-        SimValue::from_array_elements(<Vec<Element> as From<Box<[Element]>>>::from(self), ty)
-    }
-}
-
-impl<Element: ToSimValue<T>, T: Type, const N: usize> ToSimValue<Array<T>> for [Element; N]
-where
-    ConstUsize<N>: KnownSize,
-{
-    #[track_caller]
-    fn to_sim_value(&self, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(self, ty)
-    }
-    #[track_caller]
-    fn into_sim_value(self, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(self, ty)
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(<Vec<Element> as From<Box<[Element]>>>::from(self), ty)
-    }
-}
-
-impl<Element: ToSimValue<CanonicalType>, const N: usize> ToSimValue<CanonicalType>
-    for [Element; N]
-{
-    #[track_caller]
-    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
-    }
-    #[track_caller]
-    fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(
-            <Vec<Element> as From<Box<[Element]>>>::from(self),
-            <Array>::from_canonical(ty),
-        )
-        .into_canonical()
-    }
-}
-
-impl<Element: ToSimValue<T>, T: Type> ToSimValue<Array<T>> for Vec<Element> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(self, ty)
-    }
-    #[track_caller]
-    fn into_sim_value(self, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(self, ty)
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(*self, ty)
-    }
-}
-
-impl<Element: ToSimValue<CanonicalType>> ToSimValue<CanonicalType> for Vec<Element> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
-    }
-    #[track_caller]
-    fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(*self, <Array>::from_canonical(ty)).into_canonical()
-    }
-}
-
-impl<T: Type> ToSimValue<T> for Expr<T> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        assert_eq!(Expr::ty(*self), ty);
-        SimValue {
-            ty,
-            bits: self
-                .to_literal_bits()
-                .expect("must be a literal expression")
-                .to_bitvec(),
-        }
-    }
-}
-
-macro_rules! impl_to_sim_value_for_bool_like {
-    ($ty:ident) => {
-        impl ToSimValue<$ty> for bool {
-            fn to_sim_value(&self, ty: $ty) -> SimValue<$ty> {
-                SimValue {
-                    ty,
-                    bits: BitVec::repeat(*self, 1),
-                }
-            }
-        }
-    };
-}
-
-impl_to_sim_value_for_bool_like!(Bool);
-impl_to_sim_value_for_bool_like!(AsyncReset);
-impl_to_sim_value_for_bool_like!(SyncReset);
-impl_to_sim_value_for_bool_like!(Reset);
-impl_to_sim_value_for_bool_like!(Clock);
-
-impl ToSimValue<CanonicalType> for bool {
-    #[track_caller]
-    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        match ty {
-            CanonicalType::UInt(_)
-            | CanonicalType::SInt(_)
-            | CanonicalType::Array(_)
-            | CanonicalType::Enum(_)
-            | CanonicalType::Bundle(_)
-            | CanonicalType::PhantomConst(_) => {
-                panic!("can't create SimValue from bool: expected value of type: {ty:?}");
-            }
-            CanonicalType::Bool(_)
-            | CanonicalType::AsyncReset(_)
-            | CanonicalType::SyncReset(_)
-            | CanonicalType::Reset(_)
-            | CanonicalType::Clock(_) => SimValue {
-                ty,
-                bits: BitVec::repeat(*self, 1),
-            },
-        }
-    }
-}
-
-macro_rules! impl_to_sim_value_for_primitive_int {
-    ($prim:ident) => {
-        impl ToSimValue<<$prim as ToExpr>::Type> for $prim {
-            #[track_caller]
-            fn to_sim_value(
-                &self,
-                ty: <$prim as ToExpr>::Type,
-            ) -> SimValue<<$prim as ToExpr>::Type> {
-                SimValue {
-                    ty,
-                    bits: <<$prim as ToExpr>::Type as BoolOrIntType>::le_bytes_to_bits_wrapping(
-                        &self.to_le_bytes(),
-                        ty.width(),
-                    ),
-                }
-            }
-        }
-
-        impl ToSimValue<<<$prim as ToExpr>::Type as IntType>::Dyn> for $prim {
-            #[track_caller]
-            fn to_sim_value(
-                &self,
-                ty: <<$prim as ToExpr>::Type as IntType>::Dyn,
-            ) -> SimValue<<<$prim as ToExpr>::Type as IntType>::Dyn> {
-                SimValue {
-                    ty,
-                    bits: <<$prim as ToExpr>::Type as BoolOrIntType>::le_bytes_to_bits_wrapping(
-                        &self.to_le_bytes(),
-                        ty.width(),
-                    ),
-                }
-            }
-        }
-
-        impl ToSimValue<CanonicalType> for $prim {
-            #[track_caller]
-            fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-                let ty: <<$prim as ToExpr>::Type as IntType>::Dyn = Type::from_canonical(ty);
-                self.to_sim_value(ty).into_canonical()
-            }
-        }
-    };
-}
-
-impl_to_sim_value_for_primitive_int!(u8);
-impl_to_sim_value_for_primitive_int!(u16);
-impl_to_sim_value_for_primitive_int!(u32);
-impl_to_sim_value_for_primitive_int!(u64);
-impl_to_sim_value_for_primitive_int!(u128);
-impl_to_sim_value_for_primitive_int!(usize);
-impl_to_sim_value_for_primitive_int!(i8);
-impl_to_sim_value_for_primitive_int!(i16);
-impl_to_sim_value_for_primitive_int!(i32);
-impl_to_sim_value_for_primitive_int!(i64);
-impl_to_sim_value_for_primitive_int!(i128);
-impl_to_sim_value_for_primitive_int!(isize);
-
-macro_rules! impl_to_sim_value_for_int_value {
-    ($IntValue:ident, $Int:ident, $IntType:ident) => {
-        impl<Width: KnownSize> ToSimValue<$IntType<Width>> for $IntValue<Width> {
-            fn to_sim_value(&self, ty: $IntType<Width>) -> SimValue<$IntType<Width>> {
-                self.bits().to_bitvec().into_sim_value(ty)
-            }
-
-            fn into_sim_value(self, ty: $IntType<Width>) -> SimValue<$IntType<Width>> {
-                Arc::try_unwrap(self.into_bits())
-                    .unwrap_or_else(|v: Arc<BitVec>| v.to_bitvec())
-                    .into_sim_value(ty)
-            }
-
-            fn box_into_sim_value(
-                self: Box<Self>,
-                ty: $IntType<Width>,
-            ) -> SimValue<$IntType<Width>> {
-                Self::into_sim_value(*self, ty)
-            }
-        }
-
-        impl<Width: Size> ToSimValue<$Int> for $IntValue<Width> {
-            fn to_sim_value(&self, ty: $Int) -> SimValue<$Int> {
-                self.bits().to_bitvec().into_sim_value(ty)
-            }
-
-            fn into_sim_value(self, ty: $Int) -> SimValue<$Int> {
-                Arc::try_unwrap(self.into_bits())
-                    .unwrap_or_else(|v: Arc<BitVec>| v.to_bitvec())
-                    .into_sim_value(ty)
-            }
-
-            fn box_into_sim_value(self: Box<Self>, ty: $Int) -> SimValue<$Int> {
-                Self::into_sim_value(*self, ty)
-            }
-        }
-
-        impl<Width: Size> ToSimValue<CanonicalType> for $IntValue<Width> {
-            #[track_caller]
-            fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-                ToSimValue::<$Int>::to_sim_value(self, $Int::from_canonical(ty)).into_canonical()
-            }
-
-            #[track_caller]
-            fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType> {
-                ToSimValue::<$Int>::into_sim_value(self, $Int::from_canonical(ty)).into_canonical()
-            }
-
-            #[track_caller]
-            fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
-                Self::into_sim_value(*self, ty)
-            }
-        }
-    };
-}
-
-impl_to_sim_value_for_int_value!(UIntValue, UInt, UIntType);
-impl_to_sim_value_for_int_value!(SIntValue, SInt, SIntType);
-
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
 enum MaybeNeedsSettle<S, N = S> {
     NeedsSettle(S),
@@ -7024,19 +6397,19 @@ impl<I: BoolOrIntType> MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadBo
 struct ReadFn {
     compiled_value: CompiledValue<CanonicalType>,
     io: Expr<CanonicalType>,
-    bits: BitVec,
 }
 
 impl MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadFn {
     type Output = SimValue<CanonicalType>;
 
     fn call(self, state: &mut interpreter::State) -> Self::Output {
-        let Self {
-            compiled_value,
+        let Self { compiled_value, io } = self;
+        SimulationImpl::read_no_settle_helper(
+            state,
             io,
-            bits,
-        } = self;
-        SimulationImpl::read_no_settle_helper(state, io, compiled_value, bits)
+            compiled_value,
+            UIntValue::new(Arc::new(BitVec::repeat(false, Expr::ty(io).bit_width()))),
+        )
     }
 }
 
@@ -7390,7 +6763,7 @@ impl SimulationImpl {
                 (WaitTarget::Instant(instant), None) => Some(instant),
                 (WaitTarget::Instant(instant), Some(retval)) => Some(instant.min(retval)),
                 (WaitTarget::Change { key, value }, retval) => {
-                    if Self::value_changed(&mut self.state, key, &value.bits) {
+                    if Self::value_changed(&mut self.state, key, SimValue::bits(value).bits()) {
                         Some(self.instant)
                     } else {
                         retval
@@ -7688,7 +7061,7 @@ impl SimulationImpl {
         }
     }
     #[track_caller]
-    fn read_write_sim_value_helper<Bits>(
+    fn read_write_sim_value_helper<Bits: ?Sized>(
         state: &mut interpreter::State,
         compiled_value: CompiledValue<CanonicalType>,
         start_bit_index: usize,
@@ -7783,15 +7156,13 @@ impl SimulationImpl {
         state: &mut interpreter::State,
         io: Expr<CanonicalType>,
         compiled_value: CompiledValue<CanonicalType>,
-        mut bits: BitVec,
+        mut bits: UIntValue,
     ) -> SimValue<CanonicalType> {
-        bits.clear();
-        bits.resize(compiled_value.layout.ty.bit_width(), false);
         SimulationImpl::read_write_sim_value_helper(
             state,
             compiled_value,
             0,
-            &mut bits,
+            bits.bits_mut(),
             |_signed, bit_range, bits, value| {
                 <UInt>::copy_bits_from_bigint_wrapping(value, &mut bits[bit_range]);
             },
@@ -7802,10 +7173,7 @@ impl SimulationImpl {
                 bits[bit_range].clone_from_bitslice(bitslice);
             },
         );
-        SimValue {
-            ty: Expr::ty(io),
-            bits,
-        }
+        SimValue::from_bits(Expr::ty(io), bits)
     }
     /// doesn't modify `bits`
     fn value_changed(
@@ -7847,11 +7215,7 @@ impl SimulationImpl {
     ) {
         let compiled_value = self.get_module(which_module).read_helper(io, which_module);
         let value = compiled_value
-            .map(|compiled_value| ReadFn {
-                compiled_value,
-                io,
-                bits: BitVec::new(),
-            })
+            .map(|compiled_value| ReadFn { compiled_value, io })
             .apply_no_settle(&mut self.state);
         let (MaybeNeedsSettle::NeedsSettle(compiled_value)
         | MaybeNeedsSettle::NoSettleNeeded(compiled_value)) = compiled_value;
@@ -7868,12 +7232,12 @@ impl SimulationImpl {
             .get_module_mut(which_module)
             .write_helper(io, which_module);
         self.state_ready_to_run = true;
-        assert_eq!(Expr::ty(io), value.ty());
+        assert_eq!(Expr::ty(io), SimValue::ty(value));
         Self::read_write_sim_value_helper(
             &mut self.state,
             compiled_value,
             0,
-            &mut value.bits(),
+            &mut value.bits().bits(),
             |signed, bit_range, bits, value| {
                 if signed {
                     *value = SInt::bits_to_bigint(&bits[bit_range]);
@@ -8167,10 +7531,10 @@ macro_rules! impl_simulation_methods {
             SimValue::from_canonical($self.settle_if_needed(retval)$(.$await)?)
         }
         $(#[$track_caller])?
-        pub $($async)? fn write<IO: Type, V: ToSimValue<IO>>(&mut $self, io: Expr<IO>, value: V) {
+        pub $($async)? fn write<IO: Type, V: value::ToSimValue<IO>>(&mut $self, io: Expr<IO>, value: V) {
             $self.sim_impl.borrow_mut().write(
                 Expr::canonical(io),
-                &value.into_sim_value(Expr::ty(io)).into_canonical(),
+                &SimValue::into_canonical(value.into_sim_value(Expr::ty(io))),
                 $which_module,
             );
         }
diff --git a/crates/fayalite/src/sim/value.rs b/crates/fayalite/src/sim/value.rs
new file mode 100644
index 0000000..3e45016
--- /dev/null
+++ b/crates/fayalite/src/sim/value.rs
@@ -0,0 +1,665 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::{
+    array::{Array, ArrayType},
+    bundle::{Bundle, BundleType},
+    clock::Clock,
+    enum_::{Enum, EnumType},
+    expr::{CastBitsTo, Expr, ToExpr},
+    int::{Bool, IntType, KnownSize, SInt, SIntType, SIntValue, Size, UInt, UIntType, UIntValue},
+    reset::{AsyncReset, Reset, SyncReset},
+    ty::{CanonicalType, Type},
+    util::{
+        alternating_cell::{AlternatingCell, AlternatingCellMethods},
+        ConstUsize,
+    },
+};
+use bitvec::{slice::BitSlice, vec::BitVec};
+use std::{
+    fmt,
+    ops::{Deref, DerefMut},
+    sync::Arc,
+};
+
+#[derive(Copy, Clone, Eq, PartialEq)]
+enum ValidFlags {
+    BothValid = 0,
+    OnlyValueValid = 1,
+    OnlyBitsValid = 2,
+}
+
+#[derive(Clone)]
+struct SimValueInner<T: Type> {
+    value: T::SimValue,
+    bits: UIntValue,
+    valid_flags: ValidFlags,
+    ty: T,
+}
+
+impl<T: Type> SimValueInner<T> {
+    fn fill_bits(&mut self) {
+        match self.valid_flags {
+            ValidFlags::BothValid | ValidFlags::OnlyBitsValid => {}
+            ValidFlags::OnlyValueValid => {
+                self.ty.sim_value_to_bits(&self.value, self.bits.bits_mut());
+                self.valid_flags = ValidFlags::BothValid;
+            }
+        }
+    }
+    fn into_bits(mut self) -> UIntValue {
+        self.fill_bits();
+        self.bits
+    }
+    fn bits_mut(&mut self) -> &mut UIntValue {
+        self.fill_bits();
+        self.valid_flags = ValidFlags::OnlyBitsValid;
+        &mut self.bits
+    }
+    fn fill_value(&mut self) {
+        match self.valid_flags {
+            ValidFlags::BothValid | ValidFlags::OnlyValueValid => {}
+            ValidFlags::OnlyBitsValid => {
+                self.ty
+                    .sim_value_clone_from_bits(&mut self.value, self.bits.bits());
+                self.valid_flags = ValidFlags::BothValid;
+            }
+        }
+    }
+    fn into_value(mut self) -> T::SimValue {
+        self.fill_value();
+        self.value
+    }
+    fn value_mut(&mut self) -> &mut T::SimValue {
+        self.fill_value();
+        self.valid_flags = ValidFlags::OnlyValueValid;
+        &mut self.value
+    }
+}
+
+impl<T: Type> AlternatingCellMethods for SimValueInner<T> {
+    fn unique_to_shared(&mut self) {
+        match self.valid_flags {
+            ValidFlags::BothValid => return,
+            ValidFlags::OnlyValueValid => {
+                self.ty.sim_value_to_bits(&self.value, self.bits.bits_mut())
+            }
+            ValidFlags::OnlyBitsValid => self
+                .ty
+                .sim_value_clone_from_bits(&mut self.value, self.bits.bits()),
+        }
+        self.valid_flags = ValidFlags::BothValid;
+    }
+
+    fn shared_to_unique(&mut self) {}
+}
+
+pub struct SimValue<T: Type> {
+    inner: AlternatingCell<SimValueInner<T>>,
+}
+
+impl<T: Type + Clone> Clone for SimValue<T> {
+    fn clone(&self) -> Self {
+        Self {
+            inner: AlternatingCell::new_unique(self.inner.share().clone()),
+        }
+    }
+}
+
+impl<T: Type> SimValue<T> {
+    #[track_caller]
+    pub fn from_bits(ty: T, bits: UIntValue) -> Self {
+        assert_eq!(ty.canonical().bit_width(), bits.width());
+        let inner = SimValueInner {
+            value: ty.sim_value_from_bits(bits.bits()),
+            bits,
+            valid_flags: ValidFlags::BothValid,
+            ty,
+        };
+        Self {
+            inner: AlternatingCell::new_shared(inner),
+        }
+    }
+    #[track_caller]
+    pub fn from_bitslice(ty: T, bits: &BitSlice) -> Self {
+        Self::from_bits(ty, UIntValue::new(Arc::new(bits.to_bitvec())))
+    }
+    pub fn from_value(ty: T, value: T::SimValue) -> Self {
+        let inner = SimValueInner {
+            bits: UIntValue::new_dyn(Arc::new(BitVec::repeat(false, ty.canonical().bit_width()))),
+            value,
+            valid_flags: ValidFlags::OnlyValueValid,
+            ty,
+        };
+        Self {
+            inner: AlternatingCell::new_unique(inner),
+        }
+    }
+    pub fn ty(this: &Self) -> T {
+        this.inner.share().ty
+    }
+    pub fn into_bits(this: Self) -> UIntValue {
+        this.inner.into_inner().into_bits()
+    }
+    pub fn into_ty_and_bits(this: Self) -> (T, UIntValue) {
+        let inner = this.inner.into_inner();
+        (inner.ty, inner.into_bits())
+    }
+    pub fn bits(this: &Self) -> &UIntValue {
+        &this.inner.share().bits
+    }
+    pub fn bits_mut(this: &mut Self) -> &mut UIntValue {
+        this.inner.unique().bits_mut()
+    }
+    pub fn into_value(this: Self) -> T::SimValue {
+        this.inner.into_inner().into_value()
+    }
+    pub fn value(this: &Self) -> &T::SimValue {
+        &this.inner.share().value
+    }
+    pub fn value_mut(this: &mut Self) -> &mut T::SimValue {
+        this.inner.unique().value_mut()
+    }
+    #[track_caller]
+    pub fn from_canonical(v: SimValue<CanonicalType>) -> Self {
+        let (ty, bits) = SimValue::into_ty_and_bits(v);
+        Self::from_bits(T::from_canonical(ty), bits)
+    }
+    pub fn into_canonical(this: Self) -> SimValue<CanonicalType> {
+        let (ty, bits) = Self::into_ty_and_bits(this);
+        SimValue::from_bits(ty.canonical(), bits)
+    }
+    pub fn canonical(this: &Self) -> SimValue<CanonicalType> {
+        SimValue::from_bits(Self::ty(this).canonical(), Self::bits(this).clone())
+    }
+    #[track_caller]
+    pub fn from_dyn_int(v: SimValue<T::Dyn>) -> Self
+    where
+        T: IntType,
+    {
+        let (ty, bits) = SimValue::into_ty_and_bits(v);
+        SimValue::from_bits(T::from_dyn_int(ty), bits)
+    }
+    pub fn into_dyn_int(this: Self) -> SimValue<T::Dyn>
+    where
+        T: IntType,
+    {
+        let (ty, bits) = Self::into_ty_and_bits(this);
+        SimValue::from_bits(ty.as_dyn_int(), bits)
+    }
+    pub fn to_dyn_int(this: &Self) -> SimValue<T::Dyn>
+    where
+        T: IntType,
+    {
+        SimValue::from_bits(Self::ty(this).as_dyn_int(), Self::bits(&this).clone())
+    }
+    #[track_caller]
+    pub fn from_bundle(v: SimValue<Bundle>) -> Self
+    where
+        T: BundleType,
+    {
+        let (ty, bits) = SimValue::into_ty_and_bits(v);
+        SimValue::from_bits(T::from_canonical(CanonicalType::Bundle(ty)), bits)
+    }
+    pub fn into_bundle(this: Self) -> SimValue<Bundle>
+    where
+        T: BundleType,
+    {
+        let (ty, bits) = Self::into_ty_and_bits(this);
+        SimValue::from_bits(Bundle::from_canonical(ty.canonical()), bits)
+    }
+    pub fn to_bundle(this: &Self) -> SimValue<Bundle>
+    where
+        T: BundleType,
+    {
+        SimValue::from_bits(
+            Bundle::from_canonical(Self::ty(this).canonical()),
+            Self::bits(&this).clone(),
+        )
+    }
+    #[track_caller]
+    pub fn from_enum(v: SimValue<Enum>) -> Self
+    where
+        T: EnumType,
+    {
+        let (ty, bits) = SimValue::into_ty_and_bits(v);
+        SimValue::from_bits(T::from_canonical(CanonicalType::Enum(ty)), bits)
+    }
+    pub fn into_enum(this: Self) -> SimValue<Enum>
+    where
+        T: EnumType,
+    {
+        let (ty, bits) = Self::into_ty_and_bits(this);
+        SimValue::from_bits(Enum::from_canonical(ty.canonical()), bits)
+    }
+    pub fn to_enum(this: &Self) -> SimValue<Enum>
+    where
+        T: EnumType,
+    {
+        SimValue::from_bits(
+            Enum::from_canonical(Self::ty(this).canonical()),
+            Self::bits(&this).clone(),
+        )
+    }
+}
+
+impl<T: Type> Deref for SimValue<T> {
+    type Target = T::SimValue;
+
+    fn deref(&self) -> &Self::Target {
+        Self::value(self)
+    }
+}
+
+impl<T: Type> DerefMut for SimValue<T> {
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        Self::value_mut(self)
+    }
+}
+
+impl<T: Type> fmt::Debug for SimValue<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let inner = self.inner.share();
+        f.debug_struct("SimValue")
+            .field("ty", &inner.ty)
+            .field("value", &inner.value)
+            .finish()
+    }
+}
+
+impl<T: Type> ToExpr for SimValue<T> {
+    type Type = T;
+
+    #[track_caller]
+    fn to_expr(&self) -> Expr<Self::Type> {
+        let inner = self.inner.share();
+        inner.bits.cast_bits_to(inner.ty)
+    }
+}
+
+pub trait SimValuePartialEq<T: Type = Self>: Type {
+    #[track_caller]
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<T>) -> bool;
+}
+
+impl<T: SimValuePartialEq<U>, U: Type> PartialEq<SimValue<U>> for SimValue<T> {
+    #[track_caller]
+    fn eq(&self, other: &SimValue<U>) -> bool {
+        T::sim_value_eq(self, other)
+    }
+}
+
+impl<LhsWidth: Size, RhsWidth: Size> SimValuePartialEq<UIntType<RhsWidth>> for UIntType<LhsWidth> {
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<UIntType<RhsWidth>>) -> bool {
+        **this == **other
+    }
+}
+
+impl<LhsWidth: Size, RhsWidth: Size> SimValuePartialEq<SIntType<RhsWidth>> for SIntType<LhsWidth> {
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<SIntType<RhsWidth>>) -> bool {
+        **this == **other
+    }
+}
+
+impl SimValuePartialEq<Bool> for Bool {
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<Bool>) -> bool {
+        **this == **other
+    }
+}
+
+pub trait ToSimValue<T: Type> {
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T>;
+    #[track_caller]
+    fn into_sim_value(self, ty: T) -> SimValue<T>
+    where
+        Self: Sized,
+    {
+        self.to_sim_value(ty)
+    }
+    #[track_caller]
+    fn arc_into_sim_value(self: Arc<Self>, ty: T) -> SimValue<T> {
+        self.to_sim_value(ty)
+    }
+    #[track_caller]
+    fn arc_to_sim_value(self: &Arc<Self>, ty: T) -> SimValue<T> {
+        self.to_sim_value(ty)
+    }
+}
+
+impl<T: Type> ToSimValue<T> for SimValue<T> {
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        assert_eq!(SimValue::ty(self), ty);
+        self.clone()
+    }
+
+    #[track_caller]
+    fn into_sim_value(self, ty: T) -> SimValue<T> {
+        assert_eq!(SimValue::ty(&self), ty);
+        self
+    }
+}
+
+impl<T: Type> ToSimValue<T> for BitVec {
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        self.clone().into_sim_value(ty)
+    }
+
+    #[track_caller]
+    fn into_sim_value(self, ty: T) -> SimValue<T> {
+        Arc::new(self).arc_into_sim_value(ty)
+    }
+
+    #[track_caller]
+    fn arc_into_sim_value(self: Arc<Self>, ty: T) -> SimValue<T> {
+        SimValue::from_bits(ty, UIntValue::new_dyn(self))
+    }
+
+    #[track_caller]
+    fn arc_to_sim_value(self: &Arc<Self>, ty: T) -> SimValue<T> {
+        SimValue::from_bits(ty, UIntValue::new_dyn(self.clone()))
+    }
+}
+
+impl<T: Type> ToSimValue<T> for bitvec::boxed::BitBox {
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        self.clone().into_sim_value(ty)
+    }
+
+    #[track_caller]
+    fn into_sim_value(self, ty: T) -> SimValue<T> {
+        self.into_bitvec().into_sim_value(ty)
+    }
+}
+
+impl<T: Type> ToSimValue<T> for BitSlice {
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        self.to_bitvec().into_sim_value(ty)
+    }
+}
+
+impl<This: ?Sized + ToSimValue<T>, T: Type> ToSimValue<T> for &'_ This {
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value(self, ty)
+    }
+}
+
+impl<This: ?Sized + ToSimValue<T>, T: Type> ToSimValue<T> for &'_ mut This {
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value(self, ty)
+    }
+}
+
+impl<This: ?Sized + ToSimValue<T>, T: Type> ToSimValue<T> for Arc<This> {
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        This::arc_to_sim_value(self, ty)
+    }
+    fn into_sim_value(self, ty: T) -> SimValue<T> {
+        This::arc_into_sim_value(self, ty)
+    }
+}
+
+impl<This: ?Sized + ToSimValue<T> + Send + Sync + 'static, T: Type> ToSimValue<T>
+    for crate::intern::Interned<This>
+{
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value(self, ty)
+    }
+}
+
+impl<This: ToSimValue<T>, T: Type> ToSimValue<T> for Box<This> {
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value(self, ty)
+    }
+    fn into_sim_value(self, ty: T) -> SimValue<T> {
+        This::into_sim_value(*self, ty)
+    }
+}
+
+impl<T: Type, Len: Size> SimValue<ArrayType<T, Len>> {
+    #[track_caller]
+    pub fn from_array_elements<I: IntoIterator<Item: ToSimValue<T>>>(
+        ty: ArrayType<T, Len>,
+        elements: I,
+    ) -> Self {
+        let element_ty = ty.element();
+        let elements = Vec::from_iter(
+            elements
+                .into_iter()
+                .map(|element| element.into_sim_value(element_ty)),
+        );
+        assert_eq!(elements.len(), ty.len());
+        SimValue::from_value(ty, elements.try_into().ok().expect("already checked len"))
+    }
+}
+
+impl<Element: ToSimValue<T>, T: Type> ToSimValue<Array<T>> for [Element] {
+    #[track_caller]
+    fn to_sim_value(&self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+}
+
+impl<Element: ToSimValue<CanonicalType>> ToSimValue<CanonicalType> for [Element] {
+    #[track_caller]
+    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+}
+
+impl<Element: ToSimValue<T>, T: Type, const N: usize> ToSimValue<Array<T, N>> for [Element; N]
+where
+    ConstUsize<N>: KnownSize,
+{
+    #[track_caller]
+    fn to_sim_value(&self, ty: Array<T, N>) -> SimValue<Array<T, N>> {
+        SimValue::from_array_elements(ty, self)
+    }
+    #[track_caller]
+    fn into_sim_value(self, ty: Array<T, N>) -> SimValue<Array<T, N>> {
+        SimValue::from_array_elements(ty, self)
+    }
+}
+
+impl<Element: ToSimValue<T>, T: Type, const N: usize> ToSimValue<Array<T>> for [Element; N] {
+    #[track_caller]
+    fn to_sim_value(&self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+    #[track_caller]
+    fn into_sim_value(self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+}
+
+impl<Element: ToSimValue<CanonicalType>, const N: usize> ToSimValue<CanonicalType>
+    for [Element; N]
+{
+    #[track_caller]
+    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+    #[track_caller]
+    fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+}
+
+impl<Element: ToSimValue<T>, T: Type> ToSimValue<Array<T>> for Vec<Element> {
+    #[track_caller]
+    fn to_sim_value(&self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+    #[track_caller]
+    fn into_sim_value(self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+}
+
+impl<Element: ToSimValue<CanonicalType>> ToSimValue<CanonicalType> for Vec<Element> {
+    #[track_caller]
+    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+    #[track_caller]
+    fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+}
+
+impl<T: Type> ToSimValue<T> for Expr<T> {
+    #[track_caller]
+    fn to_sim_value(&self, ty: T) -> SimValue<T> {
+        assert_eq!(Expr::ty(*self), ty);
+        SimValue::from_bitslice(
+            ty,
+            &crate::expr::ToLiteralBits::to_literal_bits(self)
+                .expect("must be a literal expression"),
+        )
+    }
+}
+
+macro_rules! impl_to_sim_value_for_bool_like {
+    ($ty:ident) => {
+        impl ToSimValue<$ty> for bool {
+            fn to_sim_value(&self, ty: $ty) -> SimValue<$ty> {
+                SimValue::from_value(ty, *self)
+            }
+        }
+    };
+}
+
+impl_to_sim_value_for_bool_like!(Bool);
+impl_to_sim_value_for_bool_like!(AsyncReset);
+impl_to_sim_value_for_bool_like!(SyncReset);
+impl_to_sim_value_for_bool_like!(Reset);
+impl_to_sim_value_for_bool_like!(Clock);
+
+impl ToSimValue<CanonicalType> for bool {
+    #[track_caller]
+    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        match ty {
+            CanonicalType::UInt(_)
+            | CanonicalType::SInt(_)
+            | CanonicalType::Array(_)
+            | CanonicalType::Enum(_)
+            | CanonicalType::Bundle(_)
+            | CanonicalType::PhantomConst(_) => {
+                panic!("can't create SimValue from bool: expected value of type: {ty:?}");
+            }
+            CanonicalType::Bool(_)
+            | CanonicalType::AsyncReset(_)
+            | CanonicalType::SyncReset(_)
+            | CanonicalType::Reset(_)
+            | CanonicalType::Clock(_) => {
+                SimValue::from_bits(ty, UIntValue::new(Arc::new(BitVec::repeat(*self, 1))))
+            }
+        }
+    }
+}
+
+macro_rules! impl_to_sim_value_for_primitive_int {
+    ($prim:ident) => {
+        impl ToSimValue<<$prim as ToExpr>::Type> for $prim {
+            #[track_caller]
+            fn to_sim_value(
+                &self,
+                ty: <$prim as ToExpr>::Type,
+            ) -> SimValue<<$prim as ToExpr>::Type> {
+                SimValue::from_value(ty, (*self).into())
+            }
+        }
+
+        impl ToSimValue<<<$prim as ToExpr>::Type as IntType>::Dyn> for $prim {
+            #[track_caller]
+            fn to_sim_value(
+                &self,
+                ty: <<$prim as ToExpr>::Type as IntType>::Dyn,
+            ) -> SimValue<<<$prim as ToExpr>::Type as IntType>::Dyn> {
+                SimValue::from_value(
+                    ty,
+                    <<$prim as ToExpr>::Type as Type>::SimValue::from(*self).as_dyn_int(),
+                )
+            }
+        }
+
+        impl ToSimValue<CanonicalType> for $prim {
+            #[track_caller]
+            fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+                let ty: <<$prim as ToExpr>::Type as IntType>::Dyn = Type::from_canonical(ty);
+                SimValue::into_canonical(self.to_sim_value(ty))
+            }
+        }
+    };
+}
+
+impl_to_sim_value_for_primitive_int!(u8);
+impl_to_sim_value_for_primitive_int!(u16);
+impl_to_sim_value_for_primitive_int!(u32);
+impl_to_sim_value_for_primitive_int!(u64);
+impl_to_sim_value_for_primitive_int!(u128);
+impl_to_sim_value_for_primitive_int!(usize);
+impl_to_sim_value_for_primitive_int!(i8);
+impl_to_sim_value_for_primitive_int!(i16);
+impl_to_sim_value_for_primitive_int!(i32);
+impl_to_sim_value_for_primitive_int!(i64);
+impl_to_sim_value_for_primitive_int!(i128);
+impl_to_sim_value_for_primitive_int!(isize);
+
+macro_rules! impl_to_sim_value_for_int_value {
+    ($IntValue:ident, $Int:ident, $IntType:ident) => {
+        impl<Width: KnownSize> ToSimValue<$IntType<Width>> for $IntValue<Width> {
+            fn to_sim_value(&self, ty: $IntType<Width>) -> SimValue<$IntType<Width>> {
+                self.bits().to_sim_value(ty)
+            }
+
+            fn into_sim_value(self, ty: $IntType<Width>) -> SimValue<$IntType<Width>> {
+                self.into_bits().into_sim_value(ty)
+            }
+        }
+
+        impl<Width: Size> ToSimValue<$Int> for $IntValue<Width> {
+            fn to_sim_value(&self, ty: $Int) -> SimValue<$Int> {
+                self.bits().to_sim_value(ty)
+            }
+
+            fn into_sim_value(self, ty: $Int) -> SimValue<$Int> {
+                self.into_bits().into_sim_value(ty)
+            }
+        }
+
+        impl<Width: Size> ToSimValue<CanonicalType> for $IntValue<Width> {
+            #[track_caller]
+            fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+                SimValue::into_canonical(self.to_sim_value($Int::from_canonical(ty)))
+            }
+
+            #[track_caller]
+            fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType> {
+                SimValue::into_canonical(self.into_sim_value($Int::from_canonical(ty)))
+            }
+        }
+    };
+}
+
+impl_to_sim_value_for_int_value!(UIntValue, UInt, UIntType);
+impl_to_sim_value_for_int_value!(SIntValue, SInt, SIntType);
diff --git a/crates/fayalite/src/ty.rs b/crates/fayalite/src/ty.rs
index 2786782..cd26c9b 100644
--- a/crates/fayalite/src/ty.rs
+++ b/crates/fayalite/src/ty.rs
@@ -7,14 +7,15 @@ use crate::{
     clock::Clock,
     enum_::Enum,
     expr::Expr,
-    int::{Bool, SInt, UInt},
+    int::{Bool, SInt, UInt, UIntValue},
     intern::{Intern, Interned},
     phantom_const::PhantomConst,
     reset::{AsyncReset, Reset, SyncReset},
     source_location::SourceLocation,
     util::ConstUsize,
 };
-use std::{fmt, hash::Hash, iter::FusedIterator, ops::Index};
+use bitvec::slice::BitSlice;
+use std::{fmt, hash::Hash, iter::FusedIterator, ops::Index, sync::Arc};
 
 #[derive(Copy, Clone, Hash, PartialEq, Eq, Debug)]
 #[non_exhaustive]
@@ -268,6 +269,7 @@ pub trait Type:
 {
     type BaseType: BaseType;
     type MaskType: Type<MaskType = Self::MaskType>;
+    type SimValue: fmt::Debug + Clone + 'static;
     type MatchVariant: 'static + Send + Sync;
     type MatchActiveScope;
     type MatchVariantAndInactiveScope: MatchVariantAndInactiveScope<
@@ -285,6 +287,9 @@ pub trait Type:
     fn canonical(&self) -> CanonicalType;
     fn from_canonical(canonical_type: CanonicalType) -> Self;
     fn source_location() -> SourceLocation;
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue;
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice);
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice);
 }
 
 pub trait BaseType: Type<BaseType = Self> + sealed::BaseTypeSealed + Into<CanonicalType> {}
@@ -314,6 +319,7 @@ pub trait TypeWithDeref: Type {
 impl Type for CanonicalType {
     type BaseType = CanonicalType;
     type MaskType = CanonicalType;
+    type SimValue = OpaqueSimValue;
     impl_match_variant_as_self!();
     fn mask_type(&self) -> Self::MaskType {
         match self {
@@ -339,6 +345,48 @@ impl Type for CanonicalType {
     fn source_location() -> SourceLocation {
         SourceLocation::builtin()
     }
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        assert_eq!(bits.len(), self.bit_width());
+        OpaqueSimValue::from_bitslice(bits)
+    }
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+        assert_eq!(bits.len(), self.bit_width());
+        assert_eq!(value.bit_width(), self.bit_width());
+        value.bits_mut().bits_mut().copy_from_bitslice(bits);
+    }
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+        assert_eq!(bits.len(), self.bit_width());
+        assert_eq!(value.bit_width(), self.bit_width());
+        bits.copy_from_bitslice(value.bits().bits());
+    }
+}
+
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+pub struct OpaqueSimValue {
+    bits: UIntValue,
+}
+
+impl OpaqueSimValue {
+    pub fn bit_width(&self) -> usize {
+        self.bits.width()
+    }
+    pub fn bits(&self) -> &UIntValue {
+        &self.bits
+    }
+    pub fn bits_mut(&mut self) -> &mut UIntValue {
+        &mut self.bits
+    }
+    pub fn into_bits(self) -> UIntValue {
+        self.bits
+    }
+    pub fn from_bits(bits: UIntValue) -> Self {
+        Self { bits }
+    }
+    pub fn from_bitslice(v: &BitSlice) -> Self {
+        Self {
+            bits: UIntValue::new(Arc::new(v.to_bitvec())),
+        }
+    }
 }
 
 pub trait StaticType: Type {
diff --git a/crates/fayalite/src/util.rs b/crates/fayalite/src/util.rs
index 66fc921..804ff19 100644
--- a/crates/fayalite/src/util.rs
+++ b/crates/fayalite/src/util.rs
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 
+pub(crate) mod alternating_cell;
 mod const_bool;
 mod const_cmp;
 mod const_usize;
diff --git a/crates/fayalite/src/util/alternating_cell.rs b/crates/fayalite/src/util/alternating_cell.rs
new file mode 100644
index 0000000..17e06a6
--- /dev/null
+++ b/crates/fayalite/src/util/alternating_cell.rs
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::util::DebugAsDisplay;
+use std::{
+    cell::{Cell, UnsafeCell},
+    fmt,
+};
+
+pub(crate) trait AlternatingCellMethods {
+    fn unique_to_shared(&mut self);
+    fn shared_to_unique(&mut self);
+}
+
+#[derive(Copy, Clone, Debug)]
+enum State {
+    Unique,
+    Shared,
+    Locked,
+}
+
+pub(crate) struct AlternatingCell<T: ?Sized> {
+    state: Cell<State>,
+    value: UnsafeCell<T>,
+}
+
+impl<T: ?Sized + fmt::Debug + AlternatingCellMethods> fmt::Debug for AlternatingCell<T> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_tuple("AlternatingCell")
+            .field(
+                self.try_share()
+                    .as_ref()
+                    .map(|v| -> &dyn fmt::Debug { v })
+                    .unwrap_or(&DebugAsDisplay("<...>")),
+            )
+            .finish()
+    }
+}
+
+impl<T: ?Sized> AlternatingCell<T> {
+    pub(crate) const fn new_shared(value: T) -> Self
+    where
+        T: Sized,
+    {
+        Self {
+            state: Cell::new(State::Shared),
+            value: UnsafeCell::new(value),
+        }
+    }
+    pub(crate) const fn new_unique(value: T) -> Self
+    where
+        T: Sized,
+    {
+        Self {
+            state: Cell::new(State::Unique),
+            value: UnsafeCell::new(value),
+        }
+    }
+    pub(crate) fn is_unique(&self) -> bool {
+        matches!(self.state.get(), State::Unique)
+    }
+    pub(crate) fn is_shared(&self) -> bool {
+        matches!(self.state.get(), State::Shared)
+    }
+    pub(crate) fn into_inner(self) -> T
+    where
+        T: Sized,
+    {
+        self.value.into_inner()
+    }
+    pub(crate) fn try_share(&self) -> Option<&T>
+    where
+        T: AlternatingCellMethods,
+    {
+        match self.state.get() {
+            State::Shared => {}
+            State::Unique => {
+                struct Locked<'a>(&'a Cell<State>);
+                impl Drop for Locked<'_> {
+                    fn drop(&mut self) {
+                        self.0.set(State::Shared);
+                    }
+                }
+                self.state.set(State::Locked);
+                let lock = Locked(&self.state);
+                // Safety: state is Locked, so nothing else will
+                // access value while calling unique_to_shared.
+                unsafe { &mut *self.value.get() }.unique_to_shared();
+                drop(lock);
+            }
+            State::Locked => return None,
+        }
+
+        // Safety: state is Shared so nothing will create any mutable
+        // references until the returned reference's lifetime expires.
+        Some(unsafe { &*self.value.get() })
+    }
+    #[track_caller]
+    pub(crate) fn share(&self) -> &T
+    where
+        T: AlternatingCellMethods,
+    {
+        let Some(retval) = self.try_share() else {
+            panic!("`share` called recursively");
+        };
+        retval
+    }
+    pub(crate) fn unique(&mut self) -> &mut T
+    where
+        T: AlternatingCellMethods,
+    {
+        match self.state.get() {
+            State::Shared => {
+                self.state.set(State::Unique);
+                self.value.get_mut().shared_to_unique();
+            }
+            State::Unique => {}
+            State::Locked => unreachable!(),
+        }
+        self.value.get_mut()
+    }
+}
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 450be54..eb5c79e 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -3,10 +3,16 @@
 
 use fayalite::{
     int::UIntValue,
+    memory::{ReadStruct, ReadWriteStruct, WriteStruct},
     module::{instance_with_loc, reg_builder_with_loc},
     prelude::*,
     reset::ResetType,
-    sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation, ToSimValue},
+    sim::{
+        time::SimDuration,
+        value::{SimValue, ToSimValue},
+        vcd::VcdWriterDecls,
+        Simulation,
+    },
     ty::StaticType,
     util::RcWriter,
 };
@@ -396,32 +402,14 @@ fn test_enums() {
     sim.write_reset(sim.io().cd.rst, false);
     sim.advance_time(SimDuration::from_nanos(900));
     type BOutTy = HdlOption<(UInt<1>, Bool)>;
-    #[derive(Debug)]
+    #[derive(Debug, PartialEq)]
     struct IO {
         en: bool,
         which_in: u8,
         data_in: u8,
         which_out: u8,
         data_out: u8,
-        b_out: Expr<BOutTy>,
-    }
-    impl PartialEq for IO {
-        fn eq(&self, other: &Self) -> bool {
-            let Self {
-                en,
-                which_in,
-                data_in,
-                which_out,
-                data_out,
-                b_out,
-            } = *self;
-            en == other.en
-                && which_in == other.which_in
-                && data_in == other.data_in
-                && which_out == other.which_out
-                && data_out == other.data_out
-                && b_out.to_sim_value(BOutTy::TYPE) == other.b_out.to_sim_value(BOutTy::TYPE)
-        }
+        b_out: SimValue<BOutTy>,
     }
     let io_cycles = [
         IO {
@@ -430,7 +418,7 @@ fn test_enums() {
             data_in: 0,
             which_out: 0,
             data_out: 0,
-            b_out: HdlNone(),
+            b_out: HdlNone().to_sim_value(StaticType::TYPE),
         },
         IO {
             en: true,
@@ -438,7 +426,7 @@ fn test_enums() {
             data_in: 0,
             which_out: 0,
             data_out: 0,
-            b_out: HdlNone(),
+            b_out: HdlNone().to_sim_value(StaticType::TYPE),
         },
         IO {
             en: false,
@@ -446,7 +434,7 @@ fn test_enums() {
             data_in: 0,
             which_out: 1,
             data_out: 0,
-            b_out: HdlSome((0_hdl_u1, false)),
+            b_out: HdlSome((0_hdl_u1, false)).to_sim_value(StaticType::TYPE),
         },
         IO {
             en: true,
@@ -454,7 +442,7 @@ fn test_enums() {
             data_in: 0xF,
             which_out: 1,
             data_out: 0,
-            b_out: HdlSome((0_hdl_u1, false)),
+            b_out: HdlSome((0_hdl_u1, false)).to_sim_value(StaticType::TYPE),
         },
         IO {
             en: true,
@@ -462,7 +450,7 @@ fn test_enums() {
             data_in: 0xF,
             which_out: 1,
             data_out: 0x3,
-            b_out: HdlSome((1_hdl_u1, true)),
+            b_out: HdlSome((1_hdl_u1, true)).to_sim_value(StaticType::TYPE),
         },
         IO {
             en: true,
@@ -470,7 +458,7 @@ fn test_enums() {
             data_in: 0xF,
             which_out: 1,
             data_out: 0x3,
-            b_out: HdlSome((1_hdl_u1, true)),
+            b_out: HdlSome((1_hdl_u1, true)).to_sim_value(StaticType::TYPE),
         },
         IO {
             en: true,
@@ -478,7 +466,7 @@ fn test_enums() {
             data_in: 0xF,
             which_out: 2,
             data_out: 0xF,
-            b_out: HdlNone(),
+            b_out: HdlNone().to_sim_value(StaticType::TYPE),
         },
     ];
     for (
@@ -510,7 +498,7 @@ fn test_enums() {
                 .to_bigint()
                 .try_into()
                 .expect("known to be in range"),
-            b_out: sim.read(sim.io().b_out).to_expr(),
+            b_out: sim.read(sim.io().b_out),
         };
         assert_eq!(
             expected,
@@ -539,9 +527,9 @@ fn test_enums() {
 #[hdl_module(outline_generated)]
 pub fn memories() {
     #[hdl]
-    let r: fayalite::memory::ReadStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
+    let r: ReadStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
     #[hdl]
-    let w: fayalite::memory::WriteStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
+    let w: WriteStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
     #[hdl]
     let mut mem = memory_with_init([(0x01u8, 0x23i8); 16]);
     mem.read_latency(0);
@@ -560,120 +548,131 @@ fn test_memories() {
     sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
     sim.write_clock(sim.io().r.clk, false);
     sim.write_clock(sim.io().w.clk, false);
-    #[derive(Debug, PartialEq, Eq)]
+    #[hdl(cmp_eq)]
     struct IO {
-        r_addr: u8,
-        r_en: bool,
-        r_data: (u8, i8),
-        w_addr: u8,
-        w_en: bool,
-        w_data: (u8, i8),
-        w_mask: (bool, bool),
+        r_addr: UInt<4>,
+        r_en: Bool,
+        r_data: (UInt<8>, SInt<8>),
+        w_addr: UInt<4>,
+        w_en: Bool,
+        w_data: (UInt<8>, SInt<8>),
+        w_mask: (Bool, Bool),
     }
     let io_cycles = [
+        #[hdl]
         IO {
-            r_addr: 0,
+            r_addr: 0_hdl_u4,
             r_en: false,
-            r_data: (0, 0),
-            w_addr: 0,
+            r_data: (0u8, 0i8),
+            w_addr: 0_hdl_u4,
             w_en: false,
-            w_data: (0, 0),
+            w_data: (0u8, 0i8),
             w_mask: (false, false),
         },
+        #[hdl]
         IO {
-            r_addr: 0,
+            r_addr: 0_hdl_u4,
             r_en: true,
-            r_data: (0x1, 0x23),
-            w_addr: 0,
+            r_data: (0x1u8, 0x23i8),
+            w_addr: 0_hdl_u4,
             w_en: true,
-            w_data: (0x10, 0x20),
+            w_data: (0x10u8, 0x20i8),
             w_mask: (true, true),
         },
+        #[hdl]
         IO {
-            r_addr: 0,
+            r_addr: 0_hdl_u4,
             r_en: true,
-            r_data: (0x10, 0x20),
-            w_addr: 0,
+            r_data: (0x10u8, 0x20i8),
+            w_addr: 0_hdl_u4,
             w_en: true,
-            w_data: (0x30, 0x40),
+            w_data: (0x30u8, 0x40i8),
             w_mask: (false, true),
         },
+        #[hdl]
         IO {
-            r_addr: 0,
+            r_addr: 0_hdl_u4,
             r_en: true,
-            r_data: (0x10, 0x40),
-            w_addr: 0,
+            r_data: (0x10u8, 0x40i8),
+            w_addr: 0_hdl_u4,
             w_en: true,
-            w_data: (0x50, 0x60),
+            w_data: (0x50u8, 0x60i8),
             w_mask: (true, false),
         },
+        #[hdl]
         IO {
-            r_addr: 0,
+            r_addr: 0_hdl_u4,
             r_en: true,
-            r_data: (0x50, 0x40),
-            w_addr: 0,
+            r_data: (0x50u8, 0x40i8),
+            w_addr: 0_hdl_u4,
             w_en: true,
-            w_data: (0x70, -0x80),
+            w_data: (0x70u8, -0x80i8),
             w_mask: (false, false),
         },
+        #[hdl]
         IO {
-            r_addr: 0,
+            r_addr: 0_hdl_u4,
             r_en: true,
-            r_data: (0x50, 0x40),
-            w_addr: 0,
+            r_data: (0x50u8, 0x40i8),
+            w_addr: 0_hdl_u4,
             w_en: false,
-            w_data: (0x90, 0xA0u8 as i8),
+            w_data: (0x90u8, 0xA0u8 as i8),
             w_mask: (false, false),
         },
+        #[hdl]
         IO {
-            r_addr: 0,
+            r_addr: 0_hdl_u4,
             r_en: true,
-            r_data: (0x50, 0x40),
-            w_addr: 1,
+            r_data: (0x50u8, 0x40i8),
+            w_addr: 1_hdl_u4,
             w_en: true,
-            w_data: (0x90, 0xA0u8 as i8),
+            w_data: (0x90u8, 0xA0u8 as i8),
             w_mask: (true, true),
         },
+        #[hdl]
         IO {
-            r_addr: 0,
+            r_addr: 0_hdl_u4,
             r_en: true,
-            r_data: (0x50, 0x40),
-            w_addr: 2,
+            r_data: (0x50u8, 0x40i8),
+            w_addr: 2_hdl_u4,
             w_en: true,
-            w_data: (0xB0, 0xC0u8 as i8),
+            w_data: (0xB0u8, 0xC0u8 as i8),
             w_mask: (true, true),
         },
+        #[hdl]
         IO {
-            r_addr: 0,
+            r_addr: 0_hdl_u4,
             r_en: true,
-            r_data: (0x50, 0x40),
-            w_addr: 2,
+            r_data: (0x50u8, 0x40i8),
+            w_addr: 2_hdl_u4,
             w_en: false,
-            w_data: (0xD0, 0xE0u8 as i8),
+            w_data: (0xD0u8, 0xE0u8 as i8),
             w_mask: (true, true),
         },
+        #[hdl]
         IO {
-            r_addr: 1,
+            r_addr: 1_hdl_u4,
             r_en: true,
-            r_data: (0x90, 0xA0u8 as i8),
-            w_addr: 2,
+            r_data: (0x90u8, 0xA0u8 as i8),
+            w_addr: 2_hdl_u4,
             w_en: false,
-            w_data: (0xD0, 0xE0u8 as i8),
+            w_data: (0xD0u8, 0xE0u8 as i8),
             w_mask: (true, true),
         },
+        #[hdl]
         IO {
-            r_addr: 2,
+            r_addr: 2_hdl_u4,
             r_en: true,
-            r_data: (0xB0, 0xC0u8 as i8),
-            w_addr: 2,
+            r_data: (0xB0u8, 0xC0u8 as i8),
+            w_addr: 2_hdl_u4,
             w_en: false,
-            w_data: (0xD0, 0xE0u8 as i8),
+            w_data: (0xD0u8, 0xE0u8 as i8),
             w_mask: (true, true),
         },
     ];
-    for (
-        cycle,
-        expected @ IO {
+    for (cycle, expected) in io_cycles.into_iter().enumerate() {
+        #[hdl]
+        let IO {
             r_addr,
             r_en,
             r_data: _,
@@ -681,37 +680,26 @@ fn test_memories() {
             w_en,
             w_data,
             w_mask,
-        },
-    ) in io_cycles.into_iter().enumerate()
-    {
-        sim.write_bool_or_int(sim.io().r.addr, r_addr.cast_to_static());
-        sim.write_bool(sim.io().r.en, r_en);
-        sim.write_bool_or_int(sim.io().w.addr, w_addr.cast_to_static());
-        sim.write_bool(sim.io().w.en, w_en);
-        sim.write_bool_or_int(sim.io().w.data.0, w_data.0);
-        sim.write_bool_or_int(sim.io().w.data.1, w_data.1);
-        sim.write_bool(sim.io().w.mask.0, w_mask.0);
-        sim.write_bool(sim.io().w.mask.1, w_mask.1);
-        let io = IO {
+        } = expected;
+        sim.write(sim.io().r.addr, r_addr);
+        sim.write(sim.io().r.en, r_en);
+        sim.write(sim.io().w.addr, w_addr);
+        sim.write(sim.io().w.en, w_en);
+        sim.write(sim.io().w.data, w_data);
+        sim.write(sim.io().w.mask, w_mask);
+        let io = (#[hdl]
+        IO {
             r_addr,
             r_en,
-            r_data: (
-                sim.read_bool_or_int(sim.io().r.data.0)
-                    .to_bigint()
-                    .try_into()
-                    .expect("known to be in range"),
-                sim.read_bool_or_int(sim.io().r.data.1)
-                    .to_bigint()
-                    .try_into()
-                    .expect("known to be in range"),
-            ),
+            r_data: sim.read(sim.io().r.data),
             w_addr,
             w_en,
             w_data,
             w_mask,
-        };
+        })
+        .to_sim_value(StaticType::TYPE);
         assert_eq!(
-            expected,
+            expected.to_sim_value(StaticType::TYPE),
             io,
             "vcd:\n{}\ncycle: {cycle}",
             String::from_utf8(writer.take()).unwrap(),
@@ -739,7 +727,7 @@ fn test_memories() {
 #[hdl_module(outline_generated)]
 pub fn memories2() {
     #[hdl]
-    let rw: fayalite::memory::ReadWriteStruct<UInt<2>, ConstUsize<3>> = m.input();
+    let rw: ReadWriteStruct<UInt<2>, ConstUsize<3>> = m.input();
     #[hdl]
     let mut mem = memory_with_init([HdlSome(true); 5]);
     mem.read_latency(1);
@@ -1012,9 +1000,9 @@ fn test_memories2() {
 #[hdl_module(outline_generated)]
 pub fn memories3() {
     #[hdl]
-    let r: fayalite::memory::ReadStruct<Array<UInt<8>, 8>, ConstUsize<3>> = m.input();
+    let r: ReadStruct<Array<UInt<8>, 8>, ConstUsize<3>> = m.input();
     #[hdl]
-    let w: fayalite::memory::WriteStruct<Array<UInt<8>, 8>, ConstUsize<3>> = m.input();
+    let w: WriteStruct<Array<UInt<8>, 8>, ConstUsize<3>> = m.input();
     #[hdl]
     let mut mem: MemBuilder<Array<UInt<8>, 8>> = memory();
     mem.depth(8);
diff --git a/crates/fayalite/tests/sim/expected/extern_module2.txt b/crates/fayalite/tests/sim/expected/extern_module2.txt
index 96710fb..ec842ff 100644
--- a/crates/fayalite/tests/sim/expected/extern_module2.txt
+++ b/crates/fayalite/tests/sim/expected/extern_module2.txt
@@ -222,7 +222,9 @@ Simulation {
                     },
                     value: SimValue {
                         ty: Clock,
-                        bits: 0x1,
+                        value: OpaqueSimValue {
+                            bits: 0x1_u1,
+                        },
                     },
                 },
             },
diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.txt b/crates/fayalite/tests/sim/expected/ripple_counter.txt
index e290ace..5472950 100644
--- a/crates/fayalite/tests/sim/expected/ripple_counter.txt
+++ b/crates/fayalite/tests/sim/expected/ripple_counter.txt
@@ -826,7 +826,9 @@ Simulation {
                     },
                     value: SimValue {
                         ty: Clock,
-                        bits: 0x0,
+                        value: OpaqueSimValue {
+                            bits: 0x0_u1,
+                        },
                     },
                 },
             },
@@ -921,7 +923,9 @@ Simulation {
                     },
                     value: SimValue {
                         ty: Clock,
-                        bits: 0x0,
+                        value: OpaqueSimValue {
+                            bits: 0x0_u1,
+                        },
                     },
                 },
             },
@@ -1016,7 +1020,9 @@ Simulation {
                     },
                     value: SimValue {
                         ty: Clock,
-                        bits: 0x0,
+                        value: OpaqueSimValue {
+                            bits: 0x0_u1,
+                        },
                     },
                 },
             },

From a40eaaa2da1731eb7af535dbd6b910408f3874dc Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 30 Mar 2025 00:55:38 -0700
Subject: [PATCH 171/190] expand SimValue support

---
 .../src/hdl_bundle.rs                         |  96 ++++
 .../fayalite-proc-macros-impl/src/hdl_enum.rs |  46 ++
 crates/fayalite-proc-macros-impl/src/lib.rs   |   1 +
 .../src/module/transform_body.rs              |  46 +-
 .../expand_aggregate_literals.rs              | 111 ++++-
 .../src/module/transform_body/expand_match.rs | 113 +++--
 crates/fayalite/src/bundle.rs                 |  85 ++--
 crates/fayalite/src/int.rs                    |   9 +-
 crates/fayalite/src/phantom_const.rs          |  32 +-
 crates/fayalite/src/sim.rs                    |   4 +-
 crates/fayalite/src/sim/value.rs              | 455 +++++++++++++-----
 crates/fayalite/src/ty.rs                     |  12 +-
 crates/fayalite/tests/sim.rs                  | 196 ++++----
 13 files changed, 864 insertions(+), 342 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
index a083def..8e49ac4 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
@@ -692,6 +692,12 @@ impl ToTokens for ParsedBundle {
                 v.field_to_bits(&value.#ident);
             }
         }));
+        let to_sim_value_fields = Vec::from_iter(fields.named().into_iter().map(|field| {
+            let ident: &Ident = field.ident().as_ref().unwrap();
+            quote_spanned! {span=>
+                #ident: ::fayalite::sim::value::SimValue::ty(&self.#ident),
+            }
+        }));
         let fields_len = fields.named().into_iter().len();
         quote_spanned! {span=>
             #[automatically_derived]
@@ -797,6 +803,51 @@ impl ToTokens for ParsedBundle {
                 }
             }
             #[automatically_derived]
+            impl #impl_generics ::fayalite::sim::value::ToSimValue for #mask_type_sim_value_ident #type_generics
+            #where_clause
+            {
+                type Type = #mask_type_ident #type_generics;
+
+                fn to_sim_value(
+                    &self,
+                ) -> ::fayalite::sim::value::SimValue<
+                    <Self as ::fayalite::sim::value::ToSimValue>::Type,
+                > {
+                    let ty = #mask_type_ident {
+                        #(#to_sim_value_fields)*
+                    };
+                    ::fayalite::sim::value::SimValue::from_value(ty, ::fayalite::__std::clone::Clone::clone(self))
+                }
+                fn into_sim_value(
+                    self,
+                ) -> ::fayalite::sim::value::SimValue<
+                    <Self as ::fayalite::sim::value::ToSimValue>::Type,
+                > {
+                    let ty = #mask_type_ident {
+                        #(#to_sim_value_fields)*
+                    };
+                    ::fayalite::sim::value::SimValue::from_value(ty, self)
+                }
+            }
+            #[automatically_derived]
+            impl #impl_generics ::fayalite::sim::value::ToSimValueWithType<#mask_type_ident #type_generics>
+            for #mask_type_sim_value_ident #type_generics
+            #where_clause
+            {
+                fn to_sim_value_with_type(
+                    &self,
+                    ty: #mask_type_ident #type_generics,
+                ) -> ::fayalite::sim::value::SimValue<#mask_type_ident #type_generics> {
+                    ::fayalite::sim::value::SimValue::from_value(ty, ::fayalite::__std::clone::Clone::clone(self))
+                }
+                fn into_sim_value_with_type(
+                    self,
+                    ty: #mask_type_ident #type_generics,
+                ) -> ::fayalite::sim::value::SimValue<#mask_type_ident #type_generics> {
+                    ::fayalite::sim::value::SimValue::from_value(ty, self)
+                }
+            }
+            #[automatically_derived]
             impl #impl_generics ::fayalite::ty::Type for #target #type_generics
             #where_clause
             {
@@ -900,6 +951,51 @@ impl ToTokens for ParsedBundle {
                     ::fayalite::intern::Interned::into_inner(::fayalite::intern::Intern::intern_sized(__retval))
                 }
             }
+            #[automatically_derived]
+            impl #impl_generics ::fayalite::sim::value::ToSimValue for #sim_value_ident #type_generics
+            #where_clause
+            {
+                type Type = #target #type_generics;
+
+                fn to_sim_value(
+                    &self,
+                ) -> ::fayalite::sim::value::SimValue<
+                    <Self as ::fayalite::sim::value::ToSimValue>::Type,
+                > {
+                    let ty = #target {
+                        #(#to_sim_value_fields)*
+                    };
+                    ::fayalite::sim::value::SimValue::from_value(ty, ::fayalite::__std::clone::Clone::clone(self))
+                }
+                fn into_sim_value(
+                    self,
+                ) -> ::fayalite::sim::value::SimValue<
+                    <Self as ::fayalite::sim::value::ToSimValue>::Type,
+                > {
+                    let ty = #target {
+                        #(#to_sim_value_fields)*
+                    };
+                    ::fayalite::sim::value::SimValue::from_value(ty, self)
+                }
+            }
+            #[automatically_derived]
+            impl #impl_generics ::fayalite::sim::value::ToSimValueWithType<#target #type_generics>
+            for #sim_value_ident #type_generics
+            #where_clause
+            {
+                fn to_sim_value_with_type(
+                    &self,
+                    ty: #target #type_generics,
+                ) -> ::fayalite::sim::value::SimValue<#target #type_generics> {
+                    ::fayalite::sim::value::SimValue::from_value(ty, ::fayalite::__std::clone::Clone::clone(self))
+                }
+                fn into_sim_value_with_type(
+                    self,
+                    ty: #target #type_generics,
+                ) -> ::fayalite::sim::value::SimValue<#target #type_generics> {
+                    ::fayalite::sim::value::SimValue::from_value(ty, self)
+                }
+            }
         }
         .to_tokens(tokens);
         if let Some((cmp_eq,)) = cmp_eq {
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
index 0cdf85c..dd09a73 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
@@ -866,6 +866,24 @@ impl ToTokens for ParsedEnum {
                     ][..])
                 }
             }
+            #[automatically_derived]
+            impl #impl_generics ::fayalite::sim::value::ToSimValueWithType<#target #type_generics>
+            for #sim_value_ident #type_generics
+            #where_clause
+            {
+                fn to_sim_value_with_type(
+                    &self,
+                    ty: #target #type_generics,
+                ) -> ::fayalite::sim::value::SimValue<#target #type_generics> {
+                    ::fayalite::sim::value::SimValue::from_value(ty, ::fayalite::__std::clone::Clone::clone(self))
+                }
+                fn into_sim_value_with_type(
+                    self,
+                    ty: #target #type_generics,
+                ) -> ::fayalite::sim::value::SimValue<#target #type_generics> {
+                    ::fayalite::sim::value::SimValue::from_value(ty, self)
+                }
+            }
         }
         .to_tokens(tokens);
         if let (None, MaybeParsed::Parsed(generics)) = (no_static, &self.generics) {
@@ -921,6 +939,34 @@ impl ToTokens for ParsedEnum {
                     const MASK_TYPE_PROPERTIES: ::fayalite::ty::TypeProperties =
                         <::fayalite::int::Bool as ::fayalite::ty::StaticType>::TYPE_PROPERTIES;
                 }
+                #[automatically_derived]
+                impl #static_impl_generics ::fayalite::sim::value::ToSimValue
+                for #sim_value_ident #static_type_generics
+                #static_where_clause
+                {
+                    type Type = #target #static_type_generics;
+
+                    fn to_sim_value(
+                        &self,
+                    ) -> ::fayalite::sim::value::SimValue<
+                        <Self as ::fayalite::sim::value::ToSimValue>::Type,
+                    > {
+                        ::fayalite::sim::value::SimValue::from_value(
+                            ::fayalite::ty::StaticType::TYPE,
+                            ::fayalite::__std::clone::Clone::clone(self),
+                        )
+                    }
+                    fn into_sim_value(
+                        self,
+                    ) -> ::fayalite::sim::value::SimValue<
+                        <Self as ::fayalite::sim::value::ToSimValue>::Type,
+                    > {
+                        ::fayalite::sim::value::SimValue::from_value(
+                            ::fayalite::ty::StaticType::TYPE,
+                            self,
+                        )
+                    }
+                }
             }
             .to_tokens(tokens);
         }
diff --git a/crates/fayalite-proc-macros-impl/src/lib.rs b/crates/fayalite-proc-macros-impl/src/lib.rs
index 5fe3ae8..4f7c4f0 100644
--- a/crates/fayalite-proc-macros-impl/src/lib.rs
+++ b/crates/fayalite-proc-macros-impl/src/lib.rs
@@ -93,6 +93,7 @@ mod kw {
     custom_keyword!(output);
     custom_keyword!(reg_builder);
     custom_keyword!(reset);
+    custom_keyword!(sim);
     custom_keyword!(skip);
     custom_keyword!(target);
     custom_keyword!(wire);
diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
index c67f8dc..8f427a9 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
@@ -16,7 +16,7 @@ use std::{borrow::Borrow, convert::Infallible};
 use syn::{
     fold::{fold_expr, fold_expr_lit, fold_expr_unary, fold_local, fold_stmt, Fold},
     parenthesized,
-    parse::{Nothing, Parse, ParseStream},
+    parse::{Parse, ParseStream},
     parse_quote, parse_quote_spanned,
     spanned::Spanned,
     token::Paren,
@@ -27,6 +27,13 @@ use syn::{
 mod expand_aggregate_literals;
 mod expand_match;
 
+options! {
+    #[options = ExprOptions]
+    pub(crate) enum ExprOption {
+        Sim(sim),
+    }
+}
+
 options! {
     pub(crate) enum LetFnKind {
         Input(input),
@@ -952,7 +959,7 @@ with_debug_clone_and_fold! {
     #[allow(dead_code)]
     pub(crate) struct HdlLet<Kind = HdlLetKind> {
         pub(crate) attrs: Vec<Attribute>,
-        pub(crate) hdl_attr: HdlAttr<Nothing, kw::hdl>,
+        pub(crate) hdl_attr: HdlAttr<syn::parse::Nothing, kw::hdl>,
         pub(crate) let_token: Token![let],
         pub(crate) mut_token: Option<Token![mut]>,
         pub(crate) name: Ident,
@@ -1173,7 +1180,7 @@ impl Visitor<'_> {
             Some(_) => {}
         }
     }
-    fn process_hdl_if(&mut self, hdl_attr: HdlAttr<Nothing, kw::hdl>, expr_if: ExprIf) -> Expr {
+    fn process_hdl_if(&mut self, hdl_attr: HdlAttr<ExprOptions, kw::hdl>, expr_if: ExprIf) -> Expr {
         let ExprIf {
             attrs,
             if_token,
@@ -1181,10 +1188,10 @@ impl Visitor<'_> {
             then_branch,
             else_branch,
         } = expr_if;
-        self.require_normal_module_or_fn(if_token);
-        let else_expr = else_branch.unzip().1.map(|else_expr| match *else_expr {
-            Expr::If(expr_if) => self.process_hdl_if(hdl_attr.clone(), expr_if),
-            expr => expr,
+        let (else_token, else_expr) = else_branch.unzip();
+        let else_expr = else_expr.map(|else_expr| match *else_expr {
+            Expr::If(expr_if) => Box::new(self.process_hdl_if(hdl_attr.clone(), expr_if)),
+            _ => else_expr,
         });
         if let Expr::Let(ExprLet {
             attrs: let_attrs,
@@ -1206,7 +1213,19 @@ impl Visitor<'_> {
                 },
             );
         }
-        if let Some(else_expr) = else_expr {
+        let ExprOptions { sim } = hdl_attr.body;
+        if sim.is_some() {
+            ExprIf {
+                attrs,
+                if_token,
+                cond: parse_quote_spanned! {if_token.span=>
+                    *::fayalite::sim::value::SimValue::<::fayalite::int::Bool>::value(&::fayalite::sim::value::ToSimValue::into_sim_value(#cond))
+                },
+                then_branch,
+                else_branch: else_token.zip(else_expr),
+            }
+            .into()
+        } else if let Some(else_expr) = else_expr {
             parse_quote_spanned! {if_token.span=>
                 #(#attrs)*
                 {
@@ -1675,7 +1694,7 @@ impl Fold for Visitor<'_> {
     fn fold_local(&mut self, mut let_stmt: Local) -> Local {
         match self
             .errors
-            .ok(HdlAttr::<Nothing, kw::hdl>::parse_and_leave_attr(
+            .ok(HdlAttr::<ExprOptions, kw::hdl>::parse_and_leave_attr(
                 &let_stmt.attrs,
             )) {
             None => return empty_let(),
@@ -1694,10 +1713,11 @@ impl Fold for Visitor<'_> {
             subpat: None,
         }) = pat
         else {
-            let hdl_attr = HdlAttr::<Nothing, kw::hdl>::parse_and_take_attr(&mut let_stmt.attrs)
-                .ok()
-                .flatten()
-                .expect("already checked above");
+            let hdl_attr =
+                HdlAttr::<ExprOptions, kw::hdl>::parse_and_take_attr(&mut let_stmt.attrs)
+                    .ok()
+                    .flatten()
+                    .expect("already checked above");
             let let_stmt = fold_local(self, let_stmt);
             return self.process_hdl_let_pat(hdl_attr, let_stmt);
         };
diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs
index b5a0ad3..8892bd5 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs
@@ -1,45 +1,97 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-use crate::{kw, module::transform_body::Visitor, HdlAttr};
+use crate::{
+    kw,
+    module::transform_body::{ExprOptions, Visitor},
+    HdlAttr,
+};
 use quote::{format_ident, quote_spanned};
 use syn::{
-    parse::Nothing, parse_quote, parse_quote_spanned, spanned::Spanned, Expr, ExprArray, ExprPath,
-    ExprRepeat, ExprStruct, ExprTuple, FieldValue, TypePath,
+    parse_quote_spanned, spanned::Spanned, Expr, ExprArray, ExprPath, ExprRepeat, ExprStruct,
+    ExprTuple, FieldValue, TypePath,
 };
 
 impl Visitor<'_> {
     pub(crate) fn process_hdl_array(
         &mut self,
-        hdl_attr: HdlAttr<Nothing, kw::hdl>,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
         mut expr_array: ExprArray,
     ) -> Expr {
-        self.require_normal_module_or_fn(hdl_attr);
-        for elem in &mut expr_array.elems {
-            *elem = parse_quote_spanned! {elem.span()=>
-                ::fayalite::expr::ToExpr::to_expr(&(#elem))
-            };
+        let ExprOptions { sim } = hdl_attr.body;
+        let span = hdl_attr.kw.span;
+        if sim.is_some() {
+            for elem in &mut expr_array.elems {
+                *elem = parse_quote_spanned! {elem.span()=>
+                    ::fayalite::sim::value::ToSimValue::to_sim_value(&(#elem))
+                };
+            }
+            parse_quote_spanned! {span=>
+                ::fayalite::sim::value::ToSimValue::into_sim_value(#expr_array)
+            }
+        } else {
+            for elem in &mut expr_array.elems {
+                *elem = parse_quote_spanned! {elem.span()=>
+                    ::fayalite::expr::ToExpr::to_expr(&(#elem))
+                };
+            }
+            parse_quote_spanned! {span=>
+                ::fayalite::expr::ToExpr::to_expr(&#expr_array)
+            }
         }
-        parse_quote! {::fayalite::expr::ToExpr::to_expr(&#expr_array)}
     }
     pub(crate) fn process_hdl_repeat(
         &mut self,
-        hdl_attr: HdlAttr<Nothing, kw::hdl>,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
         mut expr_repeat: ExprRepeat,
     ) -> Expr {
-        self.require_normal_module_or_fn(hdl_attr);
         let repeated_value = &expr_repeat.expr;
-        *expr_repeat.expr = parse_quote_spanned! {repeated_value.span()=>
-            ::fayalite::expr::ToExpr::to_expr(&(#repeated_value))
-        };
-        parse_quote! {::fayalite::expr::ToExpr::to_expr(&#expr_repeat)}
+        let ExprOptions { sim } = hdl_attr.body;
+        let span = hdl_attr.kw.span;
+        if sim.is_some() {
+            *expr_repeat.expr = parse_quote_spanned! {repeated_value.span()=>
+                ::fayalite::sim::value::ToSimValue::to_sim_value(&(#repeated_value))
+            };
+            parse_quote_spanned! {span=>
+                ::fayalite::sim::value::ToSimValue::into_sim_value(#expr_repeat)
+            }
+        } else {
+            *expr_repeat.expr = parse_quote_spanned! {repeated_value.span()=>
+                ::fayalite::expr::ToExpr::to_expr(&(#repeated_value))
+            };
+            parse_quote_spanned! {span=>
+                ::fayalite::expr::ToExpr::to_expr(&#expr_repeat)
+            }
+        }
     }
     pub(crate) fn process_hdl_struct(
         &mut self,
-        hdl_attr: HdlAttr<Nothing, kw::hdl>,
-        expr_struct: ExprStruct,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
+        mut expr_struct: ExprStruct,
     ) -> Expr {
-        self.require_normal_module_or_fn(&hdl_attr);
         let name_span = expr_struct.path.segments.last().unwrap().ident.span();
+        let ExprOptions { sim } = hdl_attr.body;
+        if sim.is_some() {
+            let ty_path = TypePath {
+                qself: expr_struct.qself.take(),
+                path: expr_struct.path,
+            };
+            expr_struct.path = parse_quote_spanned! {name_span=>
+                __SimValue::<#ty_path>
+            };
+            for field in &mut expr_struct.fields {
+                let expr = &field.expr;
+                field.expr = parse_quote_spanned! {field.member.span()=>
+                    ::fayalite::sim::value::ToSimValue::to_sim_value(&(#expr))
+                };
+            }
+            return parse_quote_spanned! {name_span=>
+                {
+                    type __SimValue<T> = <T as ::fayalite::ty::Type>::SimValue;
+                    let value: ::fayalite::sim::value::SimValue<#ty_path> = ::fayalite::sim::value::ToSimValue::into_sim_value(#expr_struct);
+                    value
+                }
+            };
+        }
         let builder_ident = format_ident!("__builder", span = name_span);
         let empty_builder = if expr_struct.qself.is_some()
             || expr_struct
@@ -91,12 +143,23 @@ impl Visitor<'_> {
     }
     pub(crate) fn process_hdl_tuple(
         &mut self,
-        hdl_attr: HdlAttr<Nothing, kw::hdl>,
-        expr_tuple: ExprTuple,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
+        mut expr_tuple: ExprTuple,
     ) -> Expr {
-        self.require_normal_module_or_fn(hdl_attr);
-        parse_quote_spanned! {expr_tuple.span()=>
-            ::fayalite::expr::ToExpr::to_expr(&#expr_tuple)
+        let ExprOptions { sim } = hdl_attr.body;
+        if sim.is_some() {
+            for element in &mut expr_tuple.elems {
+                *element = parse_quote_spanned! {element.span()=>
+                    &(#element)
+                };
+            }
+            parse_quote_spanned! {expr_tuple.span()=>
+                ::fayalite::sim::value::ToSimValue::into_sim_value(#expr_tuple)
+            }
+        } else {
+            parse_quote_spanned! {expr_tuple.span()=>
+                ::fayalite::expr::ToExpr::to_expr(&#expr_tuple)
+            }
         }
     }
 }
diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
index f1ff2c2..57e919a 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
@@ -3,7 +3,9 @@
 use crate::{
     fold::{impl_fold, DoFold},
     kw,
-    module::transform_body::{empty_let, with_debug_clone_and_fold, wrap_ty_with_expr, Visitor},
+    module::transform_body::{
+        empty_let, with_debug_clone_and_fold, wrap_ty_with_expr, ExprOptions, Visitor,
+    },
     Errors, HdlAttr, PairsIterExt,
 };
 use proc_macro2::{Span, TokenStream};
@@ -11,7 +13,6 @@ use quote::{format_ident, quote_spanned, ToTokens, TokenStreamExt};
 use std::collections::BTreeSet;
 use syn::{
     fold::{fold_arm, fold_expr_match, fold_local, fold_pat, Fold},
-    parse::Nothing,
     parse_quote_spanned,
     punctuated::Punctuated,
     spanned::Spanned,
@@ -981,7 +982,7 @@ impl<'a> VisitMatchPat<'a> for HdlLetPatVisitState<'a> {
 impl Visitor<'_> {
     pub(crate) fn process_hdl_let_pat(
         &mut self,
-        _hdl_attr: HdlAttr<Nothing, kw::hdl>,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
         mut let_stmt: Local,
     ) -> Local {
         let span = let_stmt.let_token.span();
@@ -996,7 +997,6 @@ impl Visitor<'_> {
             init,
             semi_token,
         } = let_stmt;
-        self.require_normal_module_or_fn(let_token);
         let Some(syn::LocalInit {
             eq_token,
             expr,
@@ -1031,29 +1031,48 @@ impl Visitor<'_> {
             errors: _,
             bindings,
         } = state;
-        let retval = parse_quote_spanned! {span=>
-            let (#(#bindings,)* __scope,) = {
-                type __MatchTy<T> = <T as ::fayalite::ty::Type>::MatchVariant;
-                let __match_expr = ::fayalite::expr::ToExpr::to_expr(&(#expr));
-                ::fayalite::expr::check_match_expr(__match_expr, |__match_value, __infallible| {
-                    #[allow(unused_variables)]
-                    #check_let_stmt
-                    match __infallible {}
-                });
-                let mut __match_iter = ::fayalite::module::match_(__match_expr);
-                let ::fayalite::__std::option::Option::Some(__match_variant) = ::fayalite::__std::iter::Iterator::next(&mut __match_iter) else {
-                    ::fayalite::__std::unreachable!("#[hdl] let with uninhabited type");
+        let ExprOptions { sim } = hdl_attr.body;
+        let retval = if sim.is_some() {
+            parse_quote_spanned! {span=>
+                let (#(#bindings,)*) = {
+                    type __MatchTy<T> = <T as ::fayalite::ty::Type>::SimValue;
+                    let __match_value = ::fayalite::sim::value::ToSimValue::to_sim_value(&(#expr));
+                    #let_token #pat #eq_token ::fayalite::sim::value::SimValue::into_value(__match_value) #semi_token
+                    (#(#bindings,)*)
                 };
-                let ::fayalite::__std::option::Option::None = ::fayalite::__std::iter::Iterator::next(&mut __match_iter) else {
-                    ::fayalite::__std::unreachable!("#[hdl] let with refutable pattern");
-                };
-                let (__match_variant, __scope) =
-                    ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
-                        __match_variant,
+            }
+        } else {
+            parse_quote_spanned! {span=>
+                let (#(#bindings,)* __scope,) = {
+                    type __MatchTy<T> = <T as ::fayalite::ty::Type>::MatchVariant;
+                    let __match_expr = ::fayalite::expr::ToExpr::to_expr(&(#expr));
+                    ::fayalite::expr::check_match_expr(
+                        __match_expr,
+                        |__match_value, __infallible| {
+                            #[allow(unused_variables)]
+                            #check_let_stmt
+                            match __infallible {}
+                        },
                     );
-                #let_token #pat #eq_token __match_variant #semi_token
-                (#(#bindings,)* __scope,)
-            };
+                    let mut __match_iter = ::fayalite::module::match_(__match_expr);
+                    let ::fayalite::__std::option::Option::Some(__match_variant) =
+                        ::fayalite::__std::iter::Iterator::next(&mut __match_iter)
+                    else {
+                        ::fayalite::__std::unreachable!("#[hdl] let with uninhabited type");
+                    };
+                    let ::fayalite::__std::option::Option::None =
+                        ::fayalite::__std::iter::Iterator::next(&mut __match_iter)
+                    else {
+                        ::fayalite::__std::unreachable!("#[hdl] let with refutable pattern");
+                    };
+                    let (__match_variant, __scope) =
+                        ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
+                            __match_variant,
+                        );
+                    #let_token #pat #eq_token __match_variant #semi_token
+                    (#(#bindings,)* __scope,)
+                };
+            }
         };
         match retval {
             syn::Stmt::Local(retval) => retval,
@@ -1062,7 +1081,7 @@ impl Visitor<'_> {
     }
     pub(crate) fn process_hdl_match(
         &mut self,
-        _hdl_attr: HdlAttr<Nothing, kw::hdl>,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
         expr_match: ExprMatch,
     ) -> Expr {
         let span = expr_match.match_token.span();
@@ -1074,7 +1093,6 @@ impl Visitor<'_> {
             brace_token: _,
             arms,
         } = expr_match;
-        self.require_normal_module_or_fn(match_token);
         let mut state = HdlMatchParseState {
             match_span: span,
             errors: &mut self.errors,
@@ -1083,24 +1101,37 @@ impl Visitor<'_> {
             arms.into_iter()
                 .filter_map(|arm| MatchArm::parse(&mut state, arm).ok()),
         );
-        let expr = quote_spanned! {span=>
-            {
-                type __MatchTy<T> = <T as ::fayalite::ty::Type>::MatchVariant;
-                let __match_expr = ::fayalite::expr::ToExpr::to_expr(&(#expr));
-                ::fayalite::expr::check_match_expr(__match_expr, |__match_value, __infallible| {
-                    #[allow(unused_variables)]
-                    #check_match
-                });
-                for __match_variant in ::fayalite::module::match_(__match_expr) {
-                    let (__match_variant, __scope) =
-                        ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
-                            __match_variant,
-                        );
-                    #match_token __match_variant {
+        let ExprOptions { sim } = hdl_attr.body;
+        let expr = if sim.is_some() {
+            quote_spanned! {span=>
+                {
+                    type __MatchTy<T> = <T as ::fayalite::ty::Type>::SimValue;
+                    let __match_expr = ::fayalite::sim::value::ToSimValue::to_sim_value(&(#expr));
+                    #match_token *__match_expr {
                         #(#arms)*
                     }
                 }
             }
+        } else {
+            quote_spanned! {span=>
+                {
+                    type __MatchTy<T> = <T as ::fayalite::ty::Type>::MatchVariant;
+                    let __match_expr = ::fayalite::expr::ToExpr::to_expr(&(#expr));
+                    ::fayalite::expr::check_match_expr(__match_expr, |__match_value, __infallible| {
+                        #[allow(unused_variables)]
+                        #check_match
+                    });
+                    for __match_variant in ::fayalite::module::match_(__match_expr) {
+                        let (__match_variant, __scope) =
+                            ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope(
+                                __match_variant,
+                            );
+                        #match_token __match_variant {
+                            #(#arms)*
+                        }
+                    }
+                }
+            }
         };
         syn::parse2(expr).unwrap()
     }
diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs
index 06e0411..9279b57 100644
--- a/crates/fayalite/src/bundle.rs
+++ b/crates/fayalite/src/bundle.rs
@@ -8,7 +8,7 @@ use crate::{
     },
     int::{Bool, DynSize},
     intern::{Intern, Interned},
-    sim::value::{SimValue, SimValuePartialEq, ToSimValue},
+    sim::value::{SimValue, SimValuePartialEq, ToSimValue, ToSimValueWithType},
     source_location::SourceLocation,
     ty::{
         impl_match_variant_as_self, CanonicalType, MatchVariantWithoutScope, OpaqueSimValue,
@@ -562,29 +562,29 @@ macro_rules! impl_tuples {
                 BundleLiteral::new(ty, field_values[..].intern()).to_expr()
             }
         }
-        impl<$($T: ToSimValue<CanonicalType>,)*> ToSimValue<CanonicalType> for ($($T,)*) {
+        impl<$($T: ToSimValueWithType<CanonicalType>,)*> ToSimValueWithType<CanonicalType> for ($($T,)*) {
             #[track_caller]
-            fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-                SimValue::into_canonical(ToSimValue::<Bundle>::to_sim_value(self, Bundle::from_canonical(ty)))
+            fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+                SimValue::into_canonical(ToSimValueWithType::<Bundle>::to_sim_value_with_type(self, Bundle::from_canonical(ty)))
             }
             #[track_caller]
-            fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType>
+            fn into_sim_value_with_type(self, ty: CanonicalType) -> SimValue<CanonicalType>
             {
-                SimValue::into_canonical(ToSimValue::<Bundle>::into_sim_value(self, Bundle::from_canonical(ty)))
+                SimValue::into_canonical(ToSimValueWithType::<Bundle>::into_sim_value_with_type(self, Bundle::from_canonical(ty)))
             }
         }
-        impl<$($T: ToSimValue<CanonicalType>,)*> ToSimValue<Bundle> for ($($T,)*) {
+        impl<$($T: ToSimValueWithType<CanonicalType>,)*> ToSimValueWithType<Bundle> for ($($T,)*) {
             #[track_caller]
-            fn to_sim_value(&self, ty: Bundle) -> SimValue<Bundle> {
+            fn to_sim_value_with_type(&self, ty: Bundle) -> SimValue<Bundle> {
                 let ($($var,)*) = self;
                 let [$($ty_var,)*] = *ty.fields() else {
                     panic!("bundle has wrong number of fields");
                 };
-                $(let $var = $var.to_sim_value($ty_var.ty);)*
-                ToSimValue::into_sim_value(($($var,)*), ty)
+                $(let $var = $var.to_sim_value_with_type($ty_var.ty);)*
+                ToSimValueWithType::into_sim_value_with_type(($($var,)*), ty)
             }
             #[track_caller]
-            fn into_sim_value(self, ty: Bundle) -> SimValue<Bundle> {
+            fn into_sim_value_with_type(self, ty: Bundle) -> SimValue<Bundle> {
                 #![allow(unused_mut)]
                 #![allow(clippy::unused_unit)]
                 let ($($var,)*) = self;
@@ -592,29 +592,44 @@ macro_rules! impl_tuples {
                     panic!("bundle has wrong number of fields");
                 };
                 let mut bits = BitVec::new();
-                $(let $var = $var.into_sim_value($ty_var.ty);
+                $(let $var = $var.into_sim_value_with_type($ty_var.ty);
                 assert_eq!(SimValue::ty(&$var), $ty_var.ty);
                 bits.extend_from_bitslice(SimValue::bits(&$var).bits());
                 )*
-                bits.into_sim_value(ty)
+                bits.into_sim_value_with_type(ty)
             }
         }
-        impl<$($T: ToSimValue<$Ty>, $Ty: Type,)*> ToSimValue<($($Ty,)*)> for ($($T,)*) {
+        impl<$($T: ToSimValueWithType<$Ty>, $Ty: Type,)*> ToSimValueWithType<($($Ty,)*)> for ($($T,)*) {
             #[track_caller]
-            fn to_sim_value(&self, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
+            fn to_sim_value_with_type(&self, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
                 let ($($var,)*) = self;
                 let ($($ty_var,)*) = ty;
-                $(let $var = $var.to_sim_value($ty_var);)*
+                $(let $var = $var.to_sim_value_with_type($ty_var);)*
                 SimValue::from_value(ty, ($($var,)*))
             }
             #[track_caller]
-            fn into_sim_value(self, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
+            fn into_sim_value_with_type(self, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
                 let ($($var,)*) = self;
                 let ($($ty_var,)*) = ty;
-                $(let $var = $var.into_sim_value($ty_var);)*
+                $(let $var = $var.into_sim_value_with_type($ty_var);)*
                 SimValue::from_value(ty, ($($var,)*))
             }
         }
+        impl<$($T: ToSimValue,)*> ToSimValue for ($($T,)*) {
+            type Type = ($($T::Type,)*);
+            #[track_caller]
+            fn to_sim_value(&self) -> SimValue<Self::Type> {
+                let ($($var,)*) = self;
+                $(let $var = $var.to_sim_value();)*
+                SimValue::from_value(($(SimValue::ty(&$var),)*), ($($var,)*))
+            }
+            #[track_caller]
+            fn into_sim_value(self) -> SimValue<Self::Type> {
+                let ($($var,)*) = self;
+                $(let $var = $var.to_sim_value();)*
+                SimValue::from_value(($(SimValue::ty(&$var),)*), ($($var,)*))
+            }
+        }
         impl<$($Lhs: Type + ExprPartialEq<$Rhs>, $Rhs: Type,)*> ExprPartialEq<($($Rhs,)*)> for ($($Lhs,)*) {
             fn cmp_eq(lhs: Expr<Self>, rhs: Expr<($($Rhs,)*)>) -> Expr<Bool> {
                 let ($($lhs_var,)*) = *lhs;
@@ -674,7 +689,7 @@ impl_tuples! {
 impl<T: ?Sized + Send + Sync + 'static> Type for PhantomData<T> {
     type BaseType = Bundle;
     type MaskType = ();
-    type SimValue = ();
+    type SimValue = PhantomData<T>;
     type MatchVariant = PhantomData<T>;
     type MatchActiveScope = ();
     type MatchVariantAndInactiveScope = MatchVariantWithoutScope<Self::MatchVariant>;
@@ -709,7 +724,7 @@ impl<T: ?Sized + Send + Sync + 'static> Type for PhantomData<T> {
     }
     fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
         assert!(bits.is_empty());
-        ()
+        *self
     }
     fn sim_value_clone_from_bits(&self, _value: &mut Self::SimValue, bits: &BitSlice) {
         assert!(bits.is_empty());
@@ -764,26 +779,38 @@ impl<T: ?Sized + Send + Sync + 'static> ToExpr for PhantomData<T> {
     }
 }
 
-impl<T: ?Sized + Send + Sync + 'static> ToSimValue<Self> for PhantomData<T> {
+impl<T: ?Sized + Send + Sync + 'static> ToSimValue for PhantomData<T> {
+    type Type = PhantomData<T>;
+
     #[track_caller]
-    fn to_sim_value(&self, ty: Self) -> SimValue<Self> {
-        ToSimValue::into_sim_value(BitVec::new(), ty)
+    fn to_sim_value(&self) -> SimValue<Self> {
+        SimValue::from_value(*self, *self)
     }
 }
 
-impl<T: ?Sized> ToSimValue<Bundle> for PhantomData<T> {
+impl<T: ?Sized + Send + Sync + 'static> ToSimValueWithType<Self> for PhantomData<T> {
     #[track_caller]
-    fn to_sim_value(&self, ty: Bundle) -> SimValue<Bundle> {
+    fn to_sim_value_with_type(&self, ty: Self) -> SimValue<Self> {
+        SimValue::from_value(ty, *self)
+    }
+}
+
+impl<T: ?Sized> ToSimValueWithType<Bundle> for PhantomData<T> {
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: Bundle) -> SimValue<Bundle> {
         assert!(ty.fields().is_empty());
-        ToSimValue::into_sim_value(BitVec::new(), ty)
+        ToSimValueWithType::into_sim_value_with_type(BitVec::new(), ty)
     }
 }
 
-impl<T: ?Sized> ToSimValue<CanonicalType> for PhantomData<T> {
+impl<T: ?Sized> ToSimValueWithType<CanonicalType> for PhantomData<T> {
     #[track_caller]
-    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+    fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
         let ty = Bundle::from_canonical(ty);
         assert!(ty.fields().is_empty());
-        SimValue::into_canonical(ToSimValue::into_sim_value(BitVec::new(), ty))
+        SimValue::into_canonical(ToSimValueWithType::into_sim_value_with_type(
+            BitVec::new(),
+            ty,
+        ))
     }
 }
diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index a956dd5..373e150 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -2,12 +2,13 @@
 // See Notices.txt for copyright information
 
 use crate::{
+    array::ArrayType,
     expr::{
         target::{GetTarget, Target},
         Expr, NotALiteralExpr, ToExpr, ToLiteralBits,
     },
     intern::{Intern, Interned, Memoize},
-    sim::value::SimValue,
+    sim::value::{SimValue, ToSimValueWithType},
     source_location::SourceLocation,
     ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
     util::{interned_bit, ConstBool, ConstUsize, GenericConstBool, GenericConstUsize},
@@ -58,7 +59,8 @@ pub trait KnownSize:
         + std::fmt::Debug
         + IntoIterator<Item = SimValue<Element>>
         + TryFrom<Vec<SimValue<Element>>>
-        + Into<Vec<SimValue<Element>>>;
+        + Into<Vec<SimValue<Element>>>
+        + ToSimValueWithType<ArrayType<Element, Self>>;
 }
 
 macro_rules! known_widths {
@@ -120,7 +122,8 @@ pub trait Size:
         + std::fmt::Debug
         + IntoIterator<Item = SimValue<Element>>
         + TryFrom<Vec<SimValue<Element>>>
-        + Into<Vec<SimValue<Element>>>;
+        + Into<Vec<SimValue<Element>>>
+        + ToSimValueWithType<ArrayType<Element, Self>>;
     const KNOWN_VALUE: Option<usize>;
     type SizeType: SizeType<Size = Self>
         + Copy
diff --git a/crates/fayalite/src/phantom_const.rs b/crates/fayalite/src/phantom_const.rs
index 27bb04e..8422ae0 100644
--- a/crates/fayalite/src/phantom_const.rs
+++ b/crates/fayalite/src/phantom_const.rs
@@ -11,7 +11,7 @@ use crate::{
     },
     int::Bool,
     intern::{Intern, Interned, InternedCompare, LazyInterned, Memoize},
-    sim::value::{SimValue, SimValuePartialEq},
+    sim::value::{SimValue, SimValuePartialEq, ToSimValue, ToSimValueWithType},
     source_location::SourceLocation,
     ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
 };
@@ -248,7 +248,7 @@ impl<T: ?Sized + PhantomConstValue> PhantomConst<T> {
 impl<T: ?Sized + PhantomConstValue> Type for PhantomConst<T> {
     type BaseType = PhantomConst;
     type MaskType = ();
-    type SimValue = ();
+    type SimValue = PhantomConst<T>;
     impl_match_variant_as_self!();
 
     fn mask_type(&self) -> Self::MaskType {
@@ -272,15 +272,17 @@ impl<T: ?Sized + PhantomConstValue> Type for PhantomConst<T> {
 
     fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
         assert!(bits.is_empty());
-        ()
+        *self
     }
 
-    fn sim_value_clone_from_bits(&self, _value: &mut Self::SimValue, bits: &BitSlice) {
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
         assert!(bits.is_empty());
+        assert_eq!(*value, *self);
     }
 
-    fn sim_value_to_bits(&self, _value: &Self::SimValue, bits: &mut BitSlice) {
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
         assert!(bits.is_empty());
+        assert_eq!(*value, *self);
     }
 }
 
@@ -334,3 +336,23 @@ impl<T: ?Sized + PhantomConstValue> SimValuePartialEq<Self> for PhantomConst<T>
         true
     }
 }
+
+impl<T: ?Sized + PhantomConstValue> ToSimValue for PhantomConst<T> {
+    type Type = PhantomConst<T>;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        SimValue::from_value(*self, *self)
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> ToSimValueWithType<PhantomConst<T>> for PhantomConst<T> {
+    fn to_sim_value_with_type(&self, ty: PhantomConst<T>) -> SimValue<PhantomConst<T>> {
+        SimValue::from_value(ty, *self)
+    }
+}
+
+impl<T: ?Sized + PhantomConstValue> ToSimValueWithType<CanonicalType> for PhantomConst<T> {
+    fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_value(Self::from_canonical(ty), *self))
+    }
+}
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 9be4889..563cd37 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -7531,10 +7531,10 @@ macro_rules! impl_simulation_methods {
             SimValue::from_canonical($self.settle_if_needed(retval)$(.$await)?)
         }
         $(#[$track_caller])?
-        pub $($async)? fn write<IO: Type, V: value::ToSimValue<IO>>(&mut $self, io: Expr<IO>, value: V) {
+        pub $($async)? fn write<IO: Type, V: value::ToSimValueWithType<IO>>(&mut $self, io: Expr<IO>, value: V) {
             $self.sim_impl.borrow_mut().write(
                 Expr::canonical(io),
-                &SimValue::into_canonical(value.into_sim_value(Expr::ty(io))),
+                &SimValue::into_canonical(value.into_sim_value_with_type(Expr::ty(io))),
                 $which_module,
             );
         }
diff --git a/crates/fayalite/src/sim/value.rs b/crates/fayalite/src/sim/value.rs
index 3e45016..d415af4 100644
--- a/crates/fayalite/src/sim/value.rs
+++ b/crates/fayalite/src/sim/value.rs
@@ -9,7 +9,7 @@ use crate::{
     expr::{CastBitsTo, Expr, ToExpr},
     int::{Bool, IntType, KnownSize, SInt, SIntType, SIntValue, Size, UInt, UIntType, UIntValue},
     reset::{AsyncReset, Reset, SyncReset},
-    ty::{CanonicalType, Type},
+    ty::{CanonicalType, StaticType, Type},
     util::{
         alternating_cell::{AlternatingCell, AlternatingCellMethods},
         ConstUsize,
@@ -307,122 +307,223 @@ impl SimValuePartialEq<Bool> for Bool {
     }
 }
 
-pub trait ToSimValue<T: Type> {
+pub trait ToSimValue: ToSimValueWithType<<Self as ToSimValue>::Type> {
+    type Type: Type;
+
     #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T>;
+    fn to_sim_value(&self) -> SimValue<Self::Type>;
     #[track_caller]
-    fn into_sim_value(self, ty: T) -> SimValue<T>
+    fn into_sim_value(self) -> SimValue<Self::Type>
     where
         Self: Sized,
     {
-        self.to_sim_value(ty)
+        self.to_sim_value()
     }
     #[track_caller]
-    fn arc_into_sim_value(self: Arc<Self>, ty: T) -> SimValue<T> {
-        self.to_sim_value(ty)
+    fn arc_into_sim_value(self: Arc<Self>) -> SimValue<Self::Type> {
+        self.to_sim_value()
     }
     #[track_caller]
-    fn arc_to_sim_value(self: &Arc<Self>, ty: T) -> SimValue<T> {
-        self.to_sim_value(ty)
+    fn arc_to_sim_value(self: &Arc<Self>) -> SimValue<Self::Type> {
+        self.to_sim_value()
     }
 }
 
-impl<T: Type> ToSimValue<T> for SimValue<T> {
+pub trait ToSimValueWithType<T: Type> {
     #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        assert_eq!(SimValue::ty(self), ty);
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T>;
+    #[track_caller]
+    fn into_sim_value_with_type(self, ty: T) -> SimValue<T>
+    where
+        Self: Sized,
+    {
+        self.to_sim_value_with_type(ty)
+    }
+    #[track_caller]
+    fn arc_into_sim_value_with_type(self: Arc<Self>, ty: T) -> SimValue<T> {
+        self.to_sim_value_with_type(ty)
+    }
+    #[track_caller]
+    fn arc_to_sim_value_with_type(self: &Arc<Self>, ty: T) -> SimValue<T> {
+        self.to_sim_value_with_type(ty)
+    }
+}
+
+macro_rules! forward_to_sim_value_with_type {
+    ([$($generics:tt)*] $ty:ty) => {
+        impl<$($generics)*> ToSimValueWithType<<Self as ToSimValue>::Type> for $ty {
+            fn to_sim_value_with_type(&self, ty: <Self as ToSimValue>::Type) -> SimValue<<Self as ToSimValue>::Type> {
+                let retval = Self::to_sim_value(self);
+                assert_eq!(SimValue::ty(&retval), ty);
+                retval
+            }
+            #[track_caller]
+            fn into_sim_value_with_type(self, ty: <Self as ToSimValue>::Type) -> SimValue<<Self as ToSimValue>::Type>
+            where
+                Self: Sized,
+            {
+                let retval = Self::into_sim_value(self);
+                assert_eq!(SimValue::ty(&retval), ty);
+                retval
+            }
+            #[track_caller]
+            fn arc_into_sim_value_with_type(self: Arc<Self>, ty: <Self as ToSimValue>::Type) -> SimValue<<Self as ToSimValue>::Type> {
+                let retval = Self::arc_into_sim_value(self);
+                assert_eq!(SimValue::ty(&retval), ty);
+                retval
+            }
+            #[track_caller]
+            fn arc_to_sim_value_with_type(self: &Arc<Self>, ty: <Self as ToSimValue>::Type) -> SimValue<<Self as ToSimValue>::Type> {
+                let retval = Self::arc_to_sim_value(self);
+                assert_eq!(SimValue::ty(&retval), ty);
+                retval
+            }
+        }
+    };
+}
+
+impl<T: Type> ToSimValue for SimValue<T> {
+    type Type = T;
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
         self.clone()
     }
 
-    #[track_caller]
-    fn into_sim_value(self, ty: T) -> SimValue<T> {
-        assert_eq!(SimValue::ty(&self), ty);
+    fn into_sim_value(self) -> SimValue<Self::Type> {
         self
     }
 }
 
-impl<T: Type> ToSimValue<T> for BitVec {
+forward_to_sim_value_with_type!([T: Type] SimValue<T>);
+
+impl<T: Type> ToSimValueWithType<T> for BitVec {
     #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        self.clone().into_sim_value(ty)
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        self.clone().into_sim_value_with_type(ty)
     }
 
     #[track_caller]
-    fn into_sim_value(self, ty: T) -> SimValue<T> {
-        Arc::new(self).arc_into_sim_value(ty)
+    fn into_sim_value_with_type(self, ty: T) -> SimValue<T> {
+        Arc::new(self).arc_into_sim_value_with_type(ty)
     }
 
     #[track_caller]
-    fn arc_into_sim_value(self: Arc<Self>, ty: T) -> SimValue<T> {
+    fn arc_into_sim_value_with_type(self: Arc<Self>, ty: T) -> SimValue<T> {
         SimValue::from_bits(ty, UIntValue::new_dyn(self))
     }
 
     #[track_caller]
-    fn arc_to_sim_value(self: &Arc<Self>, ty: T) -> SimValue<T> {
+    fn arc_to_sim_value_with_type(self: &Arc<Self>, ty: T) -> SimValue<T> {
         SimValue::from_bits(ty, UIntValue::new_dyn(self.clone()))
     }
 }
 
-impl<T: Type> ToSimValue<T> for bitvec::boxed::BitBox {
+impl<T: Type> ToSimValueWithType<T> for bitvec::boxed::BitBox {
     #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        self.clone().into_sim_value(ty)
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        self.clone().into_sim_value_with_type(ty)
     }
 
     #[track_caller]
-    fn into_sim_value(self, ty: T) -> SimValue<T> {
-        self.into_bitvec().into_sim_value(ty)
+    fn into_sim_value_with_type(self, ty: T) -> SimValue<T> {
+        self.into_bitvec().into_sim_value_with_type(ty)
     }
 }
 
-impl<T: Type> ToSimValue<T> for BitSlice {
+impl<T: Type> ToSimValueWithType<T> for BitSlice {
     #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        self.to_bitvec().into_sim_value(ty)
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        self.to_bitvec().into_sim_value_with_type(ty)
     }
 }
 
-impl<This: ?Sized + ToSimValue<T>, T: Type> ToSimValue<T> for &'_ This {
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        This::to_sim_value(self, ty)
+impl<This: ?Sized + ToSimValue> ToSimValue for &'_ This {
+    type Type = This::Type;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        This::to_sim_value(self)
     }
 }
 
-impl<This: ?Sized + ToSimValue<T>, T: Type> ToSimValue<T> for &'_ mut This {
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        This::to_sim_value(self, ty)
+impl<This: ?Sized + ToSimValueWithType<T>, T: Type> ToSimValueWithType<T> for &'_ This {
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value_with_type(self, ty)
     }
 }
 
-impl<This: ?Sized + ToSimValue<T>, T: Type> ToSimValue<T> for Arc<This> {
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        This::arc_to_sim_value(self, ty)
-    }
-    fn into_sim_value(self, ty: T) -> SimValue<T> {
-        This::arc_into_sim_value(self, ty)
+impl<This: ?Sized + ToSimValue> ToSimValue for &'_ mut This {
+    type Type = This::Type;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        This::to_sim_value(self)
     }
 }
 
-impl<This: ?Sized + ToSimValue<T> + Send + Sync + 'static, T: Type> ToSimValue<T>
+impl<This: ?Sized + ToSimValueWithType<T>, T: Type> ToSimValueWithType<T> for &'_ mut This {
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value_with_type(self, ty)
+    }
+}
+
+impl<This: ?Sized + ToSimValue> ToSimValue for Arc<This> {
+    type Type = This::Type;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        This::arc_to_sim_value(self)
+    }
+    fn into_sim_value(self) -> SimValue<Self::Type> {
+        This::arc_into_sim_value(self)
+    }
+}
+
+impl<This: ?Sized + ToSimValueWithType<T>, T: Type> ToSimValueWithType<T> for Arc<This> {
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        This::arc_to_sim_value_with_type(self, ty)
+    }
+    fn into_sim_value_with_type(self, ty: T) -> SimValue<T> {
+        This::arc_into_sim_value_with_type(self, ty)
+    }
+}
+
+impl<This: ?Sized + ToSimValue + Send + Sync + 'static> ToSimValue
     for crate::intern::Interned<This>
 {
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        This::to_sim_value(self, ty)
+    type Type = This::Type;
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        This::to_sim_value(self)
     }
 }
 
-impl<This: ToSimValue<T>, T: Type> ToSimValue<T> for Box<This> {
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        This::to_sim_value(self, ty)
+impl<This: ?Sized + ToSimValueWithType<T> + Send + Sync + 'static, T: Type> ToSimValueWithType<T>
+    for crate::intern::Interned<This>
+{
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value_with_type(self, ty)
     }
-    fn into_sim_value(self, ty: T) -> SimValue<T> {
-        This::into_sim_value(*self, ty)
+}
+
+impl<This: ToSimValue> ToSimValue for Box<This> {
+    type Type = This::Type;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        This::to_sim_value(self)
+    }
+    fn into_sim_value(self) -> SimValue<Self::Type> {
+        This::into_sim_value(*self)
+    }
+}
+
+impl<This: ToSimValueWithType<T>, T: Type> ToSimValueWithType<T> for Box<This> {
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        This::to_sim_value_with_type(self, ty)
+    }
+    fn into_sim_value_with_type(self, ty: T) -> SimValue<T> {
+        This::into_sim_value_with_type(*self, ty)
     }
 }
 
 impl<T: Type, Len: Size> SimValue<ArrayType<T, Len>> {
     #[track_caller]
-    pub fn from_array_elements<I: IntoIterator<Item: ToSimValue<T>>>(
+    pub fn from_array_elements<I: IntoIterator<Item: ToSimValueWithType<T>>>(
         ty: ArrayType<T, Len>,
         elements: I,
     ) -> Self {
@@ -430,23 +531,32 @@ impl<T: Type, Len: Size> SimValue<ArrayType<T, Len>> {
         let elements = Vec::from_iter(
             elements
                 .into_iter()
-                .map(|element| element.into_sim_value(element_ty)),
+                .map(|element| element.into_sim_value_with_type(element_ty)),
         );
         assert_eq!(elements.len(), ty.len());
         SimValue::from_value(ty, elements.try_into().ok().expect("already checked len"))
     }
 }
 
-impl<Element: ToSimValue<T>, T: Type> ToSimValue<Array<T>> for [Element] {
+impl<Element: ToSimValueWithType<T>, T: Type> ToSimValueWithType<Array<T>> for [Element] {
     #[track_caller]
-    fn to_sim_value(&self, ty: Array<T>) -> SimValue<Array<T>> {
+    fn to_sim_value_with_type(&self, ty: Array<T>) -> SimValue<Array<T>> {
         SimValue::from_array_elements(ty, self)
     }
 }
 
-impl<Element: ToSimValue<CanonicalType>> ToSimValue<CanonicalType> for [Element] {
+impl<Element: ToSimValue<Type: StaticType>> ToSimValue for [Element] {
+    type Type = Array<Element::Type>;
+
     #[track_caller]
-    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        SimValue::from_array_elements(ArrayType::new_dyn(StaticType::TYPE, self.len()), self)
+    }
+}
+
+impl<Element: ToSimValueWithType<CanonicalType>> ToSimValueWithType<CanonicalType> for [Element] {
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
         SimValue::into_canonical(SimValue::from_array_elements(
             <Array>::from_canonical(ty),
             self,
@@ -454,71 +564,61 @@ impl<Element: ToSimValue<CanonicalType>> ToSimValue<CanonicalType> for [Element]
     }
 }
 
-impl<Element: ToSimValue<T>, T: Type, const N: usize> ToSimValue<Array<T, N>> for [Element; N]
+impl<Element: ToSimValueWithType<T>, T: Type, const N: usize> ToSimValueWithType<Array<T, N>>
+    for [Element; N]
 where
     ConstUsize<N>: KnownSize,
 {
     #[track_caller]
-    fn to_sim_value(&self, ty: Array<T, N>) -> SimValue<Array<T, N>> {
+    fn to_sim_value_with_type(&self, ty: Array<T, N>) -> SimValue<Array<T, N>> {
         SimValue::from_array_elements(ty, self)
     }
     #[track_caller]
-    fn into_sim_value(self, ty: Array<T, N>) -> SimValue<Array<T, N>> {
+    fn into_sim_value_with_type(self, ty: Array<T, N>) -> SimValue<Array<T, N>> {
         SimValue::from_array_elements(ty, self)
     }
 }
 
-impl<Element: ToSimValue<T>, T: Type, const N: usize> ToSimValue<Array<T>> for [Element; N] {
-    #[track_caller]
-    fn to_sim_value(&self, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(ty, self)
+impl<Element: ToSimValue<Type: StaticType>, const N: usize> ToSimValue for [Element; N]
+where
+    ConstUsize<N>: KnownSize,
+{
+    type Type = Array<Element::Type, N>;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        SimValue::from_array_elements(StaticType::TYPE, self)
     }
-    #[track_caller]
-    fn into_sim_value(self, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(ty, self)
+
+    fn into_sim_value(self) -> SimValue<Self::Type> {
+        SimValue::from_array_elements(StaticType::TYPE, self)
     }
 }
 
-impl<Element: ToSimValue<CanonicalType>, const N: usize> ToSimValue<CanonicalType>
+impl<Element: ToSimValueWithType<T>, T: Type, const N: usize> ToSimValueWithType<Array<T>>
     for [Element; N]
 {
     #[track_caller]
-    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::into_canonical(SimValue::from_array_elements(
-            <Array>::from_canonical(ty),
-            self,
-        ))
-    }
-    #[track_caller]
-    fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::into_canonical(SimValue::from_array_elements(
-            <Array>::from_canonical(ty),
-            self,
-        ))
-    }
-}
-
-impl<Element: ToSimValue<T>, T: Type> ToSimValue<Array<T>> for Vec<Element> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: Array<T>) -> SimValue<Array<T>> {
+    fn to_sim_value_with_type(&self, ty: Array<T>) -> SimValue<Array<T>> {
         SimValue::from_array_elements(ty, self)
     }
     #[track_caller]
-    fn into_sim_value(self, ty: Array<T>) -> SimValue<Array<T>> {
+    fn into_sim_value_with_type(self, ty: Array<T>) -> SimValue<Array<T>> {
         SimValue::from_array_elements(ty, self)
     }
 }
 
-impl<Element: ToSimValue<CanonicalType>> ToSimValue<CanonicalType> for Vec<Element> {
+impl<Element: ToSimValueWithType<CanonicalType>, const N: usize> ToSimValueWithType<CanonicalType>
+    for [Element; N]
+{
     #[track_caller]
-    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+    fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
         SimValue::into_canonical(SimValue::from_array_elements(
             <Array>::from_canonical(ty),
             self,
         ))
     }
     #[track_caller]
-    fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType> {
+    fn into_sim_value_with_type(self, ty: CanonicalType) -> SimValue<CanonicalType> {
         SimValue::into_canonical(SimValue::from_array_elements(
             <Array>::from_canonical(ty),
             self,
@@ -526,37 +626,131 @@ impl<Element: ToSimValue<CanonicalType>> ToSimValue<CanonicalType> for Vec<Eleme
     }
 }
 
-impl<T: Type> ToSimValue<T> for Expr<T> {
+impl<Element: ToSimValueWithType<T>, T: Type> ToSimValueWithType<Array<T>> for Vec<Element> {
     #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        assert_eq!(Expr::ty(*self), ty);
+    fn to_sim_value_with_type(&self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+    #[track_caller]
+    fn into_sim_value_with_type(self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+}
+
+impl<Element: ToSimValue<Type: StaticType>> ToSimValue for Vec<Element> {
+    type Type = Array<Element::Type>;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        SimValue::from_array_elements(ArrayType::new_dyn(StaticType::TYPE, self.len()), self)
+    }
+
+    fn into_sim_value(self) -> SimValue<Self::Type> {
+        SimValue::from_array_elements(ArrayType::new_dyn(StaticType::TYPE, self.len()), self)
+    }
+}
+
+impl<Element: ToSimValueWithType<CanonicalType>> ToSimValueWithType<CanonicalType>
+    for Vec<Element>
+{
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+    #[track_caller]
+    fn into_sim_value_with_type(self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+}
+
+impl<Element: ToSimValueWithType<T>, T: Type> ToSimValueWithType<Array<T>> for Box<[Element]> {
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+    #[track_caller]
+    fn into_sim_value_with_type(self, ty: Array<T>) -> SimValue<Array<T>> {
+        SimValue::from_array_elements(ty, self)
+    }
+}
+
+impl<Element: ToSimValue<Type: StaticType>> ToSimValue for Box<[Element]> {
+    type Type = Array<Element::Type>;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        SimValue::from_array_elements(ArrayType::new_dyn(StaticType::TYPE, self.len()), self)
+    }
+
+    fn into_sim_value(self) -> SimValue<Self::Type> {
+        SimValue::from_array_elements(ArrayType::new_dyn(StaticType::TYPE, self.len()), self)
+    }
+}
+
+impl<Element: ToSimValueWithType<CanonicalType>> ToSimValueWithType<CanonicalType>
+    for Box<[Element]>
+{
+    #[track_caller]
+    fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+    #[track_caller]
+    fn into_sim_value_with_type(self, ty: CanonicalType) -> SimValue<CanonicalType> {
+        SimValue::into_canonical(SimValue::from_array_elements(
+            <Array>::from_canonical(ty),
+            self,
+        ))
+    }
+}
+
+impl<T: Type> ToSimValue for Expr<T> {
+    type Type = T;
+    #[track_caller]
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
         SimValue::from_bitslice(
-            ty,
+            Expr::ty(*self),
             &crate::expr::ToLiteralBits::to_literal_bits(self)
                 .expect("must be a literal expression"),
         )
     }
 }
 
+forward_to_sim_value_with_type!([T: Type] Expr<T>);
+
 macro_rules! impl_to_sim_value_for_bool_like {
     ($ty:ident) => {
-        impl ToSimValue<$ty> for bool {
-            fn to_sim_value(&self, ty: $ty) -> SimValue<$ty> {
+        impl ToSimValueWithType<$ty> for bool {
+            fn to_sim_value_with_type(&self, ty: $ty) -> SimValue<$ty> {
                 SimValue::from_value(ty, *self)
             }
         }
     };
 }
 
+impl ToSimValue for bool {
+    type Type = Bool;
+
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        SimValue::from_value(Bool, *self)
+    }
+}
+
 impl_to_sim_value_for_bool_like!(Bool);
 impl_to_sim_value_for_bool_like!(AsyncReset);
 impl_to_sim_value_for_bool_like!(SyncReset);
 impl_to_sim_value_for_bool_like!(Reset);
 impl_to_sim_value_for_bool_like!(Clock);
 
-impl ToSimValue<CanonicalType> for bool {
+impl ToSimValueWithType<CanonicalType> for bool {
     #[track_caller]
-    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+    fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
         match ty {
             CanonicalType::UInt(_)
             | CanonicalType::SInt(_)
@@ -579,19 +773,22 @@ impl ToSimValue<CanonicalType> for bool {
 
 macro_rules! impl_to_sim_value_for_primitive_int {
     ($prim:ident) => {
-        impl ToSimValue<<$prim as ToExpr>::Type> for $prim {
+        impl ToSimValue for $prim {
+            type Type = <$prim as ToExpr>::Type;
+
             #[track_caller]
             fn to_sim_value(
                 &self,
-                ty: <$prim as ToExpr>::Type,
-            ) -> SimValue<<$prim as ToExpr>::Type> {
-                SimValue::from_value(ty, (*self).into())
+            ) -> SimValue<Self::Type> {
+                SimValue::from_value(StaticType::TYPE, (*self).into())
             }
         }
 
-        impl ToSimValue<<<$prim as ToExpr>::Type as IntType>::Dyn> for $prim {
+        forward_to_sim_value_with_type!([] $prim);
+
+        impl ToSimValueWithType<<<$prim as ToExpr>::Type as IntType>::Dyn> for $prim {
             #[track_caller]
-            fn to_sim_value(
+            fn to_sim_value_with_type(
                 &self,
                 ty: <<$prim as ToExpr>::Type as IntType>::Dyn,
             ) -> SimValue<<<$prim as ToExpr>::Type as IntType>::Dyn> {
@@ -602,11 +799,11 @@ macro_rules! impl_to_sim_value_for_primitive_int {
             }
         }
 
-        impl ToSimValue<CanonicalType> for $prim {
+        impl ToSimValueWithType<CanonicalType> for $prim {
             #[track_caller]
-            fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+            fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
                 let ty: <<$prim as ToExpr>::Type as IntType>::Dyn = Type::from_canonical(ty);
-                SimValue::into_canonical(self.to_sim_value(ty))
+                SimValue::into_canonical(self.to_sim_value_with_type(ty))
             }
         }
     };
@@ -627,35 +824,51 @@ impl_to_sim_value_for_primitive_int!(isize);
 
 macro_rules! impl_to_sim_value_for_int_value {
     ($IntValue:ident, $Int:ident, $IntType:ident) => {
-        impl<Width: KnownSize> ToSimValue<$IntType<Width>> for $IntValue<Width> {
-            fn to_sim_value(&self, ty: $IntType<Width>) -> SimValue<$IntType<Width>> {
-                self.bits().to_sim_value(ty)
+        impl<Width: Size> ToSimValue for $IntValue<Width> {
+            type Type = $IntType<Width>;
+
+            fn to_sim_value(&self) -> SimValue<Self::Type> {
+                SimValue::from_value(self.ty(), self.clone())
             }
 
-            fn into_sim_value(self, ty: $IntType<Width>) -> SimValue<$IntType<Width>> {
-                self.into_bits().into_sim_value(ty)
+            fn into_sim_value(self) -> SimValue<Self::Type> {
+                SimValue::from_value(self.ty(), self)
             }
         }
 
-        impl<Width: Size> ToSimValue<$Int> for $IntValue<Width> {
-            fn to_sim_value(&self, ty: $Int) -> SimValue<$Int> {
-                self.bits().to_sim_value(ty)
+        impl<Width: Size> ToSimValueWithType<$IntType<Width>> for $IntValue<Width> {
+            fn to_sim_value_with_type(&self, ty: $IntType<Width>) -> SimValue<$IntType<Width>> {
+                SimValue::from_value(ty, self.clone())
             }
 
-            fn into_sim_value(self, ty: $Int) -> SimValue<$Int> {
-                self.into_bits().into_sim_value(ty)
+            fn into_sim_value_with_type(self, ty: $IntType<Width>) -> SimValue<$IntType<Width>> {
+                SimValue::from_value(ty, self)
             }
         }
 
-        impl<Width: Size> ToSimValue<CanonicalType> for $IntValue<Width> {
+        impl<Width: KnownSize> ToSimValueWithType<$Int> for $IntValue<Width> {
+            fn to_sim_value_with_type(&self, ty: $Int) -> SimValue<$Int> {
+                self.bits().to_sim_value_with_type(ty)
+            }
+
+            fn into_sim_value_with_type(self, ty: $Int) -> SimValue<$Int> {
+                self.into_bits().into_sim_value_with_type(ty)
+            }
+        }
+
+        impl<Width: Size> ToSimValueWithType<CanonicalType> for $IntValue<Width> {
             #[track_caller]
-            fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-                SimValue::into_canonical(self.to_sim_value($Int::from_canonical(ty)))
+            fn to_sim_value_with_type(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
+                SimValue::into_canonical(
+                    self.to_sim_value_with_type($IntType::<Width>::from_canonical(ty)),
+                )
             }
 
             #[track_caller]
-            fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType> {
-                SimValue::into_canonical(self.into_sim_value($Int::from_canonical(ty)))
+            fn into_sim_value_with_type(self, ty: CanonicalType) -> SimValue<CanonicalType> {
+                SimValue::into_canonical(
+                    self.into_sim_value_with_type($IntType::<Width>::from_canonical(ty)),
+                )
             }
         }
     };
diff --git a/crates/fayalite/src/ty.rs b/crates/fayalite/src/ty.rs
index cd26c9b..23680f7 100644
--- a/crates/fayalite/src/ty.rs
+++ b/crates/fayalite/src/ty.rs
@@ -11,6 +11,7 @@ use crate::{
     intern::{Intern, Interned},
     phantom_const::PhantomConst,
     reset::{AsyncReset, Reset, SyncReset},
+    sim::value::{SimValue, ToSimValueWithType},
     source_location::SourceLocation,
     util::ConstUsize,
 };
@@ -269,7 +270,7 @@ pub trait Type:
 {
     type BaseType: BaseType;
     type MaskType: Type<MaskType = Self::MaskType>;
-    type SimValue: fmt::Debug + Clone + 'static;
+    type SimValue: fmt::Debug + Clone + 'static + ToSimValueWithType<Self>;
     type MatchVariant: 'static + Send + Sync;
     type MatchActiveScope;
     type MatchVariantAndInactiveScope: MatchVariantAndInactiveScope<
@@ -389,6 +390,15 @@ impl OpaqueSimValue {
     }
 }
 
+impl<T: Type<SimValue = OpaqueSimValue>> ToSimValueWithType<T> for OpaqueSimValue {
+    fn to_sim_value_with_type(&self, ty: T) -> SimValue<T> {
+        SimValue::from_value(ty, self.clone())
+    }
+    fn into_sim_value_with_type(self, ty: T) -> SimValue<T> {
+        SimValue::from_value(ty, self)
+    }
+}
+
 pub trait StaticType: Type {
     const TYPE: Self;
     const MASK_TYPE: Self::MaskType;
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index eb5c79e..398fe18 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -7,13 +7,7 @@ use fayalite::{
     module::{instance_with_loc, reg_builder_with_loc},
     prelude::*,
     reset::ResetType,
-    sim::{
-        time::SimDuration,
-        value::{SimValue, ToSimValue},
-        vcd::VcdWriterDecls,
-        Simulation,
-    },
-    ty::StaticType,
+    sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
     util::RcWriter,
 };
 use std::num::NonZeroUsize;
@@ -391,113 +385,110 @@ fn test_enums() {
     let mut sim = Simulation::new(enums());
     let mut writer = RcWriter::default();
     sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
-    sim.write_clock(sim.io().cd.clk, false);
-    sim.write_reset(sim.io().cd.rst, true);
-    sim.write_bool(sim.io().en, false);
-    sim.write_bool_or_int(sim.io().which_in, 0_hdl_u2);
-    sim.write_bool_or_int(sim.io().data_in, 0_hdl_u4);
+    sim.write(sim.io().cd.clk, false);
+    sim.write(sim.io().cd.rst, true);
+    sim.write(sim.io().en, false);
+    sim.write(sim.io().which_in, 0_hdl_u2);
+    sim.write(sim.io().data_in, 0_hdl_u4);
     sim.advance_time(SimDuration::from_micros(1));
-    sim.write_clock(sim.io().cd.clk, true);
+    sim.write(sim.io().cd.clk, true);
     sim.advance_time(SimDuration::from_nanos(100));
-    sim.write_reset(sim.io().cd.rst, false);
+    sim.write(sim.io().cd.rst, false);
     sim.advance_time(SimDuration::from_nanos(900));
-    type BOutTy = HdlOption<(UInt<1>, Bool)>;
-    #[derive(Debug, PartialEq)]
+    #[hdl(cmp_eq)]
     struct IO {
-        en: bool,
-        which_in: u8,
-        data_in: u8,
-        which_out: u8,
-        data_out: u8,
-        b_out: SimValue<BOutTy>,
+        en: Bool,
+        which_in: UInt<2>,
+        data_in: UInt<4>,
+        which_out: UInt<2>,
+        data_out: UInt<4>,
+        b_out: HdlOption<(UInt<1>, Bool)>,
     }
     let io_cycles = [
+        #[hdl(sim)]
         IO {
             en: false,
-            which_in: 0,
-            data_in: 0,
-            which_out: 0,
-            data_out: 0,
-            b_out: HdlNone().to_sim_value(StaticType::TYPE),
+            which_in: 0_hdl_u2,
+            data_in: 0_hdl_u4,
+            which_out: 0_hdl_u2,
+            data_out: 0_hdl_u4,
+            b_out: HdlNone(),
         },
+        #[hdl(sim)]
         IO {
             en: true,
-            which_in: 1,
-            data_in: 0,
-            which_out: 0,
-            data_out: 0,
-            b_out: HdlNone().to_sim_value(StaticType::TYPE),
+            which_in: 1_hdl_u2,
+            data_in: 0_hdl_u4,
+            which_out: 0_hdl_u2,
+            data_out: 0_hdl_u4,
+            b_out: HdlNone(),
         },
+        #[hdl(sim)]
         IO {
             en: false,
-            which_in: 0,
-            data_in: 0,
-            which_out: 1,
-            data_out: 0,
-            b_out: HdlSome((0_hdl_u1, false)).to_sim_value(StaticType::TYPE),
+            which_in: 0_hdl_u2,
+            data_in: 0_hdl_u4,
+            which_out: 1_hdl_u2,
+            data_out: 0_hdl_u4,
+            b_out: HdlSome((0_hdl_u1, false)),
         },
+        #[hdl(sim)]
         IO {
             en: true,
-            which_in: 1,
-            data_in: 0xF,
-            which_out: 1,
-            data_out: 0,
-            b_out: HdlSome((0_hdl_u1, false)).to_sim_value(StaticType::TYPE),
+            which_in: 1_hdl_u2,
+            data_in: 0xF_hdl_u4,
+            which_out: 1_hdl_u2,
+            data_out: 0_hdl_u4,
+            b_out: HdlSome((0_hdl_u1, false)),
         },
+        #[hdl(sim)]
         IO {
             en: true,
-            which_in: 1,
-            data_in: 0xF,
-            which_out: 1,
-            data_out: 0x3,
-            b_out: HdlSome((1_hdl_u1, true)).to_sim_value(StaticType::TYPE),
+            which_in: 1_hdl_u2,
+            data_in: 0xF_hdl_u4,
+            which_out: 1_hdl_u2,
+            data_out: 0x3_hdl_u4,
+            b_out: HdlSome((1_hdl_u1, true)),
         },
+        #[hdl(sim)]
         IO {
             en: true,
-            which_in: 2,
-            data_in: 0xF,
-            which_out: 1,
-            data_out: 0x3,
-            b_out: HdlSome((1_hdl_u1, true)).to_sim_value(StaticType::TYPE),
+            which_in: 2_hdl_u2,
+            data_in: 0xF_hdl_u4,
+            which_out: 1_hdl_u2,
+            data_out: 0x3_hdl_u4,
+            b_out: HdlSome((1_hdl_u1, true)),
         },
+        #[hdl(sim)]
         IO {
             en: true,
-            which_in: 2,
-            data_in: 0xF,
-            which_out: 2,
-            data_out: 0xF,
-            b_out: HdlNone().to_sim_value(StaticType::TYPE),
+            which_in: 2_hdl_u2,
+            data_in: 0xF_hdl_u4,
+            which_out: 2_hdl_u2,
+            data_out: 0xF_hdl_u4,
+            b_out: HdlNone(),
         },
     ];
-    for (
-        cycle,
-        expected @ IO {
+    for (cycle, expected) in io_cycles.into_iter().enumerate() {
+        #[hdl(sim)]
+        let IO {
             en,
             which_in,
             data_in,
             which_out: _,
             data_out: _,
             b_out: _,
-        },
-    ) in io_cycles.into_iter().enumerate()
-    {
-        sim.write_bool(sim.io().en, en);
-        sim.write_bool_or_int(sim.io().which_in, which_in.cast_to_static());
-        sim.write_bool_or_int(sim.io().data_in, data_in.cast_to_static());
-        let io = IO {
+        } = expected;
+        sim.write(sim.io().en, &en);
+        sim.write(sim.io().which_in, &which_in);
+        sim.write(sim.io().data_in, &data_in);
+        let io = #[hdl(sim)]
+        IO {
             en,
             which_in,
             data_in,
-            which_out: sim
-                .read_bool_or_int(sim.io().which_out)
-                .to_bigint()
-                .try_into()
-                .expect("known to be in range"),
-            data_out: sim
-                .read_bool_or_int(sim.io().data_out)
-                .to_bigint()
-                .try_into()
-                .expect("known to be in range"),
+            which_out: sim.read(sim.io().which_out),
+            data_out: sim.read(sim.io().data_out),
             b_out: sim.read(sim.io().b_out),
         };
         assert_eq!(
@@ -559,7 +550,7 @@ fn test_memories() {
         w_mask: (Bool, Bool),
     }
     let io_cycles = [
-        #[hdl]
+        #[hdl(sim)]
         IO {
             r_addr: 0_hdl_u4,
             r_en: false,
@@ -569,7 +560,7 @@ fn test_memories() {
             w_data: (0u8, 0i8),
             w_mask: (false, false),
         },
-        #[hdl]
+        #[hdl(sim)]
         IO {
             r_addr: 0_hdl_u4,
             r_en: true,
@@ -579,7 +570,7 @@ fn test_memories() {
             w_data: (0x10u8, 0x20i8),
             w_mask: (true, true),
         },
-        #[hdl]
+        #[hdl(sim)]
         IO {
             r_addr: 0_hdl_u4,
             r_en: true,
@@ -589,7 +580,7 @@ fn test_memories() {
             w_data: (0x30u8, 0x40i8),
             w_mask: (false, true),
         },
-        #[hdl]
+        #[hdl(sim)]
         IO {
             r_addr: 0_hdl_u4,
             r_en: true,
@@ -599,7 +590,7 @@ fn test_memories() {
             w_data: (0x50u8, 0x60i8),
             w_mask: (true, false),
         },
-        #[hdl]
+        #[hdl(sim)]
         IO {
             r_addr: 0_hdl_u4,
             r_en: true,
@@ -609,7 +600,7 @@ fn test_memories() {
             w_data: (0x70u8, -0x80i8),
             w_mask: (false, false),
         },
-        #[hdl]
+        #[hdl(sim)]
         IO {
             r_addr: 0_hdl_u4,
             r_en: true,
@@ -619,7 +610,7 @@ fn test_memories() {
             w_data: (0x90u8, 0xA0u8 as i8),
             w_mask: (false, false),
         },
-        #[hdl]
+        #[hdl(sim)]
         IO {
             r_addr: 0_hdl_u4,
             r_en: true,
@@ -629,7 +620,7 @@ fn test_memories() {
             w_data: (0x90u8, 0xA0u8 as i8),
             w_mask: (true, true),
         },
-        #[hdl]
+        #[hdl(sim)]
         IO {
             r_addr: 0_hdl_u4,
             r_en: true,
@@ -639,7 +630,7 @@ fn test_memories() {
             w_data: (0xB0u8, 0xC0u8 as i8),
             w_mask: (true, true),
         },
-        #[hdl]
+        #[hdl(sim)]
         IO {
             r_addr: 0_hdl_u4,
             r_en: true,
@@ -649,7 +640,7 @@ fn test_memories() {
             w_data: (0xD0u8, 0xE0u8 as i8),
             w_mask: (true, true),
         },
-        #[hdl]
+        #[hdl(sim)]
         IO {
             r_addr: 1_hdl_u4,
             r_en: true,
@@ -659,7 +650,7 @@ fn test_memories() {
             w_data: (0xD0u8, 0xE0u8 as i8),
             w_mask: (true, true),
         },
-        #[hdl]
+        #[hdl(sim)]
         IO {
             r_addr: 2_hdl_u4,
             r_en: true,
@@ -671,7 +662,7 @@ fn test_memories() {
         },
     ];
     for (cycle, expected) in io_cycles.into_iter().enumerate() {
-        #[hdl]
+        #[hdl(sim)]
         let IO {
             r_addr,
             r_en,
@@ -681,13 +672,13 @@ fn test_memories() {
             w_data,
             w_mask,
         } = expected;
-        sim.write(sim.io().r.addr, r_addr);
-        sim.write(sim.io().r.en, r_en);
-        sim.write(sim.io().w.addr, w_addr);
-        sim.write(sim.io().w.en, w_en);
-        sim.write(sim.io().w.data, w_data);
-        sim.write(sim.io().w.mask, w_mask);
-        let io = (#[hdl]
+        sim.write(sim.io().r.addr, &r_addr);
+        sim.write(sim.io().r.en, &r_en);
+        sim.write(sim.io().w.addr, &w_addr);
+        sim.write(sim.io().w.en, &w_en);
+        sim.write(sim.io().w.data, &w_data);
+        sim.write(sim.io().w.mask, &w_mask);
+        let io = #[hdl(sim)]
         IO {
             r_addr,
             r_en,
@@ -696,20 +687,19 @@ fn test_memories() {
             w_en,
             w_data,
             w_mask,
-        })
-        .to_sim_value(StaticType::TYPE);
+        };
         assert_eq!(
-            expected.to_sim_value(StaticType::TYPE),
+            expected,
             io,
             "vcd:\n{}\ncycle: {cycle}",
             String::from_utf8(writer.take()).unwrap(),
         );
         sim.advance_time(SimDuration::from_micros(1));
-        sim.write_clock(sim.io().r.clk, true);
-        sim.write_clock(sim.io().w.clk, true);
+        sim.write(sim.io().r.clk, true);
+        sim.write(sim.io().w.clk, true);
         sim.advance_time(SimDuration::from_micros(1));
-        sim.write_clock(sim.io().r.clk, false);
-        sim.write_clock(sim.io().w.clk, false);
+        sim.write(sim.io().r.clk, false);
+        sim.write(sim.io().w.clk, false);
     }
     sim.flush_traces().unwrap();
     let vcd = String::from_utf8(writer.take()).unwrap();

From 9092e45447136e332a346c82d4e2bb6bb16dac0f Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 30 Mar 2025 01:25:07 -0700
Subject: [PATCH 172/190] fix #[hdl(sim)] match on enums

---
 .../src/module/transform_body/expand_match.rs | 46 +++++++++++++++++--
 crates/fayalite/tests/sim.rs                  |  6 +++
 2 files changed, 47 insertions(+), 5 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
index 57e919a..a2e0375 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
@@ -83,7 +83,14 @@ visit_trait! {
         }
     }
     fn visit_match_pat_enum_variant(state: _, v: &MatchPatEnumVariant) {
-        let MatchPatEnumVariant {match_span:_, variant_path: _, enum_path: _, variant_name: _, field } = v;
+        let MatchPatEnumVariant {
+            match_span:_,
+            sim:_,
+            variant_path: _,
+            enum_path: _,
+            variant_name: _,
+            field,
+        } = v;
         if let Some((_, v)) = field {
             state.visit_match_pat_simple(v);
         }
@@ -293,6 +300,7 @@ impl ToTokens for MatchPatTuple {
 with_debug_clone_and_fold! {
     struct MatchPatEnumVariant<> {
         match_span: Span,
+        sim: Option<(kw::sim,)>,
         variant_path: Path,
         enum_path: Path,
         variant_name: Ident,
@@ -304,6 +312,7 @@ impl ToTokens for MatchPatEnumVariant {
     fn to_tokens(&self, tokens: &mut TokenStream) {
         let Self {
             match_span,
+            sim,
             variant_path: _,
             enum_path,
             variant_name,
@@ -313,7 +322,28 @@ impl ToTokens for MatchPatEnumVariant {
             __MatchTy::<#enum_path>::#variant_name
         }
         .to_tokens(tokens);
-        if let Some((paren_token, field)) = field {
+        if sim.is_some() {
+            if let Some((paren_token, field)) = field {
+                paren_token.surround(tokens, |tokens| {
+                    field.to_tokens(tokens);
+                    match field {
+                        MatchPatSimple::Paren(_)
+                        | MatchPatSimple::Or(_)
+                        | MatchPatSimple::Binding(_)
+                        | MatchPatSimple::Wild(_) => quote_spanned! {*match_span=>
+                            , _
+                        }
+                        .to_tokens(tokens),
+                        MatchPatSimple::Rest(_) => {}
+                    }
+                });
+            } else {
+                quote_spanned! {*match_span=>
+                    (_)
+                }
+                .to_tokens(tokens);
+            }
+        } else if let Some((paren_token, field)) = field {
             paren_token.surround(tokens, |tokens| field.to_tokens(tokens));
         }
     }
@@ -448,6 +478,7 @@ trait ParseMatchPat: Sized {
                         state,
                         MatchPatEnumVariant {
                             match_span: state.match_span,
+                            sim: state.sim,
                             variant_path,
                             enum_path,
                             variant_name,
@@ -494,6 +525,7 @@ trait ParseMatchPat: Sized {
                     state,
                     MatchPatEnumVariant {
                         match_span: state.match_span,
+                        sim: state.sim,
                         variant_path,
                         enum_path,
                         variant_name,
@@ -578,6 +610,7 @@ trait ParseMatchPat: Sized {
                     state,
                     MatchPatEnumVariant {
                         match_span: state.match_span,
+                        sim: state.sim,
                         variant_path,
                         enum_path,
                         variant_name,
@@ -940,6 +973,7 @@ impl Fold for RewriteAsCheckMatch {
 }
 
 struct HdlMatchParseState<'a> {
+    sim: Option<(kw::sim,)>,
     match_span: Span,
     errors: &'a mut Errors,
 }
@@ -986,6 +1020,7 @@ impl Visitor<'_> {
         mut let_stmt: Local,
     ) -> Local {
         let span = let_stmt.let_token.span();
+        let ExprOptions { sim } = hdl_attr.body;
         if let Pat::Type(pat) = &mut let_stmt.pat {
             *pat.ty = wrap_ty_with_expr((*pat.ty).clone());
         }
@@ -1015,6 +1050,7 @@ impl Visitor<'_> {
         }
         let Ok(pat) = MatchPat::parse(
             &mut HdlMatchParseState {
+                sim,
                 match_span: span,
                 errors: &mut self.errors,
             },
@@ -1031,7 +1067,6 @@ impl Visitor<'_> {
             errors: _,
             bindings,
         } = state;
-        let ExprOptions { sim } = hdl_attr.body;
         let retval = if sim.is_some() {
             parse_quote_spanned! {span=>
                 let (#(#bindings,)*) = {
@@ -1093,7 +1128,9 @@ impl Visitor<'_> {
             brace_token: _,
             arms,
         } = expr_match;
+        let ExprOptions { sim } = hdl_attr.body;
         let mut state = HdlMatchParseState {
+            sim,
             match_span: span,
             errors: &mut self.errors,
         };
@@ -1101,13 +1138,12 @@ impl Visitor<'_> {
             arms.into_iter()
                 .filter_map(|arm| MatchArm::parse(&mut state, arm).ok()),
         );
-        let ExprOptions { sim } = hdl_attr.body;
         let expr = if sim.is_some() {
             quote_spanned! {span=>
                 {
                     type __MatchTy<T> = <T as ::fayalite::ty::Type>::SimValue;
                     let __match_expr = ::fayalite::sim::value::ToSimValue::to_sim_value(&(#expr));
-                    #match_token *__match_expr {
+                    #match_token ::fayalite::sim::value::SimValue::into_value(__match_expr) {
                         #(#arms)*
                     }
                 }
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 398fe18..71e53ea 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -497,6 +497,12 @@ fn test_enums() {
             "vcd:\n{}\ncycle: {cycle}",
             String::from_utf8(writer.take()).unwrap(),
         );
+        // make sure matching on SimValue<SomeEnum> works
+        #[hdl(sim)]
+        match io.b_out {
+            HdlNone => println!("io.b_out is HdlNone"),
+            HdlSome(v) => println!("io.b_out is HdlSome(({:?}, {:?}))", *v.0, *v.1),
+        }
         sim.write_clock(sim.io().cd.clk, false);
         sim.advance_time(SimDuration::from_micros(1));
         sim.write_clock(sim.io().cd.clk, true);

From c4b6a0fee6501cf0dde3fb06422af3a96eca5fe3 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 1 Apr 2025 22:05:42 -0700
Subject: [PATCH 173/190] add support for #[hdl(sim)] enum_ty.Variant(value)
 and #[hdl(sim)] EnumTy::Variant(value) and non-sim variants too

---
 crates/fayalite-proc-macros-impl/src/fold.rs  |   1 +
 .../fayalite-proc-macros-impl/src/hdl_enum.rs |  74 ++
 .../src/module/transform_body.rs              |   2 +
 .../expand_aggregate_literals.rs              | 115 ++-
 .../src/module/transform_body/expand_match.rs |  10 +-
 crates/fayalite/src/enum_.rs                  |  25 +
 crates/fayalite/tests/sim.rs                  |  72 +-
 crates/fayalite/tests/sim/expected/enums.txt  | 846 +++++++++++-------
 crates/fayalite/tests/sim/expected/enums.vcd  |  42 +-
 9 files changed, 817 insertions(+), 370 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/fold.rs b/crates/fayalite-proc-macros-impl/src/fold.rs
index 49cc8c1..22e7b82 100644
--- a/crates/fayalite-proc-macros-impl/src/fold.rs
+++ b/crates/fayalite-proc-macros-impl/src/fold.rs
@@ -220,6 +220,7 @@ forward_fold!(syn::ExprArray => fold_expr_array);
 forward_fold!(syn::ExprCall => fold_expr_call);
 forward_fold!(syn::ExprIf => fold_expr_if);
 forward_fold!(syn::ExprMatch => fold_expr_match);
+forward_fold!(syn::ExprMethodCall => fold_expr_method_call);
 forward_fold!(syn::ExprPath => fold_expr_path);
 forward_fold!(syn::ExprRepeat => fold_expr_repeat);
 forward_fold!(syn::ExprStruct => fold_expr_struct);
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
index dd09a73..6fb2a56 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
@@ -130,6 +130,8 @@ pub(crate) struct ParsedEnum {
     pub(crate) variants: Punctuated<ParsedVariant, Token![,]>,
     pub(crate) match_variant_ident: Ident,
     pub(crate) sim_value_ident: Ident,
+    pub(crate) sim_builder_ident: Ident,
+    pub(crate) sim_builder_ty_field_ident: Ident,
 }
 
 impl ParsedEnum {
@@ -192,6 +194,8 @@ impl ParsedEnum {
             variants,
             match_variant_ident: format_ident!("__{}__MatchVariant", ident),
             sim_value_ident: format_ident!("__{}__SimValue", ident),
+            sim_builder_ident: format_ident!("__{}__SimBuilder", ident),
+            sim_builder_ty_field_ident: format_ident!("__ty", span = ident.span()),
             ident,
         })
     }
@@ -210,6 +214,8 @@ impl ToTokens for ParsedEnum {
             variants,
             match_variant_ident,
             sim_value_ident,
+            sim_builder_ident,
+            sim_builder_ty_field_ident,
         } = self;
         let span = ident.span();
         let ItemOptions {
@@ -412,6 +418,33 @@ impl ToTokens for ParsedEnum {
             )),
         }
         .to_tokens(tokens);
+        let mut struct_attrs = attrs.clone();
+        struct_attrs.push(parse_quote_spanned! {span=>
+            #[allow(dead_code, non_camel_case_types)]
+        });
+        ItemStruct {
+            attrs: struct_attrs,
+            vis: vis.clone(),
+            struct_token: Token![struct](enum_token.span),
+            ident: sim_builder_ident.clone(),
+            generics: generics.into(),
+            fields: FieldsNamed {
+                brace_token: *brace_token,
+                named: Punctuated::from_iter([Field {
+                    attrs: vec![],
+                    vis: Visibility::Inherited,
+                    mutability: FieldMutability::None,
+                    ident: Some(sim_builder_ty_field_ident.clone()),
+                    colon_token: Some(Token![:](span)),
+                    ty: parse_quote_spanned! {span=>
+                        #target #type_generics
+                    },
+                }]),
+            }
+            .into(),
+            semi_token: None,
+        }
+        .to_tokens(tokens);
         let mut enum_attrs = attrs.clone();
         enum_attrs.push(parse_quote_spanned! {span=>
             #[::fayalite::__std::prelude::v1::derive(
@@ -538,6 +571,25 @@ impl ToTokens for ParsedEnum {
                             )
                         }
                     }
+                    #[automatically_derived]
+                    impl #impl_generics #sim_builder_ident #type_generics
+                    #where_clause
+                    {
+                        #[allow(non_snake_case, dead_code)]
+                        #vis fn #ident<__V: ::fayalite::sim::value::ToSimValueWithType<#ty>>(
+                            #self_token,
+                            v: __V,
+                        ) -> ::fayalite::sim::value::SimValue<#target #type_generics> {
+                            let v = ::fayalite::sim::value::ToSimValueWithType::into_sim_value_with_type(
+                                v,
+                                #self_token.#sim_builder_ty_field_ident.#ident,
+                            );
+                            ::fayalite::sim::value::SimValue::from_value(
+                                #self_token.#sim_builder_ty_field_ident,
+                                #sim_value_ident::#ident(v, ::fayalite::enum_::EnumPaddingSimValue::new()),
+                            )
+                        }
+                    }
                 }
             } else {
                 quote_spanned! {span=>
@@ -556,6 +608,18 @@ impl ToTokens for ParsedEnum {
                             )
                         }
                     }
+                    #[automatically_derived]
+                    impl #impl_generics #sim_builder_ident #type_generics
+                    #where_clause
+                    {
+                        #[allow(non_snake_case, dead_code)]
+                        #vis fn #ident(#self_token) -> ::fayalite::sim::value::SimValue<#target #type_generics> {
+                            ::fayalite::sim::value::SimValue::from_value(
+                                #self_token.#sim_builder_ty_field_ident,
+                                #sim_value_ident::#ident(::fayalite::enum_::EnumPaddingSimValue::new()),
+                            )
+                        }
+                    }
                 }
             }
             .to_tokens(tokens);
@@ -848,6 +912,7 @@ impl ToTokens for ParsedEnum {
             impl #impl_generics ::fayalite::enum_::EnumType for #target #type_generics
             #where_clause
             {
+                type SimBuilder = #sim_builder_ident #type_generics;
                 fn match_activate_scope(
                     v: <Self as ::fayalite::ty::Type>::MatchVariantAndInactiveScope,
                 ) -> (<Self as ::fayalite::ty::Type>::MatchVariant, <Self as ::fayalite::ty::Type>::MatchActiveScope) {
@@ -884,6 +949,15 @@ impl ToTokens for ParsedEnum {
                     ::fayalite::sim::value::SimValue::from_value(ty, self)
                 }
             }
+            #[automatically_derived]
+            impl #impl_generics ::fayalite::__std::convert::From<#target #type_generics>
+            for #sim_builder_ident #type_generics
+            #where_clause
+            {
+                fn from(#sim_builder_ty_field_ident: #target #type_generics) -> Self {
+                    Self { #sim_builder_ty_field_ident }
+                }
+            }
         }
         .to_tokens(tokens);
         if let (None, MaybeParsed::Parsed(generics)) = (no_static, &self.generics) {
diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
index 8f427a9..a0f8eb0 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body.rs
@@ -1687,6 +1687,8 @@ impl Fold for Visitor<'_> {
                 Repeat => process_hdl_repeat,
                 Struct => process_hdl_struct,
                 Tuple => process_hdl_tuple,
+                MethodCall => process_hdl_method_call,
+                Call => process_hdl_call,
             }
         }
     }
diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs
index 8892bd5..61f6c75 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs
@@ -1,14 +1,20 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
+
 use crate::{
     kw,
-    module::transform_body::{ExprOptions, Visitor},
+    module::transform_body::{
+        expand_match::{parse_enum_path, EnumPath},
+        ExprOptions, Visitor,
+    },
     HdlAttr,
 };
 use quote::{format_ident, quote_spanned};
+use std::mem;
 use syn::{
-    parse_quote_spanned, spanned::Spanned, Expr, ExprArray, ExprPath, ExprRepeat, ExprStruct,
-    ExprTuple, FieldValue, TypePath,
+    parse_quote_spanned, punctuated::Punctuated, spanned::Spanned, token::Paren, Expr, ExprArray,
+    ExprCall, ExprGroup, ExprMethodCall, ExprParen, ExprPath, ExprRepeat, ExprStruct, ExprTuple,
+    FieldValue, Token, TypePath,
 };
 
 impl Visitor<'_> {
@@ -162,4 +168,107 @@ impl Visitor<'_> {
             }
         }
     }
+    pub(crate) fn process_hdl_call(
+        &mut self,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
+        mut expr_call: ExprCall,
+    ) -> Expr {
+        let span = hdl_attr.kw.span;
+        let mut func = &mut *expr_call.func;
+        let EnumPath {
+            variant_path: _,
+            enum_path,
+            variant_name,
+        } = loop {
+            match func {
+                Expr::Group(ExprGroup { expr, .. }) | Expr::Paren(ExprParen { expr, .. }) => {
+                    func = &mut **expr;
+                }
+                Expr::Path(_) => {
+                    let Expr::Path(ExprPath { attrs, qself, path }) =
+                        mem::replace(func, Expr::PLACEHOLDER)
+                    else {
+                        unreachable!();
+                    };
+                    match parse_enum_path(TypePath { qself, path }) {
+                        Ok(path) => break path,
+                        Err(path) => {
+                            self.errors.error(&path, "unsupported enum variant path");
+                            let TypePath { qself, path } = path;
+                            *func = ExprPath { attrs, qself, path }.into();
+                            return expr_call.into();
+                        }
+                    }
+                }
+                _ => {
+                    self.errors.error(
+                        &expr_call.func,
+                        "#[hdl] function call -- function must be a possibly-parenthesized path",
+                    );
+                    return expr_call.into();
+                }
+            }
+        };
+        self.process_hdl_method_call(
+            hdl_attr,
+            ExprMethodCall {
+                attrs: expr_call.attrs,
+                receiver: parse_quote_spanned! {span=>
+                    <#enum_path as ::fayalite::ty::StaticType>::TYPE
+                },
+                dot_token: Token![.](span),
+                method: variant_name,
+                turbofish: None,
+                paren_token: expr_call.paren_token,
+                args: expr_call.args,
+            },
+        )
+    }
+    pub(crate) fn process_hdl_method_call(
+        &mut self,
+        hdl_attr: HdlAttr<ExprOptions, kw::hdl>,
+        mut expr_method_call: ExprMethodCall,
+    ) -> Expr {
+        let ExprOptions { sim } = hdl_attr.body;
+        let span = hdl_attr.kw.span;
+        // remove any number of groups and up to one paren
+        let mut receiver = &mut *expr_method_call.receiver;
+        let mut has_group = false;
+        let receiver = loop {
+            match receiver {
+                Expr::Group(ExprGroup { expr, .. }) => {
+                    has_group = true;
+                    receiver = expr;
+                }
+                Expr::Paren(ExprParen { expr, .. }) => break &mut **expr,
+                receiver @ Expr::Path(_) => break receiver,
+                _ => {
+                    if !has_group {
+                        self.errors.error(
+                            &expr_method_call.receiver,
+                            "#[hdl] on a method call needs parenthesized receiver",
+                        );
+                    }
+                    break &mut *expr_method_call.receiver;
+                }
+            }
+        };
+        let func = if sim.is_some() {
+            parse_quote_spanned! {span=>
+                ::fayalite::enum_::enum_type_to_sim_builder
+            }
+        } else {
+            parse_quote_spanned! {span=>
+                ::fayalite::enum_::assert_is_enum_type
+            }
+        };
+        *expr_method_call.receiver = ExprCall {
+            attrs: vec![],
+            func,
+            paren_token: Paren(span),
+            args: Punctuated::from_iter([mem::replace(receiver, Expr::PLACEHOLDER)]),
+        }
+        .into();
+        expr_method_call.into()
+    }
 }
diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
index a2e0375..68218c1 100644
--- a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
+++ b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs
@@ -380,13 +380,13 @@ impl ToTokens for MatchPatSimple {
     }
 }
 
-struct EnumPath {
-    variant_path: Path,
-    enum_path: Path,
-    variant_name: Ident,
+pub(crate) struct EnumPath {
+    pub(crate) variant_path: Path,
+    pub(crate) enum_path: Path,
+    pub(crate) variant_name: Ident,
 }
 
-fn parse_enum_path(variant_path: TypePath) -> Result<EnumPath, TypePath> {
+pub(crate) fn parse_enum_path(variant_path: TypePath) -> Result<EnumPath, TypePath> {
     let TypePath {
         qself: None,
         path: variant_path,
diff --git a/crates/fayalite/src/enum_.rs b/crates/fayalite/src/enum_.rs
index 9fa38e9..e37b7a5 100644
--- a/crates/fayalite/src/enum_.rs
+++ b/crates/fayalite/src/enum_.rs
@@ -259,6 +259,7 @@ pub trait EnumType:
     MatchVariantsIter = EnumMatchVariantsIter<Self>,
 >
 {
+    type SimBuilder: From<Self>;
     fn variants(&self) -> Interned<[EnumVariant]>;
     fn match_activate_scope(
         v: Self::MatchVariantAndInactiveScope,
@@ -321,7 +322,18 @@ impl<T: EnumType> DoubleEndedIterator for EnumMatchVariantsIter<T> {
     }
 }
 
+pub struct NoBuilder {
+    _ty: Enum,
+}
+
+impl From<Enum> for NoBuilder {
+    fn from(_ty: Enum) -> Self {
+        Self { _ty }
+    }
+}
+
 impl EnumType for Enum {
+    type SimBuilder = NoBuilder;
     fn match_activate_scope(
         v: Self::MatchVariantAndInactiveScope,
     ) -> (Self::MatchVariant, Self::MatchActiveScope) {
@@ -389,6 +401,9 @@ pub struct EnumPaddingSimValue {
 }
 
 impl EnumPaddingSimValue {
+    pub const fn new() -> Self {
+        Self { bits: None }
+    }
     pub fn bit_width(&self) -> Option<usize> {
         self.bits.as_ref().map(UIntValue::width)
     }
@@ -659,6 +674,16 @@ impl<'a> EnumSimValueToBits<'a> {
     }
 }
 
+#[doc(hidden)]
+pub fn assert_is_enum_type<T: EnumType>(v: T) -> T {
+    v
+}
+
+#[doc(hidden)]
+pub fn enum_type_to_sim_builder<T: EnumType>(v: T) -> T::SimBuilder {
+    v.into()
+}
+
 #[hdl]
 pub enum HdlOption<T: Type> {
     HdlNone,
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 71e53ea..6433844 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -317,8 +317,13 @@ pub fn enums() {
     let which_out: UInt<2> = m.output();
     #[hdl]
     let data_out: UInt<4> = m.output();
+    let b_out_ty = HdlOption[(UInt[1], Bool)];
     #[hdl]
-    let b_out: HdlOption<(UInt<1>, Bool)> = m.output();
+    let b_out: HdlOption<(UInt, Bool)> = m.output(HdlOption[(UInt[1], Bool)]);
+    #[hdl]
+    let b2_out: HdlOption<(UInt<1>, Bool)> = m.output();
+
+    connect_any(b2_out, b_out);
 
     #[hdl]
     struct MyStruct<T> {
@@ -358,7 +363,7 @@ pub fn enums() {
         }
     }
 
-    connect(b_out, HdlNone());
+    connect(b_out, b_out_ty.HdlNone());
 
     #[hdl]
     match the_reg {
@@ -369,7 +374,7 @@ pub fn enums() {
         MyEnum::B(v) => {
             connect(which_out, 1_hdl_u2);
             connect_any(data_out, v.0 | (v.1.cast_to_static::<UInt<1>>() << 1));
-            connect(b_out, HdlSome(v));
+            connect_any(b_out, HdlSome(v));
         }
         MyEnum::C(v) => {
             connect(which_out, 2_hdl_u2);
@@ -396,100 +401,125 @@ fn test_enums() {
     sim.write(sim.io().cd.rst, false);
     sim.advance_time(SimDuration::from_nanos(900));
     #[hdl(cmp_eq)]
-    struct IO {
+    struct IO<W: Size> {
         en: Bool,
         which_in: UInt<2>,
         data_in: UInt<4>,
         which_out: UInt<2>,
         data_out: UInt<4>,
-        b_out: HdlOption<(UInt<1>, Bool)>,
+        b_out: HdlOption<(UIntType<W>, Bool)>,
+        b2_out: HdlOption<(UInt<1>, Bool)>,
     }
+    let io_ty = IO[1];
     let io_cycles = [
         #[hdl(sim)]
-        IO {
+        IO::<_> {
             en: false,
             which_in: 0_hdl_u2,
             data_in: 0_hdl_u4,
             which_out: 0_hdl_u2,
             data_out: 0_hdl_u4,
-            b_out: HdlNone(),
+            b_out: #[hdl(sim)]
+            (io_ty.b_out).HdlNone(),
+            b2_out: #[hdl(sim)]
+            HdlNone(),
         },
         #[hdl(sim)]
-        IO {
+        IO::<_> {
             en: true,
             which_in: 1_hdl_u2,
             data_in: 0_hdl_u4,
             which_out: 0_hdl_u2,
             data_out: 0_hdl_u4,
-            b_out: HdlNone(),
+            b_out: #[hdl(sim)]
+            (io_ty.b_out).HdlNone(),
+            b2_out: #[hdl(sim)]
+            HdlNone(),
         },
         #[hdl(sim)]
-        IO {
+        IO::<_> {
             en: false,
             which_in: 0_hdl_u2,
             data_in: 0_hdl_u4,
             which_out: 1_hdl_u2,
             data_out: 0_hdl_u4,
-            b_out: HdlSome((0_hdl_u1, false)),
+            b_out: #[hdl(sim)]
+            (io_ty.b_out).HdlSome((0u8.cast_to(UInt[1]), false)),
+            b2_out: #[hdl(sim)]
+            HdlSome((0_hdl_u1, false)),
         },
         #[hdl(sim)]
-        IO {
+        IO::<_> {
             en: true,
             which_in: 1_hdl_u2,
             data_in: 0xF_hdl_u4,
             which_out: 1_hdl_u2,
             data_out: 0_hdl_u4,
-            b_out: HdlSome((0_hdl_u1, false)),
+            b_out: #[hdl(sim)]
+            (io_ty.b_out).HdlSome((0u8.cast_to(UInt[1]), false)),
+            b2_out: #[hdl(sim)]
+            HdlSome((0_hdl_u1, false)),
         },
         #[hdl(sim)]
-        IO {
+        IO::<_> {
             en: true,
             which_in: 1_hdl_u2,
             data_in: 0xF_hdl_u4,
             which_out: 1_hdl_u2,
             data_out: 0x3_hdl_u4,
-            b_out: HdlSome((1_hdl_u1, true)),
+            b_out: #[hdl(sim)]
+            (io_ty.b_out).HdlSome((1u8.cast_to(UInt[1]), true)),
+            b2_out: #[hdl(sim)]
+            HdlSome((1_hdl_u1, true)),
         },
         #[hdl(sim)]
-        IO {
+        IO::<_> {
             en: true,
             which_in: 2_hdl_u2,
             data_in: 0xF_hdl_u4,
             which_out: 1_hdl_u2,
             data_out: 0x3_hdl_u4,
-            b_out: HdlSome((1_hdl_u1, true)),
+            b_out: #[hdl(sim)]
+            (io_ty.b_out).HdlSome((1u8.cast_to(UInt[1]), true)),
+            b2_out: #[hdl(sim)]
+            HdlSome((1_hdl_u1, true)),
         },
         #[hdl(sim)]
-        IO {
+        IO::<_> {
             en: true,
             which_in: 2_hdl_u2,
             data_in: 0xF_hdl_u4,
             which_out: 2_hdl_u2,
             data_out: 0xF_hdl_u4,
-            b_out: HdlNone(),
+            b_out: #[hdl(sim)]
+            (io_ty.b_out).HdlNone(),
+            b2_out: #[hdl(sim)]
+            HdlNone(),
         },
     ];
     for (cycle, expected) in io_cycles.into_iter().enumerate() {
         #[hdl(sim)]
-        let IO {
+        let IO::<_> {
             en,
             which_in,
             data_in,
             which_out: _,
             data_out: _,
             b_out: _,
+            b2_out: _,
         } = expected;
         sim.write(sim.io().en, &en);
         sim.write(sim.io().which_in, &which_in);
         sim.write(sim.io().data_in, &data_in);
         let io = #[hdl(sim)]
-        IO {
+        IO::<_> {
             en,
             which_in,
             data_in,
             which_out: sim.read(sim.io().which_out),
             data_out: sim.read(sim.io().data_out),
             b_out: sim.read(sim.io().b_out),
+            b2_out: sim.read(sim.io().b2_out),
         };
         assert_eq!(
             expected,
diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt
index 089ea31..61ce5d5 100644
--- a/crates/fayalite/tests/sim/expected/enums.txt
+++ b/crates/fayalite/tests/sim/expected/enums.txt
@@ -4,7 +4,7 @@ Simulation {
             state_layout: StateLayout {
                 ty: TypeLayout {
                     small_slots: StatePartLayout<SmallSlots> {
-                        len: 6,
+                        len: 7,
                         debug_data: [
                             SlotDebugData {
                                 name: "",
@@ -13,6 +13,13 @@ Simulation {
                                     HdlSome,
                                 },
                             },
+                            SlotDebugData {
+                                name: "",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome,
+                                },
+                            },
                             SlotDebugData {
                                 name: "",
                                 ty: Bool,
@@ -41,7 +48,7 @@ Simulation {
                         ..
                     },
                     big_slots: StatePartLayout<BigSlots> {
-                        len: 103,
+                        len: 111,
                         debug_data: [
                             SlotDebugData {
                                 name: "InstantiatedModule(enums: enums).enums::cd.clk",
@@ -106,6 +113,41 @@ Simulation {
                                 name: "",
                                 ty: Bool,
                             },
+                            SlotDebugData {
+                                name: "InstantiatedModule(enums: enums).enums::b2_out",
+                                ty: Enum {
+                                    HdlNone,
+                                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                                },
+                            },
+                            SlotDebugData {
+                                name: ".0",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: ".1",
+                                ty: Bool,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<3>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<2>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: UInt<1>,
+                            },
+                            SlotDebugData {
+                                name: "",
+                                ty: Bool,
+                            },
                             SlotDebugData {
                                 name: "InstantiatedModule(enums: enums).enums::the_reg",
                                 ty: Enum {
@@ -498,594 +540,640 @@ Simulation {
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
                 0: Const {
-                    dest: StatePartIndex<BigSlots>(90), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(98), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                     value: 0x1,
                 },
                 1: Const {
-                    dest: StatePartIndex<BigSlots>(82), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(90), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
                     value: 0x0,
                 },
                 2: Const {
-                    dest: StatePartIndex<BigSlots>(80), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    dest: StatePartIndex<BigSlots>(88), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     value: 0x0,
                 },
                 3: Copy {
-                    dest: StatePartIndex<BigSlots>(81), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
-                    src: StatePartIndex<BigSlots>(80), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    dest: StatePartIndex<BigSlots>(89), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    src: StatePartIndex<BigSlots>(88), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                 },
-                // at: module-XXXXXXXXXX.rs:16:1
+                // at: module-XXXXXXXXXX.rs:18:1
                 4: Copy {
                     dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
-                    src: StatePartIndex<BigSlots>(81), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    src: StatePartIndex<BigSlots>(89), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 5: SliceInt {
-                    dest: StatePartIndex<BigSlots>(69), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(77), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
                     start: 2,
                     len: 2,
                 },
                 6: CastToSInt {
-                    dest: StatePartIndex<BigSlots>(70), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(69), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(78), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(77), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     dest_width: 2,
                 },
                 7: Const {
-                    dest: StatePartIndex<BigSlots>(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(70), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
                     value: 0x2,
                 },
                 8: SliceInt {
-                    dest: StatePartIndex<BigSlots>(49), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(57), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
                     start: 1,
                     len: 1,
                 },
                 9: Copy {
-                    dest: StatePartIndex<BigSlots>(50), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(49), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(58), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(57), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 10: Copy {
-                    dest: StatePartIndex<BigSlots>(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(50), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(76), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(58), // (0x1) SlotDebugData { name: "", ty: Bool },
                 },
                 11: SliceInt {
-                    dest: StatePartIndex<BigSlots>(46), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(54), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
                     start: 0,
                     len: 1,
                 },
                 12: Copy {
-                    dest: StatePartIndex<BigSlots>(47), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(46), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(55), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(54), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 13: Copy {
-                    dest: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(47), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(56), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(55), // (0x1) SlotDebugData { name: "", ty: Bool },
                 },
                 14: Copy {
-                    dest: StatePartIndex<BigSlots>(44), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(56), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 15: Copy {
-                    dest: StatePartIndex<BigSlots>(45), // (0x1) SlotDebugData { name: ".1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(50), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(53), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(58), // (0x1) SlotDebugData { name: "", ty: Bool },
                 },
                 16: Copy {
-                    dest: StatePartIndex<BigSlots>(66), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(74), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(56), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 17: Copy {
-                    dest: StatePartIndex<BigSlots>(67), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(75), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(76), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 18: Copy {
-                    dest: StatePartIndex<BigSlots>(63), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(66), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(71), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(74), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
                 },
                 19: Copy {
-                    dest: StatePartIndex<BigSlots>(64), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(67), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(72), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(75), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
                 },
                 20: Copy {
-                    dest: StatePartIndex<BigSlots>(65), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(70), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(73), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(78), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
                 },
                 21: Copy {
-                    dest: StatePartIndex<BigSlots>(58), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(66), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(70), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 22: Copy {
-                    dest: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(63), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(67), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(71), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
                 },
                 23: Copy {
-                    dest: StatePartIndex<BigSlots>(60), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(64), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(68), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(72), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
                 },
                 24: Copy {
-                    dest: StatePartIndex<BigSlots>(61), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(65), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(69), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(73), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
                 },
                 25: Shl {
-                    dest: StatePartIndex<BigSlots>(71), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(60), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(79), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(68), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
                     rhs: 1,
                 },
                 26: Or {
-                    dest: StatePartIndex<BigSlots>(72), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(71), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(80), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(67), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(79), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 27: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(73), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(61), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(81), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(69), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
                     dest_width: 2,
                 },
                 28: Shl {
-                    dest: StatePartIndex<BigSlots>(74), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(73), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(82), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(81), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     rhs: 2,
                 },
                 29: Or {
-                    dest: StatePartIndex<BigSlots>(75), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(72), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(74), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(83), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(80), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(82), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 30: Shl {
-                    dest: StatePartIndex<BigSlots>(76), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
-                    lhs: StatePartIndex<BigSlots>(75), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(84), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(83), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
                     rhs: 2,
                 },
                 31: Or {
-                    dest: StatePartIndex<BigSlots>(77), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
-                    lhs: StatePartIndex<BigSlots>(58), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(76), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
+                    dest: StatePartIndex<BigSlots>(85), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(66), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(84), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
                 },
                 32: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(78), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
-                    src: StatePartIndex<BigSlots>(77), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    dest: StatePartIndex<BigSlots>(86), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(85), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
                     dest_width: 6,
                 },
                 33: Copy {
-                    dest: StatePartIndex<BigSlots>(79), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(78), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    dest: StatePartIndex<BigSlots>(87), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(86), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
                 },
                 34: Const {
-                    dest: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(47), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
                     value: 0x1,
                 },
                 35: CmpEq {
-                    dest: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<BigSlots>(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(47), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 36: Copy {
-                    dest: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(49), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(47), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 37: Copy {
-                    dest: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(44), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(50), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(52), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
                 },
                 38: Copy {
-                    dest: StatePartIndex<BigSlots>(43), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(45), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(53), // (0x1) SlotDebugData { name: ".1", ty: Bool },
                 },
                 39: Copy {
-                    dest: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(43), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
                 },
                 40: Shl {
-                    dest: StatePartIndex<BigSlots>(52), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(60), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 1,
                 },
                 41: Or {
-                    dest: StatePartIndex<BigSlots>(53), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(52), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(50), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(60), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 42: Shl {
-                    dest: StatePartIndex<BigSlots>(54), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(53), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(62), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     rhs: 2,
                 },
                 43: Or {
-                    dest: StatePartIndex<BigSlots>(55), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(54), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(63), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(49), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(62), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 44: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(56), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
-                    src: StatePartIndex<BigSlots>(55), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(64), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(63), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
                     dest_width: 6,
                 },
                 45: Copy {
-                    dest: StatePartIndex<BigSlots>(57), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(56), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
+                    dest: StatePartIndex<BigSlots>(65), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(64), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
                 },
                 46: Const {
-                    dest: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     value: 0x0,
                 },
                 47: CmpEq {
-                    dest: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Bool },
                     lhs: StatePartIndex<BigSlots>(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 48: Copy {
-                    dest: StatePartIndex<BigSlots>(21), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
-                    src: StatePartIndex<BigSlots>(15), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    dest: StatePartIndex<BigSlots>(29), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 49: SliceInt {
-                    dest: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(21), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    dest: StatePartIndex<BigSlots>(30), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(29), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
                     start: 2,
                     len: 2,
                 },
                 50: SliceInt {
-                    dest: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(30), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     start: 0,
                     len: 1,
                 },
                 51: SliceInt {
-                    dest: StatePartIndex<BigSlots>(24), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(32), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(30), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     start: 1,
                     len: 1,
                 },
                 52: Copy {
-                    dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(24), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(32), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 53: Copy {
-                    dest: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(31), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 54: Copy {
-                    dest: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: ".1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: Bool },
                 },
                 55: Copy {
-                    dest: StatePartIndex<BigSlots>(83), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                    dest: StatePartIndex<BigSlots>(91), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: ".1", ty: Bool },
                 },
                 56: Shl {
-                    dest: StatePartIndex<BigSlots>(84), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(83), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    rhs: 1,
-                },
-                57: Or {
-                    dest: StatePartIndex<BigSlots>(85), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(84), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                58: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(86), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(85), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    dest_width: 4,
-                },
-                59: Copy {
-                    dest: StatePartIndex<BigSlots>(87), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(90), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                60: Copy {
-                    dest: StatePartIndex<BigSlots>(88), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                },
-                61: Copy {
-                    dest: StatePartIndex<BigSlots>(89), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: ".1", ty: Bool },
-                },
-                62: Copy {
-                    dest: StatePartIndex<BigSlots>(91), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(89), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
-                },
-                63: Shl {
                     dest: StatePartIndex<BigSlots>(92), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
                     lhs: StatePartIndex<BigSlots>(91), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 1,
                 },
-                64: Or {
+                57: Or {
                     dest: StatePartIndex<BigSlots>(93), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(88), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    lhs: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
                     rhs: StatePartIndex<BigSlots>(92), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
                 },
+                58: CastToUInt {
+                    dest: StatePartIndex<BigSlots>(94), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(93), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest_width: 4,
+                },
+                59: Copy {
+                    dest: StatePartIndex<BigSlots>(95), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(98), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                60: Copy {
+                    dest: StatePartIndex<BigSlots>(96), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                },
+                61: Copy {
+                    dest: StatePartIndex<BigSlots>(97), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                },
+                62: Copy {
+                    dest: StatePartIndex<BigSlots>(99), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(97), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
+                },
+                63: Shl {
+                    dest: StatePartIndex<BigSlots>(100), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(99), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    rhs: 1,
+                },
+                64: Or {
+                    dest: StatePartIndex<BigSlots>(101), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(96), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(100), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                },
                 65: Shl {
-                    dest: StatePartIndex<BigSlots>(94), // (0x6) SlotDebugData { name: "", ty: UInt<3> },
-                    lhs: StatePartIndex<BigSlots>(93), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(102), // (0x6) SlotDebugData { name: "", ty: UInt<3> },
+                    lhs: StatePartIndex<BigSlots>(101), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     rhs: 1,
                 },
                 66: Or {
-                    dest: StatePartIndex<BigSlots>(95), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
-                    lhs: StatePartIndex<BigSlots>(87), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(94), // (0x6) SlotDebugData { name: "", ty: UInt<3> },
+                    dest: StatePartIndex<BigSlots>(103), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
+                    lhs: StatePartIndex<BigSlots>(95), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(102), // (0x6) SlotDebugData { name: "", ty: UInt<3> },
                 },
                 67: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(96), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
-                    src: StatePartIndex<BigSlots>(95), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
+                    dest: StatePartIndex<BigSlots>(104), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(103), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
                     dest_width: 3,
                 },
                 68: Copy {
-                    dest: StatePartIndex<BigSlots>(97), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
-                    src: StatePartIndex<BigSlots>(96), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
+                    dest: StatePartIndex<BigSlots>(105), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    src: StatePartIndex<BigSlots>(104), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
                 },
                 69: SliceInt {
-                    dest: StatePartIndex<BigSlots>(31), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(21), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                    dest: StatePartIndex<BigSlots>(39), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(29), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
                     start: 2,
                     len: 4,
                 },
                 70: SliceInt {
-                    dest: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(31), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(40), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(39), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
                     start: 0,
                     len: 2,
                 },
                 71: SliceInt {
-                    dest: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(40), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     start: 0,
                     len: 1,
                 },
                 72: SliceInt {
-                    dest: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(40), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     start: 1,
                     len: 1,
                 },
                 73: Copy {
-                    dest: StatePartIndex<BigSlots>(29), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 74: Copy {
-                    dest: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(38), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
                 },
                 75: SliceInt {
-                    dest: StatePartIndex<BigSlots>(35), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(31), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(43), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(39), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
                     start: 2,
                     len: 2,
                 },
                 76: CastToSInt {
-                    dest: StatePartIndex<BigSlots>(36), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(35), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(44), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(43), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     dest_width: 2,
                 },
                 77: Copy {
-                    dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(29), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(37), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
                 },
                 78: Copy {
-                    dest: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(38), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
                 },
                 79: Copy {
-                    dest: StatePartIndex<BigSlots>(28), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(36), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(36), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(44), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
                 },
                 80: Shl {
-                    dest: StatePartIndex<BigSlots>(98), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    dest: StatePartIndex<BigSlots>(106), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
                     rhs: 1,
                 },
                 81: Or {
-                    dest: StatePartIndex<BigSlots>(99), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(98), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(107), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(106), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 82: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(100), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(28), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                    dest: StatePartIndex<BigSlots>(108), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(36), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
                     dest_width: 2,
                 },
                 83: Shl {
-                    dest: StatePartIndex<BigSlots>(101), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(100), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    dest: StatePartIndex<BigSlots>(109), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(108), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
                     rhs: 2,
                 },
                 84: Or {
-                    dest: StatePartIndex<BigSlots>(102), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(99), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(101), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                    dest: StatePartIndex<BigSlots>(110), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(107), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(109), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
                 },
-                // at: module-XXXXXXXXXX.rs:9:1
+                // at: module-XXXXXXXXXX.rs:11:1
                 85: AndBigWithSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(5), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    lhs: StatePartIndex<BigSlots>(15), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    dest: StatePartIndex<SmallSlots>(6), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    lhs: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                     rhs: 0x3,
                 },
-                // at: module-XXXXXXXXXX.rs:17:1
+                // at: module-XXXXXXXXXX.rs:19:1
                 86: BranchIfSmallNeImmediate {
                     target: 89,
-                    lhs: StatePartIndex<SmallSlots>(5), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    lhs: StatePartIndex<SmallSlots>(6), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
                     rhs: 0x0,
                 },
-                // at: module-XXXXXXXXXX.rs:18:1
+                // at: module-XXXXXXXXXX.rs:20:1
                 87: Copy {
                     dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                // at: module-XXXXXXXXXX.rs:19:1
-                88: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(82), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:17:1
-                89: BranchIfSmallNeImmediate {
-                    target: 93,
-                    lhs: StatePartIndex<SmallSlots>(5), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    rhs: 0x1,
-                },
-                // at: module-XXXXXXXXXX.rs:20:1
-                90: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:21:1
-                91: Copy {
+                88: Copy {
                     dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(86), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(90), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:19:1
+                89: BranchIfSmallNeImmediate {
+                    target: 93,
+                    lhs: StatePartIndex<SmallSlots>(6), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:22:1
-                92: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
-                    src: StatePartIndex<BigSlots>(97), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
-                },
-                // at: module-XXXXXXXXXX.rs:17:1
-                93: BranchIfSmallNeImmediate {
-                    target: 96,
-                    lhs: StatePartIndex<SmallSlots>(5), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    rhs: 0x2,
+                90: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(47), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:23:1
-                94: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                91: Copy {
+                    dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(94), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:24:1
+                92: Copy {
+                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    src: StatePartIndex<BigSlots>(105), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                },
+                // at: module-XXXXXXXXXX.rs:19:1
+                93: BranchIfSmallNeImmediate {
+                    target: 96,
+                    lhs: StatePartIndex<SmallSlots>(6), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 0x2,
+                },
+                // at: module-XXXXXXXXXX.rs:25:1
+                94: Copy {
+                    dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(70), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:26:1
                 95: Copy {
                     dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(102), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(110), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
                 },
-                // at: module-XXXXXXXXXX.rs:9:1
+                // at: module-XXXXXXXXXX.rs:11:1
                 96: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
                 97: Const {
-                    dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
+                    dest: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                     value: 0x0,
                 },
                 98: Copy {
-                    dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
+                    dest: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
                 },
-                // at: module-XXXXXXXXXX.rs:10:1
+                // at: module-XXXXXXXXXX.rs:12:1
                 99: BranchIfZero {
                     target: 107,
                     value: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool },
                 },
-                // at: module-XXXXXXXXXX.rs:11:1
+                // at: module-XXXXXXXXXX.rs:13:1
                 100: BranchIfZero {
                     target: 102,
-                    value: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:12:1
-                101: Copy {
-                    dest: StatePartIndex<BigSlots>(16), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                },
-                // at: module-XXXXXXXXXX.rs:11:1
-                102: BranchIfNonZero {
-                    target: 107,
-                    value: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:13:1
-                103: BranchIfZero {
-                    target: 105,
-                    value: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:14:1
-                104: Copy {
-                    dest: StatePartIndex<BigSlots>(16), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(57), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                101: Copy {
+                    dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
                 // at: module-XXXXXXXXXX.rs:13:1
-                105: BranchIfNonZero {
+                102: BranchIfNonZero {
                     target: 107,
-                    value: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:15:1
-                106: Copy {
-                    dest: StatePartIndex<BigSlots>(16), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(79), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                103: BranchIfZero {
+                    target: 105,
+                    value: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
-                // at: module-XXXXXXXXXX.rs:9:1
+                // at: module-XXXXXXXXXX.rs:16:1
+                104: Copy {
+                    dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(65), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                // at: module-XXXXXXXXXX.rs:15:1
+                105: BranchIfNonZero {
+                    target: 107,
+                    value: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:17:1
+                106: Copy {
+                    dest: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(87), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
                 107: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock },
                 },
                 108: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                109: Copy {
+                    dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                109: Copy {
+                110: Copy {
+                    dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    src: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                },
+                111: SliceInt {
+                    dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
+                    start: 1,
+                    len: 2,
+                },
+                112: SliceInt {
+                    dest: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 0,
+                    len: 1,
+                },
+                113: SliceInt {
+                    dest: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                    start: 1,
+                    len: 1,
+                },
+                114: Copy {
+                    dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                115: Copy {
+                    dest: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
+                },
+                116: Copy {
+                    dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                117: AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
+                    lhs: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
+                    rhs: 0x1,
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                118: Copy {
                     dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                 },
-                110: SliceInt {
+                119: SliceInt {
                     dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
                     start: 1,
                     len: 2,
                 },
-                111: SliceInt {
+                120: SliceInt {
                     dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     start: 0,
                     len: 1,
                 },
-                112: SliceInt {
+                121: SliceInt {
                     dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
                     start: 1,
                     len: 1,
                 },
-                113: Copy {
+                122: Copy {
                     dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: Bool },
                     src: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                114: Copy {
+                123: Copy {
                     dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> },
                     src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
                 },
-                115: Copy {
+                124: Copy {
                     dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: ".1", ty: Bool },
                     src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
-                116: AndBigWithSmallImmediate {
+                125: AndBigWithSmallImmediate {
                     dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
                     lhs: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
                     rhs: 0x1,
                 },
-                // at: module-XXXXXXXXXX.rs:9:1
-                117: BranchIfSmallZero {
-                    target: 122,
-                    value: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                // at: module-XXXXXXXXXX.rs:11:1
+                126: BranchIfSmallZero {
+                    target: 131,
+                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                118: BranchIfSmallNonZero {
-                    target: 121,
-                    value: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                127: BranchIfSmallNonZero {
+                    target: 130,
+                    value: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
                 },
-                119: Copy {
-                    dest: StatePartIndex<BigSlots>(15), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(16), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                128: Copy {
+                    dest: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
-                120: Branch {
-                    target: 122,
+                129: Branch {
+                    target: 131,
                 },
-                121: Copy {
-                    dest: StatePartIndex<BigSlots>(15), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                130: Copy {
+                    dest: StatePartIndex<BigSlots>(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
-                122: XorSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
+                131: XorSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(4), // (0x1 1) SlotDebugData { name: "", ty: Bool },
                     rhs: 0x1,
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                123: Return,
+                132: Return,
             ],
             ..
         },
-        pc: 123,
+        pc: 132,
         memory_write_log: [],
         memories: StatePart {
             value: [],
@@ -1095,6 +1183,7 @@ Simulation {
                 0,
                 0,
                 0,
+                0,
                 1,
                 0,
                 2,
@@ -1117,6 +1206,14 @@ Simulation {
                 0,
                 0,
                 0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
+                0,
                 62,
                 62,
                 0,
@@ -1266,9 +1363,23 @@ Simulation {
                     ..
                 },
             }.b_out,
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.b2_out,
         ],
         uninitialized_ios: {},
         io_targets: {
+            Instance {
+                name: <simulator>::enums,
+                instantiated: Module {
+                    name: enums,
+                    ..
+                },
+            }.b2_out,
             Instance {
                 name: <simulator>::enums,
                 instantiated: Module {
@@ -1476,23 +1587,22 @@ Simulation {
                 },
                 flow: Sink,
             },
-            TraceReg {
-                name: "the_reg",
+            TraceModuleIO {
+                name: "b2_out",
                 child: TraceEnumWithFields {
-                    name: "the_reg",
+                    name: "b2_out",
                     discriminant: TraceEnumDiscriminant {
                         location: TraceScalarId(10),
                         name: "$tag",
                         ty: Enum {
-                            A,
-                            B(Bundle {0: UInt<1>, 1: Bool}),
-                            C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                            HdlNone,
+                            HdlSome(Bundle {0: UInt<1>, 1: Bool}),
                         },
-                        flow: Duplex,
+                        flow: Sink,
                     },
                     non_empty_fields: [
                         TraceBundle {
-                            name: "B",
+                            name: "HdlSome",
                             fields: [
                                 TraceUInt {
                                     location: TraceScalarId(11),
@@ -1514,6 +1624,57 @@ Simulation {
                             },
                             flow: Source,
                         },
+                    ],
+                    ty: Enum {
+                        HdlNone,
+                        HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                    },
+                    flow: Sink,
+                },
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                },
+                flow: Sink,
+            },
+            TraceReg {
+                name: "the_reg",
+                child: TraceEnumWithFields {
+                    name: "the_reg",
+                    discriminant: TraceEnumDiscriminant {
+                        location: TraceScalarId(13),
+                        name: "$tag",
+                        ty: Enum {
+                            A,
+                            B(Bundle {0: UInt<1>, 1: Bool}),
+                            C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
+                        },
+                        flow: Duplex,
+                    },
+                    non_empty_fields: [
+                        TraceBundle {
+                            name: "B",
+                            fields: [
+                                TraceUInt {
+                                    location: TraceScalarId(14),
+                                    name: "0",
+                                    ty: UInt<1>,
+                                    flow: Source,
+                                },
+                                TraceBool {
+                                    location: TraceScalarId(15),
+                                    name: "1",
+                                    flow: Source,
+                                },
+                            ],
+                            ty: Bundle {
+                                /* offset = 0 */
+                                0: UInt<1>,
+                                /* offset = 1 */
+                                1: Bool,
+                            },
+                            flow: Source,
+                        },
                         TraceBundle {
                             name: "C",
                             fields: [
@@ -1521,13 +1682,13 @@ Simulation {
                                     name: "a",
                                     elements: [
                                         TraceUInt {
-                                            location: TraceScalarId(13),
+                                            location: TraceScalarId(16),
                                             name: "[0]",
                                             ty: UInt<1>,
                                             flow: Source,
                                         },
                                         TraceUInt {
-                                            location: TraceScalarId(14),
+                                            location: TraceScalarId(17),
                                             name: "[1]",
                                             ty: UInt<1>,
                                             flow: Source,
@@ -1537,7 +1698,7 @@ Simulation {
                                     flow: Source,
                                 },
                                 TraceSInt {
-                                    location: TraceScalarId(15),
+                                    location: TraceScalarId(18),
                                     name: "b",
                                     ty: SInt<2>,
                                     flow: Source,
@@ -1660,7 +1821,36 @@ Simulation {
         SimTrace {
             id: TraceScalarId(10),
             kind: EnumDiscriminant {
-                index: StatePartIndex<SmallSlots>(5),
+                index: StatePartIndex<SmallSlots>(1),
+                ty: Enum {
+                    HdlNone,
+                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
+                },
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(11),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(16),
+                ty: UInt<1>,
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(12),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(17),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(13),
+            kind: EnumDiscriminant {
+                index: StatePartIndex<SmallSlots>(6),
                 ty: Enum {
                     A,
                     B(Bundle {0: UInt<1>, 1: Bool}),
@@ -1670,32 +1860,6 @@ Simulation {
             state: 0x2,
             last_state: 0x2,
         },
-        SimTrace {
-            id: TraceScalarId(11),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(19),
-                ty: UInt<1>,
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(12),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(20),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(13),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(26),
-                ty: UInt<1>,
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
         SimTrace {
             id: TraceScalarId(14),
             kind: BigUInt {
@@ -1707,8 +1871,34 @@ Simulation {
         },
         SimTrace {
             id: TraceScalarId(15),
-            kind: BigSInt {
+            kind: BigBool {
                 index: StatePartIndex<BigSlots>(28),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(16),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(34),
+                ty: UInt<1>,
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(17),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(35),
+                ty: UInt<1>,
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(18),
+            kind: BigSInt {
+                index: StatePartIndex<BigSlots>(36),
                 ty: SInt<2>,
             },
             state: 0x3,
@@ -1727,7 +1917,7 @@ Simulation {
     ],
     instant: 16 μs,
     clocks_triggered: [
-        StatePartIndex<SmallSlots>(2),
+        StatePartIndex<SmallSlots>(3),
     ],
     ..
 }
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/enums.vcd b/crates/fayalite/tests/sim/expected/enums.vcd
index 07cbd32..aff867b 100644
--- a/crates/fayalite/tests/sim/expected/enums.vcd
+++ b/crates/fayalite/tests/sim/expected/enums.vcd
@@ -16,18 +16,25 @@ $var wire 1 ) \0 $end
 $var wire 1 * \1 $end
 $upscope $end
 $upscope $end
-$scope struct the_reg $end
+$scope struct b2_out $end
 $var string 1 + \$tag $end
+$scope struct HdlSome $end
+$var wire 1 , \0 $end
+$var wire 1 - \1 $end
+$upscope $end
+$upscope $end
+$scope struct the_reg $end
+$var string 1 . \$tag $end
 $scope struct B $end
-$var reg 1 , \0 $end
-$var reg 1 - \1 $end
+$var reg 1 / \0 $end
+$var reg 1 0 \1 $end
 $upscope $end
 $scope struct C $end
 $scope struct a $end
-$var reg 1 . \[0] $end
-$var reg 1 / \[1] $end
+$var reg 1 1 \[0] $end
+$var reg 1 2 \[1] $end
 $upscope $end
-$var reg 2 0 b $end
+$var reg 2 3 b $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -43,12 +50,15 @@ b0 '
 sHdlNone\x20(0) (
 0)
 0*
-sA\x20(0) +
+sHdlNone\x20(0) +
 0,
 0-
-0.
+sA\x20(0) .
 0/
-b0 0
+00
+01
+02
+b0 3
 $end
 #1000000
 1!
@@ -66,7 +76,8 @@ b1 $
 1!
 b1 &
 sHdlSome\x20(1) (
-sB\x20(1) +
+sHdlSome\x20(1) +
+sB\x20(1) .
 #6000000
 0#
 b0 $
@@ -85,8 +96,10 @@ b11 '
 1*
 1,
 1-
-1.
 1/
+10
+11
+12
 #10000000
 0!
 #11000000
@@ -101,8 +114,11 @@ b1111 '
 sHdlNone\x20(0) (
 0)
 0*
-sC\x20(2) +
-b11 0
+sHdlNone\x20(0) +
+0,
+0-
+sC\x20(2) .
+b11 3
 #14000000
 0!
 #15000000

From 62058dc141b2673d502295730b29abf1351b3ca1 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 1 Apr 2025 22:22:54 -0700
Subject: [PATCH 174/190] fix cargo doc warnings -- convert urls to auto links

---
 crates/fayalite/src/util/prefix_sum.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/crates/fayalite/src/util/prefix_sum.rs b/crates/fayalite/src/util/prefix_sum.rs
index 758d89c..98e6d95 100644
--- a/crates/fayalite/src/util/prefix_sum.rs
+++ b/crates/fayalite/src/util/prefix_sum.rs
@@ -210,10 +210,10 @@ impl PrefixSumOp {
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
 pub enum PrefixSumAlgorithm {
     /// Uses the algorithm from:
-    /// https://en.wikipedia.org/wiki/Prefix_sum#Algorithm_1:_Shorter_span,_more_parallel
+    /// <https://en.wikipedia.org/wiki/Prefix_sum#Algorithm_1:_Shorter_span,_more_parallel>
     LowLatency,
     /// Uses the algorithm from:
-    /// https://en.wikipedia.org/wiki/Prefix_sum#Algorithm_2:_Work-efficient
+    /// <https://en.wikipedia.org/wiki/Prefix_sum#Algorithm_2:_Work-efficient>
     WorkEfficient,
 }
 

From 6929352be77883e3ce724bf3271f1d57d0b6331f Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 3 Apr 2025 15:59:03 -0700
Subject: [PATCH 175/190] re-export `bitvec` and add types useful for
 simulation to the prelude

---
 crates/fayalite-proc-macros-impl/src/hdl_bundle.rs | 12 ++++++------
 crates/fayalite-proc-macros-impl/src/hdl_enum.rs   |  6 +++---
 crates/fayalite/src/lib.rs                         |  4 ++--
 crates/fayalite/src/prelude.rs                     |  8 +++++++-
 crates/fayalite/tests/sim.rs                       |  3 +--
 5 files changed, 19 insertions(+), 14 deletions(-)

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
index 8e49ac4..5d13d39 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
@@ -746,7 +746,7 @@ impl ToTokens for ParsedBundle {
                 }
                 fn sim_value_from_bits(
                     &self,
-                    bits: &::fayalite::__bitvec::slice::BitSlice,
+                    bits: &::fayalite::bitvec::slice::BitSlice,
                 ) -> <Self as ::fayalite::ty::Type>::SimValue {
                     #![allow(unused_mut, unused_variables)]
                     let mut v = ::fayalite::bundle::BundleSimValueFromBits::new(*self, bits);
@@ -757,7 +757,7 @@ impl ToTokens for ParsedBundle {
                 fn sim_value_clone_from_bits(
                     &self,
                     value: &mut <Self as ::fayalite::ty::Type>::SimValue,
-                    bits: &::fayalite::__bitvec::slice::BitSlice,
+                    bits: &::fayalite::bitvec::slice::BitSlice,
                 ) {
                     #![allow(unused_mut, unused_variables)]
                     let mut v = ::fayalite::bundle::BundleSimValueFromBits::new(*self, bits);
@@ -766,7 +766,7 @@ impl ToTokens for ParsedBundle {
                 fn sim_value_to_bits(
                     &self,
                     value: &<Self as ::fayalite::ty::Type>::SimValue,
-                    bits: &mut ::fayalite::__bitvec::slice::BitSlice,
+                    bits: &mut ::fayalite::bitvec::slice::BitSlice,
                 ) {
                     #![allow(unused_mut, unused_variables)]
                     let mut v = ::fayalite::bundle::BundleSimValueToBits::new(*self, bits);
@@ -895,7 +895,7 @@ impl ToTokens for ParsedBundle {
                 }
                 fn sim_value_from_bits(
                     &self,
-                    bits: &::fayalite::__bitvec::slice::BitSlice,
+                    bits: &::fayalite::bitvec::slice::BitSlice,
                 ) -> <Self as ::fayalite::ty::Type>::SimValue {
                     #![allow(unused_mut, unused_variables)]
                     let mut v = ::fayalite::bundle::BundleSimValueFromBits::new(*self, bits);
@@ -906,7 +906,7 @@ impl ToTokens for ParsedBundle {
                 fn sim_value_clone_from_bits(
                     &self,
                     value: &mut <Self as ::fayalite::ty::Type>::SimValue,
-                    bits: &::fayalite::__bitvec::slice::BitSlice,
+                    bits: &::fayalite::bitvec::slice::BitSlice,
                 ) {
                     #![allow(unused_mut, unused_variables)]
                     let mut v = ::fayalite::bundle::BundleSimValueFromBits::new(*self, bits);
@@ -915,7 +915,7 @@ impl ToTokens for ParsedBundle {
                 fn sim_value_to_bits(
                     &self,
                     value: &<Self as ::fayalite::ty::Type>::SimValue,
-                    bits: &mut ::fayalite::__bitvec::slice::BitSlice,
+                    bits: &mut ::fayalite::bitvec::slice::BitSlice,
                 ) {
                     #![allow(unused_mut, unused_variables)]
                     let mut v = ::fayalite::bundle::BundleSimValueToBits::new(*self, bits);
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
index 6fb2a56..5437410 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
@@ -880,7 +880,7 @@ impl ToTokens for ParsedEnum {
                 }
                 fn sim_value_from_bits(
                     &self,
-                    bits: &::fayalite::__bitvec::slice::BitSlice,
+                    bits: &::fayalite::bitvec::slice::BitSlice,
                 ) -> <Self as ::fayalite::ty::Type>::SimValue {
                     let v = ::fayalite::enum_::EnumSimValueFromBits::new(*self, bits);
                     match v.discriminant() {
@@ -890,7 +890,7 @@ impl ToTokens for ParsedEnum {
                 fn sim_value_clone_from_bits(
                     &self,
                     value: &mut <Self as ::fayalite::ty::Type>::SimValue,
-                    bits: &::fayalite::__bitvec::slice::BitSlice,
+                    bits: &::fayalite::bitvec::slice::BitSlice,
                 ) {
                     let v = ::fayalite::enum_::EnumSimValueFromBits::new(*self, bits);
                     match v.discriminant() {
@@ -900,7 +900,7 @@ impl ToTokens for ParsedEnum {
                 fn sim_value_to_bits(
                     &self,
                     value: &<Self as ::fayalite::ty::Type>::SimValue,
-                    bits: &mut ::fayalite::__bitvec::slice::BitSlice,
+                    bits: &mut ::fayalite::bitvec::slice::BitSlice,
                 ) {
                     let v = ::fayalite::enum_::EnumSimValueToBits::new(*self, bits);
                     match value {
diff --git a/crates/fayalite/src/lib.rs b/crates/fayalite/src/lib.rs
index 0843589..932464b 100644
--- a/crates/fayalite/src/lib.rs
+++ b/crates/fayalite/src/lib.rs
@@ -8,8 +8,6 @@
 
 extern crate self as fayalite;
 
-#[doc(hidden)]
-pub use bitvec as __bitvec;
 #[doc(hidden)]
 pub use std as __std;
 
@@ -78,6 +76,8 @@ pub use fayalite_proc_macros::hdl_module;
 #[doc(inline)]
 pub use fayalite_proc_macros::hdl;
 
+pub use bitvec;
+
 /// struct used as a placeholder when applying defaults
 #[derive(Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Hash, Default)]
 pub struct __;
diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs
index 39fa143..519210f 100644
--- a/crates/fayalite/src/prelude.rs
+++ b/crates/fayalite/src/prelude.rs
@@ -20,7 +20,7 @@ pub use crate::{
         hdl_cover_with_enable, MakeFormalExpr,
     },
     hdl, hdl_module,
-    int::{Bool, DynSize, KnownSize, SInt, SIntType, Size, UInt, UIntType},
+    int::{Bool, DynSize, KnownSize, SInt, SIntType, SIntValue, Size, UInt, UIntType, UIntValue},
     memory::{Mem, MemBuilder, ReadUnderWrite},
     module::{
         annotate, connect, connect_any, incomplete_wire, instance, memory, memory_array,
@@ -29,9 +29,15 @@ pub use crate::{
     phantom_const::PhantomConst,
     reg::Reg,
     reset::{AsyncReset, Reset, SyncReset, ToAsyncReset, ToReset, ToSyncReset},
+    sim::{
+        time::{SimDuration, SimInstant},
+        value::{SimValue, ToSimValue, ToSimValueWithType},
+        ExternModuleSimulationState, Simulation,
+    },
     source_location::SourceLocation,
     ty::{AsMask, CanonicalType, Type},
     util::{ConstUsize, GenericConstUsize},
     wire::Wire,
     __,
 };
+pub use bitvec::{slice::BitSlice, vec::BitVec};
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index 6433844..655a497 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -2,12 +2,11 @@
 // See Notices.txt for copyright information
 
 use fayalite::{
-    int::UIntValue,
     memory::{ReadStruct, ReadWriteStruct, WriteStruct},
     module::{instance_with_loc, reg_builder_with_loc},
     prelude::*,
     reset::ResetType,
-    sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
+    sim::vcd::VcdWriterDecls,
     util::RcWriter,
 };
 use std::num::NonZeroUsize;

From 57aae7b7fba63d3376003549e13b93fc6fe2adda Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 4 Apr 2025 01:04:26 -0700
Subject: [PATCH 176/190] implement [de]serializing `BaseType`s, `SimValue`s,
 and support PhantomConst<T> in #[hdl] struct S<T>

---
 .../src/hdl_bundle.rs                         |  17 +
 .../fayalite-proc-macros-impl/src/hdl_enum.rs |   9 +
 crates/fayalite/src/array.rs                  |  57 +-
 crates/fayalite/src/bundle.rs                 |   3 +-
 crates/fayalite/src/enum_.rs                  |   3 +-
 crates/fayalite/src/int.rs                    | 527 +++++++++++++++++-
 crates/fayalite/src/phantom_const.rs          |  79 ++-
 crates/fayalite/src/sim/value.rs              |  35 ++
 crates/fayalite/src/ty.rs                     |  76 ++-
 crates/fayalite/src/ty/serde_impls.rs         | 130 +++++
 crates/fayalite/src/util/const_bool.rs        |  42 +-
 crates/fayalite/src/util/const_usize.rs       |  42 +-
 crates/fayalite/tests/hdl_types.rs            |   6 +
 13 files changed, 991 insertions(+), 35 deletions(-)
 create mode 100644 crates/fayalite/src/ty/serde_impls.rs

diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
index 5d13d39..7441cb3 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs
@@ -1124,6 +1124,14 @@ impl ToTokens for ParsedBundle {
                 }
             }));
             quote_spanned! {span=>
+                #[automatically_derived]
+                impl #static_impl_generics ::fayalite::__std::default::Default for #mask_type_ident #static_type_generics
+                #static_where_clause
+                {
+                    fn default() -> Self {
+                        <Self as ::fayalite::ty::StaticType>::TYPE
+                    }
+                }
                 #[automatically_derived]
                 impl #static_impl_generics ::fayalite::ty::StaticType for #mask_type_ident #static_type_generics
                 #static_where_clause
@@ -1146,6 +1154,15 @@ impl ToTokens for ParsedBundle {
                     };
                 }
                 #[automatically_derived]
+                impl #static_impl_generics ::fayalite::__std::default::Default
+                for #target #static_type_generics
+                #static_where_clause
+                {
+                    fn default() -> Self {
+                        <Self as ::fayalite::ty::StaticType>::TYPE
+                    }
+                }
+                #[automatically_derived]
                 impl #static_impl_generics ::fayalite::ty::StaticType for #target #static_type_generics
                 #static_where_clause
                 {
diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
index 5437410..e072135 100644
--- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
+++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs
@@ -995,6 +995,15 @@ impl ToTokens for ParsedEnum {
                     }
                 }));
             quote_spanned! {span=>
+                #[automatically_derived]
+                impl #static_impl_generics ::fayalite::__std::default::Default
+                for #target #static_type_generics
+                #static_where_clause
+                {
+                    fn default() -> Self {
+                        <Self as ::fayalite::ty::StaticType>::TYPE
+                    }
+                }
                 #[automatically_derived]
                 impl #static_impl_generics ::fayalite::ty::StaticType
                 for #target #static_type_generics
diff --git a/crates/fayalite/src/array.rs b/crates/fayalite/src/array.rs
index a2df6cf..6d9b043 100644
--- a/crates/fayalite/src/array.rs
+++ b/crates/fayalite/src/array.rs
@@ -1,8 +1,6 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 
-use bitvec::slice::BitSlice;
-
 use crate::{
     expr::{
         ops::{ArrayLiteral, ExprFromIterator, ExprIntoIterator, ExprPartialEq},
@@ -14,10 +12,13 @@ use crate::{
     sim::value::{SimValue, SimValuePartialEq},
     source_location::SourceLocation,
     ty::{
-        CanonicalType, MatchVariantWithoutScope, StaticType, Type, TypeProperties, TypeWithDeref,
+        serde_impls::SerdeCanonicalType, CanonicalType, MatchVariantWithoutScope, StaticType, Type,
+        TypeProperties, TypeWithDeref,
     },
     util::ConstUsize,
 };
+use bitvec::slice::BitSlice;
+use serde::{de::Error, Deserialize, Deserializer, Serialize, Serializer};
 use std::{iter::FusedIterator, ops::Index};
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash)]
@@ -97,6 +98,12 @@ impl<T: Type, Len: KnownSize + Size<SizeType = Len>> ArrayType<T, Len> {
     }
 }
 
+impl<T: StaticType, Len: KnownSize> Default for ArrayType<T, Len> {
+    fn default() -> Self {
+        Self::TYPE
+    }
+}
+
 impl<T: StaticType, Len: KnownSize> StaticType for ArrayType<T, Len> {
     const TYPE: Self = Self {
         element: LazyInterned::new_lazy(&|| T::TYPE.intern_sized()),
@@ -226,6 +233,50 @@ impl<T: Type, Len: Size> Type for ArrayType<T, Len> {
     }
 }
 
+impl<T: Type + Serialize, Len: Size> Serialize for ArrayType<T, Len> {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        SerdeCanonicalType::<T>::Array {
+            element: self.element(),
+            len: self.len(),
+        }
+        .serialize(serializer)
+    }
+}
+
+impl<'de, T: Type + Deserialize<'de>, Len: Size> Deserialize<'de> for ArrayType<T, Len> {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: Deserializer<'de>,
+    {
+        let name = |len| -> String {
+            if let Some(len) = len {
+                format!("an Array<_, {len}>")
+            } else {
+                "an Array<_>".to_string()
+            }
+        };
+        match SerdeCanonicalType::<T>::deserialize(deserializer)? {
+            SerdeCanonicalType::Array { element, len } => {
+                if let Some(len) = Len::try_from_usize(len) {
+                    Ok(Self::new(element, len))
+                } else {
+                    Err(Error::invalid_value(
+                        serde::de::Unexpected::Other(&name(Some(len))),
+                        &&*name(Len::KNOWN_VALUE),
+                    ))
+                }
+            }
+            ty => Err(Error::invalid_value(
+                serde::de::Unexpected::Other(ty.as_serde_unexpected_str()),
+                &&*name(Len::KNOWN_VALUE),
+            )),
+        }
+    }
+}
+
 impl<T: Type, Len: Size> TypeWithDeref for ArrayType<T, Len> {
     fn expr_deref(this: &Expr<Self>) -> &Self::MatchVariant {
         let retval = Vec::from_iter(*this);
diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs
index 9279b57..0fd89f1 100644
--- a/crates/fayalite/src/bundle.rs
+++ b/crates/fayalite/src/bundle.rs
@@ -17,9 +17,10 @@ use crate::{
 };
 use bitvec::{slice::BitSlice, vec::BitVec};
 use hashbrown::HashMap;
+use serde::{Deserialize, Serialize};
 use std::{fmt, marker::PhantomData};
 
-#[derive(Copy, Clone, Debug, Hash, PartialEq, Eq)]
+#[derive(Copy, Clone, Debug, Hash, PartialEq, Eq, Serialize, Deserialize)]
 pub struct BundleField {
     pub name: Interned<str>,
     pub flipped: bool,
diff --git a/crates/fayalite/src/enum_.rs b/crates/fayalite/src/enum_.rs
index e37b7a5..6205855 100644
--- a/crates/fayalite/src/enum_.rs
+++ b/crates/fayalite/src/enum_.rs
@@ -22,9 +22,10 @@ use crate::{
 };
 use bitvec::{order::Lsb0, slice::BitSlice, view::BitView};
 use hashbrown::HashMap;
+use serde::{Deserialize, Serialize};
 use std::{convert::Infallible, fmt, iter::FusedIterator, sync::Arc};
 
-#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
 pub struct EnumVariant {
     pub name: Interned<str>,
     pub ty: Option<CanonicalType>,
diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index 373e150..13b8cf1 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -13,15 +13,20 @@ use crate::{
     ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
     util::{interned_bit, ConstBool, ConstUsize, GenericConstBool, GenericConstUsize},
 };
-use bitvec::{order::Lsb0, slice::BitSlice, vec::BitVec};
+use bitvec::{order::Lsb0, slice::BitSlice, vec::BitVec, view::BitView};
 use num_bigint::{BigInt, BigUint, Sign};
-use num_traits::{Signed, Zero};
+use num_traits::{One, Signed, Zero};
+use serde::{
+    de::{DeserializeOwned, Error, Visitor},
+    Deserialize, Deserializer, Serialize, Serializer,
+};
 use std::{
     borrow::{BorrowMut, Cow},
     fmt,
     marker::PhantomData,
     num::NonZero,
     ops::{Bound, Index, Not, Range, RangeBounds, RangeInclusive},
+    str::FromStr,
     sync::Arc,
 };
 
@@ -93,13 +98,31 @@ macro_rules! known_widths {
 known_widths!([2 2 2 2 2 2 2 2 2]);
 
 pub trait SizeType:
-    sealed::SizeTypeSealed + Copy + Ord + std::hash::Hash + std::fmt::Debug + Send + Sync + 'static
+    sealed::SizeTypeSealed
+    + Copy
+    + Ord
+    + std::hash::Hash
+    + std::fmt::Debug
+    + Send
+    + Sync
+    + 'static
+    + Serialize
+    + DeserializeOwned
 {
     type Size: Size<SizeType = Self>;
 }
 
 pub trait Size:
-    sealed::SizeSealed + Copy + Ord + std::hash::Hash + std::fmt::Debug + Send + Sync + 'static
+    sealed::SizeSealed
+    + Copy
+    + Ord
+    + std::hash::Hash
+    + std::fmt::Debug
+    + Send
+    + Sync
+    + 'static
+    + Serialize
+    + DeserializeOwned
 {
     type ArrayMatch<Element: Type>: AsRef<[Expr<Element>]>
         + AsMut<[Expr<Element>]>
@@ -191,6 +214,305 @@ impl<T: KnownSize> Size for T {
     }
 }
 
+#[derive(Clone, PartialEq, Eq, Debug)]
+pub enum ParseIntValueError {
+    Empty,
+    InvalidDigit,
+    MissingDigits,
+    InvalidRadix,
+    MissingType,
+    InvalidType,
+    TypeMismatch {
+        parsed_signed: bool,
+        parsed_width: usize,
+        expected_signed: bool,
+        expected_width: usize,
+    },
+    PosOverflow,
+    NegOverflow,
+    WidthOverflow,
+    MissingWidth,
+}
+
+impl std::error::Error for ParseIntValueError {}
+
+impl fmt::Display for ParseIntValueError {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.write_str(match self {
+            Self::Empty => "can't parse integer from empty string",
+            Self::InvalidDigit => "invalid digit",
+            Self::MissingDigits => "missing digits",
+            Self::InvalidRadix => "invalid radix",
+            Self::MissingType => "missing type",
+            Self::InvalidType => "invalid type",
+            Self::TypeMismatch {
+                parsed_signed,
+                parsed_width,
+                expected_signed,
+                expected_width,
+            } => {
+                return write!(
+                    f,
+                    "type mismatch: parsed type {parsed_signed_str}{parsed_width}, \
+                    expected type {expected_signed_str}{expected_width}",
+                    parsed_signed_str = if *parsed_signed { "i" } else { "u" },
+                    expected_signed_str = if *expected_signed { "i" } else { "u" },
+                );
+            }
+            Self::PosOverflow => "value too large to fit in type",
+            Self::NegOverflow => "value too small to fit in type",
+            Self::WidthOverflow => "width is too large",
+            Self::MissingWidth => "missing width",
+        })
+    }
+}
+
+fn parse_int_value(
+    s: &str,
+    type_is_signed: bool,
+    type_width: Option<usize>,
+    parse_type: bool,
+) -> Result<Arc<BitVec>, ParseIntValueError> {
+    if !parse_type && type_width.is_none() {
+        return Err(ParseIntValueError::MissingWidth);
+    }
+    let mut s = s.trim();
+    if s.is_empty() {
+        return Err(ParseIntValueError::Empty);
+    }
+    let negative = match s.bytes().next() {
+        Some(ch @ (b'+' | b'-')) => {
+            s = s[1..].trim_start();
+            ch == b'-'
+        }
+        _ => false,
+    };
+    let radix = match s.bytes().next() {
+        Some(b'0') => match s.bytes().nth(1) {
+            Some(b'x' | b'X') => {
+                s = &s[2..];
+                16
+            }
+            Some(b'b' | b'B') => {
+                s = &s[2..];
+                2
+            }
+            Some(b'o' | b'O') => {
+                s = &s[2..];
+                8
+            }
+            _ => 10,
+        },
+        Some(b'1'..=b'9') => 10,
+        _ => return Err(ParseIntValueError::InvalidDigit),
+    };
+    let mut any_digits = false;
+    let digits_end = s
+        .as_bytes()
+        .iter()
+        .position(|&ch| {
+            if ch == b'_' {
+                false
+            } else if (ch as char).to_digit(radix).is_some() {
+                any_digits = true;
+                false
+            } else {
+                true
+            }
+        })
+        .unwrap_or(s.len());
+    let digits = &s[..digits_end];
+    s = &s[digits_end..];
+    if !any_digits {
+        return Err(ParseIntValueError::MissingDigits);
+    }
+    let width = if parse_type {
+        const HDL_PREFIX: &[u8] = b"hdl_";
+        let mut missing_type = ParseIntValueError::MissingType;
+        if s.as_bytes()
+            .get(..HDL_PREFIX.len())
+            .is_some_and(|bytes| bytes.eq_ignore_ascii_case(HDL_PREFIX))
+        {
+            s = &s[HDL_PREFIX.len()..];
+            missing_type = ParseIntValueError::InvalidType;
+        }
+        let signed = match s.bytes().next() {
+            Some(b'u' | b'U') => false,
+            Some(b'i' | b'I') => true,
+            Some(_) => return Err(ParseIntValueError::InvalidType),
+            None => return Err(missing_type),
+        };
+        s = &s[1..];
+        let mut width = 0usize;
+        let mut any_digits = false;
+        for ch in s.bytes() {
+            let digit = (ch as char)
+                .to_digit(10)
+                .ok_or(ParseIntValueError::InvalidDigit)?;
+            any_digits = true;
+            width = width
+                .checked_mul(10)
+                .and_then(|v| v.checked_add(digit as usize))
+                .ok_or(ParseIntValueError::WidthOverflow)?;
+        }
+        if !any_digits {
+            return Err(ParseIntValueError::MissingDigits);
+        }
+        if width > <BitSlice>::MAX_BITS {
+            return Err(ParseIntValueError::WidthOverflow);
+        }
+        let expected_width = type_width.unwrap_or(width);
+        if type_is_signed != signed || expected_width != width {
+            let expected_width = type_width.unwrap_or(width);
+            return Err(ParseIntValueError::TypeMismatch {
+                parsed_signed: signed,
+                parsed_width: width,
+                expected_signed: type_is_signed,
+                expected_width,
+            });
+        }
+        width
+    } else {
+        if !s.is_empty() {
+            return Err(ParseIntValueError::InvalidDigit);
+        }
+        type_width.expect("checked earlier")
+    };
+    if !type_is_signed && negative {
+        return Err(ParseIntValueError::InvalidDigit);
+    }
+    if radix == 10 {
+        let mut value: BigInt = digits
+            .replace("_", "")
+            .parse()
+            .expect("checked that the digits are valid already");
+        if negative {
+            value = -value;
+        }
+        let uint_value: UIntValue = UInt::new(width).from_bigint_wrapping(&value);
+        if value.is_zero() {
+            Ok(uint_value.into_bits())
+        } else {
+            for i in 0..width {
+                value.set_bit(i as u64, type_is_signed && negative);
+            }
+            if value.is_zero() {
+                Ok(uint_value.into_bits())
+            } else if type_is_signed && negative {
+                if value.sign() == Sign::Minus && value.magnitude().is_one() {
+                    Ok(uint_value.into_bits())
+                } else {
+                    Err(ParseIntValueError::NegOverflow)
+                }
+            } else {
+                Err(ParseIntValueError::PosOverflow)
+            }
+        }
+    } else {
+        let mut value = BitVec::repeat(false, width);
+        let bits_per_digit = match radix {
+            2 => 1,
+            8 => 3,
+            16 => 4,
+            _ => unreachable!(),
+        };
+        let mut digits = digits
+            .bytes()
+            .rev()
+            .filter_map(|ch| (ch as char).to_digit(radix));
+        let overflow_error = if negative {
+            ParseIntValueError::NegOverflow
+        } else {
+            ParseIntValueError::PosOverflow
+        };
+        for chunk in value.chunks_mut(bits_per_digit) {
+            if let Some(mut digit) = digits.next() {
+                let digit_bits = &mut digit.view_bits_mut::<Lsb0>()[..chunk.len()];
+                chunk.clone_from_bitslice(digit_bits);
+                digit_bits.fill(false);
+                if digit != 0 {
+                    return Err(overflow_error);
+                }
+            } else {
+                break;
+            }
+        }
+        for digit in digits {
+            if digit != 0 {
+                return Err(overflow_error);
+            }
+        }
+        let negative_zero = if negative {
+            // negating a value happens in three regions:
+            // * the least-significant zeros, which are left as zeros
+            // * the least-significant one bit, which is left as a one bit
+            // * all the most-significant bits, which are inverted
+            // e.g.:
+            const {
+                let inp = 0b1010_1_000_u8;
+                let out = 0b0101_1_000_u8;
+                assert!(inp.wrapping_neg() == out);
+            };
+            if let Some(first_one) = value.first_one() {
+                let most_significant_bits = &mut value[first_one + 1..];
+                // modifies in-place despite using `Not::not`
+                let _ = Not::not(most_significant_bits);
+                false
+            } else {
+                true
+            }
+        } else {
+            false
+        };
+        if !negative_zero && type_is_signed && negative != value[value.len() - 1] {
+            Err(overflow_error)
+        } else {
+            Ok(Arc::new(value))
+        }
+    }
+}
+
+fn deserialize_int_value<'de, D: Deserializer<'de>>(
+    deserializer: D,
+    type_is_signed: bool,
+    type_width: Option<usize>,
+) -> Result<Arc<BitVec>, D::Error> {
+    struct IntValueVisitor {
+        type_is_signed: bool,
+        type_width: Option<usize>,
+    }
+    impl<'de> Visitor<'de> for IntValueVisitor {
+        type Value = Arc<BitVec>;
+
+        fn expecting(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+            f.write_str(if self.type_is_signed {
+                "SIntValue"
+            } else {
+                "UIntValue"
+            })?;
+            if let Some(type_width) = self.type_width {
+                write!(f, "<{type_width}>")?;
+            }
+            Ok(())
+        }
+
+        fn visit_str<E: Error>(self, v: &str) -> Result<Self::Value, E> {
+            parse_int_value(v, self.type_is_signed, self.type_width, true).map_err(E::custom)
+        }
+
+        fn visit_bytes<E: Error>(self, v: &[u8]) -> Result<Self::Value, E> {
+            match std::str::from_utf8(v) {
+                Ok(v) => self.visit_str(v),
+                Err(_) => Err(Error::invalid_value(serde::de::Unexpected::Bytes(v), &self)),
+            }
+        }
+    }
+    deserializer.deserialize_str(IntValueVisitor {
+        type_is_signed,
+        type_width,
+    })
+}
+
 macro_rules! impl_int {
     ($pretty_name:ident, $name:ident, $generic_name:ident, $value:ident, $SIGNED:literal) => {
         #[derive(Copy, Clone, PartialEq, Eq, Hash)]
@@ -289,6 +611,12 @@ macro_rules! impl_int {
                 }
                 Expr::from_dyn_int(MemoizeBitsToExpr.get_cow(bits))
             }
+            fn from_str_without_ty(
+                self,
+                s: &str,
+            ) -> Result<Self::Value, <Self::Value as FromStr>::Err> {
+                parse_int_value(s, $SIGNED, Some(self.width()), false).map(Self::Value::new)
+            }
         }
 
         impl<Width: Size> IntType for $name<Width> {
@@ -324,7 +652,7 @@ macro_rules! impl_int {
             #[track_caller]
             fn from_canonical(canonical_type: CanonicalType) -> Self {
                 let CanonicalType::$pretty_name(retval) = canonical_type else {
-                    panic!("expected {}", stringify!($name));
+                    panic!("expected {}", stringify!($pretty_name));
                 };
                 $name {
                     width: Width::from_usize(retval.width),
@@ -349,6 +677,12 @@ macro_rules! impl_int {
             }
         }
 
+        impl<Width: KnownSize> Default for $name<Width> {
+            fn default() -> Self {
+                Self::TYPE
+            }
+        }
+
         impl<Width: KnownSize> StaticType for $name<Width> {
             const TYPE: Self = Self { width: Width::SIZE };
             const MASK_TYPE: Self::MaskType = Bool;
@@ -361,6 +695,46 @@ macro_rules! impl_int {
             const MASK_TYPE_PROPERTIES: TypeProperties = Bool::TYPE_PROPERTIES;
         }
 
+        impl<Width: Size> Serialize for $name<Width> {
+            fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+            where
+                S: Serializer,
+            {
+                self.canonical().serialize(serializer)
+            }
+        }
+
+        impl<'de, Width: Size> Deserialize<'de> for $name<Width> {
+            fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+            where
+                D: Deserializer<'de>,
+            {
+                let name = |width| -> String {
+                    if let Some(width) = width {
+                        format!("a {}<{width}>", stringify!($pretty_name))
+                    } else {
+                        format!("a {}", stringify!($pretty_name))
+                    }
+                };
+                match CanonicalType::deserialize(deserializer)? {
+                    CanonicalType::$pretty_name(retval) => {
+                        if let Some(width) = Width::try_from_usize(retval.width()) {
+                            Ok($name { width })
+                        } else {
+                            Err(Error::invalid_value(
+                                serde::de::Unexpected::Other(&name(Some(retval.width()))),
+                                &&*name(Width::KNOWN_VALUE),
+                            ))
+                        }
+                    }
+                    ty => Err(Error::invalid_value(
+                        serde::de::Unexpected::Other(ty.as_serde_unexpected_str()),
+                        &&*name(Width::KNOWN_VALUE),
+                    )),
+                }
+            }
+        }
+
         #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
         pub struct $generic_name;
 
@@ -378,7 +752,7 @@ macro_rules! impl_int {
             _phantom: PhantomData<Width>,
         }
 
-        impl<Width: Size> fmt::Debug for $value<Width> {
+        impl<Width: Size> fmt::Display for $value<Width> {
             fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
                 let value = self.to_bigint();
                 let (sign, magnitude) = value.into_parts();
@@ -392,6 +766,32 @@ macro_rules! impl_int {
             }
         }
 
+        impl<Width: Size> fmt::Debug for $value<Width> {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                fmt::Display::fmt(self, f)
+            }
+        }
+
+        impl<Width: Size> std::str::FromStr for $value<Width> {
+            type Err = ParseIntValueError;
+
+            fn from_str(s: &str) -> Result<Self, Self::Err> {
+                parse_int_value(s, $SIGNED, Width::KNOWN_VALUE, true).map(Self::new)
+            }
+        }
+
+        impl<Width: Size> Serialize for $value<Width> {
+            fn serialize<S: Serializer>(&self, serializer: S) -> Result<S::Ok, S::Error> {
+                self.to_string().serialize(serializer)
+            }
+        }
+
+        impl<'de, Width: Size> Deserialize<'de> for $value<Width> {
+            fn deserialize<D: Deserializer<'de>>(deserializer: D) -> Result<Self, D::Error> {
+                deserialize_int_value(deserializer, $SIGNED, Width::KNOWN_VALUE).map(Self::new)
+            }
+        }
+
         impl<LhsWidth: Size, RhsWidth: Size> PartialEq<$value<RhsWidth>> for $value<LhsWidth> {
             fn eq(&self, other: &$value<RhsWidth>) -> bool {
                 self.to_bigint() == other.to_bigint()
@@ -633,11 +1033,13 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
         + Ord
         + std::hash::Hash
         + fmt::Debug
+        + fmt::Display
         + Send
         + Sync
         + 'static
         + ToExpr<Type = Self>
-        + Into<BigInt>;
+        + Into<BigInt>
+        + std::str::FromStr;
     fn width(self) -> usize;
     fn new(width: <Self::Width as Size>::SizeType) -> Self;
     fn new_static() -> Self
@@ -710,9 +1112,12 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
             bytes, bit_width,
         )))
     }
+    fn from_str_without_ty(self, s: &str) -> Result<Self::Value, <Self::Value as FromStr>::Err>;
 }
 
-pub trait IntType: BoolOrIntType<BaseType = <Self as IntType>::Dyn> {
+pub trait IntType:
+    BoolOrIntType<BaseType = <Self as IntType>::Dyn, Value: FromStr<Err = ParseIntValueError>>
+{
     type Dyn: IntType<Dyn = Self::Dyn, Signed = Self::Signed, Width = DynSize>;
     fn as_dyn_int(self) -> Self::Dyn {
         Self::new_dyn(self.width())
@@ -752,7 +1157,7 @@ pub trait IntType: BoolOrIntType<BaseType = <Self as IntType>::Dyn> {
     }
 }
 
-#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
 pub struct Bool;
 
 impl sealed::BoolOrIntTypeSealed for Bool {}
@@ -784,6 +1189,10 @@ impl BoolOrIntType for Bool {
         assert_eq!(bits.len(), 1);
         bits[0]
     }
+
+    fn from_str_without_ty(self, s: &str) -> Result<Self::Value, <Self::Value as FromStr>::Err> {
+        FromStr::from_str(s)
+    }
 }
 
 impl Bool {
@@ -874,4 +1283,104 @@ mod tests {
         assert_eq!(SInt::for_value(3).width, 3);
         assert_eq!(SInt::for_value(4).width, 4);
     }
+
+    #[test]
+    fn test_serde_round_trip() {
+        use serde_json::json;
+        #[track_caller]
+        fn check<T: Serialize + DeserializeOwned + PartialEq + fmt::Debug>(
+            value: T,
+            expected: serde_json::Value,
+        ) {
+            assert_eq!(serde_json::to_value(&value).unwrap(), expected);
+            assert_eq!(value, T::deserialize(expected).unwrap());
+        }
+        check(UInt[0], json! { { "UInt": { "width": 0 } } });
+        check(UInt::<0>::TYPE, json! { { "UInt": { "width": 0 } } });
+        check(UInt::<35>::TYPE, json! { { "UInt": { "width": 35 } } });
+        check(SInt[0], json! { { "SInt": { "width": 0 } } });
+        check(SInt::<0>::TYPE, json! { { "SInt": { "width": 0 } } });
+        check(SInt::<35>::TYPE, json! { { "SInt": { "width": 35 } } });
+        check(Bool, json! { "Bool" });
+        check(UIntValue::from(0u8), json! { "0x0_u8" });
+        check(SIntValue::from(-128i8), json! { "-0x80_i8" });
+        check(UInt[3].from_int_wrapping(5), json! { "0x5_u3" });
+        check(UInt[12].from_int_wrapping(0x1123), json! { "0x123_u12" });
+        check(SInt[12].from_int_wrapping(0xFEE), json! { "-0x12_i12" });
+        check(SInt[12].from_int_wrapping(0x7EE), json! { "0x7EE_i12" });
+    }
+
+    #[test]
+    fn test_deserialize() {
+        use serde_json::json;
+        #[track_caller]
+        fn check<T: DeserializeOwned + fmt::Debug + PartialEq>(
+            expected: Result<T, &str>,
+            input: serde_json::Value,
+        ) {
+            let mut error = String::new();
+            let value = T::deserialize(input).map_err(|e| -> &str {
+                error = e.to_string();
+                &error
+            });
+            assert_eq!(value, expected);
+        }
+        check::<UInt<0>>(
+            Err("invalid value: a UInt<2>, expected a UInt<0>"),
+            json! { { "UInt": { "width": 2 } } },
+        );
+        check::<UInt<0>>(
+            Err("invalid value: a Bool, expected a UInt<0>"),
+            json! { "Bool" },
+        );
+        check::<SInt<0>>(
+            Err("invalid value: a Bool, expected a SInt<0>"),
+            json! { "Bool" },
+        );
+        check::<UInt>(
+            Err("invalid value: a Bool, expected a UInt"),
+            json! { "Bool" },
+        );
+        check::<SInt>(
+            Err("invalid value: a Bool, expected a SInt"),
+            json! { "Bool" },
+        );
+        check::<UIntValue>(Err("value too large to fit in type"), json! { "2_u1" });
+        check::<UIntValue>(Err("value too large to fit in type"), json! { "10_u1" });
+        check::<UIntValue>(Err("value too large to fit in type"), json! { "0x2_u1" });
+        check::<UIntValue>(Err("value too large to fit in type"), json! { "0b10_u1" });
+        check::<UIntValue>(Err("value too large to fit in type"), json! { "0o2_u1" });
+        check::<SIntValue>(Err("value too large to fit in type"), json! { "0o377_i8" });
+        check::<SIntValue>(Err("value too large to fit in type"), json! { "0o200_i8" });
+        check(Ok(SInt[8].from_int_wrapping(i8::MAX)), json! { "0o177_i8" });
+        check::<SIntValue>(Err("value too small to fit in type"), json! { "-0o201_i8" });
+        check::<SIntValue>(Err("value too small to fit in type"), json! { "-0o377_i8" });
+        check::<SIntValue>(Err("value too small to fit in type"), json! { "-0o400_i8" });
+        check::<SIntValue>(
+            Err("value too small to fit in type"),
+            json! { "-0o4000_i8" },
+        );
+        check(Ok(UIntValue::from(0u8)), json! { "0_u8" });
+        check(Ok(UIntValue::from(0u8)), json! { "0b0_u8" });
+        check(Ok(UIntValue::from(0u8)), json! { "00_u8" });
+        check(Ok(UIntValue::from(0u8)), json! { "0x0_u8" });
+        check(Ok(UIntValue::from(0u8)), json! { "0o0_u8" });
+        check(Ok(SIntValue::from(-128i8)), json! { "-0x000_80_i8" });
+        check(Ok(SIntValue::from(-128i8)), json! { "-0o002_00_hdl_i8" });
+        check(Ok(SIntValue::from(-128i8)), json! { "-0b1__000_0000_i8" });
+        check(Ok(UInt[3].from_int_wrapping(5)), json! { " + 0x5_u3 " });
+        check(
+            Ok(UInt[12].from_int_wrapping(0x1123)),
+            json! { "0x1_2_3_hdl_u12" },
+        );
+        check(Ok(SInt[12].from_int_wrapping(0xFEE)), json! { "-0x12_i12" });
+        check(
+            Ok(SInt[12].from_int_wrapping(0x7EE)),
+            json! { " + \t0x7__E_e_i012\n" },
+        );
+        check(Ok(SInt[0].from_int_wrapping(0)), json! { "-0i0" });
+        check(Ok(SInt[1].from_int_wrapping(0)), json! { "-0i1" });
+        check(Ok(SInt[0].from_int_wrapping(0)), json! { "-0x0i0" });
+        check(Ok(SInt[1].from_int_wrapping(0)), json! { "-0x0i1" });
+    }
 }
diff --git a/crates/fayalite/src/phantom_const.rs b/crates/fayalite/src/phantom_const.rs
index 8422ae0..d2e94d9 100644
--- a/crates/fayalite/src/phantom_const.rs
+++ b/crates/fayalite/src/phantom_const.rs
@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 
-use bitvec::slice::BitSlice;
-use serde::{de::DeserializeOwned, Deserialize, Serialize};
-
 use crate::{
     expr::{
         ops::{ExprPartialEq, ExprPartialOrd},
@@ -13,13 +10,23 @@ use crate::{
     intern::{Intern, Interned, InternedCompare, LazyInterned, Memoize},
     sim::value::{SimValue, SimValuePartialEq, ToSimValue, ToSimValueWithType},
     source_location::SourceLocation,
-    ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
+    ty::{
+        impl_match_variant_as_self,
+        serde_impls::{SerdeCanonicalType, SerdePhantomConst},
+        CanonicalType, StaticType, Type, TypeProperties,
+    },
+};
+use bitvec::slice::BitSlice;
+use serde::{
+    de::{DeserializeOwned, Error},
+    Deserialize, Deserializer, Serialize, Serializer,
 };
 use std::{
     any::Any,
     fmt,
     hash::{Hash, Hasher},
     marker::PhantomData,
+    ops::Index,
 };
 
 #[derive(Clone)]
@@ -115,6 +122,20 @@ pub struct PhantomConst<T: ?Sized + PhantomConstValue = PhantomConstCanonicalVal
     value: LazyInterned<T>,
 }
 
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+pub struct PhantomConstWithoutGenerics;
+
+#[allow(non_upper_case_globals)]
+pub const PhantomConst: PhantomConstWithoutGenerics = PhantomConstWithoutGenerics;
+
+impl<T: Type + PhantomConstValue> Index<T> for PhantomConstWithoutGenerics {
+    type Output = PhantomConst<T>;
+
+    fn index(&self, value: T) -> &Self::Output {
+        Interned::into_inner(PhantomConst::new(value.intern()).intern_sized())
+    }
+}
+
 impl<T: ?Sized + PhantomConstValue> fmt::Debug for PhantomConst<T> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         f.debug_tuple("PhantomConst").field(&self.get()).finish()
@@ -201,17 +222,6 @@ impl<T: ?Sized + PhantomConstValue> Memoize for PhantomConstCanonicalMemoize<T,
     }
 }
 
-impl<T: ?Sized + PhantomConstValue> PhantomConst<T>
-where
-    Interned<T>: Default,
-{
-    pub const fn default() -> Self {
-        PhantomConst {
-            value: LazyInterned::new_lazy(&Interned::<T>::default),
-        }
-    }
-}
-
 impl<T: ?Sized + PhantomConstValue> PhantomConst<T> {
     pub fn new(value: Interned<T>) -> Self {
         Self {
@@ -286,16 +296,53 @@ impl<T: ?Sized + PhantomConstValue> Type for PhantomConst<T> {
     }
 }
 
+impl<T: ?Sized + PhantomConstValue> Default for PhantomConst<T>
+where
+    Interned<T>: Default,
+{
+    fn default() -> Self {
+        Self::TYPE
+    }
+}
+
 impl<T: ?Sized + PhantomConstValue> StaticType for PhantomConst<T>
 where
     Interned<T>: Default,
 {
-    const TYPE: Self = Self::default();
+    const TYPE: Self = PhantomConst {
+        value: LazyInterned::new_lazy(&Interned::<T>::default),
+    };
     const MASK_TYPE: Self::MaskType = ();
     const TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES;
     const MASK_TYPE_PROPERTIES: TypeProperties = <()>::TYPE_PROPERTIES;
 }
 
+type SerdeType<T> = SerdeCanonicalType<CanonicalType, SerdePhantomConst<Interned<T>>>;
+
+impl<T: ?Sized + PhantomConstValue> Serialize for PhantomConst<T> {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        SerdeType::<T>::PhantomConst(SerdePhantomConst(self.get())).serialize(serializer)
+    }
+}
+
+impl<'de, T: ?Sized + PhantomConstValue> Deserialize<'de> for PhantomConst<T> {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: Deserializer<'de>,
+    {
+        match SerdeType::<T>::deserialize(deserializer)? {
+            SerdeCanonicalType::PhantomConst(SerdePhantomConst(value)) => Ok(Self::new(value)),
+            ty => Err(Error::invalid_value(
+                serde::de::Unexpected::Other(ty.as_serde_unexpected_str()),
+                &"a PhantomConst",
+            )),
+        }
+    }
+}
+
 impl<T: ?Sized + PhantomConstValue> ExprPartialEq<Self> for PhantomConst<T> {
     fn cmp_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
         assert_eq!(Expr::ty(lhs), Expr::ty(rhs));
diff --git a/crates/fayalite/src/sim/value.rs b/crates/fayalite/src/sim/value.rs
index d415af4..737043a 100644
--- a/crates/fayalite/src/sim/value.rs
+++ b/crates/fayalite/src/sim/value.rs
@@ -16,6 +16,7 @@ use crate::{
     },
 };
 use bitvec::{slice::BitSlice, vec::BitVec};
+use serde::{Deserialize, Deserializer, Serialize, Serializer};
 use std::{
     fmt,
     ops::{Deref, DerefMut},
@@ -94,6 +95,40 @@ impl<T: Type> AlternatingCellMethods for SimValueInner<T> {
     fn shared_to_unique(&mut self) {}
 }
 
+#[derive(Serialize, Deserialize)]
+#[serde(rename = "SimValue")]
+#[serde(bound(
+    serialize = "T: Type<SimValue: Serialize> + Serialize",
+    deserialize = "T: Type<SimValue: Deserialize<'de>> + Deserialize<'de>"
+))]
+struct SerdeSimValue<'a, T: Type> {
+    ty: T,
+    value: std::borrow::Cow<'a, T::SimValue>,
+}
+
+impl<T: Type<SimValue: Serialize> + Serialize> Serialize for SimValue<T> {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        SerdeSimValue {
+            ty: SimValue::ty(self),
+            value: std::borrow::Cow::Borrowed(&*self),
+        }
+        .serialize(serializer)
+    }
+}
+
+impl<'de, T: Type<SimValue: Deserialize<'de>> + Deserialize<'de>> Deserialize<'de> for SimValue<T> {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: Deserializer<'de>,
+    {
+        let SerdeSimValue { ty, value } = SerdeSimValue::<T>::deserialize(deserializer)?;
+        Ok(SimValue::from_value(ty, value.into_owned()))
+    }
+}
+
 pub struct SimValue<T: Type> {
     inner: AlternatingCell<SimValueInner<T>>,
 }
diff --git a/crates/fayalite/src/ty.rs b/crates/fayalite/src/ty.rs
index 23680f7..8f41c5c 100644
--- a/crates/fayalite/src/ty.rs
+++ b/crates/fayalite/src/ty.rs
@@ -16,8 +16,11 @@ use crate::{
     util::ConstUsize,
 };
 use bitvec::slice::BitSlice;
+use serde::{de::DeserializeOwned, Deserialize, Deserializer, Serialize, Serializer};
 use std::{fmt, hash::Hash, iter::FusedIterator, ops::Index, sync::Arc};
 
+pub(crate) mod serde_impls;
+
 #[derive(Copy, Clone, Hash, PartialEq, Eq, Debug)]
 #[non_exhaustive]
 pub struct TypeProperties {
@@ -60,6 +63,24 @@ impl fmt::Debug for CanonicalType {
     }
 }
 
+impl Serialize for CanonicalType {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        serde_impls::SerdeCanonicalType::from(*self).serialize(serializer)
+    }
+}
+
+impl<'de> Deserialize<'de> for CanonicalType {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: serde::Deserializer<'de>,
+    {
+        Ok(serde_impls::SerdeCanonicalType::deserialize(deserializer)?.into())
+    }
+}
+
 impl CanonicalType {
     pub fn type_properties(self) -> TypeProperties {
         match self {
@@ -158,6 +179,9 @@ impl CanonicalType {
             }
         }
     }
+    pub(crate) fn as_serde_unexpected_str(self) -> &'static str {
+        serde_impls::SerdeCanonicalType::from(self).as_serde_unexpected_str()
+    }
 }
 
 pub trait MatchVariantAndInactiveScope: Sized {
@@ -224,6 +248,34 @@ macro_rules! impl_base_type {
     };
 }
 
+macro_rules! impl_base_type_serde {
+    ($name:ident, $expected:literal) => {
+        impl Serialize for $name {
+            fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+            where
+                S: Serializer,
+            {
+                self.canonical().serialize(serializer)
+            }
+        }
+
+        impl<'de> Deserialize<'de> for $name {
+            fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+            where
+                D: Deserializer<'de>,
+            {
+                match CanonicalType::deserialize(deserializer)? {
+                    CanonicalType::$name(retval) => Ok(retval),
+                    ty => Err(serde::de::Error::invalid_value(
+                        serde::de::Unexpected::Other(ty.as_serde_unexpected_str()),
+                        &$expected,
+                    )),
+                }
+            }
+        }
+    };
+}
+
 impl_base_type!(UInt);
 impl_base_type!(SInt);
 impl_base_type!(Bool);
@@ -236,6 +288,14 @@ impl_base_type!(Reset);
 impl_base_type!(Clock);
 impl_base_type!(PhantomConst);
 
+impl_base_type_serde!(Bool, "a Bool");
+impl_base_type_serde!(Enum, "an Enum");
+impl_base_type_serde!(Bundle, "a Bundle");
+impl_base_type_serde!(AsyncReset, "an AsyncReset");
+impl_base_type_serde!(SyncReset, "a SyncReset");
+impl_base_type_serde!(Reset, "a Reset");
+impl_base_type_serde!(Clock, "a Clock");
+
 impl sealed::BaseTypeSealed for CanonicalType {}
 
 impl BaseType for CanonicalType {}
@@ -293,7 +353,17 @@ pub trait Type:
     fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice);
 }
 
-pub trait BaseType: Type<BaseType = Self> + sealed::BaseTypeSealed + Into<CanonicalType> {}
+pub trait BaseType:
+    Type<
+        BaseType = Self,
+        MaskType: Serialize + DeserializeOwned,
+        SimValue: Serialize + DeserializeOwned,
+    > + sealed::BaseTypeSealed
+    + Into<CanonicalType>
+    + Serialize
+    + DeserializeOwned
+{
+}
 
 macro_rules! impl_match_variant_as_self {
     () => {
@@ -362,7 +432,7 @@ impl Type for CanonicalType {
     }
 }
 
-#[derive(Clone, PartialEq, Eq, Hash, Debug)]
+#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
 pub struct OpaqueSimValue {
     bits: UIntValue,
 }
@@ -399,7 +469,7 @@ impl<T: Type<SimValue = OpaqueSimValue>> ToSimValueWithType<T> for OpaqueSimValu
     }
 }
 
-pub trait StaticType: Type {
+pub trait StaticType: Type + Default {
     const TYPE: Self;
     const MASK_TYPE: Self::MaskType;
     const TYPE_PROPERTIES: TypeProperties;
diff --git a/crates/fayalite/src/ty/serde_impls.rs b/crates/fayalite/src/ty/serde_impls.rs
new file mode 100644
index 0000000..2ea4362
--- /dev/null
+++ b/crates/fayalite/src/ty/serde_impls.rs
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::{
+    array::Array,
+    bundle::{Bundle, BundleType},
+    clock::Clock,
+    enum_::{Enum, EnumType},
+    int::{Bool, SInt, UInt},
+    intern::Interned,
+    phantom_const::{PhantomConstCanonicalValue, PhantomConstValue},
+    prelude::PhantomConst,
+    reset::{AsyncReset, Reset, SyncReset},
+    ty::{BaseType, CanonicalType},
+};
+use serde::{Deserialize, Deserializer, Serialize, Serializer};
+
+pub(crate) struct SerdePhantomConst<T>(pub T);
+
+impl<T: ?Sized + PhantomConstValue> Serialize for SerdePhantomConst<Interned<T>> {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        self.0.serialize(serializer)
+    }
+}
+
+impl<'de, T: ?Sized + PhantomConstValue> Deserialize<'de> for SerdePhantomConst<Interned<T>> {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: Deserializer<'de>,
+    {
+        T::deserialize_value(deserializer).map(Self)
+    }
+}
+
+#[derive(Serialize, Deserialize)]
+#[serde(rename = "CanonicalType")]
+pub(crate) enum SerdeCanonicalType<
+    ArrayElement = CanonicalType,
+    ThePhantomConst = SerdePhantomConst<Interned<PhantomConstCanonicalValue>>,
+> {
+    UInt {
+        width: usize,
+    },
+    SInt {
+        width: usize,
+    },
+    Bool,
+    Array {
+        element: ArrayElement,
+        len: usize,
+    },
+    Enum {
+        variants: Interned<[crate::enum_::EnumVariant]>,
+    },
+    Bundle {
+        fields: Interned<[crate::bundle::BundleField]>,
+    },
+    AsyncReset,
+    SyncReset,
+    Reset,
+    Clock,
+    PhantomConst(ThePhantomConst),
+}
+
+impl<ArrayElement, PhantomConstInner> SerdeCanonicalType<ArrayElement, PhantomConstInner> {
+    pub(crate) fn as_serde_unexpected_str(&self) -> &'static str {
+        match self {
+            Self::UInt { .. } => "a UInt",
+            Self::SInt { .. } => "a SInt",
+            Self::Bool => "a Bool",
+            Self::Array { .. } => "an Array",
+            Self::Enum { .. } => "an Enum",
+            Self::Bundle { .. } => "a Bundle",
+            Self::AsyncReset => "an AsyncReset",
+            Self::SyncReset => "a SyncReset",
+            Self::Reset => "a Reset",
+            Self::Clock => "a Clock",
+            Self::PhantomConst(_) => "a PhantomConst",
+        }
+    }
+}
+
+impl<T: BaseType> From<T> for SerdeCanonicalType {
+    fn from(ty: T) -> Self {
+        let ty: CanonicalType = ty.into();
+        match ty {
+            CanonicalType::UInt(ty) => Self::UInt { width: ty.width() },
+            CanonicalType::SInt(ty) => Self::SInt { width: ty.width() },
+            CanonicalType::Bool(Bool {}) => Self::Bool,
+            CanonicalType::Array(ty) => Self::Array {
+                element: ty.element(),
+                len: ty.len(),
+            },
+            CanonicalType::Enum(ty) => Self::Enum {
+                variants: ty.variants(),
+            },
+            CanonicalType::Bundle(ty) => Self::Bundle {
+                fields: ty.fields(),
+            },
+            CanonicalType::AsyncReset(AsyncReset {}) => Self::AsyncReset,
+            CanonicalType::SyncReset(SyncReset {}) => Self::SyncReset,
+            CanonicalType::Reset(Reset {}) => Self::Reset,
+            CanonicalType::Clock(Clock {}) => Self::Clock,
+            CanonicalType::PhantomConst(ty) => Self::PhantomConst(SerdePhantomConst(ty.get())),
+        }
+    }
+}
+
+impl From<SerdeCanonicalType> for CanonicalType {
+    fn from(ty: SerdeCanonicalType) -> Self {
+        match ty {
+            SerdeCanonicalType::UInt { width } => Self::UInt(UInt::new(width)),
+            SerdeCanonicalType::SInt { width } => Self::SInt(SInt::new(width)),
+            SerdeCanonicalType::Bool => Self::Bool(Bool),
+            SerdeCanonicalType::Array { element, len } => Self::Array(Array::new(element, len)),
+            SerdeCanonicalType::Enum { variants } => Self::Enum(Enum::new(variants)),
+            SerdeCanonicalType::Bundle { fields } => Self::Bundle(Bundle::new(fields)),
+            SerdeCanonicalType::AsyncReset => Self::AsyncReset(AsyncReset),
+            SerdeCanonicalType::SyncReset => Self::SyncReset(SyncReset),
+            SerdeCanonicalType::Reset => Self::Reset(Reset),
+            SerdeCanonicalType::Clock => Self::Clock(Clock),
+            SerdeCanonicalType::PhantomConst(value) => {
+                Self::PhantomConst(PhantomConst::new(value.0))
+            }
+        }
+    }
+}
diff --git a/crates/fayalite/src/util/const_bool.rs b/crates/fayalite/src/util/const_bool.rs
index 7033d6a..7def3b5 100644
--- a/crates/fayalite/src/util/const_bool.rs
+++ b/crates/fayalite/src/util/const_bool.rs
@@ -1,5 +1,9 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
+use serde::{
+    de::{DeserializeOwned, Error, Unexpected},
+    Deserialize, Deserializer, Serialize, Serializer,
+};
 use std::{fmt::Debug, hash::Hash, mem::ManuallyDrop, ptr};
 
 mod sealed {
@@ -9,7 +13,17 @@ mod sealed {
 /// # Safety
 /// the only implementation is `ConstBool<Self::VALUE>`
 pub unsafe trait GenericConstBool:
-    sealed::Sealed + Copy + Ord + Hash + Default + Debug + 'static + Send + Sync
+    sealed::Sealed
+    + Copy
+    + Ord
+    + Hash
+    + Default
+    + Debug
+    + 'static
+    + Send
+    + Sync
+    + Serialize
+    + DeserializeOwned
 {
     const VALUE: bool;
 }
@@ -30,6 +44,32 @@ unsafe impl<const VALUE: bool> GenericConstBool for ConstBool<VALUE> {
     const VALUE: bool = VALUE;
 }
 
+impl<const VALUE: bool> Serialize for ConstBool<VALUE> {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        VALUE.serialize(serializer)
+    }
+}
+
+impl<'de, const VALUE: bool> Deserialize<'de> for ConstBool<VALUE> {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: Deserializer<'de>,
+    {
+        let value = bool::deserialize(deserializer)?;
+        if value == VALUE {
+            Ok(ConstBool)
+        } else {
+            Err(D::Error::invalid_value(
+                Unexpected::Bool(value),
+                &if VALUE { "true" } else { "false" },
+            ))
+        }
+    }
+}
+
 pub trait ConstBoolDispatchTag {
     type Type<Select: GenericConstBool>;
 }
diff --git a/crates/fayalite/src/util/const_usize.rs b/crates/fayalite/src/util/const_usize.rs
index a605336..e098a12 100644
--- a/crates/fayalite/src/util/const_usize.rs
+++ b/crates/fayalite/src/util/const_usize.rs
@@ -1,5 +1,9 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
+use serde::{
+    de::{DeserializeOwned, Error, Unexpected},
+    Deserialize, Deserializer, Serialize, Serializer,
+};
 use std::{fmt::Debug, hash::Hash};
 
 mod sealed {
@@ -8,7 +12,17 @@ mod sealed {
 
 /// the only implementation is `ConstUsize<Self::VALUE>`
 pub trait GenericConstUsize:
-    sealed::Sealed + Copy + Ord + Hash + Default + Debug + 'static + Send + Sync
+    sealed::Sealed
+    + Copy
+    + Ord
+    + Hash
+    + Default
+    + Debug
+    + 'static
+    + Send
+    + Sync
+    + Serialize
+    + DeserializeOwned
 {
     const VALUE: usize;
 }
@@ -27,3 +41,29 @@ impl<const VALUE: usize> sealed::Sealed for ConstUsize<VALUE> {}
 impl<const VALUE: usize> GenericConstUsize for ConstUsize<VALUE> {
     const VALUE: usize = VALUE;
 }
+
+impl<const VALUE: usize> Serialize for ConstUsize<VALUE> {
+    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
+    where
+        S: Serializer,
+    {
+        VALUE.serialize(serializer)
+    }
+}
+
+impl<'de, const VALUE: usize> Deserialize<'de> for ConstUsize<VALUE> {
+    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
+    where
+        D: Deserializer<'de>,
+    {
+        let value = usize::deserialize(deserializer)?;
+        if value == VALUE {
+            Ok(ConstUsize)
+        } else {
+            Err(D::Error::invalid_value(
+                Unexpected::Unsigned(value as u64),
+                &&*VALUE.to_string(),
+            ))
+        }
+    }
+}
diff --git a/crates/fayalite/tests/hdl_types.rs b/crates/fayalite/tests/hdl_types.rs
index b191016..8802fd4 100644
--- a/crates/fayalite/tests/hdl_types.rs
+++ b/crates/fayalite/tests/hdl_types.rs
@@ -4,11 +4,17 @@ use fayalite::{
     bundle::BundleType,
     enum_::EnumType,
     int::{BoolOrIntType, IntType},
+    phantom_const::PhantomConst,
     prelude::*,
     ty::StaticType,
 };
 use std::marker::PhantomData;
 
+#[hdl(outline_generated)]
+pub struct MyConstSize<V: Size> {
+    pub size: PhantomConst<UIntType<V>>,
+}
+
 #[hdl(outline_generated)]
 pub struct S<T, Len: Size, T2> {
     pub a: T,

From 001fd31451398eec481375d3ee1395504580a315 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 4 Apr 2025 19:05:04 -0700
Subject: [PATCH 177/190] add UIntInRange[Inclusive][Type]

---
 crates/fayalite/src/int.rs               |  67 ++-
 crates/fayalite/src/int/uint_in_range.rs | 614 +++++++++++++++++++++++
 crates/fayalite/src/phantom_const.rs     |   7 +-
 crates/fayalite/tests/module.rs          |  88 +++-
 4 files changed, 759 insertions(+), 17 deletions(-)
 create mode 100644 crates/fayalite/src/int/uint_in_range.rs

diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index 13b8cf1..053bd1d 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -7,6 +7,7 @@ use crate::{
         target::{GetTarget, Target},
         Expr, NotALiteralExpr, ToExpr, ToLiteralBits,
     },
+    hdl,
     intern::{Intern, Interned, Memoize},
     sim::value::{SimValue, ToSimValueWithType},
     source_location::SourceLocation,
@@ -30,6 +31,23 @@ use std::{
     sync::Arc,
 };
 
+mod uint_in_range;
+
+#[hdl]
+pub type UIntInRangeType<Start: Size, End: Size> = uint_in_range::UIntInRangeType<Start, End>;
+
+#[hdl]
+pub type UIntInRange<const START: usize, const END: usize> =
+    UIntInRangeType<ConstUsize<START>, ConstUsize<END>>;
+
+#[hdl]
+pub type UIntInRangeInclusiveType<Start: Size, End: Size> =
+    uint_in_range::UIntInRangeInclusiveType<Start, End>;
+
+#[hdl]
+pub type UIntInRangeInclusive<const START: usize, const END: usize> =
+    UIntInRangeInclusiveType<ConstUsize<START>, ConstUsize<END>>;
+
 mod sealed {
     pub trait BoolOrIntTypeSealed {}
     pub trait SizeSealed {}
@@ -536,19 +554,14 @@ macro_rules! impl_int {
         pub const $name: $generic_name = $generic_name;
 
         impl<Width: Size> $name<Width> {
-            pub fn new(width: Width::SizeType) -> Self {
+            pub const fn new(width: Width::SizeType) -> Self {
                 Self { width }
             }
             pub fn width(self) -> usize {
                 Width::as_usize(self.width)
             }
             pub fn type_properties(self) -> TypeProperties {
-                TypeProperties {
-                    is_passive: true,
-                    is_storable: true,
-                    is_castable_from_bits: true,
-                    bit_width: self.width(),
-                }
+                self.as_dyn_int().type_properties_dyn()
             }
             pub fn bits_from_bigint_wrapping(self, v: &BigInt) -> BitVec {
                 BoolOrIntType::bits_from_bigint_wrapping(self, v)
@@ -624,12 +637,20 @@ macro_rules! impl_int {
         }
 
         impl $name {
-            pub fn new_dyn(width: usize) -> Self {
+            pub const fn new_dyn(width: usize) -> Self {
                 Self { width }
             }
             pub fn bits_to_bigint(bits: &BitSlice) -> BigInt {
                 <Self as BoolOrIntType>::bits_to_bigint(bits)
             }
+            pub const fn type_properties_dyn(self) -> TypeProperties {
+                TypeProperties {
+                    is_passive: true,
+                    is_storable: true,
+                    is_castable_from_bits: true,
+                    bit_width: self.width,
+                }
+            }
         }
 
         impl<Width: KnownSize> $name<Width> {
@@ -686,12 +707,10 @@ macro_rules! impl_int {
         impl<Width: KnownSize> StaticType for $name<Width> {
             const TYPE: Self = Self { width: Width::SIZE };
             const MASK_TYPE: Self::MaskType = Bool;
-            const TYPE_PROPERTIES: TypeProperties = TypeProperties {
-                is_passive: true,
-                is_storable: true,
-                is_castable_from_bits: true,
-                bit_width: Width::VALUE,
-            };
+            const TYPE_PROPERTIES: TypeProperties = $name {
+                width: Width::VALUE,
+            }
+            .type_properties_dyn();
             const MASK_TYPE_PROPERTIES: TypeProperties = Bool::TYPE_PROPERTIES;
         }
 
@@ -905,6 +924,10 @@ impl UInt {
         let v: BigUint = v.into();
         Self::new(v.bits().try_into().expect("too big"))
     }
+    /// gets the smallest `UInt` that fits `v` losslessly
+    pub const fn for_value_usize(v: usize) -> Self {
+        Self::new((usize::BITS - v.leading_zeros()) as usize)
+    }
     /// gets the smallest `UInt` that fits `r` losslessly, panics if `r` is empty
     #[track_caller]
     pub fn range(r: Range<impl Into<BigUint>>) -> Self {
@@ -915,6 +938,12 @@ impl UInt {
     }
     /// gets the smallest `UInt` that fits `r` losslessly, panics if `r` is empty
     #[track_caller]
+    pub const fn range_usize(r: Range<usize>) -> Self {
+        assert!(r.end != 0, "empty range");
+        Self::range_inclusive_usize(r.start..=(r.end - 1))
+    }
+    /// gets the smallest `UInt` that fits `r` losslessly, panics if `r` is empty
+    #[track_caller]
     pub fn range_inclusive(r: RangeInclusive<impl Into<BigUint>>) -> Self {
         let (start, end) = r.into_inner();
         let start: BigUint = start.into();
@@ -924,6 +953,16 @@ impl UInt {
         // so must not take more bits than `end`
         Self::for_value(end)
     }
+    /// gets the smallest `UInt` that fits `r` losslessly, panics if `r` is empty
+    #[track_caller]
+    pub const fn range_inclusive_usize(r: RangeInclusive<usize>) -> Self {
+        let start = *r.start();
+        let end = *r.end();
+        assert!(start <= end, "empty range");
+        // no need to check `start`` since it's no larger than `end`
+        // so must not take more bits than `end`
+        Self::for_value_usize(end)
+    }
 }
 
 impl SInt {
diff --git a/crates/fayalite/src/int/uint_in_range.rs b/crates/fayalite/src/int/uint_in_range.rs
new file mode 100644
index 0000000..0e2d07e
--- /dev/null
+++ b/crates/fayalite/src/int/uint_in_range.rs
@@ -0,0 +1,614 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::{
+    bundle::{Bundle, BundleField, BundleType, BundleTypePropertiesBuilder, NoBuilder},
+    expr::{
+        ops::{ExprCastTo, ExprPartialEq, ExprPartialOrd},
+        CastBitsTo, CastTo, CastToBits, Expr, HdlPartialEq, HdlPartialOrd,
+    },
+    int::{Bool, DynSize, KnownSize, Size, SizeType, UInt, UIntType},
+    intern::{Intern, Interned},
+    phantom_const::PhantomConst,
+    sim::value::{SimValue, SimValuePartialEq, ToSimValueWithType},
+    source_location::SourceLocation,
+    ty::{impl_match_variant_as_self, CanonicalType, StaticType, Type, TypeProperties},
+};
+use bitvec::{order::Lsb0, slice::BitSlice, view::BitView};
+use serde::{
+    de::{value::UsizeDeserializer, Error, Visitor},
+    Deserialize, Deserializer, Serialize, Serializer,
+};
+use std::{fmt, marker::PhantomData, ops::Index};
+
+const UINT_IN_RANGE_TYPE_FIELD_NAMES: [&'static str; 2] = ["value", "range"];
+
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+pub struct UIntInRangeMaskType {
+    value: Bool,
+    range: PhantomConstRangeMaskType,
+}
+
+impl Type for UIntInRangeMaskType {
+    type BaseType = Bundle;
+    type MaskType = Self;
+    type SimValue = bool;
+    impl_match_variant_as_self!();
+
+    fn mask_type(&self) -> Self::MaskType {
+        *self
+    }
+
+    fn canonical(&self) -> CanonicalType {
+        CanonicalType::Bundle(Bundle::new(self.fields()))
+    }
+
+    fn from_canonical(canonical_type: CanonicalType) -> Self {
+        let fields = Bundle::from_canonical(canonical_type).fields();
+        let [BundleField {
+            name: value_name,
+            flipped: false,
+            ty: value,
+        }, BundleField {
+            name: range_name,
+            flipped: false,
+            ty: range,
+        }] = *fields
+        else {
+            panic!("expected UIntInRangeMaskType");
+        };
+        assert_eq!([&*value_name, &*range_name], UINT_IN_RANGE_TYPE_FIELD_NAMES);
+        let value = Bool::from_canonical(value);
+        let range = PhantomConstRangeMaskType::from_canonical(range);
+        Self { value, range }
+    }
+
+    fn source_location() -> SourceLocation {
+        SourceLocation::builtin()
+    }
+
+    fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+        Bool.sim_value_from_bits(bits)
+    }
+
+    fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+        Bool.sim_value_clone_from_bits(value, bits);
+    }
+
+    fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+        Bool.sim_value_to_bits(value, bits);
+    }
+}
+
+impl BundleType for UIntInRangeMaskType {
+    type Builder = NoBuilder;
+    type FilledBuilder = Expr<UIntInRangeMaskType>;
+
+    fn fields(&self) -> Interned<[BundleField]> {
+        let [value_name, range_name] = UINT_IN_RANGE_TYPE_FIELD_NAMES;
+        let Self { value, range } = self;
+        [
+            BundleField {
+                name: value_name.intern(),
+                flipped: false,
+                ty: value.canonical(),
+            },
+            BundleField {
+                name: range_name.intern(),
+                flipped: false,
+                ty: range.canonical(),
+            },
+        ][..]
+            .intern()
+    }
+}
+
+impl StaticType for UIntInRangeMaskType {
+    const TYPE: Self = Self {
+        value: Bool,
+        range: PhantomConstRangeMaskType::TYPE,
+    };
+    const MASK_TYPE: Self::MaskType = Self::TYPE;
+    const TYPE_PROPERTIES: TypeProperties = BundleTypePropertiesBuilder::new()
+        .field(false, Bool::TYPE_PROPERTIES)
+        .field(false, PhantomConstRangeMaskType::TYPE_PROPERTIES)
+        .finish();
+    const MASK_TYPE_PROPERTIES: TypeProperties = Self::TYPE_PROPERTIES;
+}
+
+impl ToSimValueWithType<UIntInRangeMaskType> for bool {
+    fn to_sim_value_with_type(&self, ty: UIntInRangeMaskType) -> SimValue<UIntInRangeMaskType> {
+        SimValue::from_value(ty, *self)
+    }
+}
+
+impl ExprCastTo<Bool> for UIntInRangeMaskType {
+    fn cast_to(src: Expr<Self>, to_type: Bool) -> Expr<Bool> {
+        src.cast_to_bits().cast_to(to_type)
+    }
+}
+
+impl ExprCastTo<UIntInRangeMaskType> for Bool {
+    fn cast_to(src: Expr<Self>, to_type: UIntInRangeMaskType) -> Expr<UIntInRangeMaskType> {
+        src.cast_to_static::<UInt<1>>().cast_bits_to(to_type)
+    }
+}
+
+impl ExprPartialEq<Self> for UIntInRangeMaskType {
+    fn cmp_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
+    }
+    fn cmp_ne(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        lhs.cast_to_bits().cmp_ne(rhs.cast_to_bits())
+    }
+}
+
+impl SimValuePartialEq<Self> for UIntInRangeMaskType {
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<Self>) -> bool {
+        **this == **other
+    }
+}
+
+type PhantomConstRangeMaskType = <PhantomConst<SerdeRange<DynSize, DynSize>> as Type>::MaskType;
+
+#[derive(Default, Copy, Clone, Debug)]
+struct RangeParseError;
+
+macro_rules! define_uint_in_range_type {
+    (
+        $UIntInRange:ident,
+        $UIntInRangeType:ident,
+        $UIntInRangeTypeWithoutGenerics:ident,
+        $UIntInRangeTypeWithStart:ident,
+        $SerdeRange:ident,
+        $range_operator_str:literal,
+        |$uint_range_usize_start:ident, $uint_range_usize_end:ident| $uint_range_usize:expr,
+    ) => {
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        struct $SerdeRange<Start: Size, End: Size> {
+            start: Start::SizeType,
+            end: End::SizeType,
+        }
+
+        impl<Start: KnownSize, End: KnownSize> Default for $SerdeRange<Start, End> {
+            fn default() -> Self {
+                Self {
+                    start: Start::SIZE,
+                    end: End::SIZE,
+                }
+            }
+        }
+
+        impl std::str::FromStr for $SerdeRange<DynSize, DynSize> {
+            type Err = RangeParseError;
+
+            fn from_str(s: &str) -> Result<Self, Self::Err> {
+                let Some((start, end)) = s.split_once($range_operator_str) else {
+                    return Err(RangeParseError);
+                };
+                if start.is_empty()
+                    || start.bytes().any(|b| !b.is_ascii_digit())
+                    || end.is_empty()
+                    || end.bytes().any(|b| !b.is_ascii_digit())
+                {
+                    return Err(RangeParseError);
+                }
+                let start = start.parse().map_err(|_| RangeParseError)?;
+                let end = end.parse().map_err(|_| RangeParseError)?;
+                let retval = Self { start, end };
+                if retval.is_empty() {
+                    Err(RangeParseError)
+                } else {
+                    Ok(retval)
+                }
+            }
+        }
+
+        impl<Start: Size, End: Size> fmt::Display for $SerdeRange<Start, End> {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                let Self { start, end } = *self;
+                write!(
+                    f,
+                    "{}{}{}",
+                    Start::as_usize(start),
+                    $range_operator_str,
+                    End::as_usize(end),
+                )
+            }
+        }
+
+        impl<Start: Size, End: Size> Serialize for $SerdeRange<Start, End> {
+            fn serialize<S: Serializer>(&self, serializer: S) -> Result<S::Ok, S::Error> {
+                serializer.collect_str(self)
+            }
+        }
+
+        impl<'de, Start: Size, End: Size> Deserialize<'de> for $SerdeRange<Start, End> {
+            fn deserialize<D: Deserializer<'de>>(deserializer: D) -> Result<Self, D::Error> {
+                struct SerdeRangeVisitor<Start: Size, End: Size>(PhantomData<(Start, End)>);
+                impl<'de, Start: Size, End: Size> Visitor<'de> for SerdeRangeVisitor<Start, End> {
+                    type Value = $SerdeRange<Start, End>;
+
+                    fn expecting(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                        f.write_str("a string with format \"")?;
+                        if let Some(start) = Start::KNOWN_VALUE {
+                            write!(f, "{start}")?;
+                        } else {
+                            f.write_str("<int>")?;
+                        };
+                        f.write_str($range_operator_str)?;
+                        if let Some(end) = End::KNOWN_VALUE {
+                            write!(f, "{end}")?;
+                        } else {
+                            f.write_str("<int>")?;
+                        };
+                        f.write_str("\" that is a non-empty range")
+                    }
+
+                    fn visit_str<E: Error>(self, v: &str) -> Result<Self::Value, E> {
+                        let $SerdeRange::<DynSize, DynSize> { start, end } =
+                            v.parse().map_err(|_| {
+                                Error::invalid_value(serde::de::Unexpected::Str(v), &self)
+                            })?;
+                        let start =
+                            Start::SizeType::deserialize(UsizeDeserializer::<E>::new(start))?;
+                        let end = End::SizeType::deserialize(UsizeDeserializer::<E>::new(end))?;
+                        Ok($SerdeRange { start, end })
+                    }
+
+                    fn visit_bytes<E: Error>(self, v: &[u8]) -> Result<Self::Value, E> {
+                        match std::str::from_utf8(v) {
+                            Ok(v) => self.visit_str(v),
+                            Err(_) => {
+                                Err(Error::invalid_value(serde::de::Unexpected::Bytes(v), &self))
+                            }
+                        }
+                    }
+                }
+                deserializer.deserialize_str(SerdeRangeVisitor(PhantomData))
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash)]
+        pub struct $UIntInRangeType<Start: Size, End: Size> {
+            value: UInt,
+            range: PhantomConst<$SerdeRange<Start, End>>,
+        }
+
+        impl<Start: Size, End: Size> $UIntInRangeType<Start, End> {
+            fn from_phantom_const_range(range: PhantomConst<$SerdeRange<Start, End>>) -> Self {
+                let $SerdeRange { start, end } = *range.get();
+                let $uint_range_usize_start = Start::as_usize(start);
+                let $uint_range_usize_end = End::as_usize(end);
+                Self {
+                    value: $uint_range_usize,
+                    range,
+                }
+            }
+            pub fn new(start: Start::SizeType, end: End::SizeType) -> Self {
+                Self::from_phantom_const_range(PhantomConst::new(
+                    $SerdeRange { start, end }.intern_sized(),
+                ))
+            }
+        }
+
+        impl<Start: Size, End: Size> fmt::Debug for $UIntInRangeType<Start, End> {
+            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+                let Self { value, range } = self;
+                let $SerdeRange { start, end } = *range.get();
+                f.debug_struct(&format!(
+                    "{}<{}, {}>",
+                    stringify!($UIntInRange),
+                    Start::as_usize(start),
+                    End::as_usize(end),
+                ))
+                .field("value", value)
+                .finish_non_exhaustive()
+            }
+        }
+
+        impl<Start: Size, End: Size> Type for $UIntInRangeType<Start, End> {
+            type BaseType = Bundle;
+            type MaskType = UIntInRangeMaskType;
+            type SimValue = usize;
+            impl_match_variant_as_self!();
+
+            fn mask_type(&self) -> Self::MaskType {
+                UIntInRangeMaskType::TYPE
+            }
+
+            fn canonical(&self) -> CanonicalType {
+                CanonicalType::Bundle(Bundle::new(self.fields()))
+            }
+
+            fn from_canonical(canonical_type: CanonicalType) -> Self {
+                let fields = Bundle::from_canonical(canonical_type).fields();
+                let [BundleField {
+                    name: value_name,
+                    flipped: false,
+                    ty: value,
+                }, BundleField {
+                    name: range_name,
+                    flipped: false,
+                    ty: range,
+                }] = *fields
+                else {
+                    panic!("expected {}", stringify!($UIntInRange));
+                };
+                assert_eq!([&*value_name, &*range_name], UINT_IN_RANGE_TYPE_FIELD_NAMES);
+                let value = UInt::from_canonical(value);
+                let range = PhantomConst::<$SerdeRange<Start, End>>::from_canonical(range);
+                let retval = Self::from_phantom_const_range(range);
+                assert_eq!(retval, Self { value, range });
+                retval
+            }
+
+            fn source_location() -> SourceLocation {
+                SourceLocation::builtin()
+            }
+
+            fn sim_value_from_bits(&self, bits: &BitSlice) -> Self::SimValue {
+                let mut retval = 0usize;
+                retval.view_bits_mut::<Lsb0>()[..bits.len()].clone_from_bitslice(bits);
+                retval
+            }
+
+            fn sim_value_clone_from_bits(&self, value: &mut Self::SimValue, bits: &BitSlice) {
+                *value = self.sim_value_from_bits(bits);
+            }
+
+            fn sim_value_to_bits(&self, value: &Self::SimValue, bits: &mut BitSlice) {
+                bits.clone_from_bitslice(&value.view_bits::<Lsb0>()[..bits.len()]);
+            }
+        }
+
+        impl<Start: Size, End: Size> BundleType for $UIntInRangeType<Start, End> {
+            type Builder = NoBuilder;
+            type FilledBuilder = Expr<Self>;
+
+            fn fields(&self) -> Interned<[BundleField]> {
+                let [value_name, range_name] = UINT_IN_RANGE_TYPE_FIELD_NAMES;
+                let Self { value, range } = self;
+                [
+                    BundleField {
+                        name: value_name.intern(),
+                        flipped: false,
+                        ty: value.canonical(),
+                    },
+                    BundleField {
+                        name: range_name.intern(),
+                        flipped: false,
+                        ty: range.canonical(),
+                    },
+                ][..]
+                    .intern()
+            }
+        }
+
+        impl<Start: KnownSize, End: KnownSize> Default for $UIntInRangeType<Start, End> {
+            fn default() -> Self {
+                Self::TYPE
+            }
+        }
+
+        impl<Start: KnownSize, End: KnownSize> StaticType for $UIntInRangeType<Start, End> {
+            const TYPE: Self = {
+                let $uint_range_usize_start = Start::VALUE;
+                let $uint_range_usize_end = End::VALUE;
+                Self {
+                    value: $uint_range_usize,
+                    range: PhantomConst::<$SerdeRange<Start, End>>::TYPE,
+                }
+            };
+            const MASK_TYPE: Self::MaskType = UIntInRangeMaskType::TYPE;
+            const TYPE_PROPERTIES: TypeProperties = BundleTypePropertiesBuilder::new()
+                .field(false, Self::TYPE.value.type_properties_dyn())
+                .field(
+                    false,
+                    PhantomConst::<$SerdeRange<Start, End>>::TYPE_PROPERTIES,
+                )
+                .finish();
+            const MASK_TYPE_PROPERTIES: TypeProperties = UIntInRangeMaskType::TYPE_PROPERTIES;
+        }
+
+        impl<Start: Size, End: Size> ToSimValueWithType<$UIntInRangeType<Start, End>> for usize {
+            fn to_sim_value_with_type(
+                &self,
+                ty: $UIntInRangeType<Start, End>,
+            ) -> SimValue<$UIntInRangeType<Start, End>> {
+                SimValue::from_value(ty, *self)
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Default)]
+        pub struct $UIntInRangeTypeWithoutGenerics;
+
+        #[allow(non_upper_case_globals)]
+        pub const $UIntInRangeType: $UIntInRangeTypeWithoutGenerics =
+            $UIntInRangeTypeWithoutGenerics;
+
+        impl<StartSize: SizeType> Index<StartSize> for $UIntInRangeTypeWithoutGenerics {
+            type Output = $UIntInRangeTypeWithStart<StartSize::Size>;
+
+            fn index(&self, start: StartSize) -> &Self::Output {
+                Interned::into_inner($UIntInRangeTypeWithStart(start).intern_sized())
+            }
+        }
+
+        #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+        pub struct $UIntInRangeTypeWithStart<Start: Size>(Start::SizeType);
+
+        impl<Start: Size, EndSize: SizeType<Size = End>, End: Size<SizeType = EndSize>>
+            Index<EndSize> for $UIntInRangeTypeWithStart<Start>
+        {
+            type Output = $UIntInRangeType<Start, End>;
+
+            fn index(&self, end: EndSize) -> &Self::Output {
+                Interned::into_inner($UIntInRangeType::new(self.0, end).intern_sized())
+            }
+        }
+
+        impl<Start: Size, End: Size> ExprCastTo<UInt> for $UIntInRangeType<Start, End> {
+            fn cast_to(src: Expr<Self>, to_type: UInt) -> Expr<UInt> {
+                src.cast_to_bits().cast_to(to_type)
+            }
+        }
+
+        impl<Start: Size, End: Size> ExprCastTo<$UIntInRangeType<Start, End>> for UInt {
+            fn cast_to(
+                src: Expr<Self>,
+                to_type: $UIntInRangeType<Start, End>,
+            ) -> Expr<$UIntInRangeType<Start, End>> {
+                src.cast_bits_to(to_type)
+            }
+        }
+
+        impl<LhsStart: Size, LhsEnd: Size, RhsStart: Size, RhsEnd: Size>
+            ExprPartialEq<$UIntInRangeType<RhsStart, RhsEnd>>
+            for $UIntInRangeType<LhsStart, LhsEnd>
+        {
+            fn cmp_eq(
+                lhs: Expr<Self>,
+                rhs: Expr<$UIntInRangeType<RhsStart, RhsEnd>>,
+            ) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
+            }
+            fn cmp_ne(
+                lhs: Expr<Self>,
+                rhs: Expr<$UIntInRangeType<RhsStart, RhsEnd>>,
+            ) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_ne(rhs.cast_to_bits())
+            }
+        }
+
+        impl<LhsStart: Size, LhsEnd: Size, RhsStart: Size, RhsEnd: Size>
+            ExprPartialOrd<$UIntInRangeType<RhsStart, RhsEnd>>
+            for $UIntInRangeType<LhsStart, LhsEnd>
+        {
+            fn cmp_lt(
+                lhs: Expr<Self>,
+                rhs: Expr<$UIntInRangeType<RhsStart, RhsEnd>>,
+            ) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_lt(rhs.cast_to_bits())
+            }
+            fn cmp_le(
+                lhs: Expr<Self>,
+                rhs: Expr<$UIntInRangeType<RhsStart, RhsEnd>>,
+            ) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_le(rhs.cast_to_bits())
+            }
+            fn cmp_gt(
+                lhs: Expr<Self>,
+                rhs: Expr<$UIntInRangeType<RhsStart, RhsEnd>>,
+            ) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_gt(rhs.cast_to_bits())
+            }
+            fn cmp_ge(
+                lhs: Expr<Self>,
+                rhs: Expr<$UIntInRangeType<RhsStart, RhsEnd>>,
+            ) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_ge(rhs.cast_to_bits())
+            }
+        }
+
+        impl<LhsStart: Size, LhsEnd: Size, RhsStart: Size, RhsEnd: Size>
+            SimValuePartialEq<$UIntInRangeType<RhsStart, RhsEnd>>
+            for $UIntInRangeType<LhsStart, LhsEnd>
+        {
+            fn sim_value_eq(
+                this: &SimValue<Self>,
+                other: &SimValue<$UIntInRangeType<RhsStart, RhsEnd>>,
+            ) -> bool {
+                **this == **other
+            }
+        }
+
+        impl<Start: Size, End: Size, Width: Size> ExprPartialEq<UIntType<Width>>
+            for $UIntInRangeType<Start, End>
+        {
+            fn cmp_eq(lhs: Expr<Self>, rhs: Expr<UIntType<Width>>) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_eq(rhs)
+            }
+            fn cmp_ne(lhs: Expr<Self>, rhs: Expr<UIntType<Width>>) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_ne(rhs)
+            }
+        }
+
+        impl<Start: Size, End: Size, Width: Size> ExprPartialEq<$UIntInRangeType<Start, End>>
+            for UIntType<Width>
+        {
+            fn cmp_eq(lhs: Expr<Self>, rhs: Expr<$UIntInRangeType<Start, End>>) -> Expr<Bool> {
+                lhs.cmp_eq(rhs.cast_to_bits())
+            }
+            fn cmp_ne(lhs: Expr<Self>, rhs: Expr<$UIntInRangeType<Start, End>>) -> Expr<Bool> {
+                lhs.cmp_ne(rhs.cast_to_bits())
+            }
+        }
+
+        impl<Start: Size, End: Size, Width: Size> ExprPartialOrd<UIntType<Width>>
+            for $UIntInRangeType<Start, End>
+        {
+            fn cmp_lt(lhs: Expr<Self>, rhs: Expr<UIntType<Width>>) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_lt(rhs)
+            }
+            fn cmp_le(lhs: Expr<Self>, rhs: Expr<UIntType<Width>>) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_le(rhs)
+            }
+            fn cmp_gt(lhs: Expr<Self>, rhs: Expr<UIntType<Width>>) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_gt(rhs)
+            }
+            fn cmp_ge(lhs: Expr<Self>, rhs: Expr<UIntType<Width>>) -> Expr<Bool> {
+                lhs.cast_to_bits().cmp_ge(rhs)
+            }
+        }
+
+        impl<Start: Size, End: Size, Width: Size> ExprPartialOrd<$UIntInRangeType<Start, End>>
+            for UIntType<Width>
+        {
+            fn cmp_lt(lhs: Expr<Self>, rhs: Expr<$UIntInRangeType<Start, End>>) -> Expr<Bool> {
+                lhs.cmp_lt(rhs.cast_to_bits())
+            }
+            fn cmp_le(lhs: Expr<Self>, rhs: Expr<$UIntInRangeType<Start, End>>) -> Expr<Bool> {
+                lhs.cmp_le(rhs.cast_to_bits())
+            }
+            fn cmp_gt(lhs: Expr<Self>, rhs: Expr<$UIntInRangeType<Start, End>>) -> Expr<Bool> {
+                lhs.cmp_gt(rhs.cast_to_bits())
+            }
+            fn cmp_ge(lhs: Expr<Self>, rhs: Expr<$UIntInRangeType<Start, End>>) -> Expr<Bool> {
+                lhs.cmp_ge(rhs.cast_to_bits())
+            }
+        }
+    };
+}
+
+define_uint_in_range_type! {
+    UIntInRange,
+    UIntInRangeType,
+    UIntInRangeTypeWithoutGenerics,
+    UIntInRangeTypeWithStart,
+    SerdeRange,
+    "..",
+    |start, end| UInt::range_usize(start..end),
+}
+
+define_uint_in_range_type! {
+    UIntInRangeInclusive,
+    UIntInRangeInclusiveType,
+    UIntInRangeInclusiveTypeWithoutGenerics,
+    UIntInRangeInclusiveTypeWithStart,
+    SerdeRangeInclusive,
+    "..=",
+    |start, end| UInt::range_inclusive_usize(start..=end),
+}
+
+impl SerdeRange<DynSize, DynSize> {
+    fn is_empty(self) -> bool {
+        self.start >= self.end
+    }
+}
+
+impl SerdeRangeInclusive<DynSize, DynSize> {
+    fn is_empty(self) -> bool {
+        self.start > self.end
+    }
+}
diff --git a/crates/fayalite/src/phantom_const.rs b/crates/fayalite/src/phantom_const.rs
index d2e94d9..c481692 100644
--- a/crates/fayalite/src/phantom_const.rs
+++ b/crates/fayalite/src/phantom_const.rs
@@ -7,7 +7,7 @@ use crate::{
         Expr, ToExpr,
     },
     int::Bool,
-    intern::{Intern, Interned, InternedCompare, LazyInterned, Memoize},
+    intern::{Intern, Interned, InternedCompare, LazyInterned, LazyInternedTrait, Memoize},
     sim::value::{SimValue, SimValuePartialEq, ToSimValue, ToSimValueWithType},
     source_location::SourceLocation,
     ty::{
@@ -228,6 +228,11 @@ impl<T: ?Sized + PhantomConstValue> PhantomConst<T> {
             value: LazyInterned::Interned(value),
         }
     }
+    pub const fn new_lazy(v: &'static dyn LazyInternedTrait<T>) -> Self {
+        Self {
+            value: LazyInterned::new_lazy(v),
+        }
+    }
     pub fn get(self) -> Interned<T> {
         self.value.interned()
     }
diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs
index 49b226a..c2dc24e 100644
--- a/crates/fayalite/tests/module.rs
+++ b/crates/fayalite/tests/module.rs
@@ -1,8 +1,13 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use fayalite::{
-    assert_export_firrtl, firrtl::ExportOptions, intern::Intern,
-    module::transform::simplify_enums::SimplifyEnumsKind, prelude::*, reset::ResetType,
+    assert_export_firrtl,
+    firrtl::ExportOptions,
+    int::{UIntInRange, UIntInRangeInclusive},
+    intern::Intern,
+    module::transform::simplify_enums::SimplifyEnumsKind,
+    prelude::*,
+    reset::ResetType,
     ty::StaticType,
 };
 use serde_json::json;
@@ -4547,3 +4552,82 @@ circuit check_struct_cmp_eq:
 ",
     };
 }
+
+#[hdl_module(outline_generated)]
+pub fn check_uint_in_range() {
+    #[hdl]
+    let i_0_to_1: UIntInRange<0, 1> = m.input();
+    #[hdl]
+    let i_0_to_2: UIntInRange<0, 2> = m.input();
+    #[hdl]
+    let i_0_to_3: UIntInRange<0, 3> = m.input();
+    #[hdl]
+    let i_0_to_4: UIntInRange<0, 4> = m.input();
+    #[hdl]
+    let i_0_to_7: UIntInRange<0, 7> = m.input();
+    #[hdl]
+    let i_0_to_8: UIntInRange<0, 8> = m.input();
+    #[hdl]
+    let i_0_to_9: UIntInRange<0, 9> = m.input();
+    #[hdl]
+    let i_0_through_0: UIntInRangeInclusive<0, 0> = m.input();
+    #[hdl]
+    let i_0_through_1: UIntInRangeInclusive<0, 1> = m.input();
+    #[hdl]
+    let i_0_through_2: UIntInRangeInclusive<0, 2> = m.input();
+    #[hdl]
+    let i_0_through_3: UIntInRangeInclusive<0, 3> = m.input();
+    #[hdl]
+    let i_0_through_4: UIntInRangeInclusive<0, 4> = m.input();
+    #[hdl]
+    let i_0_through_7: UIntInRangeInclusive<0, 7> = m.input();
+    #[hdl]
+    let i_0_through_8: UIntInRangeInclusive<0, 8> = m.input();
+    #[hdl]
+    let i_0_through_9: UIntInRangeInclusive<0, 9> = m.input();
+}
+
+#[test]
+fn test_uint_in_range() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_uint_in_range();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_uint_in_range.fir": r"FIRRTL version 3.2.0
+circuit check_uint_in_range:
+    type Ty0 = {value: UInt<0>, range: {}}
+    type Ty1 = {value: UInt<1>, range: {}}
+    type Ty2 = {value: UInt<2>, range: {}}
+    type Ty3 = {value: UInt<2>, range: {}}
+    type Ty4 = {value: UInt<3>, range: {}}
+    type Ty5 = {value: UInt<3>, range: {}}
+    type Ty6 = {value: UInt<4>, range: {}}
+    type Ty7 = {value: UInt<0>, range: {}}
+    type Ty8 = {value: UInt<1>, range: {}}
+    type Ty9 = {value: UInt<2>, range: {}}
+    type Ty10 = {value: UInt<2>, range: {}}
+    type Ty11 = {value: UInt<3>, range: {}}
+    type Ty12 = {value: UInt<3>, range: {}}
+    type Ty13 = {value: UInt<4>, range: {}}
+    type Ty14 = {value: UInt<4>, range: {}}
+    module check_uint_in_range: @[module-XXXXXXXXXX.rs 1:1]
+        input i_0_to_1: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input i_0_to_2: Ty1 @[module-XXXXXXXXXX.rs 3:1]
+        input i_0_to_3: Ty2 @[module-XXXXXXXXXX.rs 4:1]
+        input i_0_to_4: Ty3 @[module-XXXXXXXXXX.rs 5:1]
+        input i_0_to_7: Ty4 @[module-XXXXXXXXXX.rs 6:1]
+        input i_0_to_8: Ty5 @[module-XXXXXXXXXX.rs 7:1]
+        input i_0_to_9: Ty6 @[module-XXXXXXXXXX.rs 8:1]
+        input i_0_through_0: Ty7 @[module-XXXXXXXXXX.rs 9:1]
+        input i_0_through_1: Ty8 @[module-XXXXXXXXXX.rs 10:1]
+        input i_0_through_2: Ty9 @[module-XXXXXXXXXX.rs 11:1]
+        input i_0_through_3: Ty10 @[module-XXXXXXXXXX.rs 12:1]
+        input i_0_through_4: Ty11 @[module-XXXXXXXXXX.rs 13:1]
+        input i_0_through_7: Ty12 @[module-XXXXXXXXXX.rs 14:1]
+        input i_0_through_8: Ty13 @[module-XXXXXXXXXX.rs 15:1]
+        input i_0_through_9: Ty14 @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+}

From 5967e812a2a887f44fb49443f06e1fac5cf4e916 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 8 Apr 2025 21:52:47 -0700
Subject: [PATCH 178/190] fix [SU]IntValue's PartialEq for interning

different widths must make values compare not equal otherwise interning
will e.g. substitute a 0x0_u8 for a 0x0_u2
---
 crates/fayalite/src/int.rs       | 31 +++++++++++++++----------------
 crates/fayalite/src/sim/value.rs |  8 ++++----
 2 files changed, 19 insertions(+), 20 deletions(-)

diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs
index 053bd1d..d8364b1 100644
--- a/crates/fayalite/src/int.rs
+++ b/crates/fayalite/src/int.rs
@@ -765,7 +765,7 @@ macro_rules! impl_int {
             }
         }
 
-        #[derive(Clone, Eq, Hash)]
+        #[derive(Clone, PartialEq, Eq, Hash)]
         pub struct $value<Width: Size = DynSize> {
             bits: Arc<BitVec>,
             _phantom: PhantomData<Width>,
@@ -811,24 +811,15 @@ macro_rules! impl_int {
             }
         }
 
-        impl<LhsWidth: Size, RhsWidth: Size> PartialEq<$value<RhsWidth>> for $value<LhsWidth> {
-            fn eq(&self, other: &$value<RhsWidth>) -> bool {
-                self.to_bigint() == other.to_bigint()
-            }
-        }
-
-        impl<LhsWidth: Size, RhsWidth: Size> PartialOrd<$value<RhsWidth>> for $value<LhsWidth> {
-            fn partial_cmp(&self, other: &$value<RhsWidth>) -> Option<std::cmp::Ordering> {
+        impl<Width: Size> PartialOrd for $value<Width> {
+            fn partial_cmp(&self, other: &Self) -> Option<std::cmp::Ordering> {
+                if self.width() != other.width() {
+                    return None;
+                }
                 Some(self.to_bigint().cmp(&other.to_bigint()))
             }
         }
 
-        impl<Width: Size> Ord for $value<Width> {
-            fn cmp(&self, other: &Self) -> std::cmp::Ordering {
-                self.to_bigint().cmp(&other.to_bigint())
-            }
-        }
-
         impl<Width: Size> From<$value<Width>> for BigInt {
             fn from(v: $value<Width>) -> BigInt {
                 v.to_bigint()
@@ -1069,7 +1060,8 @@ pub trait BoolOrIntType: Type + sealed::BoolOrIntTypeSealed {
     type Width: Size;
     type Signed: GenericConstBool;
     type Value: Clone
-        + Ord
+        + PartialOrd
+        + Eq
         + std::hash::Hash
         + fmt::Debug
         + fmt::Display
@@ -1300,6 +1292,13 @@ impl ToLiteralBits for bool {
 mod tests {
     use super::*;
 
+    #[test]
+    fn test_different_value_widths_compare_ne() {
+        // interning relies on [SU]IntValue with different `width` comparing not equal
+        assert_ne!(UInt[3].from_int_wrapping(0), UInt[4].from_int_wrapping(0));
+        assert_ne!(SInt[3].from_int_wrapping(0), SInt[4].from_int_wrapping(0));
+    }
+
     #[test]
     fn test_uint_for_value() {
         assert_eq!(UInt::for_value(0u8).width, 0);
diff --git a/crates/fayalite/src/sim/value.rs b/crates/fayalite/src/sim/value.rs
index 737043a..8dace78 100644
--- a/crates/fayalite/src/sim/value.rs
+++ b/crates/fayalite/src/sim/value.rs
@@ -324,14 +324,14 @@ impl<T: SimValuePartialEq<U>, U: Type> PartialEq<SimValue<U>> for SimValue<T> {
     }
 }
 
-impl<LhsWidth: Size, RhsWidth: Size> SimValuePartialEq<UIntType<RhsWidth>> for UIntType<LhsWidth> {
-    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<UIntType<RhsWidth>>) -> bool {
+impl<Width: Size> SimValuePartialEq<Self> for UIntType<Width> {
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<Self>) -> bool {
         **this == **other
     }
 }
 
-impl<LhsWidth: Size, RhsWidth: Size> SimValuePartialEq<SIntType<RhsWidth>> for SIntType<LhsWidth> {
-    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<SIntType<RhsWidth>>) -> bool {
+impl<Width: Size> SimValuePartialEq<Self> for SIntType<Width> {
+    fn sim_value_eq(this: &SimValue<Self>, other: &SimValue<Self>) -> bool {
         **this == **other
     }
 }

From 9a1b047d2f9cef4c4590d1bb079ada10cc80d740 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 9 Apr 2025 16:25:56 -0700
Subject: [PATCH 179/190] change TypeIdMap to not use any unsafe code

---
 crates/fayalite/src/intern/type_map.rs | 55 +++++++-------------------
 1 file changed, 15 insertions(+), 40 deletions(-)

diff --git a/crates/fayalite/src/intern/type_map.rs b/crates/fayalite/src/intern/type_map.rs
index 48433af..945116b 100644
--- a/crates/fayalite/src/intern/type_map.rs
+++ b/crates/fayalite/src/intern/type_map.rs
@@ -1,10 +1,8 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-use hashbrown::HashMap;
 use std::{
     any::{Any, TypeId},
     hash::{BuildHasher, Hasher},
-    ptr::NonNull,
     sync::RwLock,
 };
 
@@ -75,59 +73,36 @@ impl BuildHasher for TypeIdBuildHasher {
     }
 }
 
-struct Value(NonNull<dyn Any + Send + Sync>);
-
-impl Value {
-    unsafe fn get_transmute_lifetime<'b>(&self) -> &'b (dyn Any + Send + Sync) {
-        unsafe { &*self.0.as_ptr() }
-    }
-    fn new(v: Box<dyn Any + Send + Sync>) -> Self {
-        unsafe { Self(NonNull::new_unchecked(Box::into_raw(v))) }
-    }
-}
-
-unsafe impl Send for Value {}
-unsafe impl Sync for Value {}
-
-impl Drop for Value {
-    fn drop(&mut self) {
-        unsafe { std::ptr::drop_in_place(self.0.as_ptr()) }
-    }
-}
-
-pub struct TypeIdMap(RwLock<HashMap<TypeId, Value, TypeIdBuildHasher>>);
+pub(crate) struct TypeIdMap(
+    RwLock<hashbrown::HashMap<TypeId, &'static (dyn Any + Send + Sync), TypeIdBuildHasher>>,
+);
 
 impl TypeIdMap {
-    pub const fn new() -> Self {
-        Self(RwLock::new(HashMap::with_hasher(TypeIdBuildHasher)))
+    pub(crate) const fn new() -> Self {
+        Self(RwLock::new(hashbrown::HashMap::with_hasher(
+            TypeIdBuildHasher,
+        )))
     }
     #[cold]
-    unsafe fn insert_slow(
+    fn insert_slow(
         &self,
         type_id: TypeId,
         make: fn() -> Box<dyn Any + Sync + Send>,
-    ) -> &(dyn Any + Sync + Send) {
-        let value = Value::new(make());
+    ) -> &'static (dyn Any + Sync + Send) {
+        let value = Box::leak(make());
         let mut write_guard = self.0.write().unwrap();
-        unsafe {
-            write_guard
-                .entry(type_id)
-                .or_insert(value)
-                .get_transmute_lifetime()
-        }
+        *write_guard.entry(type_id).or_insert(value)
     }
-    pub fn get_or_insert_default<T: Sized + Any + Send + Sync + Default>(&self) -> &T {
+    pub(crate) fn get_or_insert_default<T: Sized + Any + Send + Sync + Default>(&self) -> &T {
         let type_id = TypeId::of::<T>();
         let read_guard = self.0.read().unwrap();
-        let retval = read_guard
-            .get(&type_id)
-            .map(|v| unsafe { Value::get_transmute_lifetime(v) });
+        let retval = read_guard.get(&type_id).map(|v| *v);
         drop(read_guard);
         let retval = match retval {
             Some(retval) => retval,
-            None => unsafe { self.insert_slow(type_id, move || Box::new(T::default())) },
+            None => self.insert_slow(type_id, move || Box::new(T::default())),
         };
-        unsafe { &*(retval as *const dyn Any as *const T) }
+        retval.downcast_ref().expect("known to have correct TypeId")
     }
 }
 

From 36f1b9bbb60031ee9770ba3181551b7c1117d5ea Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 9 Apr 2025 19:19:25 -0700
Subject: [PATCH 180/190] add derive(Debug) to all types that are interned

---
 crates/fayalite/src/annotations.rs | 2 +-
 crates/fayalite/src/memory.rs      | 2 +-
 crates/fayalite/src/sim.rs         | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/crates/fayalite/src/annotations.rs b/crates/fayalite/src/annotations.rs
index 8eff4a0..1c517ae 100644
--- a/crates/fayalite/src/annotations.rs
+++ b/crates/fayalite/src/annotations.rs
@@ -12,7 +12,7 @@ use std::{
     ops::Deref,
 };
 
-#[derive(Clone)]
+#[derive(Clone, Debug)]
 struct CustomFirrtlAnnotationFieldsImpl {
     value: serde_json::Map<String, serde_json::Value>,
     serialized: Interned<str>,
diff --git a/crates/fayalite/src/memory.rs b/crates/fayalite/src/memory.rs
index 1101157..622ffc6 100644
--- a/crates/fayalite/src/memory.rs
+++ b/crates/fayalite/src/memory.rs
@@ -470,7 +470,7 @@ pub enum ReadUnderWrite {
     Undefined,
 }
 
-#[derive(Copy, Clone, PartialEq, Eq, Hash)]
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
 struct MemImpl<Element: Type, Len: Size, P> {
     scoped_name: ScopedNameId,
     source_location: SourceLocation,
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index 563cd37..da7c293 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -5783,7 +5783,7 @@ where
     }
 }
 
-#[derive(Clone, PartialEq, Eq, Hash)]
+#[derive(Clone, PartialEq, Eq, Hash, Debug)]
 struct SimTrace<K, S> {
     kind: K,
     state: S,

From 07725ab489346d18e8928acf9685301adb8d778f Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 9 Apr 2025 19:30:02 -0700
Subject: [PATCH 181/190] switch interning to use HashTable rather than HashMap

---
 crates/fayalite/src/intern.rs | 39 +++++++++++++++++++++--------------
 1 file changed, 23 insertions(+), 16 deletions(-)

diff --git a/crates/fayalite/src/intern.rs b/crates/fayalite/src/intern.rs
index 3780ad3..a8f7fc0 100644
--- a/crates/fayalite/src/intern.rs
+++ b/crates/fayalite/src/intern.rs
@@ -3,7 +3,7 @@
 #![allow(clippy::type_complexity)]
 use crate::intern::type_map::TypeIdMap;
 use bitvec::{ptr::BitPtr, slice::BitSlice, vec::BitVec};
-use hashbrown::{hash_map::RawEntryMut, HashMap, HashTable};
+use hashbrown::{HashTable, hash_map::DefaultHashBuilder as DefaultBuildHasher};
 use serde::{Deserialize, Serialize};
 use std::{
     any::{Any, TypeId},
@@ -17,7 +17,7 @@ use std::{
     sync::{Mutex, RwLock},
 };
 
-pub mod type_map;
+mod type_map;
 
 pub trait LazyInternedTrait<T: ?Sized + Send + Sync + 'static>: Send + Sync + Any {
     fn get(&self) -> Interned<T>;
@@ -316,8 +316,13 @@ pub trait Intern: Any + Send + Sync {
     }
 }
 
+struct InternerState<T: ?Sized + 'static + Send + Sync> {
+    table: HashTable<&'static T>,
+    hasher: DefaultBuildHasher,
+}
+
 pub struct Interner<T: ?Sized + 'static + Send + Sync> {
-    map: Mutex<HashMap<&'static T, ()>>,
+    state: Mutex<InternerState<T>>,
 }
 
 impl<T: ?Sized + 'static + Send + Sync> Interner<T> {
@@ -330,7 +335,10 @@ impl<T: ?Sized + 'static + Send + Sync> Interner<T> {
 impl<T: ?Sized + 'static + Send + Sync> Default for Interner<T> {
     fn default() -> Self {
         Self {
-            map: Default::default(),
+            state: Mutex::new(InternerState {
+                table: HashTable::new(),
+                hasher: Default::default(),
+            }),
         }
     }
 }
@@ -341,17 +349,16 @@ impl<T: ?Sized + 'static + Send + Sync + Hash + Eq + ToOwned> Interner<T> {
         alloc: F,
         value: Cow<'_, T>,
     ) -> Interned<T> {
-        let mut map = self.map.lock().unwrap();
-        let hasher = map.hasher().clone();
-        let hash = hasher.hash_one(&*value);
-        let inner = match map.raw_entry_mut().from_hash(hash, |k| **k == *value) {
-            RawEntryMut::Occupied(entry) => *entry.key(),
-            RawEntryMut::Vacant(entry) => {
-                *entry
-                    .insert_with_hasher(hash, alloc(value), (), |k| hasher.hash_one(&**k))
-                    .0
-            }
-        };
+        let mut state = self.state.lock().unwrap();
+        let InternerState { table, hasher } = &mut *state;
+        let inner = *table
+            .entry(
+                hasher.hash_one(&*value),
+                |k| **k == *value,
+                |k| hasher.hash_one(&**k),
+            )
+            .or_insert_with(|| alloc(value))
+            .get();
         Interned { inner }
     }
 }
@@ -742,7 +749,7 @@ pub trait MemoizeGeneric: 'static + Send + Sync + Hash + Eq + Copy {
     fn get_cow(self, input: Self::InputCow<'_>) -> Self::Output {
         static TYPE_ID_MAP: TypeIdMap = TypeIdMap::new();
         let map: &RwLock<(
-            hashbrown::hash_map::DefaultHashBuilder,
+            DefaultBuildHasher,
             HashTable<(Self, Self::InputOwned, Self::Output)>,
         )> = TYPE_ID_MAP.get_or_insert_default();
         fn hash_eq_key<'a, 'b, T: MemoizeGeneric>(

From e0c9939147f04e62b4e117c87a2c03726880366b Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 9 Apr 2025 19:55:09 -0700
Subject: [PATCH 182/190] add test that SimValue can't be interned, since its
 PartialEq may ignore types

---
 .../tests/ui/simvalue_is_not_internable.rs    |  15 ++
 .../ui/simvalue_is_not_internable.stderr      | 178 ++++++++++++++++++
 2 files changed, 193 insertions(+)
 create mode 100644 crates/fayalite/tests/ui/simvalue_is_not_internable.rs
 create mode 100644 crates/fayalite/tests/ui/simvalue_is_not_internable.stderr

diff --git a/crates/fayalite/tests/ui/simvalue_is_not_internable.rs b/crates/fayalite/tests/ui/simvalue_is_not_internable.rs
new file mode 100644
index 0000000..d40990f
--- /dev/null
+++ b/crates/fayalite/tests/ui/simvalue_is_not_internable.rs
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+//! check that SimValue can't be interned, since equality may ignore types
+
+use fayalite::{
+    intern::{Intern, Interned},
+    sim::value::SimValue,
+};
+
+fn f(v: SimValue<()>) -> Interned<SimValue<()>> {
+    Intern::intern_sized(v)
+}
+
+fn main() {}
diff --git a/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr b/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr
new file mode 100644
index 0000000..eb8877b
--- /dev/null
+++ b/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr
@@ -0,0 +1,178 @@
+error[E0277]: `Cell<util::alternating_cell::State>` cannot be shared between threads safely
+  --> tests/ui/simvalue_is_not_internable.rs:11:26
+   |
+11 | fn f(v: SimValue<()>) -> Interned<SimValue<()>> {
+   |                          ^^^^^^^^^^^^^^^^^^^^^^ `Cell<util::alternating_cell::State>` cannot be shared between threads safely
+   |
+   = help: within `SimValue<()>`, the trait `Sync` is not implemented for `Cell<util::alternating_cell::State>`, which is required by `SimValue<()>: Sync`
+   = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock`
+note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
+  --> src/util/alternating_cell.rs
+   |
+   | pub(crate) struct AlternatingCell<T: ?Sized> {
+   |                   ^^^^^^^^^^^^^^^
+note: required because it appears within the type `SimValue<()>`
+  --> src/sim/value.rs
+   |
+   | pub struct SimValue<T: Type> {
+   |            ^^^^^^^^
+note: required by a bound in `fayalite::intern::Interned`
+  --> src/intern.rs
+   |
+   | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
+   |                                                  ^^^^ required by this bound in `Interned`
+
+error[E0277]: `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
+  --> tests/ui/simvalue_is_not_internable.rs:11:26
+   |
+11 | fn f(v: SimValue<()>) -> Interned<SimValue<()>> {
+   |                          ^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
+   |
+   = help: within `SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell<value::SimValueInner<()>>`, which is required by `SimValue<()>: Sync`
+note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
+  --> src/util/alternating_cell.rs
+   |
+   | pub(crate) struct AlternatingCell<T: ?Sized> {
+   |                   ^^^^^^^^^^^^^^^
+note: required because it appears within the type `SimValue<()>`
+  --> src/sim/value.rs
+   |
+   | pub struct SimValue<T: Type> {
+   |            ^^^^^^^^
+note: required by a bound in `fayalite::intern::Interned`
+  --> src/intern.rs
+   |
+   | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
+   |                                                  ^^^^ required by this bound in `Interned`
+
+error[E0277]: the trait bound `SimValue<()>: Intern` is not satisfied
+  --> tests/ui/simvalue_is_not_internable.rs:12:26
+   |
+12 |     Intern::intern_sized(v)
+   |     -------------------- ^ the trait `Hash` is not implemented for `SimValue<()>`, which is required by `SimValue<()>: Intern`
+   |     |
+   |     required by a bound introduced by this call
+   |
+   = help: the following other types implement trait `Intern`:
+             BitSlice
+             [T]
+             str
+   = note: required for `SimValue<()>` to implement `Intern`
+
+error[E0277]: the trait bound `SimValue<()>: Intern` is not satisfied
+  --> tests/ui/simvalue_is_not_internable.rs:12:26
+   |
+12 |     Intern::intern_sized(v)
+   |     -------------------- ^ the trait `std::cmp::Eq` is not implemented for `SimValue<()>`, which is required by `SimValue<()>: Intern`
+   |     |
+   |     required by a bound introduced by this call
+   |
+   = help: the following other types implement trait `Intern`:
+             BitSlice
+             [T]
+             str
+   = note: required for `SimValue<()>` to implement `Intern`
+
+error[E0277]: `Cell<util::alternating_cell::State>` cannot be shared between threads safely
+  --> tests/ui/simvalue_is_not_internable.rs:12:26
+   |
+12 |     Intern::intern_sized(v)
+   |     -------------------- ^ `Cell<util::alternating_cell::State>` cannot be shared between threads safely
+   |     |
+   |     required by a bound introduced by this call
+   |
+   = help: within `SimValue<()>`, the trait `Sync` is not implemented for `Cell<util::alternating_cell::State>`, which is required by `SimValue<()>: Sync`
+   = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock`
+note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
+  --> src/util/alternating_cell.rs
+   |
+   | pub(crate) struct AlternatingCell<T: ?Sized> {
+   |                   ^^^^^^^^^^^^^^^
+note: required because it appears within the type `SimValue<()>`
+  --> src/sim/value.rs
+   |
+   | pub struct SimValue<T: Type> {
+   |            ^^^^^^^^
+note: required by a bound in `intern_sized`
+  --> src/intern.rs
+   |
+   | pub trait Intern: Any + Send + Sync {
+   |                                ^^^^ required by this bound in `Intern::intern_sized`
+   |     fn intern(&self) -> Interned<Self>;
+   |     fn intern_sized(self) -> Interned<Self>
+   |        ------------ required by a bound in this associated function
+
+error[E0277]: `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
+  --> tests/ui/simvalue_is_not_internable.rs:12:26
+   |
+12 |     Intern::intern_sized(v)
+   |     -------------------- ^ `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
+   |     |
+   |     required by a bound introduced by this call
+   |
+   = help: within `SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell<value::SimValueInner<()>>`, which is required by `SimValue<()>: Sync`
+note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
+  --> src/util/alternating_cell.rs
+   |
+   | pub(crate) struct AlternatingCell<T: ?Sized> {
+   |                   ^^^^^^^^^^^^^^^
+note: required because it appears within the type `SimValue<()>`
+  --> src/sim/value.rs
+   |
+   | pub struct SimValue<T: Type> {
+   |            ^^^^^^^^
+note: required by a bound in `intern_sized`
+  --> src/intern.rs
+   |
+   | pub trait Intern: Any + Send + Sync {
+   |                                ^^^^ required by this bound in `Intern::intern_sized`
+   |     fn intern(&self) -> Interned<Self>;
+   |     fn intern_sized(self) -> Interned<Self>
+   |        ------------ required by a bound in this associated function
+
+error[E0277]: `Cell<util::alternating_cell::State>` cannot be shared between threads safely
+  --> tests/ui/simvalue_is_not_internable.rs:12:5
+   |
+12 |     Intern::intern_sized(v)
+   |     ^^^^^^^^^^^^^^^^^^^^^^^ `Cell<util::alternating_cell::State>` cannot be shared between threads safely
+   |
+   = help: within `SimValue<()>`, the trait `Sync` is not implemented for `Cell<util::alternating_cell::State>`, which is required by `SimValue<()>: Sync`
+   = note: if you want to do aliasing and mutation between multiple threads, use `std::sync::RwLock`
+note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
+  --> src/util/alternating_cell.rs
+   |
+   | pub(crate) struct AlternatingCell<T: ?Sized> {
+   |                   ^^^^^^^^^^^^^^^
+note: required because it appears within the type `SimValue<()>`
+  --> src/sim/value.rs
+   |
+   | pub struct SimValue<T: Type> {
+   |            ^^^^^^^^
+note: required by a bound in `fayalite::intern::Interned`
+  --> src/intern.rs
+   |
+   | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
+   |                                                  ^^^^ required by this bound in `Interned`
+
+error[E0277]: `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
+  --> tests/ui/simvalue_is_not_internable.rs:12:5
+   |
+12 |     Intern::intern_sized(v)
+   |     ^^^^^^^^^^^^^^^^^^^^^^^ `UnsafeCell<value::SimValueInner<()>>` cannot be shared between threads safely
+   |
+   = help: within `SimValue<()>`, the trait `Sync` is not implemented for `UnsafeCell<value::SimValueInner<()>>`, which is required by `SimValue<()>: Sync`
+note: required because it appears within the type `util::alternating_cell::AlternatingCell<value::SimValueInner<()>>`
+  --> src/util/alternating_cell.rs
+   |
+   | pub(crate) struct AlternatingCell<T: ?Sized> {
+   |                   ^^^^^^^^^^^^^^^
+note: required because it appears within the type `SimValue<()>`
+  --> src/sim/value.rs
+   |
+   | pub struct SimValue<T: Type> {
+   |            ^^^^^^^^
+note: required by a bound in `fayalite::intern::Interned`
+  --> src/intern.rs
+   |
+   | pub struct Interned<T: ?Sized + 'static + Send + Sync> {
+   |                                                  ^^^^ required by this bound in `Interned`

From b08a747e20494d79287e0886dc0637ebaeac37d9 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 9 Apr 2025 20:03:14 -0700
Subject: [PATCH 183/190] switch to using type aliases for HashMap/HashSet to
 allow easily switching hashers

---
 crates/fayalite/src/bundle.rs                 |  4 +--
 crates/fayalite/src/enum_.rs                  |  5 +--
 crates/fayalite/src/firrtl.rs                 |  5 ++-
 crates/fayalite/src/intern.rs                 |  4 +--
 crates/fayalite/src/module.rs                 | 14 ++++----
 .../src/module/transform/deduce_resets.rs     |  9 ++---
 .../src/module/transform/simplify_enums.rs    |  6 ++--
 .../src/module/transform/simplify_memories.rs |  5 ++-
 crates/fayalite/src/sim.rs                    | 34 +++++++++----------
 crates/fayalite/src/sim/interpreter.rs        |  3 +-
 crates/fayalite/src/sim/vcd.rs                |  3 +-
 crates/fayalite/src/source_location.rs        |  7 ++--
 crates/fayalite/src/testing.rs                |  4 +--
 crates/fayalite/src/util.rs                   |  6 ++++
 14 files changed, 57 insertions(+), 52 deletions(-)

diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs
index 0fd89f1..240c0c6 100644
--- a/crates/fayalite/src/bundle.rs
+++ b/crates/fayalite/src/bundle.rs
@@ -14,9 +14,9 @@ use crate::{
         impl_match_variant_as_self, CanonicalType, MatchVariantWithoutScope, OpaqueSimValue,
         StaticType, Type, TypeProperties, TypeWithDeref,
     },
+    util::HashMap,
 };
 use bitvec::{slice::BitSlice, vec::BitVec};
-use hashbrown::HashMap;
 use serde::{Deserialize, Serialize};
 use std::{fmt, marker::PhantomData};
 
@@ -160,7 +160,7 @@ impl Default for BundleTypePropertiesBuilder {
 impl Bundle {
     #[track_caller]
     pub fn new(fields: Interned<[BundleField]>) -> Self {
-        let mut name_indexes = HashMap::with_capacity(fields.len());
+        let mut name_indexes = HashMap::with_capacity_and_hasher(fields.len(), Default::default());
         let mut field_offsets = Vec::with_capacity(fields.len());
         let mut type_props_builder = BundleTypePropertiesBuilder::new();
         for (index, &BundleField { name, flipped, ty }) in fields.iter().enumerate() {
diff --git a/crates/fayalite/src/enum_.rs b/crates/fayalite/src/enum_.rs
index 6205855..36b5aa7 100644
--- a/crates/fayalite/src/enum_.rs
+++ b/crates/fayalite/src/enum_.rs
@@ -19,9 +19,9 @@ use crate::{
         CanonicalType, MatchVariantAndInactiveScope, OpaqueSimValue, StaticType, Type,
         TypeProperties,
     },
+    util::HashMap,
 };
 use bitvec::{order::Lsb0, slice::BitSlice, view::BitView};
-use hashbrown::HashMap;
 use serde::{Deserialize, Serialize};
 use std::{convert::Infallible, fmt, iter::FusedIterator, sync::Arc};
 
@@ -193,7 +193,8 @@ impl Default for EnumTypePropertiesBuilder {
 impl Enum {
     #[track_caller]
     pub fn new(variants: Interned<[EnumVariant]>) -> Self {
-        let mut name_indexes = HashMap::with_capacity(variants.len());
+        let mut name_indexes =
+            HashMap::with_capacity_and_hasher(variants.len(), Default::default());
         let mut type_props_builder = EnumTypePropertiesBuilder::new();
         for (index, EnumVariant { name, ty }) in variants.iter().enumerate() {
             if let Some(old_index) = name_indexes.insert(*name, index) {
diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs
index d082187..d33c7a9 100644
--- a/crates/fayalite/src/firrtl.rs
+++ b/crates/fayalite/src/firrtl.rs
@@ -36,12 +36,11 @@ use crate::{
     ty::{CanonicalType, Type},
     util::{
         const_str_array_is_strictly_ascending, BitSliceWriteWithBase, DebugAsRawString,
-        GenericConstBool,
+        GenericConstBool, HashMap, HashSet,
     },
 };
 use bitvec::slice::BitSlice;
 use clap::value_parser;
-use hashbrown::{HashMap, HashSet};
 use num_traits::Signed;
 use serde::Serialize;
 use std::{
@@ -2622,7 +2621,7 @@ fn export_impl(
             indent_depth: &indent_depth,
             indent: "    ",
         },
-        seen_modules: HashSet::new(),
+        seen_modules: HashSet::default(),
         unwritten_modules: VecDeque::new(),
         global_ns,
         module: ModuleState::default(),
diff --git a/crates/fayalite/src/intern.rs b/crates/fayalite/src/intern.rs
index a8f7fc0..af91f0a 100644
--- a/crates/fayalite/src/intern.rs
+++ b/crates/fayalite/src/intern.rs
@@ -1,9 +1,9 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 #![allow(clippy::type_complexity)]
-use crate::intern::type_map::TypeIdMap;
+use crate::{intern::type_map::TypeIdMap, util::DefaultBuildHasher};
 use bitvec::{ptr::BitPtr, slice::BitSlice, vec::BitVec};
-use hashbrown::{HashTable, hash_map::DefaultHashBuilder as DefaultBuildHasher};
+use hashbrown::HashTable;
 use serde::{Deserialize, Serialize};
 use std::{
     any::{Any, TypeId},
diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs
index 1fcb529..920b0af 100644
--- a/crates/fayalite/src/module.rs
+++ b/crates/fayalite/src/module.rs
@@ -24,10 +24,10 @@ use crate::{
     sim::{ExternModuleSimGenerator, ExternModuleSimulation},
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
-    util::ScopedRef,
+    util::{HashMap, HashSet, ScopedRef},
     wire::{IncompleteWire, Wire},
 };
-use hashbrown::{hash_map::Entry, HashMap, HashSet};
+use hashbrown::hash_map::Entry;
 use num_bigint::BigInt;
 use std::{
     cell::RefCell,
@@ -1498,7 +1498,7 @@ impl TargetState {
                         .collect(),
                 },
                 CanonicalType::PhantomConst(_) => TargetStateInner::Decomposed {
-                    subtargets: HashMap::new(),
+                    subtargets: HashMap::default(),
                 },
                 CanonicalType::Array(ty) => TargetStateInner::Decomposed {
                     subtargets: (0..ty.len())
@@ -1864,7 +1864,7 @@ impl<T: BundleType> Module<T> {
         AssertValidityState {
             module: self.canonical(),
             blocks: vec![],
-            target_states: HashMap::with_capacity(64),
+            target_states: HashMap::with_capacity_and_hasher(64, Default::default()),
         }
         .assert_validity();
     }
@@ -2125,8 +2125,8 @@ impl ModuleBuilder {
                         incomplete_declarations: vec![],
                         stmts: vec![],
                     }],
-                    annotations_map: HashMap::new(),
-                    memory_map: HashMap::new(),
+                    annotations_map: HashMap::default(),
+                    memory_map: HashMap::default(),
                 },
             }),
         };
@@ -2136,7 +2136,7 @@ impl ModuleBuilder {
             impl_: RefCell::new(ModuleBuilderImpl {
                 body,
                 io: vec![],
-                io_indexes: HashMap::new(),
+                io_indexes: HashMap::default(),
                 module_annotations: vec![],
             }),
         };
diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs
index a70dc33..5fb829e 100644
--- a/crates/fayalite/src/module/transform/deduce_resets.rs
+++ b/crates/fayalite/src/module/transform/deduce_resets.rs
@@ -24,8 +24,9 @@ use crate::{
     },
     prelude::*,
     reset::{ResetType, ResetTypeDispatch},
+    util::{HashMap, HashSet},
 };
-use hashbrown::{hash_map::Entry, HashMap, HashSet};
+use hashbrown::hash_map::Entry;
 use num_bigint::BigInt;
 use petgraph::unionfind::UnionFind;
 use std::{fmt, marker::PhantomData};
@@ -2251,9 +2252,9 @@ pub fn deduce_resets(
     fallback_to_sync_reset: bool,
 ) -> Result<Interned<Module<Bundle>>, DeduceResetsError> {
     let mut state = State {
-        modules_added_to_graph: HashSet::new(),
-        substituted_modules: HashMap::new(),
-        expr_resets: HashMap::new(),
+        modules_added_to_graph: HashSet::default(),
+        substituted_modules: HashMap::default(),
+        expr_resets: HashMap::default(),
         reset_graph: ResetGraph::default(),
         fallback_to_sync_reset,
     };
diff --git a/crates/fayalite/src/module/transform/simplify_enums.rs b/crates/fayalite/src/module/transform/simplify_enums.rs
index e8b6168..333451d 100644
--- a/crates/fayalite/src/module/transform/simplify_enums.rs
+++ b/crates/fayalite/src/module/transform/simplify_enums.rs
@@ -18,10 +18,10 @@ use crate::{
     },
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
+    util::HashMap,
     wire::Wire,
 };
 use core::fmt;
-use hashbrown::HashMap;
 
 #[derive(Debug)]
 pub enum SimplifyEnumsError {
@@ -965,8 +965,8 @@ pub fn simplify_enums(
     kind: SimplifyEnumsKind,
 ) -> Result<Interned<Module<Bundle>>, SimplifyEnumsError> {
     module.fold(&mut State {
-        enum_types: HashMap::new(),
-        replacement_mem_ports: HashMap::new(),
+        enum_types: HashMap::default(),
+        replacement_mem_ports: HashMap::default(),
         kind,
         module_state_stack: vec![],
     })
diff --git a/crates/fayalite/src/module/transform/simplify_memories.rs b/crates/fayalite/src/module/transform/simplify_memories.rs
index 101385e..6357843 100644
--- a/crates/fayalite/src/module/transform/simplify_memories.rs
+++ b/crates/fayalite/src/module/transform/simplify_memories.rs
@@ -14,11 +14,10 @@ use crate::{
     },
     source_location::SourceLocation,
     ty::{CanonicalType, Type},
-    util::MakeMutSlice,
+    util::{HashMap, MakeMutSlice},
     wire::Wire,
 };
 use bitvec::{slice::BitSlice, vec::BitVec};
-use hashbrown::HashMap;
 use std::{
     convert::Infallible,
     fmt::Write,
@@ -897,7 +896,7 @@ impl Folder for State {
             module,
             ModuleState {
                 output_module: None,
-                memories: HashMap::new(),
+                memories: HashMap::default(),
             },
         );
         let mut this = PushedState::push_module(self, module);
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index da7c293..b7845f4 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -41,10 +41,9 @@ use crate::{
         value::SimValue,
     },
     ty::StaticType,
-    util::{BitSliceWriteWithBase, DebugAsDisplay},
+    util::{BitSliceWriteWithBase, DebugAsDisplay, HashMap, HashSet},
 };
 use bitvec::{bits, order::Lsb0, slice::BitSlice, vec::BitVec, view::BitView};
-use hashbrown::{HashMap, HashSet};
 use num_bigint::BigInt;
 use num_traits::{Signed, Zero};
 use petgraph::{
@@ -580,8 +579,9 @@ impl Assignments {
             big_slots,
         }) = self.slot_readers();
         AssignmentsElements {
-            node_indexes: HashMap::with_capacity(
+            node_indexes: HashMap::with_capacity_and_hasher(
                 self.assignments().len() + small_slots.len() + big_slots.len(),
+                Default::default(),
             ),
             nodes: self.node_references(),
             edges: self.edge_references(),
@@ -1676,18 +1676,18 @@ impl Compiler {
             insns: Insns::new(),
             original_base_module,
             base_module,
-            modules: HashMap::new(),
+            modules: HashMap::default(),
             extern_modules: Vec::new(),
-            compiled_values: HashMap::new(),
-            compiled_exprs: HashMap::new(),
-            compiled_exprs_to_values: HashMap::new(),
-            decl_conditions: HashMap::new(),
-            compiled_values_to_dyn_array_indexes: HashMap::new(),
-            compiled_value_bool_dest_is_small_map: HashMap::new(),
+            compiled_values: HashMap::default(),
+            compiled_exprs: HashMap::default(),
+            compiled_exprs_to_values: HashMap::default(),
+            decl_conditions: HashMap::default(),
+            compiled_values_to_dyn_array_indexes: HashMap::default(),
+            compiled_value_bool_dest_is_small_map: HashMap::default(),
             assignments: Assignments::default(),
             clock_triggers: Vec::new(),
-            compiled_value_to_clock_trigger_map: HashMap::new(),
-            enum_discriminants: HashMap::new(),
+            compiled_value_to_clock_trigger_map: HashMap::default(),
+            enum_discriminants: HashMap::default(),
             registers: Vec::new(),
             traces: SimTraces(Vec::new()),
             memories: Vec::new(),
@@ -5976,8 +5976,8 @@ impl SimulationModuleState {
     fn new(base_targets: impl IntoIterator<Item = (Target, CompiledValue<CanonicalType>)>) -> Self {
         let mut retval = Self {
             base_targets: Vec::new(),
-            uninitialized_ios: HashMap::new(),
-            io_targets: HashMap::new(),
+            uninitialized_ios: HashMap::default(),
+            io_targets: HashMap::default(),
             did_initial_settle: false,
         };
         for (base_target, value) in base_targets {
@@ -6207,7 +6207,7 @@ impl Default for EarliestWaitTargets {
         Self {
             settle: false,
             instant: None,
-            changes: HashMap::new(),
+            changes: HashMap::default(),
         }
     }
 }
@@ -6217,14 +6217,14 @@ impl EarliestWaitTargets {
         Self {
             settle: true,
             instant: None,
-            changes: HashMap::new(),
+            changes: HashMap::default(),
         }
     }
     fn instant(instant: SimInstant) -> Self {
         Self {
             settle: false,
             instant: Some(instant),
-            changes: HashMap::new(),
+            changes: HashMap::default(),
         }
     }
     fn len(&self) -> usize {
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index 22f6f5f..de582f0 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -7,10 +7,9 @@ use crate::{
     intern::{Intern, Interned, Memoize},
     source_location::SourceLocation,
     ty::CanonicalType,
-    util::get_many_mut,
+    util::{get_many_mut, HashMap, HashSet},
 };
 use bitvec::{boxed::BitBox, slice::BitSlice};
-use hashbrown::{HashMap, HashSet};
 use num_bigint::BigInt;
 use num_traits::{One, Signed, ToPrimitive, Zero};
 use std::{
diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs
index fde30be..fcf6743 100644
--- a/crates/fayalite/src/sim/vcd.rs
+++ b/crates/fayalite/src/sim/vcd.rs
@@ -14,9 +14,10 @@ use crate::{
         TraceModuleIO, TraceReg, TraceSInt, TraceScalar, TraceScalarId, TraceScope, TraceSyncReset,
         TraceUInt, TraceWire, TraceWriter, TraceWriterDecls,
     },
+    util::HashMap,
 };
 use bitvec::{order::Lsb0, slice::BitSlice};
-use hashbrown::{hash_map::Entry, HashMap};
+use hashbrown::hash_map::Entry;
 use std::{
     fmt::{self, Write as _},
     io, mem,
diff --git a/crates/fayalite/src/source_location.rs b/crates/fayalite/src/source_location.rs
index d143f22..1a168b1 100644
--- a/crates/fayalite/src/source_location.rs
+++ b/crates/fayalite/src/source_location.rs
@@ -2,9 +2,8 @@
 // See Notices.txt for copyright information
 use crate::{
     intern::{Intern, Interned},
-    util::DebugAsDisplay,
+    util::{DebugAsDisplay, HashMap},
 };
-use hashbrown::HashMap;
 use std::{cell::RefCell, fmt, num::NonZeroUsize, panic, path::Path};
 
 #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
@@ -97,7 +96,7 @@ impl NormalizeFilesForTestsState {
     fn new() -> Self {
         Self {
             test_position: panic::Location::caller(),
-            file_pattern_matches: HashMap::new(),
+            file_pattern_matches: HashMap::default(),
         }
     }
 }
@@ -143,7 +142,7 @@ impl From<&'_ panic::Location<'_>> for SourceLocation {
                         map.entry_ref(file)
                             .or_insert_with(|| NormalizedFileForTestState {
                                 file_name_id: NonZeroUsize::new(len + 1).unwrap(),
-                                positions_map: HashMap::new(),
+                                positions_map: HashMap::default(),
                             });
                     file_str = m.generate_file_name(file_state.file_name_id);
                     file = &file_str;
diff --git a/crates/fayalite/src/testing.rs b/crates/fayalite/src/testing.rs
index 4517e34..b81bc3f 100644
--- a/crates/fayalite/src/testing.rs
+++ b/crates/fayalite/src/testing.rs
@@ -3,9 +3,9 @@
 use crate::{
     cli::{FormalArgs, FormalMode, FormalOutput, RunPhase},
     firrtl::ExportOptions,
+    util::HashMap,
 };
 use clap::Parser;
-use hashbrown::HashMap;
 use serde::Deserialize;
 use std::{
     fmt::Write,
@@ -87,7 +87,7 @@ fn get_assert_formal_target_path(test_name: &dyn std::fmt::Display) -> PathBuf {
     let index = *DIRS
         .lock()
         .unwrap()
-        .get_or_insert_with(HashMap::new)
+        .get_or_insert_with(HashMap::default)
         .entry_ref(&dir)
         .and_modify(|v| *v += 1)
         .or_insert(0);
diff --git a/crates/fayalite/src/util.rs b/crates/fayalite/src/util.rs
index 804ff19..8d90135 100644
--- a/crates/fayalite/src/util.rs
+++ b/crates/fayalite/src/util.rs
@@ -9,6 +9,12 @@ mod misc;
 mod scoped_ref;
 pub(crate) mod streaming_read_utf8;
 
+// allow easily switching the hasher crate-wide for testing
+pub(crate) type DefaultBuildHasher = hashbrown::hash_map::DefaultHashBuilder;
+
+pub(crate) type HashMap<K, V> = hashbrown::HashMap<K, V, DefaultBuildHasher>;
+pub(crate) type HashSet<T> = hashbrown::HashSet<T, DefaultBuildHasher>;
+
 #[doc(inline)]
 pub use const_bool::{ConstBool, ConstBoolDispatch, ConstBoolDispatchTag, GenericConstBool};
 #[doc(inline)]

From 122c08d3cf8668ed80a01e30f4b75a3f7fdf6d3d Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 9 Apr 2025 20:21:43 -0700
Subject: [PATCH 184/190] add fake which for miri

---
 crates/fayalite/src/cli.rs | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/crates/fayalite/src/cli.rs b/crates/fayalite/src/cli.rs
index 66741ef..1f208a8 100644
--- a/crates/fayalite/src/cli.rs
+++ b/crates/fayalite/src/cli.rs
@@ -258,7 +258,7 @@ pub struct VerilogArgs {
         default_value = "firtool",
         env = "FIRTOOL",
         value_hint = ValueHint::CommandName,
-        value_parser = OsStringValueParser::new().try_map(which::which)
+        value_parser = OsStringValueParser::new().try_map(which)
     )]
     pub firtool: PathBuf,
     #[arg(long)]
@@ -428,6 +428,13 @@ impl clap::Args for FormalAdjustArgs {
     }
 }
 
+fn which(v: std::ffi::OsString) -> which::Result<PathBuf> {
+    #[cfg(not(miri))]
+    return which::which(v);
+    #[cfg(miri)]
+    return Ok(Path::new("/").join(v));
+}
+
 #[derive(Parser, Clone)]
 #[non_exhaustive]
 pub struct FormalArgs {
@@ -438,7 +445,7 @@ pub struct FormalArgs {
         default_value = "sby",
         env = "SBY",
         value_hint = ValueHint::CommandName,
-        value_parser = OsStringValueParser::new().try_map(which::which)
+        value_parser = OsStringValueParser::new().try_map(which)
     )]
     pub sby: PathBuf,
     #[arg(long)]

From 4eda4366c86ab3b4edfb6f388f7ff864c6344d52 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 9 Apr 2025 20:23:19 -0700
Subject: [PATCH 185/190] check types in debug mode in impl Debug for Expr,
 helping to catch bugs

---
 crates/fayalite/src/expr.rs | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/crates/fayalite/src/expr.rs b/crates/fayalite/src/expr.rs
index f511c97..e070674 100644
--- a/crates/fayalite/src/expr.rs
+++ b/crates/fayalite/src/expr.rs
@@ -274,6 +274,17 @@ pub struct Expr<T: Type> {
 
 impl<T: Type + fmt::Debug> fmt::Debug for Expr<T> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        #[cfg(debug_assertions)]
+        {
+            let Self {
+                __enum,
+                __ty,
+                __flow,
+            } = self;
+            let expr_ty = __ty.canonical();
+            let enum_ty = __enum.to_expr().__ty;
+            assert_eq!(expr_ty, enum_ty, "expr ty mismatch:\nExpr {{\n__enum: {__enum:?},\n__ty: {__ty:?},\n__flow: {__flow:?}\n}}");
+        }
         self.__enum.fmt(f)
     }
 }

From b1f9706e4e06d6a8c6b23832b7e6551865cb464f Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 9 Apr 2025 20:24:39 -0700
Subject: [PATCH 186/190] add custom hasher for testing

---
 crates/fayalite/Cargo.toml              |   1 +
 crates/fayalite/src/util.rs             |   4 +
 crates/fayalite/src/util/test_hasher.rs | 240 ++++++++++++++++++++++++
 3 files changed, 245 insertions(+)
 create mode 100644 crates/fayalite/src/util/test_hasher.rs

diff --git a/crates/fayalite/Cargo.toml b/crates/fayalite/Cargo.toml
index 2652792..f176698 100644
--- a/crates/fayalite/Cargo.toml
+++ b/crates/fayalite/Cargo.toml
@@ -40,6 +40,7 @@ fayalite-visit-gen.workspace = true
 
 [features]
 unstable-doc = []
+unstable-test-hasher = []
 
 [package.metadata.docs.rs]
 features = ["unstable-doc"]
diff --git a/crates/fayalite/src/util.rs b/crates/fayalite/src/util.rs
index 8d90135..ebc3f6d 100644
--- a/crates/fayalite/src/util.rs
+++ b/crates/fayalite/src/util.rs
@@ -8,8 +8,12 @@ mod const_usize;
 mod misc;
 mod scoped_ref;
 pub(crate) mod streaming_read_utf8;
+mod test_hasher;
 
 // allow easily switching the hasher crate-wide for testing
+#[cfg(feature = "unstable-test-hasher")]
+pub type DefaultBuildHasher = test_hasher::DefaultBuildHasher;
+#[cfg(not(feature = "unstable-test-hasher"))]
 pub(crate) type DefaultBuildHasher = hashbrown::hash_map::DefaultHashBuilder;
 
 pub(crate) type HashMap<K, V> = hashbrown::HashMap<K, V, DefaultBuildHasher>;
diff --git a/crates/fayalite/src/util/test_hasher.rs b/crates/fayalite/src/util/test_hasher.rs
new file mode 100644
index 0000000..2a0cdd4
--- /dev/null
+++ b/crates/fayalite/src/util/test_hasher.rs
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+#![cfg(feature = "unstable-test-hasher")]
+
+use std::{
+    fmt::Write as _,
+    hash::{BuildHasher, Hash, Hasher},
+    io::Write as _,
+    marker::PhantomData,
+    sync::LazyLock,
+};
+
+type BoxDynHasher = Box<dyn Hasher + Send + Sync>;
+type BoxDynBuildHasher = Box<dyn DynBuildHasherTrait + Send + Sync>;
+type BoxDynMakeBuildHasher = Box<dyn Fn() -> BoxDynBuildHasher + Send + Sync>;
+
+trait TryGetDynBuildHasher: Copy {
+    type Type;
+    fn try_get_make_build_hasher(self) -> Option<BoxDynMakeBuildHasher>;
+}
+
+impl<T> TryGetDynBuildHasher for PhantomData<T> {
+    type Type = T;
+    fn try_get_make_build_hasher(self) -> Option<BoxDynMakeBuildHasher> {
+        None
+    }
+}
+
+impl<T: Default + BuildHasher<Hasher: Send + Sync + 'static> + Send + Sync + 'static + Clone>
+    TryGetDynBuildHasher for &'_ PhantomData<T>
+{
+    type Type = T;
+    fn try_get_make_build_hasher(self) -> Option<BoxDynMakeBuildHasher> {
+        Some(Box::new(|| Box::<DynBuildHasher<T>>::default()))
+    }
+}
+
+#[derive(Default, Clone)]
+struct DynBuildHasher<T>(T);
+
+trait DynBuildHasherTrait: BuildHasher<Hasher = BoxDynHasher> {
+    fn clone_dyn_build_hasher(&self) -> BoxDynBuildHasher;
+}
+
+impl<BH: BuildHasher<Hasher: Send + Sync + 'static>> BuildHasher for DynBuildHasher<BH> {
+    type Hasher = BoxDynHasher;
+
+    fn build_hasher(&self) -> Self::Hasher {
+        Box::new(self.0.build_hasher())
+    }
+
+    fn hash_one<T: Hash>(&self, x: T) -> u64 {
+        self.0.hash_one(x)
+    }
+}
+
+impl<BH> DynBuildHasherTrait for DynBuildHasher<BH>
+where
+    Self: Clone + BuildHasher<Hasher = BoxDynHasher> + Send + Sync + 'static,
+{
+    fn clone_dyn_build_hasher(&self) -> BoxDynBuildHasher {
+        Box::new(self.clone())
+    }
+}
+
+pub struct DefaultBuildHasher(BoxDynBuildHasher);
+
+impl Clone for DefaultBuildHasher {
+    fn clone(&self) -> Self {
+        DefaultBuildHasher(self.0.clone_dyn_build_hasher())
+    }
+}
+
+const ENV_VAR_NAME: &'static str = "FAYALITE_TEST_HASHER";
+
+struct EnvVarValue {
+    key: &'static str,
+    try_get_make_build_hasher: fn() -> Option<BoxDynMakeBuildHasher>,
+    description: &'static str,
+}
+
+macro_rules! env_var_value {
+    (
+        key: $key:literal,
+        build_hasher: $build_hasher:ty,
+        description: $description:literal,
+    ) => {
+        EnvVarValue {
+            key: $key,
+            try_get_make_build_hasher: || {
+                // use rust method resolution to detect if $build_hasher is usable
+                // (e.g. hashbrown's hasher won't be usable without the right feature enabled)
+                (&PhantomData::<DynBuildHasher<$build_hasher>>).try_get_make_build_hasher()
+            },
+            description: $description,
+        }
+    };
+}
+
+#[derive(Default)]
+struct AlwaysZeroHasher;
+
+impl Hasher for AlwaysZeroHasher {
+    fn write(&mut self, _bytes: &[u8]) {}
+    fn finish(&self) -> u64 {
+        0
+    }
+}
+
+const ENV_VAR_VALUES: &'static [EnvVarValue] = &[
+    env_var_value! {
+        key: "std",
+        build_hasher: std::hash::RandomState,
+        description: "use std::hash::RandomState",
+    },
+    env_var_value! {
+        key: "hashbrown",
+        build_hasher: hashbrown::hash_map::DefaultHashBuilder,
+        description: "use hashbrown's DefaultHashBuilder",
+    },
+    env_var_value! {
+        key: "always_zero",
+        build_hasher: std::hash::BuildHasherDefault<AlwaysZeroHasher>,
+        description: "use a hasher that always returns 0 for all hashes,\n    \
+        this is useful for checking that PartialEq impls are correct",
+    },
+];
+
+fn report_bad_env_var(msg: impl std::fmt::Display) -> ! {
+    let mut msg = format!("{ENV_VAR_NAME}: {msg}\n");
+    for &EnvVarValue {
+        key,
+        try_get_make_build_hasher,
+        description,
+    } in ENV_VAR_VALUES
+    {
+        let availability = match try_get_make_build_hasher() {
+            Some(_) => "available",
+            None => "unavailable",
+        };
+        writeln!(msg, "{key}: ({availability})\n    {description}").expect("can't fail");
+    }
+    std::io::stderr()
+        .write_all(msg.as_bytes())
+        .expect("should be able to write to stderr");
+    std::process::abort();
+}
+
+impl Default for DefaultBuildHasher {
+    fn default() -> Self {
+        static DEFAULT_FN: LazyLock<BoxDynMakeBuildHasher> = LazyLock::new(|| {
+            let var = std::env::var_os(ENV_VAR_NAME);
+            let var = var.as_deref().unwrap_or("std".as_ref());
+            for &EnvVarValue {
+                key,
+                try_get_make_build_hasher,
+                description: _,
+            } in ENV_VAR_VALUES
+            {
+                if var.as_encoded_bytes().eq_ignore_ascii_case(key.as_bytes()) {
+                    return try_get_make_build_hasher().unwrap_or_else(|| {
+                        report_bad_env_var(format_args!(
+                            "unavailable hasher: {key} (is the appropriate feature enabled?)"
+                        ));
+                    });
+                }
+            }
+            report_bad_env_var(format_args!("unrecognized hasher: {var:?}"));
+        });
+        Self(DEFAULT_FN())
+    }
+}
+
+pub struct DefaultHasher(BoxDynHasher);
+
+impl BuildHasher for DefaultBuildHasher {
+    type Hasher = DefaultHasher;
+
+    fn build_hasher(&self) -> Self::Hasher {
+        DefaultHasher(self.0.build_hasher())
+    }
+}
+
+impl Hasher for DefaultHasher {
+    fn finish(&self) -> u64 {
+        self.0.finish()
+    }
+
+    fn write(&mut self, bytes: &[u8]) {
+        self.0.write(bytes)
+    }
+
+    fn write_u8(&mut self, i: u8) {
+        self.0.write_u8(i)
+    }
+
+    fn write_u16(&mut self, i: u16) {
+        self.0.write_u16(i)
+    }
+
+    fn write_u32(&mut self, i: u32) {
+        self.0.write_u32(i)
+    }
+
+    fn write_u64(&mut self, i: u64) {
+        self.0.write_u64(i)
+    }
+
+    fn write_u128(&mut self, i: u128) {
+        self.0.write_u128(i)
+    }
+
+    fn write_usize(&mut self, i: usize) {
+        self.0.write_usize(i)
+    }
+
+    fn write_i8(&mut self, i: i8) {
+        self.0.write_i8(i)
+    }
+
+    fn write_i16(&mut self, i: i16) {
+        self.0.write_i16(i)
+    }
+
+    fn write_i32(&mut self, i: i32) {
+        self.0.write_i32(i)
+    }
+
+    fn write_i64(&mut self, i: i64) {
+        self.0.write_i64(i)
+    }
+
+    fn write_i128(&mut self, i: i128) {
+        self.0.write_i128(i)
+    }
+
+    fn write_isize(&mut self, i: isize) {
+        self.0.write_isize(i)
+    }
+}

From e2d2d4110be5d15e0bdc1eb81bd84ed7786c3ad8 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 9 Apr 2025 20:33:21 -0700
Subject: [PATCH 187/190] upgrade hashbrown to 0.15.2

---
 Cargo.lock                              | 51 ++++++++-----------------
 Cargo.toml                              |  2 +-
 crates/fayalite/src/util.rs             |  2 +-
 crates/fayalite/src/util/test_hasher.rs |  2 +-
 4 files changed, 19 insertions(+), 38 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 23cdc34..611e42e 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -2,18 +2,6 @@
 # It is not intended for manual editing.
 version = 3
 
-[[package]]
-name = "ahash"
-version = "0.8.7"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "77c3a9648d43b9cd48db467b3f87fdd6e146bcc88ab0180006cef2179fe11d01"
-dependencies = [
- "cfg-if",
- "once_cell",
- "version_check",
- "zerocopy",
-]
-
 [[package]]
 name = "allocator-api2"
 version = "0.2.16"
@@ -310,7 +298,7 @@ dependencies = [
  "eyre",
  "fayalite-proc-macros",
  "fayalite-visit-gen",
- "hashbrown",
+ "hashbrown 0.15.2",
  "jobslot",
  "num-bigint",
  "num-traits",
@@ -365,6 +353,12 @@ version = "0.5.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "1d674e81391d1e1ab681a28d99df07927c6d4aa5b027d7da16ba32d1d21ecd99"
 
+[[package]]
+name = "foldhash"
+version = "0.1.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2"
+
 [[package]]
 name = "funty"
 version = "2.0.0"
@@ -403,9 +397,16 @@ name = "hashbrown"
 version = "0.14.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "290f1a1d9242c78d09ce40a5e87e7554ee637af1351968159f4952f028f75604"
+
+[[package]]
+name = "hashbrown"
+version = "0.15.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "bf151400ff0baff5465007dd2f3e717f3fe502074ca563069ce3a6629d07b289"
 dependencies = [
- "ahash",
  "allocator-api2",
+ "equivalent",
+ "foldhash",
 ]
 
 [[package]]
@@ -436,7 +437,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "68b900aa2f7301e21c36462b170ee99994de34dff39a4a6a528e80e7376d07e5"
 dependencies = [
  "equivalent",
- "hashbrown",
+ "hashbrown 0.14.3",
  "serde",
 ]
 
@@ -893,23 +894,3 @@ checksum = "05f360fc0b24296329c78fda852a1e9ae82de9cf7b27dae4b7f62f118f77b9ed"
 dependencies = [
  "tap",
 ]
-
-[[package]]
-name = "zerocopy"
-version = "0.7.32"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "74d4d3961e53fa4c9a25a8637fc2bfaf2595b3d3ae34875568a5cf64787716be"
-dependencies = [
- "zerocopy-derive",
-]
-
-[[package]]
-name = "zerocopy-derive"
-version = "0.7.32"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9ce1b18ccd8e73a9321186f97e46f9f04b778851177567b1975109d26a08d2a6"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
-]
diff --git a/Cargo.toml b/Cargo.toml
index 54de3a8..8a022c9 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -23,7 +23,7 @@ blake3 = { version = "1.5.4", features = ["serde"] }
 clap = { version = "4.5.9", features = ["derive", "env", "string"] }
 ctor = "0.2.8"
 eyre = "0.6.12"
-hashbrown = "0.14.3"
+hashbrown = "0.15.2"
 indexmap = { version = "2.5.0", features = ["serde"] }
 jobslot = "0.2.19"
 num-bigint = "0.4.6"
diff --git a/crates/fayalite/src/util.rs b/crates/fayalite/src/util.rs
index ebc3f6d..233867e 100644
--- a/crates/fayalite/src/util.rs
+++ b/crates/fayalite/src/util.rs
@@ -14,7 +14,7 @@ mod test_hasher;
 #[cfg(feature = "unstable-test-hasher")]
 pub type DefaultBuildHasher = test_hasher::DefaultBuildHasher;
 #[cfg(not(feature = "unstable-test-hasher"))]
-pub(crate) type DefaultBuildHasher = hashbrown::hash_map::DefaultHashBuilder;
+pub(crate) type DefaultBuildHasher = hashbrown::DefaultHashBuilder;
 
 pub(crate) type HashMap<K, V> = hashbrown::HashMap<K, V, DefaultBuildHasher>;
 pub(crate) type HashSet<T> = hashbrown::HashSet<T, DefaultBuildHasher>;
diff --git a/crates/fayalite/src/util/test_hasher.rs b/crates/fayalite/src/util/test_hasher.rs
index 2a0cdd4..20df5b7 100644
--- a/crates/fayalite/src/util/test_hasher.rs
+++ b/crates/fayalite/src/util/test_hasher.rs
@@ -115,7 +115,7 @@ const ENV_VAR_VALUES: &'static [EnvVarValue] = &[
     },
     env_var_value! {
         key: "hashbrown",
-        build_hasher: hashbrown::hash_map::DefaultHashBuilder,
+        build_hasher: hashbrown::DefaultHashBuilder,
         description: "use hashbrown's DefaultHashBuilder",
     },
     env_var_value! {

From 91e1b619e8e6c4130cc7e80bd683625b1ec3cd9d Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 9 Apr 2025 20:48:40 -0700
Subject: [PATCH 188/190] switch to petgraph 0.8.1 now that my PR was merged
 and released to crates.io

---
 Cargo.lock                 | 21 +++++++++------------
 Cargo.toml                 |  3 +--
 crates/fayalite/src/sim.rs | 10 ++++++++++
 3 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 611e42e..e0c32e9 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -298,7 +298,7 @@ dependencies = [
  "eyre",
  "fayalite-proc-macros",
  "fayalite-visit-gen",
- "hashbrown 0.15.2",
+ "hashbrown",
  "jobslot",
  "num-bigint",
  "num-traits",
@@ -392,12 +392,6 @@ version = "0.3.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "d2fabcfbdc87f4758337ca535fb41a6d701b65693ce38287d856d1674551ec9b"
 
-[[package]]
-name = "hashbrown"
-version = "0.14.3"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "290f1a1d9242c78d09ce40a5e87e7554ee637af1351968159f4952f028f75604"
-
 [[package]]
 name = "hashbrown"
 version = "0.15.2"
@@ -432,12 +426,12 @@ checksum = "ce23b50ad8242c51a442f3ff322d56b02f08852c77e4c0b4d3fd684abc89c683"
 
 [[package]]
 name = "indexmap"
-version = "2.5.0"
+version = "2.9.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "68b900aa2f7301e21c36462b170ee99994de34dff39a4a6a528e80e7376d07e5"
+checksum = "cea70ddb795996207ad57735b50c5982d8844f38ba9ee5f1aedcfb708a2aa11e"
 dependencies = [
  "equivalent",
- "hashbrown 0.14.3",
+ "hashbrown",
  "serde",
 ]
 
@@ -525,11 +519,14 @@ dependencies = [
 
 [[package]]
 name = "petgraph"
-version = "0.6.5"
-source = "git+https://github.com/programmerjake/petgraph.git?rev=258ea8071209a924b73fe96f9f87a3b7b45cbc9f#258ea8071209a924b73fe96f9f87a3b7b45cbc9f"
+version = "0.8.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7a98c6720655620a521dcc722d0ad66cd8afd5d86e34a89ef691c50b7b24de06"
 dependencies = [
  "fixedbitset",
+ "hashbrown",
  "indexmap",
+ "serde",
 ]
 
 [[package]]
diff --git a/Cargo.toml b/Cargo.toml
index 8a022c9..d681425 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -29,8 +29,7 @@ jobslot = "0.2.19"
 num-bigint = "0.4.6"
 num-traits = "0.2.16"
 os_pipe = "1.2.1"
-# TODO: switch back to crates.io once petgraph accepts PR #684 and releases a new version
-petgraph = { git = "https://github.com/programmerjake/petgraph.git", rev = "258ea8071209a924b73fe96f9f87a3b7b45cbc9f" }
+petgraph = "0.8.1"
 prettyplease = "0.2.20"
 proc-macro2 = "1.0.83"
 quote = "1.0.36"
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index b7845f4..6659391 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -1022,6 +1022,16 @@ impl VisitMap<AssignmentOrSlotIndex> for AssignmentsVisitMap {
             AssignmentOrSlotIndex::BigSlot(slot) => self.slots.contains(slot),
         }
     }
+
+    fn unvisit(&mut self, n: AssignmentOrSlotIndex) -> bool {
+        match n {
+            AssignmentOrSlotIndex::AssignmentIndex(assignment_index) => {
+                mem::replace(&mut self.assignments[assignment_index], false)
+            }
+            AssignmentOrSlotIndex::SmallSlot(slot) => self.slots.remove(slot),
+            AssignmentOrSlotIndex::BigSlot(slot) => self.slots.remove(slot),
+        }
+    }
 }
 
 impl Visitable for Assignments {

From 88323a8c164d54966ddde60a73f0132d732cd3f8 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 9 Apr 2025 21:03:57 -0700
Subject: [PATCH 189/190] run some tests with always_zero hasher

---
 .forgejo/workflows/test.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index 49fb3e4..d878758 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -59,3 +59,4 @@ jobs:
       - run: cargo build --tests --features=unstable-doc
       - run: cargo test --doc --features=unstable-doc
       - run: cargo doc --features=unstable-doc
+      - run: cargo test --test=module --features=unstable-doc,unstable-test-hasher

From 668e714dc98231eca52541aadd7ce160cfed3f90 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 9 Apr 2025 21:11:09 -0700
Subject: [PATCH 190/190] actually test always_zero hasher

---
 .forgejo/workflows/test.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index d878758..b2d03ba 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -59,4 +59,4 @@ jobs:
       - run: cargo build --tests --features=unstable-doc
       - run: cargo test --doc --features=unstable-doc
       - run: cargo doc --features=unstable-doc
-      - run: cargo test --test=module --features=unstable-doc,unstable-test-hasher
+      - run: FAYALITE_TEST_HASHER=always_zero cargo test --test=module --features=unstable-doc,unstable-test-hasher