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non-working build on TLII (using QEMU for x86 binaries)
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This commit is contained in:
Tobias Platen 2026-05-24 14:05:49 +02:00
parent 34b4a57507
commit fd2c635343
6 changed files with 1811 additions and 61 deletions
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2
crates/fayalite/src/vendor/lattice.rs vendored
View file

@ -144,7 +144,7 @@ macro_rules! make_device_enum {
};
}
//ECP5 variants
//ECP5 variants -- needs fixme
make_device_enum! {
pub enum Device {
#[

96
crates/fayalite/src/vendor/lattice/orangecrab.rs vendored
View file

@ -66,20 +66,20 @@ orangecrab_platform! {
}
}
//FIXME
//FIXME rename
#[derive(Debug)]
pub struct ArtyA7Peripherals {
clk100_div_pow2: [Peripheral<ClockInput>; 4],
rst: Peripheral<Reset>,
rst_sync: Peripheral<SyncReset>,
ld0: Peripheral<RgbLed>,
ld1: Peripheral<RgbLed>,
ld2: Peripheral<RgbLed>,
ld3: Peripheral<RgbLed>,
ld4: Peripheral<Led>,
ld5: Peripheral<Led>,
ld6: Peripheral<Led>,
ld7: Peripheral<Led>,
//ld1: Peripheral<RgbLed>,
//ld2: Peripheral<RgbLed>,
//ld3: Peripheral<RgbLed>,
//ld4: Peripheral<Led>,
//ld5: Peripheral<Led>,
//ld6: Peripheral<Led>,
//ld7: Peripheral<Led>,
uart: Peripheral<Uart>,
// TODO: add rest of peripherals when we need them
}
@ -91,26 +91,26 @@ impl Peripherals for ArtyA7Peripherals {
rst,
rst_sync,
ld0,
ld1,
ld2,
ld3,
ld4,
ld5,
ld6,
ld7,
//ld1,
//ld2,
//ld3,
//ld4,
//ld5,
//ld6,
//ld7,
uart,
} = self;
clk100_div_pow2.append_peripherals(peripherals);
rst.append_peripherals(peripherals);
rst_sync.append_peripherals(peripherals);
ld0.append_peripherals(peripherals);
ld1.append_peripherals(peripherals);
ld2.append_peripherals(peripherals);
ld3.append_peripherals(peripherals);
ld4.append_peripherals(peripherals);
ld5.append_peripherals(peripherals);
ld6.append_peripherals(peripherals);
ld7.append_peripherals(peripherals);
//ld1.append_peripherals(peripherals);
//ld2.append_peripherals(peripherals);
//ld3.append_peripherals(peripherals);
//ld4.append_peripherals(peripherals);
//ld5.append_peripherals(peripherals);
//ld6.append_peripherals(peripherals);
//ld7.append_peripherals(peripherals);
uart.append_peripherals(peripherals);
}
}
@ -175,13 +175,13 @@ impl Platform for OrangeCrabPlatform {
rst: builder.input_peripheral("rst", Reset),
rst_sync: builder.input_peripheral("rst_sync", SyncReset),
ld0: builder.output_peripheral("ld0", RgbLed),
ld1: builder.output_peripheral("ld1", RgbLed),
ld2: builder.output_peripheral("ld2", RgbLed),
ld3: builder.output_peripheral("ld3", RgbLed),
ld4: builder.output_peripheral("ld4", Led),
ld5: builder.output_peripheral("ld5", Led),
ld6: builder.output_peripheral("ld6", Led),
ld7: builder.output_peripheral("ld7", Led),
//ld1: builder.output_peripheral("ld1", RgbLed),
//ld2: builder.output_peripheral("ld2", RgbLed),
//ld3: builder.output_peripheral("ld3", RgbLed),
//ld4: builder.output_peripheral("ld4", Led),
//ld5: builder.output_peripheral("ld5", Led),
//ld6: builder.output_peripheral("ld6", Led),
//ld7: builder.output_peripheral("ld7", Led),
uart: builder.output_peripheral("uart", Uart),
},
builder.finish(),
@ -198,13 +198,13 @@ impl Platform for OrangeCrabPlatform {
rst,
rst_sync,
ld0,
ld1,
ld2,
ld3,
ld4,
ld5,
ld6,
ld7,
//ld1,
//ld2,
//ld3,
//ld4,
//ld5,
//ld6,
//ld7,
uart,
} = peripherals;
let make_buffered_input = |name: &str, location: &str, io_standard: &str, invert: bool| {
@ -343,9 +343,9 @@ impl Platform for OrangeCrabPlatform {
}
let rgb_leds = [
(ld0, ("G6", "F6", "E1")),
(ld1, ("G3", "J4", "G4")),
(ld2, ("J3", "J2", "H4")),
(ld3, ("K1", "H6", "K2")),
//(ld1, ("G3", "J4", "G4")),
//(ld2, ("J3", "J2", "H4")),
//(ld3, ("K1", "H6", "K2")),
];
for (rgb_led, (r_loc, g_loc, b_loc)) in rgb_leds {
let r = make_buffered_output(&format!("{}_r", rgb_led.name()), r_loc, "LVCMOS33");
@ -361,15 +361,15 @@ impl Platform for OrangeCrabPlatform {
connect(b, false);
}
}
let leds = [(ld4, "H5"), (ld5, "J5"), (ld6, "T9"), (ld7, "T10")];
for (led, loc) in leds {
let o = make_buffered_output(&led.name(), loc, "LVCMOS33");
if let Some(led) = led.into_used() {
connect(o, led.instance_io_field().on);
} else {
connect(o, false);
}
}
//let leds = [(ld4, "H5"), (ld5, "J5"), (ld6, "T9"), (ld7, "T10")];
//for (led, loc) in leds {
// let o = make_buffered_output(&led.name(), loc, "LVCMOS33");
// if let Some(led) = led.into_used() {
// connect(o, led.instance_io_field().on);
// } else {
// connect(o, false);
// }
//}
let uart_tx = make_buffered_output("uart_tx", "D10", "LVCMOS33");
let uart_rx = make_buffered_input("uart_rx", "A9", "LVCMOS33", false);
if let Some(uart) = uart.into_used() {

9
crates/fayalite/src/vendor/lattice/yosys_nextpnr.rs vendored
View file

@ -713,11 +713,14 @@ impl ExternalCommand for YosysNextpnrRunNextpnr {
} = job.additional_job_data();
args.write_long_option_eq("json", json_file_name);
args.write_long_option_eq("textcfg",textcfg_file_name);
args.write_arg("--25k");
args.write_long_option_eq("write",routed_json_file_name);
args.write_arg("--85k"); //FIXME do not hardcode
args.write_long_option_eq("package","CSFBGA285");
args.write_long_option_eq("lpf","/tmp/orangecrab_r0.2.1.pcf");
args.write_arg("--lpf-allow-unconstrained");
args.write_long_option_eq("lpf","/home/alex/Hacking/FPGA/orangecrab/orangecrab-examples/fayalite/orangecrab_r0.2.1.pcf"); //just a quick test
//handwrite before adding new module, ask pj before cont
//HACK: args.write_arg("--lpf-allow-unconstrained");
//???args.write_display_arg(format_args!("--seed={nextpnr_lattice_seed}"));
//fix ERROR: failed to open LPF file '/tmp/orangecrab_r0.2.1.pcf' FIRST
}