diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs index cca0d82..59fbec7 100644 --- a/crates/fayalite/src/firrtl.rs +++ b/crates/fayalite/src/firrtl.rs @@ -2326,6 +2326,7 @@ impl<'a> Exporter<'a> { ModuleBody::Extern(ExternModuleBody { verilog_name, parameters, + clocks_for_past: _, simulation: _, }) => { let verilog_name = Ident(verilog_name); diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs index 6527043..5ffeaae 100644 --- a/crates/fayalite/src/module.rs +++ b/crates/fayalite/src/module.rs @@ -41,7 +41,6 @@ use std::{ marker::PhantomData, mem, num::NonZeroU64, - ops::Deref, rc::Rc, sync::atomic::AtomicU64, }; @@ -67,6 +66,8 @@ pub trait ModuleBuildingStatus: type ModuleBody: fmt::Debug; type StmtAnnotations: 'static + Send + Sync + Copy + Eq + Hash + fmt::Debug; type ModuleIOAnnotations; + type ExternModuleParameters: fmt::Debug; + type ExternModuleClocksForPast: fmt::Debug; } #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash, Default)] @@ -79,6 +80,8 @@ impl ModuleBuildingStatus for ModuleBuilt { type ModuleBody = Block; type StmtAnnotations = Interned<[TargetedAnnotation]>; type ModuleIOAnnotations = Interned<[TargetedAnnotation]>; + type ExternModuleParameters = Interned<[ExternModuleParameter]>; + type ExternModuleClocksForPast = Interned<[Target]>; } #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash, Default)] @@ -91,6 +94,8 @@ impl ModuleBuildingStatus for ModuleBuilding { type ModuleBody = BuilderModuleBody; type StmtAnnotations = (); type ModuleIOAnnotations = Vec; + type ExternModuleParameters = Vec; + type ExternModuleClocksForPast = Vec; } #[derive(Debug)] @@ -1080,26 +1085,65 @@ impl From for ModuleBody { } } +#[track_caller] +fn validate_clock_for_past( + clock_for_past: Option, + module_io: &[AnnotatedModuleIO], +) -> Target { + if let Some(clock_for_past) = clock_for_past { + assert_eq!( + clock_for_past.canonical_ty(), + Clock.canonical(), + "clock_for_past: clock is not of type Clock", + ); + if clock_for_past + .base() + .module_io() + .is_some_and(|v| module_io.iter().any(|module_io| module_io.module_io == *v)) + { + let mut target = clock_for_past; + while let Target::Child(child) = target { + match *child.path_element() { + TargetPathElement::BundleField(_) | TargetPathElement::ArrayElement(_) => {} + TargetPathElement::DynArrayElement(_) => { + panic!( + "clock_for_past: clock must be a static target (you can't use `Expr` array indexes):\n{clock_for_past:?}" + ); + } + } + target = *child.parent(); + } + return clock_for_past; + } + } + panic!("clock_for_past: clock must be some part of this module's I/O:\n{clock_for_past:?}"); +} + #[derive(PartialEq, Eq, Hash, Copy, Clone, Debug)] -pub struct ExternModuleBody< - P: Deref = Interned<[ExternModuleParameter]>, -> { +pub struct ExternModuleBody { pub verilog_name: Interned, - pub parameters: P, + pub parameters: S::ExternModuleParameters, + /// [`Clock`]s that the [`Simulation`] will store the past values of all [`ModuleIO`] for. + /// + /// [`Simulation`]: crate::sim::Simulation + pub clocks_for_past: S::ExternModuleClocksForPast, pub simulation: Option, } -impl From>> for ExternModuleBody { - fn from(value: ExternModuleBody>) -> Self { +impl From> for ExternModuleBody { + fn from(value: ExternModuleBody) -> Self { let ExternModuleBody { verilog_name, parameters, + clocks_for_past, simulation, } = value; let parameters = Intern::intern_owned(parameters); + let clocks_for_past = Intern::intern_owned(clocks_for_past); Self { verilog_name, parameters, + clocks_for_past, simulation, } } @@ -1112,15 +1156,12 @@ impl From for ModuleBody { } #[derive(Debug)] -pub enum ModuleBody< - S: ModuleBuildingStatus = ModuleBuilt, - P: Deref = Interned<[ExternModuleParameter]>, -> { +pub enum ModuleBody { Normal(NormalModuleBody), - Extern(ExternModuleBody

), + Extern(ExternModuleBody), } -pub(crate) type ModuleBodyBuilding = ModuleBody>; +pub(crate) type ModuleBodyBuilding = ModuleBody; impl ModuleBodyBuilding { pub(crate) fn builder_normal_body_opt( @@ -1141,9 +1182,7 @@ impl ModuleBodyBuilding { } } #[track_caller] - pub(crate) fn builder_extern_body( - &mut self, - ) -> &mut ExternModuleBody> { + pub(crate) fn builder_extern_body(&mut self) -> &mut ExternModuleBody { if let Self::Extern(v) = self { v } else { @@ -1297,11 +1336,13 @@ impl fmt::Debug for DebugModuleBody { ModuleBody::Extern(ExternModuleBody { verilog_name, parameters, + clocks_for_past, simulation, }) => { debug_struct .field("verilog_name", verilog_name) .field("parameters", parameters) + .field("clocks_for_past", clocks_for_past) .field("simulation", simulation); } } @@ -1780,8 +1821,13 @@ impl AssertValidityState { ModuleBody::Extern(ExternModuleBody { verilog_name: _, parameters: _, + clocks_for_past, simulation: _, - }) => {} + }) => { + for clock_for_past in clocks_for_past { + validate_clock_for_past(Some(clock_for_past), &self.module.module_io); + } + } ModuleBody::Normal(NormalModuleBody { body }) => { let body = self.make_block_index(body); assert_eq!(body, 0); @@ -1811,9 +1857,17 @@ impl Module { match &mut body { ModuleBody::Normal(_) => {} ModuleBody::Extern(ExternModuleBody { + verilog_name: _, + parameters: _, + clocks_for_past, simulation: Some(simulation), - .. }) => { + let mut clocks_for_past_set = HashSet::default(); + *clocks_for_past = clocks_for_past + .iter() + .copied() + .filter(|clock_for_past| clocks_for_past_set.insert(*clock_for_past)) + .collect(); if module_io.iter().any(|io| { !simulation .sim_io_to_generator_map @@ -2186,6 +2240,7 @@ impl ModuleBuilder { ModuleKind::Extern => ModuleBody::Extern(ExternModuleBody { verilog_name: name.0, parameters: vec![], + clocks_for_past: vec![], simulation: None, }), ModuleKind::Normal => ModuleBody::Normal(NormalModuleBody { @@ -2308,6 +2363,20 @@ impl ModuleBuilder { value: ExternModuleParameterValue::RawVerilog(raw_verilog.intern()), }); } + /// registers a [`Clock`] so you can use it with the [`ExternModuleSimulationState::read_past()`] family of functions. + /// + /// [`ExternModuleSimulationState::read_past()`]: crate::sim::ExternModuleSimulationState::read_past() + #[track_caller] + pub fn register_clock_for_past(&self, clock_for_past: impl ToExpr) { + let clock_for_past = clock_for_past.to_expr().target().as_deref().copied(); + let mut impl_ = self.impl_.borrow_mut(); + let clock_for_past = validate_clock_for_past(clock_for_past, &impl_.io); + impl_ + .body + .builder_extern_body() + .clocks_for_past + .push(clock_for_past); + } #[track_caller] pub fn extern_module_simulation(&self, generator: G) { let mut impl_ = self.impl_.borrow_mut(); diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs index e84d835..bd4e939 100644 --- a/crates/fayalite/src/module/transform/deduce_resets.rs +++ b/crates/fayalite/src/module/transform/deduce_resets.rs @@ -2073,6 +2073,7 @@ impl_run_pass_for_struct! { impl[] RunPass for ExternModuleBody { verilog_name: _, parameters: _, + clocks_for_past: _, simulation: _, } } diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index 01233cb..808ead4 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -24,7 +24,7 @@ use crate::{ sim::{ compiler::{ Compiled, CompiledBundleField, CompiledExternModule, CompiledTypeLayoutBody, - CompiledValue, + CompiledValue, ExternModuleClockForPast, }, interpreter::{ BreakAction, BreakpointsSet, RunResult, SmallUInt, State, @@ -57,7 +57,7 @@ use std::{ pin::{Pin, pin}, ptr, rc::Rc, - sync::{Arc, Mutex}, + sync::{Arc, Mutex, MutexGuard}, task::Poll, usize, }; @@ -1040,6 +1040,12 @@ impl MaybeNeedsSettle { MaybeNeedsSettle::NoSettleNeeded(v) => MaybeNeedsSettle::NoSettleNeeded(f(v)), } } + fn into_inner(self) -> T { + match self { + MaybeNeedsSettle::NeedsSettle(v) => v, + MaybeNeedsSettle::NoSettleNeeded(v) => v, + } + } } // workaround implementing FnOnce not being stable @@ -1074,6 +1080,7 @@ struct SimulationModuleState { uninitialized_ios: HashMap>, io_targets: HashMap>, did_initial_settle: bool, + clocks_for_past: HashMap, SimulationExternModuleClockForPast>, } impl fmt::Debug for SimulationModuleState { @@ -1083,23 +1090,37 @@ impl fmt::Debug for SimulationModuleState { uninitialized_ios, io_targets, did_initial_settle, + clocks_for_past, } = self; f.debug_struct("SimulationModuleState") .field("base_targets", base_targets) .field("uninitialized_ios", &SortedSetDebug(uninitialized_ios)) .field("io_targets", &SortedSetDebug(io_targets)) .field("did_initial_settle", did_initial_settle) + .field("clocks_for_past", &SortedMapDebug(clocks_for_past)) .finish() } } impl SimulationModuleState { - fn new(base_targets: impl IntoIterator)>) -> Self { + fn new( + base_targets: impl IntoIterator)>, + clocks_for_past: &[ExternModuleClockForPast], + ) -> Self { let mut retval = Self { base_targets: Vec::new(), uninitialized_ios: HashMap::default(), io_targets: HashMap::default(), did_initial_settle: false, + clocks_for_past: clocks_for_past + .iter() + .map(|clock_for_past| { + ( + clock_for_past.clock_for_past, + SimulationExternModuleClockForPast::new(clock_for_past), + ) + }) + .collect(), }; for (base_target, value) in base_targets { retval.base_targets.push(base_target); @@ -1255,7 +1276,7 @@ impl SimulationModuleState { } } #[track_caller] - fn read_helper( + fn read_helper_current( &self, io: Expr, which_module: WhichModule, @@ -1300,6 +1321,33 @@ impl SimulationModuleState { } } #[track_caller] + fn read_helper( + &self, + io: Expr, + read_time: ReadTime, + which_module: WhichModule, + ) -> MaybeNeedsSettle> { + match read_time { + ReadTime::Current => self.read_helper_current(io, which_module), + ReadTime::Past { clock_for_past } => { + let current = self.read_helper_current(io, which_module); + let clock_for_past_value = self + .read_helper_current(Expr::canonical(clock_for_past), which_module) + .into_inner() + .map_ty(Clock::from_canonical); + let Some(clock_for_past) = self.clocks_for_past.get(&clock_for_past_value) else { + panic!( + "In order to use the `read_past()` family of functions,\n\ + you must call `m.register_clock_for_past(my_io.clk)`\n\ + in the module's body for every clock you use as the\n\ + second argument of the `read_past()` family." + ); + }; + current.map(|current| clock_for_past.current_to_past_map[¤t]) + } + } + } + #[track_caller] fn write_helper( &mut self, io: Expr, @@ -1331,11 +1379,71 @@ impl SimulationModuleState { } } +struct SimulationExternModuleClockForPast { + current_to_past_map: HashMap, CompiledValue>, +} + +impl fmt::Debug for SimulationExternModuleClockForPast { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + current_to_past_map, + } = self; + f.debug_struct("SimulationExternModuleClockForPast") + .field("current_to_past_map", &SortedMapDebug(current_to_past_map)) + .finish() + } +} + +impl SimulationExternModuleClockForPast { + fn new(clock_for_past: &ExternModuleClockForPast) -> Self { + let mut retval = Self { + current_to_past_map: HashMap::default(), + }; + for (current, past) in clock_for_past.current_to_past_map { + retval.add_current_to_past_mapping(current, past); + } + retval + } + fn add_current_to_past_mapping( + &mut self, + current: CompiledValue, + past: CompiledValue, + ) { + self.current_to_past_map.insert(current, past); + match current.layout.body { + CompiledTypeLayoutBody::Scalar | CompiledTypeLayoutBody::PhantomConst => {} + CompiledTypeLayoutBody::Array { .. } => { + let current = current.map_ty(Array::from_canonical); + let past = past.map_ty(Array::from_canonical); + for index in 0..current.layout.ty.len() { + self.add_current_to_past_mapping(current.element(index), past.element(index)); + } + } + CompiledTypeLayoutBody::Bundle { .. } => { + let current = current.map_ty(Bundle::from_canonical); + let past = past.map_ty(Bundle::from_canonical); + for BundleField { name, .. } in current.layout.ty.fields() { + self.add_current_to_past_mapping( + current.field_by_name(name), + past.field_by_name(name), + ); + } + } + } + } +} + +enum ReadTime { + Current, + Past { clock_for_past: Expr }, +} + struct SimulationExternModuleState { module_state: SimulationModuleState, sim: ExternModuleSimulation, running_generator: Option + 'static>>>, waker: Arc, + debug_name: Interned, } impl fmt::Debug for SimulationExternModuleState { @@ -1345,6 +1453,7 @@ impl fmt::Debug for SimulationExternModuleState { sim, running_generator, waker: _, + debug_name: _, } = self; f.debug_struct("SimulationExternModuleState") .field("module_state", module_state) @@ -1489,75 +1598,170 @@ impl Hash for HashableWaker { } } +enum EventWakers { + Wakers(HashSet), + CurrentlyWaking, +} + +impl EventWakers { + fn start_waking(&mut self) -> HashSet { + match std::mem::replace(self, Self::CurrentlyWaking) { + Self::Wakers(retval) => retval, + Self::CurrentlyWaking => unreachable!(), + } + } +} + +impl fmt::Debug for EventWakers { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + Self::Wakers(wakers) => f.debug_tuple("Wakers").field(&wakers.len()).finish(), + Self::CurrentlyWaking => write!(f, "CurrentlyWaking"), + } + } +} + struct EventQueueData { instant: SimInstant, - events: BTreeMap>, + events: BTreeMap, + trace: bool, } impl fmt::Debug for EventQueueData { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - struct EventsDebug<'a>(&'a BTreeMap>); - impl fmt::Debug for EventsDebug<'_> { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let mut debug_map = f.debug_map(); - for (k, v) in self.0 { - debug_map.entry(&format_args!("{k:?}"), &v.len()); - } - debug_map.finish() - } - } - let Self { instant, events } = self; + let Self { + instant, + events, + trace: _, + } = self; f.debug_struct("EventQueueData") .field("instant", instant) - .field("events", &EventsDebug(events)) + .field("events", events) .finish() } } -struct EventQueueFirstEntry<'a>( - std::collections::btree_map::OccupiedEntry<'a, Event, HashSet>, -); +struct EventQueueFirstEvent<'a> { + event_queue: Arc, + event_queue_lock: MutexGuard<'a, EventQueueData>, +} -impl<'a> EventQueueFirstEntry<'a> { - fn key(&self) -> &Event { - self.0.key() +impl<'a> EventQueueFirstEvent<'a> { + fn event(&self) -> &Event { + self.event_queue_lock + .events + .first_key_value() + .expect("known to be non-empty") + .0 } - fn remove(self) -> HashSet { - self.0.remove() + fn remove_and_wake_all_wakers(self) { + let Self { + event_queue, + mut event_queue_lock, + } = self; + let trace = event_queue_lock.trace; + let mut entry = event_queue_lock + .events + .first_entry() + .expect("known to be non-empty"); + let wakers = entry.get_mut().start_waking(); + let event = *entry.key(); + if wakers.is_empty() { + entry.remove(); + if trace { + println!( + "EventQueue first_event remove_and_wake_all_wakers(): event={event:?} no wakers", + ); + } + drop(event_queue_lock); + return; + } + drop(event_queue_lock); + if trace { + println!( + "EventQueue first_event remove_and_wake_all_wakers(): event={event:?} wakers_len={}", + wakers.len() + ); + } + for waker in wakers { + waker.0.wake(); + } + event_queue.lock().events.remove(&event); + if trace { + println!( + "EventQueue first_event remove_and_wake_all_wakers(): event={event:?} finished waking", + ); + } + } + fn into_event_queue_lock(self) -> MutexGuard<'a, EventQueueData> { + self.event_queue_lock } } impl EventQueueData { - fn new(instant: SimInstant) -> Self { + fn new(instant: SimInstant, trace: bool) -> Self { Self { instant, events: BTreeMap::new(), + trace, } } fn instant(&self) -> SimInstant { self.instant } fn set_instant(&mut self, instant: SimInstant) { + if self.trace { + println!("EventQueue set_instant({instant:?})"); + } self.instant = instant; } - fn add_event(&mut self, mut event: Event, waker: Option) { + fn add_event( + &mut self, + mut event: Event, + waker: Option, + ) -> Result<(), std::task::Waker> { event.instant = event.instant.max(self.instant); - self.events + let wakers = self + .events .entry(event) - .or_default() - .extend(waker.map(HashableWaker)); + .or_insert_with(|| EventWakers::Wakers(HashSet::default())); + let EventWakers::Wakers(wakers) = wakers else { + return match waker { + Some(waker) => Err(waker), + None => Ok(()), + }; + }; + if self.trace { + println!( + "EventQueue add_event({event:?}, {:?})", + waker.is_some().then_some(format_args!("")) + ); + } + wakers.extend(waker.map(HashableWaker)); + Ok(()) } - fn add_event_for_now(&mut self, kind: EventKind, waker: Option) { + fn add_event_for_now(&mut self, kind: EventKind) { self.add_event( Event { instant: self.instant, kind, }, - waker, - ); + None, + ) + .expect("no waker passed in") } - fn first_entry(&mut self) -> Option> { - self.events.first_entry().map(EventQueueFirstEntry) + fn first_event<'a>( + this: MutexGuard<'a, EventQueueData>, + event_queue: Arc, + ) -> Result, MutexGuard<'a, EventQueueData>> { + if this.events.is_empty() { + Err(this) + } else { + Ok(EventQueueFirstEvent { + event_queue, + event_queue_lock: this, + }) + } } fn peek_first_event(&self) -> Option { Some(*self.events.first_key_value()?.0) @@ -1586,11 +1790,11 @@ impl EventQueue { fn new(data: EventQueueData) -> Self { Self(Mutex::new(data)) } - fn lock(&self) -> std::sync::MutexGuard<'_, EventQueueData> { + fn lock(&self) -> MutexGuard<'_, EventQueueData> { self.0.lock().expect("not poisoned") } - fn add_event_for_now(&self, kind: EventKind, waker: Option) { - self.lock().add_event_for_now(kind, waker); + fn add_event_for_now(&self, kind: EventKind) { + self.lock().add_event_for_now(kind); } fn peek_first_event_for_now(&self) -> Option { self.lock().peek_first_event_for_now() @@ -1608,7 +1812,7 @@ impl std::task::Wake for ExternModuleGeneratorWaker { } fn wake_by_ref(self: &Arc) { if let Some(event_queue) = self.event_queue.upgrade() { - event_queue.add_event_for_now(EventKind::ExternModule(self.module_index), None); + event_queue.add_event_for_now(EventKind::ExternModule(self.module_index)); } } } @@ -1808,10 +2012,10 @@ impl SimulationImpl { } fn new(compiled: Compiled) -> Self { let io_target = Target::from(compiled.io); - let mut event_queue = EventQueueData::new(SimInstant::START); - event_queue.add_event_for_now(EventKind::State, None); + let mut event_queue = EventQueueData::new(SimInstant::START, false); + event_queue.add_event_for_now(EventKind::State); for module_index in 0..compiled.extern_modules.len() { - event_queue.add_event_for_now(EventKind::ExternModule(module_index), None); + event_queue.add_event_for_now(EventKind::ExternModule(module_index)); } let event_queue = Arc::new(EventQueue::new(event_queue)); let extern_modules = Box::from_iter(compiled.extern_modules.iter().enumerate().map( @@ -1820,7 +2024,9 @@ impl SimulationImpl { &CompiledExternModule { module_io_targets, module_io, + clocks_for_past, simulation, + debug_name, }, )| { SimulationExternModuleState { @@ -1829,6 +2035,7 @@ impl SimulationImpl { .iter() .copied() .zip(module_io.iter().copied()), + &clocks_for_past, ), sim: simulation, running_generator: None, @@ -1836,6 +2043,7 @@ impl SimulationImpl { event_queue: Arc::downgrade(&event_queue), module_index, }), + debug_name, } }, )); @@ -1858,6 +2066,7 @@ impl SimulationImpl { value, ) }), + &[], ), extern_modules, trace_decls: compiled.base_module.trace_decls, @@ -2048,6 +2257,9 @@ impl SimulationImpl { // already added return; }; + if self.breakpoints.as_ref().is_some_and(|v| v.trace) { + println!("SimulationImpl::wake_after_change:\n{sensitivity_set:#?}"); + } let SensitivitySet { debug_id: _, compiled_values: _, @@ -2070,6 +2282,9 @@ impl SimulationImpl { else { return; }; + if self.breakpoints.as_ref().is_some_and(|v| v.trace) { + println!("SimulationImpl::cancel_wake_after_change:\n{sensitivity_set:#?}"); + } let SensitivitySet { debug_id: _, compiled_values: _, @@ -2099,13 +2314,19 @@ impl SimulationImpl { let Some(instant) = instant(event_queue.instant()) else { return Err(waker); }; - event_queue.add_event( + match event_queue.add_event( Event { instant, kind: EventKind::ExternModule(module_index), }, Some(waker), - ); + ) { + Ok(()) => {} + Err(waker) => { + drop(event_queue); + waker.wake(); + } + } Ok(()) } async fn yield_advance_time_or_settle( @@ -2248,17 +2469,25 @@ impl SimulationImpl { .iter() .any(|i| self.state.small_slots[*i] != 0) { - self.event_queue.add_event_for_now(EventKind::State, None); + if self.breakpoints.as_ref().is_some_and(|v| v.trace) { + println!("SimulationImpl clocks triggered"); + } + self.event_queue.add_event_for_now(EventKind::State); } } #[track_caller] fn run_extern_module(this_ref: &Rc>, module_index: usize) { let mut this = this_ref.borrow_mut(); + let trace = this.breakpoints.as_ref().is_some_and(|v| v.trace); let extern_module = &mut this.extern_modules[module_index]; + let debug_name = extern_module.debug_name; let waker = std::task::Waker::from(extern_module.waker.clone()); let mut generator = if !extern_module.module_state.did_initial_settle { let sim = extern_module.sim; drop(this); + if trace { + println!("{debug_name}: start"); + } Box::into_pin(sim.run(ExternModuleSimulationState { sim_impl: this_ref.clone(), module_index, @@ -2269,13 +2498,19 @@ impl SimulationImpl { } else { return; }; - let generator = match generator + if trace { + println!("{debug_name}: poll"); + } + let poll_result = generator .as_mut() - .poll(&mut std::task::Context::from_waker(&waker)) - { + .poll(&mut std::task::Context::from_waker(&waker)); + let generator = match poll_result { Poll::Ready(()) => None, Poll::Pending => Some(generator), }; + if trace { + println!("{debug_name}: poll returned {poll_result:?}"); + } this = this_ref.borrow_mut(); this.extern_modules[module_index] .module_state @@ -2378,7 +2613,8 @@ impl SimulationImpl { "didn't initialize all inputs", ); this.check_waiting_sensitivity_sets(); - let mut event_queue = this.event_queue.lock(); + let arc_event_queue = this.event_queue.clone(); // avoid borrow errors + let mut event_queue = arc_event_queue.lock(); let Some(run_target) = run_target(event_queue.instant()) else { drop(event_queue); panic!("SimInstant overflowed"); @@ -2392,10 +2628,14 @@ impl SimulationImpl { } settle_cycle += 1; let event_queue_instant = event_queue.instant(); - let Some(first_entry) = event_queue.first_entry() else { - let changed_time = event_queue_instant != run_target; - event_queue.set_instant(run_target); - drop(event_queue); + let mut changed_time = false; + let first_entry = EventQueueData::first_event(event_queue, arc_event_queue.clone()) + .map_err(|mut event_queue| { + changed_time = event_queue_instant != run_target; + event_queue.set_instant(run_target); + drop(event_queue); + }); + let Ok(first_entry) = first_entry else { if changed_time { this.write_traces_change_time_to(run_target); } @@ -2404,13 +2644,9 @@ impl SimulationImpl { let Event { instant: event_instant, kind: event_kind, - } = *first_entry.key(); + } = *first_entry.event(); if event_instant <= event_queue_instant { - let wakers = first_entry.remove(); - drop(event_queue); - for HashableWaker(waker) in wakers { - waker.wake(); - } + first_entry.remove_and_wake_all_wakers(); match event_kind { EventKind::State => this.run_state_settle_cycle(), EventKind::ExternModule(module_index) => { @@ -2422,6 +2658,7 @@ impl SimulationImpl { this.write_traces_after_event(); this.check_waiting_sensitivity_sets(); } else { + event_queue = first_entry.into_event_queue_lock(); let new_instant = event_instant.min(run_target); let changed_time = event_queue_instant != new_instant; event_queue.set_instant(new_instant); @@ -2433,7 +2670,7 @@ impl SimulationImpl { return; } } - event_queue = this.event_queue.lock(); + event_queue = arc_event_queue.lock(); } } #[track_caller] @@ -2458,10 +2695,11 @@ impl SimulationImpl { fn read_bit( &mut self, io: Expr, + read_time: ReadTime, which_module: WhichModule, ) -> MaybeNeedsSettle { self.get_module(which_module) - .read_helper(Expr::canonical(io), which_module) + .read_helper(Expr::canonical(io), read_time, which_module) .map(|compiled_value| ReadBitFn { compiled_value }) .apply_no_settle(&mut self.state) } @@ -2470,7 +2708,7 @@ impl SimulationImpl { let compiled_value = self .get_module_mut(which_module) .write_helper(io, which_module); - self.event_queue.add_event_for_now(EventKind::State, None); + self.event_queue.add_event_for_now(EventKind::State); match compiled_value.range.len().as_single() { Some(TypeLenSingle::SmallSlot) => { self.state.small_slots[compiled_value.range.small_slots.start] = value as _; @@ -2480,15 +2718,17 @@ impl SimulationImpl { } Some(TypeLenSingle::SimOnlySlot) | None => unreachable!(), } + self.debug_write(compiled_value); } #[track_caller] fn read_bool_or_int( &mut self, io: Expr, + read_time: ReadTime, which_module: WhichModule, ) -> MaybeNeedsSettle, I::Value> { self.get_module(which_module) - .read_helper(Expr::canonical(io), which_module) + .read_helper(Expr::canonical(io), read_time, which_module) .map(|compiled_value| ReadBoolOrIntFn { compiled_value, io }) .apply_no_settle(&mut self.state) } @@ -2502,7 +2742,7 @@ impl SimulationImpl { let compiled_value = self .get_module_mut(which_module) .write_helper(Expr::canonical(io), which_module); - self.event_queue.add_event_for_now(EventKind::State, None); + self.event_queue.add_event_for_now(EventKind::State); let value: BigInt = value.into(); match compiled_value.range.len().as_single() { Some(TypeLenSingle::SmallSlot) => { @@ -2517,6 +2757,7 @@ impl SimulationImpl { } Some(TypeLenSingle::SimOnlySlot) | None => unreachable!(), } + self.debug_write(compiled_value); } #[track_caller] fn read_write_sim_value_helper( @@ -2569,17 +2810,18 @@ impl SimulationImpl { None => unreachable!(), } } - CompiledTypeLayoutBody::Array { element } => { + CompiledTypeLayoutBody::Array { elements_non_empty } => { let ty = ::from_canonical(compiled_value.layout.ty); let element_size = ty.element().size(); for element_index in 0..ty.len() { Self::read_write_sim_value_helper( state, CompiledValue { - layout: *element, - range: compiled_value - .range - .index_array(element.layout.len(), element_index), + layout: elements_non_empty[element_index], + range: compiled_value.range.index_array( + elements_non_empty[element_index].layout.len(), + element_index, + ), write: None, }, start_index + element_index * element_size, @@ -2725,12 +2967,15 @@ impl SimulationImpl { fn read( &mut self, io: Expr, + read_time: ReadTime, which_module: WhichModule, ) -> ( CompiledValue, MaybeNeedsSettle>, ) { - let compiled_value = self.get_module(which_module).read_helper(io, which_module); + let compiled_value = self + .get_module(which_module) + .read_helper(io, read_time, which_module); let value = compiled_value .map(|compiled_value| ReadFn { compiled_value, io }) .apply_no_settle(&mut self.state); @@ -2738,6 +2983,18 @@ impl SimulationImpl { | MaybeNeedsSettle::NoSettleNeeded(compiled_value)) = compiled_value; (compiled_value, value) } + fn debug_write(&self, compiled_value: CompiledValue) { + if self.breakpoints.as_ref().is_some_and(|v| v.trace) { + println!( + "wrote: {:#?}", + compiler::DebugCompiledValueStateAsMap { + compiled_value, + state_layout: self.state.insns.state_layout(), + state: &self.state, + }, + ); + } + } #[track_caller] fn write( &mut self, @@ -2748,7 +3005,7 @@ impl SimulationImpl { let compiled_value = self .get_module_mut(which_module) .write_helper(io, which_module); - self.event_queue.add_event_for_now(EventKind::State, None); + self.event_queue.add_event_for_now(EventKind::State); assert_eq!(Expr::ty(io), SimValue::ty(value)); Self::read_write_sim_value_helper( &mut self.state, @@ -2781,6 +3038,7 @@ impl SimulationImpl { value.clone_from(&opaque.sim_only_values()[index]); }, ); + self.debug_write(compiled_value); } #[track_caller] fn settle_if_needed(this_ref: &Rc>, v: MaybeNeedsSettle) -> O @@ -2946,11 +3204,14 @@ impl fmt::Debug for SortedSetDebug<'_, T, V> { } } -struct SortedMapDebug<'a, K: 'static + Send + Sync, V>(&'a BTreeMap, V>); +struct SortedMapDebug<'a, T>(&'a T); -impl fmt::Debug for SortedMapDebug<'_, K, V> { +impl<'a, K: fmt::Debug + 'a, V: fmt::Debug + 'a, T> fmt::Debug for SortedMapDebug<'a, T> +where + &'a T: IntoIterator, +{ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let mut entries = Vec::from_iter(self.0.iter().map(|(k, v)| { + let mut entries = Vec::from_iter(self.0.into_iter().map(|(k, v)| { if f.alternate() { (format!("{k:#?}"), format!("{v:#?}")) } else { @@ -3001,7 +3262,7 @@ macro_rules! impl_simulation_methods { let retval = $self .sim_impl .borrow_mut() - .read_bool_or_int(io, $which_module); + .read_bool_or_int(io, ReadTime::Current, $which_module); $self.settle_if_needed(retval)$(.$await)? } $(#[$track_caller])? @@ -3032,7 +3293,7 @@ macro_rules! impl_simulation_methods { let retval = $self .sim_impl .borrow_mut() - .read_bit(Expr::canonical(io), $which_module); + .read_bit(Expr::canonical(io), ReadTime::Current, $which_module); $self.settle_if_needed(retval)$(.$await)? } $(#[$track_caller])? @@ -3046,7 +3307,7 @@ macro_rules! impl_simulation_methods { let retval = $self .sim_impl .borrow_mut() - .read_bit(Expr::canonical(io), $which_module); + .read_bit(Expr::canonical(io), ReadTime::Current, $which_module); $self.settle_if_needed(retval)$(.$await)? } $(#[$track_caller])? @@ -3060,7 +3321,7 @@ macro_rules! impl_simulation_methods { let retval = $self .sim_impl .borrow_mut() - .read_bit(Expr::canonical(io), $which_module); + .read_bit(Expr::canonical(io), ReadTime::Current, $which_module); $self.settle_if_needed(retval)$(.$await)? } #[track_caller] @@ -3075,7 +3336,7 @@ macro_rules! impl_simulation_methods { let retval = $self .sim_impl .borrow_mut() - .read(Expr::canonical(io), $which_module).1; + .read(Expr::canonical(io), ReadTime::Current, $which_module).1; SimValue::from_canonical($self.settle_if_needed(retval)$(.$await)?) } $(#[$track_caller])? @@ -3152,11 +3413,13 @@ impl Simulation { #[doc(hidden)] /// This is explicitly unstable and may be changed/removed at any time pub fn set_breakpoints_unstable(&mut self, pcs: HashSet, trace: bool) { - self.sim_impl.borrow_mut().breakpoints = Some(BreakpointsSet { + let mut sim_impl = self.sim_impl.borrow_mut(); + sim_impl.breakpoints = Some(BreakpointsSet { last_was_break: false, set: pcs, trace, }); + sim_impl.event_queue.lock().trace = trace; } } @@ -3211,7 +3474,10 @@ impl ExternModuleSimulationState { }; for io in iter { let io = Expr::canonical(io.to_expr()); - let (key, value) = self.sim_impl.borrow_mut().read(io, which_module); + let (key, value) = self + .sim_impl + .borrow_mut() + .read(io, ReadTime::Current, which_module); let value = self.settle_if_needed(value).await; let key = Rc::new(key); if sensitivity_set.compiled_values.insert(key.clone()) { @@ -3469,6 +3735,102 @@ impl ExternModuleSimulationState { .expect("filled by running all futures to completion"), } } + /// Reads the value of `io` from right before the last clock edge of `clock_for_past`. + /// + /// In order to use the `read_past()` family of functions, you must call [`m.register_clock_for_past(my_io.clk)`] + /// in the module's body for every clock you use as the second argument of the `read_past()` family. + /// + /// [`m.register_clock_for_past(my_io.clk)`]: crate::module::ModuleBuilder::register_clock_for_past + pub async fn read_past_bool_or_int( + &mut self, + io: Expr, + clock_for_past: Expr, + ) -> I::Value { + let retval = self.sim_impl.borrow_mut().read_bool_or_int( + io, + ReadTime::Past { clock_for_past }, + WhichModule::Extern { + module_index: self.module_index, + }, + ); + self.settle_if_needed(retval).await + } + /// Reads the value of `io` from right before the last clock edge of `clock_for_past`. + /// + /// In order to use the `read_past()` family of functions, you must call [`m.register_clock_for_past(my_io.clk)`] + /// in the module's body for every clock you use as the second argument of the `read_past()` family. + /// + /// [`m.register_clock_for_past(my_io.clk)`]: crate::module::ModuleBuilder::register_clock_for_past + pub async fn read_past_clock(&mut self, io: Expr, clock_for_past: Expr) -> bool { + let retval = self.sim_impl.borrow_mut().read_bit( + Expr::canonical(io), + ReadTime::Past { clock_for_past }, + WhichModule::Extern { + module_index: self.module_index, + }, + ); + self.settle_if_needed(retval).await + } + /// Reads the value of `io` from right before the last clock edge of `clock_for_past`. + /// + /// In order to use the `read_past()` family of functions, you must call [`m.register_clock_for_past(my_io.clk)`] + /// in the module's body for every clock you use as the second argument of the `read_past()` family. + /// + /// [`m.register_clock_for_past(my_io.clk)`]: crate::module::ModuleBuilder::register_clock_for_past + pub async fn read_past_bool(&mut self, io: Expr, clock_for_past: Expr) -> bool { + let retval = self.sim_impl.borrow_mut().read_bit( + Expr::canonical(io), + ReadTime::Past { clock_for_past }, + WhichModule::Extern { + module_index: self.module_index, + }, + ); + self.settle_if_needed(retval).await + } + /// Reads the value of `io` from right before the last clock edge of `clock_for_past`. + /// + /// In order to use the `read_past()` family of functions, you must call [`m.register_clock_for_past(my_io.clk)`] + /// in the module's body for every clock you use as the second argument of the `read_past()` family. + /// + /// [`m.register_clock_for_past(my_io.clk)`]: crate::module::ModuleBuilder::register_clock_for_past + pub async fn read_past_reset( + &mut self, + io: Expr, + clock_for_past: Expr, + ) -> bool { + let retval = self.sim_impl.borrow_mut().read_bit( + Expr::canonical(io), + ReadTime::Past { clock_for_past }, + WhichModule::Extern { + module_index: self.module_index, + }, + ); + self.settle_if_needed(retval).await + } + /// Reads the value of `io` from right before the last clock edge of `clock_for_past`. + /// + /// In order to use the `read_past()` family of functions, you must call [`m.register_clock_for_past(my_io.clk)`] + /// in the module's body for every clock you use as the second argument of the `read_past()` family. + /// + /// [`m.register_clock_for_past(my_io.clk)`]: crate::module::ModuleBuilder::register_clock_for_past + pub async fn read_past( + &mut self, + io: Expr, + clock_for_past: Expr, + ) -> SimValue { + let retval = self + .sim_impl + .borrow_mut() + .read( + Expr::canonical(io), + ReadTime::Past { clock_for_past }, + WhichModule::Extern { + module_index: self.module_index, + }, + ) + .1; + SimValue::from_canonical(self.settle_if_needed(retval).await) + } impl_simulation_methods!( async_await = (async, await), track_caller = (), @@ -3803,7 +4165,7 @@ impl fmt::Debug for ExternModuleSimulation { .field("generator", &self.generator) .field( "sim_io_to_generator_map", - &SortedMapDebug(&self.sim_io_to_generator_map), + &SortedMapDebug(&*self.sim_io_to_generator_map), ) .field("source_location", &self.source_location) .finish() diff --git a/crates/fayalite/src/sim/compiler.rs b/crates/fayalite/src/sim/compiler.rs index 98e5abf..7a0ac0a 100644 --- a/crates/fayalite/src/sim/compiler.rs +++ b/crates/fayalite/src/sim/compiler.rs @@ -31,9 +31,9 @@ use crate::{ TraceMemoryLocation, TraceModule, TraceModuleIO, TracePhantomConst, TraceReg, TraceSInt, TraceScalarId, TraceScope, TraceSimOnly, TraceSyncReset, TraceUInt, TraceWire, interpreter::{ - Insn, InsnField, InsnFieldKind, InsnFieldType, InsnOrLabel, Insns, InsnsBuilding, - InsnsBuildingDone, InsnsBuildingKind, Label, SmallUInt, StatePartArrayIndex, - StatePartArrayIndexed, + self, Insn, InsnField, InsnFieldKind, InsnFieldType, InsnOrLabel, Insns, InsnsBuilding, + InsnsBuildingDone, InsnsBuildingKind, Label, PrefixLinesWrapper, SmallUInt, + StatePartArrayIndex, StatePartArrayIndexed, parts::{ MemoryData, SlotDebugData, StatePartIndex, StatePartIndexRange, StatePartKind, StatePartKindBigSlots, StatePartKindMemories, StatePartKindSimOnlySlots, @@ -82,20 +82,73 @@ pub(crate) struct CompiledBundleField { pub(crate) ty: CompiledTypeLayout, } +impl CompiledBundleField { + fn with_prefixed_debug_names(self, prefix: &str) -> Self { + let Self { offset, ty } = self; + Self { + offset, + ty: ty.with_prefixed_debug_names(prefix), + } + } + fn with_anonymized_debug_info(self) -> Self { + let Self { offset, ty } = self; + Self { + offset, + ty: ty.with_anonymized_debug_info(), + } + } +} + #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)] pub(crate) enum CompiledTypeLayoutBody { Scalar, PhantomConst, Array { - /// debug names are ignored, use parent's layout instead - element: Interned>, + /// always has at least one element even for zero-sized arrays + elements_non_empty: Interned<[CompiledTypeLayout]>, }, Bundle { - /// debug names are ignored, use parent's layout instead fields: Interned<[CompiledBundleField]>, }, } +impl CompiledTypeLayoutBody { + fn with_prefixed_debug_names(self, prefix: &str) -> Self { + match self { + CompiledTypeLayoutBody::Scalar | CompiledTypeLayoutBody::PhantomConst => self, + CompiledTypeLayoutBody::Array { elements_non_empty } => CompiledTypeLayoutBody::Array { + elements_non_empty: elements_non_empty + .iter() + .map(|element| element.with_prefixed_debug_names(prefix)) + .collect(), + }, + CompiledTypeLayoutBody::Bundle { fields } => CompiledTypeLayoutBody::Bundle { + fields: fields + .iter() + .map(|field| field.with_prefixed_debug_names(prefix)) + .collect(), + }, + } + } + fn with_anonymized_debug_info(self) -> Self { + match self { + CompiledTypeLayoutBody::Scalar | CompiledTypeLayoutBody::PhantomConst => self, + CompiledTypeLayoutBody::Array { elements_non_empty } => CompiledTypeLayoutBody::Array { + elements_non_empty: elements_non_empty + .iter() + .map(|element| element.with_anonymized_debug_info()) + .collect(), + }, + CompiledTypeLayoutBody::Bundle { fields } => CompiledTypeLayoutBody::Bundle { + fields: fields + .iter() + .map(|field| field.with_anonymized_debug_info()) + .collect(), + }, + } + } +} + #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)] pub(crate) struct CompiledTypeLayout { pub(crate) ty: T, @@ -109,7 +162,7 @@ impl CompiledTypeLayout { Self { ty, layout: layout.with_prefixed_debug_names(prefix), - body, + body: body.with_prefixed_debug_names(prefix), } } fn with_anonymized_debug_info(self) -> Self { @@ -117,7 +170,7 @@ impl CompiledTypeLayout { Self { ty, layout: layout.with_anonymized_debug_info(), - body, + body: body.with_anonymized_debug_info(), } } fn get(ty: T) -> Self { @@ -152,18 +205,22 @@ impl CompiledTypeLayout { } CanonicalType::Array(array) => { let mut layout = TypeLayout::empty(); - let element = CompiledTypeLayout::get(array.element()).intern_sized(); + let element = CompiledTypeLayout::get(array.element()); + let mut elements_non_empty = vec![]; for index in 0..array.len() { - layout.allocate( - &element - .layout - .with_prefixed_debug_names(&format!("[{index}]")), - ); + let element = element.with_prefixed_debug_names(&format!("[{index}]")); + layout.allocate(&element.layout); + elements_non_empty.push(element); + } + if array.is_empty() { + elements_non_empty.push(element.with_prefixed_debug_names("[]")); } CompiledTypeLayout { ty: *input, layout: layout.into(), - body: CompiledTypeLayoutBody::Array { element }, + body: CompiledTypeLayoutBody::Array { + elements_non_empty: elements_non_empty.intern_deref(), + }, } } CanonicalType::PhantomConst(_) => CompiledTypeLayout { @@ -182,13 +239,9 @@ impl CompiledTypeLayout { flipped: _, ty, }| { - let ty = CompiledTypeLayout::get(*ty); - let offset = layout - .allocate( - &ty.layout - .with_prefixed_debug_names(&format!(".{name}")), - ) - .start(); + let ty = CompiledTypeLayout::get(*ty) + .with_prefixed_debug_names(&format!(".{name}")); + let offset = layout.allocate(&ty.layout).start(); CompiledBundleField { offset, ty } }, ) @@ -271,6 +324,39 @@ impl CompiledValue { } } +pub(crate) struct DebugCompiledValueStateAsMap<'a> { + pub(crate) compiled_value: CompiledValue, + pub(crate) state_layout: &'a interpreter::parts::StateLayout, + pub(crate) state: &'a interpreter::State, +} + +impl fmt::Debug for DebugCompiledValueStateAsMap<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + use fmt::Write; + if self.compiled_value.range.is_empty() { + return f.write_str("{}"); + } + writeln!(f, "{{")?; + let mut f = PrefixLinesWrapper::new(f, true, " "); + macro_rules! debug_fmt { + ( + type_plural_fields = [$($type_plural_field:ident,)*]; + ) => { + $(for slot in self.compiled_value.range.$type_plural_field.iter() { + slot.debug_fmt(&mut f, ":", " ", " ", "", Some(self.state_layout), Some(self.state))?; + writeln!(f, ",")?; + })* + }; + } + get_state_part_kinds! { + debug_fmt! { + type_plural_fields; + } + } + write!(f.into_inner(), "}}") + } +} + impl CompiledValue { fn field_by_index(self, field_index: usize) -> CompiledValue { self.map(|layout, range| { @@ -299,10 +385,13 @@ impl CompiledValue { impl CompiledValue { pub(crate) fn element(self, index: usize) -> CompiledValue { self.map(|layout, range| { - let CompiledTypeLayoutBody::Array { element } = layout.body else { + let CompiledTypeLayoutBody::Array { elements_non_empty } = layout.body else { unreachable!(); }; - (*element, range.index_array(element.layout.len(), index)) + ( + elements_non_empty[index], + range.index_array(elements_non_empty[index].layout.len(), index), + ) }) } fn element_dyn( @@ -555,10 +644,11 @@ impl CompiledExpr { self, index_slot: StatePartIndex, ) -> CompiledExpr { - let CompiledTypeLayoutBody::Array { element } = self.static_part.layout.body else { + let CompiledTypeLayoutBody::Array { elements_non_empty } = self.static_part.layout.body + else { unreachable!(); }; - let stride = element.layout.len(); + let stride = elements_non_empty[0].layout.len(); let indexes = self.indexes.join(TypeArrayIndex::from_parts( index_slot, self.static_part.layout.ty.len(), @@ -566,10 +656,10 @@ impl CompiledExpr { )); CompiledExpr { static_part: self.static_part.map(|layout, range| { - let CompiledTypeLayoutBody::Array { element } = layout.body else { + let CompiledTypeLayoutBody::Array { elements_non_empty } = layout.body else { unreachable!(); }; - (*element, range.index_array(stride, 0)) + (elements_non_empty[0], range.index_array(stride, 0)) }), indexes, } @@ -1548,6 +1638,13 @@ struct ClockTrigger { source_location: SourceLocation, } +#[derive(Debug, Clone, Copy, Hash, PartialEq, Eq)] +pub(crate) struct ExternModuleClockForPast { + pub(crate) clock_for_past: CompiledValue, + pub(crate) current_to_past_map: + Interned<[(CompiledValue, CompiledValue)]>, +} + #[derive(Debug)] struct Register { value: CompiledValue, @@ -1635,7 +1732,9 @@ impl fmt::Debug for DebugOpaque { pub(crate) struct CompiledExternModule { pub(crate) module_io_targets: Interned<[Target]>, pub(crate) module_io: Interned<[CompiledValue]>, + pub(crate) clocks_for_past: Interned<[ExternModuleClockForPast]>, pub(crate) simulation: ExternModuleSimulation, + pub(crate) debug_name: Interned, } #[derive(Debug)] @@ -3915,18 +4014,15 @@ impl Compiler { self.enum_discriminants.insert(enum_value, retval); retval } - fn compile_stmt_reg( + fn compile_reg( &mut self, - stmt_reg: StmtReg, + clk: CompiledValue, + reset_and_init: Option<(Expr, CompiledValue)>, + source_location: SourceLocation, instantiated_module: InstantiatedModule, value: CompiledValue, ) { - let StmtReg { annotations, reg } = stmt_reg; - let clk = self.compile_expr(instantiated_module, Expr::canonical(reg.clock_domain().clk)); - let clk = self - .compiled_expr_to_value(clk, reg.source_location()) - .map_ty(Clock::from_canonical); - let clk = self.compile_clock(clk, reg.source_location()); + let clk = self.compile_clock(clk, source_location); struct Dispatch; impl ResetTypeDispatch for Dispatch { type Input = (); @@ -3945,18 +4041,15 @@ impl Compiler { true } } - let reset = if let Some(init) = reg.init() { - let init = self.compile_expr(instantiated_module, init); - let init = self.compiled_expr_to_value(init, reg.source_location()); - let rst = - self.compile_expr(instantiated_module, Expr::canonical(reg.clock_domain().rst)); - let rst = self.compiled_expr_to_value(rst, reg.source_location()); - let rst = self.compiled_value_bool_dest_is_small(rst, reg.source_location()); + let reset = if let Some((rst_expr, init)) = reset_and_init { + let rst = self.compile_expr(instantiated_module, Expr::canonical(rst_expr)); + let rst = self.compiled_expr_to_value(rst, source_location); + let rst = self.compiled_value_bool_dest_is_small(rst, source_location); let is_async = R::dispatch((), Dispatch); if is_async { - let cond = Expr::canonical(reg.clock_domain().rst.cast_to(Bool)); + let cond = Expr::canonical(rst_expr.cast_to(Bool)); let cond = self.compile_expr(instantiated_module, cond); - let cond = self.compiled_expr_to_value(cond, reg.source_location()); + let cond = self.compiled_expr_to_value(cond, source_location); let cond = cond.map_ty(Bool::from_canonical); // write to the register's current value since asynchronous reset is combinational let lhs = CompiledValue { @@ -3968,12 +4061,12 @@ impl Compiler { self.compile_simple_connect( [Cond { body: CondBody::IfTrue { cond }, - source_location: reg.source_location(), + source_location: source_location, }] .intern_slice(), lhs, init, - reg.source_location(), + source_location, ); } Some(RegisterReset { @@ -3988,9 +4081,33 @@ impl Compiler { value, clk_triggered: clk.clk_triggered, reset, - source_location: reg.source_location(), + source_location, }); } + fn compile_stmt_reg( + &mut self, + stmt_reg: StmtReg, + instantiated_module: InstantiatedModule, + value: CompiledValue, + ) { + let StmtReg { annotations, reg } = stmt_reg; + let clk = self.compile_expr(instantiated_module, Expr::canonical(reg.clock_domain().clk)); + let clk = self + .compiled_expr_to_value(clk, reg.source_location()) + .map_ty(Clock::from_canonical); + let reset_and_init = reg.init().map(|init| { + let init = self.compile_expr(instantiated_module, init); + let init = self.compiled_expr_to_value(init, reg.source_location()); + (reg.clock_domain().rst, init) + }); + self.compile_reg( + clk, + reset_and_init, + reg.source_location(), + instantiated_module, + value, + ); + } fn compile_declaration( &mut self, declaration: StmtDeclaration, @@ -4256,24 +4373,24 @@ impl Compiler { insns.push(end_label.into()); } } - CompiledTypeLayoutBody::Array { element } => { + CompiledTypeLayoutBody::Array { elements_non_empty } => { let CompiledTypeLayoutBody::Array { - element: mask_element, + elements_non_empty: mask_elements_non_empty, } = mask_layout.body else { unreachable!(); }; let ty = ::from_canonical(data_layout.ty); let element_bit_width = ty.element().bit_width(); - let element_size = element.layout.len(); - let mask_element_size = mask_element.layout.len(); + let element_size = elements_non_empty[0].layout.len(); + let mask_element_size = mask_elements_non_empty[0].layout.len(); for element_index in 0..ty.len() { self.compile_memory_port_rw_helper( memory, stride, start, - *element, - *mask_element, + elements_non_empty[element_index], + mask_elements_non_empty[element_index], read.as_mut().map( |MemoryPortReadInsns { addr, @@ -4880,6 +4997,88 @@ impl Compiler { } } } + fn compile_extern_module_clock_for_past( + &mut self, + instantiated_module: InstantiatedModule, + clock_for_past: Target, + ) -> ExternModuleClockForPast { + let clock_for_past = TargetInInstantiatedModule { + instantiated_module, + target: clock_for_past, + }; + let clock_for_past = self + .compile_value(clock_for_past) + .map_ty(Clock::from_canonical); + let clock_for_past_debug_name = match clock_for_past + .range + .len() + .as_single() + .expect("Clock is a single slot") + { + TypeLenSingle::BigSlot => { + self.insns + .state_layout + .ty + .big_slots + .debug_data(clock_for_past.range.start().big_slots) + .name + } + TypeLenSingle::SmallSlot => { + self.insns + .state_layout + .ty + .small_slots + .debug_data(clock_for_past.range.start().small_slots) + .name + } + TypeLenSingle::SimOnlySlot => { + unreachable!() + } + }; + let module_prefix = format!("{instantiated_module:?}."); + let trimmed_clock_for_past_debug_name = clock_for_past_debug_name + .strip_prefix(&module_prefix) + .unwrap_or(&clock_for_past_debug_name); + let current_to_past_map = instantiated_module + .leaf_module() + .module_io() + .iter() + .map( + |&AnnotatedModuleIO { + annotations: _, + module_io, + }| { + let target_base = TargetBase::from(module_io); + let current = self.compile_value(TargetInInstantiatedModule { + instantiated_module, + target: target_base.into(), + }); + let unprefixed_layout = CompiledTypeLayout::get(module_io.ty()); + let past_layout = unprefixed_layout.with_prefixed_debug_names(&format!( + "{module_prefix}{:?}$past({trimmed_clock_for_past_debug_name})", + target_base.target_name(), + )); + let past = CompiledValue { + range: self.insns.allocate_variable(&past_layout.layout), + layout: past_layout, + write: Some((current.layout, current.range)), + }; + self.compile_reg::( + clock_for_past, + None, + module_io.source_location(), + instantiated_module, + past, + ); + (current, past) + }, + ) + .collect(); + ExternModuleClockForPast { + clock_for_past, + current_to_past_map, + } + } fn compile_module(&mut self, module: Interned) -> &CompiledModule { let mut trace_decls = Vec::new(); let module_io = module @@ -4908,6 +5107,7 @@ impl Compiler { ModuleBody::Extern(ExternModuleBody { verilog_name: _, parameters: _, + clocks_for_past, simulation, }) => { let Some(simulation) = simulation else { @@ -4924,10 +5124,18 @@ impl Compiler { Target::from(*simulation.sim_io_to_generator_map[&v.module_io.intern()]) }) .collect(); + let clocks_for_past = clocks_for_past + .iter() + .map(|clock_for_past| { + self.compile_extern_module_clock_for_past(*module, *clock_for_past) + }) + .collect(); self.extern_modules.push(CompiledExternModule { module_io_targets, module_io, + clocks_for_past, simulation, + debug_name: format!("{module:?}").intern_deref(), }); } } diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs index 1a6c269..391172e 100644 --- a/crates/fayalite/src/sim/interpreter.rs +++ b/crates/fayalite/src/sim/interpreter.rs @@ -196,13 +196,27 @@ impl fmt::Debug for Insn { } } -struct PrefixLinesWrapper<'a, W> { +pub(crate) struct PrefixLinesWrapper<'a, W> { writer: W, at_beginning_of_line: bool, blank_line_prefix: &'a str, line_prefix: &'a str, } +impl<'a, W> PrefixLinesWrapper<'a, W> { + pub(crate) fn new(writer: W, at_beginning_of_line: bool, line_prefix: &'a str) -> Self { + Self { + writer, + at_beginning_of_line, + blank_line_prefix: line_prefix.trim_end(), + line_prefix, + } + } + pub(crate) fn into_inner(self) -> W { + self.writer + } +} + impl fmt::Write for PrefixLinesWrapper<'_, T> { fn write_str(&mut self, input: &str) -> fmt::Result { for part in input.split_inclusive('\n') { @@ -239,12 +253,7 @@ impl Insn { if fields.len() == 0 { return Ok(()); } - let mut f = PrefixLinesWrapper { - writer: f, - at_beginning_of_line: false, - blank_line_prefix: "", - line_prefix: " ", - }; + let mut f = PrefixLinesWrapper::new(f, false, " "); writeln!(f, " {{")?; for (field_name, field) in fields { write!(f, "{field_name}: ")?; @@ -320,7 +329,7 @@ impl Insn { } writeln!(f, ",")?; } - write!(f.writer, "}}") + write!(f.into_inner(), "}}") } } diff --git a/crates/fayalite/src/sim/interpreter/parts.rs b/crates/fayalite/src/sim/interpreter/parts.rs index 8732146..75427c9 100644 --- a/crates/fayalite/src/sim/interpreter/parts.rs +++ b/crates/fayalite/src/sim/interpreter/parts.rs @@ -9,7 +9,7 @@ use crate::{ Insn, InsnsBuilding, InsnsBuildingDone, InsnsBuildingKind, PrefixLinesWrapper, SmallSInt, SmallUInt, State, }, - value::{DynSimOnlyValue, DynSimOnly}, + value::{DynSimOnly, DynSimOnlyValue}, }, ty::CanonicalType, util::{chain, const_str_cmp}, @@ -435,12 +435,7 @@ impl StatePartIndex { if state.is_some() || debug_data.is_some() { f.write_str(comment_start)?; } - let mut f = PrefixLinesWrapper { - writer: f, - at_beginning_of_line: false, - blank_line_prefix: comment_line_start.trim_end(), - line_prefix: comment_line_start, - }; + let mut f = PrefixLinesWrapper::new(f, false, comment_line_start); if let Some(state) = state { f.write_str("(")?; K::debug_fmt_state_value(state, *self, &mut f)?; @@ -453,7 +448,7 @@ impl StatePartIndex { write!(f, "{debug_data:?}")?; } if state.is_some() || debug_data.is_some() { - f.writer.write_str(comment_end)?; + f.into_inner().write_str(comment_end)?; } Ok(()) } diff --git a/crates/fayalite/src/sim/value.rs b/crates/fayalite/src/sim/value.rs index 9717417..89eb4e6 100644 --- a/crates/fayalite/src/sim/value.rs +++ b/crates/fayalite/src/sim/value.rs @@ -394,6 +394,30 @@ impl SimValuePartialEq for Bool { } } +impl SimValuePartialEq for Clock { + fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { + **this == **other + } +} + +impl SimValuePartialEq for Reset { + fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { + **this == **other + } +} + +impl SimValuePartialEq for SyncReset { + fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { + **this == **other + } +} + +impl SimValuePartialEq for AsyncReset { + fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { + **this == **other + } +} + pub trait ToSimValue: ToSimValueWithType<::Type> { type Type: Type; @@ -1302,6 +1326,20 @@ impl ToSimValue for SimOnlyValue { } } +impl SimValuePartialEq for DynSimOnly { + fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { + **this == **other + } +} + +impl, U: SimOnlyValueTrait> SimValuePartialEq> + for SimOnly +{ + fn sim_value_eq(this: &SimValue, other: &SimValue>) -> bool { + ***this == ***other + } +} + #[cfg(test)] mod tests { use super::*; diff --git a/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs b/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs index 98a199c..3df80a8 100644 --- a/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs +++ b/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs @@ -206,9 +206,25 @@ impl Default for SimOnly { } /// a value that can only be used in a Fayalite simulation, it can't be converted to FIRRTL -#[derive(Clone, Eq, PartialEq, Hash, Default, PartialOrd, Ord)] +#[derive(Clone, Eq, Hash, Default, Ord)] pub struct SimOnlyValue(Rc); +impl, U: SimOnlyValueTrait> PartialEq> + for SimOnlyValue +{ + fn eq(&self, other: &SimOnlyValue) -> bool { + >::eq(self, other) + } +} + +impl, U: SimOnlyValueTrait> PartialOrd> + for SimOnlyValue +{ + fn partial_cmp(&self, other: &SimOnlyValue) -> Option { + >::partial_cmp(self, other) + } +} + impl SimOnlyValue { pub fn with_dyn_ref R, R>(&self, f: F) -> R { // Safety: creating a copied `Rc` is safe as long as the copy isn't dropped and isn't changed diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index 6d0380b..b4169c6 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -2375,3 +2375,123 @@ fn test_phantom_const() { panic!(); } } + +#[hdl_module(outline_generated, extern)] +pub fn sim_read_past() +where + ConstUsize: KnownSize, +{ + #[hdl] + let clocks: Array = m.input(); + #[hdl] + let outputs: Array, N> = m.output(); + #[hdl] + let past_clocks: Array = m.output(); + #[hdl] + let past_outputs: Array, N> = m.output(); + for clock in clocks { + m.register_clock_for_past(clock); + } + m.extern_module_simulation_fn( + (clocks, outputs, past_clocks, past_outputs), + |(clocks, outputs, past_clocks, past_outputs), mut sim| async move { + sim.write(outputs, [0u8; N]).await; + sim.write(past_clocks, [false; N]).await; + sim.write(past_outputs, [0u8; N]).await; + loop { + sim.fork_join_scope(|scope, _| async move { + for (clock, output) in clocks.into_iter().zip(outputs) { + scope.spawn_detached( + move |_, mut sim: ExternModuleSimulationState| async move { + sim.wait_for_clock_edge(clock).await; + dbg!(clock); + let v = sim + .read_bool_or_int(output) + .await + .to_bigint() + .try_into() + .expect("known to be in range"); + sim.write(output, 1u8.wrapping_add(v)).await; + let past_outputs_v = sim.read_past(outputs, clock).await; + dbg!(&past_outputs_v); + sim.write(past_outputs, past_outputs_v).await; + let past_clocks_v = sim.read_past(clocks, clock).await; + dbg!(&past_clocks_v); + sim.write(past_clocks, past_clocks_v).await; + }, + ); + } + }) + .await; + } + }, + ); +} + +#[test] +fn test_sim_read_past() { + let _n = SourceLocation::normalize_files_for_tests(); + const N: usize = 3; + let mut sim = Simulation::new(sim_read_past::()); + // sim.set_breakpoints_unstable(Default::default(), true); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + sim.write(sim.io().clocks, [false; N]); + let mut clocks_triggered = [false; N]; + let mut expected = [0u8; N]; + let mut past_clocks_expected = [false; N]; + let mut past_expected = expected; + for i0 in 0..N { + for i1 in 0..N { + for i2 in 0..N { + for i3 in 0..N { + let indexes = [i0, i1, i2, i3]; + for i in indexes { + sim.advance_time(SimDuration::from_micros(1)); + sim.write(sim.io().clocks[i], true); + sim.advance_time(SimDuration::from_micros(1)); + sim.write(sim.io().clocks[i], false); + if !clocks_triggered[i] { + past_expected = expected; + expected[i] = expected[i].wrapping_add(1); + past_clocks_expected = [false; N]; + past_clocks_expected[i] = true; + } + dbg!(past_expected); + clocks_triggered[i] = true; + if clocks_triggered == [true; N] { + clocks_triggered = [false; N]; + } + let output = sim.read(sim.io().outputs); + assert_eq!(output, expected.to_sim_value(), "indexes={indexes:?} i={i}"); + let past_clocks = sim.read(sim.io().past_clocks); + assert_eq!( + past_clocks, + past_clocks_expected + .to_sim_value_with_type(Array::::default()), + "indexes={indexes:?} i={i}" + ); + let past_outputs = sim.read(sim.io().past_outputs); + dbg!(&past_outputs); + assert_eq!( + past_outputs, + past_expected.to_sim_value(), + "indexes={indexes:?} i={i}" + ); + } + } + } + } + } + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/sim_read_past.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/sim_read_past.txt") { + panic!(); + } +} diff --git a/crates/fayalite/tests/sim/expected/array_rw.txt b/crates/fayalite/tests/sim/expected/array_rw.txt index 2f25f35..27b040d 100644 --- a/crates/fayalite/tests/sim/expected/array_rw.txt +++ b/crates/fayalite/tests/sim/expected/array_rw.txt @@ -826,6 +826,7 @@ Simulation { }.write_index, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt index 47997e5..d470792 100644 --- a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt +++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt @@ -122,6 +122,7 @@ Simulation { }.i, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt index ac6c052..56ea4ad 100644 --- a/crates/fayalite/tests/sim/expected/connect_const.txt +++ b/crates/fayalite/tests/sim/expected/connect_const.txt @@ -98,6 +98,7 @@ Simulation { }.o, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt index 999f414..a9c1878 100644 --- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt +++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt @@ -141,6 +141,7 @@ Simulation { }.reset_out, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt index 7a43720..86bde88 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.txt +++ b/crates/fayalite/tests/sim/expected/counter_async.txt @@ -100,51 +100,51 @@ Simulation { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset }, }, + 3: IsNonZeroDestIsSmall { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, + }, + 4: AndSmall { + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 3: Const { + 5: Const { dest: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, value: 0x3, }, // at: module-XXXXXXXXXX.rs:3:1 - 4: BranchIfZero { - target: 6, + 6: BranchIfZero { + target: 8, value: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, - 5: Copy { + 7: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:1:1 - 6: Add { + 8: Add { dest: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, lhs: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, rhs: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, - 7: CastToUInt { + 9: CastToUInt { dest: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, src: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, dest_width: 4, }, // at: module-XXXXXXXXXX.rs:4:1 - 8: Copy { + 10: Copy { dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, src: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:6:1 - 9: Copy { + 11: Copy { dest: StatePartIndex(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> }, src: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:3:1 - 10: IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, - }, - 11: AndSmall { - dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, 12: BranchIfSmallNonZero { target: 16, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, @@ -261,6 +261,7 @@ Simulation { }.count, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt index b96ce5f..0a7517e 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/counter_sync.txt @@ -112,21 +112,21 @@ Simulation { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset }, }, - // at: module-XXXXXXXXXX.rs:1:1 - 6: Const { - dest: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, - value: 0x3, - }, - // at: module-XXXXXXXXXX.rs:3:1 - 7: IsNonZeroDestIsSmall { + 6: IsNonZeroDestIsSmall { dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, }, - 8: AndSmall { + 7: AndSmall { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, + // at: module-XXXXXXXXXX.rs:1:1 + 8: Const { + dest: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, + value: 0x3, + }, + // at: module-XXXXXXXXXX.rs:3:1 9: BranchIfSmallZero { target: 14, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, @@ -242,6 +242,7 @@ Simulation { }.count, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.txt b/crates/fayalite/tests/sim/expected/duplicate_names.txt index e127210..64bbbe6 100644 --- a/crates/fayalite/tests/sim/expected/duplicate_names.txt +++ b/crates/fayalite/tests/sim/expected/duplicate_names.txt @@ -102,6 +102,7 @@ Simulation { uninitialized_ios: {}, io_targets: {}, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt index eeef867..a193e92 100644 --- a/crates/fayalite/tests/sim/expected/enums.txt +++ b/crates/fayalite/tests/sim/expected/enums.txt @@ -1003,65 +1003,64 @@ Simulation { dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset }, }, + 97: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock }, + }, + 98: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 97: Const { + 99: Const { dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, value: 0x0, }, - 98: Copy { + 100: Copy { dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, }, // at: module-XXXXXXXXXX.rs:12:1 - 99: BranchIfZero { - target: 107, + 101: BranchIfZero { + target: 109, value: StatePartIndex(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:13:1 - 100: BranchIfZero { - target: 102, + 102: BranchIfZero { + target: 104, value: StatePartIndex(46), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:14:1 - 101: Copy { + 103: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:13:1 - 102: BranchIfNonZero { - target: 107, + 104: BranchIfNonZero { + target: 109, value: StatePartIndex(46), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:15:1 - 103: BranchIfZero { - target: 105, + 105: BranchIfZero { + target: 107, value: StatePartIndex(48), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:16:1 - 104: Copy { + 106: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(65), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:15:1 - 105: BranchIfNonZero { - target: 107, + 107: BranchIfNonZero { + target: 109, value: StatePartIndex(48), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:17:1 - 106: Copy { + 108: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(87), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, - // at: module-XXXXXXXXXX.rs:11:1 - 107: IsNonZeroDestIsSmall { - dest: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock }, - }, - 108: AndSmall { - dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:10:1 109: Copy { dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, @@ -1454,6 +1453,7 @@ Simulation { }.which_out, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/extern_module.txt b/crates/fayalite/tests/sim/expected/extern_module.txt index 0334940..f49106f 100644 --- a/crates/fayalite/tests/sim/expected/extern_module.txt +++ b/crates/fayalite/tests/sim/expected/extern_module.txt @@ -102,6 +102,7 @@ Simulation { }.o, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -136,6 +137,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -228,7 +230,7 @@ Simulation { index: StatePartIndex(1), }, state: 0x1, - last_state: 0x1, + last_state: 0x0, }, ], trace_memories: {}, @@ -245,7 +247,14 @@ Simulation { event_queue: EventQueue(EventQueueData { instant: 20 μs, events: { - Event { instant: 20.500000000000 μs, kind: ExternModule(0) }: 1, + Event { + instant: 20.500000000000 μs, + kind: ExternModule( + 0, + ), + }: Wakers( + 1, + ), }, }), waiting_sensitivity_sets_by_address: {}, diff --git a/crates/fayalite/tests/sim/expected/extern_module2.txt b/crates/fayalite/tests/sim/expected/extern_module2.txt index 3d7cfae..fa6e767 100644 --- a/crates/fayalite/tests/sim/expected/extern_module2.txt +++ b/crates/fayalite/tests/sim/expected/extern_module2.txt @@ -121,6 +121,7 @@ Simulation { }.o, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -167,6 +168,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { diff --git a/crates/fayalite/tests/sim/expected/many_memories.txt b/crates/fayalite/tests/sim/expected/many_memories.txt index f311cf7..c521d72 100644 --- a/crates/fayalite/tests/sim/expected/many_memories.txt +++ b/crates/fayalite/tests/sim/expected/many_memories.txt @@ -3834,6 +3834,7 @@ Simulation { }.w[7].mask, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/memories.txt b/crates/fayalite/tests/sim/expected/memories.txt index 03c5ee3..0358bb3 100644 --- a/crates/fayalite/tests/sim/expected/memories.txt +++ b/crates/fayalite/tests/sim/expected/memories.txt @@ -719,6 +719,7 @@ Simulation { }.w.mask.1, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/memories2.txt b/crates/fayalite/tests/sim/expected/memories2.txt index f1cb72b..b4041ba 100644 --- a/crates/fayalite/tests/sim/expected/memories2.txt +++ b/crates/fayalite/tests/sim/expected/memories2.txt @@ -677,6 +677,7 @@ Simulation { }.rw.wmode, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/memories3.txt b/crates/fayalite/tests/sim/expected/memories3.txt index 3166e17..2213912 100644 --- a/crates/fayalite/tests/sim/expected/memories3.txt +++ b/crates/fayalite/tests/sim/expected/memories3.txt @@ -1761,6 +1761,7 @@ Simulation { }.w.mask[7], }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt index 355b6ee..3f7a55e 100644 --- a/crates/fayalite/tests/sim/expected/mod1.txt +++ b/crates/fayalite/tests/sim/expected/mod1.txt @@ -274,6 +274,7 @@ Simulation { }.o.o2, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/phantom_const.txt b/crates/fayalite/tests/sim/expected/phantom_const.txt index dbc8f12..8c2237d 100644 --- a/crates/fayalite/tests/sim/expected/phantom_const.txt +++ b/crates/fayalite/tests/sim/expected/phantom_const.txt @@ -240,6 +240,7 @@ Simulation { }.out[1], }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.txt b/crates/fayalite/tests/sim/expected/ripple_counter.txt index 5818975..9e46be4 100644 --- a/crates/fayalite/tests/sim/expected/ripple_counter.txt +++ b/crates/fayalite/tests/sim/expected/ripple_counter.txt @@ -743,6 +743,7 @@ Simulation { }.o, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -777,6 +778,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -860,6 +862,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -943,6 +946,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt index 2ca06d2..7dcf26c 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.txt +++ b/crates/fayalite/tests/sim/expected/shift_register.txt @@ -128,21 +128,21 @@ Simulation { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset }, }, - // at: module-XXXXXXXXXX.rs:1:1 - 6: Const { - dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, - value: 0x0, - }, - // at: module-XXXXXXXXXX.rs:5:1 - 7: IsNonZeroDestIsSmall { + 6: IsNonZeroDestIsSmall { dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock }, }, - 8: AndSmall { + 7: AndSmall { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, + // at: module-XXXXXXXXXX.rs:1:1 + 8: Const { + dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: module-XXXXXXXXXX.rs:5:1 9: BranchIfSmallZero { target: 14, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, @@ -337,6 +337,7 @@ Simulation { }.q, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join.txt b/crates/fayalite/tests/sim/expected/sim_fork_join.txt index 4ad3e62..680fedb 100644 --- a/crates/fayalite/tests/sim/expected/sim_fork_join.txt +++ b/crates/fayalite/tests/sim/expected/sim_fork_join.txt @@ -164,6 +164,7 @@ Simulation { }.outputs[2], }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -234,6 +235,7 @@ Simulation { }[2], }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -433,7 +435,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[0]", ty: Clock, }, ], @@ -482,7 +484,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[0]", ty: Clock, }, ], diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt index ba5577d..40d16a9 100644 --- a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt +++ b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt @@ -164,6 +164,7 @@ Simulation { }.outputs[2], }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -234,6 +235,7 @@ Simulation { }[2], }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -433,7 +435,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::clocks[0]", ty: Clock, }, ], @@ -482,7 +484,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::clocks[0]", ty: Clock, }, ], diff --git a/crates/fayalite/tests/sim/expected/sim_only_connects.txt b/crates/fayalite/tests/sim/expected/sim_only_connects.txt index 3c1605d..15456d2 100644 --- a/crates/fayalite/tests/sim/expected/sim_only_connects.txt +++ b/crates/fayalite/tests/sim/expected/sim_only_connects.txt @@ -557,6 +557,7 @@ Simulation { }.out3, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -635,6 +636,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -794,6 +796,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -1559,7 +1562,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock, }, ], @@ -1609,7 +1612,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock, }, ], @@ -1658,7 +1661,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock, }, ], @@ -1707,7 +1710,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock, }, ], diff --git a/crates/fayalite/tests/sim/expected/sim_read_past.txt b/crates/fayalite/tests/sim/expected/sim_read_past.txt new file mode 100644 index 0000000..475943e --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_read_past.txt @@ -0,0 +1,9724 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 9, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 48, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[2]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:2:1 + 0: IsNonZeroDestIsSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock }, + }, + 1: AndSmall { + dest: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 2: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock }, + }, + 3: AndSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 4: IsNonZeroDestIsSmall { + dest: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock }, + }, + 5: AndSmall { + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 6: BranchIfSmallZero { + target: 10, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 7: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[0]", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock }, + }, + 8: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[1]", ty: Clock }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock }, + }, + 9: Copy { + dest: StatePartIndex(14), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[2]", ty: Clock }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:3:1 + 10: BranchIfSmallZero { + target: 14, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 11: Copy { + dest: StatePartIndex(15), // (0x30) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[0]", ty: UInt<8> }, + src: StatePartIndex(3), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", ty: UInt<8> }, + }, + 12: Copy { + dest: StatePartIndex(16), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[1]", ty: UInt<8> }, + src: StatePartIndex(4), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", ty: UInt<8> }, + }, + 13: Copy { + dest: StatePartIndex(17), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[2]", ty: UInt<8> }, + src: StatePartIndex(5), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 14: BranchIfSmallZero { + target: 18, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 15: Copy { + dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[0]", ty: Clock }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", ty: Clock }, + }, + 16: Copy { + dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[1]", ty: Clock }, + src: StatePartIndex(7), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", ty: Clock }, + }, + 17: Copy { + dest: StatePartIndex(20), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[2]", ty: Clock }, + src: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:5:1 + 18: BranchIfSmallZero { + target: 22, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 19: Copy { + dest: StatePartIndex(21), // (0x30) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[0]", ty: UInt<8> }, + src: StatePartIndex(9), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", ty: UInt<8> }, + }, + 20: Copy { + dest: StatePartIndex(22), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[1]", ty: UInt<8> }, + src: StatePartIndex(10), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", ty: UInt<8> }, + }, + 21: Copy { + dest: StatePartIndex(23), // (0x30) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[2]", ty: UInt<8> }, + src: StatePartIndex(11), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:2:1 + 22: BranchIfSmallZero { + target: 26, + value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 23: Copy { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[0]", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock }, + }, + 24: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[1]", ty: Clock }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock }, + }, + 25: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[2]", ty: Clock }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:3:1 + 26: BranchIfSmallZero { + target: 30, + value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 27: Copy { + dest: StatePartIndex(27), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[0]", ty: UInt<8> }, + src: StatePartIndex(3), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", ty: UInt<8> }, + }, + 28: Copy { + dest: StatePartIndex(28), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[1]", ty: UInt<8> }, + src: StatePartIndex(4), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", ty: UInt<8> }, + }, + 29: Copy { + dest: StatePartIndex(29), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[2]", ty: UInt<8> }, + src: StatePartIndex(5), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 30: BranchIfSmallZero { + target: 34, + value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 31: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[0]", ty: Clock }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", ty: Clock }, + }, + 32: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[1]", ty: Clock }, + src: StatePartIndex(7), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", ty: Clock }, + }, + 33: Copy { + dest: StatePartIndex(32), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[2]", ty: Clock }, + src: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:5:1 + 34: BranchIfSmallZero { + target: 38, + value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 35: Copy { + dest: StatePartIndex(33), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[0]", ty: UInt<8> }, + src: StatePartIndex(9), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", ty: UInt<8> }, + }, + 36: Copy { + dest: StatePartIndex(34), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[1]", ty: UInt<8> }, + src: StatePartIndex(10), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", ty: UInt<8> }, + }, + 37: Copy { + dest: StatePartIndex(35), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[2]", ty: UInt<8> }, + src: StatePartIndex(11), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:2:1 + 38: BranchIfSmallZero { + target: 42, + value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 39: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[0]", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock }, + }, + 40: Copy { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[1]", ty: Clock }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock }, + }, + 41: Copy { + dest: StatePartIndex(38), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[2]", ty: Clock }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:3:1 + 42: BranchIfSmallZero { + target: 46, + value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 43: Copy { + dest: StatePartIndex(39), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[0]", ty: UInt<8> }, + src: StatePartIndex(3), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", ty: UInt<8> }, + }, + 44: Copy { + dest: StatePartIndex(40), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[1]", ty: UInt<8> }, + src: StatePartIndex(4), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", ty: UInt<8> }, + }, + 45: Copy { + dest: StatePartIndex(41), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[2]", ty: UInt<8> }, + src: StatePartIndex(5), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 46: BranchIfSmallZero { + target: 50, + value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 47: Copy { + dest: StatePartIndex(42), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[0]", ty: Clock }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", ty: Clock }, + }, + 48: Copy { + dest: StatePartIndex(43), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[1]", ty: Clock }, + src: StatePartIndex(7), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", ty: Clock }, + }, + 49: Copy { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[2]", ty: Clock }, + src: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:5:1 + 50: BranchIfSmallZero { + target: 54, + value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 51: Copy { + dest: StatePartIndex(45), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[0]", ty: UInt<8> }, + src: StatePartIndex(9), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", ty: UInt<8> }, + }, + 52: Copy { + dest: StatePartIndex(46), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[1]", ty: UInt<8> }, + src: StatePartIndex(10), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", ty: UInt<8> }, + }, + 53: Copy { + dest: StatePartIndex(47), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[2]", ty: UInt<8> }, + src: StatePartIndex(11), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:2:1 + 54: XorSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 55: XorSmallImmediate { + dest: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 56: XorSmallImmediate { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 57: Return, + ], + .. + }, + pc: 57, + memory_write_log: [], + memories: StatePart { + value: [], + }, + small_slots: StatePart { + value: [ + 1, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 0, + 49, + 50, + 50, + 0, + 1, + 0, + 49, + 49, + 50, + 1, + 0, + 0, + 48, + 49, + 49, + 0, + 0, + 1, + 48, + 49, + 48, + 0, + 1, + 0, + 49, + 49, + 50, + 0, + 0, + 1, + 49, + 49, + 49, + 0, + 0, + 1, + 49, + 50, + 50, + 0, + 1, + 0, + 49, + 49, + 50, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.clocks, + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.outputs, + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_clocks, + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_outputs, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.clocks, + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.clocks[0], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.clocks[1], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.clocks[2], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.outputs, + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.outputs[0], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.outputs[1], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.outputs[2], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_clocks, + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_clocks[0], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_clocks[1], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_clocks[2], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_outputs, + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_outputs[0], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_outputs[1], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_outputs[2], + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [ + SimulationExternModuleState { + module_state: SimulationModuleState { + base_targets: [ + ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ], + uninitialized_ios: {}, + io_targets: { + ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }[0], + ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }[1], + ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }[2], + ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }[0], + ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }[1], + ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }[2], + ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }[0], + ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }[1], + ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }[2], + ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }[0], + ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }[1], + ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }[2], + }, + did_initial_settle: true, + clocks_for_past: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimulationExternModuleClockForPast { + current_to_past_map: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Array, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 3, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Array { + elements_non_empty: [ + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 3 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: CompiledValue { + layout: CompiledTypeLayout { + ty: Array, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 3, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[2]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Array { + elements_non_empty: [ + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[0]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[1]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[2]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 12, len: 3 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: Some( + ( + CompiledTypeLayout { + ty: Array, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 3, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Array { + elements_non_empty: [ + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + ], + }, + }, + TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 3 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + ), + ), + }, + CompiledValue { + layout: CompiledTypeLayout { + ty: Array, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 3, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Array { + elements_non_empty: [ + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 6, len: 3 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: CompiledValue { + layout: CompiledTypeLayout { + ty: Array, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 3, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[2]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Array { + elements_non_empty: [ + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[0]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[1]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[2]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 3, len: 0 }, + big_slots: StatePartIndexRange { start: 18, len: 3 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: Some( + ( + CompiledTypeLayout { + ty: Array, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 3, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", + ty: 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small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[2]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 9, len: 0 }, + big_slots: StatePartIndexRange { start: 41, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: Some( + ( + CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 5, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + ), + ), + }, + CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 9, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[0]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 9, len: 0 }, + big_slots: StatePartIndexRange { start: 45, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: Some( + ( + CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 9, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + ), + ), + }, + CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 10, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[1]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 9, len: 0 }, + big_slots: StatePartIndexRange { start: 46, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: Some( + ( + CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 10, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + ), + ), + }, + CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 11, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[2]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 9, len: 0 }, + big_slots: StatePartIndexRange { start: 47, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: Some( + ( + CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 11, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + ), + ), + }, + }, + }, + }, + }, + sim: ExternModuleSimulation { + generator: SimGeneratorFn { + args: ( + ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ), + f: ..., + }, + sim_io_to_generator_map: { + ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }: ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }: ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }: ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }: ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }, + }, + source_location: SourceLocation( + module-XXXXXXXXXX.rs:6:1, + ), + }, + running_generator: Some( + ..., + ), + }, + ], + trace_decls: TraceModule { + name: "sim_read_past", + children: [ + TraceModuleIO { + name: "clocks", + child: TraceArray { + name: "clocks", + elements: [ + TraceClock { + location: TraceScalarId(0), + name: "[0]", + flow: Source, + }, + TraceClock { + location: TraceScalarId(1), + name: "[1]", + flow: Source, + }, + TraceClock { + location: TraceScalarId(2), + name: "[2]", + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ty: Array, + flow: Source, + }, + TraceModuleIO { + name: "outputs", + child: TraceArray { + name: "outputs", + elements: [ + TraceUInt { + location: TraceScalarId(3), + name: "[0]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(4), + name: "[1]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(5), + name: "[2]", + ty: UInt<8>, + flow: Sink, + }, + ], + ty: Array, 3>, + flow: Sink, + }, + ty: Array, 3>, + flow: Sink, + }, + TraceModuleIO { + name: "past_clocks", + child: TraceArray { + name: "past_clocks", + elements: [ + TraceClock { + location: TraceScalarId(6), + name: "[0]", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(7), + name: "[1]", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(8), + name: "[2]", + flow: Sink, + }, + ], + ty: Array, + flow: Sink, + }, + ty: Array, + flow: Sink, + }, + TraceModuleIO { + name: "past_outputs", + child: TraceArray { + name: "past_outputs", + elements: [ + TraceUInt { + location: TraceScalarId(9), + name: "[0]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(10), + name: "[1]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(11), + name: "[2]", + ty: UInt<8>, + flow: Sink, + }, + ], + ty: Array, 3>, + flow: Sink, + }, + ty: Array, 3>, + flow: Sink, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigClock { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigClock { + index: StatePartIndex(2), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(3), + ty: UInt<8>, + }, + state: 0x31, + last_state: 0x31, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigUInt { + index: StatePartIndex(4), + ty: UInt<8>, + }, + state: 0x32, + last_state: 0x32, + }, + SimTrace { + id: TraceScalarId(5), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x32, + last_state: 0x32, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigClock { + index: StatePartIndex(6), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigClock { + index: StatePartIndex(7), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigClock { + index: StatePartIndex(8), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x31, + last_state: 0x31, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<8>, + }, + state: 0x31, + last_state: 0x31, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<8>, + }, + state: 0x32, + last_state: 0x32, + }, + ], + trace_memories: {}, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(1), + StatePartIndex(4), + StatePartIndex(7), + ], + event_queue: EventQueue(EventQueueData { + instant: 648 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: { + SensitivitySet { + id: 198, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + }, + waiting_sensitivity_sets_by_compiled_value: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 198, + .. + }, + }, + ), + }, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_read_past.vcd b/crates/fayalite/tests/sim/expected/sim_read_past.vcd new file mode 100644 index 0000000..5d0a932 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_read_past.vcd @@ -0,0 +1,1908 @@ +$timescale 1 ps $end +$scope module sim_read_past $end +$scope struct clocks $end +$var wire 1 ! \[0] $end +$var wire 1 " \[1] $end +$var wire 1 # \[2] $end +$upscope $end +$scope struct outputs $end +$var wire 8 $ \[0] $end +$var wire 8 % \[1] $end +$var wire 8 & \[2] $end +$upscope $end +$scope struct past_clocks $end +$var wire 1 ' \[0] $end +$var wire 1 ( \[1] $end +$var wire 1 ) \[2] $end +$upscope $end +$scope struct past_outputs $end +$var wire 8 * \[0] $end +$var wire 8 + \[1] $end +$var wire 8 , \[2] $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +0! +0" +0# +b0 $ +b0 % +b0 & +0' +0( +0) +b0 * +b0 + +b0 , +$end +#1000000 +1! +b1 $ +1' +#2000000 +0! +#3000000 +1! +#4000000 +0! +#5000000 +1! +#6000000 +0! +#7000000 +1! +#8000000 +0! +#9000000 +1! +#10000000 +0! +#11000000 +1! +#12000000 +0! +#13000000 +1! +#14000000 +0! +#15000000 +1" +b1 % +b1 * +0' +1( +#16000000 +0" +#17000000 +1! +#18000000 +0! +#19000000 +1! +#20000000 +0! +#21000000 +1! +#22000000 +0! +#23000000 +1# +b1 & +b1 + +0( +1) +#24000000 +0# +#25000000 +1! +b10 $ +b1 , +1' +0) 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+#214000000 +0# +#215000000 +1# +#216000000 +0# +#217000000 +1" +b10000 % +b10000 , +1( +0) +#218000000 +0" +#219000000 +1! +b10001 $ +b10000 + +1' +0( +#220000000 +0! +#221000000 +1! +#222000000 +0! +#223000000 +1! +#224000000 +0! +#225000000 +1" +b10001 % +b10001 * +0' +1( +#226000000 +0" +#227000000 +1! +#228000000 +0! +#229000000 +1! +#230000000 +0! +#231000000 +1" +#232000000 +0" +#233000000 +1" +#234000000 +0" +#235000000 +1! +#236000000 +0! +#237000000 +1! +#238000000 +0! +#239000000 +1# +b10001 & +b10001 + +0( +1) +#240000000 +0# +#241000000 +1" +b10010 % +b10001 , +1( +0) +#242000000 +0" +#243000000 +1! +b10010 $ +b10010 + +1' +0( +#244000000 +0! +#245000000 +1" +#246000000 +0" +#247000000 +1! +#248000000 +0! +#249000000 +1" +#250000000 +0" +#251000000 +1! +#252000000 +0! +#253000000 +1" +#254000000 +0" +#255000000 +1" +#256000000 +0" +#257000000 +1" +#258000000 +0" +#259000000 +1! +#260000000 +0! +#261000000 +1" +#262000000 +0" +#263000000 +1# +b10010 & +b10010 * +0' +1) +#264000000 +0# +#265000000 +1" +b10011 % +b10010 , +1( +0) +#266000000 +0" +#267000000 +1! +b10011 $ +b10011 + +1' +0( +#268000000 +0! +#269000000 +1# +b10011 & +b10011 * +0' +1) +#270000000 +0# +#271000000 +1! +b10100 $ +b10011 , +1' +0) +#272000000 +0! +#273000000 +1" +b10100 % +b10100 * +0' +1( +#274000000 +0" +#275000000 +1! +#276000000 +0! +#277000000 +1# +b10100 & +b10100 + +0( +1) +#278000000 +0# +#279000000 +1" +b10101 % +b10100 , +1( +0) +#280000000 +0" +#281000000 +1" +#282000000 +0" +#283000000 +1! +b10101 $ +b10101 + +1' +0( +#284000000 +0! +#285000000 +1# +b10101 & +b10101 * +0' +1) +#286000000 +0# +#287000000 +1# +b10110 & +b10101 , +#288000000 +0# +#289000000 +1" +b10110 % +b10110 , +1( +0) +#290000000 +0" +#291000000 +1" +#292000000 +0" +#293000000 +1! +b10110 $ +b10110 + +1' +0( +#294000000 +0! +#295000000 +1! +b10111 $ +b10110 * +#296000000 +0! +#297000000 +1" +b10111 % +b10111 * +0' +1( +#298000000 +0" +#299000000 +1" +#300000000 +0" +#301000000 +1! +#302000000 +0! +#303000000 +1" +#304000000 +0" +#305000000 +1" +#306000000 +0" +#307000000 +1" +#308000000 +0" +#309000000 +1! +#310000000 +0! +#311000000 +1# +b10111 & +b10111 + +0( +1) +#312000000 +0# +#313000000 +1" +b11000 % +b10111 , +1( +0) +#314000000 +0" +#315000000 +1" +#316000000 +0" +#317000000 +1" +#318000000 +0" +#319000000 +1! +b11000 $ +b11000 + +1' +0( +#320000000 +0! +#321000000 +1" +#322000000 +0" +#323000000 +1" +#324000000 +0" +#325000000 +1" +#326000000 +0" +#327000000 +1" +#328000000 +0" +#329000000 +1" +#330000000 +0" +#331000000 +1" +#332000000 +0" +#333000000 +1" +#334000000 +0" +#335000000 +1# +b11000 & +b11000 * +0' +1) +#336000000 +0# +#337000000 +1" +b11001 % +b11000 , +1( +0) +#338000000 +0" +#339000000 +1" +#340000000 +0" +#341000000 +1# +b11001 & +b11001 + +0( +1) +#342000000 +0# +#343000000 +1! +b11001 $ +b11001 , +1' +0) +#344000000 +0! +#345000000 +1" +b11010 % +b11001 * +0' +1( +#346000000 +0" +#347000000 +1" +#348000000 +0" +#349000000 +1# +b11010 & +b11010 + +0( +1) +#350000000 +0# +#351000000 +1" +#352000000 +0" +#353000000 +1" +#354000000 +0" +#355000000 +1" +#356000000 +0" +#357000000 +1# +#358000000 +0# +#359000000 +1# +#360000000 +0# +#361000000 +1" +#362000000 +0" +#363000000 +1# +#364000000 +0# +#365000000 +1! +b11010 $ +b11010 , +1' +0) +#366000000 +0! +#367000000 +1! +b11011 $ +b11010 * +#368000000 +0! +#369000000 +1" +b11011 % +b11011 * +0' +1( +#370000000 +0" +#371000000 +1# +b11011 & +b11011 + +0( +1) +#372000000 +0# +#373000000 +1! +b11100 $ +b11011 , +1' +0) +#374000000 +0! +#375000000 +1" +b11100 % +b11100 * +0' +1( +#376000000 +0" +#377000000 +1" +#378000000 +0" +#379000000 +1# +b11100 & +b11100 + +0( +1) +#380000000 +0# +#381000000 +1! +b11101 $ +b11100 , +1' +0) +#382000000 +0! +#383000000 +1# +b11101 & +b11101 * +0' +1) +#384000000 +0# +#385000000 +1" +b11101 % +b11101 , +1( +0) +#386000000 +0" +#387000000 +1# +b11110 & +b11101 + +0( +1) +#388000000 +0# +#389000000 +1" +b11110 % +b11110 , +1( +0) +#390000000 +0" +#391000000 +1! +b11110 $ +b11110 + +1' +0( +#392000000 +0! +#393000000 +1" +b11111 % +b11110 * +0' +1( +#394000000 +0" +#395000000 +1# +b11111 & +b11111 + +0( +1) +#396000000 +0# +#397000000 +1" +#398000000 +0" +#399000000 +1" +#400000000 +0" +#401000000 +1" +#402000000 +0" +#403000000 +1# +#404000000 +0# +#405000000 +1" +#406000000 +0" +#407000000 +1# +#408000000 +0# +#409000000 +1" +#410000000 +0" +#411000000 +1# +#412000000 +0# +#413000000 +1# +#414000000 +0# +#415000000 +1! +b11111 $ +b11111 , +1' +0) +#416000000 +0! +#417000000 +1" +b100000 % +b11111 * +0' +1( +#418000000 +0" +#419000000 +1# +b100000 & +b100000 + +0( +1) +#420000000 +0# +#421000000 +1# +#422000000 +0# +#423000000 +1" +#424000000 +0" +#425000000 +1" +#426000000 +0" +#427000000 +1# +#428000000 +0# +#429000000 +1# +#430000000 +0# +#431000000 +1# +#432000000 +0# +#433000000 +1# +#434000000 +0# +#435000000 +1! +b100000 $ +b100000 , +1' +0) +#436000000 +0! +#437000000 +1! +b100001 $ +b100000 * +#438000000 +0! +#439000000 +1! +#440000000 +0! +#441000000 +1# +b100001 & +b100001 * +0' +1) +#442000000 +0# +#443000000 +1! +#444000000 +0! +#445000000 +1! +#446000000 +0! +#447000000 +1" +b100001 % +b100001 , +1( +0) +#448000000 +0" +#449000000 +1# +b100010 & +b100001 + +0( +1) +#450000000 +0# +#451000000 +1! +b100010 $ +b100010 , +1' +0) +#452000000 +0! +#453000000 +1! +#454000000 +0! +#455000000 +1# +#456000000 +0# +#457000000 +1# +#458000000 +0# +#459000000 +1! +#460000000 +0! +#461000000 +1" +b100010 % +b100010 * +0' +1( +#462000000 +0" +#463000000 +1! +b100011 $ +b100010 + +1' +0( +#464000000 +0! +#465000000 +1# +b100011 & +b100011 * +0' +1) +#466000000 +0# +#467000000 +1! +#468000000 +0! +#469000000 +1" +b100011 % +b100011 , +1( +0) +#470000000 +0" +#471000000 +1" +b100100 % +b100011 + +#472000000 +0" +#473000000 +1# +b100100 & +b100100 + +0( +1) +#474000000 +0# +#475000000 +1! +b100100 $ +b100100 , +1' +0) +#476000000 +0! +#477000000 +1" +b100101 % +b100100 * +0' +1( +#478000000 +0" +#479000000 +1# +b100101 & +b100101 + +0( +1) +#480000000 +0# +#481000000 +1# +#482000000 +0# +#483000000 +1! +b100101 $ +b100101 , +1' +0) +#484000000 +0! +#485000000 +1# +b100110 & +b100101 * +0' +1) +#486000000 +0# +#487000000 +1! +b100110 $ +b100110 , +1' +0) +#488000000 +0! +#489000000 +1# +#490000000 +0# +#491000000 +1! +#492000000 +0! +#493000000 +1# +#494000000 +0# +#495000000 +1" +b100110 % +b100110 * +0' +1( +#496000000 +0" +#497000000 +1# +b100111 & +b100110 + +0( +1) +#498000000 +0# +#499000000 +1! +b100111 $ +b100111 , +1' +0) +#500000000 +0! +#501000000 +1# +#502000000 +0# +#503000000 +1# +#504000000 +0# +#505000000 +1# +#506000000 +0# +#507000000 +1" +b100111 % +b100111 * +0' +1( +#508000000 +0" +#509000000 +1! +b101000 $ +b100111 + +1' +0( +#510000000 +0! +#511000000 +1! +#512000000 +0! +#513000000 +1# +b101000 & +b101000 * +0' +1) +#514000000 +0# +#515000000 +1" +b101000 % +b101000 , +1( +0) +#516000000 +0" +#517000000 +1! +b101001 $ +b101000 + +1' +0( +#518000000 +0! +#519000000 +1" +b101001 % +b101001 * +0' +1( +#520000000 +0" +#521000000 +1# +b101001 & +b101001 + +0( +1) +#522000000 +0# +#523000000 +1" +b101010 % +b101001 , +1( +0) +#524000000 +0" +#525000000 +1! +b101010 $ +b101010 + +1' +0( +#526000000 +0! +#527000000 +1# +b101010 & +b101010 * +0' +1) +#528000000 +0# +#529000000 +1# +b101011 & +b101010 , +#530000000 +0# +#531000000 +1" +b101011 % +b101011 , +1( +0) +#532000000 +0" +#533000000 +1" +#534000000 +0" +#535000000 +1! +b101011 $ +b101011 + +1' +0( +#536000000 +0! +#537000000 +1# +b101100 & +b101011 * +0' +1) +#538000000 +0# +#539000000 +1" +b101100 % +b101100 , +1( +0) +#540000000 +0" +#541000000 +1" +#542000000 +0" +#543000000 +1" +#544000000 +0" +#545000000 +1# +#546000000 +0# +#547000000 +1" +#548000000 +0" +#549000000 +1" +#550000000 +0" +#551000000 +1# +#552000000 +0# +#553000000 +1# +#554000000 +0# +#555000000 +1" +#556000000 +0" +#557000000 +1# +#558000000 +0# +#559000000 +1! +b101100 $ +b101100 + +1' +0( +#560000000 +0! +#561000000 +1# +b101101 & +b101100 * +0' +1) +#562000000 +0# +#563000000 +1" +b101101 % +b101101 , +1( +0) +#564000000 +0" +#565000000 +1# +#566000000 +0# +#567000000 +1" +#568000000 +0" +#569000000 +1# +#570000000 +0# +#571000000 +1" +#572000000 +0" +#573000000 +1# +#574000000 +0# +#575000000 +1# +#576000000 +0# +#577000000 +1# +#578000000 +0# +#579000000 +1# +#580000000 +0# +#581000000 +1! +b101101 $ +b101101 + +1' +0( +#582000000 +0! +#583000000 +1! +b101110 $ +b101101 * +#584000000 +0! +#585000000 +1# +b101110 & +b101110 * +0' +1) +#586000000 +0# +#587000000 +1# +#588000000 +0# +#589000000 +1! +#590000000 +0! +#591000000 +1" +b101110 % +b101110 , +1( +0) +#592000000 +0" +#593000000 +1# +b101111 & +b101110 + +0( +1) +#594000000 +0# +#595000000 +1# +#596000000 +0# +#597000000 +1! +b101111 $ +b101111 , +1' +0) +#598000000 +0! +#599000000 +1# +#600000000 +0# +#601000000 +1# +#602000000 +0# +#603000000 +1# +#604000000 +0# +#605000000 +1" +b101111 % +b101111 * +0' +1( +#606000000 +0" +#607000000 +1! +b110000 $ +b101111 + +1' +0( +#608000000 +0! +#609000000 +1# +b110000 & +b110000 * +0' +1) +#610000000 +0# +#611000000 +1# +#612000000 +0# +#613000000 +1" +b110000 % +b110000 , +1( +0) +#614000000 +0" +#615000000 +1" +b110001 % +b110000 + +#616000000 +0" +#617000000 +1# +b110001 & +b110001 + +0( +1) +#618000000 +0# +#619000000 +1# +#620000000 +0# +#621000000 +1" +#622000000 +0" +#623000000 +1# +#624000000 +0# +#625000000 +1# +#626000000 +0# +#627000000 +1# +#628000000 +0# +#629000000 +1# +#630000000 +0# +#631000000 +1! +b110001 $ +b110001 , +1' +0) +#632000000 +0! +#633000000 +1# +b110010 & +b110001 * +0' +1) +#634000000 +0# +#635000000 +1# +#636000000 +0# +#637000000 +1# +#638000000 +0# +#639000000 +1" +b110010 % +b110010 , +1( +0) +#640000000 +0" +#641000000 +1# +#642000000 +0# +#643000000 +1# +#644000000 +0# +#645000000 +1# +#646000000 +0# +#647000000 +1# +#648000000 +0# diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt index 351f944..7b11157 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt @@ -121,6 +121,7 @@ Simulation { }.out, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -187,6 +188,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -361,7 +363,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", ty: AsyncReset, }, ], @@ -411,7 +413,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], @@ -460,7 +462,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", ty: AsyncReset, }, ], @@ -509,7 +511,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt index abd7cf6..0ca767a 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt @@ -121,6 +121,7 @@ Simulation { }.out, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -187,6 +188,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -361,7 +363,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", ty: AsyncReset, }, ], @@ -411,7 +413,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], @@ -460,7 +462,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", ty: AsyncReset, }, ], @@ -509,7 +511,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt index 8ff0c2f..4af2eb6 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt @@ -121,6 +121,7 @@ Simulation { }.out, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -187,6 +188,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -361,7 +363,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], @@ -411,7 +413,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], @@ -460,7 +462,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt index e681947..45f09d2 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt @@ -121,6 +121,7 @@ Simulation { }.out, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -187,6 +188,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -361,7 +363,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], @@ -411,7 +413,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], @@ -460,7 +462,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json index 04227ef..a74cef9 100644 --- a/crates/fayalite/visit_types.json +++ b/crates/fayalite/visit_types.json @@ -162,6 +162,7 @@ "$kind": "Struct", "verilog_name": "Visible", "parameters": "Visible", + "clocks_for_past": "Visible", "simulation": "Visible" } },