From c97b44d9d646a4aa64fcc046538fc2354bb708ee Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 14 Dec 2025 20:41:16 -0800
Subject: [PATCH] simplify SimValue Debug format, making complex structures
 much easier to read

---
 crates/fayalite/src/sim/value.rs              |  6 +--
 .../tests/sim/expected/extern_module2.txt     | 18 +++----
 .../tests/sim/expected/ripple_counter.txt     | 54 +++++++------------
 .../tests/sim/expected/sim_fork_join.txt      | 18 +++----
 .../sim/expected/sim_fork_join_scope.txt      | 18 +++----
 .../tests/sim/expected/sim_only_connects.txt  | 36 +++++--------
 .../tests/sim/expected/sim_read_past.txt      | 18 +++----
 .../expected/sim_resettable_counter_async.txt | 36 +++++--------
 ...settable_counter_async_immediate_reset.txt | 36 +++++--------
 .../expected/sim_resettable_counter_sync.txt  | 27 ++++------
 ...esettable_counter_sync_immediate_reset.txt | 27 ++++------
 11 files changed, 97 insertions(+), 197 deletions(-)

diff --git a/crates/fayalite/src/sim/value.rs b/crates/fayalite/src/sim/value.rs
index def2ae3..b6a4e4b 100644
--- a/crates/fayalite/src/sim/value.rs
+++ b/crates/fayalite/src/sim/value.rs
@@ -358,11 +358,7 @@ impl<T: Type> DerefMut for SimValue<T> {
 
 impl<T: Type> fmt::Debug for SimValue<T> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        let inner = self.inner.share();
-        f.debug_struct("SimValue")
-            .field("ty", &inner.ty)
-            .field("value", &inner.value)
-            .finish()
+        T::SimValue::fmt(&**self, f)
     }
 }
 
diff --git a/crates/fayalite/tests/sim/expected/extern_module2.txt b/crates/fayalite/tests/sim/expected/extern_module2.txt
index fa6e767..365830f 100644
--- a/crates/fayalite/tests/sim/expected/extern_module2.txt
+++ b/crates/fayalite/tests/sim/expected/extern_module2.txt
@@ -354,12 +354,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: Clock,
-                    value: OpaqueSimValue {
-                        bits: 0x1_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x1_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -404,12 +401,9 @@ Simulation {
             },
             write: None,
         }: (
-            SimValue {
-                ty: Clock,
-                value: OpaqueSimValue {
-                    bits: 0x1_u1,
-                    sim_only_values: [],
-                },
+            OpaqueSimValue {
+                bits: 0x1_u1,
+                sim_only_values: [],
             },
             {
                 SensitivitySet {
diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.txt b/crates/fayalite/tests/sim/expected/ripple_counter.txt
index 9cc5f02..2be69b5 100644
--- a/crates/fayalite/tests/sim/expected/ripple_counter.txt
+++ b/crates/fayalite/tests/sim/expected/ripple_counter.txt
@@ -1505,12 +1505,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: Clock,
-                    value: OpaqueSimValue {
-                        bits: 0x0_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -1555,12 +1552,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: Clock,
-                    value: OpaqueSimValue {
-                        bits: 0x0_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -1605,12 +1599,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: Clock,
-                    value: OpaqueSimValue {
-                        bits: 0x0_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -1655,12 +1646,9 @@ Simulation {
             },
             write: None,
         }: (
-            SimValue {
-                ty: Clock,
-                value: OpaqueSimValue {
-                    bits: 0x0_u1,
-                    sim_only_values: [],
-                },
+            OpaqueSimValue {
+                bits: 0x0_u1,
+                sim_only_values: [],
             },
             {
                 SensitivitySet {
@@ -1704,12 +1692,9 @@ Simulation {
             },
             write: None,
         }: (
-            SimValue {
-                ty: Clock,
-                value: OpaqueSimValue {
-                    bits: 0x0_u1,
-                    sim_only_values: [],
-                },
+            OpaqueSimValue {
+                bits: 0x0_u1,
+                sim_only_values: [],
             },
             {
                 SensitivitySet {
@@ -1753,12 +1738,9 @@ Simulation {
             },
             write: None,
         }: (
-            SimValue {
-                ty: Clock,
-                value: OpaqueSimValue {
-                    bits: 0x0_u1,
-                    sim_only_values: [],
-                },
+            OpaqueSimValue {
+                bits: 0x0_u1,
+                sim_only_values: [],
             },
             {
                 SensitivitySet {
diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join.txt b/crates/fayalite/tests/sim/expected/sim_fork_join.txt
index 680fedb..df9c092 100644
--- a/crates/fayalite/tests/sim/expected/sim_fork_join.txt
+++ b/crates/fayalite/tests/sim/expected/sim_fork_join.txt
@@ -456,12 +456,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: Clock,
-                    value: OpaqueSimValue {
-                        bits: 0x0_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -506,12 +503,9 @@ Simulation {
             },
             write: None,
         }: (
-            SimValue {
-                ty: Clock,
-                value: OpaqueSimValue {
-                    bits: 0x0_u1,
-                    sim_only_values: [],
-                },
+            OpaqueSimValue {
+                bits: 0x0_u1,
+                sim_only_values: [],
             },
             {
                 SensitivitySet {
diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt
index 40d16a9..917dd5d 100644
--- a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt
+++ b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt
@@ -456,12 +456,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: Clock,
-                    value: OpaqueSimValue {
-                        bits: 0x0_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -506,12 +503,9 @@ Simulation {
             },
             write: None,
         }: (
-            SimValue {
-                ty: Clock,
-                value: OpaqueSimValue {
-                    bits: 0x0_u1,
-                    sim_only_values: [],
-                },
+            OpaqueSimValue {
+                bits: 0x0_u1,
+                sim_only_values: [],
             },
             {
                 SensitivitySet {
diff --git a/crates/fayalite/tests/sim/expected/sim_only_connects.txt b/crates/fayalite/tests/sim/expected/sim_only_connects.txt
index 15456d2..af41fe2 100644
--- a/crates/fayalite/tests/sim/expected/sim_only_connects.txt
+++ b/crates/fayalite/tests/sim/expected/sim_only_connects.txt
@@ -1583,12 +1583,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 6, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: Clock,
-                    value: OpaqueSimValue {
-                        bits: 0x1_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x1_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -1633,12 +1630,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 13, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: Clock,
-                    value: OpaqueSimValue {
-                        bits: 0x1_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x1_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -1683,12 +1677,9 @@ Simulation {
             },
             write: None,
         }: (
-            SimValue {
-                ty: Clock,
-                value: OpaqueSimValue {
-                    bits: 0x1_u1,
-                    sim_only_values: [],
-                },
+            OpaqueSimValue {
+                bits: 0x1_u1,
+                sim_only_values: [],
             },
             {
                 SensitivitySet {
@@ -1732,12 +1723,9 @@ Simulation {
             },
             write: None,
         }: (
-            SimValue {
-                ty: Clock,
-                value: OpaqueSimValue {
-                    bits: 0x1_u1,
-                    sim_only_values: [],
-                },
+            OpaqueSimValue {
+                bits: 0x1_u1,
+                sim_only_values: [],
             },
             {
                 SensitivitySet {
diff --git a/crates/fayalite/tests/sim/expected/sim_read_past.txt b/crates/fayalite/tests/sim/expected/sim_read_past.txt
index 475943e..6df4571 100644
--- a/crates/fayalite/tests/sim/expected/sim_read_past.txt
+++ b/crates/fayalite/tests/sim/expected/sim_read_past.txt
@@ -9655,12 +9655,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: Clock,
-                    value: OpaqueSimValue {
-                        bits: 0x0_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -9705,12 +9702,9 @@ Simulation {
             },
             write: None,
         }: (
-            SimValue {
-                ty: Clock,
-                value: OpaqueSimValue {
-                    bits: 0x0_u1,
-                    sim_only_values: [],
-                },
+            OpaqueSimValue {
+                bits: 0x0_u1,
+                sim_only_values: [],
             },
             {
                 SensitivitySet {
diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt
index 7b11157..3fea928 100644
--- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt
+++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt
@@ -384,12 +384,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: AsyncReset,
-                    value: OpaqueSimValue {
-                        bits: 0x0_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -434,12 +431,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: Clock,
-                    value: OpaqueSimValue {
-                        bits: 0x0_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -484,12 +478,9 @@ Simulation {
             },
             write: None,
         }: (
-            SimValue {
-                ty: AsyncReset,
-                value: OpaqueSimValue {
-                    bits: 0x0_u1,
-                    sim_only_values: [],
-                },
+            OpaqueSimValue {
+                bits: 0x0_u1,
+                sim_only_values: [],
             },
             {
                 SensitivitySet {
@@ -533,12 +524,9 @@ Simulation {
             },
             write: None,
         }: (
-            SimValue {
-                ty: Clock,
-                value: OpaqueSimValue {
-                    bits: 0x0_u1,
-                    sim_only_values: [],
-                },
+            OpaqueSimValue {
+                bits: 0x0_u1,
+                sim_only_values: [],
             },
             {
                 SensitivitySet {
diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt
index 0ca767a..2283ce5 100644
--- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt
+++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt
@@ -384,12 +384,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: AsyncReset,
-                    value: OpaqueSimValue {
-                        bits: 0x0_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -434,12 +431,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: Clock,
-                    value: OpaqueSimValue {
-                        bits: 0x0_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -484,12 +478,9 @@ Simulation {
             },
             write: None,
         }: (
-            SimValue {
-                ty: AsyncReset,
-                value: OpaqueSimValue {
-                    bits: 0x0_u1,
-                    sim_only_values: [],
-                },
+            OpaqueSimValue {
+                bits: 0x0_u1,
+                sim_only_values: [],
             },
             {
                 SensitivitySet {
@@ -533,12 +524,9 @@ Simulation {
             },
             write: None,
         }: (
-            SimValue {
-                ty: Clock,
-                value: OpaqueSimValue {
-                    bits: 0x0_u1,
-                    sim_only_values: [],
-                },
+            OpaqueSimValue {
+                bits: 0x0_u1,
+                sim_only_values: [],
             },
             {
                 SensitivitySet {
diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt
index 4af2eb6..c77046f 100644
--- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt
+++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt
@@ -384,12 +384,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: Clock,
-                    value: OpaqueSimValue {
-                        bits: 0x0_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -434,12 +431,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: Clock,
-                    value: OpaqueSimValue {
-                        bits: 0x0_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -484,12 +478,9 @@ Simulation {
             },
             write: None,
         }: (
-            SimValue {
-                ty: Clock,
-                value: OpaqueSimValue {
-                    bits: 0x0_u1,
-                    sim_only_values: [],
-                },
+            OpaqueSimValue {
+                bits: 0x0_u1,
+                sim_only_values: [],
             },
             {
                 SensitivitySet {
diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt
index 45f09d2..e1c565a 100644
--- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt
+++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt
@@ -384,12 +384,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: Clock,
-                    value: OpaqueSimValue {
-                        bits: 0x0_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -434,12 +431,9 @@ Simulation {
                         sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
                     },
                     write: None,
-                }: SimValue {
-                    ty: Clock,
-                    value: OpaqueSimValue {
-                        bits: 0x0_u1,
-                        sim_only_values: [],
-                    },
+                }: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
                 },
             },
             changed: Cell {
@@ -484,12 +478,9 @@ Simulation {
             },
             write: None,
         }: (
-            SimValue {
-                ty: Clock,
-                value: OpaqueSimValue {
-                    bits: 0x0_u1,
-                    sim_only_values: [],
-                },
+            OpaqueSimValue {
+                bits: 0x0_u1,
+                sim_only_values: [],
             },
             {
                 SensitivitySet {