From c756aeec704e3abcb54b023b6f215d25338701ca Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 12 Dec 2024 20:50:41 -0800 Subject: [PATCH] tests/sim: add test for memory rw port --- crates/fayalite/tests/sim.rs | 273 +++ .../fayalite/tests/sim/expected/memories2.txt | 1694 +++++++++++++++++ .../fayalite/tests/sim/expected/memories2.vcd | 363 ++++ 3 files changed, 2330 insertions(+) create mode 100644 crates/fayalite/tests/sim/expected/memories2.txt create mode 100644 crates/fayalite/tests/sim/expected/memories2.vcd diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index 2b8f276..3fc643c 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -694,4 +694,277 @@ fn test_memories() { } } +#[hdl_module(outline_generated)] +pub fn memories2() { + #[hdl] + let rw: fayalite::memory::ReadWriteStruct, ConstUsize<3>> = m.input(); + #[hdl] + let mut mem = memory_with_init([HdlSome(true); 5]); + mem.read_latency(1); + mem.write_latency(NonZeroUsize::new(1).unwrap()); + mem.read_under_write(ReadUnderWrite::New); + let rw_port = mem.new_rw_port(); + connect_any(rw_port.addr, rw.addr); + connect(rw_port.en, rw.en); + connect(rw_port.clk, rw.clk); + connect_any(rw.rdata, rw_port.rdata.cast_to_bits()); + connect(rw_port.wmode, rw.wmode); + connect(rw_port.wdata, HdlNone()); + #[hdl] + if rw.wdata[0] { + connect(rw_port.wdata, HdlSome(rw.wdata[1])); + } + connect(rw_port.wmask, rw.wmask); +} + +#[hdl] +#[test] +fn test_memories2() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut sim = Simulation::new(memories2()); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + sim.write_clock(sim.io().rw.clk, false); + #[derive(Debug, PartialEq, Eq)] + struct IO { + addr: u8, + en: bool, + rdata: u8, + wmode: bool, + wdata: u8, + wmask: bool, + } + let io_cycles = [ + IO { + addr: 0, + en: false, + rdata: 0, + wmode: false, + wdata: 0, + wmask: false, + }, + IO { + addr: 0, + en: true, + rdata: 0x3, + wmode: false, + wdata: 0, + wmask: false, + }, + IO { + addr: 0, + en: false, + rdata: 0, + wmode: false, + wdata: 0, + wmask: false, + }, + IO { + addr: 0, + en: true, + rdata: 0, + wmode: true, + wdata: 0, + wmask: true, + }, + IO { + addr: 0, + en: true, + rdata: 0, + wmode: false, + wdata: 0, + wmask: false, + }, + IO { + addr: 0, + en: true, + rdata: 0, + wmode: true, + wdata: 3, + wmask: false, + }, + IO { + addr: 1, + en: true, + rdata: 0, + wmode: true, + wdata: 1, + wmask: true, + }, + IO { + addr: 2, + en: true, + rdata: 0, + wmode: true, + wdata: 2, + wmask: true, + }, + IO { + addr: 3, + en: true, + rdata: 0, + wmode: true, + wdata: 3, + wmask: true, + }, + IO { + addr: 4, + en: true, + rdata: 0, + wmode: true, + wdata: 2, + wmask: true, + }, + IO { + addr: 5, + en: true, + rdata: 0, + wmode: true, + wdata: 1, + wmask: true, + }, + IO { + addr: 6, + en: true, + rdata: 0, + wmode: true, + wdata: 1, + wmask: true, + }, + IO { + addr: 7, + en: true, + rdata: 0, + wmode: true, + wdata: 1, + wmask: true, + }, + IO { + addr: 7, + en: true, + rdata: 0, + wmode: false, + wdata: 0, + wmask: false, + }, + IO { + addr: 6, + en: true, + rdata: 0, + wmode: false, + wdata: 0, + wmask: false, + }, + IO { + addr: 5, + en: true, + rdata: 0, + wmode: false, + wdata: 0, + wmask: false, + }, + IO { + addr: 4, + en: true, + rdata: 0, + wmode: false, + wdata: 0, + wmask: false, + }, + IO { + addr: 3, + en: true, + rdata: 3, + wmode: false, + wdata: 0, + wmask: false, + }, + IO { + addr: 2, + en: true, + rdata: 0, + wmode: false, + wdata: 0, + wmask: false, + }, + IO { + addr: 0, + en: true, + rdata: 0, + wmode: false, + wdata: 0, + wmask: false, + }, + IO { + addr: 1, + en: true, + rdata: 1, + wmode: false, + wdata: 0, + wmask: false, + }, + IO { + addr: 0, + en: false, + rdata: 0, + wmode: false, + wdata: 0, + wmask: false, + }, + ]; + for ( + cycle, + expected @ IO { + addr, + en, + rdata: _, + wmode, + wdata, + wmask, + }, + ) in io_cycles.into_iter().enumerate() + { + sim.write_bool_or_int(sim.io().rw.addr, addr.cast_to_static()); + sim.write_bool(sim.io().rw.en, en); + sim.write_bool(sim.io().rw.wmode, wmode); + sim.write_bool_or_int(sim.io().rw.wdata, wdata.cast_to_static()); + sim.write_bool(sim.io().rw.wmask, wmask); + sim.advance_time(SimDuration::from_nanos(250)); + sim.write_clock(sim.io().rw.clk, true); + sim.advance_time(SimDuration::from_nanos(250)); + let io = IO { + addr, + en, + rdata: sim + .read_bool_or_int(sim.io().rw.rdata) + .to_bigint() + .try_into() + .expect("known to be in range"), + wmode, + wdata, + wmask, + }; + assert_eq!( + expected, + io, + "cycle: {cycle}\nvcd:\n{}", + String::from_utf8(writer.take()).unwrap(), + ); + sim.advance_time(SimDuration::from_nanos(250)); + sim.write_clock(sim.io().rw.clk, false); + sim.advance_time(SimDuration::from_nanos(250)); + } + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/memories2.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/memories2.txt") { + panic!(); + } +} + // TODO: add more tests for memories diff --git a/crates/fayalite/tests/sim/expected/memories2.txt b/crates/fayalite/tests/sim/expected/memories2.txt new file mode 100644 index 0000000..5d90815 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/memories2.txt @@ -0,0 +1,1694 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 11, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 36, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.addr", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + }, + ], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, + data: [ + // len = 0x5 + [0x0]: 0x3, + [0x1]: 0x3, + [0x2]: 0x3, + [0x3]: 0x3, + [0x4]: 0x3, + ], + }, + ], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:13:1 + 0: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask", ty: Bool }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 1: SliceInt { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", ty: UInt<2> }, + start: 1, + len: 1, + }, + 2: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 3: Const { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 4: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 5: Copy { + dest: StatePartIndex(27), // (0x0) SlotDebugData { name: ".1", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 6: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(27), // (0x0) SlotDebugData { name: ".1", ty: Bool }, + }, + 7: Shl { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(31), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + rhs: 1, + }, + 8: Or { + dest: StatePartIndex(33), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(26), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 9: CastToUInt { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(33), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 2, + }, + 10: Copy { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} }, + src: StatePartIndex(34), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 11: SliceInt { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", ty: UInt<2> }, + start: 0, + len: 1, + }, + 12: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 13: Const { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + 14: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: module-XXXXXXXXXX.rs:10:1 + 15: Copy { + dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} }, + }, + // at: module-XXXXXXXXXX.rs:11:1 + 16: BranchIfZero { + target: 18, + value: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:12:1 + 17: Copy { + dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 18: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode", ty: Bool }, + src: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:7:1 + 19: Copy { + dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk", ty: Clock }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.clk", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 20: Copy { + dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.en", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:5:1 + 21: Copy { + dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr", ty: UInt<3> }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.addr", ty: UInt<3> }, + }, + // at: module-XXXXXXXXXX.rs:3:1 + 22: BranchIfSmallZero { + target: 26, + value: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 23: BranchIfSmallNonZero { + target: 26, + value: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 24: MemoryReadUInt { + dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x5 + // [0x0]: 0x0, + // [0x1]: 0x1, + // [0x2]: 0x0, + // [0x3]: 0x3, + // [0x4]: 0x0, + // ], + // }) (), + addr: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 2, + start: 0, + width: 2, + }, + 25: Branch { + target: 27, + }, + 26: Const { + dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} }, + value: 0x0, + }, + 27: IsNonZeroDestIsSmall { + dest: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode", ty: Bool }, + }, + 28: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr", ty: UInt<3> }, + }, + 29: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en", ty: Bool }, + }, + 30: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk", ty: Clock }, + }, + 31: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 32: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} }, + }, + 33: SliceInt { + dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 1, + len: 1, + }, + 34: Copy { + dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 35: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 36: Copy { + dest: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} }, + }, + 37: SliceInt { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + start: 1, + len: 1, + }, + 38: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 39: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata", ty: UInt<2> }, + src: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 40: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:3:1 + 41: BranchIfSmallZero { + target: 51, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 42: CopySmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 43: CopySmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 44: Copy { + dest: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} }, + src: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} }, + }, + 45: Copy { + dest: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask", ty: Bool }, + }, + 46: CopySmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 47: BranchIfSmallZero { + target: 51, + value: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 48: BranchIfSmallZero { + target: 51, + value: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 49: BranchIfZero { + target: 51, + value: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + 50: MemoryWriteUInt { + value: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x5 + // [0x0]: 0x0, + // [0x1]: 0x1, + // [0x2]: 0x0, + // [0x3]: 0x3, + // [0x4]: 0x0, + // ], + // }) (), + addr: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 2, + start: 0, + width: 2, + }, + 51: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 52: Return, + ], + .. + }, + pc: 52, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, + data: [ + // len = 0x5 + [0x0]: 0x0, + [0x1]: 0x1, + [0x2]: 0x0, + [0x3]: 0x3, + [0x4]: 0x0, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + ], + }, + }, + io: Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }, + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + rdata: UInt<2>, + /* offset = 7 */ + wmode: Bool, + /* offset = 8 */ + wdata: UInt<2>, + /* offset = 10 */ + wmask: Bool, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 7, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.addr", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<3>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(2), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(3), + }, + ty: CompiledTypeLayout { + ty: UInt<2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(4), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(5), + }, + ty: CompiledTypeLayout { + ty: UInt<2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(6), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 7 }, + }, + write: None, + }, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.addr: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<3>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.en: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.rdata: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.wdata: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<2>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 5, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.wmask: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 6, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.wmode: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 1 }, + }, + write: None, + }, + }, + made_initial_step: true, + needs_settle: false, + trace_decls: TraceModule { + name: "memories2", + children: [ + TraceModuleIO { + name: "rw", + child: TraceBundle { + name: "rw", + fields: [ + TraceUInt { + location: TraceScalarId(0), + name: "addr", + ty: UInt<3>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(2), + name: "clk", + flow: Source, + }, + TraceUInt { + location: TraceScalarId(3), + name: "rdata", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(4), + name: "wmode", + flow: Source, + }, + TraceUInt { + location: TraceScalarId(5), + name: "wdata", + ty: UInt<2>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(6), + name: "wmask", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + rdata: UInt<2>, + /* offset = 7 */ + wmode: Bool, + /* offset = 8 */ + wdata: UInt<2>, + /* offset = 10 */ + wmask: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + rdata: UInt<2>, + /* offset = 7 */ + wmode: Bool, + /* offset = 8 */ + wdata: UInt<2>, + /* offset = 10 */ + wmask: Bool, + }, + flow: Source, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 2, + element_type: TraceEnumWithFields { + name: "mem", + discriminant: TraceEnumDiscriminant { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 5, + stride: 2, + start: 0, + len: 1, + }, + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 5, + stride: 2, + start: 1, + len: 1, + }, + name: "HdlSome", + flow: Duplex, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "rw0", + bundle: TraceBundle { + name: "rw0", + fields: [ + TraceUInt { + location: TraceScalarId(7), + name: "addr", + ty: UInt<3>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(8), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(9), + name: "clk", + flow: Sink, + }, + TraceEnumWithFields { + name: "rdata", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(10), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBool { + location: TraceScalarId(11), + name: "HdlSome", + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(12), + name: "wmode", + flow: Sink, + }, + TraceEnumWithFields { + name: "wdata", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(13), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceBool { + location: TraceScalarId(14), + name: "HdlSome", + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(15), + name: "wmask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + rdata: Enum { + HdlNone, + HdlSome(Bool), + }, + /* offset = 7 */ + wmode: Bool, + /* offset = 8 */ + wdata: Enum { + HdlNone, + HdlSome(Bool), + }, + /* offset = 10 */ + wmask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + rdata: Enum { + HdlNone, + HdlSome(Bool), + }, + /* offset = 7 */ + wmode: Bool, + /* offset = 8 */ + wdata: Enum { + HdlNone, + HdlSome(Bool), + }, + /* offset = 10 */ + wmask: Bool, + }, + }, + ], + array_type: Array, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigUInt { + index: StatePartIndex(0), + ty: UInt<3>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigBool { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigClock { + index: StatePartIndex(2), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(3), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(4), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigBool { + index: StatePartIndex(6), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigUInt { + index: StatePartIndex(7), + ty: UInt<3>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigBool { + index: StatePartIndex(8), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigClock { + index: StatePartIndex(9), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigBool { + index: StatePartIndex(11), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(13), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigBool { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 2, + element_type: TraceEnumWithFields { + name: "mem", + discriminant: TraceEnumDiscriminant { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 5, + stride: 2, + start: 0, + len: 1, + }, + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + flow: Duplex, + }, + non_empty_fields: [ + TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 5, + stride: 2, + start: 1, + len: 1, + }, + name: "HdlSome", + flow: Duplex, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "rw0", + bundle: TraceBundle { + name: "rw0", + fields: [ + TraceUInt { + location: TraceScalarId(7), + name: "addr", + ty: UInt<3>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(8), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(9), + name: "clk", + flow: Sink, + }, + TraceEnumWithFields { + name: "rdata", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(10), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + flow: Source, + }, + non_empty_fields: [ + TraceBool { + location: TraceScalarId(11), + name: "HdlSome", + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(12), + name: "wmode", + flow: Sink, + }, + TraceEnumWithFields { + name: "wdata", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(13), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceBool { + location: TraceScalarId(14), + name: "HdlSome", + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Bool), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(15), + name: "wmask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + rdata: Enum { + HdlNone, + HdlSome(Bool), + }, + /* offset = 7 */ + wmode: Bool, + /* offset = 8 */ + wdata: Enum { + HdlNone, + HdlSome(Bool), + }, + /* offset = 10 */ + wmask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + rdata: Enum { + HdlNone, + HdlSome(Bool), + }, + /* offset = 7 */ + wmode: Bool, + /* offset = 8 */ + wdata: Enum { + HdlNone, + HdlSome(Bool), + }, + /* offset = 10 */ + wmask: Bool, + }, + }, + ], + array_type: Array, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + instant: 22 μs, + clocks_triggered: [ + StatePartIndex(3), + ], + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories2.vcd b/crates/fayalite/tests/sim/expected/memories2.vcd new file mode 100644 index 0000000..bd48f24 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/memories2.vcd @@ -0,0 +1,363 @@ +$timescale 1 ps $end +$scope module memories2 $end +$scope struct rw $end +$var wire 3 ! addr $end +$var wire 1 " en $end +$var wire 1 # clk $end +$var wire 2 $ rdata $end +$var wire 1 % wmode $end +$var wire 2 & wdata $end +$var wire 1 ' wmask $end +$upscope $end +$scope struct mem $end +$scope struct contents $end +$scope struct [0] $end +$scope struct mem $end +$var string 1 1 \$tag $end +$var reg 1 6 HdlSome $end +$upscope $end +$upscope $end +$scope struct [1] $end +$scope struct mem $end +$var string 1 2 \$tag $end +$var reg 1 7 HdlSome $end +$upscope $end +$upscope $end +$scope struct [2] $end +$scope struct mem $end +$var string 1 3 \$tag $end +$var reg 1 8 HdlSome $end +$upscope $end +$upscope $end +$scope struct [3] $end +$scope struct mem $end +$var string 1 4 \$tag $end +$var reg 1 9 HdlSome $end +$upscope $end +$upscope $end +$scope struct [4] $end +$scope struct mem $end +$var string 1 5 \$tag $end +$var reg 1 : HdlSome $end +$upscope $end +$upscope $end +$upscope $end +$scope struct rw0 $end +$var wire 3 ( addr $end +$var wire 1 ) en $end +$var wire 1 * clk $end +$scope struct rdata $end +$var string 1 + \$tag $end +$var wire 1 , HdlSome $end +$upscope $end +$var wire 1 - wmode $end +$scope struct wdata $end +$var string 1 . \$tag $end +$var wire 1 / HdlSome $end +$upscope $end +$var wire 1 0 wmask $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +sHdlSome\x20(1) 1 +16 +sHdlSome\x20(1) 2 +17 +sHdlSome\x20(1) 3 +18 +sHdlSome\x20(1) 4 +19 +sHdlSome\x20(1) 5 +1: +b0 ! +0" +0# +b0 $ +0% +b0 & +0' +b0 ( +0) +0* +sHdlNone\x20(0) + +0, +0- +sHdlNone\x20(0) . +0/ +00 +$end +#250000 +1# +1* +#500000 +#750000 +0# +0* +#1000000 +1" +1) +#1250000 +1# +1* +b11 $ +sHdlSome\x20(1) + +1, +#1500000 +#1750000 +0# +0* +#2000000 +0" +0) +#2250000 +1# +1* +b0 $ +sHdlNone\x20(0) + +0, +#2500000 +#2750000 +0# +0* +#3000000 +1" +1% +1' +1) +1- +10 +#3250000 +sHdlNone\x20(0) 1 +06 +1# +1* +#3500000 +#3750000 +0# +0* +#4000000 +0% +0' +0- +00 +#4250000 +1# +1* +#4500000 +#4750000 +0# +0* +#5000000 +1% +b11 & +1- +sHdlSome\x20(1) . +1/ +#5250000 +1# +1* +#5500000 +#5750000 +0# +0* +#6000000 +b1 ! +b1 & +1' +b1 ( +0/ +10 +#6250000 +sHdlSome\x20(1) 2 +07 +1# +1* +#6500000 +#6750000 +0# +0* +#7000000 +b10 ! +b10 & +b10 ( +sHdlNone\x20(0) . +#7250000 +sHdlNone\x20(0) 3 +08 +1# +1* +#7500000 +#7750000 +0# +0* +#8000000 +b11 ! +b11 & +b11 ( +sHdlSome\x20(1) . +1/ +#8250000 +sHdlSome\x20(1) 4 +19 +1# +1* +#8500000 +#8750000 +0# +0* +#9000000 +b100 ! +b10 & +b100 ( +sHdlNone\x20(0) . +0/ +#9250000 +sHdlNone\x20(0) 5 +0: +1# +1* +#9500000 +#9750000 +0# +0* +#10000000 +b101 ! +b1 & +b101 ( +sHdlSome\x20(1) . +#10250000 +1# +1* +#10500000 +#10750000 +0# +0* +#11000000 +b110 ! +b110 ( +#11250000 +1# +1* +#11500000 +#11750000 +0# +0* +#12000000 +b111 ! +b111 ( +#12250000 +1# +1* +#12500000 +#12750000 +0# +0* +#13000000 +0% +b0 & +0' +0- +sHdlNone\x20(0) . +00 +#13250000 +1# +1* +#13500000 +#13750000 +0# +0* +#14000000 +b110 ! +b110 ( +#14250000 +1# +1* +#14500000 +#14750000 +0# +0* +#15000000 +b101 ! +b101 ( +#15250000 +1# +1* +#15500000 +#15750000 +0# +0* +#16000000 +b100 ! +b100 ( +#16250000 +1# +1* +#16500000 +#16750000 +0# +0* +#17000000 +b11 ! +b11 ( +#17250000 +1# +1* +b11 $ +sHdlSome\x20(1) + +1, +#17500000 +#17750000 +0# +0* +#18000000 +b10 ! +b10 ( +#18250000 +1# +1* +b0 $ +sHdlNone\x20(0) + +0, +#18500000 +#18750000 +0# +0* +#19000000 +b0 ! +b0 ( +#19250000 +1# +1* +#19500000 +#19750000 +0# +0* +#20000000 +b1 ! +b1 ( +#20250000 +1# +1* +b1 $ +sHdlSome\x20(1) + +#20500000 +#20750000 +0# +0* +#21000000 +b0 ! +0" +b0 ( +0) +#21250000 +1# +1* +b0 $ +sHdlNone\x20(0) + +#21500000 +#21750000 +0# +0* +#22000000