diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index b9c6a80..873978a 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -3,7 +3,7 @@ use fayalite::{ memory::{ReadStruct, ReadWriteStruct, WriteStruct}, - module::{instance_with_loc, reg_builder_with_loc}, + module::{instance_with_loc, memory_with_init_and_loc, reg_builder_with_loc}, prelude::*, reset::ResetType, sim::vcd::VcdWriterDecls, @@ -1261,6 +1261,310 @@ fn test_memories3() { } } +#[hdl_module(outline_generated)] +pub fn many_memories() { + #[hdl] + let r: Array>, 8> = m.input(); + #[hdl] + let w: Array>, 8> = m.input(); + for (mem_index, (r, w)) in r.into_iter().zip(w).enumerate() { + let mut mem = memory_with_init_and_loc( + &format!("mem_{mem_index}"), + (0..16) + .map(|bit_index| mem_index.pow(5).to_expr()[bit_index]) + .collect::>(), + SourceLocation::caller(), + ); + connect_any(mem.new_read_port(), r); + connect_any(mem.new_write_port(), w); + } +} + +#[hdl] +#[test] +fn test_many_memories() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut sim = Simulation::new(many_memories()); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + for r in sim.io().r { + sim.write_clock(r.clk, false); + } + for w in sim.io().w { + sim.write_clock(w.clk, false); + } + #[hdl(cmp_eq)] + struct IO { + r_addr: UInt<4>, + r_en: Bool, + r_data: Array, + w_addr: UInt<4>, + w_en: Bool, + w_data: Array, + w_mask: Array, + } + let io_cycles = [ + #[hdl(sim)] + IO { + r_addr: 0_hdl_u4, + r_en: false, + r_data: [false; 8], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [false; 8], + }, + #[hdl(sim)] + IO { + r_addr: 0_hdl_u4, + r_en: true, + r_data: [false, true, false, true, false, true, false, true], + w_addr: 0_hdl_u4, + w_en: true, + w_data: [true; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 0_hdl_u4, + r_en: true, + r_data: [true; 8], + w_addr: 0_hdl_u4, + w_en: true, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 0_hdl_u4, + r_en: true, + r_data: [false; 8], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 1_hdl_u4, + r_en: true, + r_data: [false, false, false, true, false, false, false, true], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 2_hdl_u4, + r_en: true, + r_data: [false, false, false, false, false, true, false, true], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 3_hdl_u4, + r_en: true, + r_data: [false, false, false, false, false, false, false, false], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 4_hdl_u4, + r_en: true, + r_data: [false, false, false, true, false, true, false, false], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 5_hdl_u4, + r_en: true, + r_data: [false, false, true, true, false, true, true, true], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 6_hdl_u4, + r_en: true, + r_data: [false, false, false, true, false, false, true, false], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 7_hdl_u4, + r_en: true, + r_data: [false, false, false, true, false, false, false, true], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 8_hdl_u4, + r_en: true, + r_data: [false, false, false, false, false, false, false, true], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 9_hdl_u4, + r_en: true, + r_data: [false, false, false, false, false, false, true, false], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 0xA_hdl_u4, + r_en: true, + r_data: [false, false, false, false, true, true, true, false], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 0xB_hdl_u4, + r_en: true, + r_data: [false, false, false, false, false, true, true, false], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 0xC_hdl_u4, + r_en: true, + r_data: [false, false, false, false, false, false, true, false], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 0xD_hdl_u4, + r_en: true, + r_data: [false, false, false, false, false, false, false, false], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 0xE_hdl_u4, + r_en: true, + r_data: [false, false, false, false, false, false, false, true], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + #[hdl(sim)] + IO { + r_addr: 0xF_hdl_u4, + r_en: true, + r_data: [false, false, false, false, false, false, false, false], + w_addr: 0_hdl_u4, + w_en: false, + w_data: [false; 8], + w_mask: [true; 8], + }, + ]; + for (cycle, expected) in io_cycles.into_iter().enumerate() { + #[hdl(sim)] + let IO { + r_addr, + r_en, + r_data: _, + w_addr, + w_en, + w_data, + w_mask, + } = expected; + for (((r, w), w_data), w_mask) in sim + .io() + .r + .into_iter() + .zip(sim.io().w) + .zip(w_data.iter()) + .zip(w_mask.iter()) + { + sim.write(r.addr, &r_addr); + sim.write(r.en, &r_en); + sim.write(w.addr, &w_addr); + sim.write(w.en, &w_en); + sim.write(w.data, w_data); + sim.write(w.mask, w_mask); + } + let io = #[hdl(sim)] + IO { + r_addr, + r_en, + r_data: std::array::from_fn(|i| sim.read(sim.io().r[i].data)), + w_addr, + w_en, + w_data, + w_mask, + }; + assert_eq!( + expected, + io, + "vcd:\n{}\ncycle: {cycle}", + String::from_utf8(writer.take()).unwrap(), + ); + sim.advance_time(SimDuration::from_micros(1)); + for r in sim.io().r { + sim.write_clock(r.clk, true); + } + for w in sim.io().w { + sim.write_clock(w.clk, true); + } + sim.advance_time(SimDuration::from_micros(1)); + for r in sim.io().r { + sim.write_clock(r.clk, false); + } + for w in sim.io().w { + sim.write_clock(w.clk, false); + } + } + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/many_memories.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/many_memories.txt") { + panic!(); + } +} + #[hdl_module(outline_generated)] pub fn duplicate_names() { #[hdl] diff --git a/crates/fayalite/tests/sim/expected/many_memories.txt b/crates/fayalite/tests/sim/expected/many_memories.txt new file mode 100644 index 0000000..fbbc581 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/many_memories.txt @@ -0,0 +1,7782 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 96, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 160, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].mask", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].mask", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].mask", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].mask", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].mask", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].mask", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].mask", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].mask", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.addr", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.data", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 8, + debug_data: [ + (), + (), + (), + (), + (), + (), + (), + (), + ], + layout_data: [ + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x0, + [0x1]: 0x0, + [0x2]: 0x0, + [0x3]: 0x0, + [0x4]: 0x0, + [0x5]: 0x0, + [0x6]: 0x0, + [0x7]: 0x0, + [0x8]: 0x0, + [0x9]: 0x0, + [0xa]: 0x0, + [0xb]: 0x0, + [0xc]: 0x0, + [0xd]: 0x0, + [0xe]: 0x0, + [0xf]: 0x0, + ], + }, + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x1, + [0x1]: 0x0, + [0x2]: 0x0, + [0x3]: 0x0, + [0x4]: 0x0, + [0x5]: 0x0, + [0x6]: 0x0, + [0x7]: 0x0, + [0x8]: 0x0, + [0x9]: 0x0, + [0xa]: 0x0, + [0xb]: 0x0, + [0xc]: 0x0, + [0xd]: 0x0, + [0xe]: 0x0, + [0xf]: 0x0, + ], + }, + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x0, + [0x1]: 0x0, + [0x2]: 0x0, + [0x3]: 0x0, + [0x4]: 0x0, + [0x5]: 0x1, + [0x6]: 0x0, + [0x7]: 0x0, + [0x8]: 0x0, + [0x9]: 0x0, + [0xa]: 0x0, + [0xb]: 0x0, + [0xc]: 0x0, + [0xd]: 0x0, + [0xe]: 0x0, + [0xf]: 0x0, + ], + }, + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x1, + [0x1]: 0x1, + [0x2]: 0x0, + [0x3]: 0x0, + [0x4]: 0x1, + [0x5]: 0x1, + [0x6]: 0x1, + [0x7]: 0x1, + [0x8]: 0x0, + [0x9]: 0x0, + [0xa]: 0x0, + [0xb]: 0x0, + [0xc]: 0x0, + [0xd]: 0x0, + [0xe]: 0x0, + [0xf]: 0x0, + ], + }, + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x0, + [0x1]: 0x0, + [0x2]: 0x0, + [0x3]: 0x0, + [0x4]: 0x0, + [0x5]: 0x0, + [0x6]: 0x0, + [0x7]: 0x0, + [0x8]: 0x0, + [0x9]: 0x0, + [0xa]: 0x1, + [0xb]: 0x0, + [0xc]: 0x0, + [0xd]: 0x0, + [0xe]: 0x0, + [0xf]: 0x0, + ], + }, + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x1, + [0x1]: 0x0, + [0x2]: 0x1, + [0x3]: 0x0, + [0x4]: 0x1, + [0x5]: 0x1, + [0x6]: 0x0, + [0x7]: 0x0, + [0x8]: 0x0, + [0x9]: 0x0, + [0xa]: 0x1, + [0xb]: 0x1, + [0xc]: 0x0, + [0xd]: 0x0, + [0xe]: 0x0, + [0xf]: 0x0, + ], + }, + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x0, + [0x1]: 0x0, + [0x2]: 0x0, + [0x3]: 0x0, + [0x4]: 0x0, + [0x5]: 0x1, + [0x6]: 0x1, + [0x7]: 0x0, + [0x8]: 0x0, + [0x9]: 0x1, + [0xa]: 0x1, + [0xb]: 0x1, + [0xc]: 0x1, + [0xd]: 0x0, + [0xe]: 0x0, + [0xf]: 0x0, + ], + }, + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x1, + [0x1]: 0x1, + [0x2]: 0x1, + [0x3]: 0x0, + [0x4]: 0x0, + [0x5]: 0x1, + [0x6]: 0x0, + [0x7]: 0x1, + [0x8]: 0x1, + [0x9]: 0x0, + [0xa]: 0x0, + [0xb]: 0x0, + [0xc]: 0x0, + [0xd]: 0x0, + [0xe]: 0x1, + [0xf]: 0x0, + ], + }, + ], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:8:1 + 0: Copy { + dest: StatePartIndex(153), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.addr", ty: UInt<4> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].addr", ty: UInt<4> }, + }, + 1: Copy { + dest: StatePartIndex(154), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.en", ty: Bool }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].en", ty: Bool }, + }, + 2: Copy { + dest: StatePartIndex(155), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.clk", ty: Clock }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].clk", ty: Clock }, + }, + 3: Copy { + dest: StatePartIndex(156), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.data", ty: Bool }, + src: StatePartIndex(70), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].data", ty: Bool }, + }, + 4: Copy { + dest: StatePartIndex(157), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.mask", ty: Bool }, + src: StatePartIndex(71), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].mask", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 5: Copy { + dest: StatePartIndex(151), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.clk", ty: Clock }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].clk", ty: Clock }, + }, + 6: Copy { + dest: StatePartIndex(150), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.en", ty: Bool }, + src: StatePartIndex(29), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].en", ty: Bool }, + }, + 7: Copy { + dest: StatePartIndex(149), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.addr", ty: UInt<4> }, + src: StatePartIndex(28), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].addr", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 8: Copy { + dest: StatePartIndex(142), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.addr", ty: UInt<4> }, + src: StatePartIndex(62), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].addr", ty: UInt<4> }, + }, + 9: Copy { + dest: StatePartIndex(143), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.en", ty: Bool }, + src: StatePartIndex(63), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].en", ty: Bool }, + }, + 10: Copy { + dest: StatePartIndex(144), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.clk", ty: Clock }, + src: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].clk", ty: Clock }, + }, + 11: Copy { + dest: StatePartIndex(145), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.data", ty: Bool }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].data", ty: Bool }, + }, + 12: Copy { + dest: StatePartIndex(146), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.mask", ty: Bool }, + src: StatePartIndex(66), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].mask", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 13: Copy { + dest: StatePartIndex(140), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.clk", ty: Clock }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].clk", ty: Clock }, + }, + 14: Copy { + dest: StatePartIndex(139), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.en", ty: Bool }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].en", ty: Bool }, + }, + 15: Copy { + dest: StatePartIndex(138), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.addr", ty: UInt<4> }, + src: StatePartIndex(24), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].addr", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 16: Copy { + dest: StatePartIndex(131), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.addr", ty: UInt<4> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].addr", ty: UInt<4> }, + }, + 17: Copy { + dest: StatePartIndex(132), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.en", ty: Bool }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].en", ty: Bool }, + }, + 18: Copy { + dest: StatePartIndex(133), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.clk", ty: Clock }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].clk", ty: Clock }, + }, + 19: Copy { + dest: StatePartIndex(134), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.data", ty: Bool }, + src: StatePartIndex(60), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].data", ty: Bool }, + }, + 20: Copy { + dest: StatePartIndex(135), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.mask", ty: Bool }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].mask", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 21: Copy { + dest: StatePartIndex(129), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.clk", ty: Clock }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].clk", ty: Clock }, + }, + 22: Copy { + dest: StatePartIndex(128), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.en", ty: Bool }, + src: StatePartIndex(21), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].en", ty: Bool }, + }, + 23: Copy { + dest: StatePartIndex(127), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.addr", ty: UInt<4> }, + src: StatePartIndex(20), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].addr", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 24: Copy { + dest: StatePartIndex(120), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.addr", ty: UInt<4> }, + src: StatePartIndex(52), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].addr", ty: UInt<4> }, + }, + 25: Copy { + dest: StatePartIndex(121), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.en", ty: Bool }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].en", ty: Bool }, + }, + 26: Copy { + dest: StatePartIndex(122), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.clk", ty: Clock }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].clk", ty: Clock }, + }, + 27: Copy { + dest: StatePartIndex(123), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.data", ty: Bool }, + src: StatePartIndex(55), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].data", ty: Bool }, + }, + 28: Copy { + dest: StatePartIndex(124), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.mask", ty: Bool }, + src: StatePartIndex(56), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].mask", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 29: Copy { + dest: StatePartIndex(118), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.clk", ty: Clock }, + src: StatePartIndex(18), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].clk", ty: Clock }, + }, + 30: Copy { + dest: StatePartIndex(117), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.en", ty: Bool }, + src: StatePartIndex(17), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].en", ty: Bool }, + }, + 31: Copy { + dest: StatePartIndex(116), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.addr", ty: UInt<4> }, + src: StatePartIndex(16), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].addr", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 32: Copy { + dest: StatePartIndex(109), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.addr", ty: UInt<4> }, + src: StatePartIndex(47), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].addr", ty: UInt<4> }, + }, + 33: Copy { + dest: StatePartIndex(110), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.en", ty: Bool }, + src: StatePartIndex(48), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].en", ty: Bool }, + }, + 34: Copy { + dest: StatePartIndex(111), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.clk", ty: Clock }, + src: StatePartIndex(49), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].clk", ty: Clock }, + }, + 35: Copy { + dest: StatePartIndex(112), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.data", ty: Bool }, + src: StatePartIndex(50), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].data", ty: Bool }, + }, + 36: Copy { + dest: StatePartIndex(113), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.mask", ty: Bool }, + src: StatePartIndex(51), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].mask", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 37: Copy { + dest: StatePartIndex(107), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.clk", ty: Clock }, + src: StatePartIndex(14), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].clk", ty: Clock }, + }, + 38: Copy { + dest: StatePartIndex(106), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.en", ty: Bool }, + src: StatePartIndex(13), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].en", ty: Bool }, + }, + 39: Copy { + dest: StatePartIndex(105), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.addr", ty: UInt<4> }, + src: StatePartIndex(12), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].addr", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 40: Copy { + dest: StatePartIndex(98), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.addr", ty: UInt<4> }, + src: StatePartIndex(42), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].addr", ty: UInt<4> }, + }, + 41: Copy { + dest: StatePartIndex(99), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.en", ty: Bool }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].en", ty: Bool }, + }, + 42: Copy { + dest: StatePartIndex(100), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.clk", ty: Clock }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].clk", ty: Clock }, + }, + 43: Copy { + dest: StatePartIndex(101), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.data", ty: Bool }, + src: StatePartIndex(45), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].data", ty: Bool }, + }, + 44: Copy { + dest: StatePartIndex(102), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.mask", ty: Bool }, + src: StatePartIndex(46), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].mask", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 45: Copy { + dest: StatePartIndex(96), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.clk", ty: Clock }, + src: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].clk", ty: Clock }, + }, + 46: Copy { + dest: StatePartIndex(95), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.en", ty: Bool }, + src: StatePartIndex(9), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].en", ty: Bool }, + }, + 47: Copy { + dest: StatePartIndex(94), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.addr", ty: UInt<4> }, + src: StatePartIndex(8), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].addr", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 48: Copy { + dest: StatePartIndex(87), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.addr", ty: UInt<4> }, + src: StatePartIndex(37), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].addr", ty: UInt<4> }, + }, + 49: Copy { + dest: StatePartIndex(88), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.en", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].en", ty: Bool }, + }, + 50: Copy { + dest: StatePartIndex(89), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.clk", ty: Clock }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].clk", ty: Clock }, + }, + 51: Copy { + dest: StatePartIndex(90), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.data", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].data", ty: Bool }, + }, + 52: Copy { + dest: StatePartIndex(91), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].mask", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 53: Copy { + dest: StatePartIndex(85), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.clk", ty: Clock }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].clk", ty: Clock }, + }, + 54: Copy { + dest: StatePartIndex(84), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.en", ty: Bool }, + src: StatePartIndex(5), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].en", ty: Bool }, + }, + 55: Copy { + dest: StatePartIndex(83), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.addr", ty: UInt<4> }, + src: StatePartIndex(4), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].addr", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 56: Copy { + dest: StatePartIndex(76), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.addr", ty: UInt<4> }, + src: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].addr", ty: UInt<4> }, + }, + 57: Copy { + dest: StatePartIndex(77), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.en", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].en", ty: Bool }, + }, + 58: Copy { + dest: StatePartIndex(78), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.clk", ty: Clock }, + src: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].clk", ty: Clock }, + }, + 59: Copy { + dest: StatePartIndex(79), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.data", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].data", ty: Bool }, + }, + 60: Copy { + dest: StatePartIndex(80), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.mask", ty: Bool }, + src: StatePartIndex(36), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].mask", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 61: Copy { + dest: StatePartIndex(74), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.clk", ty: Clock }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].clk", ty: Clock }, + }, + 62: Copy { + dest: StatePartIndex(73), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.en", ty: Bool }, + src: StatePartIndex(1), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].en", ty: Bool }, + }, + 63: Copy { + dest: StatePartIndex(72), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.addr", ty: UInt<4> }, + src: StatePartIndex(0), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].addr", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 64: CastBigToArrayIndex { + dest: StatePartIndex(93), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(153), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.addr", ty: UInt<4> }, + }, + 65: IsNonZeroDestIsSmall { + dest: StatePartIndex(92), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(154), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.en", ty: Bool }, + }, + 66: IsNonZeroDestIsSmall { + dest: StatePartIndex(91), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(155), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.clk", ty: Clock }, + }, + 67: AndSmall { + dest: StatePartIndex(90), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(91), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(89), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 68: CastBigToArrayIndex { + dest: StatePartIndex(88), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(149), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.addr", ty: UInt<4> }, + }, + 69: IsNonZeroDestIsSmall { + dest: StatePartIndex(87), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(150), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.en", ty: Bool }, + }, + 70: BranchIfSmallZero { + target: 73, + value: StatePartIndex(87), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 71: MemoryReadUInt { + dest: StatePartIndex(152), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.data", ty: Bool }, + memory: StatePartIndex(7), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x1, + // [0x2]: 0x1, + // [0x3]: 0x0, + // [0x4]: 0x0, + // [0x5]: 0x1, + // [0x6]: 0x0, + // [0x7]: 0x1, + // [0x8]: 0x1, + // [0x9]: 0x0, + // [0xa]: 0x0, + // [0xb]: 0x0, + // [0xc]: 0x0, + // [0xd]: 0x0, + // [0xe]: 0x1, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(88), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 72: Branch { + target: 74, + }, + 73: Const { + dest: StatePartIndex(152), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.data", ty: Bool }, + value: 0x0, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 74: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].data", ty: Bool }, + src: StatePartIndex(152), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.data", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 75: IsNonZeroDestIsSmall { + dest: StatePartIndex(86), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(151), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.clk", ty: Clock }, + }, + 76: AndSmall { + dest: StatePartIndex(85), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(86), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(84), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 77: CastBigToArrayIndex { + dest: StatePartIndex(81), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(142), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.addr", ty: UInt<4> }, + }, + 78: IsNonZeroDestIsSmall { + dest: StatePartIndex(80), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(143), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.en", ty: Bool }, + }, + 79: IsNonZeroDestIsSmall { + dest: StatePartIndex(79), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(144), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.clk", ty: Clock }, + }, + 80: AndSmall { + dest: StatePartIndex(78), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(79), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(77), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 81: CastBigToArrayIndex { + dest: StatePartIndex(76), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(138), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.addr", ty: UInt<4> }, + }, + 82: IsNonZeroDestIsSmall { + dest: StatePartIndex(75), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(139), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.en", ty: Bool }, + }, + 83: BranchIfSmallZero { + target: 86, + value: StatePartIndex(75), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 84: MemoryReadUInt { + dest: StatePartIndex(141), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.data", ty: Bool }, + memory: StatePartIndex(6), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x0, + // [0x2]: 0x0, + // [0x3]: 0x0, + // [0x4]: 0x0, + // [0x5]: 0x1, + // [0x6]: 0x1, + // [0x7]: 0x0, + // [0x8]: 0x0, + // [0x9]: 0x1, + // [0xa]: 0x1, + // [0xb]: 0x1, + // [0xc]: 0x1, + // [0xd]: 0x0, + // [0xe]: 0x0, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(76), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 85: Branch { + target: 87, + }, + 86: Const { + dest: StatePartIndex(141), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.data", ty: Bool }, + value: 0x0, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 87: Copy { + dest: StatePartIndex(27), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].data", ty: Bool }, + src: StatePartIndex(141), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.data", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 88: IsNonZeroDestIsSmall { + dest: StatePartIndex(74), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(140), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.clk", ty: Clock }, + }, + 89: AndSmall { + dest: StatePartIndex(73), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(74), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(72), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 90: CastBigToArrayIndex { + dest: StatePartIndex(69), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(131), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.addr", ty: UInt<4> }, + }, + 91: IsNonZeroDestIsSmall { + dest: StatePartIndex(68), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(132), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.en", ty: Bool }, + }, + 92: IsNonZeroDestIsSmall { + dest: StatePartIndex(67), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(133), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.clk", ty: Clock }, + }, + 93: AndSmall { + dest: StatePartIndex(66), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(67), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(65), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 94: CastBigToArrayIndex { + dest: StatePartIndex(64), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(127), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.addr", ty: UInt<4> }, + }, + 95: IsNonZeroDestIsSmall { + dest: StatePartIndex(63), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(128), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.en", ty: Bool }, + }, + 96: BranchIfSmallZero { + target: 99, + value: StatePartIndex(63), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 97: MemoryReadUInt { + dest: StatePartIndex(130), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.data", ty: Bool }, + memory: StatePartIndex(5), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x0, + // [0x2]: 0x1, + // [0x3]: 0x0, + // [0x4]: 0x1, + // [0x5]: 0x1, + // [0x6]: 0x0, + // [0x7]: 0x0, + // [0x8]: 0x0, + // [0x9]: 0x0, + // [0xa]: 0x1, + // [0xb]: 0x1, + // [0xc]: 0x0, + // [0xd]: 0x0, + // [0xe]: 0x0, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(64), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 98: Branch { + target: 100, + }, + 99: Const { + dest: StatePartIndex(130), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.data", ty: Bool }, + value: 0x0, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 100: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].data", ty: Bool }, + src: StatePartIndex(130), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.data", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 101: IsNonZeroDestIsSmall { + dest: StatePartIndex(62), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(129), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.clk", ty: Clock }, + }, + 102: AndSmall { + dest: StatePartIndex(61), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(62), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(60), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 103: CastBigToArrayIndex { + dest: StatePartIndex(57), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(120), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.addr", ty: UInt<4> }, + }, + 104: IsNonZeroDestIsSmall { + dest: StatePartIndex(56), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(121), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.en", ty: Bool }, + }, + 105: IsNonZeroDestIsSmall { + dest: StatePartIndex(55), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(122), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.clk", ty: Clock }, + }, + 106: AndSmall { + dest: StatePartIndex(54), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(55), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(53), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 107: CastBigToArrayIndex { + dest: StatePartIndex(52), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(116), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.addr", ty: UInt<4> }, + }, + 108: IsNonZeroDestIsSmall { + dest: StatePartIndex(51), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(117), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.en", ty: Bool }, + }, + 109: BranchIfSmallZero { + target: 112, + value: StatePartIndex(51), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 110: MemoryReadUInt { + dest: StatePartIndex(119), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.data", ty: Bool }, + memory: StatePartIndex(4), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x0, + // [0x2]: 0x0, + // [0x3]: 0x0, + // [0x4]: 0x0, + // [0x5]: 0x0, + // [0x6]: 0x0, + // [0x7]: 0x0, + // [0x8]: 0x0, + // [0x9]: 0x0, + // [0xa]: 0x1, + // [0xb]: 0x0, + // [0xc]: 0x0, + // [0xd]: 0x0, + // [0xe]: 0x0, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(52), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 111: Branch { + target: 113, + }, + 112: Const { + dest: StatePartIndex(119), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.data", ty: Bool }, + value: 0x0, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 113: Copy { + dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].data", ty: Bool }, + src: StatePartIndex(119), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.data", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 114: IsNonZeroDestIsSmall { + dest: StatePartIndex(50), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(118), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.clk", ty: Clock }, + }, + 115: AndSmall { + dest: StatePartIndex(49), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(50), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(48), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 116: CastBigToArrayIndex { + dest: StatePartIndex(45), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(109), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.addr", ty: UInt<4> }, + }, + 117: IsNonZeroDestIsSmall { + dest: StatePartIndex(44), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(110), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.en", ty: Bool }, + }, + 118: IsNonZeroDestIsSmall { + dest: StatePartIndex(43), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(111), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.clk", ty: Clock }, + }, + 119: AndSmall { + dest: StatePartIndex(42), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(43), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(41), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 120: CastBigToArrayIndex { + dest: StatePartIndex(40), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(105), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.addr", ty: UInt<4> }, + }, + 121: IsNonZeroDestIsSmall { + dest: StatePartIndex(39), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(106), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.en", ty: Bool }, + }, + 122: BranchIfSmallZero { + target: 125, + value: StatePartIndex(39), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 123: MemoryReadUInt { + dest: StatePartIndex(108), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.data", ty: Bool }, + memory: StatePartIndex(3), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x1, + // [0x2]: 0x0, + // [0x3]: 0x0, + // [0x4]: 0x1, + // [0x5]: 0x1, + // [0x6]: 0x1, + // [0x7]: 0x1, + // [0x8]: 0x0, + // [0x9]: 0x0, + // [0xa]: 0x0, + // [0xb]: 0x0, + // [0xc]: 0x0, + // [0xd]: 0x0, + // [0xe]: 0x0, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(40), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 124: Branch { + target: 126, + }, + 125: Const { + dest: StatePartIndex(108), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.data", ty: Bool }, + value: 0x0, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 126: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].data", ty: Bool }, + src: StatePartIndex(108), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.data", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 127: IsNonZeroDestIsSmall { + dest: StatePartIndex(38), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(107), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.clk", ty: Clock }, + }, + 128: AndSmall { + dest: StatePartIndex(37), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(38), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(36), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 129: CastBigToArrayIndex { + dest: StatePartIndex(33), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(98), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.addr", ty: UInt<4> }, + }, + 130: IsNonZeroDestIsSmall { + dest: StatePartIndex(32), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(99), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.en", ty: Bool }, + }, + 131: IsNonZeroDestIsSmall { + dest: StatePartIndex(31), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(100), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.clk", ty: Clock }, + }, + 132: AndSmall { + dest: StatePartIndex(30), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(31), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(29), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 133: CastBigToArrayIndex { + dest: StatePartIndex(28), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(94), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.addr", ty: UInt<4> }, + }, + 134: IsNonZeroDestIsSmall { + dest: StatePartIndex(27), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(95), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.en", ty: Bool }, + }, + 135: BranchIfSmallZero { + target: 138, + value: StatePartIndex(27), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 136: MemoryReadUInt { + dest: StatePartIndex(97), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.data", ty: Bool }, + memory: StatePartIndex(2), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x0, + // [0x2]: 0x0, + // [0x3]: 0x0, + // [0x4]: 0x0, + // [0x5]: 0x1, + // [0x6]: 0x0, + // [0x7]: 0x0, + // [0x8]: 0x0, + // [0x9]: 0x0, + // [0xa]: 0x0, + // [0xb]: 0x0, + // [0xc]: 0x0, + // [0xd]: 0x0, + // [0xe]: 0x0, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(28), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 137: Branch { + target: 139, + }, + 138: Const { + dest: StatePartIndex(97), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.data", ty: Bool }, + value: 0x0, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 139: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].data", ty: Bool }, + src: StatePartIndex(97), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.data", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 140: IsNonZeroDestIsSmall { + dest: StatePartIndex(26), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(96), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.clk", ty: Clock }, + }, + 141: AndSmall { + dest: StatePartIndex(25), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(26), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(24), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 142: CastBigToArrayIndex { + dest: StatePartIndex(21), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(87), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.addr", ty: UInt<4> }, + }, + 143: IsNonZeroDestIsSmall { + dest: StatePartIndex(20), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(88), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.en", ty: Bool }, + }, + 144: IsNonZeroDestIsSmall { + dest: StatePartIndex(19), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(89), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.clk", ty: Clock }, + }, + 145: AndSmall { + dest: StatePartIndex(18), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(19), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(17), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 146: CastBigToArrayIndex { + dest: StatePartIndex(16), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(83), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.addr", ty: UInt<4> }, + }, + 147: IsNonZeroDestIsSmall { + dest: StatePartIndex(15), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(84), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.en", ty: Bool }, + }, + 148: BranchIfSmallZero { + target: 151, + value: StatePartIndex(15), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 149: MemoryReadUInt { + dest: StatePartIndex(86), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.data", ty: Bool }, + memory: StatePartIndex(1), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x0, + // [0x2]: 0x0, + // [0x3]: 0x0, + // [0x4]: 0x0, + // [0x5]: 0x0, + // [0x6]: 0x0, + // [0x7]: 0x0, + // [0x8]: 0x0, + // [0x9]: 0x0, + // [0xa]: 0x0, + // [0xb]: 0x0, + // [0xc]: 0x0, + // [0xd]: 0x0, + // [0xe]: 0x0, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(16), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 150: Branch { + target: 152, + }, + 151: Const { + dest: StatePartIndex(86), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.data", ty: Bool }, + value: 0x0, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 152: Copy { + dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].data", ty: Bool }, + src: StatePartIndex(86), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.data", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 153: IsNonZeroDestIsSmall { + dest: StatePartIndex(14), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(85), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.clk", ty: Clock }, + }, + 154: AndSmall { + dest: StatePartIndex(13), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(14), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 155: CastBigToArrayIndex { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(76), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.addr", ty: UInt<4> }, + }, + 156: IsNonZeroDestIsSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(77), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.en", ty: Bool }, + }, + 157: IsNonZeroDestIsSmall { + dest: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(78), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.clk", ty: Clock }, + }, + 158: AndSmall { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 159: CastBigToArrayIndex { + dest: StatePartIndex(4), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(72), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.addr", ty: UInt<4> }, + }, + 160: IsNonZeroDestIsSmall { + dest: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(73), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.en", ty: Bool }, + }, + 161: BranchIfSmallZero { + target: 164, + value: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 162: MemoryReadUInt { + dest: StatePartIndex(75), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.data", ty: Bool }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x0, + // [0x2]: 0x0, + // [0x3]: 0x0, + // [0x4]: 0x0, + // [0x5]: 0x0, + // [0x6]: 0x0, + // [0x7]: 0x0, + // [0x8]: 0x0, + // [0x9]: 0x0, + // [0xa]: 0x0, + // [0xb]: 0x0, + // [0xc]: 0x0, + // [0xd]: 0x0, + // [0xe]: 0x0, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(4), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 163: Branch { + target: 165, + }, + 164: Const { + dest: StatePartIndex(75), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.data", ty: Bool }, + value: 0x0, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 165: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].data", ty: Bool }, + src: StatePartIndex(75), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.data", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 166: IsNonZeroDestIsSmall { + dest: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(74), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.clk", ty: Clock }, + }, + 167: AndSmall { + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 168: BranchIfSmallZero { + target: 169, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 169: BranchIfSmallZero { + target: 177, + value: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 170: CopySmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 171: CopySmall { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 172: Copy { + dest: StatePartIndex(81), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(79), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.data", ty: Bool }, + }, + 173: Copy { + dest: StatePartIndex(82), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(80), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.mask", ty: Bool }, + }, + 174: BranchIfSmallZero { + target: 177, + value: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 175: BranchIfZero { + target: 177, + value: StatePartIndex(82), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 176: MemoryWriteUInt { + value: StatePartIndex(81), // (0x0) SlotDebugData { name: "", ty: Bool }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x0, + // [0x2]: 0x0, + // [0x3]: 0x0, + // [0x4]: 0x0, + // [0x5]: 0x0, + // [0x6]: 0x0, + // [0x7]: 0x0, + // [0x8]: 0x0, + // [0x9]: 0x0, + // [0xa]: 0x0, + // [0xb]: 0x0, + // [0xc]: 0x0, + // [0xd]: 0x0, + // [0xe]: 0x0, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 177: BranchIfSmallZero { + target: 178, + value: StatePartIndex(13), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 178: BranchIfSmallZero { + target: 186, + value: StatePartIndex(18), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 179: CopySmall { + dest: StatePartIndex(22), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(21), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 180: CopySmall { + dest: StatePartIndex(23), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(20), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 181: Copy { + dest: StatePartIndex(92), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(90), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.data", ty: Bool }, + }, + 182: Copy { + dest: StatePartIndex(93), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(91), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.mask", ty: Bool }, + }, + 183: BranchIfSmallZero { + target: 186, + value: StatePartIndex(23), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 184: BranchIfZero { + target: 186, + value: StatePartIndex(93), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 185: MemoryWriteUInt { + value: StatePartIndex(92), // (0x0) SlotDebugData { name: "", ty: Bool }, + memory: StatePartIndex(1), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x0, + // [0x2]: 0x0, + // [0x3]: 0x0, + // [0x4]: 0x0, + // [0x5]: 0x0, + // [0x6]: 0x0, + // [0x7]: 0x0, + // [0x8]: 0x0, + // [0x9]: 0x0, + // [0xa]: 0x0, + // [0xb]: 0x0, + // [0xc]: 0x0, + // [0xd]: 0x0, + // [0xe]: 0x0, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(22), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 186: BranchIfSmallZero { + target: 187, + value: StatePartIndex(25), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 187: BranchIfSmallZero { + target: 195, + value: StatePartIndex(30), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 188: CopySmall { + dest: StatePartIndex(34), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(33), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 189: CopySmall { + dest: StatePartIndex(35), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(32), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 190: Copy { + dest: StatePartIndex(103), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(101), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.data", ty: Bool }, + }, + 191: Copy { + dest: StatePartIndex(104), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(102), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.mask", ty: Bool }, + }, + 192: BranchIfSmallZero { + target: 195, + value: StatePartIndex(35), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 193: BranchIfZero { + target: 195, + value: StatePartIndex(104), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 194: MemoryWriteUInt { + value: StatePartIndex(103), // (0x0) SlotDebugData { name: "", ty: Bool }, + memory: StatePartIndex(2), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x0, + // [0x2]: 0x0, + // [0x3]: 0x0, + // [0x4]: 0x0, + // [0x5]: 0x1, + // [0x6]: 0x0, + // [0x7]: 0x0, + // [0x8]: 0x0, + // [0x9]: 0x0, + // [0xa]: 0x0, + // [0xb]: 0x0, + // [0xc]: 0x0, + // [0xd]: 0x0, + // [0xe]: 0x0, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(34), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 195: BranchIfSmallZero { + target: 196, + value: StatePartIndex(37), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 196: BranchIfSmallZero { + target: 204, + value: StatePartIndex(42), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 197: CopySmall { + dest: StatePartIndex(46), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(45), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 198: CopySmall { + dest: StatePartIndex(47), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(44), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 199: Copy { + dest: StatePartIndex(114), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(112), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.data", ty: Bool }, + }, + 200: Copy { + dest: StatePartIndex(115), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(113), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.mask", ty: Bool }, + }, + 201: BranchIfSmallZero { + target: 204, + value: StatePartIndex(47), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 202: BranchIfZero { + target: 204, + value: StatePartIndex(115), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 203: MemoryWriteUInt { + value: StatePartIndex(114), // (0x0) SlotDebugData { name: "", ty: Bool }, + memory: StatePartIndex(3), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x1, + // [0x2]: 0x0, + // [0x3]: 0x0, + // [0x4]: 0x1, + // [0x5]: 0x1, + // [0x6]: 0x1, + // [0x7]: 0x1, + // [0x8]: 0x0, + // [0x9]: 0x0, + // [0xa]: 0x0, + // [0xb]: 0x0, + // [0xc]: 0x0, + // [0xd]: 0x0, + // [0xe]: 0x0, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(46), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 204: BranchIfSmallZero { + target: 205, + value: StatePartIndex(49), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 205: BranchIfSmallZero { + target: 213, + value: StatePartIndex(54), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 206: CopySmall { + dest: StatePartIndex(58), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(57), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 207: CopySmall { + dest: StatePartIndex(59), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(56), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 208: Copy { + dest: StatePartIndex(125), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(123), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.data", ty: Bool }, + }, + 209: Copy { + dest: StatePartIndex(126), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(124), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.mask", ty: Bool }, + }, + 210: BranchIfSmallZero { + target: 213, + value: StatePartIndex(59), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 211: BranchIfZero { + target: 213, + value: StatePartIndex(126), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 212: MemoryWriteUInt { + value: StatePartIndex(125), // (0x0) SlotDebugData { name: "", ty: Bool }, + memory: StatePartIndex(4), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x0, + // [0x2]: 0x0, + // [0x3]: 0x0, + // [0x4]: 0x0, + // [0x5]: 0x0, + // [0x6]: 0x0, + // [0x7]: 0x0, + // [0x8]: 0x0, + // [0x9]: 0x0, + // [0xa]: 0x1, + // [0xb]: 0x0, + // [0xc]: 0x0, + // [0xd]: 0x0, + // [0xe]: 0x0, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(58), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 213: BranchIfSmallZero { + target: 214, + value: StatePartIndex(61), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 214: BranchIfSmallZero { + target: 222, + value: StatePartIndex(66), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 215: CopySmall { + dest: StatePartIndex(70), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(69), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 216: CopySmall { + dest: StatePartIndex(71), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(68), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 217: Copy { + dest: StatePartIndex(136), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(134), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.data", ty: Bool }, + }, + 218: Copy { + dest: StatePartIndex(137), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(135), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.mask", ty: Bool }, + }, + 219: BranchIfSmallZero { + target: 222, + value: StatePartIndex(71), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 220: BranchIfZero { + target: 222, + value: StatePartIndex(137), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 221: MemoryWriteUInt { + value: StatePartIndex(136), // (0x0) SlotDebugData { name: "", ty: Bool }, + memory: StatePartIndex(5), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x0, + // [0x2]: 0x1, + // [0x3]: 0x0, + // [0x4]: 0x1, + // [0x5]: 0x1, + // [0x6]: 0x0, + // [0x7]: 0x0, + // [0x8]: 0x0, + // [0x9]: 0x0, + // [0xa]: 0x1, + // [0xb]: 0x1, + // [0xc]: 0x0, + // [0xd]: 0x0, + // [0xe]: 0x0, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(70), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 222: BranchIfSmallZero { + target: 223, + value: StatePartIndex(73), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 223: BranchIfSmallZero { + target: 231, + value: StatePartIndex(78), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 224: CopySmall { + dest: StatePartIndex(82), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(81), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 225: CopySmall { + dest: StatePartIndex(83), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(80), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 226: Copy { + dest: StatePartIndex(147), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(145), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.data", ty: Bool }, + }, + 227: Copy { + dest: StatePartIndex(148), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(146), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.mask", ty: Bool }, + }, + 228: BranchIfSmallZero { + target: 231, + value: StatePartIndex(83), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 229: BranchIfZero { + target: 231, + value: StatePartIndex(148), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 230: MemoryWriteUInt { + value: StatePartIndex(147), // (0x0) SlotDebugData { name: "", ty: Bool }, + memory: StatePartIndex(6), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x0, + // [0x2]: 0x0, + // [0x3]: 0x0, + // [0x4]: 0x0, + // [0x5]: 0x1, + // [0x6]: 0x1, + // [0x7]: 0x0, + // [0x8]: 0x0, + // [0x9]: 0x1, + // [0xa]: 0x1, + // [0xb]: 0x1, + // [0xc]: 0x1, + // [0xd]: 0x0, + // [0xe]: 0x0, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(82), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 231: BranchIfSmallZero { + target: 232, + value: StatePartIndex(85), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 232: BranchIfSmallZero { + target: 240, + value: StatePartIndex(90), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 233: CopySmall { + dest: StatePartIndex(94), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(93), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + }, + 234: CopySmall { + dest: StatePartIndex(95), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(92), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 235: Copy { + dest: StatePartIndex(158), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(156), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.data", ty: Bool }, + }, + 236: Copy { + dest: StatePartIndex(159), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(157), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.mask", ty: Bool }, + }, + 237: BranchIfSmallZero { + target: 240, + value: StatePartIndex(95), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 238: BranchIfZero { + target: 240, + value: StatePartIndex(159), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 239: MemoryWriteUInt { + value: StatePartIndex(158), // (0x0) SlotDebugData { name: "", ty: Bool }, + memory: StatePartIndex(7), // (MemoryData { + // array_type: Array, + // data: [ + // // len = 0x10 + // [0x0]: 0x0, + // [0x1]: 0x1, + // [0x2]: 0x1, + // [0x3]: 0x0, + // [0x4]: 0x0, + // [0x5]: 0x1, + // [0x6]: 0x0, + // [0x7]: 0x1, + // [0x8]: 0x1, + // [0x9]: 0x0, + // [0xa]: 0x0, + // [0xb]: 0x0, + // [0xc]: 0x0, + // [0xd]: 0x0, + // [0xe]: 0x1, + // [0xf]: 0x0, + // ], + // }) (), + addr: StatePartIndex(94), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, + stride: 1, + start: 0, + width: 1, + }, + 240: XorSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 241: XorSmallImmediate { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 242: XorSmallImmediate { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(14), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 243: XorSmallImmediate { + dest: StatePartIndex(17), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(19), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 244: XorSmallImmediate { + dest: StatePartIndex(24), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(26), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 245: XorSmallImmediate { + dest: StatePartIndex(29), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(31), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 246: XorSmallImmediate { + dest: StatePartIndex(36), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(38), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 247: XorSmallImmediate { + dest: StatePartIndex(41), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(43), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 248: XorSmallImmediate { + dest: StatePartIndex(48), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(50), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 249: XorSmallImmediate { + dest: StatePartIndex(53), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(55), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 250: XorSmallImmediate { + dest: StatePartIndex(60), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(62), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 251: XorSmallImmediate { + dest: StatePartIndex(65), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(67), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 252: XorSmallImmediate { + dest: StatePartIndex(72), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(74), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 253: XorSmallImmediate { + dest: StatePartIndex(77), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(79), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 254: XorSmallImmediate { + dest: StatePartIndex(84), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(86), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 255: XorSmallImmediate { + dest: StatePartIndex(89), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(91), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 256: Return, + ], + .. + }, + pc: 256, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x0, + [0x1]: 0x0, + [0x2]: 0x0, + [0x3]: 0x0, + [0x4]: 0x0, + [0x5]: 0x0, + [0x6]: 0x0, + [0x7]: 0x0, + [0x8]: 0x0, + [0x9]: 0x0, + [0xa]: 0x0, + [0xb]: 0x0, + [0xc]: 0x0, + [0xd]: 0x0, + [0xe]: 0x0, + [0xf]: 0x0, + ], + }, + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x0, + [0x1]: 0x0, + [0x2]: 0x0, + [0x3]: 0x0, + [0x4]: 0x0, + [0x5]: 0x0, + [0x6]: 0x0, + [0x7]: 0x0, + [0x8]: 0x0, + [0x9]: 0x0, + [0xa]: 0x0, + [0xb]: 0x0, + [0xc]: 0x0, + [0xd]: 0x0, + [0xe]: 0x0, + [0xf]: 0x0, + ], + }, + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x0, + [0x1]: 0x0, + [0x2]: 0x0, + [0x3]: 0x0, + [0x4]: 0x0, + [0x5]: 0x1, + [0x6]: 0x0, + [0x7]: 0x0, + [0x8]: 0x0, + [0x9]: 0x0, + [0xa]: 0x0, + [0xb]: 0x0, + [0xc]: 0x0, + [0xd]: 0x0, + [0xe]: 0x0, + [0xf]: 0x0, + ], + }, + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x0, + [0x1]: 0x1, + [0x2]: 0x0, + [0x3]: 0x0, + [0x4]: 0x1, + [0x5]: 0x1, + [0x6]: 0x1, + [0x7]: 0x1, + [0x8]: 0x0, + [0x9]: 0x0, + [0xa]: 0x0, + [0xb]: 0x0, + [0xc]: 0x0, + [0xd]: 0x0, + [0xe]: 0x0, + [0xf]: 0x0, + ], + }, + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x0, + [0x1]: 0x0, + [0x2]: 0x0, + [0x3]: 0x0, + [0x4]: 0x0, + [0x5]: 0x0, + [0x6]: 0x0, + [0x7]: 0x0, + [0x8]: 0x0, + [0x9]: 0x0, + [0xa]: 0x1, + [0xb]: 0x0, + [0xc]: 0x0, + [0xd]: 0x0, + [0xe]: 0x0, + [0xf]: 0x0, + ], + }, + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x0, + [0x1]: 0x0, + [0x2]: 0x1, + [0x3]: 0x0, + [0x4]: 0x1, + [0x5]: 0x1, + [0x6]: 0x0, + [0x7]: 0x0, + [0x8]: 0x0, + [0x9]: 0x0, + [0xa]: 0x1, + [0xb]: 0x1, + [0xc]: 0x0, + [0xd]: 0x0, + [0xe]: 0x0, + [0xf]: 0x0, + ], + }, + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x0, + [0x1]: 0x0, + [0x2]: 0x0, + [0x3]: 0x0, + [0x4]: 0x0, + [0x5]: 0x1, + [0x6]: 0x1, + [0x7]: 0x0, + [0x8]: 0x0, + [0x9]: 0x1, + [0xa]: 0x1, + [0xb]: 0x1, + [0xc]: 0x1, + [0xd]: 0x0, + [0xe]: 0x0, + [0xf]: 0x0, + ], + }, + MemoryData { + array_type: Array, + data: [ + // len = 0x10 + [0x0]: 0x0, + [0x1]: 0x1, + [0x2]: 0x1, + [0x3]: 0x0, + [0x4]: 0x0, + [0x5]: 0x1, + [0x6]: 0x0, + [0x7]: 0x1, + [0x8]: 0x1, + [0x9]: 0x0, + [0xa]: 0x0, + [0xb]: 0x0, + [0xc]: 0x0, + [0xd]: 0x0, + [0xe]: 0x1, + [0xf]: 0x0, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 0, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 15, + 1, + 0, + 0, + 15, + 1, + 0, + 0, + 15, + 1, + 0, + 0, + 15, + 1, + 0, + 0, + 15, + 1, + 0, + 0, + 15, + 1, + 0, + 0, + 15, + 1, + 0, + 0, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 15, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[0], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[0].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[0].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[0].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[0].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[1], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[1].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[1].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[1].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[1].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[2], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[2].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[2].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[2].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[2].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[3], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[3].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[3].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[3].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[3].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[4], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[4].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[4].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[4].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[4].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[5], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[5].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[5].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[5].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[5].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[6], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[6].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[6].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[6].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[6].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[7], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[7].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[7].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[7].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.r[7].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[0], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[0].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[0].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[0].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[0].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[0].mask, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[1], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[1].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[1].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[1].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[1].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[1].mask, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[2], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[2].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[2].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[2].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[2].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[2].mask, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[3], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[3].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[3].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[3].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[3].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[3].mask, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[4], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[4].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[4].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[4].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[4].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[4].mask, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[5], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[5].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[5].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[5].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[5].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[5].mask, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[6], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[6].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[6].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[6].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[6].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[6].mask, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[7], + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[7].addr, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[7].clk, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[7].data, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[7].en, + Instance { + name: ::many_memories, + instantiated: Module { + name: many_memories, + .. + }, + }.w[7].mask, + }, + did_initial_settle: true, + }, + extern_modules: [], + state_ready_to_run: false, + trace_decls: TraceModule { + name: "many_memories", + children: [ + TraceModuleIO { + name: "r", + child: TraceArray { + name: "r", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(0), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(2), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(3), + name: "data", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(4), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(5), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(6), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(7), + name: "data", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "[2]", + fields: [ + TraceUInt { + location: TraceScalarId(8), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(9), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(10), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(11), + name: "data", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "[3]", + fields: [ + TraceUInt { + location: TraceScalarId(12), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(13), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(14), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(15), + name: "data", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "[4]", + fields: [ + TraceUInt { + location: TraceScalarId(16), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(17), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(18), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(19), + name: "data", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "[5]", + fields: [ + TraceUInt { + location: TraceScalarId(20), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(21), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(22), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(23), + name: "data", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "[6]", + fields: [ + TraceUInt { + location: TraceScalarId(24), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(25), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(26), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(27), + name: "data", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "[7]", + fields: [ + TraceUInt { + location: TraceScalarId(28), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(29), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(30), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(31), + name: "data", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Source, + }, + ], + ty: Array, en: Bool, clk: Clock, #[hdl(flip)] data: Bool}, 8>, + flow: Source, + }, + ty: Array, en: Bool, clk: Clock, #[hdl(flip)] data: Bool}, 8>, + flow: Source, + }, + TraceModuleIO { + name: "w", + child: TraceArray { + name: "w", + elements: [ + TraceBundle { + name: "[0]", + fields: [ + TraceUInt { + location: TraceScalarId(32), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(33), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(34), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(35), + name: "data", + flow: Source, + }, + TraceBool { + location: TraceScalarId(36), + name: "mask", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "[1]", + fields: [ + TraceUInt { + location: TraceScalarId(37), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(38), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(39), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(40), + name: "data", + flow: Source, + }, + TraceBool { + location: TraceScalarId(41), + name: "mask", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "[2]", + fields: [ + TraceUInt { + location: TraceScalarId(42), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(43), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(44), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(45), + name: "data", + flow: Source, + }, + TraceBool { + location: TraceScalarId(46), + name: "mask", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "[3]", + fields: [ + TraceUInt { + location: TraceScalarId(47), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(48), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(49), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(50), + name: "data", + flow: Source, + }, + TraceBool { + location: TraceScalarId(51), + name: "mask", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "[4]", + fields: [ + TraceUInt { + location: TraceScalarId(52), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(53), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(54), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(55), + name: "data", + flow: Source, + }, + TraceBool { + location: TraceScalarId(56), + name: "mask", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "[5]", + fields: [ + TraceUInt { + location: TraceScalarId(57), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(58), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(59), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(60), + name: "data", + flow: Source, + }, + TraceBool { + location: TraceScalarId(61), + name: "mask", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "[6]", + fields: [ + TraceUInt { + location: TraceScalarId(62), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(63), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(64), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(65), + name: "data", + flow: Source, + }, + TraceBool { + location: TraceScalarId(66), + name: "mask", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Source, + }, + TraceBundle { + name: "[7]", + fields: [ + TraceUInt { + location: TraceScalarId(67), + name: "addr", + ty: UInt<4>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(68), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(69), + name: "clk", + flow: Source, + }, + TraceBool { + location: TraceScalarId(70), + name: "data", + flow: Source, + }, + TraceBool { + location: TraceScalarId(71), + name: "mask", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Source, + }, + ], + ty: Array, en: Bool, clk: Clock, data: Bool, mask: Bool}, 8>, + flow: Source, + }, + ty: Array, en: Bool, clk: Clock, data: Bool, mask: Bool}, 8>, + flow: Source, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem_0", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_0", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(72), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(73), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(74), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(75), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(76), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(77), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(78), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(79), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(80), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + TraceMem { + id: TraceMemoryId(1), + name: "mem_1", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(1), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_1", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(81), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(82), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(83), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(84), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(85), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(86), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(87), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(88), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(89), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + TraceMem { + id: TraceMemoryId(2), + name: "mem_2", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(2), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_2", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(90), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(91), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(92), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(93), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(94), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(95), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(96), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(97), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(98), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + TraceMem { + id: TraceMemoryId(3), + name: "mem_3", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(3), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_3", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(99), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(100), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(101), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(102), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(103), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(104), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(105), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(106), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(107), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + TraceMem { + id: TraceMemoryId(4), + name: "mem_4", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(4), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_4", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(108), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(109), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(110), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(111), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(112), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(113), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(114), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(115), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(116), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + TraceMem { + id: TraceMemoryId(5), + name: "mem_5", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(5), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_5", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(117), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(118), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(119), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(120), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(121), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(122), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(123), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(124), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(125), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + TraceMem { + id: TraceMemoryId(6), + name: "mem_6", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(6), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_6", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(126), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(127), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(128), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(129), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(130), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(131), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(132), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(133), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(134), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + TraceMem { + id: TraceMemoryId(7), + name: "mem_7", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(7), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_7", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(135), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(136), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(137), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(138), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(139), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(140), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(141), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(142), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(143), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigUInt { + index: StatePartIndex(0), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigBool { + index: StatePartIndex(1), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigClock { + index: StatePartIndex(2), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigUInt { + index: StatePartIndex(4), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(5), + kind: BigBool { + index: StatePartIndex(5), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigClock { + index: StatePartIndex(6), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(8), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigBool { + index: StatePartIndex(9), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigClock { + index: StatePartIndex(10), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigBool { + index: StatePartIndex(11), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(12), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigBool { + index: StatePartIndex(13), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigClock { + index: StatePartIndex(14), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigBool { + index: StatePartIndex(15), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(16), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(17), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigClock { + index: StatePartIndex(18), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigUInt { + index: StatePartIndex(20), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(21), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigClock { + index: StatePartIndex(22), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(23), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigUInt { + index: StatePartIndex(24), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(25), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigClock { + index: StatePartIndex(26), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(28), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigBool { + index: StatePartIndex(29), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(30), + kind: BigClock { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(31), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(32), + kind: BigUInt { + index: StatePartIndex(32), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(33), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(34), + kind: BigClock { + index: StatePartIndex(34), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(35), + kind: BigBool { + index: StatePartIndex(35), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(36), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(37), + kind: BigUInt { + index: StatePartIndex(37), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(38), + kind: BigBool { + index: StatePartIndex(38), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(39), + kind: BigClock { + index: StatePartIndex(39), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(40), + kind: BigBool { + index: StatePartIndex(40), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(41), + kind: BigBool { + index: StatePartIndex(41), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(42), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(43), + kind: BigBool { + index: StatePartIndex(43), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(44), + kind: BigClock { + index: StatePartIndex(44), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(45), + kind: BigBool { + index: StatePartIndex(45), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(46), + kind: BigBool { + index: StatePartIndex(46), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(47), + kind: BigUInt { + index: StatePartIndex(47), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(48), + kind: BigBool { + index: StatePartIndex(48), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(49), + kind: BigClock { + index: StatePartIndex(49), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(50), + kind: BigBool { + index: StatePartIndex(50), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(51), + kind: BigBool { + index: StatePartIndex(51), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(52), + kind: BigUInt { + index: StatePartIndex(52), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(53), + kind: BigBool { + index: StatePartIndex(53), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(54), + kind: BigClock { + index: StatePartIndex(54), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(55), + kind: BigBool { + index: StatePartIndex(55), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(56), + kind: BigBool { + index: StatePartIndex(56), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(57), + kind: BigUInt { + index: StatePartIndex(57), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(58), + kind: BigBool { + index: StatePartIndex(58), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(59), + kind: BigClock { + index: StatePartIndex(59), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(60), + kind: BigBool { + index: StatePartIndex(60), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(61), + kind: BigBool { + index: StatePartIndex(61), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(62), + kind: BigUInt { + index: StatePartIndex(62), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(63), + kind: BigBool { + index: StatePartIndex(63), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(64), + kind: BigClock { + index: StatePartIndex(64), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(65), + kind: BigBool { + index: StatePartIndex(65), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(66), + kind: BigBool { + index: StatePartIndex(66), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(67), + kind: BigUInt { + index: StatePartIndex(67), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(68), + kind: BigBool { + index: StatePartIndex(68), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(69), + kind: BigClock { + index: StatePartIndex(69), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(70), + kind: BigBool { + index: StatePartIndex(70), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(71), + kind: BigBool { + index: StatePartIndex(71), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(72), + kind: BigUInt { + index: StatePartIndex(72), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(73), + kind: BigBool { + index: StatePartIndex(73), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(74), + kind: BigClock { + index: StatePartIndex(74), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(75), + kind: BigBool { + index: StatePartIndex(75), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(76), + kind: BigUInt { + index: StatePartIndex(76), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(77), + kind: BigBool { + index: StatePartIndex(77), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(78), + kind: BigClock { + index: StatePartIndex(78), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(79), + kind: BigBool { + index: StatePartIndex(79), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(80), + kind: BigBool { + index: StatePartIndex(80), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(81), + kind: BigUInt { + index: StatePartIndex(83), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(82), + kind: BigBool { + index: StatePartIndex(84), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(83), + kind: BigClock { + index: StatePartIndex(85), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(84), + kind: BigBool { + index: StatePartIndex(86), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(85), + kind: BigUInt { + index: StatePartIndex(87), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(86), + kind: BigBool { + index: StatePartIndex(88), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(87), + kind: BigClock { + index: StatePartIndex(89), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(88), + kind: BigBool { + index: StatePartIndex(90), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(89), + kind: BigBool { + index: StatePartIndex(91), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(90), + kind: BigUInt { + index: StatePartIndex(94), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(91), + kind: BigBool { + index: StatePartIndex(95), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(92), + kind: BigClock { + index: StatePartIndex(96), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(93), + kind: BigBool { + index: StatePartIndex(97), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(94), + kind: BigUInt { + index: StatePartIndex(98), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(95), + kind: BigBool { + index: StatePartIndex(99), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(96), + kind: BigClock { + index: StatePartIndex(100), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(97), + kind: BigBool { + index: StatePartIndex(101), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(98), + kind: BigBool { + index: StatePartIndex(102), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(99), + kind: BigUInt { + index: StatePartIndex(105), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(100), + kind: BigBool { + index: StatePartIndex(106), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(101), + kind: BigClock { + index: StatePartIndex(107), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(102), + kind: BigBool { + index: StatePartIndex(108), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(103), + kind: BigUInt { + index: StatePartIndex(109), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(104), + kind: BigBool { + index: StatePartIndex(110), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(105), + kind: BigClock { + index: StatePartIndex(111), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(106), + kind: BigBool { + index: StatePartIndex(112), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(107), + kind: BigBool { + index: StatePartIndex(113), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(108), + kind: BigUInt { + index: StatePartIndex(116), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(109), + kind: BigBool { + index: StatePartIndex(117), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(110), + kind: BigClock { + index: StatePartIndex(118), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(111), + kind: BigBool { + index: StatePartIndex(119), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(112), + kind: BigUInt { + index: StatePartIndex(120), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(113), + kind: BigBool { + index: StatePartIndex(121), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(114), + kind: BigClock { + index: StatePartIndex(122), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(115), + kind: BigBool { + index: StatePartIndex(123), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(116), + kind: BigBool { + index: StatePartIndex(124), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(117), + kind: BigUInt { + index: StatePartIndex(127), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(118), + kind: BigBool { + index: StatePartIndex(128), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(119), + kind: BigClock { + index: StatePartIndex(129), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(120), + kind: BigBool { + index: StatePartIndex(130), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(121), + kind: BigUInt { + index: StatePartIndex(131), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(122), + kind: BigBool { + index: StatePartIndex(132), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(123), + kind: BigClock { + index: StatePartIndex(133), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(124), + kind: BigBool { + index: StatePartIndex(134), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(125), + kind: BigBool { + index: StatePartIndex(135), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(126), + kind: BigUInt { + index: StatePartIndex(138), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(127), + kind: BigBool { + index: StatePartIndex(139), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(128), + kind: BigClock { + index: StatePartIndex(140), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(129), + kind: BigBool { + index: StatePartIndex(141), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(130), + kind: BigUInt { + index: StatePartIndex(142), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(131), + kind: BigBool { + index: StatePartIndex(143), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(132), + kind: BigClock { + index: StatePartIndex(144), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(133), + kind: BigBool { + index: StatePartIndex(145), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(134), + kind: BigBool { + index: StatePartIndex(146), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(135), + kind: BigUInt { + index: StatePartIndex(149), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xf, + }, + SimTrace { + id: TraceScalarId(136), + kind: BigBool { + index: StatePartIndex(150), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(137), + kind: BigClock { + index: StatePartIndex(151), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(138), + kind: BigBool { + index: StatePartIndex(152), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(139), + kind: BigUInt { + index: StatePartIndex(153), + ty: UInt<4>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(140), + kind: BigBool { + index: StatePartIndex(154), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(141), + kind: BigClock { + index: StatePartIndex(155), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(142), + kind: BigBool { + index: StatePartIndex(156), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(143), + kind: BigBool { + index: StatePartIndex(157), + }, + state: 0x1, + last_state: 0x1, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem_0", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_0", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(72), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(73), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(74), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(75), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(76), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(77), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(78), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(79), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(80), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + StatePartIndex(1): TraceMem { + id: TraceMemoryId(1), + name: "mem_1", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(1), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_1", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(81), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(82), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(83), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(84), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(85), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(86), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(87), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(88), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(89), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + StatePartIndex(2): TraceMem { + id: TraceMemoryId(2), + name: "mem_2", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(2), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_2", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(90), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(91), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(92), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(93), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(94), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(95), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(96), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(97), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(98), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + StatePartIndex(3): TraceMem { + id: TraceMemoryId(3), + name: "mem_3", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(3), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_3", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(99), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(100), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(101), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(102), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(103), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(104), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(105), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(106), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(107), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + StatePartIndex(4): TraceMem { + id: TraceMemoryId(4), + name: "mem_4", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(4), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_4", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(108), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(109), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(110), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(111), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(112), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(113), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(114), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(115), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(116), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + StatePartIndex(5): TraceMem { + id: TraceMemoryId(5), + name: "mem_5", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(5), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_5", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(117), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(118), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(119), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(120), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(121), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(122), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(123), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(124), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(125), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + StatePartIndex(6): TraceMem { + id: TraceMemoryId(6), + name: "mem_6", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(6), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_6", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(126), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(127), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(128), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(129), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(130), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(131), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(132), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(133), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(134), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + StatePartIndex(7): TraceMem { + id: TraceMemoryId(7), + name: "mem_7", + stride: 1, + element_type: TraceBool { + location: TraceMemoryLocation { + id: TraceMemoryId(7), + depth: 16, + stride: 1, + start: 0, + len: 1, + }, + name: "mem_7", + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(135), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(136), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(137), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(138), + name: "data", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + #[hdl(flip)] /* offset = 6 */ + data: Bool, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(139), + name: "addr", + ty: UInt<4>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(140), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(141), + name: "clk", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(142), + name: "data", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(143), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<4>, + /* offset = 4 */ + en: Bool, + /* offset = 5 */ + clk: Clock, + /* offset = 6 */ + data: Bool, + /* offset = 7 */ + mask: Bool, + }, + }, + ], + array_type: Array, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + instant: 38 μs, + clocks_triggered: [ + StatePartIndex(1), + StatePartIndex(6), + StatePartIndex(13), + StatePartIndex(18), + StatePartIndex(25), + StatePartIndex(30), + StatePartIndex(37), + StatePartIndex(42), + StatePartIndex(49), + StatePartIndex(54), + StatePartIndex(61), + StatePartIndex(66), + StatePartIndex(73), + StatePartIndex(78), + StatePartIndex(85), + StatePartIndex(90), + ], + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/many_memories.vcd b/crates/fayalite/tests/sim/expected/many_memories.vcd new file mode 100644 index 0000000..cbaeb7b --- /dev/null +++ b/crates/fayalite/tests/sim/expected/many_memories.vcd @@ -0,0 +1,2596 @@ +$timescale 1 ps $end +$scope module many_memories $end +$scope struct r $end +$scope struct \[0] $end +$var wire 4 ! addr $end +$var wire 1 " en $end +$var wire 1 # clk $end +$var wire 1 $ data $end +$upscope $end +$scope struct \[1] $end +$var wire 4 % addr $end +$var wire 1 & en $end +$var wire 1 ' clk $end +$var wire 1 ( data $end +$upscope $end +$scope struct \[2] $end +$var wire 4 ) addr $end +$var wire 1 * en $end +$var wire 1 + clk $end +$var wire 1 , data $end +$upscope $end +$scope struct \[3] $end +$var wire 4 - addr $end +$var wire 1 . en $end +$var wire 1 / clk $end +$var wire 1 0 data $end +$upscope $end +$scope struct \[4] $end +$var wire 4 1 addr $end +$var wire 1 2 en $end +$var wire 1 3 clk $end +$var wire 1 4 data $end +$upscope $end +$scope struct \[5] $end +$var wire 4 5 addr $end +$var wire 1 6 en $end +$var wire 1 7 clk $end +$var wire 1 8 data $end +$upscope $end +$scope struct \[6] $end +$var wire 4 9 addr $end +$var wire 1 : en $end +$var wire 1 ; clk $end +$var wire 1 < data $end +$upscope $end +$scope struct \[7] $end +$var wire 4 = addr $end +$var wire 1 > en $end +$var wire 1 ? clk $end +$var wire 1 @ data $end +$upscope $end +$upscope $end +$scope struct w $end +$scope struct \[0] $end +$var wire 4 A addr $end +$var wire 1 B en $end +$var wire 1 C clk $end +$var wire 1 D data $end +$var wire 1 E mask $end +$upscope $end +$scope struct \[1] $end +$var wire 4 F addr $end +$var wire 1 G en $end +$var wire 1 H clk $end +$var wire 1 I data $end +$var wire 1 J mask $end +$upscope $end +$scope struct \[2] $end +$var wire 4 K addr $end +$var wire 1 L en $end +$var wire 1 M clk $end +$var wire 1 N data $end +$var wire 1 O mask $end +$upscope $end +$scope struct \[3] $end +$var wire 4 P addr $end +$var wire 1 Q en $end +$var wire 1 R clk $end +$var wire 1 S data $end +$var wire 1 T mask $end +$upscope $end +$scope struct \[4] $end +$var wire 4 U addr $end +$var wire 1 V en $end +$var wire 1 W clk $end +$var wire 1 X data $end +$var wire 1 Y mask $end +$upscope $end +$scope struct \[5] $end +$var wire 4 Z addr $end +$var wire 1 [ en $end +$var wire 1 \ clk $end +$var wire 1 ] data $end +$var wire 1 ^ mask $end +$upscope $end +$scope struct \[6] $end +$var wire 4 _ addr $end +$var wire 1 ` en $end +$var wire 1 a clk $end +$var wire 1 b data $end +$var wire 1 c mask $end +$upscope $end +$scope struct \[7] $end +$var wire 4 d addr $end +$var wire 1 e en $end +$var wire 1 f clk $end +$var wire 1 g data $end +$var wire 1 h mask $end +$upscope $end +$upscope $end +$scope struct mem_0 $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 1 S" mem_0 $end +$upscope $end +$scope struct \[1] $end +$var reg 1 T" mem_0 $end +$upscope $end +$scope struct \[2] $end +$var reg 1 U" mem_0 $end +$upscope $end +$scope struct \[3] $end +$var reg 1 V" mem_0 $end +$upscope $end +$scope struct \[4] $end +$var reg 1 W" mem_0 $end +$upscope $end +$scope struct \[5] $end +$var reg 1 X" mem_0 $end +$upscope $end +$scope struct \[6] $end +$var reg 1 Y" mem_0 $end +$upscope $end +$scope struct \[7] $end +$var reg 1 Z" mem_0 $end +$upscope $end +$scope struct \[8] $end +$var reg 1 [" mem_0 $end +$upscope $end +$scope struct \[9] $end +$var reg 1 \" mem_0 $end +$upscope $end +$scope struct \[10] $end +$var reg 1 ]" mem_0 $end +$upscope $end +$scope struct \[11] $end +$var reg 1 ^" mem_0 $end +$upscope $end +$scope struct \[12] $end +$var reg 1 _" mem_0 $end +$upscope $end +$scope struct \[13] $end +$var reg 1 `" mem_0 $end +$upscope $end +$scope struct \[14] $end +$var reg 1 a" mem_0 $end +$upscope $end +$scope struct \[15] $end +$var reg 1 b" mem_0 $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 4 i addr $end +$var wire 1 j en $end +$var wire 1 k clk $end +$var wire 1 l data $end +$upscope $end +$scope struct w1 $end +$var wire 4 m addr $end +$var wire 1 n en $end +$var wire 1 o clk $end +$var wire 1 p data $end +$var wire 1 q mask $end +$upscope $end +$upscope $end +$scope struct mem_1 $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 1 c" mem_1 $end +$upscope $end +$scope struct \[1] $end +$var reg 1 d" mem_1 $end +$upscope $end +$scope struct \[2] $end +$var reg 1 e" mem_1 $end +$upscope $end +$scope struct \[3] $end +$var reg 1 f" mem_1 $end +$upscope $end +$scope struct \[4] $end +$var reg 1 g" mem_1 $end +$upscope $end +$scope struct \[5] $end +$var reg 1 h" mem_1 $end +$upscope $end +$scope struct \[6] $end +$var reg 1 i" mem_1 $end +$upscope $end +$scope struct \[7] $end +$var reg 1 j" mem_1 $end +$upscope $end +$scope struct \[8] $end +$var reg 1 k" mem_1 $end +$upscope $end +$scope struct \[9] $end +$var reg 1 l" mem_1 $end +$upscope $end +$scope struct \[10] $end +$var reg 1 m" mem_1 $end +$upscope $end +$scope struct \[11] $end +$var reg 1 n" mem_1 $end +$upscope $end +$scope struct \[12] $end +$var reg 1 o" mem_1 $end +$upscope $end +$scope struct \[13] $end +$var reg 1 p" mem_1 $end +$upscope $end +$scope struct \[14] $end +$var reg 1 q" mem_1 $end +$upscope $end +$scope struct \[15] $end +$var reg 1 r" mem_1 $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 4 r addr $end +$var wire 1 s en $end +$var wire 1 t clk $end +$var wire 1 u data $end +$upscope $end +$scope struct w1 $end +$var wire 4 v addr $end +$var wire 1 w en $end +$var wire 1 x clk $end +$var wire 1 y data $end +$var wire 1 z mask $end +$upscope $end +$upscope $end +$scope struct mem_2 $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 1 s" mem_2 $end +$upscope $end +$scope struct \[1] $end +$var reg 1 t" mem_2 $end +$upscope $end +$scope struct \[2] $end +$var reg 1 u" mem_2 $end +$upscope $end +$scope struct \[3] $end +$var reg 1 v" mem_2 $end +$upscope $end +$scope struct \[4] $end +$var reg 1 w" mem_2 $end +$upscope $end +$scope struct \[5] $end +$var reg 1 x" mem_2 $end +$upscope $end +$scope struct \[6] $end +$var reg 1 y" mem_2 $end +$upscope $end +$scope struct \[7] $end +$var reg 1 z" mem_2 $end +$upscope $end +$scope struct \[8] $end +$var reg 1 {" mem_2 $end +$upscope $end +$scope struct \[9] $end +$var reg 1 |" mem_2 $end +$upscope $end +$scope struct \[10] $end +$var reg 1 }" mem_2 $end +$upscope $end +$scope struct \[11] $end +$var reg 1 ~" mem_2 $end +$upscope $end +$scope struct \[12] $end +$var reg 1 !# mem_2 $end +$upscope $end +$scope struct \[13] $end +$var reg 1 "# mem_2 $end +$upscope $end +$scope struct \[14] $end +$var reg 1 ## mem_2 $end +$upscope $end +$scope struct \[15] $end +$var reg 1 $# mem_2 $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 4 { addr $end +$var wire 1 | en $end +$var wire 1 } clk $end +$var wire 1 ~ data $end +$upscope $end +$scope struct w1 $end +$var wire 4 !" addr $end +$var wire 1 "" en $end +$var wire 1 #" clk $end +$var wire 1 $" data $end +$var wire 1 %" mask $end +$upscope $end +$upscope $end +$scope struct mem_3 $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 1 %# mem_3 $end +$upscope $end +$scope struct \[1] $end +$var reg 1 &# mem_3 $end +$upscope $end +$scope struct \[2] $end +$var reg 1 '# mem_3 $end +$upscope $end +$scope struct \[3] $end +$var reg 1 (# mem_3 $end +$upscope $end +$scope struct \[4] $end +$var reg 1 )# mem_3 $end +$upscope $end +$scope struct \[5] $end +$var reg 1 *# mem_3 $end +$upscope $end +$scope struct \[6] $end +$var reg 1 +# mem_3 $end +$upscope $end +$scope struct \[7] $end +$var reg 1 ,# mem_3 $end +$upscope $end +$scope struct \[8] $end +$var reg 1 -# mem_3 $end +$upscope $end +$scope struct \[9] $end +$var reg 1 .# mem_3 $end +$upscope $end +$scope struct \[10] $end +$var reg 1 /# mem_3 $end +$upscope $end +$scope struct \[11] $end +$var reg 1 0# mem_3 $end +$upscope $end +$scope struct \[12] $end +$var reg 1 1# mem_3 $end +$upscope $end +$scope struct \[13] $end +$var reg 1 2# mem_3 $end +$upscope $end +$scope struct \[14] $end +$var reg 1 3# mem_3 $end +$upscope $end +$scope struct \[15] $end +$var reg 1 4# mem_3 $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 4 &" addr $end +$var wire 1 '" en $end +$var wire 1 (" clk $end +$var wire 1 )" data $end +$upscope $end +$scope struct w1 $end +$var wire 4 *" addr $end +$var wire 1 +" en $end +$var wire 1 ," clk $end +$var wire 1 -" data $end +$var wire 1 ." mask $end +$upscope $end +$upscope $end +$scope struct mem_4 $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 1 5# mem_4 $end +$upscope $end +$scope struct \[1] $end +$var reg 1 6# mem_4 $end +$upscope $end +$scope struct \[2] $end +$var reg 1 7# mem_4 $end +$upscope $end +$scope struct \[3] $end +$var reg 1 8# mem_4 $end +$upscope $end +$scope struct \[4] $end +$var reg 1 9# mem_4 $end +$upscope $end +$scope struct \[5] $end +$var reg 1 :# mem_4 $end +$upscope $end +$scope struct \[6] $end +$var reg 1 ;# mem_4 $end +$upscope $end +$scope struct \[7] $end +$var reg 1 <# mem_4 $end +$upscope $end +$scope struct \[8] $end +$var reg 1 =# mem_4 $end +$upscope $end +$scope struct \[9] $end +$var reg 1 ># mem_4 $end +$upscope $end +$scope struct \[10] $end +$var reg 1 ?# mem_4 $end +$upscope $end +$scope struct \[11] $end +$var reg 1 @# mem_4 $end +$upscope $end +$scope struct \[12] $end +$var reg 1 A# mem_4 $end +$upscope $end +$scope struct \[13] $end +$var reg 1 B# mem_4 $end +$upscope $end +$scope struct \[14] $end +$var reg 1 C# mem_4 $end +$upscope $end +$scope struct \[15] $end +$var reg 1 D# mem_4 $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 4 /" addr $end +$var wire 1 0" en $end +$var wire 1 1" clk $end +$var wire 1 2" data $end +$upscope $end +$scope struct w1 $end +$var wire 4 3" addr $end +$var wire 1 4" en $end +$var wire 1 5" clk $end +$var wire 1 6" data $end +$var wire 1 7" mask $end +$upscope $end +$upscope $end +$scope struct mem_5 $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 1 E# mem_5 $end +$upscope $end +$scope struct \[1] $end +$var reg 1 F# mem_5 $end +$upscope $end +$scope struct \[2] $end +$var reg 1 G# mem_5 $end +$upscope $end +$scope struct \[3] $end +$var reg 1 H# mem_5 $end +$upscope $end +$scope struct \[4] $end +$var reg 1 I# mem_5 $end +$upscope $end +$scope struct \[5] $end +$var reg 1 J# mem_5 $end +$upscope $end +$scope struct \[6] $end +$var reg 1 K# mem_5 $end +$upscope $end +$scope struct \[7] $end +$var reg 1 L# mem_5 $end +$upscope $end +$scope struct \[8] $end +$var reg 1 M# mem_5 $end +$upscope $end +$scope struct \[9] $end +$var reg 1 N# mem_5 $end +$upscope $end +$scope struct \[10] $end +$var reg 1 O# mem_5 $end +$upscope $end +$scope struct \[11] $end +$var reg 1 P# mem_5 $end +$upscope $end +$scope struct \[12] $end +$var reg 1 Q# mem_5 $end +$upscope $end +$scope struct \[13] $end +$var reg 1 R# mem_5 $end +$upscope $end +$scope struct \[14] $end +$var reg 1 S# mem_5 $end +$upscope $end +$scope struct \[15] $end +$var reg 1 T# mem_5 $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 4 8" addr $end +$var wire 1 9" en $end +$var wire 1 :" clk $end +$var wire 1 ;" data $end +$upscope $end +$scope struct w1 $end +$var wire 4 <" addr $end +$var wire 1 =" en $end +$var wire 1 >" clk $end +$var wire 1 ?" data $end +$var wire 1 @" mask $end +$upscope $end +$upscope $end +$scope struct mem_6 $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 1 U# mem_6 $end +$upscope $end +$scope struct \[1] $end +$var reg 1 V# mem_6 $end +$upscope $end +$scope struct \[2] $end +$var reg 1 W# mem_6 $end +$upscope $end +$scope struct \[3] $end +$var reg 1 X# mem_6 $end +$upscope $end +$scope struct \[4] $end +$var reg 1 Y# mem_6 $end +$upscope $end +$scope struct \[5] $end +$var reg 1 Z# mem_6 $end +$upscope $end +$scope struct \[6] $end +$var reg 1 [# mem_6 $end +$upscope $end +$scope struct \[7] $end +$var reg 1 \# mem_6 $end +$upscope $end +$scope struct \[8] $end +$var reg 1 ]# mem_6 $end +$upscope $end +$scope struct \[9] $end +$var reg 1 ^# mem_6 $end +$upscope $end +$scope struct \[10] $end +$var reg 1 _# mem_6 $end +$upscope $end +$scope struct \[11] $end +$var reg 1 `# mem_6 $end +$upscope $end +$scope struct \[12] $end +$var reg 1 a# mem_6 $end +$upscope $end +$scope struct \[13] $end +$var reg 1 b# mem_6 $end +$upscope $end +$scope struct \[14] $end +$var reg 1 c# mem_6 $end +$upscope $end +$scope struct \[15] $end +$var reg 1 d# mem_6 $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 4 A" addr $end +$var wire 1 B" en $end +$var wire 1 C" clk $end +$var wire 1 D" data $end +$upscope $end +$scope struct w1 $end +$var wire 4 E" addr $end +$var wire 1 F" en $end +$var wire 1 G" clk $end +$var wire 1 H" data $end +$var wire 1 I" mask $end +$upscope $end +$upscope $end +$scope struct mem_7 $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 1 e# mem_7 $end +$upscope $end +$scope struct \[1] $end +$var reg 1 f# mem_7 $end +$upscope $end +$scope struct \[2] $end +$var reg 1 g# mem_7 $end +$upscope $end +$scope struct \[3] $end +$var reg 1 h# mem_7 $end +$upscope $end +$scope struct \[4] $end +$var reg 1 i# mem_7 $end +$upscope $end +$scope struct \[5] $end +$var reg 1 j# mem_7 $end +$upscope $end +$scope struct \[6] $end +$var reg 1 k# mem_7 $end +$upscope $end +$scope struct \[7] $end +$var reg 1 l# mem_7 $end +$upscope $end +$scope struct \[8] $end +$var reg 1 m# mem_7 $end +$upscope $end +$scope struct \[9] $end +$var reg 1 n# mem_7 $end +$upscope $end +$scope struct \[10] $end +$var reg 1 o# mem_7 $end +$upscope $end +$scope struct \[11] $end +$var reg 1 p# mem_7 $end +$upscope $end +$scope struct \[12] $end +$var reg 1 q# mem_7 $end +$upscope $end +$scope struct \[13] $end +$var reg 1 r# mem_7 $end +$upscope $end +$scope struct \[14] $end +$var reg 1 s# mem_7 $end +$upscope $end +$scope struct \[15] $end +$var reg 1 t# mem_7 $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 4 J" addr $end +$var wire 1 K" en $end +$var wire 1 L" clk $end +$var wire 1 M" data $end +$upscope $end +$scope struct w1 $end +$var wire 4 N" addr $end +$var wire 1 O" en $end +$var wire 1 P" clk $end +$var wire 1 Q" data $end +$var wire 1 R" mask $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +0S" +0T" +0U" +0V" +0W" +0X" +0Y" +0Z" +0[" +0\" +0]" +0^" +0_" +0`" +0a" +0b" +1c" +0d" +0e" +0f" +0g" +0h" +0i" +0j" +0k" +0l" +0m" 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+b0 /" +00" +01" +02" +b0 3" +04" +05" +06" +07" +b0 8" +09" +0:" +0;" +b0 <" +0=" +0>" +0?" +0@" +b0 A" +0B" +0C" +0D" +b0 E" +0F" +0G" +0H" +0I" +b0 J" +0K" +0L" +0M" +b0 N" +0O" +0P" +0Q" +0R" +$end +#1000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#2000000 +1" +0# +1& +0' +1( +1* +0+ +1. +0/ +10 +12 +03 +16 +07 +18 +1: +0; +1> +0? +1@ +1B +0C +1D +1E +1G +0H +1I +1J +1L +0M +1N +1O +1Q +0R +1S +1T +1V +0W +1X +1Y +1[ +0\ +1] +1^ +1` +0a +1b +1c +1e +0f +1g +1h +1j +0k +1n +0o +1p +1q +1s +0t +1u +1w +0x +1y +1z +1| +0} +1"" +0#" +1$" +1%" +1'" +0(" +1)" +1+" +0," +1-" +1." +10" +01" +14" +05" +16" +17" +19" +0:" +1;" +1=" +0>" +1?" +1@" +1B" +0C" +1F" +0G" +1H" +1I" +1K" +0L" +1M" +1O" +0P" +1Q" +1R" +#3000000 +1S" +1c" +1s" +1%# +15# +1E# +1U# +1e# +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +1$ +1, +14 +1< +1l +1~ +12" +1D" +#4000000 +0# +0' +0+ +0/ +03 +07 +0; +0? +0C +0D +0H +0I +0M +0N +0R +0S +0W +0X +0\ +0] +0a +0b +0f +0g +0k +0o +0p +0t +0x +0y +0} +0#" +0$" +0(" +0," +0-" +01" +05" +06" +0:" +0>" +0?" +0C" +0G" +0H" +0L" +0P" +0Q" +#5000000 +0S" +0c" +0s" +0%# +05# +0E# +0U# +0e# +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +0$ +0( +0, +00 +04 +08 +0< +0@ +0l +0u +0~ +0)" +02" +0;" +0D" +0M" +#6000000 +0# +0' +0+ +0/ +03 +07 +0; +0? +0B +0C +0G +0H +0L +0M +0Q +0R +0V +0W +0[ +0\ +0` +0a +0e +0f +0k +0n +0o +0t +0w +0x +0} +0"" +0#" +0(" +0+" +0," +01" +04" +05" +0:" +0=" +0>" +0C" +0F" +0G" +0L" +0O" +0P" +#7000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#8000000 +b1 ! +0# +b1 % +0' +b1 ) +0+ +b1 - +0/ +10 +b1 1 +03 +b1 5 +07 +b1 9 +0; +b1 = +0? +1@ +0C +0H +0M +0R +0W +0\ +0a +0f +b1 i +0k +0o +b1 r +0t +0x +b1 { +0} +0#" +b1 &" +0(" +1)" +0," +b1 /" +01" +05" +b1 8" +0:" +0>" +b1 A" +0C" +0G" +b1 J" +0L" +1M" +0P" +#9000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#10000000 +b10 ! +0# +b10 % +0' +b10 ) +0+ +b10 - +0/ +00 +b10 1 +03 +b10 5 +07 +18 +b10 9 +0; +b10 = +0? +0C +0H +0M +0R +0W +0\ +0a +0f +b10 i +0k +0o +b10 r +0t +0x +b10 { +0} +0#" +b10 &" +0(" +0)" +0," +b10 /" +01" +05" +b10 8" +0:" +1;" +0>" +b10 A" +0C" +0G" +b10 J" +0L" +0P" +#11000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#12000000 +b11 ! +0# +b11 % +0' +b11 ) +0+ +b11 - +0/ +b11 1 +03 +b11 5 +07 +08 +b11 9 +0; +b11 = +0? +0@ +0C +0H +0M +0R +0W +0\ +0a +0f +b11 i +0k +0o +b11 r +0t +0x +b11 { +0} +0#" +b11 &" +0(" +0," +b11 /" +01" +05" +b11 8" +0:" +0;" +0>" +b11 A" +0C" +0G" +b11 J" +0L" +0M" +0P" +#13000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#14000000 +b100 ! +0# +b100 % +0' +b100 ) +0+ +b100 - +0/ +10 +b100 1 +03 +b100 5 +07 +18 +b100 9 +0; +b100 = +0? +0C +0H +0M +0R +0W +0\ +0a +0f +b100 i +0k +0o +b100 r +0t +0x +b100 { +0} +0#" +b100 &" +0(" +1)" +0," +b100 /" +01" +05" +b100 8" +0:" +1;" +0>" +b100 A" +0C" +0G" +b100 J" +0L" +0P" +#15000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#16000000 +b101 ! +0# +b101 % +0' +b101 ) +0+ +1, +b101 - +0/ +b101 1 +03 +b101 5 +07 +b101 9 +0; +1< +b101 = +0? +1@ +0C +0H +0M +0R +0W +0\ +0a +0f +b101 i +0k +0o +b101 r +0t +0x +b101 { +0} +1~ +0#" +b101 &" +0(" +0," +b101 /" +01" +05" +b101 8" +0:" +0>" +b101 A" +0C" +1D" +0G" +b101 J" +0L" +1M" +0P" +#17000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#18000000 +b110 ! +0# +b110 % +0' +b110 ) +0+ +0, +b110 - +0/ +b110 1 +03 +b110 5 +07 +08 +b110 9 +0; +b110 = +0? +0@ +0C +0H +0M +0R +0W +0\ +0a +0f +b110 i +0k +0o +b110 r +0t +0x +b110 { +0} +0~ +0#" +b110 &" +0(" +0," +b110 /" +01" +05" +b110 8" +0:" +0;" +0>" +b110 A" +0C" +0G" +b110 J" +0L" +0M" +0P" +#19000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#20000000 +b111 ! +0# +b111 % +0' +b111 ) +0+ +b111 - +0/ +b111 1 +03 +b111 5 +07 +b111 9 +0; +0< +b111 = +0? +1@ +0C +0H +0M +0R +0W +0\ +0a +0f +b111 i +0k +0o +b111 r +0t +0x +b111 { +0} +0#" +b111 &" +0(" +0," +b111 /" +01" +05" +b111 8" +0:" +0>" +b111 A" +0C" +0D" +0G" +b111 J" +0L" +1M" +0P" +#21000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#22000000 +b1000 ! +0# +b1000 % +0' +b1000 ) +0+ +b1000 - +0/ +00 +b1000 1 +03 +b1000 5 +07 +b1000 9 +0; +b1000 = +0? +0C +0H +0M +0R +0W +0\ +0a +0f +b1000 i +0k +0o +b1000 r +0t +0x +b1000 { +0} +0#" +b1000 &" +0(" +0)" +0," +b1000 /" +01" +05" +b1000 8" +0:" +0>" +b1000 A" +0C" +0G" +b1000 J" +0L" +0P" +#23000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#24000000 +b1001 ! +0# +b1001 % +0' +b1001 ) +0+ +b1001 - +0/ +b1001 1 +03 +b1001 5 +07 +b1001 9 +0; +1< +b1001 = +0? +0@ +0C +0H +0M +0R +0W +0\ +0a +0f +b1001 i +0k +0o +b1001 r +0t +0x +b1001 { +0} +0#" +b1001 &" +0(" +0," +b1001 /" +01" +05" +b1001 8" +0:" +0>" +b1001 A" +0C" +1D" +0G" +b1001 J" +0L" +0M" +0P" +#25000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#26000000 +b1010 ! +0# +b1010 % +0' +b1010 ) +0+ +b1010 - +0/ +b1010 1 +03 +14 +b1010 5 +07 +18 +b1010 9 +0; +b1010 = +0? +0C +0H +0M +0R +0W +0\ +0a +0f +b1010 i +0k +0o +b1010 r +0t +0x +b1010 { +0} +0#" +b1010 &" +0(" +0," +b1010 /" +01" +12" +05" +b1010 8" +0:" +1;" +0>" +b1010 A" +0C" +0G" +b1010 J" +0L" +0P" +#27000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#28000000 +b1011 ! +0# +b1011 % +0' +b1011 ) +0+ +b1011 - +0/ +b1011 1 +03 +04 +b1011 5 +07 +b1011 9 +0; +b1011 = +0? +0C +0H +0M +0R +0W +0\ +0a +0f +b1011 i +0k +0o +b1011 r +0t +0x +b1011 { +0} +0#" +b1011 &" +0(" +0," +b1011 /" +01" +02" +05" +b1011 8" +0:" +0>" +b1011 A" +0C" +0G" +b1011 J" +0L" +0P" +#29000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#30000000 +b1100 ! +0# +b1100 % +0' +b1100 ) +0+ +b1100 - +0/ +b1100 1 +03 +b1100 5 +07 +08 +b1100 9 +0; +b1100 = +0? +0C +0H +0M +0R +0W +0\ +0a +0f +b1100 i +0k +0o +b1100 r +0t +0x +b1100 { +0} +0#" +b1100 &" +0(" +0," +b1100 /" +01" +05" +b1100 8" +0:" +0;" +0>" +b1100 A" +0C" +0G" +b1100 J" +0L" +0P" +#31000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#32000000 +b1101 ! +0# +b1101 % +0' +b1101 ) +0+ +b1101 - +0/ +b1101 1 +03 +b1101 5 +07 +b1101 9 +0; +0< +b1101 = +0? +0C +0H +0M +0R +0W +0\ +0a +0f +b1101 i +0k +0o +b1101 r +0t +0x +b1101 { +0} +0#" +b1101 &" +0(" +0," +b1101 /" +01" +05" +b1101 8" +0:" +0>" +b1101 A" +0C" +0D" +0G" +b1101 J" +0L" +0P" +#33000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#34000000 +b1110 ! +0# +b1110 % +0' +b1110 ) +0+ +b1110 - +0/ +b1110 1 +03 +b1110 5 +07 +b1110 9 +0; +b1110 = +0? +1@ +0C +0H +0M +0R +0W +0\ +0a +0f +b1110 i +0k +0o +b1110 r +0t +0x +b1110 { +0} +0#" +b1110 &" +0(" +0," +b1110 /" +01" +05" +b1110 8" +0:" +0>" +b1110 A" +0C" +0G" +b1110 J" +0L" +1M" +0P" +#35000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#36000000 +b1111 ! +0# +b1111 % +0' +b1111 ) +0+ +b1111 - +0/ +b1111 1 +03 +b1111 5 +07 +b1111 9 +0; +b1111 = +0? +0@ +0C +0H +0M +0R +0W +0\ +0a +0f +b1111 i +0k +0o +b1111 r +0t +0x +b1111 { +0} +0#" +b1111 &" +0(" +0," +b1111 /" +01" +05" +b1111 8" +0:" +0>" +b1111 A" +0C" +0G" +b1111 J" +0L" +0M" +0P" +#37000000 +1# +1' +1+ +1/ +13 +17 +1; +1? +1C +1H +1M +1R +1W +1\ +1a +1f +1k +1o +1t +1x +1} +1#" +1(" +1," +11" +15" +1:" +1>" +1C" +1G" +1L" +1P" +#38000000 +0# +0' +0+ +0/ +03 +07 +0; +0? +0C +0H +0M +0R +0W +0\ +0a +0f +0k +0o +0t +0x +0} +0#" +0(" +0," +01" +05" +0:" +0>" +0C" +0G" +0L" +0P"