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fix blinky example to use cmp_eq instead of ==

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This commit is contained in:
Jacob Lifshay 2024-07-22 00:52:29 -07:00
parent 5707ede2ae
commit 79031ccf88
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
1 changed files with 3 additions and 3 deletions
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6
crates/fayalite/examples/blinky.rs
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@ -2,7 +2,7 @@ use clap::Parser;
use fayalite::{ use fayalite::{
clock::{Clock, ClockDomain}, clock::{Clock, ClockDomain},
hdl_module, hdl_module,
int::{DynUInt, DynUIntType, IntTypeTrait, UInt}, int::{DynUInt, DynUIntType, IntCmp, IntTypeTrait, UInt},
reset::{SyncReset, ToReset}, reset::{SyncReset, ToReset},
}; };
@ -24,8 +24,8 @@ fn blinky(clock_frequency: u64) {
#[hdl] #[hdl]
let output_reg: UInt<1> = m.reg_builder().clock_domain(cd).reset_default(); let output_reg: UInt<1> = m.reg_builder().clock_domain(cd).reset_default();
#[hdl] #[hdl]
if counter == int_ty.literal(max_value) { if counter.cmp_eq(max_value) {
m.connect(counter, int_ty.literal(0)); m.connect_any(counter, 0u8);
m.connect(output_reg, !output_reg); m.connect(output_reg, !output_reg);
} else { } else {
m.connect_any(counter, counter + 1_hdl_u1); m.connect_any(counter, counter + 1_hdl_u1);