diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index 3fc643c..008d792 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -271,7 +271,7 @@ fn test_shift_register() { assert_eq!( *expected, sim.read_bool(sim.io().q), - "cycle: {cycle}\nvcd:\n{}", + "vcd:\n{}\ncycle: {cycle}", String::from_utf8(writer.take()).unwrap(), ); } @@ -473,7 +473,7 @@ fn test_enums() { assert_eq!( expected, io, - "cycle: {cycle}\nvcd:\n{}", + "vcd:\n{}\ncycle: {cycle}", String::from_utf8(writer.take()).unwrap(), ); sim.write_clock(sim.io().cd.clk, false); @@ -671,7 +671,7 @@ fn test_memories() { assert_eq!( expected, io, - "cycle: {cycle}\nvcd:\n{}", + "vcd:\n{}\ncycle: {cycle}", String::from_utf8(writer.take()).unwrap(), ); sim.advance_time(SimDuration::from_micros(1)); @@ -947,7 +947,7 @@ fn test_memories2() { assert_eq!( expected, io, - "cycle: {cycle}\nvcd:\n{}", + "vcd:\n{}\ncycle: {cycle}", String::from_utf8(writer.take()).unwrap(), ); sim.advance_time(SimDuration::from_nanos(250)); @@ -967,4 +967,241 @@ fn test_memories2() { } } -// TODO: add more tests for memories +#[hdl_module(outline_generated)] +pub fn memories3() { + #[hdl] + let r: fayalite::memory::ReadStruct, 8>, ConstUsize<3>> = m.input(); + #[hdl] + let w: fayalite::memory::WriteStruct, 8>, ConstUsize<3>> = m.input(); + #[hdl] + let mut mem: MemBuilder, 8>> = memory(); + mem.depth(8); + mem.read_latency(2); + mem.write_latency(NonZeroUsize::new(2).unwrap()); + mem.read_under_write(ReadUnderWrite::Old); + connect_any(mem.new_read_port(), r); + connect_any(mem.new_write_port(), w); +} + +#[hdl] +#[test] +fn test_memories3() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut sim = Simulation::new(memories3()); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + sim.write_clock(sim.io().r.clk, false); + sim.write_clock(sim.io().w.clk, false); + #[derive(Debug, PartialEq, Eq, Clone, Copy)] + struct IO { + r_addr: u8, + r_en: bool, + r_data: [u8; 8], + w_addr: u8, + w_en: bool, + w_data: [u8; 8], + w_mask: [bool; 8], + } + let io_cycles = [ + IO { + r_addr: 0, + r_en: false, + r_data: [0; 8], + w_addr: 0, + w_en: true, + w_data: [0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0], + w_mask: [false, true, false, true, true, false, false, true], + }, + IO { + r_addr: 0, + r_en: true, + r_data: [0; 8], + w_addr: 1, + w_en: false, + w_data: [0; 8], + w_mask: [false; 8], + }, + IO { + r_addr: 0, + r_en: true, + r_data: [0, 0x34, 0, 0x78, 0x9A, 0, 0, 0xF0], + w_addr: 1, + w_en: false, + w_data: [0; 8], + w_mask: [false; 8], + }, + IO { + r_addr: 0, + r_en: true, + r_data: [0, 0x34, 0, 0x78, 0x9A, 0, 0, 0xF0], + w_addr: 0, + w_en: true, + w_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10], + w_mask: [true; 8], + }, + IO { + r_addr: 0, + r_en: true, + r_data: [0, 0x34, 0, 0x78, 0x9A, 0, 0, 0xF0], + w_addr: 0, + w_en: true, + w_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10], + w_mask: [true; 8], + }, + IO { + r_addr: 0, + r_en: true, + r_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10], + w_addr: 0, + w_en: true, + w_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10], + w_mask: [true; 8], + }, + IO { + r_addr: 0, + r_en: false, + r_data: [0; 8], + w_addr: 1, + w_en: true, + w_data: [0x13, 0x57, 0x9B, 0xDF, 0x02, 0x46, 0x8A, 0xCE], + w_mask: [true; 8], + }, + IO { + r_addr: 0, + r_en: false, + r_data: [0; 8], + w_addr: 2, + w_en: true, + w_data: *b"testing!", + w_mask: [true; 8], + }, + IO { + r_addr: 0, + r_en: false, + r_data: [0; 8], + w_addr: 3, + w_en: true, + w_data: *b"more tst", + w_mask: [true; 8], + }, + IO { + r_addr: 0, + r_en: true, + r_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10], + w_addr: 0, + w_en: false, + w_data: [0; 8], + w_mask: [false; 8], + }, + IO { + r_addr: 1, + r_en: true, + r_data: [0x13, 0x57, 0x9B, 0xDF, 0x02, 0x46, 0x8A, 0xCE], + w_addr: 0, + w_en: false, + w_data: [0; 8], + w_mask: [false; 8], + }, + IO { + r_addr: 2, + r_en: true, + r_data: *b"testing!", + w_addr: 0, + w_en: false, + w_data: [0; 8], + w_mask: [false; 8], + }, + IO { + r_addr: 3, + r_en: true, + r_data: *b"more tst", + w_addr: 0, + w_en: false, + w_data: [0; 8], + w_mask: [false; 8], + }, + ]; + for cycle in 0..io_cycles.len() + 2 { + { + let IO { + r_addr, + r_en, + r_data: _, + w_addr, + w_en, + w_data, + w_mask, + } = io_cycles.get(cycle).copied().unwrap_or(IO { + r_addr: 0, + r_en: false, + r_data: [0; 8], + w_addr: 0, + w_en: false, + w_data: [0; 8], + w_mask: [false; 8], + }); + sim.write_bool_or_int(sim.io().r.addr, r_addr.cast_to_static()); + sim.write_bool(sim.io().r.en, r_en); + sim.write_bool_or_int(sim.io().w.addr, w_addr.cast_to_static()); + sim.write_bool(sim.io().w.en, w_en); + for (i, v) in w_data.into_iter().enumerate() { + sim.write_bool_or_int(sim.io().w.data[i], v); + } + for (i, v) in w_mask.into_iter().enumerate() { + sim.write_bool_or_int(sim.io().w.mask[i], v); + } + } + sim.advance_time(SimDuration::from_nanos(250)); + sim.write_clock(sim.io().r.clk, true); + sim.write_clock(sim.io().w.clk, true); + sim.advance_time(SimDuration::from_nanos(250)); + if let Some( + expected @ IO { + r_addr, + r_en, + r_data: _, + w_addr, + w_en, + w_data, + w_mask, + }, + ) = cycle.checked_sub(1).and_then(|i| io_cycles.get(i).copied()) + { + let io = IO { + r_addr, + r_en, + r_data: std::array::from_fn(|i| { + sim.read_bool_or_int(sim.io().r.data[i]) + .to_bigint() + .try_into() + .expect("known to be in range") + }), + w_addr, + w_en, + w_data, + w_mask, + }; + assert_eq!( + expected, + io, + "vcd:\n{}\ncycle: {cycle}", + String::from_utf8(writer.take()).unwrap(), + ); + } + sim.advance_time(SimDuration::from_nanos(250)); + sim.write_clock(sim.io().r.clk, false); + sim.write_clock(sim.io().w.clk, false); + sim.advance_time(SimDuration::from_nanos(250)); + } + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/memories3.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/memories3.txt") { + panic!(); + } +} diff --git a/crates/fayalite/tests/sim/expected/memories3.txt b/crates/fayalite/tests/sim/expected/memories3.txt new file mode 100644 index 0000000..7860bc5 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/memories3.txt @@ -0,0 +1,4882 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 14, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 108, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.addr", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[7]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.addr", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[7]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[0]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[1]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[2]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[3]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[4]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[5]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[6]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[7]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.addr", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[7]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[7]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[7]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.addr", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[7]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[0]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[1]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[2]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[3]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[4]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[5]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[6]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[7]", + ty: Bool, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[7]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[7]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[0]", + ty: Bool, + }, + SlotDebugData { + name: "[1]", + ty: Bool, + }, + SlotDebugData { + name: "[2]", + ty: Bool, + }, + SlotDebugData { + name: "[3]", + ty: Bool, + }, + SlotDebugData { + name: "[4]", + ty: Bool, + }, + SlotDebugData { + name: "[5]", + ty: Bool, + }, + SlotDebugData { + name: "[6]", + ty: Bool, + }, + SlotDebugData { + name: "[7]", + ty: Bool, + }, + SlotDebugData { + name: "[0]", + ty: Bool, + }, + SlotDebugData { + name: "[1]", + ty: Bool, + }, + SlotDebugData { + name: "[2]", + ty: Bool, + }, + SlotDebugData { + name: "[3]", + ty: Bool, + }, + SlotDebugData { + name: "[4]", + ty: Bool, + }, + SlotDebugData { + name: "[5]", + ty: Bool, + }, + SlotDebugData { + name: "[6]", + ty: Bool, + }, + SlotDebugData { + name: "[7]", + ty: Bool, + }, + ], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 8>, 8>, + data: [ + // len = 0x8 + [0x0]: 0x0000000000000000, + [0x1]: 0x0000000000000000, + [0x2]: 0x0000000000000000, + [0x3]: 0x0000000000000000, + [0x4]: 0x0000000000000000, + [0x5]: 0x0000000000000000, + [0x6]: 0x0000000000000000, + [0x7]: 0x0000000000000000, + ], + }, + ], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:8:1 + 0: Copy { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.addr", ty: UInt<3> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.addr", ty: UInt<3> }, + }, + 1: Copy { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.en", ty: Bool }, + src: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.en", ty: Bool }, + }, + 2: Copy { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.clk", ty: Clock }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.clk", ty: Clock }, + }, + 3: Copy { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[0]", ty: UInt<8> }, + src: StatePartIndex(14), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[0]", ty: UInt<8> }, + }, + 4: Copy { + dest: StatePartIndex(61), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[1]", ty: UInt<8> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[1]", ty: UInt<8> }, + }, + 5: Copy { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[2]", ty: UInt<8> }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[2]", ty: UInt<8> }, + }, + 6: Copy { + dest: StatePartIndex(63), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[3]", ty: UInt<8> }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[3]", ty: UInt<8> }, + }, + 7: Copy { + dest: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[4]", ty: UInt<8> }, + src: StatePartIndex(18), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[4]", ty: UInt<8> }, + }, + 8: Copy { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[5]", ty: UInt<8> }, + src: StatePartIndex(19), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[5]", ty: UInt<8> }, + }, + 9: Copy { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[6]", ty: UInt<8> }, + src: StatePartIndex(20), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[6]", ty: UInt<8> }, + }, + 10: Copy { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[7]", ty: UInt<8> }, + src: StatePartIndex(21), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[7]", ty: UInt<8> }, + }, + 11: Copy { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[0]", ty: Bool }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[0]", ty: Bool }, + }, + 12: Copy { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[1]", ty: Bool }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[1]", ty: Bool }, + }, + 13: Copy { + dest: StatePartIndex(70), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[2]", ty: Bool }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[2]", ty: Bool }, + }, + 14: Copy { + dest: StatePartIndex(71), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[3]", ty: Bool }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[3]", ty: Bool }, + }, + 15: Copy { + dest: StatePartIndex(72), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[4]", ty: Bool }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[4]", ty: Bool }, + }, + 16: Copy { + dest: StatePartIndex(73), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[5]", ty: Bool }, + src: StatePartIndex(27), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[5]", ty: Bool }, + }, + 17: Copy { + dest: StatePartIndex(74), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[6]", ty: Bool }, + src: StatePartIndex(28), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[6]", ty: Bool }, + }, + 18: Copy { + dest: StatePartIndex(75), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[7]", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[7]", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 19: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[0]", ty: UInt<8> }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[0]", ty: UInt<8> }, + }, + 20: Copy { + dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[1]", ty: UInt<8> }, + src: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[1]", ty: UInt<8> }, + }, + 21: Copy { + dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[2]", ty: UInt<8> }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[2]", ty: UInt<8> }, + }, + 22: Copy { + dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[3]", ty: UInt<8> }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[3]", ty: UInt<8> }, + }, + 23: Copy { + dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[4]", ty: UInt<8> }, + src: StatePartIndex(37), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[4]", ty: UInt<8> }, + }, + 24: Copy { + dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[5]", ty: UInt<8> }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[5]", ty: UInt<8> }, + }, + 25: Copy { + dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[6]", ty: UInt<8> }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[6]", ty: UInt<8> }, + }, + 26: Copy { + dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[7]", ty: UInt<8> }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[7]", ty: UInt<8> }, + }, + 27: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.clk", ty: Clock }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.clk", ty: Clock }, + }, + 28: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.en", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.en", ty: Bool }, + }, + 29: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.addr", ty: UInt<3> }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.addr", ty: UInt<3> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 30: CastBigToArrayIndex { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.addr", ty: UInt<3> }, + }, + 31: IsNonZeroDestIsSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.en", ty: Bool }, + }, + 32: IsNonZeroDestIsSmall { + dest: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.clk", ty: Clock }, + }, + 33: AndSmall { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 34: CastBigToArrayIndex { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.addr", ty: UInt<3> }, + }, + 35: IsNonZeroDestIsSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.en", ty: Bool }, + }, + 36: BranchIfSmallZero { + target: 46, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 37: MemoryReadUInt { + dest: StatePartIndex(41), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 0, + width: 8, + }, + 38: MemoryReadUInt { + dest: StatePartIndex(42), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 8, + width: 8, + }, + 39: MemoryReadUInt { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 16, + width: 8, + }, + 40: MemoryReadUInt { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 24, + width: 8, + }, + 41: MemoryReadUInt { + dest: StatePartIndex(45), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 32, + width: 8, + }, + 42: MemoryReadUInt { + dest: StatePartIndex(46), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 40, + width: 8, + }, + 43: MemoryReadUInt { + dest: StatePartIndex(47), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 48, + width: 8, + }, + 44: MemoryReadUInt { + dest: StatePartIndex(48), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 56, + width: 8, + }, + 45: Branch { + target: 54, + }, + 46: Const { + dest: StatePartIndex(41), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + value: 0x0, + }, + 47: Const { + dest: StatePartIndex(42), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> }, + value: 0x0, + }, + 48: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + value: 0x0, + }, + 49: Const { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> }, + value: 0x0, + }, + 50: Const { + dest: StatePartIndex(45), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> }, + value: 0x0, + }, + 51: Const { + dest: StatePartIndex(46), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> }, + value: 0x0, + }, + 52: Const { + dest: StatePartIndex(47), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> }, + value: 0x0, + }, + 53: Const { + dest: StatePartIndex(48), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> }, + value: 0x0, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.clk", ty: Clock }, + }, + 55: AndSmall { + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: BranchIfSmallZero { + target: 73, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 57: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[0]", ty: UInt<8> }, + src: StatePartIndex(49), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 58: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[1]", ty: UInt<8> }, + src: StatePartIndex(50), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> }, + }, + 59: Copy { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[2]", ty: UInt<8> }, + src: StatePartIndex(51), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + }, + 60: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[3]", ty: UInt<8> }, + src: StatePartIndex(52), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> }, + }, + 61: Copy { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[4]", ty: UInt<8> }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> }, + }, + 62: Copy { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[5]", ty: UInt<8> }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> }, + }, + 63: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[6]", ty: UInt<8> }, + src: StatePartIndex(55), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> }, + }, + 64: Copy { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[7]", ty: UInt<8> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> }, + }, + 65: Copy { + dest: StatePartIndex(49), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(41), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 66: Copy { + dest: StatePartIndex(50), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> }, + src: StatePartIndex(42), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> }, + }, + 67: Copy { + dest: StatePartIndex(51), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + }, + 68: Copy { + dest: StatePartIndex(52), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> }, + }, + 69: Copy { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> }, + src: StatePartIndex(45), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> }, + }, + 70: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> }, + src: StatePartIndex(46), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> }, + }, + 71: Copy { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> }, + src: StatePartIndex(47), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> }, + }, + 72: Copy { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> }, + src: StatePartIndex(48), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> }, + }, + 73: BranchIfSmallZero { + target: 127, + value: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 74: CopySmall { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 75: CopySmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + }, + 76: CopySmall { + dest: StatePartIndex(13), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 77: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 78: Copy { + dest: StatePartIndex(84), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(76), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + }, + 79: Copy { + dest: StatePartIndex(85), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> }, + src: StatePartIndex(77), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> }, + }, + 80: Copy { + dest: StatePartIndex(86), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + src: StatePartIndex(78), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + }, + 81: Copy { + dest: StatePartIndex(87), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> }, + src: StatePartIndex(79), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> }, + }, + 82: Copy { + dest: StatePartIndex(88), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> }, + src: StatePartIndex(80), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> }, + }, + 83: Copy { + dest: StatePartIndex(89), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> }, + src: StatePartIndex(81), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> }, + }, + 84: Copy { + dest: StatePartIndex(90), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> }, + src: StatePartIndex(82), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> }, + }, + 85: Copy { + dest: StatePartIndex(91), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> }, + src: StatePartIndex(83), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> }, + }, + 86: Copy { + dest: StatePartIndex(76), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + src: StatePartIndex(60), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[0]", ty: UInt<8> }, + }, + 87: Copy { + dest: StatePartIndex(77), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> }, + src: StatePartIndex(61), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[1]", ty: UInt<8> }, + }, + 88: Copy { + dest: StatePartIndex(78), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + src: StatePartIndex(62), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[2]", ty: UInt<8> }, + }, + 89: Copy { + dest: StatePartIndex(79), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> }, + src: StatePartIndex(63), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[3]", ty: UInt<8> }, + }, + 90: Copy { + dest: StatePartIndex(80), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> }, + src: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[4]", ty: UInt<8> }, + }, + 91: Copy { + dest: StatePartIndex(81), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[5]", ty: UInt<8> }, + }, + 92: Copy { + dest: StatePartIndex(82), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[6]", ty: UInt<8> }, + }, + 93: Copy { + dest: StatePartIndex(83), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[7]", ty: UInt<8> }, + }, + 94: Copy { + dest: StatePartIndex(100), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, + src: StatePartIndex(92), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, + }, + 95: Copy { + dest: StatePartIndex(101), // (0x0) SlotDebugData { name: "[1]", ty: Bool }, + src: StatePartIndex(93), // (0x0) SlotDebugData { name: "[1]", ty: Bool }, + }, + 96: Copy { + dest: StatePartIndex(102), // (0x0) SlotDebugData { name: "[2]", ty: Bool }, + src: StatePartIndex(94), // (0x0) SlotDebugData { name: "[2]", ty: Bool }, + }, + 97: Copy { + dest: StatePartIndex(103), // (0x0) SlotDebugData { name: "[3]", ty: Bool }, + src: StatePartIndex(95), // (0x0) SlotDebugData { name: "[3]", ty: Bool }, + }, + 98: Copy { + dest: StatePartIndex(104), // (0x0) SlotDebugData { name: "[4]", ty: Bool }, + src: StatePartIndex(96), // (0x0) SlotDebugData { name: "[4]", ty: Bool }, + }, + 99: Copy { + dest: StatePartIndex(105), // (0x0) SlotDebugData { name: "[5]", ty: Bool }, + src: StatePartIndex(97), // (0x0) SlotDebugData { name: "[5]", ty: Bool }, + }, + 100: Copy { + dest: StatePartIndex(106), // (0x0) SlotDebugData { name: "[6]", ty: Bool }, + src: StatePartIndex(98), // (0x0) SlotDebugData { name: "[6]", ty: Bool }, + }, + 101: Copy { + dest: StatePartIndex(107), // (0x0) SlotDebugData { name: "[7]", ty: Bool }, + src: StatePartIndex(99), // (0x0) SlotDebugData { name: "[7]", ty: Bool }, + }, + 102: Copy { + dest: StatePartIndex(92), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[0]", ty: Bool }, + }, + 103: Copy { + dest: StatePartIndex(93), // (0x0) SlotDebugData { name: "[1]", ty: Bool }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[1]", ty: Bool }, + }, + 104: Copy { + dest: StatePartIndex(94), // (0x0) SlotDebugData { name: "[2]", ty: Bool }, + src: StatePartIndex(70), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[2]", ty: Bool }, + }, + 105: Copy { + dest: StatePartIndex(95), // (0x0) SlotDebugData { name: "[3]", ty: Bool }, + src: StatePartIndex(71), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[3]", ty: Bool }, + }, + 106: Copy { + dest: StatePartIndex(96), // (0x0) SlotDebugData { name: "[4]", ty: Bool }, + src: StatePartIndex(72), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[4]", ty: Bool }, + }, + 107: Copy { + dest: StatePartIndex(97), // (0x0) SlotDebugData { name: "[5]", ty: Bool }, + src: StatePartIndex(73), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[5]", ty: Bool }, + }, + 108: Copy { + dest: StatePartIndex(98), // (0x0) SlotDebugData { name: "[6]", ty: Bool }, + src: StatePartIndex(74), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[6]", ty: Bool }, + }, + 109: Copy { + dest: StatePartIndex(99), // (0x0) SlotDebugData { name: "[7]", ty: Bool }, + src: StatePartIndex(75), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[7]", ty: Bool }, + }, + 110: BranchIfSmallZero { + target: 127, + value: StatePartIndex(13), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: BranchIfZero { + target: 113, + value: StatePartIndex(100), // (0x0) SlotDebugData { name: "[0]", ty: Bool }, + }, + 112: MemoryWriteUInt { + value: StatePartIndex(84), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 0, + width: 8, + }, + 113: BranchIfZero { + target: 115, + value: StatePartIndex(101), // (0x0) SlotDebugData { name: "[1]", ty: Bool }, + }, + 114: MemoryWriteUInt { + value: StatePartIndex(85), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 8, + width: 8, + }, + 115: BranchIfZero { + target: 117, + value: StatePartIndex(102), // (0x0) SlotDebugData { name: "[2]", ty: Bool }, + }, + 116: MemoryWriteUInt { + value: StatePartIndex(86), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 16, + width: 8, + }, + 117: BranchIfZero { + target: 119, + value: StatePartIndex(103), // (0x0) SlotDebugData { name: "[3]", ty: Bool }, + }, + 118: MemoryWriteUInt { + value: StatePartIndex(87), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 24, + width: 8, + }, + 119: BranchIfZero { + target: 121, + value: StatePartIndex(104), // (0x0) SlotDebugData { name: "[4]", ty: Bool }, + }, + 120: MemoryWriteUInt { + value: StatePartIndex(88), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 32, + width: 8, + }, + 121: BranchIfZero { + target: 123, + value: StatePartIndex(105), // (0x0) SlotDebugData { name: "[5]", ty: Bool }, + }, + 122: MemoryWriteUInt { + value: StatePartIndex(89), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 40, + width: 8, + }, + 123: BranchIfZero { + target: 125, + value: StatePartIndex(106), // (0x0) SlotDebugData { name: "[6]", ty: Bool }, + }, + 124: MemoryWriteUInt { + value: StatePartIndex(90), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 48, + width: 8, + }, + 125: BranchIfZero { + target: 127, + value: StatePartIndex(107), // (0x0) SlotDebugData { name: "[7]", ty: Bool }, + }, + 126: MemoryWriteUInt { + value: StatePartIndex(91), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 8>, 8>, + // data: [ + // // len = 0x8 + // [0x0]: 0x1032547698badcfe, + // [0x1]: 0xce8a4602df9b5713, + // [0x2]: 0x21676e6974736574, + // [0x3]: 0x7473742065726f6d, + // [0x4]: 0x0000000000000000, + // [0x5]: 0x0000000000000000, + // [0x6]: 0x0000000000000000, + // [0x7]: 0x0000000000000000, + // ], + // }) (), + addr: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, + stride: 64, + start: 56, + width: 8, + }, + 127: XorSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 128: XorSmallImmediate { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 129: Return, + ], + .. + }, + pc: 129, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 8>, 8>, + data: [ + // len = 0x8 + [0x0]: 0x1032547698badcfe, + [0x1]: 0xce8a4602df9b5713, + [0x2]: 0x21676e6974736574, + [0x3]: 0x7473742065726f6d, + [0x4]: 0x0000000000000000, + [0x5]: 0x0000000000000000, + [0x6]: 0x0000000000000000, + [0x7]: 0x0000000000000000, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + ], + }, + }, + io: Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }, + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + data: Array, 8>, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 11, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.addr", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::r.data[7]", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<3>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(2), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(3), + }, + ty: CompiledTypeLayout { + ty: Array, 8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 8, + debug_data: [ + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[7]", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Array { + element: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, 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ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 7, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[5]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 8, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[6]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 9, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[7]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 10, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.en: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + /* offset = 5 */ + data: Array, 8>, + /* offset = 69 */ + mask: Array, + }, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 19, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.addr", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.data[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: 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"InstantiatedModule(memories3: memories3).memories3::w.mask[5]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[6]", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(memories3: memories3).memories3::w.mask[7]", + ty: Bool, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<3>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(2), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(3), + }, + ty: CompiledTypeLayout { + ty: Array, 8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 8, + debug_data: [ + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: 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SlotDebugData { + name: "[1]", + ty: Bool, + }, + SlotDebugData { + name: "[2]", + ty: Bool, + }, + SlotDebugData { + name: "[3]", + ty: Bool, + }, + SlotDebugData { + name: "[4]", + ty: Bool, + }, + SlotDebugData { + name: "[5]", + ty: Bool, + }, + SlotDebugData { + name: "[6]", + ty: Bool, + }, + SlotDebugData { + name: "[7]", + ty: Bool, + }, + ], + .. + }, + }, + body: Array { + element: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 11, len: 19 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.addr: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<3>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 11, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 13, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data: CompiledValue { + layout: CompiledTypeLayout { + ty: Array, 8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 8, + debug_data: [ + SlotDebugData { + name: "[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[3]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[4]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[5]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[6]", + ty: UInt<8>, + }, + SlotDebugData { + name: "[7]", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Array { + element: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 14, len: 8 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[0]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 14, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[1]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 15, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[2]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 16, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[3]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 17, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[4]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 18, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[5]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 19, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[6]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 20, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[7]: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 21, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.en: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 12, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask: CompiledValue { + layout: CompiledTypeLayout { + ty: Array, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 8, + debug_data: [ + SlotDebugData { + name: "[0]", + ty: Bool, + }, + SlotDebugData { + name: "[1]", + ty: Bool, + }, + SlotDebugData { + name: "[2]", + ty: Bool, + }, + SlotDebugData { + name: "[3]", + ty: Bool, + }, + SlotDebugData { + name: "[4]", + ty: Bool, + }, + SlotDebugData { + name: "[5]", + ty: Bool, + }, + SlotDebugData { + name: "[6]", + ty: Bool, + }, + SlotDebugData { + name: "[7]", + ty: Bool, + }, + ], + .. + }, + }, + body: Array { + element: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 22, len: 8 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[0]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 22, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[1]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 23, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[2]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 24, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[3]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 25, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[4]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 26, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[5]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 27, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[6]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 28, len: 1 }, + }, + write: None, + }, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[7]: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 29, len: 1 }, + }, + write: None, + }, + }, + made_initial_step: true, + needs_settle: false, + trace_decls: TraceModule { + name: "memories3", + children: [ + TraceModuleIO { + name: "r", + child: TraceBundle { + name: "r", + fields: [ + TraceUInt { + location: TraceScalarId(0), + name: "addr", + ty: UInt<3>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(1), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(2), + name: "clk", + flow: Source, + }, + TraceArray { + name: "data", + elements: [ + TraceUInt { + location: TraceScalarId(3), + name: "[0]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(4), + name: "[1]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(5), + name: "[2]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(6), + name: "[3]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(7), + name: "[4]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(8), + name: "[5]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(9), + name: "[6]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(10), + name: "[7]", + ty: UInt<8>, + flow: Sink, + }, + ], + ty: Array, 8>, + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + data: Array, 8>, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + data: Array, 8>, + }, + flow: Source, + }, + TraceModuleIO { + name: "w", + child: TraceBundle { + name: "w", + fields: [ + TraceUInt { + location: TraceScalarId(11), + name: "addr", + ty: UInt<3>, + flow: Source, + }, + TraceBool { + location: TraceScalarId(12), + name: "en", + flow: Source, + }, + TraceClock { + location: TraceScalarId(13), + name: "clk", + flow: Source, + }, + TraceArray { + name: "data", + elements: [ + TraceUInt { + location: TraceScalarId(14), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(15), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(16), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(17), + name: "[3]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(18), + name: "[4]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(19), + name: "[5]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(20), + name: "[6]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(21), + name: "[7]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 8>, + flow: Source, + }, + TraceArray { + name: "mask", + elements: [ + TraceBool { + location: TraceScalarId(22), + name: "[0]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(23), + name: "[1]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(24), + name: "[2]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(25), + name: "[3]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(26), + name: "[4]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(27), + name: "[5]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(28), + name: "[6]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(29), + name: "[7]", + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + /* offset = 5 */ + data: Array, 8>, + /* offset = 69 */ + mask: Array, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + /* offset = 5 */ + data: Array, 8>, + /* offset = 69 */ + mask: Array, + }, + flow: Source, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 64, + element_type: TraceArray { + name: "mem", + elements: [ + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 0, + len: 8, + }, + name: "[0]", + ty: UInt<8>, + flow: Duplex, + }, + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 8, + len: 8, + }, + name: "[1]", + ty: UInt<8>, + flow: Duplex, + }, + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 16, + len: 8, + }, + name: "[2]", + ty: UInt<8>, + flow: Duplex, + }, + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 24, + len: 8, + }, + name: "[3]", + ty: UInt<8>, + flow: Duplex, + }, + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 32, + len: 8, + }, + name: "[4]", + ty: UInt<8>, + flow: Duplex, + }, + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 40, + len: 8, + }, + name: "[5]", + ty: UInt<8>, + flow: Duplex, + }, + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 48, + len: 8, + }, + name: "[6]", + ty: UInt<8>, + flow: Duplex, + }, + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 56, + len: 8, + }, + name: "[7]", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Array, 8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(30), + name: "addr", + ty: UInt<3>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(31), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(32), + name: "clk", + flow: Sink, + }, + TraceArray { + name: "data", + elements: [ + TraceUInt { + location: TraceScalarId(33), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(34), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(35), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(36), + name: "[3]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(37), + name: "[4]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(38), + name: "[5]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(39), + name: "[6]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(40), + name: "[7]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + data: Array, 8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + data: Array, 8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(41), + name: "addr", + ty: UInt<3>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(42), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(43), + name: "clk", + flow: Sink, + }, + TraceArray { + name: "data", + elements: [ + TraceUInt { + location: TraceScalarId(44), + name: "[0]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(45), + name: "[1]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(46), + name: "[2]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(47), + name: "[3]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(48), + name: "[4]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(49), + name: "[5]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(50), + name: "[6]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(51), + name: "[7]", + ty: UInt<8>, + flow: Sink, + }, + ], + ty: Array, 8>, + flow: Sink, + }, + TraceArray { + name: "mask", + elements: [ + TraceBool { + location: TraceScalarId(52), + name: "[0]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(53), + name: "[1]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(54), + name: "[2]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(55), + name: "[3]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(56), + name: "[4]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(57), + name: "[5]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(58), + name: "[6]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(59), + name: "[7]", + flow: Sink, + }, + ], + ty: Array, + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + /* offset = 5 */ + data: Array, 8>, + /* offset = 69 */ + mask: Array, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + /* offset = 5 */ + data: Array, 8>, + /* offset = 69 */ + mask: Array, + }, + }, + ], + array_type: Array, 8>, 8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigUInt { + index: StatePartIndex(0), + ty: UInt<3>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigBool { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigClock { + index: StatePartIndex(2), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(3), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigUInt { + index: StatePartIndex(4), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(5), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(6), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigUInt { + index: StatePartIndex(7), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(8), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<3>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(16), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigUInt { + index: StatePartIndex(17), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(19), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigUInt { + index: StatePartIndex(20), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigUInt { + index: StatePartIndex(21), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(22), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(23), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(24), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(25), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(26), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigBool { + index: StatePartIndex(28), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigBool { + index: StatePartIndex(29), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(30), + kind: BigUInt { + index: StatePartIndex(30), + ty: UInt<3>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(31), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(32), + kind: BigClock { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(33), + kind: BigUInt { + index: StatePartIndex(33), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(34), + kind: BigUInt { + index: StatePartIndex(34), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(35), + kind: BigUInt { + index: StatePartIndex(35), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(36), + kind: BigUInt { + index: StatePartIndex(36), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(37), + kind: BigUInt { + index: StatePartIndex(37), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(38), + kind: BigUInt { + index: StatePartIndex(38), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(39), + kind: BigUInt { + index: StatePartIndex(39), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(40), + kind: BigUInt { + index: StatePartIndex(40), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(41), + kind: BigUInt { + index: StatePartIndex(57), + ty: UInt<3>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(42), + kind: BigBool { + index: StatePartIndex(58), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(43), + kind: BigClock { + index: StatePartIndex(59), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(44), + kind: BigUInt { + index: StatePartIndex(60), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(45), + kind: BigUInt { + index: StatePartIndex(61), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(46), + kind: BigUInt { + index: StatePartIndex(62), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(47), + kind: BigUInt { + index: StatePartIndex(63), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(48), + kind: BigUInt { + index: StatePartIndex(64), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(49), + kind: BigUInt { + index: StatePartIndex(65), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(50), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(51), + kind: BigUInt { + index: StatePartIndex(67), + ty: UInt<8>, + }, + state: 0x00, + last_state: 0x00, + }, + SimTrace { + id: TraceScalarId(52), + kind: BigBool { + index: StatePartIndex(68), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(53), + kind: BigBool { + index: StatePartIndex(69), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(54), + kind: BigBool { + index: StatePartIndex(70), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(55), + kind: BigBool { + index: StatePartIndex(71), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(56), + kind: BigBool { + index: StatePartIndex(72), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(57), + kind: BigBool { + index: StatePartIndex(73), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(58), + kind: BigBool { + index: StatePartIndex(74), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(59), + kind: BigBool { + index: StatePartIndex(75), + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 64, + element_type: TraceArray { + name: "mem", + elements: [ + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 0, + len: 8, + }, + name: "[0]", + ty: UInt<8>, + flow: Duplex, + }, + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 8, + len: 8, + }, + name: "[1]", + ty: UInt<8>, + flow: Duplex, + }, + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 16, + len: 8, + }, + name: "[2]", + ty: UInt<8>, + flow: Duplex, + }, + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 24, + len: 8, + }, + name: "[3]", + ty: UInt<8>, + flow: Duplex, + }, + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 32, + len: 8, + }, + name: "[4]", + ty: UInt<8>, + flow: Duplex, + }, + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 40, + len: 8, + }, + name: "[5]", + ty: UInt<8>, + flow: Duplex, + }, + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 48, + len: 8, + }, + name: "[6]", + ty: UInt<8>, + flow: Duplex, + }, + TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 8, + stride: 64, + start: 56, + len: 8, + }, + name: "[7]", + ty: UInt<8>, + flow: Duplex, + }, + ], + ty: Array, 8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(30), + name: "addr", + ty: UInt<3>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(31), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(32), + name: "clk", + flow: Sink, + }, + TraceArray { + name: "data", + elements: [ + TraceUInt { + location: TraceScalarId(33), + name: "[0]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(34), + name: "[1]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(35), + name: "[2]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(36), + name: "[3]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(37), + name: "[4]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(38), + name: "[5]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(39), + name: "[6]", + ty: UInt<8>, + flow: Source, + }, + TraceUInt { + location: TraceScalarId(40), + name: "[7]", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Array, 8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + data: Array, 8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + #[hdl(flip)] /* offset = 5 */ + data: Array, 8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(41), + name: "addr", + ty: UInt<3>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(42), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(43), + name: "clk", + flow: Sink, + }, + TraceArray { + name: "data", + elements: [ + TraceUInt { + location: TraceScalarId(44), + name: "[0]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(45), + name: "[1]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(46), + name: "[2]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(47), + name: "[3]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(48), + name: "[4]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(49), + name: "[5]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(50), + name: "[6]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(51), + name: "[7]", + ty: UInt<8>, + flow: Sink, + }, + ], + ty: Array, 8>, + flow: Sink, + }, + TraceArray { + name: "mask", + elements: [ + TraceBool { + location: TraceScalarId(52), + name: "[0]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(53), + name: "[1]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(54), + name: "[2]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(55), + name: "[3]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(56), + name: "[4]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(57), + name: "[5]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(58), + name: "[6]", + flow: Sink, + }, + TraceBool { + location: TraceScalarId(59), + name: "[7]", + flow: Sink, + }, + ], + ty: Array, + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + /* offset = 5 */ + data: Array, 8>, + /* offset = 69 */ + mask: Array, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<3>, + /* offset = 3 */ + en: Bool, + /* offset = 4 */ + clk: Clock, + /* offset = 5 */ + data: Array, 8>, + /* offset = 69 */ + mask: Array, + }, + }, + ], + array_type: Array, 8>, 8>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + instant: 15 μs, + clocks_triggered: [ + StatePartIndex(1), + StatePartIndex(6), + ], + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories3.vcd b/crates/fayalite/tests/sim/expected/memories3.vcd new file mode 100644 index 0000000..328fcaa --- /dev/null +++ b/crates/fayalite/tests/sim/expected/memories3.vcd @@ -0,0 +1,836 @@ +$timescale 1 ps $end +$scope module memories3 $end +$scope struct r $end +$var wire 3 ! addr $end +$var wire 1 " en $end +$var wire 1 # clk $end +$scope struct data $end +$var wire 8 $ \[0] $end +$var wire 8 % \[1] $end +$var wire 8 & \[2] $end +$var wire 8 ' \[3] $end +$var wire 8 ( \[4] $end +$var wire 8 ) \[5] $end +$var wire 8 * \[6] $end +$var wire 8 + \[7] $end +$upscope $end +$upscope $end +$scope struct w $end +$var wire 3 , addr $end +$var wire 1 - en $end +$var wire 1 . clk $end +$scope struct data $end +$var wire 8 / \[0] $end +$var wire 8 0 \[1] $end +$var wire 8 1 \[2] $end +$var wire 8 2 \[3] $end +$var wire 8 3 \[4] $end +$var wire 8 4 \[5] $end +$var wire 8 5 \[6] $end +$var wire 8 6 \[7] $end +$upscope $end +$scope struct mask $end +$var wire 1 7 \[0] $end +$var wire 1 8 \[1] $end +$var wire 1 9 \[2] $end +$var wire 1 : \[3] $end +$var wire 1 ; \[4] $end +$var wire 1 < \[5] $end +$var wire 1 = \[6] $end +$var wire 1 > \[7] $end +$upscope $end +$upscope $end +$scope struct mem $end +$scope struct contents $end +$scope struct [0] $end +$scope struct mem $end +$var reg 8 ] \[0] $end +$var reg 8 e \[1] $end +$var reg 8 m \[2] $end +$var reg 8 u \[3] $end +$var reg 8 } \[4] $end +$var reg 8 '" \[5] $end +$var reg 8 /" \[6] $end +$var reg 8 7" \[7] $end +$upscope $end +$upscope $end +$scope struct [1] $end +$scope struct mem $end +$var reg 8 ^ \[0] $end +$var reg 8 f \[1] $end +$var reg 8 n \[2] $end +$var reg 8 v \[3] $end +$var reg 8 ~ \[4] $end +$var reg 8 (" \[5] $end +$var reg 8 0" \[6] $end +$var reg 8 8" \[7] $end +$upscope $end +$upscope $end +$scope struct [2] $end +$scope struct mem $end +$var reg 8 _ \[0] $end +$var reg 8 g \[1] $end +$var reg 8 o \[2] $end +$var reg 8 w \[3] $end +$var reg 8 !" \[4] $end +$var reg 8 )" \[5] $end +$var reg 8 1" \[6] $end +$var reg 8 9" \[7] $end +$upscope $end +$upscope $end +$scope struct [3] $end +$scope struct mem $end +$var reg 8 ` \[0] $end +$var reg 8 h \[1] $end +$var reg 8 p \[2] $end +$var reg 8 x \[3] $end +$var reg 8 "" \[4] $end +$var reg 8 *" \[5] $end +$var reg 8 2" \[6] $end +$var reg 8 :" \[7] $end +$upscope $end +$upscope $end +$scope struct [4] $end +$scope struct mem $end +$var reg 8 a \[0] $end +$var reg 8 i \[1] $end +$var reg 8 q \[2] $end +$var reg 8 y \[3] $end +$var reg 8 #" \[4] $end +$var reg 8 +" \[5] $end +$var reg 8 3" \[6] $end +$var reg 8 ;" \[7] $end +$upscope $end +$upscope $end +$scope struct [5] $end +$scope struct mem $end +$var reg 8 b \[0] $end +$var reg 8 j \[1] $end +$var reg 8 r \[2] $end +$var reg 8 z \[3] $end +$var reg 8 $" \[4] $end +$var reg 8 ," \[5] $end +$var reg 8 4" \[6] $end +$var reg 8 <" \[7] $end +$upscope $end +$upscope $end +$scope struct [6] $end +$scope struct mem $end +$var reg 8 c \[0] $end +$var reg 8 k \[1] $end +$var reg 8 s \[2] $end +$var reg 8 { \[3] $end +$var reg 8 %" \[4] $end +$var reg 8 -" \[5] $end +$var reg 8 5" \[6] $end +$var reg 8 =" \[7] $end +$upscope $end +$upscope $end +$scope struct [7] $end +$scope struct mem $end +$var reg 8 d \[0] $end +$var reg 8 l \[1] $end +$var reg 8 t \[2] $end +$var reg 8 | \[3] $end +$var reg 8 &" \[4] $end +$var reg 8 ." \[5] $end +$var reg 8 6" \[6] $end +$var reg 8 >" \[7] $end +$upscope $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 3 ? addr $end +$var wire 1 @ en $end +$var wire 1 A clk $end +$scope struct data $end +$var wire 8 B \[0] $end +$var wire 8 C \[1] $end +$var wire 8 D \[2] $end +$var wire 8 E \[3] $end +$var wire 8 F \[4] $end +$var wire 8 G \[5] $end +$var wire 8 H \[6] $end +$var wire 8 I \[7] $end +$upscope $end +$upscope $end +$scope struct w1 $end +$var wire 3 J addr $end +$var wire 1 K en $end +$var wire 1 L clk $end +$scope struct data $end +$var wire 8 M \[0] $end +$var wire 8 N \[1] $end +$var wire 8 O \[2] $end +$var wire 8 P \[3] $end +$var wire 8 Q \[4] $end +$var wire 8 R \[5] $end +$var wire 8 S \[6] $end +$var wire 8 T \[7] $end +$upscope $end +$scope struct mask $end +$var wire 1 U \[0] $end +$var wire 1 V \[1] $end +$var wire 1 W \[2] $end +$var wire 1 X \[3] $end +$var wire 1 Y \[4] $end +$var wire 1 Z \[5] $end +$var wire 1 [ \[6] $end +$var wire 1 \ \[7] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +b0 ] +b0 e +b0 m +b0 u +b0 } +b0 '" +b0 /" +b0 7" +b0 ^ +b0 f +b0 n +b0 v +b0 ~ +b0 (" +b0 0" +b0 8" +b0 _ +b0 g +b0 o +b0 w +b0 !" +b0 )" +b0 1" +b0 9" +b0 ` +b0 h +b0 p +b0 x +b0 "" +b0 *" +b0 2" +b0 :" +b0 a +b0 i +b0 q +b0 y +b0 #" +b0 +" +b0 3" +b0 ;" +b0 b +b0 j +b0 r +b0 z +b0 $" +b0 ," +b0 4" +b0 <" +b0 c +b0 k +b0 s +b0 { +b0 %" +b0 -" +b0 5" +b0 =" +b0 d +b0 l +b0 t +b0 | +b0 &" +b0 ." +b0 6" +b0 >" +b0 ! +0" +0# +b0 $ +b0 % +b0 & +b0 ' +b0 ( +b0 ) +b0 * +b0 + +b0 , +1- +0. +b10010 / +b110100 0 +b1010110 1 +b1111000 2 +b10011010 3 +b10111100 4 +b11011110 5 +b11110000 6 +07 +18 +09 +1: +1; +0< +0= +1> +b0 ? +0@ +0A +b0 B +b0 C +b0 D +b0 E +b0 F +b0 G +b0 H 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+ +#3500000 +#3750000 +0# +0. +0A +0L +#4000000 +#4250000 +b11111110 ] +b11011100 e +b10111010 m +b10011000 u +b1110110 } +b1010100 '" +b110010 /" +b10000 7" +1# +1. +1A +1L +#4500000 +#4750000 +0# +0. +0A +0L +#5000000 +#5250000 +b11111110 ] +b11011100 e +b10111010 m +b10011000 u +b1110110 } +b1010100 '" +b110010 /" +b10000 7" +1# +1. +1A +1L +#5500000 +#5750000 +0# +0. +0A +0L +#6000000 +0" +b1 , +b10011 / +b1010111 0 +b10011011 1 +b11011111 2 +b10 3 +b1000110 4 +b10001010 5 +b11001110 6 +0@ +b1 J +b10011 M +b1010111 N +b10011011 O +b11011111 P +b10 Q +b1000110 R +b10001010 S +b11001110 T +#6250000 +b11111110 ] +b11011100 e +b10111010 m +b10011000 u +b1110110 } +b1010100 '" +b110010 /" +b10000 7" +1# +1. +1A +b11111110 B +b11011100 C +b10111010 D +b10011000 E +b1110110 F +b1010100 G +b110010 H +b10000 I +1L +b11111110 $ +b11011100 % +b10111010 & +b10011000 ' +b1110110 ( +b1010100 ) +b110010 * +b10000 + +#6500000 +#6750000 +0# +0. +0A +0L +#7000000 +b10 , +b1110100 / +b1100101 0 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