From 259bee39c226bdcdbfd5cb0d5456272062b1b21d Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 5 Dec 2024 18:15:38 -0800 Subject: [PATCH] tests/sim: split expected output text into separate files --- crates/fayalite/tests/sim.rs | 3523 +---------------- .../tests/sim/expected/connect_const.txt | 130 + .../sim/expected/connect_const_reset.txt | 217 + .../sim/expected/connect_const_reset.vcd | 11 + .../tests/sim/expected/counter_async.txt | 509 +++ .../tests/sim/expected/counter_async.vcd | 217 + .../tests/sim/expected/counter_sync.txt | 490 +++ .../tests/sim/expected/counter_sync.vcd | 214 + crates/fayalite/tests/sim/expected/mod1.txt | 798 ++++ crates/fayalite/tests/sim/expected/mod1.vcd | 47 + .../tests/sim/expected/shift_register.txt | 670 ++++ .../tests/sim/expected/shift_register.vcd | 193 + scripts/check-copyright.sh | 2 +- 13 files changed, 3508 insertions(+), 3513 deletions(-) create mode 100644 crates/fayalite/tests/sim/expected/connect_const.txt create mode 100644 crates/fayalite/tests/sim/expected/connect_const_reset.txt create mode 100644 crates/fayalite/tests/sim/expected/connect_const_reset.vcd create mode 100644 crates/fayalite/tests/sim/expected/counter_async.txt create mode 100644 crates/fayalite/tests/sim/expected/counter_async.vcd create mode 100644 crates/fayalite/tests/sim/expected/counter_sync.txt create mode 100644 crates/fayalite/tests/sim/expected/counter_sync.vcd create mode 100644 crates/fayalite/tests/sim/expected/mod1.txt create mode 100644 crates/fayalite/tests/sim/expected/mod1.vcd create mode 100644 crates/fayalite/tests/sim/expected/shift_register.txt create mode 100644 crates/fayalite/tests/sim/expected/shift_register.vcd diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index c837927..e65064d 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -22,137 +22,7 @@ fn test_connect_const() { sim.settle(); let sim_debug = format!("{sim:#?}"); println!("#######\n{sim_debug}\n#######"); - if sim_debug - != r#"Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(connect_const: connect_const).connect_const::o", - ty: UInt<8>, - }, - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:1:1 - Const { - dest: StatePartIndex(1), // SlotDebugData { name: "", ty: UInt<8> }, - value: 5, - }, - // at: module-XXXXXXXXXX.rs:3:1 - Copy { - dest: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> }, - src: StatePartIndex(1), // SlotDebugData { name: "", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - Return, - ], - .. - }, - pc: 2, - small_slots: StatePart { - value: [], - }, - big_slots: StatePart { - value: [ - 5, - 5, - ], - }, - }, - io: Instance { - name: ::connect_const, - instantiated: Module { - name: connect_const, - .. - }, - }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::connect_const, - instantiated: Module { - name: connect_const, - .. - }, - }.o: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(connect_const: connect_const).connect_const::o", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, - }, - }, - made_initial_step: true, - needs_settle: false, - trace_decls: TraceModule { - name: "connect_const", - children: [ - TraceModuleIO { - name: "o", - child: TraceUInt { - id: TraceScalarId(0), - name: "o", - ty: UInt<8>, - flow: Sink, - }, - ty: UInt<8>, - flow: Sink, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigUInt { - index: StatePartIndex(0), - ty: UInt<8>, - }, - state: 0x05, - last_state: 0x05, - }, - ], - trace_writers: [], - instant: 0 s, - clocks_triggered: [], -}"# { + if sim_debug != include_str!("sim/expected/connect_const.txt") { panic!(); } assert_eq!(sim.read_bool_or_int(sim.io().o), UIntValue::from(5u8)); @@ -179,241 +49,12 @@ fn test_connect_const_reset() { sim.flush_traces().unwrap(); let vcd = String::from_utf8(writer.take()).unwrap(); println!("####### VCD:\n{vcd}\n#######"); - if vcd - != r#"$timescale 1 ps $end -$scope module connect_const_reset $end -$var wire 1 ! reset_out $end -$var wire 1 " bit_out $end -$upscope $end -$enddefinitions $end -$dumpvars -1! -1" -$end -#1000000 -"# { + if vcd != include_str!("sim/expected/connect_const_reset.vcd") { panic!(); } let sim_debug = format!("{sim:#?}"); println!("#######\n{sim_debug}\n#######"); - if sim_debug - != r#"Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 5, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", - ty: AsyncReset, - }, - SlotDebugData { - name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: AsyncReset, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:1:1 - Const { - dest: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - value: 1, - }, - Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "", ty: AsyncReset }, - src: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - Copy { - dest: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset }, - src: StatePartIndex(3), // SlotDebugData { name: "", ty: AsyncReset }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - Copy { - dest: StatePartIndex(4), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset }, - }, - // at: module-XXXXXXXXXX.rs:5:1 - Copy { - dest: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool }, - src: StatePartIndex(4), // SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - Return, - ], - .. - }, - pc: 5, - small_slots: StatePart { - value: [], - }, - big_slots: StatePart { - value: [ - 1, - 1, - 1, - 1, - 1, - ], - }, - }, - io: Instance { - name: ::connect_const_reset, - instantiated: Module { - name: connect_const_reset, - .. - }, - }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::connect_const_reset, - instantiated: Module { - name: connect_const_reset, - .. - }, - }.bit_out: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - Instance { - name: ::connect_const_reset, - instantiated: Module { - name: connect_const_reset, - .. - }, - }.reset_out: CompiledValue { - layout: CompiledTypeLayout { - ty: AsyncReset, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", - ty: AsyncReset, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, - }, - }, - made_initial_step: true, - needs_settle: false, - trace_decls: TraceModule { - name: "connect_const_reset", - children: [ - TraceModuleIO { - name: "reset_out", - child: TraceAsyncReset { - id: TraceScalarId(0), - name: "reset_out", - flow: Sink, - }, - ty: AsyncReset, - flow: Sink, - }, - TraceModuleIO { - name: "bit_out", - child: TraceBool { - id: TraceScalarId(1), - name: "bit_out", - flow: Sink, - }, - ty: Bool, - flow: Sink, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigAsyncReset { - index: StatePartIndex(0), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigBool { - index: StatePartIndex(1), - }, - state: 0x1, - last_state: 0x1, - }, - ], - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - instant: 1 μs, - clocks_triggered: [], -}"# { + if sim_debug != include_str!("sim/expected/connect_const_reset.txt") { panic!(); } assert_eq!(sim.read_bool_or_int(sim.io().bit_out), true); @@ -461,858 +102,12 @@ fn test_mod1() { sim.flush_traces().unwrap(); let vcd = String::from_utf8(writer.take()).unwrap(); println!("####### VCD:\n{vcd}\n#######"); - if vcd - != r#"$timescale 1 ps $end -$scope module mod1 $end -$scope struct o $end -$var wire 4 ! i $end -$var wire 2 " o $end -$var wire 2 # i2 $end -$var wire 4 $ o2 $end -$upscope $end -$scope struct child $end -$var wire 4 ) i $end -$var wire 2 * o $end -$var wire 2 + i2 $end -$var wire 4 , o2 $end -$upscope $end -$scope module mod1_child $end -$var wire 4 % i $end -$var wire 2 & o $end -$var wire 2 ' i2 $end -$var wire 4 ( o2 $end -$upscope $end -$upscope $end -$enddefinitions $end -$dumpvars -b11 ! -b11 " -b10 # -b1110 $ -b11 % -b11 & -b10 ' -b1110 ( -b11 ) -b11 * -b10 + -b1110 , -$end -#1000000 -b1010 ! -b10 " -b1111 $ -b1010 % -b10 & -b1111 ( -b1010 ) -b10 * -b1111 , -#2000000 -"# { + if vcd != include_str!("sim/expected/mod1.vcd") { panic!(); } let sim_debug = format!("{sim:#?}"); println!("#######\n{sim_debug}\n#######"); - if sim_debug - != r#"Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 17, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::o.i", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::o.o", - ty: SInt<2>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::o.i2", - ty: SInt<2>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::o.o2", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::child.i", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::child.o", - ty: SInt<2>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::child.i2", - ty: SInt<2>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::child.o2", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", - ty: SInt<2>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", - ty: SInt<2>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: SInt<2>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - ], - .. - }, - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:4:1 - Copy { - dest: StatePartIndex(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> }, - src: StatePartIndex(2), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> }, - }, - Copy { - dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> }, - src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:2:1 - Copy { - dest: StatePartIndex(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> }, - src: StatePartIndex(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> }, - }, - Copy { - dest: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> }, - src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX-2.rs:1:1 - Const { - dest: StatePartIndex(16), // SlotDebugData { name: "", ty: UInt<4> }, - value: 15, - }, - Const { - dest: StatePartIndex(14), // SlotDebugData { name: "", ty: UInt<4> }, - value: 5, - }, - CmpLt { - dest: StatePartIndex(15), // SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(14), // SlotDebugData { name: "", ty: UInt<4> }, - rhs: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> }, - }, - CastToUInt { - dest: StatePartIndex(13), // SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> }, - dest_width: 4, - }, - // at: module-XXXXXXXXXX-2.rs:7:1 - Copy { - dest: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> }, - src: StatePartIndex(13), // SlotDebugData { name: "", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX-2.rs:8:1 - BranchIfZero { - target: 11, - value: StatePartIndex(15), // SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX-2.rs:9:1 - Copy { - dest: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> }, - src: StatePartIndex(16), // SlotDebugData { name: "", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:2:1 - Copy { - dest: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> }, - src: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> }, - src: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX-2.rs:1:1 - CastToSInt { - dest: StatePartIndex(12), // SlotDebugData { name: "", ty: SInt<2> }, - src: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> }, - dest_width: 2, - }, - // at: module-XXXXXXXXXX-2.rs:6:1 - Copy { - dest: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> }, - src: StatePartIndex(12), // SlotDebugData { name: "", ty: SInt<2> }, - }, - // at: module-XXXXXXXXXX.rs:2:1 - Copy { - dest: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> }, - src: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - Copy { - dest: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> }, - src: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - Return, - ], - .. - }, - pc: 17, - small_slots: StatePart { - value: [], - }, - big_slots: StatePart { - value: [ - 10, - -2, - -2, - 15, - 10, - -2, - -2, - 15, - 10, - -2, - -2, - 15, - -2, - 14, - 5, - 1, - 15, - ], - }, - }, - io: Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. - }, - }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. - }, - }.o: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - #[hdl(flip)] /* offset = 0 */ - i: UInt<4>, - /* offset = 4 */ - o: SInt<2>, - #[hdl(flip)] /* offset = 6 */ - i2: SInt<2>, - /* offset = 8 */ - o2: UInt<4>, - }, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 4, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::o.i", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::o.o", - ty: SInt<2>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::o.i2", - ty: SInt<2>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::o.o2", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: SInt<2>, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SInt<2>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(2), - }, - ty: CompiledTypeLayout { - ty: SInt<2>, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SInt<2>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(3), - }, - ty: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 4 }, - }, - write: None, - }, - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. - }, - }.o.i: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, - }, - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. - }, - }.o.i2: CompiledValue { - layout: CompiledTypeLayout { - ty: SInt<2>, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SInt<2>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 2, len: 1 }, - }, - write: None, - }, - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. - }, - }.o.o: CompiledValue { - layout: CompiledTypeLayout { - ty: SInt<2>, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SInt<2>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. - }, - }.o.o2: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 3, len: 1 }, - }, - write: None, - }, - }, - made_initial_step: true, - needs_settle: false, - trace_decls: TraceModule { - name: "mod1", - children: [ - TraceModuleIO { - name: "o", - child: TraceBundle { - name: "o", - fields: [ - TraceUInt { - id: TraceScalarId(0), - name: "i", - ty: UInt<4>, - flow: Source, - }, - TraceSInt { - id: TraceScalarId(1), - name: "o", - ty: SInt<2>, - flow: Sink, - }, - TraceSInt { - id: TraceScalarId(2), - name: "i2", - ty: SInt<2>, - flow: Source, - }, - TraceUInt { - id: TraceScalarId(3), - name: "o2", - ty: UInt<4>, - flow: Sink, - }, - ], - ty: Bundle { - #[hdl(flip)] /* offset = 0 */ - i: UInt<4>, - /* offset = 4 */ - o: SInt<2>, - #[hdl(flip)] /* offset = 6 */ - i2: SInt<2>, - /* offset = 8 */ - o2: UInt<4>, - }, - flow: Sink, - }, - ty: Bundle { - #[hdl(flip)] /* offset = 0 */ - i: UInt<4>, - /* offset = 4 */ - o: SInt<2>, - #[hdl(flip)] /* offset = 6 */ - i2: SInt<2>, - /* offset = 8 */ - o2: UInt<4>, - }, - flow: Sink, - }, - TraceInstance { - name: "child", - instance_io: TraceBundle { - name: "child", - fields: [ - TraceUInt { - id: TraceScalarId(8), - name: "i", - ty: UInt<4>, - flow: Sink, - }, - TraceSInt { - id: TraceScalarId(9), - name: "o", - ty: SInt<2>, - flow: Source, - }, - TraceSInt { - id: TraceScalarId(10), - name: "i2", - ty: SInt<2>, - flow: Sink, - }, - TraceUInt { - id: TraceScalarId(11), - name: "o2", - ty: UInt<4>, - flow: Source, - }, - ], - ty: Bundle { - #[hdl(flip)] /* offset = 0 */ - i: UInt<4>, - /* offset = 4 */ - o: SInt<2>, - #[hdl(flip)] /* offset = 6 */ - i2: SInt<2>, - /* offset = 8 */ - o2: UInt<4>, - }, - flow: Source, - }, - module: TraceModule { - name: "mod1_child", - children: [ - TraceModuleIO { - name: "i", - child: TraceUInt { - id: TraceScalarId(4), - name: "i", - ty: UInt<4>, - flow: Source, - }, - ty: UInt<4>, - flow: Source, - }, - TraceModuleIO { - name: "o", - child: TraceSInt { - id: TraceScalarId(5), - name: "o", - ty: SInt<2>, - flow: Sink, - }, - ty: SInt<2>, - flow: Sink, - }, - TraceModuleIO { - name: "i2", - child: TraceSInt { - id: TraceScalarId(6), - name: "i2", - ty: SInt<2>, - flow: Source, - }, - ty: SInt<2>, - flow: Source, - }, - TraceModuleIO { - name: "o2", - child: TraceUInt { - id: TraceScalarId(7), - name: "o2", - ty: UInt<4>, - flow: Sink, - }, - ty: UInt<4>, - flow: Sink, - }, - ], - }, - ty: Bundle { - #[hdl(flip)] /* offset = 0 */ - i: UInt<4>, - /* offset = 4 */ - o: SInt<2>, - #[hdl(flip)] /* offset = 6 */ - i2: SInt<2>, - /* offset = 8 */ - o2: UInt<4>, - }, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigUInt { - index: StatePartIndex(0), - ty: UInt<4>, - }, - state: 0xa, - last_state: 0x3, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigSInt { - index: StatePartIndex(1), - ty: SInt<2>, - }, - state: 0x2, - last_state: 0x3, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigSInt { - index: StatePartIndex(2), - ty: SInt<2>, - }, - state: 0x2, - last_state: 0x2, - }, - SimTrace { - id: TraceScalarId(3), - kind: BigUInt { - index: StatePartIndex(3), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xe, - }, - SimTrace { - id: TraceScalarId(4), - kind: BigUInt { - index: StatePartIndex(8), - ty: UInt<4>, - }, - state: 0xa, - last_state: 0x3, - }, - SimTrace { - id: TraceScalarId(5), - kind: BigSInt { - index: StatePartIndex(9), - ty: SInt<2>, - }, - state: 0x2, - last_state: 0x3, - }, - SimTrace { - id: TraceScalarId(6), - kind: BigSInt { - index: StatePartIndex(10), - ty: SInt<2>, - }, - state: 0x2, - last_state: 0x2, - }, - SimTrace { - id: TraceScalarId(7), - kind: BigUInt { - index: StatePartIndex(11), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xe, - }, - SimTrace { - id: TraceScalarId(8), - kind: BigUInt { - index: StatePartIndex(4), - ty: UInt<4>, - }, - state: 0xa, - last_state: 0x3, - }, - SimTrace { - id: TraceScalarId(9), - kind: BigSInt { - index: StatePartIndex(5), - ty: SInt<2>, - }, - state: 0x2, - last_state: 0x3, - }, - SimTrace { - id: TraceScalarId(10), - kind: BigSInt { - index: StatePartIndex(6), - ty: SInt<2>, - }, - state: 0x2, - last_state: 0x2, - }, - SimTrace { - id: TraceScalarId(11), - kind: BigUInt { - index: StatePartIndex(7), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xe, - }, - ], - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - instant: 2 μs, - clocks_triggered: [], -}"# { + if sim_debug != include_str!("sim/expected/mod1.txt") { panic!(); } let expected = -2_hdl_i2; @@ -1369,717 +164,12 @@ fn test_counter_sync() { sim.flush_traces().unwrap(); let vcd = String::from_utf8(writer.take()).unwrap(); println!("####### VCD:\n{vcd}\n#######"); - if vcd - != r#"$timescale 1 ps $end -$scope module counter $end -$scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end -$upscope $end -$var wire 4 # count $end -$var reg 4 $ count_reg $end -$upscope $end -$enddefinitions $end -$dumpvars -0! -1" -b0 # -b0 $ -$end -#1000000 -1! -b11 $ -b11 # -0" -#2000000 -0! -#3000000 -1! -b100 $ -b100 # -#4000000 -0! -#5000000 -1! -b101 $ -b101 # -#6000000 -0! -#7000000 -1! -b110 $ -b110 # -#8000000 -0! -#9000000 -1! -b111 $ -b111 # -#10000000 -0! -#11000000 -1! -b1000 $ -b1000 # -#12000000 -0! -#13000000 -1! -b1001 $ -b1001 # -#14000000 -0! -#15000000 -1! -b1010 $ -b1010 # -#16000000 -0! -#17000000 -1! -b1011 $ -b1011 # -#18000000 -0! -#19000000 -1! -b1100 $ -b1100 # -#20000000 -0! -#21000000 -1! -b1101 $ -b1101 # -#22000000 -0! -#23000000 -1! -b1110 $ -b1110 # -#24000000 -0! -#25000000 -1! -b1111 $ -b1111 # -#26000000 -0! -#27000000 -1! -b0 $ -b0 # -#28000000 -0! -#29000000 -1! -b1 $ -b1 # -#30000000 -0! -#31000000 -1! -b10 $ -b10 # -#32000000 -0! -#33000000 -1! -b11 $ -b11 # -#34000000 -0! -#35000000 -1! -b100 $ -b100 # -#36000000 -0! -#37000000 -1! -b101 $ -b101 # -#38000000 -0! -#39000000 -1! -b110 $ -b110 # -#40000000 -0! -#41000000 -1! -b111 $ -b111 # -#42000000 -0! -#43000000 -1! -b1000 $ -b1000 # -#44000000 -0! -#45000000 -1! -b1001 $ -b1001 # -#46000000 -0! -#47000000 -1! -b1010 $ -b1010 # -#48000000 -0! -#49000000 -1! -b1011 $ -b1011 # -#50000000 -0! -#51000000 -1! -b1100 $ -b1100 # -#52000000 -0! -#53000000 -1! -b1101 $ -b1101 # -#54000000 -0! -#55000000 -1! -b1110 $ -b1110 # -#56000000 -0! -#57000000 -1! -b1111 $ -b1111 # -#58000000 -0! -#59000000 -1! -b0 $ -b0 # -#60000000 -0! -#61000000 -1! -b1 $ -b1 # -#62000000 -0! -#63000000 -1! -b10 $ -b10 # -#64000000 -0! -#65000000 -1! -b11 $ -b11 # -#66000000 -"# { + if vcd != include_str!("sim/expected/counter_sync.vcd") { panic!(); } let sim_debug = format!("{sim:#?}"); println!("#######\n{sim_debug}\n#######"); - if sim_debug - != r#"Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 4, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - big_slots: StatePartAllocationLayout { - len: 9, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::cd.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::cd.rst", - ty: SyncReset, - }, - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::count", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::count_reg", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::count_reg$next", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: UInt<1>, - }, - SlotDebugData { - name: "", - ty: UInt<5>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - ], - .. - }, - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:6:1 - Copy { - dest: StatePartIndex(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> }, - src: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - Const { - dest: StatePartIndex(6), // SlotDebugData { name: "", ty: UInt<1> }, - value: 1, - }, - Add { - dest: StatePartIndex(7), // SlotDebugData { name: "", ty: UInt<5> }, - lhs: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - rhs: StatePartIndex(6), // SlotDebugData { name: "", ty: UInt<1> }, - }, - CastToUInt { - dest: StatePartIndex(8), // SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(7), // SlotDebugData { name: "", ty: UInt<5> }, - dest_width: 4, - }, - // at: module-XXXXXXXXXX.rs:4:1 - Copy { - dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, - src: StatePartIndex(8), // SlotDebugData { name: "", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:3:1 - IsNonZeroDestIsSmall { - dest: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - Const { - dest: StatePartIndex(5), // SlotDebugData { name: "", ty: UInt<4> }, - value: 3, - }, - // at: module-XXXXXXXXXX.rs:3:1 - IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, - }, - AndSmall { - dest: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, - }, - BranchIfSmallZero { - target: 14, - value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, - }, - BranchIfSmallNonZero { - target: 13, - value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, - }, - Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, - }, - Branch { - target: 14, - }, - Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - src: StatePartIndex(5), // SlotDebugData { name: "", ty: UInt<4> }, - }, - NotSmall { - dest: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - Return, - ], - .. - }, - pc: 15, - small_slots: StatePart { - value: [ - 18446744073709551614, - 0, - 1, - 0, - ], - }, - big_slots: StatePart { - value: [ - 1, - 0, - 3, - 3, - 4, - 3, - 1, - 4, - 4, - ], - }, - }, - io: Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::cd.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::cd.rst", - ty: SyncReset, - }, - ], - .. - }, - }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: SyncReset, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SyncReset, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 2 }, - }, - write: None, - }, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd.clk: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, - }, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd.rst: CompiledValue { - layout: CompiledTypeLayout { - ty: SyncReset, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SyncReset, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.count: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::count", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 2, len: 1 }, - }, - write: None, - }, - }, - made_initial_step: true, - needs_settle: false, - trace_decls: TraceModule { - name: "counter", - children: [ - TraceModuleIO { - name: "cd", - child: TraceBundle { - name: "cd", - fields: [ - TraceClock { - id: TraceScalarId(0), - name: "clk", - flow: Source, - }, - TraceSyncReset { - id: TraceScalarId(1), - name: "rst", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - flow: Source, - }, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - flow: Source, - }, - TraceModuleIO { - name: "count", - child: TraceUInt { - id: TraceScalarId(2), - name: "count", - ty: UInt<4>, - flow: Sink, - }, - ty: UInt<4>, - flow: Sink, - }, - TraceReg { - name: "count_reg", - child: TraceUInt { - id: TraceScalarId(3), - name: "count_reg", - ty: UInt<4>, - flow: Duplex, - }, - ty: UInt<4>, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigClock { - index: StatePartIndex(0), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigSyncReset { - index: StatePartIndex(1), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigUInt { - index: StatePartIndex(2), - ty: UInt<4>, - }, - state: 0x3, - last_state: 0x2, - }, - SimTrace { - id: TraceScalarId(3), - kind: BigUInt { - index: StatePartIndex(3), - ty: UInt<4>, - }, - state: 0x3, - last_state: 0x3, - }, - ], - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - instant: 66 μs, - clocks_triggered: [ - StatePartIndex(1), - ], -}"# { + if sim_debug != include_str!("sim/expected/counter_sync.txt") { panic!(); } } @@ -2122,739 +212,12 @@ fn test_counter_async() { sim.flush_traces().unwrap(); let vcd = String::from_utf8(writer.take()).unwrap(); println!("####### VCD:\n{vcd}\n#######"); - if vcd - != r#"$timescale 1 ps $end -$scope module counter $end -$scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end -$upscope $end -$var wire 4 # count $end -$var reg 4 $ count_reg $end -$upscope $end -$enddefinitions $end -$dumpvars -0! -0" -b0 # -b0 $ -$end -#500000 -1" -b11 # -b11 $ -#1000000 -1! -#1500000 -0" -#2000000 -0! -#3000000 -1! -b100 $ -b100 # -#4000000 -0! -#5000000 -1! -b101 $ -b101 # -#6000000 -0! -#7000000 -1! -b110 $ -b110 # -#8000000 -0! -#9000000 -1! -b111 $ -b111 # -#10000000 -0! -#11000000 -1! -b1000 $ -b1000 # -#12000000 -0! -#13000000 -1! -b1001 $ -b1001 # -#14000000 -0! -#15000000 -1! -b1010 $ -b1010 # -#16000000 -0! -#17000000 -1! -b1011 $ -b1011 # -#18000000 -0! -#19000000 -1! -b1100 $ -b1100 # -#20000000 -0! -#21000000 -1! -b1101 $ -b1101 # -#22000000 -0! -#23000000 -1! -b1110 $ -b1110 # -#24000000 -0! -#25000000 -1! -b1111 $ -b1111 # -#26000000 -0! -#27000000 -1! -b0 $ -b0 # -#28000000 -0! -#29000000 -1! -b1 $ -b1 # -#30000000 -0! -#31000000 -1! -b10 $ -b10 # -#32000000 -0! -#33000000 -1! -b11 $ -b11 # -#34000000 -0! -#35000000 -1! -b100 $ -b100 # -#36000000 -0! -#37000000 -1! -b101 $ -b101 # -#38000000 -0! -#39000000 -1! -b110 $ -b110 # -#40000000 -0! -#41000000 -1! -b111 $ -b111 # -#42000000 -0! -#43000000 -1! -b1000 $ -b1000 # -#44000000 -0! -#45000000 -1! -b1001 $ -b1001 # -#46000000 -0! -#47000000 -1! -b1010 $ -b1010 # -#48000000 -0! -#49000000 -1! -b1011 $ -b1011 # -#50000000 -0! -#51000000 -1! -b1100 $ -b1100 # -#52000000 -0! -#53000000 -1! -b1101 $ -b1101 # -#54000000 -0! -#55000000 -1! -b1110 $ -b1110 # -#56000000 -0! -#57000000 -1! -b1111 $ -b1111 # -#58000000 -0! -#59000000 -1! -b0 $ -b0 # -#60000000 -0! -#61000000 -1! -b1 $ -b1 # -#62000000 -0! -#63000000 -1! -b10 $ -b10 # -#64000000 -0! -#65000000 -1! -b11 $ -b11 # -#66000000 -"# { + if vcd != include_str!("sim/expected/counter_async.vcd") { panic!(); } let sim_debug = format!("{sim:#?}"); println!("#######\n{sim_debug}\n#######"); - if sim_debug - != r#"Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 4, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - big_slots: StatePartAllocationLayout { - len: 10, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::cd.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::cd.rst", - ty: AsyncReset, - }, - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::count", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::count_reg", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::count_reg$next", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<1>, - }, - SlotDebugData { - name: "", - ty: UInt<5>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - ], - .. - }, - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:1:1 - Const { - dest: StatePartIndex(7), // SlotDebugData { name: "", ty: UInt<1> }, - value: 1, - }, - Copy { - dest: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset }, - }, - // at: module-XXXXXXXXXX.rs:3:1 - IsNonZeroDestIsSmall { - dest: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - Const { - dest: StatePartIndex(5), // SlotDebugData { name: "", ty: UInt<4> }, - value: 3, - }, - // at: module-XXXXXXXXXX.rs:3:1 - BranchIfZero { - target: 6, - value: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, - }, - Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - src: StatePartIndex(5), // SlotDebugData { name: "", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - Add { - dest: StatePartIndex(8), // SlotDebugData { name: "", ty: UInt<5> }, - lhs: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - rhs: StatePartIndex(7), // SlotDebugData { name: "", ty: UInt<1> }, - }, - CastToUInt { - dest: StatePartIndex(9), // SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(8), // SlotDebugData { name: "", ty: UInt<5> }, - dest_width: 4, - }, - // at: module-XXXXXXXXXX.rs:4:1 - Copy { - dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, - src: StatePartIndex(9), // SlotDebugData { name: "", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - Copy { - dest: StatePartIndex(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> }, - src: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:3:1 - IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, - }, - AndSmall { - dest: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, - }, - BranchIfSmallNonZero { - target: 16, - value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, - }, - BranchIfSmallZero { - target: 17, - value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, - }, - Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, - }, - Branch { - target: 17, - }, - Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, - src: StatePartIndex(5), // SlotDebugData { name: "", ty: UInt<4> }, - }, - NotSmall { - dest: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - Return, - ], - .. - }, - pc: 18, - small_slots: StatePart { - value: [ - 18446744073709551614, - 0, - 1, - 0, - ], - }, - big_slots: StatePart { - value: [ - 1, - 0, - 3, - 3, - 4, - 3, - 0, - 1, - 4, - 4, - ], - }, - }, - io: Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::cd.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::cd.rst", - ty: AsyncReset, - }, - ], - .. - }, - }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: AsyncReset, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: AsyncReset, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 2 }, - }, - write: None, - }, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd.clk: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, - }, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd.rst: CompiledValue { - layout: CompiledTypeLayout { - ty: AsyncReset, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: AsyncReset, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.count: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::count", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 2, len: 1 }, - }, - write: None, - }, - }, - made_initial_step: true, - needs_settle: false, - trace_decls: TraceModule { - name: "counter", - children: [ - TraceModuleIO { - name: "cd", - child: TraceBundle { - name: "cd", - fields: [ - TraceClock { - id: TraceScalarId(0), - name: "clk", - flow: Source, - }, - TraceAsyncReset { - id: TraceScalarId(1), - name: "rst", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - flow: Source, - }, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - flow: Source, - }, - TraceModuleIO { - name: "count", - child: TraceUInt { - id: TraceScalarId(2), - name: "count", - ty: UInt<4>, - flow: Sink, - }, - ty: UInt<4>, - flow: Sink, - }, - TraceReg { - name: "count_reg", - child: TraceUInt { - id: TraceScalarId(3), - name: "count_reg", - ty: UInt<4>, - flow: Duplex, - }, - ty: UInt<4>, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigClock { - index: StatePartIndex(0), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigAsyncReset { - index: StatePartIndex(1), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigUInt { - index: StatePartIndex(2), - ty: UInt<4>, - }, - state: 0x3, - last_state: 0x2, - }, - SimTrace { - id: TraceScalarId(3), - kind: BigUInt { - index: StatePartIndex(3), - ty: UInt<4>, - }, - state: 0x3, - last_state: 0x3, - }, - ], - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - instant: 66 μs, - clocks_triggered: [ - StatePartIndex(1), - ], -}"# { + if sim_debug != include_str!("sim/expected/counter_async.txt") { panic!(); } } @@ -2920,876 +283,12 @@ fn test_shift_register() { sim.flush_traces().unwrap(); let vcd = String::from_utf8(writer.take()).unwrap(); println!("####### VCD:\n{vcd}\n#######"); - if vcd - != r#"$timescale 1 ps $end -$scope module shift_register $end -$scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end -$upscope $end -$var wire 1 # d $end -$var wire 1 $ q $end -$var reg 1 % reg0 $end -$var reg 1 & reg1 $end -$var reg 1 ' reg2 $end -$var reg 1 ( reg3 $end -$upscope $end -$enddefinitions $end -$dumpvars -0! -1" -0# -0$ -0% -0& -0' -0( -$end -#1000000 -1! -#1100000 -0" -#2000000 -0! -#3000000 -1! -#4000000 -0! -1# -#5000000 -1! -1% -#6000000 -0! -#7000000 -1! -1& -#8000000 -0! -0# -#9000000 -1! -0% -1' -#10000000 -0! -#11000000 -1! -0& -1( -1$ -#12000000 -0! -1# -#13000000 -1! -1% -0' -#14000000 -0! -0# -#15000000 -1! -0% -1& -0( -0$ -#16000000 -0! -1# -#17000000 -1! -1% -0& -1' -#18000000 -0! -#19000000 -1! -1& -0' -1( -1$ -#20000000 -0! -#21000000 -1! -1' -0( -0$ -#22000000 -0! -#23000000 -1! -1( -1$ -#24000000 -0! -0# -#25000000 -1! -0% -#26000000 -0! -#27000000 -1! -0& -#28000000 -0! -#29000000 -1! -0' -#30000000 -0! -#31000000 -1! -0( -0$ -#32000000 -0! -#33000000 -1! -#34000000 -0! -#35000000 -1! -#36000000 -0! -#37000000 -1! -#38000000 -0! -#39000000 -1! -#40000000 -0! -#41000000 -1! -#42000000 -0! -#43000000 -1! -#44000000 -0! -#45000000 -1! -#46000000 -0! -#47000000 -1! -#48000000 -0! -#49000000 -1! -#50000000 -0! -#51000000 -1! -#52000000 -0! -#53000000 -1! -#54000000 -0! -#55000000 -1! -#56000000 -0! -#57000000 -1! -#58000000 -0! -#59000000 -1! -#60000000 -0! -#61000000 -1! -#62000000 -0! -#63000000 -1! -#64000000 -0! -#65000000 -1! -#66000000 -"# { + if vcd != include_str!("sim/expected/shift_register.vcd") { panic!(); } let sim_debug = format!("{sim:#?}"); println!("#######\n{sim_debug}\n#######"); - if sim_debug - != r#"Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 4, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - big_slots: StatePartAllocationLayout { - len: 13, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", - ty: SyncReset, - }, - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::d", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::q", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", - ty: Bool, - }, - ], - .. - }, - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:13:1 - Copy { - dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool }, - src: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:12:1 - Copy { - dest: StatePartIndex(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, - src: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:10:1 - Copy { - dest: StatePartIndex(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, - src: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:8:1 - Copy { - dest: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, - src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - Copy { - dest: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, - src: StatePartIndex(2), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:5:1 - IsNonZeroDestIsSmall { - dest: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - Const { - dest: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, - value: 0, - }, - // at: module-XXXXXXXXXX.rs:5:1 - IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock }, - }, - AndSmall { - dest: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, - }, - BranchIfSmallZero { - target: 14, - value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, - }, - BranchIfSmallNonZero { - target: 13, - value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, - }, - Copy { - dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, - src: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, - }, - Branch { - target: 14, - }, - Copy { - dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, - src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:7:1 - BranchIfSmallZero { - target: 19, - value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, - }, - BranchIfSmallNonZero { - target: 18, - value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, - }, - Copy { - dest: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, - src: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, - }, - Branch { - target: 19, - }, - Copy { - dest: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, - src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:9:1 - BranchIfSmallZero { - target: 24, - value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, - }, - BranchIfSmallNonZero { - target: 23, - value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, - }, - Copy { - dest: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, - src: StatePartIndex(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, - }, - Branch { - target: 24, - }, - Copy { - dest: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, - src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:11:1 - BranchIfSmallZero { - target: 29, - value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, - }, - BranchIfSmallNonZero { - target: 28, - value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, - }, - Copy { - dest: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, - src: StatePartIndex(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, - }, - Branch { - target: 29, - }, - Copy { - dest: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, - src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:5:1 - NotSmall { - dest: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - Return, - ], - .. - }, - pc: 30, - small_slots: StatePart { - value: [ - 18446744073709551614, - 0, - 1, - 0, - ], - }, - big_slots: StatePart { - value: [ - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - ], - }, - }, - io: Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }.cd: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", - ty: SyncReset, - }, - ], - .. - }, - }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: SyncReset, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SyncReset, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 2 }, - }, - write: None, - }, - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }.cd.clk: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, - }, - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }.cd.rst: CompiledValue { - layout: CompiledTypeLayout { - ty: SyncReset, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SyncReset, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }.d: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::d", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 2, len: 1 }, - }, - write: None, - }, - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }.q: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartAllocationLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartAllocationLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::q", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 3, len: 1 }, - }, - write: None, - }, - }, - made_initial_step: true, - needs_settle: false, - trace_decls: TraceModule { - name: "shift_register", - children: [ - TraceModuleIO { - name: "cd", - child: TraceBundle { - name: "cd", - fields: [ - TraceClock { - id: TraceScalarId(0), - name: "clk", - flow: Source, - }, - TraceSyncReset { - id: TraceScalarId(1), - name: "rst", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - flow: Source, - }, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - flow: Source, - }, - TraceModuleIO { - name: "d", - child: TraceBool { - id: TraceScalarId(2), - name: "d", - flow: Source, - }, - ty: Bool, - flow: Source, - }, - TraceModuleIO { - name: "q", - child: TraceBool { - id: TraceScalarId(3), - name: "q", - flow: Sink, - }, - ty: Bool, - flow: Sink, - }, - TraceReg { - name: "reg0", - child: TraceBool { - id: TraceScalarId(4), - name: "reg0", - flow: Duplex, - }, - ty: Bool, - }, - TraceReg { - name: "reg1", - child: TraceBool { - id: TraceScalarId(5), - name: "reg1", - flow: Duplex, - }, - ty: Bool, - }, - TraceReg { - name: "reg2", - child: TraceBool { - id: TraceScalarId(6), - name: "reg2", - flow: Duplex, - }, - ty: Bool, - }, - TraceReg { - name: "reg3", - child: TraceBool { - id: TraceScalarId(7), - name: "reg3", - flow: Duplex, - }, - ty: Bool, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigClock { - index: StatePartIndex(0), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigSyncReset { - index: StatePartIndex(1), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigBool { - index: StatePartIndex(2), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(3), - kind: BigBool { - index: StatePartIndex(3), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(4), - kind: BigBool { - index: StatePartIndex(4), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(5), - kind: BigBool { - index: StatePartIndex(7), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(6), - kind: BigBool { - index: StatePartIndex(9), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(7), - kind: BigBool { - index: StatePartIndex(11), - }, - state: 0x0, - last_state: 0x0, - }, - ], - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - instant: 66 μs, - clocks_triggered: [ - StatePartIndex(1), - ], -}"# { + if sim_debug != include_str!("sim/expected/shift_register.txt") { panic!(); } } diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt new file mode 100644 index 0000000..189056b --- /dev/null +++ b/crates/fayalite/tests/sim/expected/connect_const.txt @@ -0,0 +1,130 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(connect_const: connect_const).connect_const::o", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:1:1 + Const { + dest: StatePartIndex(1), // SlotDebugData { name: "", ty: UInt<8> }, + value: 5, + }, + // at: module-XXXXXXXXXX.rs:3:1 + Copy { + dest: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> }, + src: StatePartIndex(1), // SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + Return, + ], + .. + }, + pc: 2, + small_slots: StatePart { + value: [], + }, + big_slots: StatePart { + value: [ + 5, + 5, + ], + }, + }, + io: Instance { + name: ::connect_const, + instantiated: Module { + name: connect_const, + .. + }, + }, + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::connect_const, + instantiated: Module { + name: connect_const, + .. + }, + }.o: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(connect_const: connect_const).connect_const::o", + ty: UInt<8>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + }, + made_initial_step: true, + needs_settle: false, + trace_decls: TraceModule { + name: "connect_const", + children: [ + TraceModuleIO { + name: "o", + child: TraceUInt { + id: TraceScalarId(0), + name: "o", + ty: UInt<8>, + flow: Sink, + }, + ty: UInt<8>, + flow: Sink, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigUInt { + index: StatePartIndex(0), + ty: UInt<8>, + }, + state: 0x05, + last_state: 0x05, + }, + ], + trace_writers: [], + instant: 0 s, + clocks_triggered: [], +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt new file mode 100644 index 0000000..5e6f0eb --- /dev/null +++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt @@ -0,0 +1,217 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 5, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", + ty: AsyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: AsyncReset, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:1:1 + Const { + dest: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + value: 1, + }, + Copy { + dest: StatePartIndex(3), // SlotDebugData { name: "", ty: AsyncReset }, + src: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + Copy { + dest: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset }, + src: StatePartIndex(3), // SlotDebugData { name: "", ty: AsyncReset }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + Copy { + dest: StatePartIndex(4), // SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset }, + }, + // at: module-XXXXXXXXXX.rs:5:1 + Copy { + dest: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool }, + src: StatePartIndex(4), // SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + Return, + ], + .. + }, + pc: 5, + small_slots: StatePart { + value: [], + }, + big_slots: StatePart { + value: [ + 1, + 1, + 1, + 1, + 1, + ], + }, + }, + io: Instance { + name: ::connect_const_reset, + instantiated: Module { + name: connect_const_reset, + .. + }, + }, + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::connect_const_reset, + instantiated: Module { + name: connect_const_reset, + .. + }, + }.bit_out: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::connect_const_reset, + instantiated: Module { + name: connect_const_reset, + .. + }, + }.reset_out: CompiledValue { + layout: CompiledTypeLayout { + ty: AsyncReset, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", + ty: AsyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + }, + made_initial_step: true, + needs_settle: false, + trace_decls: TraceModule { + name: "connect_const_reset", + children: [ + TraceModuleIO { + name: "reset_out", + child: TraceAsyncReset { + id: TraceScalarId(0), + name: "reset_out", + flow: Sink, + }, + ty: AsyncReset, + flow: Sink, + }, + TraceModuleIO { + name: "bit_out", + child: TraceBool { + id: TraceScalarId(1), + name: "bit_out", + flow: Sink, + }, + ty: Bool, + flow: Sink, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigAsyncReset { + index: StatePartIndex(0), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigBool { + index: StatePartIndex(1), + }, + state: 0x1, + last_state: 0x1, + }, + ], + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + instant: 1 μs, + clocks_triggered: [], +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.vcd b/crates/fayalite/tests/sim/expected/connect_const_reset.vcd new file mode 100644 index 0000000..50b427c --- /dev/null +++ b/crates/fayalite/tests/sim/expected/connect_const_reset.vcd @@ -0,0 +1,11 @@ +$timescale 1 ps $end +$scope module connect_const_reset $end +$var wire 1 ! reset_out $end +$var wire 1 " bit_out $end +$upscope $end +$enddefinitions $end +$dumpvars +1! +1" +$end +#1000000 diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt new file mode 100644 index 0000000..b72ebbb --- /dev/null +++ b/crates/fayalite/tests/sim/expected/counter_async.txt @@ -0,0 +1,509 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 4, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartAllocationLayout { + len: 10, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::cd.rst", + ty: AsyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::count", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::count_reg", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::count_reg$next", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:1:1 + Const { + dest: StatePartIndex(7), // SlotDebugData { name: "", ty: UInt<1> }, + value: 1, + }, + Copy { + dest: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset }, + }, + // at: module-XXXXXXXXXX.rs:3:1 + IsNonZeroDestIsSmall { + dest: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + Const { + dest: StatePartIndex(5), // SlotDebugData { name: "", ty: UInt<4> }, + value: 3, + }, + // at: module-XXXXXXXXXX.rs:3:1 + BranchIfZero { + target: 6, + value: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, + }, + Copy { + dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + src: StatePartIndex(5), // SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + Add { + dest: StatePartIndex(8), // SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + rhs: StatePartIndex(7), // SlotDebugData { name: "", ty: UInt<1> }, + }, + CastToUInt { + dest: StatePartIndex(9), // SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(8), // SlotDebugData { name: "", ty: UInt<5> }, + dest_width: 4, + }, + // at: module-XXXXXXXXXX.rs:4:1 + Copy { + dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + src: StatePartIndex(9), // SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + Copy { + dest: StatePartIndex(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> }, + src: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:3:1 + IsNonZeroDestIsSmall { + dest: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, + }, + AndSmall { + dest: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, + }, + BranchIfSmallNonZero { + target: 16, + value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + }, + BranchIfSmallZero { + target: 17, + value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + }, + Copy { + dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + }, + Branch { + target: 17, + }, + Copy { + dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + src: StatePartIndex(5), // SlotDebugData { name: "", ty: UInt<4> }, + }, + NotSmall { + dest: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + Return, + ], + .. + }, + pc: 18, + small_slots: StatePart { + value: [ + 18446744073709551614, + 0, + 1, + 0, + ], + }, + big_slots: StatePart { + value: [ + 1, + 0, + 3, + 3, + 4, + 3, + 0, + 1, + 4, + 4, + ], + }, + }, + io: Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }, + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::cd.rst", + ty: AsyncReset, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: AsyncReset, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: AsyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 2 }, + }, + write: None, + }, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd.rst: CompiledValue { + layout: CompiledTypeLayout { + ty: AsyncReset, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: AsyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.count: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::count", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, + }, + }, + made_initial_step: true, + needs_settle: false, + trace_decls: TraceModule { + name: "counter", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + id: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceAsyncReset { + id: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + id: TraceScalarId(2), + name: "count", + ty: UInt<4>, + flow: Sink, + }, + ty: UInt<4>, + flow: Sink, + }, + TraceReg { + name: "count_reg", + child: TraceUInt { + id: TraceScalarId(3), + name: "count_reg", + ty: UInt<4>, + flow: Duplex, + }, + ty: UInt<4>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigAsyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigUInt { + index: StatePartIndex(2), + ty: UInt<4>, + }, + state: 0x3, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(3), + ty: UInt<4>, + }, + state: 0x3, + last_state: 0x3, + }, + ], + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + instant: 66 μs, + clocks_triggered: [ + StatePartIndex(1), + ], +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/counter_async.vcd b/crates/fayalite/tests/sim/expected/counter_async.vcd new file mode 100644 index 0000000..a4b2ee9 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/counter_async.vcd @@ -0,0 +1,217 @@ +$timescale 1 ps $end +$scope module counter $end +$scope struct cd $end +$var wire 1 ! clk $end +$var wire 1 " rst $end +$upscope $end +$var wire 4 # count $end +$var reg 4 $ count_reg $end +$upscope $end +$enddefinitions $end +$dumpvars +0! +0" +b0 # +b0 $ +$end +#500000 +1" +b11 # +b11 $ +#1000000 +1! +#1500000 +0" +#2000000 +0! +#3000000 +1! +b100 $ +b100 # +#4000000 +0! +#5000000 +1! +b101 $ +b101 # +#6000000 +0! +#7000000 +1! +b110 $ +b110 # +#8000000 +0! +#9000000 +1! +b111 $ +b111 # +#10000000 +0! +#11000000 +1! +b1000 $ +b1000 # +#12000000 +0! +#13000000 +1! +b1001 $ +b1001 # +#14000000 +0! +#15000000 +1! +b1010 $ +b1010 # +#16000000 +0! +#17000000 +1! +b1011 $ +b1011 # +#18000000 +0! +#19000000 +1! +b1100 $ +b1100 # +#20000000 +0! +#21000000 +1! +b1101 $ +b1101 # +#22000000 +0! +#23000000 +1! +b1110 $ +b1110 # +#24000000 +0! +#25000000 +1! +b1111 $ +b1111 # +#26000000 +0! +#27000000 +1! +b0 $ +b0 # +#28000000 +0! +#29000000 +1! +b1 $ +b1 # +#30000000 +0! +#31000000 +1! +b10 $ +b10 # +#32000000 +0! +#33000000 +1! +b11 $ +b11 # +#34000000 +0! +#35000000 +1! +b100 $ +b100 # +#36000000 +0! +#37000000 +1! +b101 $ +b101 # +#38000000 +0! +#39000000 +1! +b110 $ +b110 # +#40000000 +0! +#41000000 +1! +b111 $ +b111 # +#42000000 +0! +#43000000 +1! +b1000 $ +b1000 # +#44000000 +0! +#45000000 +1! +b1001 $ +b1001 # +#46000000 +0! +#47000000 +1! +b1010 $ +b1010 # +#48000000 +0! +#49000000 +1! +b1011 $ +b1011 # +#50000000 +0! +#51000000 +1! +b1100 $ +b1100 # +#52000000 +0! +#53000000 +1! +b1101 $ +b1101 # +#54000000 +0! +#55000000 +1! +b1110 $ +b1110 # +#56000000 +0! +#57000000 +1! +b1111 $ +b1111 # +#58000000 +0! +#59000000 +1! +b0 $ +b0 # +#60000000 +0! +#61000000 +1! +b1 $ +b1 # +#62000000 +0! +#63000000 +1! +b10 $ +b10 # +#64000000 +0! +#65000000 +1! +b11 $ +b11 # +#66000000 diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt new file mode 100644 index 0000000..dbb6134 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/counter_sync.txt @@ -0,0 +1,490 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 4, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartAllocationLayout { + len: 9, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::count", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::count_reg", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::count_reg$next", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:6:1 + Copy { + dest: StatePartIndex(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> }, + src: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + Const { + dest: StatePartIndex(6), // SlotDebugData { name: "", ty: UInt<1> }, + value: 1, + }, + Add { + dest: StatePartIndex(7), // SlotDebugData { name: "", ty: UInt<5> }, + lhs: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + rhs: StatePartIndex(6), // SlotDebugData { name: "", ty: UInt<1> }, + }, + CastToUInt { + dest: StatePartIndex(8), // SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(7), // SlotDebugData { name: "", ty: UInt<5> }, + dest_width: 4, + }, + // at: module-XXXXXXXXXX.rs:4:1 + Copy { + dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + src: StatePartIndex(8), // SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:3:1 + IsNonZeroDestIsSmall { + dest: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + Const { + dest: StatePartIndex(5), // SlotDebugData { name: "", ty: UInt<4> }, + value: 3, + }, + // at: module-XXXXXXXXXX.rs:3:1 + IsNonZeroDestIsSmall { + dest: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, + }, + AndSmall { + dest: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, + }, + BranchIfSmallZero { + target: 14, + value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + }, + BranchIfSmallNonZero { + target: 13, + value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + }, + Copy { + dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + }, + Branch { + target: 14, + }, + Copy { + dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + src: StatePartIndex(5), // SlotDebugData { name: "", ty: UInt<4> }, + }, + NotSmall { + dest: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + Return, + ], + .. + }, + pc: 15, + small_slots: StatePart { + value: [ + 18446744073709551614, + 0, + 1, + 0, + ], + }, + big_slots: StatePart { + value: [ + 1, + 0, + 3, + 3, + 4, + 3, + 1, + 4, + 4, + ], + }, + }, + io: Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }, + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::cd.rst", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SyncReset, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 2 }, + }, + write: None, + }, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd.rst: CompiledValue { + layout: CompiledTypeLayout { + ty: SyncReset, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.count: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(counter: counter).counter::count", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, + }, + }, + made_initial_step: true, + needs_settle: false, + trace_decls: TraceModule { + name: "counter", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + id: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + id: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + id: TraceScalarId(2), + name: "count", + ty: UInt<4>, + flow: Sink, + }, + ty: UInt<4>, + flow: Sink, + }, + TraceReg { + name: "count_reg", + child: TraceUInt { + id: TraceScalarId(3), + name: "count_reg", + ty: UInt<4>, + flow: Duplex, + }, + ty: UInt<4>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigUInt { + index: StatePartIndex(2), + ty: UInt<4>, + }, + state: 0x3, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(3), + ty: UInt<4>, + }, + state: 0x3, + last_state: 0x3, + }, + ], + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + instant: 66 μs, + clocks_triggered: [ + StatePartIndex(1), + ], +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/counter_sync.vcd b/crates/fayalite/tests/sim/expected/counter_sync.vcd new file mode 100644 index 0000000..bf6249e --- /dev/null +++ b/crates/fayalite/tests/sim/expected/counter_sync.vcd @@ -0,0 +1,214 @@ +$timescale 1 ps $end +$scope module counter $end +$scope struct cd $end +$var wire 1 ! clk $end +$var wire 1 " rst $end +$upscope $end +$var wire 4 # count $end +$var reg 4 $ count_reg $end +$upscope $end +$enddefinitions $end +$dumpvars +0! +1" +b0 # +b0 $ +$end +#1000000 +1! +b11 $ +b11 # +0" +#2000000 +0! +#3000000 +1! +b100 $ +b100 # +#4000000 +0! +#5000000 +1! +b101 $ +b101 # +#6000000 +0! +#7000000 +1! +b110 $ +b110 # +#8000000 +0! +#9000000 +1! +b111 $ +b111 # +#10000000 +0! +#11000000 +1! +b1000 $ +b1000 # +#12000000 +0! +#13000000 +1! +b1001 $ +b1001 # +#14000000 +0! +#15000000 +1! +b1010 $ +b1010 # +#16000000 +0! +#17000000 +1! +b1011 $ +b1011 # +#18000000 +0! +#19000000 +1! +b1100 $ +b1100 # +#20000000 +0! +#21000000 +1! +b1101 $ +b1101 # +#22000000 +0! +#23000000 +1! +b1110 $ +b1110 # +#24000000 +0! +#25000000 +1! +b1111 $ +b1111 # +#26000000 +0! +#27000000 +1! +b0 $ +b0 # +#28000000 +0! +#29000000 +1! +b1 $ +b1 # +#30000000 +0! +#31000000 +1! +b10 $ +b10 # +#32000000 +0! +#33000000 +1! +b11 $ +b11 # +#34000000 +0! +#35000000 +1! +b100 $ +b100 # +#36000000 +0! +#37000000 +1! +b101 $ +b101 # +#38000000 +0! +#39000000 +1! +b110 $ +b110 # +#40000000 +0! +#41000000 +1! +b111 $ +b111 # +#42000000 +0! +#43000000 +1! +b1000 $ +b1000 # +#44000000 +0! +#45000000 +1! +b1001 $ +b1001 # +#46000000 +0! +#47000000 +1! +b1010 $ +b1010 # +#48000000 +0! +#49000000 +1! +b1011 $ +b1011 # +#50000000 +0! +#51000000 +1! +b1100 $ +b1100 # +#52000000 +0! +#53000000 +1! +b1101 $ +b1101 # +#54000000 +0! +#55000000 +1! +b1110 $ +b1110 # +#56000000 +0! +#57000000 +1! +b1111 $ +b1111 # +#58000000 +0! +#59000000 +1! +b0 $ +b0 # +#60000000 +0! +#61000000 +1! +b1 $ +b1 # +#62000000 +0! +#63000000 +1! +b10 $ +b10 # +#64000000 +0! +#65000000 +1! +b11 $ +b11 # +#66000000 diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt new file mode 100644 index 0000000..74ba140 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/mod1.txt @@ -0,0 +1,798 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 17, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::o.i", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::o.o", + ty: SInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::o.i2", + ty: SInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::o.o2", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::child.i", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::child.o", + ty: SInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::child.i2", + ty: SInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::child.o2", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", + ty: SInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", + ty: SInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: SInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:4:1 + Copy { + dest: StatePartIndex(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> }, + src: StatePartIndex(2), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> }, + }, + Copy { + dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> }, + src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:2:1 + Copy { + dest: StatePartIndex(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> }, + src: StatePartIndex(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> }, + }, + Copy { + dest: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> }, + src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX-2.rs:1:1 + Const { + dest: StatePartIndex(16), // SlotDebugData { name: "", ty: UInt<4> }, + value: 15, + }, + Const { + dest: StatePartIndex(14), // SlotDebugData { name: "", ty: UInt<4> }, + value: 5, + }, + CmpLt { + dest: StatePartIndex(15), // SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(14), // SlotDebugData { name: "", ty: UInt<4> }, + rhs: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> }, + }, + CastToUInt { + dest: StatePartIndex(13), // SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> }, + dest_width: 4, + }, + // at: module-XXXXXXXXXX-2.rs:7:1 + Copy { + dest: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> }, + src: StatePartIndex(13), // SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX-2.rs:8:1 + BranchIfZero { + target: 11, + value: StatePartIndex(15), // SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX-2.rs:9:1 + Copy { + dest: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> }, + src: StatePartIndex(16), // SlotDebugData { name: "", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:2:1 + Copy { + dest: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> }, + src: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + Copy { + dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> }, + src: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX-2.rs:1:1 + CastToSInt { + dest: StatePartIndex(12), // SlotDebugData { name: "", ty: SInt<2> }, + src: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> }, + dest_width: 2, + }, + // at: module-XXXXXXXXXX-2.rs:6:1 + Copy { + dest: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> }, + src: StatePartIndex(12), // SlotDebugData { name: "", ty: SInt<2> }, + }, + // at: module-XXXXXXXXXX.rs:2:1 + Copy { + dest: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> }, + src: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + Copy { + dest: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> }, + src: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + Return, + ], + .. + }, + pc: 17, + small_slots: StatePart { + value: [], + }, + big_slots: StatePart { + value: [ + 10, + -2, + -2, + 15, + 10, + -2, + -2, + 15, + 10, + -2, + -2, + 15, + -2, + 14, + 5, + 1, + 15, + ], + }, + }, + io: Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. + }, + }, + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. + }, + }.o: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + #[hdl(flip)] /* offset = 0 */ + i: UInt<4>, + /* offset = 4 */ + o: SInt<2>, + #[hdl(flip)] /* offset = 6 */ + i2: SInt<2>, + /* offset = 8 */ + o2: UInt<4>, + }, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 4, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::o.i", + ty: UInt<4>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::o.o", + ty: SInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::o.i2", + ty: SInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(mod1: mod1).mod1::o.o2", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SInt<2>, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(2), + }, + ty: CompiledTypeLayout { + ty: SInt<2>, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(3), + }, + ty: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 4 }, + }, + write: None, + }, + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. + }, + }.o.i: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. + }, + }.o.i2: CompiledValue { + layout: CompiledTypeLayout { + ty: SInt<2>, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, + }, + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. + }, + }.o.o: CompiledValue { + layout: CompiledTypeLayout { + ty: SInt<2>, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SInt<2>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. + }, + }.o.o2: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<4>, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: UInt<4>, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 1 }, + }, + write: None, + }, + }, + made_initial_step: true, + needs_settle: false, + trace_decls: TraceModule { + name: "mod1", + children: [ + TraceModuleIO { + name: "o", + child: TraceBundle { + name: "o", + fields: [ + TraceUInt { + id: TraceScalarId(0), + name: "i", + ty: UInt<4>, + flow: Source, + }, + TraceSInt { + id: TraceScalarId(1), + name: "o", + ty: SInt<2>, + flow: Sink, + }, + TraceSInt { + id: TraceScalarId(2), + name: "i2", + ty: SInt<2>, + flow: Source, + }, + TraceUInt { + id: TraceScalarId(3), + name: "o2", + ty: UInt<4>, + flow: Sink, + }, + ], + ty: Bundle { + #[hdl(flip)] /* offset = 0 */ + i: UInt<4>, + /* offset = 4 */ + o: SInt<2>, + #[hdl(flip)] /* offset = 6 */ + i2: SInt<2>, + /* offset = 8 */ + o2: UInt<4>, + }, + flow: Sink, + }, + ty: Bundle { + #[hdl(flip)] /* offset = 0 */ + i: UInt<4>, + /* offset = 4 */ + o: SInt<2>, + #[hdl(flip)] /* offset = 6 */ + i2: SInt<2>, + /* offset = 8 */ + o2: UInt<4>, + }, + flow: Sink, + }, + TraceInstance { + name: "child", + instance_io: TraceBundle { + name: "child", + fields: [ + TraceUInt { + id: TraceScalarId(8), + name: "i", + ty: UInt<4>, + flow: Sink, + }, + TraceSInt { + id: TraceScalarId(9), + name: "o", + ty: SInt<2>, + flow: Source, + }, + TraceSInt { + id: TraceScalarId(10), + name: "i2", + ty: SInt<2>, + flow: Sink, + }, + TraceUInt { + id: TraceScalarId(11), + name: "o2", + ty: UInt<4>, + flow: Source, + }, + ], + ty: Bundle { + #[hdl(flip)] /* offset = 0 */ + i: UInt<4>, + /* offset = 4 */ + o: SInt<2>, + #[hdl(flip)] /* offset = 6 */ + i2: SInt<2>, + /* offset = 8 */ + o2: UInt<4>, + }, + flow: Source, + }, + module: TraceModule { + name: "mod1_child", + children: [ + TraceModuleIO { + name: "i", + child: TraceUInt { + id: TraceScalarId(4), + name: "i", + ty: UInt<4>, + flow: Source, + }, + ty: UInt<4>, + flow: Source, + }, + TraceModuleIO { + name: "o", + child: TraceSInt { + id: TraceScalarId(5), + name: "o", + ty: SInt<2>, + flow: Sink, + }, + ty: SInt<2>, + flow: Sink, + }, + TraceModuleIO { + name: "i2", + child: TraceSInt { + id: TraceScalarId(6), + name: "i2", + ty: SInt<2>, + flow: Source, + }, + ty: SInt<2>, + flow: Source, + }, + TraceModuleIO { + name: "o2", + child: TraceUInt { + id: TraceScalarId(7), + name: "o2", + ty: UInt<4>, + flow: Sink, + }, + ty: UInt<4>, + flow: Sink, + }, + ], + }, + ty: Bundle { + #[hdl(flip)] /* offset = 0 */ + i: UInt<4>, + /* offset = 4 */ + o: SInt<2>, + #[hdl(flip)] /* offset = 6 */ + i2: SInt<2>, + /* offset = 8 */ + o2: UInt<4>, + }, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigUInt { + index: StatePartIndex(0), + ty: UInt<4>, + }, + state: 0xa, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSInt { + index: StatePartIndex(1), + ty: SInt<2>, + }, + state: 0x2, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigSInt { + index: StatePartIndex(2), + ty: SInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(3), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xe, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigUInt { + index: StatePartIndex(8), + ty: UInt<4>, + }, + state: 0xa, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(5), + kind: BigSInt { + index: StatePartIndex(9), + ty: SInt<2>, + }, + state: 0x2, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigSInt { + index: StatePartIndex(10), + ty: SInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xe, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(4), + ty: UInt<4>, + }, + state: 0xa, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigSInt { + index: StatePartIndex(5), + ty: SInt<2>, + }, + state: 0x2, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigSInt { + index: StatePartIndex(6), + ty: SInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigUInt { + index: StatePartIndex(7), + ty: UInt<4>, + }, + state: 0xf, + last_state: 0xe, + }, + ], + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + instant: 2 μs, + clocks_triggered: [], +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/mod1.vcd b/crates/fayalite/tests/sim/expected/mod1.vcd new file mode 100644 index 0000000..0d1a6f4 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/mod1.vcd @@ -0,0 +1,47 @@ +$timescale 1 ps $end +$scope module mod1 $end +$scope struct o $end +$var wire 4 ! i $end +$var wire 2 " o $end +$var wire 2 # i2 $end +$var wire 4 $ o2 $end +$upscope $end +$scope struct child $end +$var wire 4 ) i $end +$var wire 2 * o $end +$var wire 2 + i2 $end +$var wire 4 , o2 $end +$upscope $end +$scope module mod1_child $end +$var wire 4 % i $end +$var wire 2 & o $end +$var wire 2 ' i2 $end +$var wire 4 ( o2 $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +b11 ! +b11 " +b10 # +b1110 $ +b11 % +b11 & +b10 ' +b1110 ( +b11 ) +b11 * +b10 + +b1110 , +$end +#1000000 +b1010 ! +b10 " +b1111 $ +b1010 % +b10 & +b1111 ( +b1010 ) +b10 * +b1111 , +#2000000 diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt new file mode 100644 index 0000000..5447d49 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/shift_register.txt @@ -0,0 +1,670 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 4, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartAllocationLayout { + len: 13, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::d", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::q", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", + ty: Bool, + }, + ], + .. + }, + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:13:1 + Copy { + dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool }, + src: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:12:1 + Copy { + dest: StatePartIndex(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, + src: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:10:1 + Copy { + dest: StatePartIndex(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, + src: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + Copy { + dest: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, + src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + Copy { + dest: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, + src: StatePartIndex(2), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:5:1 + IsNonZeroDestIsSmall { + dest: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + Const { + dest: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, + value: 0, + }, + // at: module-XXXXXXXXXX.rs:5:1 + IsNonZeroDestIsSmall { + dest: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock }, + }, + AndSmall { + dest: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, + }, + BranchIfSmallZero { + target: 14, + value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + }, + BranchIfSmallNonZero { + target: 13, + value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + }, + Copy { + dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, + src: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, + }, + Branch { + target: 14, + }, + Copy { + dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, + src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:7:1 + BranchIfSmallZero { + target: 19, + value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + }, + BranchIfSmallNonZero { + target: 18, + value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + }, + Copy { + dest: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, + src: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, + }, + Branch { + target: 19, + }, + Copy { + dest: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, + src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + BranchIfSmallZero { + target: 24, + value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + }, + BranchIfSmallNonZero { + target: 23, + value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + }, + Copy { + dest: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, + src: StatePartIndex(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, + }, + Branch { + target: 24, + }, + Copy { + dest: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, + src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:11:1 + BranchIfSmallZero { + target: 29, + value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, + }, + BranchIfSmallNonZero { + target: 28, + value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, + }, + Copy { + dest: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, + src: StatePartIndex(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, + }, + Branch { + target: 29, + }, + Copy { + dest: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, + src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:5:1 + NotSmall { + dest: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + Return, + ], + .. + }, + pc: 30, + small_slots: StatePart { + value: [ + 18446744073709551614, + 0, + 1, + 0, + ], + }, + big_slots: StatePart { + value: [ + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + ], + }, + }, + io: Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }, + uninitialized_inputs: {}, + io_targets: { + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }.cd: CompiledValue { + layout: CompiledTypeLayout { + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Bundle { + fields: [ + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(0), + }, + ty: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + CompiledBundleField { + offset: TypeIndex { + small_slots: StatePartIndex(0), + big_slots: StatePartIndex(1), + }, + ty: CompiledTypeLayout { + ty: SyncReset, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + }, + ], + }, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 2 }, + }, + write: None, + }, + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }.cd.clk: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + }, + write: None, + }, + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }.cd.rst: CompiledValue { + layout: CompiledTypeLayout { + ty: SyncReset, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: SyncReset, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + }, + write: None, + }, + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }.d: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::d", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 2, len: 1 }, + }, + write: None, + }, + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }.q: CompiledValue { + layout: CompiledTypeLayout { + ty: Bool, + layout: TypeLayout { + small_slots: StatePartAllocationLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartAllocationLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(shift_register: shift_register).shift_register::q", + ty: Bool, + }, + ], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 1 }, + }, + write: None, + }, + }, + made_initial_step: true, + needs_settle: false, + trace_decls: TraceModule { + name: "shift_register", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + id: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + id: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "d", + child: TraceBool { + id: TraceScalarId(2), + name: "d", + flow: Source, + }, + ty: Bool, + flow: Source, + }, + TraceModuleIO { + name: "q", + child: TraceBool { + id: TraceScalarId(3), + name: "q", + flow: Sink, + }, + ty: Bool, + flow: Sink, + }, + TraceReg { + name: "reg0", + child: TraceBool { + id: TraceScalarId(4), + name: "reg0", + flow: Duplex, + }, + ty: Bool, + }, + TraceReg { + name: "reg1", + child: TraceBool { + id: TraceScalarId(5), + name: "reg1", + flow: Duplex, + }, + ty: Bool, + }, + TraceReg { + name: "reg2", + child: TraceBool { + id: TraceScalarId(6), + name: "reg2", + flow: Duplex, + }, + ty: Bool, + }, + TraceReg { + name: "reg3", + child: TraceBool { + id: TraceScalarId(7), + name: "reg3", + flow: Duplex, + }, + ty: Bool, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigBool { + index: StatePartIndex(2), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(4), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigBool { + index: StatePartIndex(9), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(11), + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + instant: 66 μs, + clocks_triggered: [ + StatePartIndex(1), + ], +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/shift_register.vcd b/crates/fayalite/tests/sim/expected/shift_register.vcd new file mode 100644 index 0000000..0b5f429 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/shift_register.vcd @@ -0,0 +1,193 @@ +$timescale 1 ps $end +$scope module shift_register $end +$scope struct cd $end +$var wire 1 ! clk $end +$var wire 1 " rst $end +$upscope $end +$var wire 1 # d $end +$var wire 1 $ q $end +$var reg 1 % reg0 $end +$var reg 1 & reg1 $end +$var reg 1 ' reg2 $end +$var reg 1 ( reg3 $end +$upscope $end +$enddefinitions $end +$dumpvars +0! +1" +0# +0$ +0% +0& +0' +0( +$end +#1000000 +1! +#1100000 +0" +#2000000 +0! +#3000000 +1! +#4000000 +0! +1# +#5000000 +1! +1% +#6000000 +0! +#7000000 +1! +1& +#8000000 +0! +0# +#9000000 +1! +0% +1' +#10000000 +0! +#11000000 +1! +0& +1( +1$ +#12000000 +0! +1# +#13000000 +1! +1% +0' +#14000000 +0! +0# +#15000000 +1! +0% +1& +0( +0$ +#16000000 +0! +1# +#17000000 +1! +1% +0& +1' +#18000000 +0! +#19000000 +1! +1& +0' +1( +1$ +#20000000 +0! +#21000000 +1! +1' +0( +0$ +#22000000 +0! +#23000000 +1! +1( +1$ +#24000000 +0! +0# +#25000000 +1! +0% +#26000000 +0! +#27000000 +1! +0& +#28000000 +0! +#29000000 +1! +0' +#30000000 +0! +#31000000 +1! +0( +0$ +#32000000 +0! +#33000000 +1! +#34000000 +0! +#35000000 +1! +#36000000 +0! +#37000000 +1! +#38000000 +0! +#39000000 +1! +#40000000 +0! +#41000000 +1! +#42000000 +0! +#43000000 +1! +#44000000 +0! +#45000000 +1! +#46000000 +0! +#47000000 +1! +#48000000 +0! +#49000000 +1! +#50000000 +0! +#51000000 +1! +#52000000 +0! +#53000000 +1! +#54000000 +0! +#55000000 +1! +#56000000 +0! +#57000000 +1! +#58000000 +0! +#59000000 +1! +#60000000 +0! +#61000000 +1! +#62000000 +0! +#63000000 +1! +#64000000 +0! +#65000000 +1! +#66000000 diff --git a/scripts/check-copyright.sh b/scripts/check-copyright.sh index 8104f9c..3651931 100755 --- a/scripts/check-copyright.sh +++ b/scripts/check-copyright.sh @@ -46,7 +46,7 @@ function main() */LICENSE.md|*/Notices.txt) # copyright file ;; - /crates/fayalite/tests/ui/*.stderr) + /crates/fayalite/tests/ui/*.stderr|/crates/fayalite/tests/sim/expected/*.vcd|/crates/fayalite/tests/sim/expected/*.txt) # file that can't contain copyright header ;; /.forgejo/workflows/*.yml|*/.gitignore|*.toml)