From 180ecad01762d9f81c6ef8b70afb0c16b76ea802 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 22 Jul 2024 02:20:06 -0700 Subject: [PATCH] fix doctests to use Expr> instead of bool for example conditions --- .../modules/module_bodies/hdl_let_statements/registers.rs | 3 ++- .../_docs/modules/module_bodies/hdl_let_statements/wires.rs | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/registers.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/registers.rs index d278434..68dfaed 100644 --- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/registers.rs +++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/registers.rs @@ -11,7 +11,8 @@ //! # use fayalite::{hdl_module, int::UInt, array::Array, clock::ClockDomain}; //! # #[hdl_module] //! # fn module() { -//! # let v = true; +//! # #[hdl] +//! # let v: UInt<1> = m.input(); //! #[hdl] //! let cd: ClockDomain = m.input(); //! #[hdl] diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs index 7a78d95..3128e99 100644 --- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs +++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs @@ -12,7 +12,8 @@ //! # use fayalite::{hdl_module, int::UInt, array::Array, clock::ClockDomain}; //! # #[hdl_module] //! # fn module() { -//! # let v = true; +//! # #[hdl] +//! # let v: UInt<1> = m.input(); //! #[hdl] //! let cd: ClockDomain = m.input(); //! #[hdl]