add UIntInRange[Inclusive][Type]

crates/fayalite/tests/module.rs

@@ -1,8 +1,13 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use fayalite::{
-    assert_export_firrtl, firrtl::ExportOptions, intern::Intern,
-    module::transform::simplify_enums::SimplifyEnumsKind, prelude::*, reset::ResetType,
+    assert_export_firrtl,
+    firrtl::ExportOptions,
+    int::{UIntInRange, UIntInRangeInclusive},
+    intern::Intern,
+    module::transform::simplify_enums::SimplifyEnumsKind,
+    prelude::*,
+    reset::ResetType,
     ty::StaticType,
 };
 use serde_json::json;
@@ -4547,3 +4552,82 @@ circuit check_struct_cmp_eq:
 ",
     };
 }
+
+#[hdl_module(outline_generated)]
+pub fn check_uint_in_range() {
+    #[hdl]
+    let i_0_to_1: UIntInRange<0, 1> = m.input();
+    #[hdl]
+    let i_0_to_2: UIntInRange<0, 2> = m.input();
+    #[hdl]
+    let i_0_to_3: UIntInRange<0, 3> = m.input();
+    #[hdl]
+    let i_0_to_4: UIntInRange<0, 4> = m.input();
+    #[hdl]
+    let i_0_to_7: UIntInRange<0, 7> = m.input();
+    #[hdl]
+    let i_0_to_8: UIntInRange<0, 8> = m.input();
+    #[hdl]
+    let i_0_to_9: UIntInRange<0, 9> = m.input();
+    #[hdl]
+    let i_0_through_0: UIntInRangeInclusive<0, 0> = m.input();
+    #[hdl]
+    let i_0_through_1: UIntInRangeInclusive<0, 1> = m.input();
+    #[hdl]
+    let i_0_through_2: UIntInRangeInclusive<0, 2> = m.input();
+    #[hdl]
+    let i_0_through_3: UIntInRangeInclusive<0, 3> = m.input();
+    #[hdl]
+    let i_0_through_4: UIntInRangeInclusive<0, 4> = m.input();
+    #[hdl]
+    let i_0_through_7: UIntInRangeInclusive<0, 7> = m.input();
+    #[hdl]
+    let i_0_through_8: UIntInRangeInclusive<0, 8> = m.input();
+    #[hdl]
+    let i_0_through_9: UIntInRangeInclusive<0, 9> = m.input();
+}
+
+#[test]
+fn test_uint_in_range() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let m = check_uint_in_range();
+    dbg!(m);
+    #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
+    assert_export_firrtl! {
+        m =>
+        "/test/check_uint_in_range.fir": r"FIRRTL version 3.2.0
+circuit check_uint_in_range:
+    type Ty0 = {value: UInt<0>, range: {}}
+    type Ty1 = {value: UInt<1>, range: {}}
+    type Ty2 = {value: UInt<2>, range: {}}
+    type Ty3 = {value: UInt<2>, range: {}}
+    type Ty4 = {value: UInt<3>, range: {}}
+    type Ty5 = {value: UInt<3>, range: {}}
+    type Ty6 = {value: UInt<4>, range: {}}
+    type Ty7 = {value: UInt<0>, range: {}}
+    type Ty8 = {value: UInt<1>, range: {}}
+    type Ty9 = {value: UInt<2>, range: {}}
+    type Ty10 = {value: UInt<2>, range: {}}
+    type Ty11 = {value: UInt<3>, range: {}}
+    type Ty12 = {value: UInt<3>, range: {}}
+    type Ty13 = {value: UInt<4>, range: {}}
+    type Ty14 = {value: UInt<4>, range: {}}
+    module check_uint_in_range: @[module-XXXXXXXXXX.rs 1:1]
+        input i_0_to_1: Ty0 @[module-XXXXXXXXXX.rs 2:1]
+        input i_0_to_2: Ty1 @[module-XXXXXXXXXX.rs 3:1]
+        input i_0_to_3: Ty2 @[module-XXXXXXXXXX.rs 4:1]
+        input i_0_to_4: Ty3 @[module-XXXXXXXXXX.rs 5:1]
+        input i_0_to_7: Ty4 @[module-XXXXXXXXXX.rs 6:1]
+        input i_0_to_8: Ty5 @[module-XXXXXXXXXX.rs 7:1]
+        input i_0_to_9: Ty6 @[module-XXXXXXXXXX.rs 8:1]
+        input i_0_through_0: Ty7 @[module-XXXXXXXXXX.rs 9:1]
+        input i_0_through_1: Ty8 @[module-XXXXXXXXXX.rs 10:1]
+        input i_0_through_2: Ty9 @[module-XXXXXXXXXX.rs 11:1]
+        input i_0_through_3: Ty10 @[module-XXXXXXXXXX.rs 12:1]
+        input i_0_through_4: Ty11 @[module-XXXXXXXXXX.rs 13:1]
+        input i_0_through_7: Ty12 @[module-XXXXXXXXXX.rs 14:1]
+        input i_0_through_8: Ty13 @[module-XXXXXXXXXX.rs 15:1]
+        input i_0_through_9: Ty14 @[module-XXXXXXXXXX.rs 16:1]
+",
+    };
+}