libre-chip/fayalite
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Gather the FIFO debug ports in a bundle
#220 -Commit 3771cea78e pushed by cesar
#11
2024-12-29 16:37:56 +00:00
3m53s
Gather the FIFO debug ports in a bundle
#219 -Commit 3771cea78e pushed by cesar
fifo-proof
2024-12-29 16:34:03 +00:00
3m57s
Grammar fix.
#212 -Commit 8d7c691002 pushed by cesar
#11
2024-12-26 22:48:13 +00:00
3m53s
Gather the FIFO debug ports in a bundle
#211 -Commit 9f0fb0188a pushed by cesar
#11
2024-12-26 18:06:00 +00:00
3m54s
Add assertions and debug ports in order for the FIFO to pass induction
#210 -Commit ad1101934c pushed by cesar
#11
2024-12-26 14:06:06 +00:00
3m57s
Initial queue formal proof based on one-entry FIFO equivalence
#209 -Commit fef7fea3ea pushed by cesar
#11
2024-12-24 11:10:43 +00:00
5m10s
add module exercising formal verification of memories
#180 -Commit 2e7d685dc7 pushed by cesar
#7
2024-12-08 20:52:04 +00:00
17m31s
Add test module exercising formal verification.
#126 -Commit c1f1a8b749 pushed by cesar
#2
2024-11-20 21:40:00 +00:00
5m6s
Add test module exercising formal verification.
#124 -Commit 39d895764a pushed by cesar
#2
2024-11-20 21:11:40 +00:00
5m8s