fayalite

Add .to_trace_as_string() and clean up code

#389 -Commit cf3e6cfc6b pushed by programmerjake

master

2026-05-15 05:27:48 +00:00

4m46s

Add .to_trace_as_string() and clean up code

#388 -Commit cf3e6cfc6b pushed by programmerjake

#75

2026-05-15 05:17:51 +00:00

4m10s

Add .to_trace_as_string() and clean up code

#387 -Commit cefccab47c pushed by programmerjake

#75

2026-05-15 05:08:21 +00:00

1m1s

add TraceAsString<T> -- sim traces it as a string rather than all its internal fields

#386 -Commit ea183eac87 pushed by programmerjake

master

2026-05-14 02:53:13 +00:00

4m54s

add TraceAsString<T> -- sim traces it as a string rather than all its internal fields

#385 -Commit ea183eac87 pushed by programmerjake

#74

2026-05-14 02:48:15 +00:00

4m16s

add TraceAsString<T> -- sim traces it as a string rather than all its internal fields

#384 -Commit 299cbfa348 pushed by programmerjake

#74

2026-05-14 02:42:58 +00:00

1m42s

add TraceAsString<T> -- sim traces it as a string rather than all its internal fields

#383 -Commit 36c348e01c pushed by programmerjake

#74

2026-05-14 02:38:36 +00:00

3m11s

sim: properly update all VCD wires when they share simulation state

#382 -Commit 26224abe1c pushed by programmerjake

master

2026-05-06 04:27:05 +00:00

4m42s

sim: properly update all VCD wires when they share simulation state

#381 -Commit 26224abe1c pushed by programmerjake

#73

2026-05-06 04:22:19 +00:00

4m9s

redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue

#380 -Commit 2266315944 pushed by programmerjake

master

2026-05-04 06:38:15 +00:00

4m43s

redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue

#379 -Commit 2266315944 pushed by programmerjake

#72

2026-05-04 06:33:28 +00:00

7m18s

use #[hdl(cmp_eq)] for HdlOption and implement conversion <-> Option

#378 -Commit 7e9d7739fb pushed by programmerjake

master

2026-05-02 02:00:27 +00:00

4m41s

use #[hdl(cmp_eq)] for HdlOption and implement conversion <-> Option

#377 -Commit 7e9d7739fb pushed by programmerjake

#71

2026-05-02 01:55:40 +00:00

4m7s

add support for custom debug/display formatting of #[hdl] structs/enums

#376 -Commit 8e4eeef723 pushed by programmerjake

master

2026-05-01 06:23:14 +00:00

4m42s

add support for custom debug/display formatting of #[hdl] structs/enums

#375 -Commit 8e4eeef723 pushed by programmerjake

#70

2026-05-01 06:18:29 +00:00

4m7s

sim: Speed up updating traces by tracking which traces are written to

#374 -Commit 402f457c68 pushed by programmerjake

master

2026-05-01 02:23:30 +00:00

4m48s

sim: Speed up updating traces by tracking which traces are written to

#373 -Commit 402f457c68 pushed by programmerjake

#69

2026-05-01 02:18:37 +00:00

4m11s

change vcd output to have module contents under instance's name, more closely matching how it works in verilog

#370 -Commit 80b92c7dd3 pushed by programmerjake

master

2026-03-27 02:24:13 +00:00

4m55s

change vcd output to have module contents under instance's name, more closely matching how it works in verilog

#369 -Commit 80b92c7dd3 pushed by programmerjake

#68

2026-03-27 02:19:14 +00:00

4m18s

add simulator tests for queue()

#368 -Commit 2aa41137d4 pushed by programmerjake

master

2026-03-25 06:48:49 +00:00

5m3s

add simulator tests for queue()

#367 -Commit 2aa41137d4 pushed by programmerjake

#67

2026-03-25 06:43:42 +00:00

8m0s

update ui test's expected output for having rust-src available

#366 -Commit a93e66d8ab pushed by programmerjake

master

2026-03-18 03:59:45 +00:00

4m58s

update ui test's expected output for having rust-src available

#365 -Commit a93e66d8ab pushed by programmerjake

#66

2026-03-18 03:54:40 +00:00

4m21s

change VCD id generation to be based on hashing the path, making them better for git diff

#364 -Commit dbed947408 pushed by programmerjake

master

2026-03-18 03:28:55 +00:00

10m23s

change VCD id generation to be based on hashing the path, making them better for git diff

#363 -Commit dbed947408 pushed by programmerjake

#65

2026-02-24 04:18:22 +00:00

7m50s

speed up simulation by optimizing SimulationImpl::read_traces

#360 -Commit c632e5d570 pushed by programmerjake

master

2026-02-04 23:52:35 +00:00

5m24s

speed up simulation by optimizing SimulationImpl::read_traces

#359 -Commit c632e5d570 pushed by programmerjake

#63

2026-02-04 23:46:27 +00:00

4m23s

speed up LazyInterned by redoing caching using RwLock and add a thread-local cache

#358 -Commit 1bc835803b pushed by programmerjake

master

2026-02-04 02:17:31 +00:00

5m33s

speed up LazyInterned by redoing caching using RwLock and add a thread-local cache

#357 -Commit 1bc835803b pushed by programmerjake

#62

2026-02-04 02:11:42 +00:00

4m28s

speed up LazyInterned by redoing caching using RwLock and add a thread-local cache

#356 -Commit f236c9f404 pushed by programmerjake

#62

2026-02-04 01:44:35 +00:00

1m55s