fayalite

fayalite::build::verilog: tell firtool to only preserve values with significant names

#405 -Commit bb34aeb7f1 pushed by programmerjake

master

2026-06-15 02:00:08 +00:00

5m17s

fayalite::build::verilog: tell firtool to only preserve values with significant names

#404 -Commit bb34aeb7f1 pushed by programmerjake

#79

2026-06-15 01:54:46 +00:00

4m46s

module::transform::deduce_structural_eq_flags: rewrite to use BoolFixedPointSolver for a massive speedup on large inputs

#403 -Commit 7ddb4780fa pushed by programmerjake

master

2026-06-14 08:44:04 +00:00

5m18s

module::transform::deduce_structural_eq_flags: rewrite to use BoolFixedPointSolver for a massive speedup on large inputs

#402 -Commit 7ddb4780fa pushed by programmerjake

#78

2026-06-14 08:38:04 +00:00

4m44s

add BoolFixedPointSolver

#401 -Commit b0e7873a17 pushed by programmerjake

#78

2026-06-13 03:03:55 +00:00

4m44s

deduce_structural_eq_flags: use expressions' literal_bits to improve deduction around cast_bits_to

#400 -Commit 1b16118ce5 pushed by programmerjake

#78

2026-06-12 04:01:10 +00:00

4m18s

add deduce_structural_eq_flags transform

#398 -Commit 4bd6db3de8 pushed by programmerjake

#78

2026-06-11 08:31:29 +00:00

4m18s

fayalite::expr::ops: add and automatically generate ops::StructuralEq

#396 -Commit 80a11ec1c2 pushed by programmerjake

#78

2026-06-09 07:23:55 +00:00

4m20s

switch ready_valid::queue formal proofs to use formal_global_clock

#395 -Commit ffca1a279d pushed by programmerjake

master

2026-06-05 08:13:36 +00:00

4m47s

switch ready_valid::queue formal proofs to use formal_global_clock

#394 -Commit ffca1a279d pushed by programmerjake

#77

2026-06-05 08:01:39 +00:00

4m16s

fayalite/src/module: check that expressions are visible where they are used, e.g. erroring when a wire is inside an `if` but used outside.

#392 -Commit 31353862ce pushed by programmerjake

master

2026-06-02 08:36:33 +00:00

4m55s

fayalite/src/module: check that expressions are visible where they are used, e.g. erroring when a wire is inside an `if` but used outside.

#391 -Commit 31353862ce pushed by programmerjake

#76

2026-06-02 08:30:31 +00:00

4m21s

Add .to_trace_as_string() and clean up code

#389 -Commit cf3e6cfc6b pushed by programmerjake

master

2026-05-15 05:27:48 +00:00

4m46s

Add .to_trace_as_string() and clean up code

#388 -Commit cf3e6cfc6b pushed by programmerjake

#75

2026-05-15 05:17:51 +00:00

4m10s

add TraceAsString<T> -- sim traces it as a string rather than all its internal fields

#386 -Commit ea183eac87 pushed by programmerjake

master

2026-05-14 02:53:13 +00:00

4m54s

add TraceAsString<T> -- sim traces it as a string rather than all its internal fields

#385 -Commit ea183eac87 pushed by programmerjake

#74

2026-05-14 02:48:15 +00:00

4m16s

sim: properly update all VCD wires when they share simulation state

#382 -Commit 26224abe1c pushed by programmerjake

master

2026-05-06 04:27:05 +00:00

4m42s

sim: properly update all VCD wires when they share simulation state

#381 -Commit 26224abe1c pushed by programmerjake

#73

2026-05-06 04:22:19 +00:00

4m9s

redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue

#380 -Commit 2266315944 pushed by programmerjake

master

2026-05-04 06:38:15 +00:00

4m43s

redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue

#379 -Commit 2266315944 pushed by programmerjake

#72

2026-05-04 06:33:28 +00:00

7m18s

use #[hdl(cmp_eq)] for HdlOption and implement conversion <-> Option

#378 -Commit 7e9d7739fb pushed by programmerjake

master

2026-05-02 02:00:27 +00:00

4m41s

use #[hdl(cmp_eq)] for HdlOption and implement conversion <-> Option

#377 -Commit 7e9d7739fb pushed by programmerjake

#71

2026-05-02 01:55:40 +00:00

4m7s

add support for custom debug/display formatting of #[hdl] structs/enums

#376 -Commit 8e4eeef723 pushed by programmerjake

master

2026-05-01 06:23:14 +00:00

4m42s

add support for custom debug/display formatting of #[hdl] structs/enums

#375 -Commit 8e4eeef723 pushed by programmerjake

#70

2026-05-01 06:18:29 +00:00

4m7s

sim: Speed up updating traces by tracking which traces are written to

#374 -Commit 402f457c68 pushed by programmerjake

master

2026-05-01 02:23:30 +00:00

4m48s

sim: Speed up updating traces by tracking which traces are written to

#373 -Commit 402f457c68 pushed by programmerjake

#69

2026-05-01 02:18:37 +00:00

4m11s

Run Rocq tests.

#372 -Commit 8cff3687f7 pushed by cesar

master

2026-03-31 00:27:46 +00:00

4m59s

Run Rocq tests.

#371 -Commit 8cff3687f7 pushed by cesar

#64

2026-03-30 22:47:14 +00:00

8m7s

change vcd output to have module contents under instance's name, more closely matching how it works in verilog

#370 -Commit 80b92c7dd3 pushed by programmerjake

master

2026-03-27 02:24:13 +00:00

4m55s

change vcd output to have module contents under instance's name, more closely matching how it works in verilog

#369 -Commit 80b92c7dd3 pushed by programmerjake

#68

2026-03-27 02:19:14 +00:00

4m18s