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update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name #11

Merged
programmerjake merged 1 commit from programmerjake/cpu:make_vcd_modules_use_instance_names into master 2026-03-27 02:46:34 +00:00
Conversation 0 Commits 1 Files changed 10 +482113 -958901
10 changed files with 482113 additions and 958901 deletions
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8
Cargo.lock generated
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@ -388,7 +388,7 @@ checksum = "e8c02a5121d4ea3eb16a80748c74f5549a5665e4c21333c6098f283870fbdea6"
[[package]]
name = "fayalite"
version = "0.3.0"
source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#2aa41137d4eec592bd591fddb558bc78a52c635c"
source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#80b92c7dd3adcad8487a3f8224846e381219bfa6"
dependencies = [
"base64",
"bitvec",
@ -417,7 +417,7 @@ dependencies = [
[[package]]
name = "fayalite-proc-macros"
version = "0.3.0"
source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#2aa41137d4eec592bd591fddb558bc78a52c635c"
source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#80b92c7dd3adcad8487a3f8224846e381219bfa6"
dependencies = [
"fayalite-proc-macros-impl",
]
@ -425,7 +425,7 @@ dependencies = [
[[package]]
name = "fayalite-proc-macros-impl"
version = "0.3.0"
source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#2aa41137d4eec592bd591fddb558bc78a52c635c"
source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#80b92c7dd3adcad8487a3f8224846e381219bfa6"
dependencies = [
"base16ct 0.2.0",
"num-bigint",
@ -440,7 +440,7 @@ dependencies = [
[[package]]
name = "fayalite-visit-gen"
version = "0.3.0"
source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#2aa41137d4eec592bd591fddb558bc78a52c635c"
source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#80b92c7dd3adcad8487a3f8224846e381219bfa6"
dependencies = [
"indexmap",
"prettyplease",

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crates/cpu/tests/expected/main_memory_and_io.vcd generated
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crates/cpu/tests/expected/receiver_and_uart_clock_gen.vcd generated
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crates/cpu/tests/expected/receiver_no_queue_and_uart_clock_gen.vcd generated
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crates/cpu/tests/expected/reg_alloc.vcd generated
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crates/cpu/tests/expected/simple_uart.vcd generated
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crates/cpu/tests/expected/transmitter_and_uart_clock_gen.vcd generated
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