diff --git a/Cargo.lock b/Cargo.lock
index 172eda7..ea04274 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -300,7 +300,7 @@ checksum = "e8c02a5121d4ea3eb16a80748c74f5549a5665e4c21333c6098f283870fbdea6"
 [[package]]
 name = "fayalite"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#86a1bb46be4690e854470cf4a1a6e90c92268391"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#d4ea8260512e54c5187c1c59bd9bac47a319f86d"
 dependencies = [
  "bitvec",
  "blake3",
@@ -325,7 +325,7 @@ dependencies = [
 [[package]]
 name = "fayalite-proc-macros"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#86a1bb46be4690e854470cf4a1a6e90c92268391"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#d4ea8260512e54c5187c1c59bd9bac47a319f86d"
 dependencies = [
  "fayalite-proc-macros-impl",
 ]
@@ -333,7 +333,7 @@ dependencies = [
 [[package]]
 name = "fayalite-proc-macros-impl"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#86a1bb46be4690e854470cf4a1a6e90c92268391"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#d4ea8260512e54c5187c1c59bd9bac47a319f86d"
 dependencies = [
  "base16ct",
  "num-bigint",
@@ -348,7 +348,7 @@ dependencies = [
 [[package]]
 name = "fayalite-visit-gen"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#86a1bb46be4690e854470cf4a1a6e90c92268391"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#d4ea8260512e54c5187c1c59bd9bac47a319f86d"
 dependencies = [
  "indexmap",
  "prettyplease",
diff --git a/crates/cpu/src/instruction.rs b/crates/cpu/src/instruction.rs
index 46c778c..c073049 100644
--- a/crates/cpu/src/instruction.rs
+++ b/crates/cpu/src/instruction.rs
@@ -2,7 +2,7 @@
 // See Notices.txt for copyright information
 use crate::{unit::UnitMOp, util::range_u32_len};
 use fayalite::{expr::ops::ArrayLiteral, intern::Interned, prelude::*};
-use std::{fmt, marker::PhantomData, ops::Range};
+use std::{marker::PhantomData, ops::Range};
 
 pub mod power_isa;
 
@@ -668,29 +668,6 @@ pub struct MOpDestReg {
     pub flag_regs: Array<HdlOption<()>, { range_u32_len(&MOpRegNum::FLAG_REG_NUMS) }>,
 }
 
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash, Debug)]
-pub enum RenameTableName {
-    /// the large rename table for normal registers (has less read/write ports)
-    Normal,
-    /// a special small rename table (for flags and stuff, since it has more read/write ports)
-    Special,
-}
-
-impl RenameTableName {
-    pub const fn reg_range(self) -> std::ops::Range<u32> {
-        match self {
-            Self::Normal => MOpRegNum::NORMAL_REG_NUMS,
-            Self::Special => MOpRegNum::SPECIAL_REG_NUMS,
-        }
-    }
-    pub const fn as_str(self) -> &'static str {
-        match self {
-            Self::Normal => "rename_table_normal",
-            Self::Special => "rename_table_special",
-        }
-    }
-}
-
 #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)]
 pub enum MOpDestRegKind {
     NormalReg {
@@ -705,69 +682,6 @@ pub enum MOpDestRegKind {
     },
 }
 
-#[derive(Copy, Clone, Debug)]
-pub struct MOpDestRegName {
-    base_name: &'static str,
-    index: usize,
-    reg_num: Option<u32>,
-}
-
-impl fmt::Display for MOpDestRegName {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        let Self {
-            base_name,
-            index,
-            reg_num,
-        } = self;
-        write!(f, "{base_name}{index}")?;
-        if let Some(reg_num) = reg_num {
-            write!(f, "_r{reg_num:02X}")?;
-        }
-        Ok(())
-    }
-}
-
-impl MOpDestRegKind {
-    pub const fn reg_range(self) -> std::ops::Range<u32> {
-        match self {
-            Self::NormalReg { .. } => MOpRegNum::NORMAL_REG_NUMS,
-            Self::FlagReg { .. } => MOpRegNum::FLAG_REG_NUMS,
-        }
-    }
-    pub const fn rename_table_names(self) -> &'static [RenameTableName] {
-        match self {
-            Self::NormalReg { .. } => &[RenameTableName::Normal, RenameTableName::Special],
-            Self::FlagReg { .. } => &[RenameTableName::Special],
-        }
-    }
-    pub fn fixed_reg_num(self) -> Option<u32> {
-        match self {
-            Self::NormalReg { dest_reg_index: _ } => None,
-            Self::FlagReg {
-                flag_reg_index: _,
-                reg_num,
-            } => Some(reg_num),
-        }
-    }
-    pub fn reg_name(self) -> MOpDestRegName {
-        match self {
-            Self::NormalReg { dest_reg_index } => MOpDestRegName {
-                base_name: "dest",
-                index: dest_reg_index,
-                reg_num: None,
-            },
-            Self::FlagReg {
-                flag_reg_index,
-                reg_num,
-            } => MOpDestRegName {
-                base_name: "flag",
-                index: flag_reg_index,
-                reg_num: Some(reg_num),
-            },
-        }
-    }
-}
-
 impl MOpDestReg {
     pub const NORMAL_REG_COUNT: usize = 2;
     pub const REG_COUNT: usize = Self::NORMAL_REG_COUNT + range_u32_len(&MOpRegNum::FLAG_REG_NUMS);
diff --git a/crates/cpu/src/reg_alloc.rs b/crates/cpu/src/reg_alloc.rs
index d064bab..3d32261 100644
--- a/crates/cpu/src/reg_alloc.rs
+++ b/crates/cpu/src/reg_alloc.rs
@@ -3,22 +3,17 @@
 use crate::{
     config::CpuConfig,
     instruction::{
-        MOp, MOpDestReg, MOpRegNum, MOpTrait, PRegNum, RenameTableName, UnitOutRegNum,
-        COMMON_MOP_SRC_LEN,
+        MOp, MOpDestReg, MOpRegNum, MOpTrait, PRegNum, UnitOutRegNum, COMMON_MOP_SRC_LEN,
     },
     unit::{TrapData, UnitTrait},
     util::tree_reduce::tree_reduce_with_state,
 };
 use fayalite::{
-    memory::{splat_mask, WriteStruct},
-    module::{instance_with_loc, memory_with_loc, wire_with_loc},
+    module::{instance_with_loc, wire_with_loc},
     prelude::*,
     util::ready_valid::ReadyValid,
 };
-use std::{
-    collections::{BTreeMap, VecDeque},
-    num::NonZeroUsize,
-};
+use std::num::NonZeroUsize;
 
 pub mod unit_free_regs_tracker;
 
@@ -60,23 +55,15 @@ pub fn reg_alloc(config: &CpuConfig) {
     );
     // TODO: finish
 
-    let mut rename_table_mems = BTreeMap::<RenameTableName, MemBuilder<_>>::new();
+    // the large rename table for normal registers (has less read/write ports)
+    #[hdl]
+    let mut rename_table_normal_mem = memory(config.p_reg_num());
+    rename_table_normal_mem.depth(MOpRegNum::NORMAL_REG_NUMS.len());
 
-    for reg_kind in MOpDestReg::REG_KINDS {
-        for &rename_table_name in reg_kind.rename_table_names() {
-            rename_table_mems
-                .entry(rename_table_name)
-                .or_insert_with(|| {
-                    let mut mem = memory_with_loc(
-                        &format!("{}_mem", rename_table_name.as_str()),
-                        config.p_reg_num(),
-                        SourceLocation::caller(),
-                    );
-                    mem.depth(rename_table_name.reg_range().len());
-                    mem
-                });
-        }
-    }
+    // a special small rename table (for flags and stuff, since it has more read/write ports)
+    #[hdl]
+    let mut rename_table_special_mem = memory(config.p_reg_num());
+    rename_table_special_mem.depth(MOpRegNum::SPECIAL_REG_NUMS.len());
 
     #[hdl]
     let available_units =
@@ -105,28 +92,29 @@ pub fn reg_alloc(config: &CpuConfig) {
         struct RenameTableReadPort<T> {
             addr: MOpRegNum,
             #[hdl(flip)]
-            data: T,
+            data: HdlOption<T>,
         }
-        let rename_table_read_ports: [_; COMMON_MOP_SRC_LEN] = std::array::from_fn(|src_index| {
-            let wire = wire_with_loc(
-                &format!("rename_{fetch_index}_src_{src_index}"),
-                SourceLocation::caller(),
-                RenameTableReadPort[config.p_reg_num()],
-            );
-            connect(wire.addr, MOpRegNum::const_zero());
-            connect(wire.data, config.p_reg_num().const_zero());
-            for (&rename_table_name, mem) in &mut rename_table_mems {
-                let table_name = rename_table_name.as_str();
+        let make_rename_table_read_port =
+            |mem: &mut MemBuilder<_>,
+             reg_range: std::ops::Range<u32>,
+             src_index: usize,
+             table_name: &str| {
                 let read_port = mem.new_read_port();
                 connect(read_port.clk, cd.clk);
                 connect_any(read_port.addr, 0u8);
                 connect(read_port.en, false);
-                let reg_range = rename_table_name.reg_range();
+                let wire = wire_with_loc(
+                    &format!("{table_name}_{fetch_index}_src_{src_index}"),
+                    SourceLocation::caller(),
+                    RenameTableReadPort[config.p_reg_num()],
+                );
+                connect(wire.addr, MOpRegNum::const_zero());
+                connect(wire.data, Expr::ty(wire.data).HdlNone());
                 #[hdl]
                 if wire.addr.value.cmp_ge(reg_range.start) & wire.addr.value.cmp_lt(reg_range.end) {
                     connect_any(read_port.addr, wire.addr.value - reg_range.start);
                     connect(read_port.en, true);
-                    connect(wire.data, read_port.data);
+                    connect(wire.data, HdlSome(read_port.data));
                     for prev_fetch_index in 0..fetch_index {
                         #[hdl]
                         if let HdlSome(decoded_insn) =
@@ -137,55 +125,36 @@ pub fn reg_alloc(config: &CpuConfig) {
                                 renamed_mops_out_reg[prev_fetch_index]
                             {
                                 let dest_reg = MOpTrait::dest_reg(decoded_insn.mop);
-                                for (dest_reg, reg_kind) in MOpDestReg::regs(dest_reg)
-                                    .into_iter()
-                                    .zip(MOpDestReg::REG_KINDS)
-                                {
-                                    if reg_kind.rename_table_names().contains(&rename_table_name) {
-                                        #[hdl]
-                                        if dest_reg.value.cmp_eq(wire.addr.value) {
-                                            connect(wire.data, renamed_mop_out_reg);
-                                        }
+                                for dest_reg in MOpDestReg::regs(dest_reg) {
+                                    #[hdl]
+                                    if dest_reg.value.cmp_eq(wire.addr.value) {
+                                        connect(wire.data, HdlSome(renamed_mop_out_reg));
                                     }
                                 }
                             }
                         }
                     }
                 }
-            }
-            wire
-        });
-        let mut rename_table_write_ports = BTreeMap::<RenameTableName, VecDeque<_>>::new();
-        for reg_kind in MOpDestReg::REG_KINDS {
-            for &rename_table_name in reg_kind.rename_table_names() {
-                let mem = rename_table_mems
-                    .get_mut(&rename_table_name)
-                    .expect("already added all RenameTableName values");
-                let write_ports = rename_table_write_ports
-                    .entry(rename_table_name)
-                    .or_default();
-                let write_port_ = mem.new_write_port();
-                let table_name = rename_table_name.as_str();
-                let write_port = wire_with_loc(
-                    &format!("{table_name}_{fetch_index}_{}", reg_kind.reg_name()),
-                    SourceLocation::caller(),
-                    Expr::ty(write_port_),
-                );
-                connect(write_port_, write_port);
-                write_ports.push_back(write_port);
-                connect_any(
-                    write_port,
-                    #[hdl]
-                    WriteStruct::<_, _> {
-                        addr: 0_hdl_u0,
-                        en: false,
-                        clk: cd.clk,
-                        data: Expr::ty(write_port.data).uninit(),
-                        mask: splat_mask(config.p_reg_num(), true.to_expr()),
-                    },
-                );
-            }
-        }
+                wire
+            };
+        let rename_table_normal_read_ports: [_; COMMON_MOP_SRC_LEN] =
+            std::array::from_fn(|src_index| {
+                make_rename_table_read_port(
+                    &mut rename_table_normal_mem,
+                    MOpRegNum::NORMAL_REG_NUMS,
+                    src_index,
+                    "rename_table_normal",
+                )
+            });
+        let rename_table_special_read_ports: [_; COMMON_MOP_SRC_LEN] =
+            std::array::from_fn(|src_index| {
+                make_rename_table_read_port(
+                    &mut rename_table_special_mem,
+                    MOpRegNum::FLAG_REG_NUMS,
+                    src_index,
+                    "rename_table_special",
+                )
+            });
         #[hdl]
         if let HdlSome(decoded_insn) = fetch_decode_interface.decoded_insns[fetch_index].data {
             connect(
@@ -202,41 +171,31 @@ pub fn reg_alloc(config: &CpuConfig) {
                         renamed_mop_out_reg.unit_out_reg,
                         config.p_reg_num_width(),
                         &mut |src_reg, src_index| {
-                            connect(
-                                rename_table_read_ports[src_index].addr,
-                                #[hdl]
-                                MOpRegNum { value: src_reg },
+                            let src_reg = #[hdl]
+                            MOpRegNum { value: src_reg };
+                            let renamed_src_reg = wire_with_loc(
+                                &format!("renamed_src_reg_{fetch_index}_{src_index}"),
+                                SourceLocation::caller(),
+                                config.p_reg_num(),
                             );
-                            rename_table_read_ports[src_index].data.cast_to_bits()
+                            connect(rename_table_normal_read_ports[src_index].addr, src_reg);
+                            connect(rename_table_special_read_ports[src_index].addr, src_reg);
+                            #[hdl]
+                            if let HdlSome(v) = rename_table_normal_read_ports[src_index].data {
+                                connect(renamed_src_reg, v);
+                            } else if let HdlSome(v) =
+                                rename_table_special_read_ports[src_index].data
+                            {
+                                connect(renamed_src_reg, v);
+                            } else {
+                                connect(renamed_src_reg, config.p_reg_num().const_zero());
+                            }
+                            renamed_src_reg.cast_to_bits()
                         },
                     )),
                 );
-                for (reg, reg_kind) in MOpDestReg::regs(dest_reg)
-                    .into_iter()
-                    .zip(MOpDestReg::REG_KINDS)
-                {
-                    for &rename_table_name in reg_kind.rename_table_names() {
-                        let Some(write_ports) =
-                            rename_table_write_ports.get_mut(&rename_table_name)
-                        else {
-                            unreachable!();
-                        };
-                        let Some(write_port) = write_ports.pop_front() else {
-                            unreachable!();
-                        };
-                        let reg_range = rename_table_name.reg_range();
-                        #[hdl]
-                        if reg.value.cmp_ge(reg_range.start) & reg.value.cmp_lt(reg_range.end) {
-                            connect(write_port.data, renamed_mop_out_reg);
-                            if let Some(fixed_reg_num) = reg_kind.fixed_reg_num() {
-                                connect_any(write_port.addr, fixed_reg_num - reg_range.start);
-                            } else {
-                                connect_any(write_port.addr, reg.value - reg_range.start);
-                            }
-                            connect(write_port.en, true);
-                        }
-                    }
-                }
+                // TODO: write dest_reg to rename table
+                // rename_table_mem.new_write_port()
             }
         }
         connect(
diff --git a/crates/cpu/tests/expected/reg_alloc.vcd b/crates/cpu/tests/expected/reg_alloc.vcd
index 54c1f5f..97da171 100644
--- a/crates/cpu/tests/expected/reg_alloc.vcd
+++ b/crates/cpu/tests/expected/reg_alloc.vcd
@@ -600,6 +600,1066 @@ $scope struct contents $end
 $scope struct \[0] $end
 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
+$var reg 2 p0 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 S3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[1] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 q0 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 T3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[2] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 r0 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 U3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[3] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 s0 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 V3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[4] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 t0 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 W3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[5] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 u0 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 X3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[6] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 v0 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 Y3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[7] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 w0 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 Z3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[8] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 x0 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 [3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[9] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 y0 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 \3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[10] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 z0 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 ]3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[11] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 {0 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 ^3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[12] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 |0 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 _3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[13] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 }0 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 `3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[14] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 ~0 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 a3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[15] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 !1 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 b3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[16] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 "1 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 c3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[17] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 #1 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 d3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[18] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 $1 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 e3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[19] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 %1 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 f3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[20] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 &1 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 g3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[21] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 '1 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 h3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[22] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 (1 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 i3 value $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[23] $end
+$scope struct rename_table_normal_mem $end
+$scope struct unit_num $end
+$var reg 2 )1 adj_value $end
+$upscope $end
+$scope struct unit_out_reg $end
+$var reg 4 j3 value $end
+$upscope $end
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@@ -617,7 +1677,7 @@ $var reg 4 `4 value $end
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 $scope struct rename_table_normal_mem $end
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@@ -627,7 +1687,7 @@ $var reg 4 a4 value $end
 $upscope $end
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@@ -637,7 +1697,7 @@ $var reg 4 b4 value $end
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 $scope struct rename_table_normal_mem $end
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@@ -647,7 +1707,7 @@ $var reg 4 c4 value $end
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 $scope struct rename_table_normal_mem $end
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@@ -657,7 +1717,7 @@ $var reg 4 d4 value $end
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@@ -667,7 +1727,7 @@ $var reg 4 e4 value $end
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@@ -677,7 +1737,7 @@ $var reg 4 f4 value $end
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@@ -687,7 +1747,7 @@ $var reg 4 g4 value $end
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@@ -697,7 +1757,7 @@ $var reg 4 h4 value $end
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@@ -707,7 +1767,7 @@ $var reg 4 i4 value $end
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@@ -717,7 +1777,7 @@ $var reg 4 j4 value $end
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@@ -727,7 +1787,7 @@ $var reg 4 k4 value $end
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@@ -737,7 +1797,7 @@ $var reg 4 l4 value $end
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@@ -747,7 +1807,7 @@ $var reg 4 m4 value $end
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@@ -757,7 +1817,7 @@ $var reg 4 n4 value $end
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@@ -767,7 +1827,7 @@ $var reg 4 o4 value $end
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@@ -777,7 +1837,7 @@ $var reg 4 p4 value $end
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@@ -787,7 +1847,7 @@ $var reg 4 q4 value $end
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@@ -797,7 +1857,7 @@ $var reg 4 r4 value $end
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@@ -807,7 +1867,7 @@ $var reg 4 s4 value $end
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@@ -817,7 +1877,7 @@ $var reg 4 t4 value $end
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@@ -827,7 +1887,7 @@ $var reg 4 u4 value $end
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@@ -837,7 +1897,7 @@ $var reg 4 v4 value $end
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@@ -847,7 +1907,7 @@ $var reg 4 w4 value $end
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@@ -857,7 +1917,7 @@ $var reg 4 x4 value $end
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@@ -867,7 +1927,7 @@ $var reg 4 y4 value $end
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@@ -877,7 +1937,7 @@ $var reg 4 z4 value $end
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@@ -887,7 +1947,7 @@ $var reg 4 {4 value $end
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@@ -897,7 +1957,7 @@ $var reg 4 |4 value $end
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@@ -907,7 +1967,7 @@ $var reg 4 }4 value $end
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@@ -917,7 +1977,7 @@ $var reg 4 ~4 value $end
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@@ -927,7 +1987,7 @@ $var reg 4 !5 value $end
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@@ -937,7 +1997,7 @@ $var reg 4 "5 value $end
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@@ -947,7 +2007,7 @@ $var reg 4 #5 value $end
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@@ -957,7 +2017,7 @@ $var reg 4 $5 value $end
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@@ -967,7 +2027,7 @@ $var reg 4 %5 value $end
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@@ -977,7 +2037,7 @@ $var reg 4 &5 value $end
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@@ -987,7 +2047,7 @@ $var reg 4 '5 value $end
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@@ -997,7 +2057,7 @@ $var reg 4 (5 value $end
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@@ -1007,7 +2067,7 @@ $var reg 4 )5 value $end
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@@ -1017,7 +2077,7 @@ $var reg 4 *5 value $end
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@@ -1027,7 +2087,7 @@ $var reg 4 +5 value $end
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@@ -1037,7 +2097,7 @@ $var reg 4 ,5 value $end
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@@ -1047,7 +2107,7 @@ $var reg 4 -5 value $end
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@@ -1057,7 +2117,7 @@ $var reg 4 .5 value $end
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@@ -1067,7 +2127,7 @@ $var reg 4 /5 value $end
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@@ -1077,7 +2137,7 @@ $var reg 4 05 value $end
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@@ -1087,7 +2147,7 @@ $var reg 4 15 value $end
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@@ -1097,7 +2157,7 @@ $var reg 4 25 value $end
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@@ -1107,7 +2167,7 @@ $var reg 4 35 value $end
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@@ -1117,7 +2177,7 @@ $var reg 4 45 value $end
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@@ -1127,7 +2187,7 @@ $var reg 4 55 value $end
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@@ -1137,7 +2197,7 @@ $var reg 4 65 value $end
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@@ -1147,7 +2207,7 @@ $var reg 4 75 value $end
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@@ -1157,7 +2217,7 @@ $var reg 4 85 value $end
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@@ -1167,7 +2227,7 @@ $var reg 4 95 value $end
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@@ -1177,7 +2237,7 @@ $var reg 4 :5 value $end
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@@ -1187,7 +2247,7 @@ $var reg 4 ;5 value $end
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@@ -1197,7 +2257,7 @@ $var reg 4 <5 value $end
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@@ -1207,7 +2267,7 @@ $var reg 4 =5 value $end
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@@ -1217,7 +2277,7 @@ $var reg 4 >5 value $end
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@@ -1227,7 +2287,7 @@ $var reg 4 ?5 value $end
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@@ -1237,7 +2297,7 @@ $var reg 4 @5 value $end
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@@ -1247,7 +2307,7 @@ $var reg 4 A5 value $end
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@@ -1257,7 +2317,7 @@ $var reg 4 B5 value $end
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@@ -1267,7 +2327,7 @@ $var reg 4 C5 value $end
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@@ -1277,7 +2337,7 @@ $var reg 4 D5 value $end
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@@ -1287,7 +2347,7 @@ $var reg 4 E5 value $end
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@@ -1297,7 +2357,7 @@ $var reg 4 F5 value $end
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@@ -1307,7 +2367,7 @@ $var reg 4 G5 value $end
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@@ -1317,7 +2377,7 @@ $var reg 4 H5 value $end
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@@ -1327,7 +2387,7 @@ $var reg 4 I5 value $end
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@@ -1337,7 +2397,7 @@ $var reg 4 J5 value $end
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@@ -1347,7 +2407,7 @@ $var reg 4 K5 value $end
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@@ -1357,7 +2417,7 @@ $var reg 4 L5 value $end
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@@ -1367,7 +2427,7 @@ $var reg 4 M5 value $end
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@@ -1377,7 +2437,7 @@ $var reg 4 N5 value $end
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 $upscope $end
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@@ -1387,7 +2447,7 @@ $var reg 4 O5 value $end
 $upscope $end
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 $scope struct rename_table_normal_mem $end
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@@ -1397,7 +2457,7 @@ $var reg 4 P5 value $end
 $upscope $end
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 $scope struct rename_table_normal_mem $end
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@@ -1407,7 +2467,7 @@ $var reg 4 Q5 value $end
 $upscope $end
 $upscope $end
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 $scope struct rename_table_normal_mem $end
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@@ -1417,7 +2477,7 @@ $var reg 4 R5 value $end
 $upscope $end
 $upscope $end
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 $scope struct rename_table_normal_mem $end
 $scope struct unit_num $end
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@@ -1427,7 +2487,7 @@ $var reg 4 S5 value $end
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 $upscope $end
 $scope struct r0 $end
 $var wire 8 |" addr $end
@@ -3167,7 +3167,7 @@ $var wire 4 ,# value $end
 $upscope $end
 $upscope $end
 $upscope $end
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 $var wire 8 -# addr $end
 $var wire 1 .# en $end
 $var wire 1 /# clk $end
@@ -3179,114 +3179,30 @@ $scope struct unit_out_reg $end
 $var wire 4 1# value $end
 $upscope $end
 $upscope $end
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 $upscope $end
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 $scope struct data $end
 $scope struct unit_num $end
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 $upscope $end
 $scope struct unit_out_reg $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct r5 $end
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 $scope struct data $end
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 $upscope $end
 $upscope $end
 $upscope $end
@@ -3296,434 +3212,266 @@ $scope struct contents $end
 $scope struct \[0] $end
 $scope struct rename_table_special_mem $end
 $scope struct unit_num $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
 $scope struct rename_table_special_mem $end
 $scope struct unit_num $end
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 $upscope $end
 $scope struct unit_out_reg $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct r0 $end
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 $scope struct data $end
 $scope struct unit_num $end
-$var wire 2 [# adj_value $end
+$var wire 2 ?# adj_value $end
 $upscope $end
 $scope struct unit_out_reg $end
-$var wire 4 \# value $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct r1 $end
-$var wire 1 ]# addr $end
-$var wire 1 ^# en $end
-$var wire 1 _# clk $end
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 $scope struct data $end
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 $scope struct r2 $end
-$var wire 1 b# addr $end
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 $scope struct data $end
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 $scope struct data $end
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 $scope struct data $end
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 $upscope $end
 $upscope $end
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 $scope struct data $end
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-$upscope $end
-$scope struct w13 $end
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-$upscope $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct available_units $end
 $scope struct \[0] $end
-$var wire 1 P$ \[0] $end
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 $upscope $end
 $scope struct \[1] $end
-$var wire 1 R$ \[0] $end
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 $upscope $end
 $upscope $end
 $scope struct selected_unit_indexes $end
 $scope struct \[0] $end
-$var string 1 T$ \$tag $end
-$var wire 2 U$ HdlSome $end
+$var string 1 ^# \$tag $end
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 $upscope $end
 $scope struct \[1] $end
-$var string 1 V$ \$tag $end
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 $upscope $end
 $upscope $end
 $scope struct renamed_mops $end
 $scope struct \[0] $end
-$var string 1 X$ \$tag $end
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 $scope struct HdlSome $end
-$var string 1 Y$ \$tag $end
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 $scope struct AluBranch $end
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 $scope struct AddSub $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 [$ prefix_pad $end
+$var string 0 e# prefix_pad $end
 $scope struct dest $end
-$var wire 4 \$ value $end
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 $upscope $end
 $scope struct src $end
-$var wire 6 ]$ \[0] $end
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 $upscope $end
-$var wire 25 `$ imm_low $end
-$var wire 1 a$ imm_sign $end
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+$var wire 1 k# imm_sign $end
 $scope struct _phantom $end
 $upscope $end
 $upscope $end
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+$var string 1 l# output_integer_mode $end
 $upscope $end
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-$var wire 1 f$ add_pc $end
+$var wire 1 m# invert_src0 $end
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 $upscope $end
 $scope struct AddSubI $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 g$ prefix_pad $end
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 $scope struct dest $end
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 $upscope $end
 $scope struct src $end
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 $upscope $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
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 $upscope $end
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 $upscope $end
 $scope struct Logical $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 s$ prefix_pad $end
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 $scope struct dest $end
-$var wire 4 t$ value $end
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 $upscope $end
 $scope struct src $end
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 $upscope $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 z$ output_integer_mode $end
+$var string 1 &$ output_integer_mode $end
 $upscope $end
-$var wire 4 {$ lut $end
+$var wire 4 '$ lut $end
 $upscope $end
 $upscope $end
 $scope struct L2RegisterFile $end
-$var string 1 |$ \$tag $end
+$var string 1 ($ \$tag $end
 $scope struct ReadL2Reg $end
 $scope struct common $end
-$var wire 1 }$ prefix_pad $end
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 $scope struct dest $end
-$var wire 4 ~$ value $end
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 $upscope $end
 $scope struct src $end
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 $upscope $end
-$var wire 25 $% imm_low $end
-$var wire 1 %% imm_sign $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct WriteL2Reg $end
 $scope struct common $end
-$var wire 1 &% prefix_pad $end
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 $scope struct dest $end
-$var wire 4 '% value $end
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 $upscope $end
 $scope struct src $end
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 $upscope $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct LoadStore $end
-$var string 1 -% \$tag $end
+$var string 1 7$ \$tag $end
 $scope struct Load $end
-$var wire 1 .% prefix_pad $end
+$var wire 1 8$ prefix_pad $end
 $scope struct dest $end
-$var wire 4 /% value $end
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 $upscope $end
 $scope struct src $end
-$var wire 6 0% \[0] $end
-$var wire 6 1% \[1] $end
-$var wire 6 2% \[2] $end
+$var wire 6 :$ \[0] $end
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+$var wire 6 <$ \[2] $end
 $upscope $end
-$var wire 25 3% imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
 $scope struct Store $end
-$var wire 1 5% prefix_pad $end
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 $scope struct dest $end
-$var wire 4 6% value $end
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 $upscope $end
 $scope struct src $end
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 $upscope $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
@@ -3731,147 +3479,147 @@ $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
-$var string 1 <% \$tag $end
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 $scope struct HdlSome $end
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 $scope struct AluBranch $end
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 $scope struct AddSub $end
 $scope struct alu_common $end
 $scope struct common $end
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 $scope struct dest $end
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 $upscope $end
 $scope struct src $end
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 $upscope $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
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 $upscope $end
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 $upscope $end
 $scope struct AddSubI $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 K% prefix_pad $end
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 $scope struct dest $end
-$var wire 4 L% value $end
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 $upscope $end
 $scope struct src $end
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@@ -3881,215 +3629,146 @@ $upscope $end
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@@ -4098,20 +3777,20 @@ $upscope $end
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@@ -4120,20 +3799,20 @@ $upscope $end
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@@ -4142,362 +3821,431 @@ $upscope $end
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 $scope struct common $end
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 $scope struct dest $end
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 $upscope $end
 $scope struct src $end
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 $scope struct _phantom $end
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 $scope struct mapped_regs_4 $end
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 $scope struct Load $end
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 $scope struct dest $end
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 $upscope $end
 $scope struct src $end
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 $upscope $end
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 $scope struct _phantom $end
 $upscope $end
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 $scope struct dest $end
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 $upscope $end
 $scope struct src $end
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 $upscope $end
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 $scope struct _phantom $end
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 $upscope $end
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 $scope struct unit_num $end
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 $upscope $end
 $scope struct unit_out_reg $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct dest_reg_5 $end
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 $scope struct \[0] $end
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 $upscope $end
 $scope struct \[1] $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
@@ -4506,20 +4254,20 @@ $upscope $end
 $scope struct dest_reg_6 $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 B( value $end
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 $upscope $end
 $scope struct \[1] $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 D( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
@@ -4528,20 +4276,20 @@ $upscope $end
 $scope struct dest_reg_7 $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 F( value $end
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 $upscope $end
 $scope struct \[1] $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 H( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
-$var string 1 I( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
@@ -4550,48 +4298,64 @@ $upscope $end
 $scope struct dest_reg_8 $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 J( value $end
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 $upscope $end
 $scope struct \[1] $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 L( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
-$var string 1 M( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
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+$upscope $end
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 $upscope $end
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 $upscope $end
 $scope struct dest_reg_9 $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 P( value $end
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 $upscope $end
 $scope struct \[1] $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 R( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
-$var string 1 S( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
@@ -4600,20 +4364,20 @@ $upscope $end
 $scope struct dest_reg_10 $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 T( value $end
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 $upscope $end
 $scope struct \[1] $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 V( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
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+$var string 1 [' \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
@@ -4622,20 +4386,20 @@ $upscope $end
 $scope struct dest_reg_11 $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 X( value $end
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 $upscope $end
 $scope struct \[1] $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 Z( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
-$var string 1 [( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
@@ -4644,61 +4408,64 @@ $upscope $end
 $scope struct dest_reg_12 $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 \( value $end
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 $upscope $end
 $scope struct \[1] $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 ^( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
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 $upscope $end
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 $upscope $end
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 $scope struct addr $end
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 $upscope $end
 $scope struct data $end
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 $scope struct unit_num $end
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 $upscope $end
 $scope struct unit_out_reg $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct dest_reg_13 $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 e( value $end
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 $upscope $end
 $scope struct \[1] $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 g( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
@@ -4707,20 +4474,20 @@ $upscope $end
 $scope struct dest_reg_14 $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 i( value $end
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 $upscope $end
 $scope struct \[1] $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 k( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
@@ -4729,20 +4496,20 @@ $upscope $end
 $scope struct dest_reg_15 $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 m( value $end
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 $upscope $end
 $scope struct \[1] $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 o( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
-$var string 1 p( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
@@ -4751,48 +4518,64 @@ $upscope $end
 $scope struct dest_reg_16 $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 q( value $end
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 $upscope $end
 $scope struct \[1] $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 s( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
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 $upscope $end
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 $upscope $end
 $scope struct dest_reg_17 $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
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 $upscope $end
 $scope struct \[1] $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
@@ -4801,20 +4584,20 @@ $upscope $end
 $scope struct dest_reg_18 $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 {( value $end
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 $upscope $end
 $scope struct \[1] $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 }( \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
@@ -4823,20 +4606,20 @@ $upscope $end
 $scope struct dest_reg_19 $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 !) value $end
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 $upscope $end
 $scope struct \[1] $end
-$var wire 8 ") value $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 #) \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
-$var string 1 $) \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
@@ -4845,61 +4628,64 @@ $upscope $end
 $scope struct dest_reg_20 $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 %) value $end
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 $upscope $end
 $scope struct \[1] $end
-$var wire 8 &) value $end
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 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 ') \$tag $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
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 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
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 $upscope $end
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 $upscope $end
-$scope struct rename_1_src_2 $end
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 $scope struct addr $end
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 $upscope $end
 $scope struct data $end
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 $scope struct unit_num $end
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@@ -4908,20 +4694,20 @@ $upscope $end
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@@ -4930,20 +4716,20 @@ $upscope $end
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@@ -4952,48 +4738,64 @@ $upscope $end
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@@ -5002,20 +4804,20 @@ $upscope $end
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@@ -5024,20 +4826,20 @@ $upscope $end
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@@ -5046,179 +4848,53 @@ $upscope $end
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@@ -5227,20 +4903,20 @@ $upscope $end
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@@ -5249,20 +4925,20 @@ $upscope $end
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@@ -5271,1569 +4947,1847 @@ $upscope $end
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 $scope struct AddSub $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 A- prefix_pad $end
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 $upscope $end
-$var wire 25 F- imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 H- output_integer_mode $end
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-$var wire 1 L- add_pc $end
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 $scope struct common $end
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 $upscope $end
-$var wire 25 R- imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 T- output_integer_mode $end
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 $upscope $end
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-$var wire 1 X- add_pc $end
+$var wire 1 I, invert_src0 $end
+$var wire 1 J, invert_carry_in $end
+$var wire 1 K, invert_carry_out $end
+$var wire 1 L, add_pc $end
 $upscope $end
 $scope struct Logical $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 Y- prefix_pad $end
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 $scope struct dest $end
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 $upscope $end
 $scope struct src $end
-$var wire 6 [- \[0] $end
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 $upscope $end
-$var wire 25 ^- imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 `- output_integer_mode $end
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 $upscope $end
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 $upscope $end
 $upscope $end
 $scope struct alu_branch_mop $end
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 $upscope $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
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 $upscope $end
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 $upscope $end
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 $upscope $end
 $upscope $end
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 $upscope $end
 $scope struct Logical $end
 $scope struct alu_common $end
 $scope struct common $end
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 $scope struct src $end
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 $upscope $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 %. output_integer_mode $end
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 $upscope $end
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 $upscope $end
 $upscope $end
 $scope struct and_then_out_2 $end
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 $scope struct common $end
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 $upscope $end
 $scope struct src $end
-$var wire 6 +. \[0] $end
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 $upscope $end
-$var wire 25 .. imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 0. output_integer_mode $end
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 $upscope $end
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-$var wire 1 4. add_pc $end
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 $upscope $end
 $scope struct AddSubI $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 5. prefix_pad $end
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 $upscope $end
 $scope struct src $end
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 $upscope $end
-$var wire 25 :. imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 <. output_integer_mode $end
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 $upscope $end
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 $upscope $end
 $scope struct Logical $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 A. prefix_pad $end
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 $scope struct dest $end
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 $upscope $end
 $scope struct src $end
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 $upscope $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 H. output_integer_mode $end
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 $upscope $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct alu_branch_mop_2 $end
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 $scope struct HdlSome $end
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 $scope struct AddSub $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 L. prefix_pad $end
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 $scope struct dest $end
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 $upscope $end
 $scope struct src $end
-$var wire 6 N. \[0] $end
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 $upscope $end
-$var wire 25 Q. imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 S. output_integer_mode $end
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 $upscope $end
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 $upscope $end
 $scope struct AddSubI $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 X. prefix_pad $end
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 $scope struct dest $end
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 $upscope $end
 $scope struct src $end
-$var wire 6 Z. \[0] $end
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 $upscope $end
-$var wire 25 ]. imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 _. output_integer_mode $end
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 $upscope $end
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 $upscope $end
 $scope struct Logical $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 d. prefix_pad $end
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 $scope struct dest $end
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 $upscope $end
 $scope struct src $end
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 $upscope $end
-$var wire 25 i. imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 k. output_integer_mode $end
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 $upscope $end
-$var wire 4 l. lut $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct unit_1 $end
 $scope struct cd $end
-$var wire 1 5/ clk $end
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 $upscope $end
 $scope struct input $end
 $scope struct data $end
-$var string 1 7/ \$tag $end
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 $scope struct HdlSome $end
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 $scope struct AddSub $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 9/ prefix_pad $end
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 $scope struct dest $end
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 $upscope $end
 $scope struct src $end
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 $upscope $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
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 $upscope $end
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 $upscope $end
 $scope struct AddSubI $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 E/ prefix_pad $end
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 $scope struct dest $end
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 $upscope $end
 $scope struct src $end
-$var wire 6 G/ \[0] $end
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 $upscope $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
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 $upscope $end
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+$var wire 1 C. invert_carry_out $end
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 $upscope $end
 $scope struct Logical $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 Q/ prefix_pad $end
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 $scope struct dest $end
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 $upscope $end
 $scope struct src $end
-$var wire 6 S/ \[0] $end
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 $upscope $end
-$var wire 25 V/ imm_low $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
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 $upscope $end
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 $upscope $end
 $upscope $end
 $upscope $end
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 $upscope $end
 $scope module alu_branch_2 $end
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-$var wire 1 m. clk $end
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 $upscope $end
 $scope struct input $end
 $scope struct data $end
-$var string 1 o. \$tag $end
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 $scope struct HdlSome $end
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 $scope struct common $end
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 $scope struct dest $end
-$var wire 4 r. value $end
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 $upscope $end
 $scope struct src $end
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 $upscope $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
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 $upscope $end
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 $upscope $end
 $scope struct AddSubI $end
 $scope struct alu_common $end
 $scope struct common $end
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 $scope struct dest $end
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 $upscope $end
 $scope struct src $end
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 $upscope $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
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 $upscope $end
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 $upscope $end
 $scope struct Logical $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 +/ prefix_pad $end
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 $scope struct dest $end
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 $upscope $end
 $scope struct src $end
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 $upscope $end
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 $scope struct _phantom $end
 $upscope $end
 $upscope $end
-$var string 1 2/ output_integer_mode $end
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 $upscope $end
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 $upscope $end
 $upscope $end
 $upscope $end
-$var wire 1 4/ ready $end
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 $upscope $end
 $upscope $end
 $scope struct unit_1_free_regs_tracker $end
 $scope struct cd $end
-$var wire 1 F0 clk $end
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 $upscope $end
 $scope struct free_in $end
 $scope struct \[0] $end
 $scope struct data $end
-$var string 1 H0 \$tag $end
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 $upscope $end
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 $upscope $end
 $upscope $end
 $scope struct alloc_out $end
 $scope struct \[0] $end
 $scope struct data $end
-$var string 1 K0 \$tag $end
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 $upscope $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope module unit_free_regs_tracker_2 $end
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-$var wire 1 [/ clk $end
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 $upscope $end
 $scope struct free_in $end
 $scope struct \[0] $end
 $scope struct data $end
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 $upscope $end
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 $upscope $end
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 $scope struct alloc_out $end
 $scope struct \[0] $end
 $scope struct data $end
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 $scope struct allocated_reg $end
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-$var reg 1 h/ \[5] $end
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-$var reg 1 j/ \[7] $end
-$var reg 1 k/ \[8] $end
-$var reg 1 l/ \[9] $end
-$var reg 1 m/ \[10] $end
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-$var reg 1 o/ \[12] $end
-$var reg 1 p/ \[13] $end
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 $upscope $end
 $scope struct firing_data $end
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 $upscope $end
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 $scope struct reduced_alloc_nums_0_2 $end
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 $upscope $end
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 $scope struct reduced_alloc_nums_2_4 $end
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 $scope struct reduced_alloc_nums_0_4 $end
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 $scope struct reduced_alloc_nums_4_6 $end
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 $scope struct reduced_alloc_nums_6_8 $end
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 $scope struct reduced_alloc_nums_4_8 $end
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 $scope struct reduced_alloc_nums_0_8 $end
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 $scope struct reduced_alloc_nums_8_10 $end
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 $scope struct reduced_alloc_nums_10_12 $end
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 $scope struct reduced_alloc_nums_8_12 $end
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 $scope struct reduced_alloc_nums_12_14 $end
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 $scope struct reduced_alloc_nums_14_16 $end
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 $scope struct reduced_alloc_nums_12_16 $end
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 #20000000
diff --git a/crates/cpu/tests/reg_alloc.rs b/crates/cpu/tests/reg_alloc.rs
index 2d6ae29..552a6dd 100644
--- a/crates/cpu/tests/reg_alloc.rs
+++ b/crates/cpu/tests/reg_alloc.rs
@@ -155,51 +155,41 @@ circuit reg_alloc:
     type Ty24 = {value: UInt<4>}
     type Ty25 = {unit_num: Ty23, unit_out_reg: Ty24}
     type Ty26 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: Ty25}
-    type Ty27 = {adj_value: UInt<1>}
-    type Ty28 = {value: UInt<1>}
-    type Ty29 = {unit_num: Ty27, unit_out_reg: Ty28}
-    type Ty30 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: Ty25, mask: Ty29}
-    type Ty31 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: UInt<2>}
-    type Ty32 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: UInt<2>, mask: UInt<1>}
-    type Ty33 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: UInt<4>}
-    type Ty34 = {addr: UInt<8>, en: UInt<1>, clk: Clock, data: UInt<4>, mask: UInt<1>}
-    type Ty35 = {addr: UInt<1>, en: UInt<1>, clk: Clock, flip data: Ty25}
-    type Ty36 = {addr: UInt<1>, en: UInt<1>, clk: Clock, data: Ty25, mask: Ty29}
-    type Ty37 = {addr: UInt<1>, en: UInt<1>, clk: Clock, flip data: UInt<2>}
-    type Ty38 = {addr: UInt<1>, en: UInt<1>, clk: Clock, data: UInt<2>, mask: UInt<1>}
-    type Ty39 = {addr: UInt<1>, en: UInt<1>, clk: Clock, flip data: UInt<4>}
-    type Ty40 = {addr: UInt<1>, en: UInt<1>, clk: Clock, data: UInt<4>, mask: UInt<1>}
-    type Ty41 = {|HdlNone, HdlSome: UInt<2>|}
-    type Ty42 = {prefix_pad: UInt<0>, dest: Ty24, src: UInt<6>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty2}
-    type Ty43 = {common: Ty42, output_integer_mode: Ty6}
-    type Ty44 = {alu_common: Ty43, invert_src0: UInt<1>, invert_carry_in: UInt<1>, invert_carry_out: UInt<1>, add_pc: UInt<1>}
-    type Ty45 = {alu_common: Ty43, lut: UInt<4>}
-    type Ty46 = {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}
-    type Ty47 = {prefix_pad: UInt<1>, dest: Ty24, src: UInt<6>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty2}
-    type Ty48 = {common: Ty47}
-    type Ty49 = {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}
-    type Ty50 = {|Load: Ty47, Store: Ty47|}
-    type Ty51 = {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}
-    type Ty52 = {|HdlNone, HdlSome: Ty51|}
-    type Ty53 = {|HdlNone, HdlSome: Ty25|}
-    type Ty54 = {addr: Ty1, flip data: Ty25}
-    type Ty55 = {addr: UInt<0>, en: UInt<1>, clk: Clock, data: Ty25, mask: Ty29}
-    type Ty56 = {|AluBranch, L2RegisterFile, LoadStore|}
-    type Ty57 = {unit_num: UInt<2>, unit_out_reg: UInt<4>}
-    type Ty58 = {imm_low: UInt<25>, reversed_src: UInt<8>[0], imm_sign: SInt<1>}
-    type Ty59 = {imm_low: UInt<25>, reversed_src: UInt<0>, imm_sign: UInt<1>}
-    type Ty60 = {imm_low: UInt<25>, reversed_src: UInt<8>[1], imm_sign: SInt<1>}
-    type Ty61 = {imm_low: UInt<25>, reversed_src: UInt<8>, imm_sign: UInt<1>}
-    type Ty62 = {|HdlNone, HdlSome: Ty46|}
-    type Ty63 = {data: Ty62, flip ready: UInt<1>}
-    type Ty64 = {flip cd: Ty0, flip `input`: Ty63}
-    type Ty65 = {|HdlNone, HdlSome: UInt<4>|}
-    type Ty66 = {data: Ty65, flip ready: UInt<1>}
-    type Ty67 = {flip cd: Ty0, flip free_in: Ty66[1], alloc_out: Ty66[1]}
-    module reg_alloc: @[reg_alloc.rs 48:1]
-        input cd: Ty0 @[reg_alloc.rs 52:29]
-        input fetch_decode_interface: Ty22 @[reg_alloc.rs 55:11]
-        mem rename_table_normal_mem_unit_num_adj_value: @[reg_alloc.rs 73:25]
+    type Ty27 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: UInt<2>}
+    type Ty28 = {addr: UInt<8>, en: UInt<1>, clk: Clock, flip data: UInt<4>}
+    type Ty29 = {addr: UInt<1>, en: UInt<1>, clk: Clock, flip data: Ty25}
+    type Ty30 = {addr: UInt<1>, en: UInt<1>, clk: Clock, flip data: UInt<2>}
+    type Ty31 = {addr: UInt<1>, en: UInt<1>, clk: Clock, flip data: UInt<4>}
+    type Ty32 = {|HdlNone, HdlSome: UInt<2>|}
+    type Ty33 = {prefix_pad: UInt<0>, dest: Ty24, src: UInt<6>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty2}
+    type Ty34 = {common: Ty33, output_integer_mode: Ty6}
+    type Ty35 = {alu_common: Ty34, invert_src0: UInt<1>, invert_carry_in: UInt<1>, invert_carry_out: UInt<1>, add_pc: UInt<1>}
+    type Ty36 = {alu_common: Ty34, lut: UInt<4>}
+    type Ty37 = {|AddSub: Ty35, AddSubI: Ty35, Logical: Ty36|}
+    type Ty38 = {prefix_pad: UInt<1>, dest: Ty24, src: UInt<6>[3], imm_low: UInt<25>, imm_sign: SInt<1>, _phantom: Ty2}
+    type Ty39 = {common: Ty38}
+    type Ty40 = {|ReadL2Reg: Ty39, WriteL2Reg: Ty39|}
+    type Ty41 = {|Load: Ty38, Store: Ty38|}
+    type Ty42 = {|AluBranch: Ty37, L2RegisterFile: Ty40, LoadStore: Ty41|}
+    type Ty43 = {|HdlNone, HdlSome: Ty42|}
+    type Ty44 = {|HdlNone, HdlSome: Ty25|}
+    type Ty45 = {addr: Ty1, flip data: Ty44}
+    type Ty46 = {|AluBranch, L2RegisterFile, LoadStore|}
+    type Ty47 = {unit_num: UInt<2>, unit_out_reg: UInt<4>}
+    type Ty48 = {imm_low: UInt<25>, reversed_src: UInt<8>[0], imm_sign: SInt<1>}
+    type Ty49 = {imm_low: UInt<25>, reversed_src: UInt<0>, imm_sign: UInt<1>}
+    type Ty50 = {imm_low: UInt<25>, reversed_src: UInt<8>[1], imm_sign: SInt<1>}
+    type Ty51 = {imm_low: UInt<25>, reversed_src: UInt<8>, imm_sign: UInt<1>}
+    type Ty52 = {|HdlNone, HdlSome: Ty37|}
+    type Ty53 = {data: Ty52, flip ready: UInt<1>}
+    type Ty54 = {flip cd: Ty0, flip `input`: Ty53}
+    type Ty55 = {|HdlNone, HdlSome: UInt<4>|}
+    type Ty56 = {data: Ty55, flip ready: UInt<1>}
+    type Ty57 = {flip cd: Ty0, flip free_in: Ty56[1], alloc_out: Ty56[1]}
+    module reg_alloc: @[reg_alloc.rs 43:1]
+        input cd: Ty0 @[reg_alloc.rs 47:29]
+        input fetch_decode_interface: Ty22 @[reg_alloc.rs 50:11]
+        mem rename_table_normal_mem_unit_num_adj_value: @[reg_alloc.rs 60:39]
             data-type => UInt<2>
             depth => 253
             read-latency => 0
@@ -208,14 +198,10 @@ circuit reg_alloc:
             reader => r0
             reader => r1
             reader => r2
+            reader => r3
+            reader => r4
             reader => r5
-            reader => r6
-            reader => r7
-            writer => w3
-            writer => w4
-            writer => w8
-            writer => w9
-        mem rename_table_normal_mem_unit_out_reg_value: @[reg_alloc.rs 73:25]
+        mem rename_table_normal_mem_unit_out_reg_value: @[reg_alloc.rs 60:39]
             data-type => UInt<4>
             depth => 253
             read-latency => 0
@@ -224,14 +210,10 @@ circuit reg_alloc:
             reader => r0
             reader => r1
             reader => r2
+            reader => r3
+            reader => r4
             reader => r5
-            reader => r6
-            reader => r7
-            writer => w3
-            writer => w4
-            writer => w8
-            writer => w9
-        mem rename_table_special_mem_unit_num_adj_value: @[reg_alloc.rs 73:25]
+        mem rename_table_special_mem_unit_num_adj_value: @[reg_alloc.rs 65:40]
             data-type => UInt<2>
             depth => 2
             read-latency => 0
@@ -240,18 +222,10 @@ circuit reg_alloc:
             reader => r0
             reader => r1
             reader => r2
-            reader => r7
-            reader => r8
-            reader => r9
-            writer => w3
-            writer => w4
-            writer => w5
-            writer => w6
-            writer => w10
-            writer => w11
-            writer => w12
-            writer => w13
-        mem rename_table_special_mem_unit_out_reg_value: @[reg_alloc.rs 73:25]
+            reader => r3
+            reader => r4
+            reader => r5
+        mem rename_table_special_mem_unit_out_reg_value: @[reg_alloc.rs 65:40]
             data-type => UInt<4>
             depth => 2
             read-latency => 0
@@ -260,504 +234,232 @@ circuit reg_alloc:
             reader => r0
             reader => r1
             reader => r2
-            reader => r7
-            reader => r8
-            reader => r9
-            writer => w3
-            writer => w4
-            writer => w5
-            writer => w6
-            writer => w10
-            writer => w11
-            writer => w12
-            writer => w13
-        wire rename_table_normal_mem_r0: Ty26 @[reg_alloc.rs 120:37]
-        wire rename_table_normal_mem_r1: Ty26 @[reg_alloc.rs 120:37]
-        wire rename_table_normal_mem_r2: Ty26 @[reg_alloc.rs 120:37]
-        wire rename_table_normal_mem_w3: Ty30 @[reg_alloc.rs 167:39]
-        wire rename_table_normal_mem_w4: Ty30 @[reg_alloc.rs 167:39]
-        wire rename_table_normal_mem_r5: Ty26 @[reg_alloc.rs 120:37]
-        wire rename_table_normal_mem_r6: Ty26 @[reg_alloc.rs 120:37]
-        wire rename_table_normal_mem_r7: Ty26 @[reg_alloc.rs 120:37]
-        wire rename_table_normal_mem_w8: Ty30 @[reg_alloc.rs 167:39]
-        wire rename_table_normal_mem_w9: Ty30 @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_r0.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r0.data @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_r1.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r1.data @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_r2.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r2.data @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.w3.data, rename_table_normal_mem_w3.data.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w3.mask, rename_table_normal_mem_w3.mask.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w4.data, rename_table_normal_mem_w4.data.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w4.mask, rename_table_normal_mem_w4.mask.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_r5.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r5.data @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_r6.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r6.data @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_r7.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r7.data @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.w8.data, rename_table_normal_mem_w8.data.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w8.mask, rename_table_normal_mem_w8.mask.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w9.data, rename_table_normal_mem_w9.data.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w9.mask, rename_table_normal_mem_w9.mask.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.r0.addr, rename_table_normal_mem_r0.addr @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r0.clk, rename_table_normal_mem_r0.clk @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r0.en, rename_table_normal_mem_r0.en @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r1.addr, rename_table_normal_mem_r1.addr @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r1.clk, rename_table_normal_mem_r1.clk @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r1.en, rename_table_normal_mem_r1.en @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r2.addr, rename_table_normal_mem_r2.addr @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r2.clk, rename_table_normal_mem_r2.clk @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r2.en, rename_table_normal_mem_r2.en @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.w3.addr, rename_table_normal_mem_w3.addr @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w3.clk, rename_table_normal_mem_w3.clk @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w3.en, rename_table_normal_mem_w3.en @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w4.addr, rename_table_normal_mem_w4.addr @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w4.clk, rename_table_normal_mem_w4.clk @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w4.en, rename_table_normal_mem_w4.en @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.r5.addr, rename_table_normal_mem_r5.addr @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r5.clk, rename_table_normal_mem_r5.clk @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r5.en, rename_table_normal_mem_r5.en @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r6.addr, rename_table_normal_mem_r6.addr @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r6.clk, rename_table_normal_mem_r6.clk @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r6.en, rename_table_normal_mem_r6.en @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r7.addr, rename_table_normal_mem_r7.addr @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r7.clk, rename_table_normal_mem_r7.clk @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.r7.en, rename_table_normal_mem_r7.en @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_num_adj_value.w8.addr, rename_table_normal_mem_w8.addr @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w8.clk, rename_table_normal_mem_w8.clk @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w8.en, rename_table_normal_mem_w8.en @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w9.addr, rename_table_normal_mem_w9.addr @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w9.clk, rename_table_normal_mem_w9.clk @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_num_adj_value.w9.en, rename_table_normal_mem_w9.en @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_r0.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r0.data @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_r1.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r1.data @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_r2.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r2.data @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.w3.data, rename_table_normal_mem_w3.data.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w3.mask, rename_table_normal_mem_w3.mask.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w4.data, rename_table_normal_mem_w4.data.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w4.mask, rename_table_normal_mem_w4.mask.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_r5.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r5.data @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_r6.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r6.data @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_r7.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r7.data @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.w8.data, rename_table_normal_mem_w8.data.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w8.mask, rename_table_normal_mem_w8.mask.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w9.data, rename_table_normal_mem_w9.data.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w9.mask, rename_table_normal_mem_w9.mask.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.r0.addr, rename_table_normal_mem_r0.addr @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r0.clk, rename_table_normal_mem_r0.clk @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r0.en, rename_table_normal_mem_r0.en @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r1.addr, rename_table_normal_mem_r1.addr @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r1.clk, rename_table_normal_mem_r1.clk @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r1.en, rename_table_normal_mem_r1.en @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r2.addr, rename_table_normal_mem_r2.addr @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r2.clk, rename_table_normal_mem_r2.clk @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r2.en, rename_table_normal_mem_r2.en @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.w3.addr, rename_table_normal_mem_w3.addr @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w3.clk, rename_table_normal_mem_w3.clk @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w3.en, rename_table_normal_mem_w3.en @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w4.addr, rename_table_normal_mem_w4.addr @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w4.clk, rename_table_normal_mem_w4.clk @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w4.en, rename_table_normal_mem_w4.en @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.r5.addr, rename_table_normal_mem_r5.addr @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r5.clk, rename_table_normal_mem_r5.clk @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r5.en, rename_table_normal_mem_r5.en @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r6.addr, rename_table_normal_mem_r6.addr @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r6.clk, rename_table_normal_mem_r6.clk @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r6.en, rename_table_normal_mem_r6.en @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r7.addr, rename_table_normal_mem_r7.addr @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r7.clk, rename_table_normal_mem_r7.clk @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.r7.en, rename_table_normal_mem_r7.en @[reg_alloc.rs 120:37]
-        connect rename_table_normal_mem_unit_out_reg_value.w8.addr, rename_table_normal_mem_w8.addr @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w8.clk, rename_table_normal_mem_w8.clk @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w8.en, rename_table_normal_mem_w8.en @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w9.addr, rename_table_normal_mem_w9.addr @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w9.clk, rename_table_normal_mem_w9.clk @[reg_alloc.rs 167:39]
-        connect rename_table_normal_mem_unit_out_reg_value.w9.en, rename_table_normal_mem_w9.en @[reg_alloc.rs 167:39]
-        wire rename_table_special_mem_r0: Ty35 @[reg_alloc.rs 120:37]
-        wire rename_table_special_mem_r1: Ty35 @[reg_alloc.rs 120:37]
-        wire rename_table_special_mem_r2: Ty35 @[reg_alloc.rs 120:37]
-        wire rename_table_special_mem_w3: Ty36 @[reg_alloc.rs 167:39]
-        wire rename_table_special_mem_w4: Ty36 @[reg_alloc.rs 167:39]
-        wire rename_table_special_mem_w5: Ty36 @[reg_alloc.rs 167:39]
-        wire rename_table_special_mem_w6: Ty36 @[reg_alloc.rs 167:39]
-        wire rename_table_special_mem_r7: Ty35 @[reg_alloc.rs 120:37]
-        wire rename_table_special_mem_r8: Ty35 @[reg_alloc.rs 120:37]
-        wire rename_table_special_mem_r9: Ty35 @[reg_alloc.rs 120:37]
-        wire rename_table_special_mem_w10: Ty36 @[reg_alloc.rs 167:39]
-        wire rename_table_special_mem_w11: Ty36 @[reg_alloc.rs 167:39]
-        wire rename_table_special_mem_w12: Ty36 @[reg_alloc.rs 167:39]
-        wire rename_table_special_mem_w13: Ty36 @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_r0.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r0.data @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_r1.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r1.data @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_r2.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r2.data @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.w3.data, rename_table_special_mem_w3.data.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w3.mask, rename_table_special_mem_w3.mask.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w4.data, rename_table_special_mem_w4.data.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w4.mask, rename_table_special_mem_w4.mask.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w5.data, rename_table_special_mem_w5.data.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w5.mask, rename_table_special_mem_w5.mask.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w6.data, rename_table_special_mem_w6.data.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w6.mask, rename_table_special_mem_w6.mask.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_r7.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r7.data @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_r8.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r8.data @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_r9.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r9.data @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.w10.data, rename_table_special_mem_w10.data.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w10.mask, rename_table_special_mem_w10.mask.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w11.data, rename_table_special_mem_w11.data.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w11.mask, rename_table_special_mem_w11.mask.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w12.data, rename_table_special_mem_w12.data.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w12.mask, rename_table_special_mem_w12.mask.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w13.data, rename_table_special_mem_w13.data.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w13.mask, rename_table_special_mem_w13.mask.unit_num.adj_value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.r0.addr, rename_table_special_mem_r0.addr @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r0.clk, rename_table_special_mem_r0.clk @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r0.en, rename_table_special_mem_r0.en @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r1.addr, rename_table_special_mem_r1.addr @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r1.clk, rename_table_special_mem_r1.clk @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r1.en, rename_table_special_mem_r1.en @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r2.addr, rename_table_special_mem_r2.addr @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r2.clk, rename_table_special_mem_r2.clk @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r2.en, rename_table_special_mem_r2.en @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.w3.addr, rename_table_special_mem_w3.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w3.clk, rename_table_special_mem_w3.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w3.en, rename_table_special_mem_w3.en @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w4.addr, rename_table_special_mem_w4.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w4.clk, rename_table_special_mem_w4.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w4.en, rename_table_special_mem_w4.en @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w5.addr, rename_table_special_mem_w5.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w5.clk, rename_table_special_mem_w5.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w5.en, rename_table_special_mem_w5.en @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w6.addr, rename_table_special_mem_w6.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w6.clk, rename_table_special_mem_w6.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w6.en, rename_table_special_mem_w6.en @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.r7.addr, rename_table_special_mem_r7.addr @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r7.clk, rename_table_special_mem_r7.clk @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r7.en, rename_table_special_mem_r7.en @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r8.addr, rename_table_special_mem_r8.addr @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r8.clk, rename_table_special_mem_r8.clk @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r8.en, rename_table_special_mem_r8.en @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r9.addr, rename_table_special_mem_r9.addr @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r9.clk, rename_table_special_mem_r9.clk @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.r9.en, rename_table_special_mem_r9.en @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_num_adj_value.w10.addr, rename_table_special_mem_w10.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w10.clk, rename_table_special_mem_w10.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w10.en, rename_table_special_mem_w10.en @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w11.addr, rename_table_special_mem_w11.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w11.clk, rename_table_special_mem_w11.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w11.en, rename_table_special_mem_w11.en @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w12.addr, rename_table_special_mem_w12.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w12.clk, rename_table_special_mem_w12.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w12.en, rename_table_special_mem_w12.en @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w13.addr, rename_table_special_mem_w13.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w13.clk, rename_table_special_mem_w13.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_num_adj_value.w13.en, rename_table_special_mem_w13.en @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_r0.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r0.data @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_r1.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r1.data @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_r2.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r2.data @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.w3.data, rename_table_special_mem_w3.data.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w3.mask, rename_table_special_mem_w3.mask.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w4.data, rename_table_special_mem_w4.data.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w4.mask, rename_table_special_mem_w4.mask.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w5.data, rename_table_special_mem_w5.data.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w5.mask, rename_table_special_mem_w5.mask.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w6.data, rename_table_special_mem_w6.data.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w6.mask, rename_table_special_mem_w6.mask.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_r7.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r7.data @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_r8.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r8.data @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_r9.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r9.data @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.w10.data, rename_table_special_mem_w10.data.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w10.mask, rename_table_special_mem_w10.mask.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w11.data, rename_table_special_mem_w11.data.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w11.mask, rename_table_special_mem_w11.mask.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w12.data, rename_table_special_mem_w12.data.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w12.mask, rename_table_special_mem_w12.mask.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w13.data, rename_table_special_mem_w13.data.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w13.mask, rename_table_special_mem_w13.mask.unit_out_reg.value @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.r0.addr, rename_table_special_mem_r0.addr @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r0.clk, rename_table_special_mem_r0.clk @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r0.en, rename_table_special_mem_r0.en @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r1.addr, rename_table_special_mem_r1.addr @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r1.clk, rename_table_special_mem_r1.clk @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r1.en, rename_table_special_mem_r1.en @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r2.addr, rename_table_special_mem_r2.addr @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r2.clk, rename_table_special_mem_r2.clk @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r2.en, rename_table_special_mem_r2.en @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.w3.addr, rename_table_special_mem_w3.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w3.clk, rename_table_special_mem_w3.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w3.en, rename_table_special_mem_w3.en @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w4.addr, rename_table_special_mem_w4.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w4.clk, rename_table_special_mem_w4.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w4.en, rename_table_special_mem_w4.en @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w5.addr, rename_table_special_mem_w5.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w5.clk, rename_table_special_mem_w5.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w5.en, rename_table_special_mem_w5.en @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w6.addr, rename_table_special_mem_w6.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w6.clk, rename_table_special_mem_w6.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w6.en, rename_table_special_mem_w6.en @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.r7.addr, rename_table_special_mem_r7.addr @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r7.clk, rename_table_special_mem_r7.clk @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r7.en, rename_table_special_mem_r7.en @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r8.addr, rename_table_special_mem_r8.addr @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r8.clk, rename_table_special_mem_r8.clk @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r8.en, rename_table_special_mem_r8.en @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r9.addr, rename_table_special_mem_r9.addr @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r9.clk, rename_table_special_mem_r9.clk @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.r9.en, rename_table_special_mem_r9.en @[reg_alloc.rs 120:37]
-        connect rename_table_special_mem_unit_out_reg_value.w10.addr, rename_table_special_mem_w10.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w10.clk, rename_table_special_mem_w10.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w10.en, rename_table_special_mem_w10.en @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w11.addr, rename_table_special_mem_w11.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w11.clk, rename_table_special_mem_w11.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w11.en, rename_table_special_mem_w11.en @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w12.addr, rename_table_special_mem_w12.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w12.clk, rename_table_special_mem_w12.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w12.en, rename_table_special_mem_w12.en @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w13.addr, rename_table_special_mem_w13.addr @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w13.clk, rename_table_special_mem_w13.clk @[reg_alloc.rs 167:39]
-        connect rename_table_special_mem_unit_out_reg_value.w13.en, rename_table_special_mem_w13.en @[reg_alloc.rs 167:39]
-        connect fetch_decode_interface.fetch_decode_special_op.data, {|HdlNone, HdlSome: Ty19|}(HdlNone) @[reg_alloc.rs 57:5]
-        wire available_units: UInt<1>[2][2] @[reg_alloc.rs 83:9]
-        wire selected_unit_indexes: Ty41[2] @[reg_alloc.rs 86:9]
-        wire renamed_mops: Ty52[2] @[reg_alloc.rs 88:24]
-        wire renamed_mops_out_reg: Ty53[2] @[reg_alloc.rs 90:32]
-        connect fetch_decode_interface.decoded_insns[0].ready, UInt<1>(0h1) @[reg_alloc.rs 92:9]
+            reader => r3
+            reader => r4
+            reader => r5
+        wire rename_table_normal_mem_r0: Ty26 @[reg_alloc.rs 102:37]
+        wire rename_table_normal_mem_r1: Ty26 @[reg_alloc.rs 102:37]
+        wire rename_table_normal_mem_r2: Ty26 @[reg_alloc.rs 102:37]
+        wire rename_table_normal_mem_r3: Ty26 @[reg_alloc.rs 102:37]
+        wire rename_table_normal_mem_r4: Ty26 @[reg_alloc.rs 102:37]
+        wire rename_table_normal_mem_r5: Ty26 @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_r0.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r0.data @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_r1.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r1.data @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_r2.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r2.data @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_r3.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r3.data @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_r4.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r4.data @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_r5.data.unit_num.adj_value, rename_table_normal_mem_unit_num_adj_value.r5.data @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r0.addr, rename_table_normal_mem_r0.addr @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r0.clk, rename_table_normal_mem_r0.clk @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r0.en, rename_table_normal_mem_r0.en @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r1.addr, rename_table_normal_mem_r1.addr @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r1.clk, rename_table_normal_mem_r1.clk @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r1.en, rename_table_normal_mem_r1.en @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r2.addr, rename_table_normal_mem_r2.addr @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r2.clk, rename_table_normal_mem_r2.clk @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r2.en, rename_table_normal_mem_r2.en @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r3.addr, rename_table_normal_mem_r3.addr @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r3.clk, rename_table_normal_mem_r3.clk @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r3.en, rename_table_normal_mem_r3.en @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r4.addr, rename_table_normal_mem_r4.addr @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r4.clk, rename_table_normal_mem_r4.clk @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r4.en, rename_table_normal_mem_r4.en @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r5.addr, rename_table_normal_mem_r5.addr @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r5.clk, rename_table_normal_mem_r5.clk @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_num_adj_value.r5.en, rename_table_normal_mem_r5.en @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_r0.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r0.data @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_r1.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r1.data @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_r2.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r2.data @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_r3.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r3.data @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_r4.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r4.data @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_r5.data.unit_out_reg.value, rename_table_normal_mem_unit_out_reg_value.r5.data @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r0.addr, rename_table_normal_mem_r0.addr @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r0.clk, rename_table_normal_mem_r0.clk @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r0.en, rename_table_normal_mem_r0.en @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r1.addr, rename_table_normal_mem_r1.addr @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r1.clk, rename_table_normal_mem_r1.clk @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r1.en, rename_table_normal_mem_r1.en @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r2.addr, rename_table_normal_mem_r2.addr @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r2.clk, rename_table_normal_mem_r2.clk @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r2.en, rename_table_normal_mem_r2.en @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r3.addr, rename_table_normal_mem_r3.addr @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r3.clk, rename_table_normal_mem_r3.clk @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r3.en, rename_table_normal_mem_r3.en @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r4.addr, rename_table_normal_mem_r4.addr @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r4.clk, rename_table_normal_mem_r4.clk @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r4.en, rename_table_normal_mem_r4.en @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r5.addr, rename_table_normal_mem_r5.addr @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r5.clk, rename_table_normal_mem_r5.clk @[reg_alloc.rs 102:37]
+        connect rename_table_normal_mem_unit_out_reg_value.r5.en, rename_table_normal_mem_r5.en @[reg_alloc.rs 102:37]
+        wire rename_table_special_mem_r0: Ty29 @[reg_alloc.rs 102:37]
+        wire rename_table_special_mem_r1: Ty29 @[reg_alloc.rs 102:37]
+        wire rename_table_special_mem_r2: Ty29 @[reg_alloc.rs 102:37]
+        wire rename_table_special_mem_r3: Ty29 @[reg_alloc.rs 102:37]
+        wire rename_table_special_mem_r4: Ty29 @[reg_alloc.rs 102:37]
+        wire rename_table_special_mem_r5: Ty29 @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_r0.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r0.data @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_r1.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r1.data @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_r2.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r2.data @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_r3.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r3.data @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_r4.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r4.data @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_r5.data.unit_num.adj_value, rename_table_special_mem_unit_num_adj_value.r5.data @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r0.addr, rename_table_special_mem_r0.addr @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r0.clk, rename_table_special_mem_r0.clk @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r0.en, rename_table_special_mem_r0.en @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r1.addr, rename_table_special_mem_r1.addr @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r1.clk, rename_table_special_mem_r1.clk @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r1.en, rename_table_special_mem_r1.en @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r2.addr, rename_table_special_mem_r2.addr @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r2.clk, rename_table_special_mem_r2.clk @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r2.en, rename_table_special_mem_r2.en @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r3.addr, rename_table_special_mem_r3.addr @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r3.clk, rename_table_special_mem_r3.clk @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r3.en, rename_table_special_mem_r3.en @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r4.addr, rename_table_special_mem_r4.addr @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r4.clk, rename_table_special_mem_r4.clk @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r4.en, rename_table_special_mem_r4.en @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r5.addr, rename_table_special_mem_r5.addr @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r5.clk, rename_table_special_mem_r5.clk @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_num_adj_value.r5.en, rename_table_special_mem_r5.en @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_r0.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r0.data @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_r1.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r1.data @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_r2.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r2.data @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_r3.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r3.data @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_r4.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r4.data @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_r5.data.unit_out_reg.value, rename_table_special_mem_unit_out_reg_value.r5.data @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r0.addr, rename_table_special_mem_r0.addr @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r0.clk, rename_table_special_mem_r0.clk @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r0.en, rename_table_special_mem_r0.en @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r1.addr, rename_table_special_mem_r1.addr @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r1.clk, rename_table_special_mem_r1.clk @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r1.en, rename_table_special_mem_r1.en @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r2.addr, rename_table_special_mem_r2.addr @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r2.clk, rename_table_special_mem_r2.clk @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r2.en, rename_table_special_mem_r2.en @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r3.addr, rename_table_special_mem_r3.addr @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r3.clk, rename_table_special_mem_r3.clk @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r3.en, rename_table_special_mem_r3.en @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r4.addr, rename_table_special_mem_r4.addr @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r4.clk, rename_table_special_mem_r4.clk @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r4.en, rename_table_special_mem_r4.en @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r5.addr, rename_table_special_mem_r5.addr @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r5.clk, rename_table_special_mem_r5.clk @[reg_alloc.rs 102:37]
+        connect rename_table_special_mem_unit_out_reg_value.r5.en, rename_table_special_mem_r5.en @[reg_alloc.rs 102:37]
+        connect fetch_decode_interface.fetch_decode_special_op.data, {|HdlNone, HdlSome: Ty19|}(HdlNone) @[reg_alloc.rs 52:5]
+        wire available_units: UInt<1>[2][2] @[reg_alloc.rs 70:9]
+        wire selected_unit_indexes: Ty32[2] @[reg_alloc.rs 73:9]
+        wire renamed_mops: Ty43[2] @[reg_alloc.rs 75:24]
+        wire renamed_mops_out_reg: Ty44[2] @[reg_alloc.rs 77:32]
+        connect fetch_decode_interface.decoded_insns[0].ready, UInt<1>(0h1) @[reg_alloc.rs 79:9]
         wire _array_literal_expr: UInt<1>[2]
         connect _array_literal_expr[0], UInt<1>(0h0)
         connect _array_literal_expr[1], UInt<1>(0h0)
-        connect available_units[0], _array_literal_expr @[reg_alloc.rs 96:9]
-        connect renamed_mops[0], {|HdlNone, HdlSome: Ty51|}(HdlNone) @[reg_alloc.rs 100:9]
-        wire rename_0_src_0: Ty54 @[reg_alloc.rs 113:17]
+        connect available_units[0], _array_literal_expr @[reg_alloc.rs 83:9]
+        connect renamed_mops[0], {|HdlNone, HdlSome: Ty42|}(HdlNone) @[reg_alloc.rs 87:9]
+        connect rename_table_normal_mem_r0.clk, cd.clk @[reg_alloc.rs 103:17]
+        connect rename_table_normal_mem_r0.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17]
+        connect rename_table_normal_mem_r0.en, UInt<1>(0h0) @[reg_alloc.rs 105:17]
+        wire rename_table_normal_0_src_0: Ty45 @[reg_alloc.rs 108:21]
         wire _bundle_literal_expr: Ty1
         connect _bundle_literal_expr.value, tail(UInt<32>(0h0), 24)
-        connect rename_0_src_0.addr, _bundle_literal_expr @[reg_alloc.rs 116:13]
-        wire _bundle_literal_expr_1: Ty25
-        wire _bundle_literal_expr_2: Ty23
-        connect _bundle_literal_expr_2.adj_value, tail(UInt<64>(0h0), 62)
-        connect _bundle_literal_expr_1.unit_num, _bundle_literal_expr_2
-        wire _bundle_literal_expr_3: Ty24
-        connect _bundle_literal_expr_3.value, tail(UInt<8>(0h0), 4)
-        connect _bundle_literal_expr_1.unit_out_reg, _bundle_literal_expr_3
-        connect rename_0_src_0.data, _bundle_literal_expr_1 @[reg_alloc.rs 117:13]
-        connect rename_table_normal_mem_r0.clk, cd.clk @[reg_alloc.rs 121:17]
-        connect rename_table_normal_mem_r0.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17]
-        connect rename_table_normal_mem_r0.en, UInt<1>(0h0) @[reg_alloc.rs 123:17]
-        when and(geq(rename_0_src_0.addr.value, UInt<32>(0h1)), lt(rename_0_src_0.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 126:17]
+        connect rename_table_normal_0_src_0.addr, _bundle_literal_expr @[reg_alloc.rs 111:17]
+        connect rename_table_normal_0_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17]
+        when and(geq(rename_table_normal_0_src_0.addr.value, UInt<32>(0h1)), lt(rename_table_normal_0_src_0.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 114:17]
             ; connect different types:
             ; lhs: UInt<8>
             ; rhs: UInt<33>
-            connect rename_table_normal_mem_r0.addr, sub(rename_0_src_0.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 127:21]
-            connect rename_table_normal_mem_r0.en, UInt<1>(0h1) @[reg_alloc.rs 128:21]
-            connect rename_0_src_0.data, rename_table_normal_mem_r0.data @[reg_alloc.rs 129:21]
-        connect rename_table_special_mem_r0.clk, cd.clk @[reg_alloc.rs 121:17]
+            connect rename_table_normal_mem_r0.addr, sub(rename_table_normal_0_src_0.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 115:21]
+            connect rename_table_normal_mem_r0.en, UInt<1>(0h1) @[reg_alloc.rs 116:21]
+            connect rename_table_normal_0_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_normal_mem_r0.data) @[reg_alloc.rs 117:21]
+        connect rename_table_normal_mem_r1.clk, cd.clk @[reg_alloc.rs 103:17]
+        connect rename_table_normal_mem_r1.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17]
+        connect rename_table_normal_mem_r1.en, UInt<1>(0h0) @[reg_alloc.rs 105:17]
+        wire rename_table_normal_0_src_1: Ty45 @[reg_alloc.rs 108:21]
+        wire _bundle_literal_expr_1: Ty1
+        connect _bundle_literal_expr_1.value, tail(UInt<32>(0h0), 24)
+        connect rename_table_normal_0_src_1.addr, _bundle_literal_expr_1 @[reg_alloc.rs 111:17]
+        connect rename_table_normal_0_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17]
+        when and(geq(rename_table_normal_0_src_1.addr.value, UInt<32>(0h1)), lt(rename_table_normal_0_src_1.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 114:17]
+            ; connect different types:
+            ; lhs: UInt<8>
+            ; rhs: UInt<33>
+            connect rename_table_normal_mem_r1.addr, sub(rename_table_normal_0_src_1.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 115:21]
+            connect rename_table_normal_mem_r1.en, UInt<1>(0h1) @[reg_alloc.rs 116:21]
+            connect rename_table_normal_0_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_normal_mem_r1.data) @[reg_alloc.rs 117:21]
+        connect rename_table_normal_mem_r2.clk, cd.clk @[reg_alloc.rs 103:17]
+        connect rename_table_normal_mem_r2.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17]
+        connect rename_table_normal_mem_r2.en, UInt<1>(0h0) @[reg_alloc.rs 105:17]
+        wire rename_table_normal_0_src_2: Ty45 @[reg_alloc.rs 108:21]
+        wire _bundle_literal_expr_2: Ty1
+        connect _bundle_literal_expr_2.value, tail(UInt<32>(0h0), 24)
+        connect rename_table_normal_0_src_2.addr, _bundle_literal_expr_2 @[reg_alloc.rs 111:17]
+        connect rename_table_normal_0_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17]
+        when and(geq(rename_table_normal_0_src_2.addr.value, UInt<32>(0h1)), lt(rename_table_normal_0_src_2.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 114:17]
+            ; connect different types:
+            ; lhs: UInt<8>
+            ; rhs: UInt<33>
+            connect rename_table_normal_mem_r2.addr, sub(rename_table_normal_0_src_2.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 115:21]
+            connect rename_table_normal_mem_r2.en, UInt<1>(0h1) @[reg_alloc.rs 116:21]
+            connect rename_table_normal_0_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_normal_mem_r2.data) @[reg_alloc.rs 117:21]
+        connect rename_table_special_mem_r0.clk, cd.clk @[reg_alloc.rs 103:17]
         ; connect different types:
         ; lhs: UInt<1>
         ; rhs: UInt<8>
-        connect rename_table_special_mem_r0.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17]
-        connect rename_table_special_mem_r0.en, UInt<1>(0h0) @[reg_alloc.rs 123:17]
-        when and(geq(rename_0_src_0.addr.value, UInt<32>(0hFE)), lt(rename_0_src_0.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 126:17]
+        connect rename_table_special_mem_r0.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17]
+        connect rename_table_special_mem_r0.en, UInt<1>(0h0) @[reg_alloc.rs 105:17]
+        wire rename_table_special_0_src_0: Ty45 @[reg_alloc.rs 108:21]
+        wire _bundle_literal_expr_3: Ty1
+        connect _bundle_literal_expr_3.value, tail(UInt<32>(0h0), 24)
+        connect rename_table_special_0_src_0.addr, _bundle_literal_expr_3 @[reg_alloc.rs 111:17]
+        connect rename_table_special_0_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17]
+        when and(geq(rename_table_special_0_src_0.addr.value, UInt<32>(0hFE)), lt(rename_table_special_0_src_0.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 114:17]
             ; connect different types:
             ; lhs: UInt<1>
             ; rhs: UInt<33>
-            connect rename_table_special_mem_r0.addr, sub(rename_0_src_0.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 127:21]
-            connect rename_table_special_mem_r0.en, UInt<1>(0h1) @[reg_alloc.rs 128:21]
-            connect rename_0_src_0.data, rename_table_special_mem_r0.data @[reg_alloc.rs 129:21]
-        wire rename_0_src_1: Ty54 @[reg_alloc.rs 113:17]
+            connect rename_table_special_mem_r0.addr, sub(rename_table_special_0_src_0.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 115:21]
+            connect rename_table_special_mem_r0.en, UInt<1>(0h1) @[reg_alloc.rs 116:21]
+            connect rename_table_special_0_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_special_mem_r0.data) @[reg_alloc.rs 117:21]
+        connect rename_table_special_mem_r1.clk, cd.clk @[reg_alloc.rs 103:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<8>
+        connect rename_table_special_mem_r1.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17]
+        connect rename_table_special_mem_r1.en, UInt<1>(0h0) @[reg_alloc.rs 105:17]
+        wire rename_table_special_0_src_1: Ty45 @[reg_alloc.rs 108:21]
         wire _bundle_literal_expr_4: Ty1
         connect _bundle_literal_expr_4.value, tail(UInt<32>(0h0), 24)
-        connect rename_0_src_1.addr, _bundle_literal_expr_4 @[reg_alloc.rs 116:13]
-        wire _bundle_literal_expr_5: Ty25
-        wire _bundle_literal_expr_6: Ty23
-        connect _bundle_literal_expr_6.adj_value, tail(UInt<64>(0h0), 62)
-        connect _bundle_literal_expr_5.unit_num, _bundle_literal_expr_6
-        wire _bundle_literal_expr_7: Ty24
-        connect _bundle_literal_expr_7.value, tail(UInt<8>(0h0), 4)
-        connect _bundle_literal_expr_5.unit_out_reg, _bundle_literal_expr_7
-        connect rename_0_src_1.data, _bundle_literal_expr_5 @[reg_alloc.rs 117:13]
-        connect rename_table_normal_mem_r1.clk, cd.clk @[reg_alloc.rs 121:17]
-        connect rename_table_normal_mem_r1.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17]
-        connect rename_table_normal_mem_r1.en, UInt<1>(0h0) @[reg_alloc.rs 123:17]
-        when and(geq(rename_0_src_1.addr.value, UInt<32>(0h1)), lt(rename_0_src_1.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 126:17]
-            ; connect different types:
-            ; lhs: UInt<8>
-            ; rhs: UInt<33>
-            connect rename_table_normal_mem_r1.addr, sub(rename_0_src_1.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 127:21]
-            connect rename_table_normal_mem_r1.en, UInt<1>(0h1) @[reg_alloc.rs 128:21]
-            connect rename_0_src_1.data, rename_table_normal_mem_r1.data @[reg_alloc.rs 129:21]
-        connect rename_table_special_mem_r1.clk, cd.clk @[reg_alloc.rs 121:17]
-        ; connect different types:
-        ; lhs: UInt<1>
-        ; rhs: UInt<8>
-        connect rename_table_special_mem_r1.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17]
-        connect rename_table_special_mem_r1.en, UInt<1>(0h0) @[reg_alloc.rs 123:17]
-        when and(geq(rename_0_src_1.addr.value, UInt<32>(0hFE)), lt(rename_0_src_1.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 126:17]
+        connect rename_table_special_0_src_1.addr, _bundle_literal_expr_4 @[reg_alloc.rs 111:17]
+        connect rename_table_special_0_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17]
+        when and(geq(rename_table_special_0_src_1.addr.value, UInt<32>(0hFE)), lt(rename_table_special_0_src_1.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 114:17]
             ; connect different types:
             ; lhs: UInt<1>
             ; rhs: UInt<33>
-            connect rename_table_special_mem_r1.addr, sub(rename_0_src_1.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 127:21]
-            connect rename_table_special_mem_r1.en, UInt<1>(0h1) @[reg_alloc.rs 128:21]
-            connect rename_0_src_1.data, rename_table_special_mem_r1.data @[reg_alloc.rs 129:21]
-        wire rename_0_src_2: Ty54 @[reg_alloc.rs 113:17]
-        wire _bundle_literal_expr_8: Ty1
-        connect _bundle_literal_expr_8.value, tail(UInt<32>(0h0), 24)
-        connect rename_0_src_2.addr, _bundle_literal_expr_8 @[reg_alloc.rs 116:13]
-        wire _bundle_literal_expr_9: Ty25
-        wire _bundle_literal_expr_10: Ty23
-        connect _bundle_literal_expr_10.adj_value, tail(UInt<64>(0h0), 62)
-        connect _bundle_literal_expr_9.unit_num, _bundle_literal_expr_10
-        wire _bundle_literal_expr_11: Ty24
-        connect _bundle_literal_expr_11.value, tail(UInt<8>(0h0), 4)
-        connect _bundle_literal_expr_9.unit_out_reg, _bundle_literal_expr_11
-        connect rename_0_src_2.data, _bundle_literal_expr_9 @[reg_alloc.rs 117:13]
-        connect rename_table_normal_mem_r2.clk, cd.clk @[reg_alloc.rs 121:17]
-        connect rename_table_normal_mem_r2.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17]
-        connect rename_table_normal_mem_r2.en, UInt<1>(0h0) @[reg_alloc.rs 123:17]
-        when and(geq(rename_0_src_2.addr.value, UInt<32>(0h1)), lt(rename_0_src_2.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 126:17]
-            ; connect different types:
-            ; lhs: UInt<8>
-            ; rhs: UInt<33>
-            connect rename_table_normal_mem_r2.addr, sub(rename_0_src_2.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 127:21]
-            connect rename_table_normal_mem_r2.en, UInt<1>(0h1) @[reg_alloc.rs 128:21]
-            connect rename_0_src_2.data, rename_table_normal_mem_r2.data @[reg_alloc.rs 129:21]
-        connect rename_table_special_mem_r2.clk, cd.clk @[reg_alloc.rs 121:17]
+            connect rename_table_special_mem_r1.addr, sub(rename_table_special_0_src_1.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 115:21]
+            connect rename_table_special_mem_r1.en, UInt<1>(0h1) @[reg_alloc.rs 116:21]
+            connect rename_table_special_0_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_special_mem_r1.data) @[reg_alloc.rs 117:21]
+        connect rename_table_special_mem_r2.clk, cd.clk @[reg_alloc.rs 103:17]
         ; connect different types:
         ; lhs: UInt<1>
         ; rhs: UInt<8>
-        connect rename_table_special_mem_r2.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17]
-        connect rename_table_special_mem_r2.en, UInt<1>(0h0) @[reg_alloc.rs 123:17]
-        when and(geq(rename_0_src_2.addr.value, UInt<32>(0hFE)), lt(rename_0_src_2.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 126:17]
+        connect rename_table_special_mem_r2.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17]
+        connect rename_table_special_mem_r2.en, UInt<1>(0h0) @[reg_alloc.rs 105:17]
+        wire rename_table_special_0_src_2: Ty45 @[reg_alloc.rs 108:21]
+        wire _bundle_literal_expr_5: Ty1
+        connect _bundle_literal_expr_5.value, tail(UInt<32>(0h0), 24)
+        connect rename_table_special_0_src_2.addr, _bundle_literal_expr_5 @[reg_alloc.rs 111:17]
+        connect rename_table_special_0_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17]
+        when and(geq(rename_table_special_0_src_2.addr.value, UInt<32>(0hFE)), lt(rename_table_special_0_src_2.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 114:17]
             ; connect different types:
             ; lhs: UInt<1>
             ; rhs: UInt<33>
-            connect rename_table_special_mem_r2.addr, sub(rename_0_src_2.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 127:21]
-            connect rename_table_special_mem_r2.en, UInt<1>(0h1) @[reg_alloc.rs 128:21]
-            connect rename_0_src_2.data, rename_table_special_mem_r2.data @[reg_alloc.rs 129:21]
-        wire rename_table_normal_0_dest0: Ty30 @[reg_alloc.rs 171:21]
-        connect rename_table_normal_mem_w3, rename_table_normal_0_dest0 @[reg_alloc.rs 174:17]
-        wire _bundle_literal_expr_12: Ty55
-        connect _bundle_literal_expr_12.addr, UInt<0>(0h0)
-        connect _bundle_literal_expr_12.en, UInt<1>(0h0)
-        connect _bundle_literal_expr_12.clk, cd.clk
-        wire _uninit_expr: Ty25
-        invalidate _uninit_expr
-        connect _bundle_literal_expr_12.data, _uninit_expr
-        wire _bundle_literal_expr_13: Ty29
-        wire _bundle_literal_expr_14: Ty27
-        connect _bundle_literal_expr_14.adj_value, UInt<1>(0h1)
-        connect _bundle_literal_expr_13.unit_num, _bundle_literal_expr_14
-        wire _bundle_literal_expr_15: Ty28
-        connect _bundle_literal_expr_15.value, UInt<1>(0h1)
-        connect _bundle_literal_expr_13.unit_out_reg, _bundle_literal_expr_15
-        connect _bundle_literal_expr_12.mask, _bundle_literal_expr_13
-        ; connect different types:
-        ; lhs: Bundle {addr: UInt<8>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        connect rename_table_normal_0_dest0, _bundle_literal_expr_12 @[reg_alloc.rs 176:17]
-        wire rename_table_special_0_dest0: Ty36 @[reg_alloc.rs 171:21]
-        connect rename_table_special_mem_w3, rename_table_special_0_dest0 @[reg_alloc.rs 174:17]
-        wire _bundle_literal_expr_16: Ty55
-        connect _bundle_literal_expr_16.addr, UInt<0>(0h0)
-        connect _bundle_literal_expr_16.en, UInt<1>(0h0)
-        connect _bundle_literal_expr_16.clk, cd.clk
-        wire _uninit_expr_1: Ty25
-        invalidate _uninit_expr_1
-        connect _bundle_literal_expr_16.data, _uninit_expr_1
-        wire _bundle_literal_expr_17: Ty29
-        wire _bundle_literal_expr_18: Ty27
-        connect _bundle_literal_expr_18.adj_value, UInt<1>(0h1)
-        connect _bundle_literal_expr_17.unit_num, _bundle_literal_expr_18
-        wire _bundle_literal_expr_19: Ty28
-        connect _bundle_literal_expr_19.value, UInt<1>(0h1)
-        connect _bundle_literal_expr_17.unit_out_reg, _bundle_literal_expr_19
-        connect _bundle_literal_expr_16.mask, _bundle_literal_expr_17
-        ; connect different types:
-        ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        connect rename_table_special_0_dest0, _bundle_literal_expr_16 @[reg_alloc.rs 176:17]
-        wire rename_table_normal_0_dest1: Ty30 @[reg_alloc.rs 171:21]
-        connect rename_table_normal_mem_w4, rename_table_normal_0_dest1 @[reg_alloc.rs 174:17]
-        wire _bundle_literal_expr_20: Ty55
-        connect _bundle_literal_expr_20.addr, UInt<0>(0h0)
-        connect _bundle_literal_expr_20.en, UInt<1>(0h0)
-        connect _bundle_literal_expr_20.clk, cd.clk
-        wire _uninit_expr_2: Ty25
-        invalidate _uninit_expr_2
-        connect _bundle_literal_expr_20.data, _uninit_expr_2
-        wire _bundle_literal_expr_21: Ty29
-        wire _bundle_literal_expr_22: Ty27
-        connect _bundle_literal_expr_22.adj_value, UInt<1>(0h1)
-        connect _bundle_literal_expr_21.unit_num, _bundle_literal_expr_22
-        wire _bundle_literal_expr_23: Ty28
-        connect _bundle_literal_expr_23.value, UInt<1>(0h1)
-        connect _bundle_literal_expr_21.unit_out_reg, _bundle_literal_expr_23
-        connect _bundle_literal_expr_20.mask, _bundle_literal_expr_21
-        ; connect different types:
-        ; lhs: Bundle {addr: UInt<8>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        connect rename_table_normal_0_dest1, _bundle_literal_expr_20 @[reg_alloc.rs 176:17]
-        wire rename_table_special_0_dest1: Ty36 @[reg_alloc.rs 171:21]
-        connect rename_table_special_mem_w4, rename_table_special_0_dest1 @[reg_alloc.rs 174:17]
-        wire _bundle_literal_expr_24: Ty55
-        connect _bundle_literal_expr_24.addr, UInt<0>(0h0)
-        connect _bundle_literal_expr_24.en, UInt<1>(0h0)
-        connect _bundle_literal_expr_24.clk, cd.clk
-        wire _uninit_expr_3: Ty25
-        invalidate _uninit_expr_3
-        connect _bundle_literal_expr_24.data, _uninit_expr_3
-        wire _bundle_literal_expr_25: Ty29
-        wire _bundle_literal_expr_26: Ty27
-        connect _bundle_literal_expr_26.adj_value, UInt<1>(0h1)
-        connect _bundle_literal_expr_25.unit_num, _bundle_literal_expr_26
-        wire _bundle_literal_expr_27: Ty28
-        connect _bundle_literal_expr_27.value, UInt<1>(0h1)
-        connect _bundle_literal_expr_25.unit_out_reg, _bundle_literal_expr_27
-        connect _bundle_literal_expr_24.mask, _bundle_literal_expr_25
-        ; connect different types:
-        ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        connect rename_table_special_0_dest1, _bundle_literal_expr_24 @[reg_alloc.rs 176:17]
-        wire rename_table_special_0_flag0_rFE: Ty36 @[reg_alloc.rs 171:21]
-        connect rename_table_special_mem_w5, rename_table_special_0_flag0_rFE @[reg_alloc.rs 174:17]
-        wire _bundle_literal_expr_28: Ty55
-        connect _bundle_literal_expr_28.addr, UInt<0>(0h0)
-        connect _bundle_literal_expr_28.en, UInt<1>(0h0)
-        connect _bundle_literal_expr_28.clk, cd.clk
-        wire _uninit_expr_4: Ty25
-        invalidate _uninit_expr_4
-        connect _bundle_literal_expr_28.data, _uninit_expr_4
-        wire _bundle_literal_expr_29: Ty29
-        wire _bundle_literal_expr_30: Ty27
-        connect _bundle_literal_expr_30.adj_value, UInt<1>(0h1)
-        connect _bundle_literal_expr_29.unit_num, _bundle_literal_expr_30
-        wire _bundle_literal_expr_31: Ty28
-        connect _bundle_literal_expr_31.value, UInt<1>(0h1)
-        connect _bundle_literal_expr_29.unit_out_reg, _bundle_literal_expr_31
-        connect _bundle_literal_expr_28.mask, _bundle_literal_expr_29
-        ; connect different types:
-        ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        connect rename_table_special_0_flag0_rFE, _bundle_literal_expr_28 @[reg_alloc.rs 176:17]
-        wire rename_table_special_0_flag1_rFF: Ty36 @[reg_alloc.rs 171:21]
-        connect rename_table_special_mem_w6, rename_table_special_0_flag1_rFF @[reg_alloc.rs 174:17]
-        wire _bundle_literal_expr_32: Ty55
-        connect _bundle_literal_expr_32.addr, UInt<0>(0h0)
-        connect _bundle_literal_expr_32.en, UInt<1>(0h0)
-        connect _bundle_literal_expr_32.clk, cd.clk
-        wire _uninit_expr_5: Ty25
-        invalidate _uninit_expr_5
-        connect _bundle_literal_expr_32.data, _uninit_expr_5
-        wire _bundle_literal_expr_33: Ty29
-        wire _bundle_literal_expr_34: Ty27
-        connect _bundle_literal_expr_34.adj_value, UInt<1>(0h1)
-        connect _bundle_literal_expr_33.unit_num, _bundle_literal_expr_34
-        wire _bundle_literal_expr_35: Ty28
-        connect _bundle_literal_expr_35.value, UInt<1>(0h1)
-        connect _bundle_literal_expr_33.unit_out_reg, _bundle_literal_expr_35
-        connect _bundle_literal_expr_32.mask, _bundle_literal_expr_33
-        ; connect different types:
-        ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        connect rename_table_special_0_flag1_rFF, _bundle_literal_expr_32 @[reg_alloc.rs 176:17]
-        match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 190:9]
+            connect rename_table_special_mem_r2.addr, sub(rename_table_special_0_src_2.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 115:21]
+            connect rename_table_special_mem_r2.en, UInt<1>(0h1) @[reg_alloc.rs 116:21]
+            connect rename_table_special_0_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_special_mem_r2.data) @[reg_alloc.rs 117:21]
+        match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 159:9]
             HdlNone:
                 skip
             HdlSome(_match_arm_value):
-                wire unit_kind: Ty56 @[unit.rs 127:1]
+                wire unit_kind: Ty46 @[unit.rs 127:1]
                 match _match_arm_value.mop: @[unit.rs 127:1]
                     AluBranch(_match_arm_value_1):
                         connect unit_kind, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 127:1]
@@ -776,8 +478,8 @@ circuit reg_alloc:
                     LoadStore:
                         connect available_units_for_kind[0], UInt<1>(0h0) @[unit.rs 127:1]
                         connect available_units_for_kind[1], UInt<1>(0h0) @[unit.rs 127:1]
-                connect available_units[0], available_units_for_kind @[reg_alloc.rs 191:13]
-                match renamed_mops_out_reg[0]: @[reg_alloc.rs 196:13]
+                connect available_units[0], available_units_for_kind @[reg_alloc.rs 160:13]
+                match renamed_mops_out_reg[0]: @[reg_alloc.rs 165:13]
                     HdlNone:
                         skip
                     HdlSome(_match_arm_value_4):
@@ -809,180 +511,280 @@ circuit reg_alloc:
                                     Store(_match_arm_value_14):
                                         connect dest_reg_3, _match_arm_value_14.dest @[instruction.rs 539:1]
                                 connect dest_reg, dest_reg_3 @[unit.rs 127:1]
-                        wire mapped_regs: Ty51 @[unit.rs 127:1]
+                        wire mapped_regs: Ty42 @[unit.rs 127:1]
                         match _match_arm_value.mop: @[unit.rs 127:1]
                             AluBranch(_match_arm_value_15):
-                                wire mapped_regs_1: Ty46 @[instruction.rs 477:1]
+                                wire mapped_regs_1: Ty37 @[instruction.rs 477:1]
                                 match _match_arm_value_15: @[instruction.rs 477:1]
                                     AddSub(_match_arm_value_16):
-                                        wire _bundle_literal_expr_36: Ty1
-                                        connect _bundle_literal_expr_36.value, _match_arm_value_16.alu_common.common.src[0]
-                                        connect rename_0_src_0.addr, _bundle_literal_expr_36 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_37: Ty1
-                                        connect _bundle_literal_expr_37.value, _match_arm_value_16.alu_common.common.src[1]
-                                        connect rename_0_src_1.addr, _bundle_literal_expr_37 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_38: Ty1
-                                        connect _bundle_literal_expr_38.value, _match_arm_value_16.alu_common.common.src[2]
-                                        connect rename_0_src_2.addr, _bundle_literal_expr_38 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_39: Ty44
-                                        wire _bundle_literal_expr_40: Ty43
-                                        wire _bundle_literal_expr_41: Ty42
-                                        connect _bundle_literal_expr_41.prefix_pad, _match_arm_value_16.alu_common.common.prefix_pad
-                                        connect _bundle_literal_expr_41.dest, _match_arm_value_4.unit_out_reg
+                                        wire renamed_src_reg_0_0: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_6: Ty1
+                                        connect _bundle_literal_expr_6.value, _match_arm_value_16.alu_common.common.src[0]
+                                        connect rename_table_normal_0_src_0.addr, _bundle_literal_expr_6 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_7: Ty1
+                                        connect _bundle_literal_expr_7.value, _match_arm_value_16.alu_common.common.src[0]
+                                        connect rename_table_special_0_src_0.addr, _bundle_literal_expr_7 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_0_src_0.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_0_src_0.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_8: Ty25
+                                                        wire _bundle_literal_expr_9: Ty23
+                                                        connect _bundle_literal_expr_9.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_8.unit_num, _bundle_literal_expr_9
+                                                        wire _bundle_literal_expr_10: Ty24
+                                                        connect _bundle_literal_expr_10.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_8.unit_out_reg, _bundle_literal_expr_10
+                                                        connect renamed_src_reg_0_0, _bundle_literal_expr_8 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_17):
+                                                        connect renamed_src_reg_0_0, _match_arm_value_17 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_18):
+                                                connect renamed_src_reg_0_0, _match_arm_value_18 @[reg_alloc.rs 185:33]
+                                        wire renamed_src_reg_0_1: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_11: Ty1
+                                        connect _bundle_literal_expr_11.value, _match_arm_value_16.alu_common.common.src[1]
+                                        connect rename_table_normal_0_src_1.addr, _bundle_literal_expr_11 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_12: Ty1
+                                        connect _bundle_literal_expr_12.value, _match_arm_value_16.alu_common.common.src[1]
+                                        connect rename_table_special_0_src_1.addr, _bundle_literal_expr_12 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_0_src_1.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_0_src_1.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_13: Ty25
+                                                        wire _bundle_literal_expr_14: Ty23
+                                                        connect _bundle_literal_expr_14.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_13.unit_num, _bundle_literal_expr_14
+                                                        wire _bundle_literal_expr_15: Ty24
+                                                        connect _bundle_literal_expr_15.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_13.unit_out_reg, _bundle_literal_expr_15
+                                                        connect renamed_src_reg_0_1, _bundle_literal_expr_13 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_19):
+                                                        connect renamed_src_reg_0_1, _match_arm_value_19 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_20):
+                                                connect renamed_src_reg_0_1, _match_arm_value_20 @[reg_alloc.rs 185:33]
+                                        wire renamed_src_reg_0_2: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_16: Ty1
+                                        connect _bundle_literal_expr_16.value, _match_arm_value_16.alu_common.common.src[2]
+                                        connect rename_table_normal_0_src_2.addr, _bundle_literal_expr_16 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_17: Ty1
+                                        connect _bundle_literal_expr_17.value, _match_arm_value_16.alu_common.common.src[2]
+                                        connect rename_table_special_0_src_2.addr, _bundle_literal_expr_17 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_0_src_2.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_0_src_2.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_18: Ty25
+                                                        wire _bundle_literal_expr_19: Ty23
+                                                        connect _bundle_literal_expr_19.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_18.unit_num, _bundle_literal_expr_19
+                                                        wire _bundle_literal_expr_20: Ty24
+                                                        connect _bundle_literal_expr_20.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_18.unit_out_reg, _bundle_literal_expr_20
+                                                        connect renamed_src_reg_0_2, _bundle_literal_expr_18 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_21):
+                                                        connect renamed_src_reg_0_2, _match_arm_value_21 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_22):
+                                                connect renamed_src_reg_0_2, _match_arm_value_22 @[reg_alloc.rs 185:33]
+                                        wire _bundle_literal_expr_21: Ty35
+                                        wire _bundle_literal_expr_22: Ty34
+                                        wire _bundle_literal_expr_23: Ty33
+                                        connect _bundle_literal_expr_23.prefix_pad, _match_arm_value_16.alu_common.common.prefix_pad
+                                        connect _bundle_literal_expr_23.dest, _match_arm_value_4.unit_out_reg
                                         wire _array_literal_expr_1: UInt<6>[3]
                                         wire _array_literal_expr_2: UInt<6>[3]
-                                        wire _cast_bundle_to_bits_expr: Ty57
-                                        connect _cast_bundle_to_bits_expr.unit_num, rename_0_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr.unit_out_reg, rename_0_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr: Ty47
+                                        connect _cast_bundle_to_bits_expr.unit_num, renamed_src_reg_0_0.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr.unit_out_reg, renamed_src_reg_0_0.unit_out_reg.value
                                         wire _cast_to_bits_expr: UInt<6>
                                         connect _cast_to_bits_expr, cat(_cast_bundle_to_bits_expr.unit_out_reg, _cast_bundle_to_bits_expr.unit_num)
                                         connect _array_literal_expr_2[0], _cast_to_bits_expr
-                                        wire _cast_bundle_to_bits_expr_1: Ty57
-                                        connect _cast_bundle_to_bits_expr_1.unit_num, rename_0_src_1.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_1.unit_out_reg, rename_0_src_1.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_1: Ty47
+                                        connect _cast_bundle_to_bits_expr_1.unit_num, renamed_src_reg_0_1.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_1.unit_out_reg, renamed_src_reg_0_1.unit_out_reg.value
                                         wire _cast_to_bits_expr_1: UInt<6>
                                         connect _cast_to_bits_expr_1, cat(_cast_bundle_to_bits_expr_1.unit_out_reg, _cast_bundle_to_bits_expr_1.unit_num)
                                         connect _array_literal_expr_2[1], _cast_to_bits_expr_1
-                                        wire _cast_bundle_to_bits_expr_2: Ty57
-                                        connect _cast_bundle_to_bits_expr_2.unit_num, rename_0_src_2.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_2.unit_out_reg, rename_0_src_2.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_2: Ty47
+                                        connect _cast_bundle_to_bits_expr_2.unit_num, renamed_src_reg_0_2.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_2.unit_out_reg, renamed_src_reg_0_2.unit_out_reg.value
                                         wire _cast_to_bits_expr_2: UInt<6>
                                         connect _cast_to_bits_expr_2, cat(_cast_bundle_to_bits_expr_2.unit_out_reg, _cast_bundle_to_bits_expr_2.unit_num)
                                         connect _array_literal_expr_2[2], _cast_to_bits_expr_2
                                         connect _array_literal_expr_1[0], _array_literal_expr_2[0]
                                         wire _array_literal_expr_3: UInt<6>[3]
-                                        wire _cast_bundle_to_bits_expr_3: Ty57
-                                        connect _cast_bundle_to_bits_expr_3.unit_num, rename_0_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_3.unit_out_reg, rename_0_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_3: Ty47
+                                        connect _cast_bundle_to_bits_expr_3.unit_num, renamed_src_reg_0_0.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_3.unit_out_reg, renamed_src_reg_0_0.unit_out_reg.value
                                         wire _cast_to_bits_expr_3: UInt<6>
                                         connect _cast_to_bits_expr_3, cat(_cast_bundle_to_bits_expr_3.unit_out_reg, _cast_bundle_to_bits_expr_3.unit_num)
                                         connect _array_literal_expr_3[0], _cast_to_bits_expr_3
-                                        wire _cast_bundle_to_bits_expr_4: Ty57
-                                        connect _cast_bundle_to_bits_expr_4.unit_num, rename_0_src_1.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_4.unit_out_reg, rename_0_src_1.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_4: Ty47
+                                        connect _cast_bundle_to_bits_expr_4.unit_num, renamed_src_reg_0_1.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_4.unit_out_reg, renamed_src_reg_0_1.unit_out_reg.value
                                         wire _cast_to_bits_expr_4: UInt<6>
                                         connect _cast_to_bits_expr_4, cat(_cast_bundle_to_bits_expr_4.unit_out_reg, _cast_bundle_to_bits_expr_4.unit_num)
                                         connect _array_literal_expr_3[1], _cast_to_bits_expr_4
-                                        wire _cast_bundle_to_bits_expr_5: Ty57
-                                        connect _cast_bundle_to_bits_expr_5.unit_num, rename_0_src_2.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_5.unit_out_reg, rename_0_src_2.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_5: Ty47
+                                        connect _cast_bundle_to_bits_expr_5.unit_num, renamed_src_reg_0_2.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_5.unit_out_reg, renamed_src_reg_0_2.unit_out_reg.value
                                         wire _cast_to_bits_expr_5: UInt<6>
                                         connect _cast_to_bits_expr_5, cat(_cast_bundle_to_bits_expr_5.unit_out_reg, _cast_bundle_to_bits_expr_5.unit_num)
                                         connect _array_literal_expr_3[2], _cast_to_bits_expr_5
                                         connect _array_literal_expr_1[1], _array_literal_expr_3[1]
                                         wire _array_literal_expr_4: UInt<6>[3]
-                                        wire _cast_bundle_to_bits_expr_6: Ty57
-                                        connect _cast_bundle_to_bits_expr_6.unit_num, rename_0_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_6.unit_out_reg, rename_0_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_6: Ty47
+                                        connect _cast_bundle_to_bits_expr_6.unit_num, renamed_src_reg_0_0.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_6.unit_out_reg, renamed_src_reg_0_0.unit_out_reg.value
                                         wire _cast_to_bits_expr_6: UInt<6>
                                         connect _cast_to_bits_expr_6, cat(_cast_bundle_to_bits_expr_6.unit_out_reg, _cast_bundle_to_bits_expr_6.unit_num)
                                         connect _array_literal_expr_4[0], _cast_to_bits_expr_6
-                                        wire _cast_bundle_to_bits_expr_7: Ty57
-                                        connect _cast_bundle_to_bits_expr_7.unit_num, rename_0_src_1.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_7.unit_out_reg, rename_0_src_1.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_7: Ty47
+                                        connect _cast_bundle_to_bits_expr_7.unit_num, renamed_src_reg_0_1.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_7.unit_out_reg, renamed_src_reg_0_1.unit_out_reg.value
                                         wire _cast_to_bits_expr_7: UInt<6>
                                         connect _cast_to_bits_expr_7, cat(_cast_bundle_to_bits_expr_7.unit_out_reg, _cast_bundle_to_bits_expr_7.unit_num)
                                         connect _array_literal_expr_4[1], _cast_to_bits_expr_7
-                                        wire _cast_bundle_to_bits_expr_8: Ty57
-                                        connect _cast_bundle_to_bits_expr_8.unit_num, rename_0_src_2.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_8.unit_out_reg, rename_0_src_2.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_8: Ty47
+                                        connect _cast_bundle_to_bits_expr_8.unit_num, renamed_src_reg_0_2.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_8.unit_out_reg, renamed_src_reg_0_2.unit_out_reg.value
                                         wire _cast_to_bits_expr_8: UInt<6>
                                         connect _cast_to_bits_expr_8, cat(_cast_bundle_to_bits_expr_8.unit_out_reg, _cast_bundle_to_bits_expr_8.unit_num)
                                         connect _array_literal_expr_4[2], _cast_to_bits_expr_8
                                         connect _array_literal_expr_1[2], _array_literal_expr_4[2]
-                                        connect _bundle_literal_expr_41.src, _array_literal_expr_1
-                                        wire _bundle_literal_expr_42: Ty58
-                                        connect _bundle_literal_expr_42.imm_low, _match_arm_value_16.alu_common.common.imm_low
+                                        connect _bundle_literal_expr_23.src, _array_literal_expr_1
+                                        wire _bundle_literal_expr_24: Ty48
+                                        connect _bundle_literal_expr_24.imm_low, _match_arm_value_16.alu_common.common.imm_low
                                         wire _array_literal_expr_5: UInt<8>[0]
                                         invalidate _array_literal_expr_5
-                                        connect _bundle_literal_expr_42.reversed_src, _array_literal_expr_5
-                                        connect _bundle_literal_expr_42.imm_sign, _match_arm_value_16.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_9: Ty59
-                                        connect _cast_bundle_to_bits_expr_9.imm_low, _bundle_literal_expr_42.imm_low
+                                        connect _bundle_literal_expr_24.reversed_src, _array_literal_expr_5
+                                        connect _bundle_literal_expr_24.imm_sign, _match_arm_value_16.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_9: Ty49
+                                        connect _cast_bundle_to_bits_expr_9.imm_low, _bundle_literal_expr_24.imm_low
                                         connect _cast_bundle_to_bits_expr_9.reversed_src, UInt<0>(0)
-                                        connect _cast_bundle_to_bits_expr_9.imm_sign, asUInt(_bundle_literal_expr_42.imm_sign)
+                                        connect _cast_bundle_to_bits_expr_9.imm_sign, asUInt(_bundle_literal_expr_24.imm_sign)
                                         wire _cast_to_bits_expr_9: UInt<26>
                                         connect _cast_to_bits_expr_9, cat(_cast_bundle_to_bits_expr_9.imm_sign, cat(_cast_bundle_to_bits_expr_9.reversed_src, _cast_bundle_to_bits_expr_9.imm_low))
-                                        connect _bundle_literal_expr_41.imm_low, bits(asSInt(_cast_to_bits_expr_9), 24, 0)
-                                        wire _bundle_literal_expr_43: Ty58
-                                        connect _bundle_literal_expr_43.imm_low, _match_arm_value_16.alu_common.common.imm_low
+                                        connect _bundle_literal_expr_23.imm_low, bits(asSInt(_cast_to_bits_expr_9), 24, 0)
+                                        wire _bundle_literal_expr_25: Ty48
+                                        connect _bundle_literal_expr_25.imm_low, _match_arm_value_16.alu_common.common.imm_low
                                         wire _array_literal_expr_6: UInt<8>[0]
                                         invalidate _array_literal_expr_6
-                                        connect _bundle_literal_expr_43.reversed_src, _array_literal_expr_6
-                                        connect _bundle_literal_expr_43.imm_sign, _match_arm_value_16.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_10: Ty59
-                                        connect _cast_bundle_to_bits_expr_10.imm_low, _bundle_literal_expr_43.imm_low
+                                        connect _bundle_literal_expr_25.reversed_src, _array_literal_expr_6
+                                        connect _bundle_literal_expr_25.imm_sign, _match_arm_value_16.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_10: Ty49
+                                        connect _cast_bundle_to_bits_expr_10.imm_low, _bundle_literal_expr_25.imm_low
                                         connect _cast_bundle_to_bits_expr_10.reversed_src, UInt<0>(0)
-                                        connect _cast_bundle_to_bits_expr_10.imm_sign, asUInt(_bundle_literal_expr_43.imm_sign)
+                                        connect _cast_bundle_to_bits_expr_10.imm_sign, asUInt(_bundle_literal_expr_25.imm_sign)
                                         wire _cast_to_bits_expr_10: UInt<26>
                                         connect _cast_to_bits_expr_10, cat(_cast_bundle_to_bits_expr_10.imm_sign, cat(_cast_bundle_to_bits_expr_10.reversed_src, _cast_bundle_to_bits_expr_10.imm_low))
-                                        connect _bundle_literal_expr_41.imm_sign, shr(asSInt(_cast_to_bits_expr_10), 25)
-                                        wire _bundle_literal_expr_44: Ty2
-                                        invalidate _bundle_literal_expr_44
-                                        connect _bundle_literal_expr_41._phantom, _bundle_literal_expr_44
-                                        connect _bundle_literal_expr_40.common, _bundle_literal_expr_41
-                                        connect _bundle_literal_expr_40.output_integer_mode, _match_arm_value_16.alu_common.output_integer_mode
-                                        connect _bundle_literal_expr_39.alu_common, _bundle_literal_expr_40
-                                        connect _bundle_literal_expr_39.invert_src0, _match_arm_value_16.invert_src0
-                                        connect _bundle_literal_expr_39.invert_carry_in, _match_arm_value_16.invert_carry_in
-                                        connect _bundle_literal_expr_39.invert_carry_out, _match_arm_value_16.invert_carry_out
-                                        connect _bundle_literal_expr_39.add_pc, _match_arm_value_16.add_pc
-                                        connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSub, _bundle_literal_expr_39) @[instruction.rs 477:1]
-                                    AddSubI(_match_arm_value_17):
-                                        wire _bundle_literal_expr_45: Ty1
-                                        connect _bundle_literal_expr_45.value, _match_arm_value_17.alu_common.common.src[0]
-                                        connect rename_0_src_0.addr, _bundle_literal_expr_45 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_46: Ty1
-                                        connect _bundle_literal_expr_46.value, _match_arm_value_17.alu_common.common.src[1]
-                                        connect rename_0_src_1.addr, _bundle_literal_expr_46 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_47: Ty44
-                                        wire _bundle_literal_expr_48: Ty43
-                                        wire _bundle_literal_expr_49: Ty42
-                                        connect _bundle_literal_expr_49.prefix_pad, _match_arm_value_17.alu_common.common.prefix_pad
-                                        connect _bundle_literal_expr_49.dest, _match_arm_value_4.unit_out_reg
+                                        connect _bundle_literal_expr_23.imm_sign, shr(asSInt(_cast_to_bits_expr_10), 25)
+                                        wire _bundle_literal_expr_26: Ty2
+                                        invalidate _bundle_literal_expr_26
+                                        connect _bundle_literal_expr_23._phantom, _bundle_literal_expr_26
+                                        connect _bundle_literal_expr_22.common, _bundle_literal_expr_23
+                                        connect _bundle_literal_expr_22.output_integer_mode, _match_arm_value_16.alu_common.output_integer_mode
+                                        connect _bundle_literal_expr_21.alu_common, _bundle_literal_expr_22
+                                        connect _bundle_literal_expr_21.invert_src0, _match_arm_value_16.invert_src0
+                                        connect _bundle_literal_expr_21.invert_carry_in, _match_arm_value_16.invert_carry_in
+                                        connect _bundle_literal_expr_21.invert_carry_out, _match_arm_value_16.invert_carry_out
+                                        connect _bundle_literal_expr_21.add_pc, _match_arm_value_16.add_pc
+                                        connect mapped_regs_1, {|AddSub: Ty35, AddSubI: Ty35, Logical: Ty36|}(AddSub, _bundle_literal_expr_21) @[instruction.rs 477:1]
+                                    AddSubI(_match_arm_value_23):
+                                        wire renamed_src_reg_0_0_1: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_27: Ty1
+                                        connect _bundle_literal_expr_27.value, _match_arm_value_23.alu_common.common.src[0]
+                                        connect rename_table_normal_0_src_0.addr, _bundle_literal_expr_27 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_28: Ty1
+                                        connect _bundle_literal_expr_28.value, _match_arm_value_23.alu_common.common.src[0]
+                                        connect rename_table_special_0_src_0.addr, _bundle_literal_expr_28 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_0_src_0.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_0_src_0.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_29: Ty25
+                                                        wire _bundle_literal_expr_30: Ty23
+                                                        connect _bundle_literal_expr_30.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_29.unit_num, _bundle_literal_expr_30
+                                                        wire _bundle_literal_expr_31: Ty24
+                                                        connect _bundle_literal_expr_31.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_29.unit_out_reg, _bundle_literal_expr_31
+                                                        connect renamed_src_reg_0_0_1, _bundle_literal_expr_29 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_24):
+                                                        connect renamed_src_reg_0_0_1, _match_arm_value_24 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_25):
+                                                connect renamed_src_reg_0_0_1, _match_arm_value_25 @[reg_alloc.rs 185:33]
+                                        wire renamed_src_reg_0_1_1: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_32: Ty1
+                                        connect _bundle_literal_expr_32.value, _match_arm_value_23.alu_common.common.src[1]
+                                        connect rename_table_normal_0_src_1.addr, _bundle_literal_expr_32 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_33: Ty1
+                                        connect _bundle_literal_expr_33.value, _match_arm_value_23.alu_common.common.src[1]
+                                        connect rename_table_special_0_src_1.addr, _bundle_literal_expr_33 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_0_src_1.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_0_src_1.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_34: Ty25
+                                                        wire _bundle_literal_expr_35: Ty23
+                                                        connect _bundle_literal_expr_35.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_34.unit_num, _bundle_literal_expr_35
+                                                        wire _bundle_literal_expr_36: Ty24
+                                                        connect _bundle_literal_expr_36.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_34.unit_out_reg, _bundle_literal_expr_36
+                                                        connect renamed_src_reg_0_1_1, _bundle_literal_expr_34 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_26):
+                                                        connect renamed_src_reg_0_1_1, _match_arm_value_26 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_27):
+                                                connect renamed_src_reg_0_1_1, _match_arm_value_27 @[reg_alloc.rs 185:33]
+                                        wire _bundle_literal_expr_37: Ty35
+                                        wire _bundle_literal_expr_38: Ty34
+                                        wire _bundle_literal_expr_39: Ty33
+                                        connect _bundle_literal_expr_39.prefix_pad, _match_arm_value_23.alu_common.common.prefix_pad
+                                        connect _bundle_literal_expr_39.dest, _match_arm_value_4.unit_out_reg
                                         wire _array_literal_expr_7: UInt<6>[3]
                                         wire _array_literal_expr_8: UInt<6>[2]
-                                        wire _cast_bundle_to_bits_expr_11: Ty57
-                                        connect _cast_bundle_to_bits_expr_11.unit_num, rename_0_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_11.unit_out_reg, rename_0_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_11: Ty47
+                                        connect _cast_bundle_to_bits_expr_11.unit_num, renamed_src_reg_0_0_1.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_11.unit_out_reg, renamed_src_reg_0_0_1.unit_out_reg.value
                                         wire _cast_to_bits_expr_11: UInt<6>
                                         connect _cast_to_bits_expr_11, cat(_cast_bundle_to_bits_expr_11.unit_out_reg, _cast_bundle_to_bits_expr_11.unit_num)
                                         connect _array_literal_expr_8[0], _cast_to_bits_expr_11
-                                        wire _cast_bundle_to_bits_expr_12: Ty57
-                                        connect _cast_bundle_to_bits_expr_12.unit_num, rename_0_src_1.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_12.unit_out_reg, rename_0_src_1.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_12: Ty47
+                                        connect _cast_bundle_to_bits_expr_12.unit_num, renamed_src_reg_0_1_1.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_12.unit_out_reg, renamed_src_reg_0_1_1.unit_out_reg.value
                                         wire _cast_to_bits_expr_12: UInt<6>
                                         connect _cast_to_bits_expr_12, cat(_cast_bundle_to_bits_expr_12.unit_out_reg, _cast_bundle_to_bits_expr_12.unit_num)
                                         connect _array_literal_expr_8[1], _cast_to_bits_expr_12
                                         connect _array_literal_expr_7[0], _array_literal_expr_8[0]
                                         wire _array_literal_expr_9: UInt<6>[2]
-                                        wire _cast_bundle_to_bits_expr_13: Ty57
-                                        connect _cast_bundle_to_bits_expr_13.unit_num, rename_0_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_13.unit_out_reg, rename_0_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_13: Ty47
+                                        connect _cast_bundle_to_bits_expr_13.unit_num, renamed_src_reg_0_0_1.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_13.unit_out_reg, renamed_src_reg_0_0_1.unit_out_reg.value
                                         wire _cast_to_bits_expr_13: UInt<6>
                                         connect _cast_to_bits_expr_13, cat(_cast_bundle_to_bits_expr_13.unit_out_reg, _cast_bundle_to_bits_expr_13.unit_num)
                                         connect _array_literal_expr_9[0], _cast_to_bits_expr_13
-                                        wire _cast_bundle_to_bits_expr_14: Ty57
-                                        connect _cast_bundle_to_bits_expr_14.unit_num, rename_0_src_1.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_14.unit_out_reg, rename_0_src_1.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_14: Ty47
+                                        connect _cast_bundle_to_bits_expr_14.unit_num, renamed_src_reg_0_1_1.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_14.unit_out_reg, renamed_src_reg_0_1_1.unit_out_reg.value
                                         wire _cast_to_bits_expr_14: UInt<6>
                                         connect _cast_to_bits_expr_14, cat(_cast_bundle_to_bits_expr_14.unit_out_reg, _cast_bundle_to_bits_expr_14.unit_num)
                                         connect _array_literal_expr_9[1], _cast_to_bits_expr_14
                                         connect _array_literal_expr_7[1], _array_literal_expr_9[1]
-                                        wire _bundle_literal_expr_50: Ty60
-                                        connect _bundle_literal_expr_50.imm_low, _match_arm_value_17.alu_common.common.imm_low
+                                        wire _bundle_literal_expr_40: Ty50
+                                        connect _bundle_literal_expr_40.imm_low, _match_arm_value_23.alu_common.common.imm_low
                                         wire _array_literal_expr_10: UInt<8>[1]
-                                        connect _array_literal_expr_10[0], _match_arm_value_17.alu_common.common.src[2]
-                                        connect _bundle_literal_expr_50.reversed_src, _array_literal_expr_10
-                                        connect _bundle_literal_expr_50.imm_sign, _match_arm_value_17.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_15: Ty61
-                                        connect _cast_bundle_to_bits_expr_15.imm_low, _bundle_literal_expr_50.imm_low
-                                        connect _cast_bundle_to_bits_expr_15.reversed_src, _bundle_literal_expr_50.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_15.imm_sign, asUInt(_bundle_literal_expr_50.imm_sign)
+                                        connect _array_literal_expr_10[0], _match_arm_value_23.alu_common.common.src[2]
+                                        connect _bundle_literal_expr_40.reversed_src, _array_literal_expr_10
+                                        connect _bundle_literal_expr_40.imm_sign, _match_arm_value_23.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_15: Ty51
+                                        connect _cast_bundle_to_bits_expr_15.imm_low, _bundle_literal_expr_40.imm_low
+                                        connect _cast_bundle_to_bits_expr_15.reversed_src, _bundle_literal_expr_40.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_15.imm_sign, asUInt(_bundle_literal_expr_40.imm_sign)
                                         wire _cast_to_bits_expr_15: UInt<34>
                                         connect _cast_to_bits_expr_15, cat(_cast_bundle_to_bits_expr_15.imm_sign, cat(_cast_bundle_to_bits_expr_15.reversed_src, _cast_bundle_to_bits_expr_15.imm_low))
-                                        wire _cast_bits_to_bundle_expr: Ty60
-                                        wire _cast_bits_to_bundle_expr_flattened: Ty61
+                                        wire _cast_bits_to_bundle_expr: Ty50
+                                        wire _cast_bits_to_bundle_expr_flattened: Ty51
                                         connect _cast_bits_to_bundle_expr_flattened.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_15)), 24, 0)
                                         connect _cast_bits_to_bundle_expr.imm_low, _cast_bits_to_bundle_expr_flattened.imm_low
                                         connect _cast_bits_to_bundle_expr_flattened.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_15)), 32, 25)
@@ -994,99 +796,139 @@ circuit reg_alloc:
                                         connect _cast_bits_to_bundle_expr_flattened.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_15)), 33, 33)
                                         connect _cast_bits_to_bundle_expr.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened.imm_sign)
                                         connect _array_literal_expr_7[2], tail(_cast_bits_to_bundle_expr.reversed_src[0], 2)
-                                        connect _bundle_literal_expr_49.src, _array_literal_expr_7
-                                        wire _bundle_literal_expr_51: Ty60
-                                        connect _bundle_literal_expr_51.imm_low, _match_arm_value_17.alu_common.common.imm_low
+                                        connect _bundle_literal_expr_39.src, _array_literal_expr_7
+                                        wire _bundle_literal_expr_41: Ty50
+                                        connect _bundle_literal_expr_41.imm_low, _match_arm_value_23.alu_common.common.imm_low
                                         wire _array_literal_expr_11: UInt<8>[1]
-                                        connect _array_literal_expr_11[0], _match_arm_value_17.alu_common.common.src[2]
-                                        connect _bundle_literal_expr_51.reversed_src, _array_literal_expr_11
-                                        connect _bundle_literal_expr_51.imm_sign, _match_arm_value_17.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_16: Ty61
-                                        connect _cast_bundle_to_bits_expr_16.imm_low, _bundle_literal_expr_51.imm_low
-                                        connect _cast_bundle_to_bits_expr_16.reversed_src, _bundle_literal_expr_51.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_16.imm_sign, asUInt(_bundle_literal_expr_51.imm_sign)
+                                        connect _array_literal_expr_11[0], _match_arm_value_23.alu_common.common.src[2]
+                                        connect _bundle_literal_expr_41.reversed_src, _array_literal_expr_11
+                                        connect _bundle_literal_expr_41.imm_sign, _match_arm_value_23.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_16: Ty51
+                                        connect _cast_bundle_to_bits_expr_16.imm_low, _bundle_literal_expr_41.imm_low
+                                        connect _cast_bundle_to_bits_expr_16.reversed_src, _bundle_literal_expr_41.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_16.imm_sign, asUInt(_bundle_literal_expr_41.imm_sign)
                                         wire _cast_to_bits_expr_16: UInt<34>
                                         connect _cast_to_bits_expr_16, cat(_cast_bundle_to_bits_expr_16.imm_sign, cat(_cast_bundle_to_bits_expr_16.reversed_src, _cast_bundle_to_bits_expr_16.imm_low))
-                                        connect _bundle_literal_expr_49.imm_low, bits(asSInt(_cast_to_bits_expr_16), 24, 0)
-                                        wire _bundle_literal_expr_52: Ty60
-                                        connect _bundle_literal_expr_52.imm_low, _match_arm_value_17.alu_common.common.imm_low
+                                        connect _bundle_literal_expr_39.imm_low, bits(asSInt(_cast_to_bits_expr_16), 24, 0)
+                                        wire _bundle_literal_expr_42: Ty50
+                                        connect _bundle_literal_expr_42.imm_low, _match_arm_value_23.alu_common.common.imm_low
                                         wire _array_literal_expr_12: UInt<8>[1]
-                                        connect _array_literal_expr_12[0], _match_arm_value_17.alu_common.common.src[2]
-                                        connect _bundle_literal_expr_52.reversed_src, _array_literal_expr_12
-                                        connect _bundle_literal_expr_52.imm_sign, _match_arm_value_17.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_17: Ty61
-                                        connect _cast_bundle_to_bits_expr_17.imm_low, _bundle_literal_expr_52.imm_low
-                                        connect _cast_bundle_to_bits_expr_17.reversed_src, _bundle_literal_expr_52.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_17.imm_sign, asUInt(_bundle_literal_expr_52.imm_sign)
+                                        connect _array_literal_expr_12[0], _match_arm_value_23.alu_common.common.src[2]
+                                        connect _bundle_literal_expr_42.reversed_src, _array_literal_expr_12
+                                        connect _bundle_literal_expr_42.imm_sign, _match_arm_value_23.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_17: Ty51
+                                        connect _cast_bundle_to_bits_expr_17.imm_low, _bundle_literal_expr_42.imm_low
+                                        connect _cast_bundle_to_bits_expr_17.reversed_src, _bundle_literal_expr_42.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_17.imm_sign, asUInt(_bundle_literal_expr_42.imm_sign)
                                         wire _cast_to_bits_expr_17: UInt<34>
                                         connect _cast_to_bits_expr_17, cat(_cast_bundle_to_bits_expr_17.imm_sign, cat(_cast_bundle_to_bits_expr_17.reversed_src, _cast_bundle_to_bits_expr_17.imm_low))
-                                        connect _bundle_literal_expr_49.imm_sign, shr(asSInt(_cast_to_bits_expr_17), 33)
-                                        wire _bundle_literal_expr_53: Ty2
-                                        invalidate _bundle_literal_expr_53
-                                        connect _bundle_literal_expr_49._phantom, _bundle_literal_expr_53
-                                        connect _bundle_literal_expr_48.common, _bundle_literal_expr_49
-                                        connect _bundle_literal_expr_48.output_integer_mode, _match_arm_value_17.alu_common.output_integer_mode
-                                        connect _bundle_literal_expr_47.alu_common, _bundle_literal_expr_48
-                                        connect _bundle_literal_expr_47.invert_src0, _match_arm_value_17.invert_src0
-                                        connect _bundle_literal_expr_47.invert_carry_in, _match_arm_value_17.invert_carry_in
-                                        connect _bundle_literal_expr_47.invert_carry_out, _match_arm_value_17.invert_carry_out
-                                        connect _bundle_literal_expr_47.add_pc, _match_arm_value_17.add_pc
-                                        connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSubI, _bundle_literal_expr_47) @[instruction.rs 477:1]
-                                    Logical(_match_arm_value_18):
-                                        wire _bundle_literal_expr_54: Ty1
-                                        connect _bundle_literal_expr_54.value, _match_arm_value_18.alu_common.common.src[0]
-                                        connect rename_0_src_0.addr, _bundle_literal_expr_54 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_55: Ty1
-                                        connect _bundle_literal_expr_55.value, _match_arm_value_18.alu_common.common.src[1]
-                                        connect rename_0_src_1.addr, _bundle_literal_expr_55 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_56: Ty45
-                                        wire _bundle_literal_expr_57: Ty43
-                                        wire _bundle_literal_expr_58: Ty42
-                                        connect _bundle_literal_expr_58.prefix_pad, _match_arm_value_18.alu_common.common.prefix_pad
-                                        connect _bundle_literal_expr_58.dest, _match_arm_value_4.unit_out_reg
+                                        connect _bundle_literal_expr_39.imm_sign, shr(asSInt(_cast_to_bits_expr_17), 33)
+                                        wire _bundle_literal_expr_43: Ty2
+                                        invalidate _bundle_literal_expr_43
+                                        connect _bundle_literal_expr_39._phantom, _bundle_literal_expr_43
+                                        connect _bundle_literal_expr_38.common, _bundle_literal_expr_39
+                                        connect _bundle_literal_expr_38.output_integer_mode, _match_arm_value_23.alu_common.output_integer_mode
+                                        connect _bundle_literal_expr_37.alu_common, _bundle_literal_expr_38
+                                        connect _bundle_literal_expr_37.invert_src0, _match_arm_value_23.invert_src0
+                                        connect _bundle_literal_expr_37.invert_carry_in, _match_arm_value_23.invert_carry_in
+                                        connect _bundle_literal_expr_37.invert_carry_out, _match_arm_value_23.invert_carry_out
+                                        connect _bundle_literal_expr_37.add_pc, _match_arm_value_23.add_pc
+                                        connect mapped_regs_1, {|AddSub: Ty35, AddSubI: Ty35, Logical: Ty36|}(AddSubI, _bundle_literal_expr_37) @[instruction.rs 477:1]
+                                    Logical(_match_arm_value_28):
+                                        wire renamed_src_reg_0_0_2: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_44: Ty1
+                                        connect _bundle_literal_expr_44.value, _match_arm_value_28.alu_common.common.src[0]
+                                        connect rename_table_normal_0_src_0.addr, _bundle_literal_expr_44 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_45: Ty1
+                                        connect _bundle_literal_expr_45.value, _match_arm_value_28.alu_common.common.src[0]
+                                        connect rename_table_special_0_src_0.addr, _bundle_literal_expr_45 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_0_src_0.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_0_src_0.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_46: Ty25
+                                                        wire _bundle_literal_expr_47: Ty23
+                                                        connect _bundle_literal_expr_47.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_46.unit_num, _bundle_literal_expr_47
+                                                        wire _bundle_literal_expr_48: Ty24
+                                                        connect _bundle_literal_expr_48.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_46.unit_out_reg, _bundle_literal_expr_48
+                                                        connect renamed_src_reg_0_0_2, _bundle_literal_expr_46 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_29):
+                                                        connect renamed_src_reg_0_0_2, _match_arm_value_29 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_30):
+                                                connect renamed_src_reg_0_0_2, _match_arm_value_30 @[reg_alloc.rs 185:33]
+                                        wire renamed_src_reg_0_1_2: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_49: Ty1
+                                        connect _bundle_literal_expr_49.value, _match_arm_value_28.alu_common.common.src[1]
+                                        connect rename_table_normal_0_src_1.addr, _bundle_literal_expr_49 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_50: Ty1
+                                        connect _bundle_literal_expr_50.value, _match_arm_value_28.alu_common.common.src[1]
+                                        connect rename_table_special_0_src_1.addr, _bundle_literal_expr_50 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_0_src_1.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_0_src_1.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_51: Ty25
+                                                        wire _bundle_literal_expr_52: Ty23
+                                                        connect _bundle_literal_expr_52.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_51.unit_num, _bundle_literal_expr_52
+                                                        wire _bundle_literal_expr_53: Ty24
+                                                        connect _bundle_literal_expr_53.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_51.unit_out_reg, _bundle_literal_expr_53
+                                                        connect renamed_src_reg_0_1_2, _bundle_literal_expr_51 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_31):
+                                                        connect renamed_src_reg_0_1_2, _match_arm_value_31 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_32):
+                                                connect renamed_src_reg_0_1_2, _match_arm_value_32 @[reg_alloc.rs 185:33]
+                                        wire _bundle_literal_expr_54: Ty36
+                                        wire _bundle_literal_expr_55: Ty34
+                                        wire _bundle_literal_expr_56: Ty33
+                                        connect _bundle_literal_expr_56.prefix_pad, _match_arm_value_28.alu_common.common.prefix_pad
+                                        connect _bundle_literal_expr_56.dest, _match_arm_value_4.unit_out_reg
                                         wire _array_literal_expr_13: UInt<6>[3]
                                         wire _array_literal_expr_14: UInt<6>[2]
-                                        wire _cast_bundle_to_bits_expr_18: Ty57
-                                        connect _cast_bundle_to_bits_expr_18.unit_num, rename_0_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_18.unit_out_reg, rename_0_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_18: Ty47
+                                        connect _cast_bundle_to_bits_expr_18.unit_num, renamed_src_reg_0_0_2.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_18.unit_out_reg, renamed_src_reg_0_0_2.unit_out_reg.value
                                         wire _cast_to_bits_expr_18: UInt<6>
                                         connect _cast_to_bits_expr_18, cat(_cast_bundle_to_bits_expr_18.unit_out_reg, _cast_bundle_to_bits_expr_18.unit_num)
                                         connect _array_literal_expr_14[0], _cast_to_bits_expr_18
-                                        wire _cast_bundle_to_bits_expr_19: Ty57
-                                        connect _cast_bundle_to_bits_expr_19.unit_num, rename_0_src_1.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_19.unit_out_reg, rename_0_src_1.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_19: Ty47
+                                        connect _cast_bundle_to_bits_expr_19.unit_num, renamed_src_reg_0_1_2.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_19.unit_out_reg, renamed_src_reg_0_1_2.unit_out_reg.value
                                         wire _cast_to_bits_expr_19: UInt<6>
                                         connect _cast_to_bits_expr_19, cat(_cast_bundle_to_bits_expr_19.unit_out_reg, _cast_bundle_to_bits_expr_19.unit_num)
                                         connect _array_literal_expr_14[1], _cast_to_bits_expr_19
                                         connect _array_literal_expr_13[0], _array_literal_expr_14[0]
                                         wire _array_literal_expr_15: UInt<6>[2]
-                                        wire _cast_bundle_to_bits_expr_20: Ty57
-                                        connect _cast_bundle_to_bits_expr_20.unit_num, rename_0_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_20.unit_out_reg, rename_0_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_20: Ty47
+                                        connect _cast_bundle_to_bits_expr_20.unit_num, renamed_src_reg_0_0_2.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_20.unit_out_reg, renamed_src_reg_0_0_2.unit_out_reg.value
                                         wire _cast_to_bits_expr_20: UInt<6>
                                         connect _cast_to_bits_expr_20, cat(_cast_bundle_to_bits_expr_20.unit_out_reg, _cast_bundle_to_bits_expr_20.unit_num)
                                         connect _array_literal_expr_15[0], _cast_to_bits_expr_20
-                                        wire _cast_bundle_to_bits_expr_21: Ty57
-                                        connect _cast_bundle_to_bits_expr_21.unit_num, rename_0_src_1.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_21.unit_out_reg, rename_0_src_1.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_21: Ty47
+                                        connect _cast_bundle_to_bits_expr_21.unit_num, renamed_src_reg_0_1_2.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_21.unit_out_reg, renamed_src_reg_0_1_2.unit_out_reg.value
                                         wire _cast_to_bits_expr_21: UInt<6>
                                         connect _cast_to_bits_expr_21, cat(_cast_bundle_to_bits_expr_21.unit_out_reg, _cast_bundle_to_bits_expr_21.unit_num)
                                         connect _array_literal_expr_15[1], _cast_to_bits_expr_21
                                         connect _array_literal_expr_13[1], _array_literal_expr_15[1]
-                                        wire _bundle_literal_expr_59: Ty60
-                                        connect _bundle_literal_expr_59.imm_low, _match_arm_value_18.alu_common.common.imm_low
+                                        wire _bundle_literal_expr_57: Ty50
+                                        connect _bundle_literal_expr_57.imm_low, _match_arm_value_28.alu_common.common.imm_low
                                         wire _array_literal_expr_16: UInt<8>[1]
-                                        connect _array_literal_expr_16[0], _match_arm_value_18.alu_common.common.src[2]
-                                        connect _bundle_literal_expr_59.reversed_src, _array_literal_expr_16
-                                        connect _bundle_literal_expr_59.imm_sign, _match_arm_value_18.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_22: Ty61
-                                        connect _cast_bundle_to_bits_expr_22.imm_low, _bundle_literal_expr_59.imm_low
-                                        connect _cast_bundle_to_bits_expr_22.reversed_src, _bundle_literal_expr_59.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_22.imm_sign, asUInt(_bundle_literal_expr_59.imm_sign)
+                                        connect _array_literal_expr_16[0], _match_arm_value_28.alu_common.common.src[2]
+                                        connect _bundle_literal_expr_57.reversed_src, _array_literal_expr_16
+                                        connect _bundle_literal_expr_57.imm_sign, _match_arm_value_28.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_22: Ty51
+                                        connect _cast_bundle_to_bits_expr_22.imm_low, _bundle_literal_expr_57.imm_low
+                                        connect _cast_bundle_to_bits_expr_22.reversed_src, _bundle_literal_expr_57.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_22.imm_sign, asUInt(_bundle_literal_expr_57.imm_sign)
                                         wire _cast_to_bits_expr_22: UInt<34>
                                         connect _cast_to_bits_expr_22, cat(_cast_bundle_to_bits_expr_22.imm_sign, cat(_cast_bundle_to_bits_expr_22.reversed_src, _cast_bundle_to_bits_expr_22.imm_low))
-                                        wire _cast_bits_to_bundle_expr_1: Ty60
-                                        wire _cast_bits_to_bundle_expr_flattened_1: Ty61
+                                        wire _cast_bits_to_bundle_expr_1: Ty50
+                                        wire _cast_bits_to_bundle_expr_flattened_1: Ty51
                                         connect _cast_bits_to_bundle_expr_flattened_1.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_22)), 24, 0)
                                         connect _cast_bits_to_bundle_expr_1.imm_low, _cast_bits_to_bundle_expr_flattened_1.imm_low
                                         connect _cast_bits_to_bundle_expr_flattened_1.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_22)), 32, 25)
@@ -1098,67 +940,67 @@ circuit reg_alloc:
                                         connect _cast_bits_to_bundle_expr_flattened_1.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_22)), 33, 33)
                                         connect _cast_bits_to_bundle_expr_1.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_1.imm_sign)
                                         connect _array_literal_expr_13[2], tail(_cast_bits_to_bundle_expr_1.reversed_src[0], 2)
-                                        connect _bundle_literal_expr_58.src, _array_literal_expr_13
-                                        wire _bundle_literal_expr_60: Ty60
-                                        connect _bundle_literal_expr_60.imm_low, _match_arm_value_18.alu_common.common.imm_low
+                                        connect _bundle_literal_expr_56.src, _array_literal_expr_13
+                                        wire _bundle_literal_expr_58: Ty50
+                                        connect _bundle_literal_expr_58.imm_low, _match_arm_value_28.alu_common.common.imm_low
                                         wire _array_literal_expr_17: UInt<8>[1]
-                                        connect _array_literal_expr_17[0], _match_arm_value_18.alu_common.common.src[2]
-                                        connect _bundle_literal_expr_60.reversed_src, _array_literal_expr_17
-                                        connect _bundle_literal_expr_60.imm_sign, _match_arm_value_18.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_23: Ty61
-                                        connect _cast_bundle_to_bits_expr_23.imm_low, _bundle_literal_expr_60.imm_low
-                                        connect _cast_bundle_to_bits_expr_23.reversed_src, _bundle_literal_expr_60.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_23.imm_sign, asUInt(_bundle_literal_expr_60.imm_sign)
+                                        connect _array_literal_expr_17[0], _match_arm_value_28.alu_common.common.src[2]
+                                        connect _bundle_literal_expr_58.reversed_src, _array_literal_expr_17
+                                        connect _bundle_literal_expr_58.imm_sign, _match_arm_value_28.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_23: Ty51
+                                        connect _cast_bundle_to_bits_expr_23.imm_low, _bundle_literal_expr_58.imm_low
+                                        connect _cast_bundle_to_bits_expr_23.reversed_src, _bundle_literal_expr_58.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_23.imm_sign, asUInt(_bundle_literal_expr_58.imm_sign)
                                         wire _cast_to_bits_expr_23: UInt<34>
                                         connect _cast_to_bits_expr_23, cat(_cast_bundle_to_bits_expr_23.imm_sign, cat(_cast_bundle_to_bits_expr_23.reversed_src, _cast_bundle_to_bits_expr_23.imm_low))
-                                        connect _bundle_literal_expr_58.imm_low, bits(asSInt(_cast_to_bits_expr_23), 24, 0)
-                                        wire _bundle_literal_expr_61: Ty60
-                                        connect _bundle_literal_expr_61.imm_low, _match_arm_value_18.alu_common.common.imm_low
+                                        connect _bundle_literal_expr_56.imm_low, bits(asSInt(_cast_to_bits_expr_23), 24, 0)
+                                        wire _bundle_literal_expr_59: Ty50
+                                        connect _bundle_literal_expr_59.imm_low, _match_arm_value_28.alu_common.common.imm_low
                                         wire _array_literal_expr_18: UInt<8>[1]
-                                        connect _array_literal_expr_18[0], _match_arm_value_18.alu_common.common.src[2]
-                                        connect _bundle_literal_expr_61.reversed_src, _array_literal_expr_18
-                                        connect _bundle_literal_expr_61.imm_sign, _match_arm_value_18.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_24: Ty61
-                                        connect _cast_bundle_to_bits_expr_24.imm_low, _bundle_literal_expr_61.imm_low
-                                        connect _cast_bundle_to_bits_expr_24.reversed_src, _bundle_literal_expr_61.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_24.imm_sign, asUInt(_bundle_literal_expr_61.imm_sign)
+                                        connect _array_literal_expr_18[0], _match_arm_value_28.alu_common.common.src[2]
+                                        connect _bundle_literal_expr_59.reversed_src, _array_literal_expr_18
+                                        connect _bundle_literal_expr_59.imm_sign, _match_arm_value_28.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_24: Ty51
+                                        connect _cast_bundle_to_bits_expr_24.imm_low, _bundle_literal_expr_59.imm_low
+                                        connect _cast_bundle_to_bits_expr_24.reversed_src, _bundle_literal_expr_59.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_24.imm_sign, asUInt(_bundle_literal_expr_59.imm_sign)
                                         wire _cast_to_bits_expr_24: UInt<34>
                                         connect _cast_to_bits_expr_24, cat(_cast_bundle_to_bits_expr_24.imm_sign, cat(_cast_bundle_to_bits_expr_24.reversed_src, _cast_bundle_to_bits_expr_24.imm_low))
-                                        connect _bundle_literal_expr_58.imm_sign, shr(asSInt(_cast_to_bits_expr_24), 33)
-                                        wire _bundle_literal_expr_62: Ty2
-                                        invalidate _bundle_literal_expr_62
-                                        connect _bundle_literal_expr_58._phantom, _bundle_literal_expr_62
-                                        connect _bundle_literal_expr_57.common, _bundle_literal_expr_58
-                                        connect _bundle_literal_expr_57.output_integer_mode, _match_arm_value_18.alu_common.output_integer_mode
-                                        connect _bundle_literal_expr_56.alu_common, _bundle_literal_expr_57
-                                        connect _bundle_literal_expr_56.lut, _match_arm_value_18.lut
-                                        connect mapped_regs_1, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(Logical, _bundle_literal_expr_56) @[instruction.rs 477:1]
-                                connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(AluBranch, mapped_regs_1) @[unit.rs 127:1]
-                            L2RegisterFile(_match_arm_value_19):
-                                wire mapped_regs_2: Ty49 @[instruction.rs 504:1]
-                                match _match_arm_value_19: @[instruction.rs 504:1]
-                                    ReadL2Reg(_match_arm_value_20):
-                                        wire _bundle_literal_expr_63: Ty48
-                                        wire _bundle_literal_expr_64: Ty47
-                                        connect _bundle_literal_expr_64.prefix_pad, _match_arm_value_20.common.prefix_pad
-                                        connect _bundle_literal_expr_64.dest, _match_arm_value_4.unit_out_reg
+                                        connect _bundle_literal_expr_56.imm_sign, shr(asSInt(_cast_to_bits_expr_24), 33)
+                                        wire _bundle_literal_expr_60: Ty2
+                                        invalidate _bundle_literal_expr_60
+                                        connect _bundle_literal_expr_56._phantom, _bundle_literal_expr_60
+                                        connect _bundle_literal_expr_55.common, _bundle_literal_expr_56
+                                        connect _bundle_literal_expr_55.output_integer_mode, _match_arm_value_28.alu_common.output_integer_mode
+                                        connect _bundle_literal_expr_54.alu_common, _bundle_literal_expr_55
+                                        connect _bundle_literal_expr_54.lut, _match_arm_value_28.lut
+                                        connect mapped_regs_1, {|AddSub: Ty35, AddSubI: Ty35, Logical: Ty36|}(Logical, _bundle_literal_expr_54) @[instruction.rs 477:1]
+                                connect mapped_regs, {|AluBranch: Ty37, L2RegisterFile: Ty40, LoadStore: Ty41|}(AluBranch, mapped_regs_1) @[unit.rs 127:1]
+                            L2RegisterFile(_match_arm_value_33):
+                                wire mapped_regs_2: Ty40 @[instruction.rs 504:1]
+                                match _match_arm_value_33: @[instruction.rs 504:1]
+                                    ReadL2Reg(_match_arm_value_34):
+                                        wire _bundle_literal_expr_61: Ty39
+                                        wire _bundle_literal_expr_62: Ty38
+                                        connect _bundle_literal_expr_62.prefix_pad, _match_arm_value_34.common.prefix_pad
+                                        connect _bundle_literal_expr_62.dest, _match_arm_value_4.unit_out_reg
                                         wire _array_literal_expr_19: UInt<6>[3]
                                         connect _array_literal_expr_19[0], pad(UInt<0>(0h0), 6)
                                         connect _array_literal_expr_19[1], pad(UInt<0>(0h0), 6)
-                                        wire _bundle_literal_expr_65: Ty60
-                                        connect _bundle_literal_expr_65.imm_low, _match_arm_value_20.common.imm_low
+                                        wire _bundle_literal_expr_63: Ty50
+                                        connect _bundle_literal_expr_63.imm_low, _match_arm_value_34.common.imm_low
                                         wire _array_literal_expr_20: UInt<8>[1]
-                                        connect _array_literal_expr_20[0], _match_arm_value_20.common.src[2]
-                                        connect _bundle_literal_expr_65.reversed_src, _array_literal_expr_20
-                                        connect _bundle_literal_expr_65.imm_sign, _match_arm_value_20.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_25: Ty61
-                                        connect _cast_bundle_to_bits_expr_25.imm_low, _bundle_literal_expr_65.imm_low
-                                        connect _cast_bundle_to_bits_expr_25.reversed_src, _bundle_literal_expr_65.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_25.imm_sign, asUInt(_bundle_literal_expr_65.imm_sign)
+                                        connect _array_literal_expr_20[0], _match_arm_value_34.common.src[2]
+                                        connect _bundle_literal_expr_63.reversed_src, _array_literal_expr_20
+                                        connect _bundle_literal_expr_63.imm_sign, _match_arm_value_34.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_25: Ty51
+                                        connect _cast_bundle_to_bits_expr_25.imm_low, _bundle_literal_expr_63.imm_low
+                                        connect _cast_bundle_to_bits_expr_25.reversed_src, _bundle_literal_expr_63.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_25.imm_sign, asUInt(_bundle_literal_expr_63.imm_sign)
                                         wire _cast_to_bits_expr_25: UInt<34>
                                         connect _cast_to_bits_expr_25, cat(_cast_bundle_to_bits_expr_25.imm_sign, cat(_cast_bundle_to_bits_expr_25.reversed_src, _cast_bundle_to_bits_expr_25.imm_low))
-                                        wire _cast_bits_to_bundle_expr_2: Ty60
-                                        wire _cast_bits_to_bundle_expr_flattened_2: Ty61
+                                        wire _cast_bits_to_bundle_expr_2: Ty50
+                                        wire _cast_bits_to_bundle_expr_flattened_2: Ty51
                                         connect _cast_bits_to_bundle_expr_flattened_2.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_25)), 24, 0)
                                         connect _cast_bits_to_bundle_expr_2.imm_low, _cast_bits_to_bundle_expr_flattened_2.imm_low
                                         connect _cast_bits_to_bundle_expr_flattened_2.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_25)), 32, 25)
@@ -1170,70 +1012,90 @@ circuit reg_alloc:
                                         connect _cast_bits_to_bundle_expr_flattened_2.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_25)), 33, 33)
                                         connect _cast_bits_to_bundle_expr_2.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_2.imm_sign)
                                         connect _array_literal_expr_19[2], tail(_cast_bits_to_bundle_expr_2.reversed_src[0], 2)
-                                        connect _bundle_literal_expr_64.src, _array_literal_expr_19
-                                        wire _bundle_literal_expr_66: Ty60
-                                        connect _bundle_literal_expr_66.imm_low, _match_arm_value_20.common.imm_low
+                                        connect _bundle_literal_expr_62.src, _array_literal_expr_19
+                                        wire _bundle_literal_expr_64: Ty50
+                                        connect _bundle_literal_expr_64.imm_low, _match_arm_value_34.common.imm_low
                                         wire _array_literal_expr_21: UInt<8>[1]
-                                        connect _array_literal_expr_21[0], _match_arm_value_20.common.src[2]
-                                        connect _bundle_literal_expr_66.reversed_src, _array_literal_expr_21
-                                        connect _bundle_literal_expr_66.imm_sign, _match_arm_value_20.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_26: Ty61
-                                        connect _cast_bundle_to_bits_expr_26.imm_low, _bundle_literal_expr_66.imm_low
-                                        connect _cast_bundle_to_bits_expr_26.reversed_src, _bundle_literal_expr_66.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_26.imm_sign, asUInt(_bundle_literal_expr_66.imm_sign)
+                                        connect _array_literal_expr_21[0], _match_arm_value_34.common.src[2]
+                                        connect _bundle_literal_expr_64.reversed_src, _array_literal_expr_21
+                                        connect _bundle_literal_expr_64.imm_sign, _match_arm_value_34.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_26: Ty51
+                                        connect _cast_bundle_to_bits_expr_26.imm_low, _bundle_literal_expr_64.imm_low
+                                        connect _cast_bundle_to_bits_expr_26.reversed_src, _bundle_literal_expr_64.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_26.imm_sign, asUInt(_bundle_literal_expr_64.imm_sign)
                                         wire _cast_to_bits_expr_26: UInt<34>
                                         connect _cast_to_bits_expr_26, cat(_cast_bundle_to_bits_expr_26.imm_sign, cat(_cast_bundle_to_bits_expr_26.reversed_src, _cast_bundle_to_bits_expr_26.imm_low))
-                                        connect _bundle_literal_expr_64.imm_low, bits(asSInt(_cast_to_bits_expr_26), 24, 0)
-                                        wire _bundle_literal_expr_67: Ty60
-                                        connect _bundle_literal_expr_67.imm_low, _match_arm_value_20.common.imm_low
+                                        connect _bundle_literal_expr_62.imm_low, bits(asSInt(_cast_to_bits_expr_26), 24, 0)
+                                        wire _bundle_literal_expr_65: Ty50
+                                        connect _bundle_literal_expr_65.imm_low, _match_arm_value_34.common.imm_low
                                         wire _array_literal_expr_22: UInt<8>[1]
-                                        connect _array_literal_expr_22[0], _match_arm_value_20.common.src[2]
-                                        connect _bundle_literal_expr_67.reversed_src, _array_literal_expr_22
-                                        connect _bundle_literal_expr_67.imm_sign, _match_arm_value_20.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_27: Ty61
-                                        connect _cast_bundle_to_bits_expr_27.imm_low, _bundle_literal_expr_67.imm_low
-                                        connect _cast_bundle_to_bits_expr_27.reversed_src, _bundle_literal_expr_67.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_27.imm_sign, asUInt(_bundle_literal_expr_67.imm_sign)
+                                        connect _array_literal_expr_22[0], _match_arm_value_34.common.src[2]
+                                        connect _bundle_literal_expr_65.reversed_src, _array_literal_expr_22
+                                        connect _bundle_literal_expr_65.imm_sign, _match_arm_value_34.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_27: Ty51
+                                        connect _cast_bundle_to_bits_expr_27.imm_low, _bundle_literal_expr_65.imm_low
+                                        connect _cast_bundle_to_bits_expr_27.reversed_src, _bundle_literal_expr_65.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_27.imm_sign, asUInt(_bundle_literal_expr_65.imm_sign)
                                         wire _cast_to_bits_expr_27: UInt<34>
                                         connect _cast_to_bits_expr_27, cat(_cast_bundle_to_bits_expr_27.imm_sign, cat(_cast_bundle_to_bits_expr_27.reversed_src, _cast_bundle_to_bits_expr_27.imm_low))
-                                        connect _bundle_literal_expr_64.imm_sign, shr(asSInt(_cast_to_bits_expr_27), 33)
-                                        wire _bundle_literal_expr_68: Ty2
-                                        invalidate _bundle_literal_expr_68
-                                        connect _bundle_literal_expr_64._phantom, _bundle_literal_expr_68
-                                        connect _bundle_literal_expr_63.common, _bundle_literal_expr_64
-                                        connect mapped_regs_2, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(ReadL2Reg, _bundle_literal_expr_63) @[instruction.rs 504:1]
-                                    WriteL2Reg(_match_arm_value_21):
-                                        wire _bundle_literal_expr_69: Ty1
-                                        connect _bundle_literal_expr_69.value, _match_arm_value_21.common.src[0]
-                                        connect rename_0_src_0.addr, _bundle_literal_expr_69 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_70: Ty48
-                                        wire _bundle_literal_expr_71: Ty47
-                                        connect _bundle_literal_expr_71.prefix_pad, _match_arm_value_21.common.prefix_pad
-                                        connect _bundle_literal_expr_71.dest, _match_arm_value_4.unit_out_reg
+                                        connect _bundle_literal_expr_62.imm_sign, shr(asSInt(_cast_to_bits_expr_27), 33)
+                                        wire _bundle_literal_expr_66: Ty2
+                                        invalidate _bundle_literal_expr_66
+                                        connect _bundle_literal_expr_62._phantom, _bundle_literal_expr_66
+                                        connect _bundle_literal_expr_61.common, _bundle_literal_expr_62
+                                        connect mapped_regs_2, {|ReadL2Reg: Ty39, WriteL2Reg: Ty39|}(ReadL2Reg, _bundle_literal_expr_61) @[instruction.rs 504:1]
+                                    WriteL2Reg(_match_arm_value_35):
+                                        wire renamed_src_reg_0_0_3: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_67: Ty1
+                                        connect _bundle_literal_expr_67.value, _match_arm_value_35.common.src[0]
+                                        connect rename_table_normal_0_src_0.addr, _bundle_literal_expr_67 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_68: Ty1
+                                        connect _bundle_literal_expr_68.value, _match_arm_value_35.common.src[0]
+                                        connect rename_table_special_0_src_0.addr, _bundle_literal_expr_68 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_0_src_0.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_0_src_0.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_69: Ty25
+                                                        wire _bundle_literal_expr_70: Ty23
+                                                        connect _bundle_literal_expr_70.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_69.unit_num, _bundle_literal_expr_70
+                                                        wire _bundle_literal_expr_71: Ty24
+                                                        connect _bundle_literal_expr_71.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_69.unit_out_reg, _bundle_literal_expr_71
+                                                        connect renamed_src_reg_0_0_3, _bundle_literal_expr_69 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_36):
+                                                        connect renamed_src_reg_0_0_3, _match_arm_value_36 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_37):
+                                                connect renamed_src_reg_0_0_3, _match_arm_value_37 @[reg_alloc.rs 185:33]
+                                        wire _bundle_literal_expr_72: Ty39
+                                        wire _bundle_literal_expr_73: Ty38
+                                        connect _bundle_literal_expr_73.prefix_pad, _match_arm_value_35.common.prefix_pad
+                                        connect _bundle_literal_expr_73.dest, _match_arm_value_4.unit_out_reg
                                         wire _array_literal_expr_23: UInt<6>[3]
                                         wire _array_literal_expr_24: UInt<6>[1]
-                                        wire _cast_bundle_to_bits_expr_28: Ty57
-                                        connect _cast_bundle_to_bits_expr_28.unit_num, rename_0_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_28.unit_out_reg, rename_0_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_28: Ty47
+                                        connect _cast_bundle_to_bits_expr_28.unit_num, renamed_src_reg_0_0_3.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_28.unit_out_reg, renamed_src_reg_0_0_3.unit_out_reg.value
                                         wire _cast_to_bits_expr_28: UInt<6>
                                         connect _cast_to_bits_expr_28, cat(_cast_bundle_to_bits_expr_28.unit_out_reg, _cast_bundle_to_bits_expr_28.unit_num)
                                         connect _array_literal_expr_24[0], _cast_to_bits_expr_28
                                         connect _array_literal_expr_23[0], _array_literal_expr_24[0]
                                         connect _array_literal_expr_23[1], pad(UInt<0>(0h0), 6)
-                                        wire _bundle_literal_expr_72: Ty60
-                                        connect _bundle_literal_expr_72.imm_low, _match_arm_value_21.common.imm_low
+                                        wire _bundle_literal_expr_74: Ty50
+                                        connect _bundle_literal_expr_74.imm_low, _match_arm_value_35.common.imm_low
                                         wire _array_literal_expr_25: UInt<8>[1]
-                                        connect _array_literal_expr_25[0], _match_arm_value_21.common.src[2]
-                                        connect _bundle_literal_expr_72.reversed_src, _array_literal_expr_25
-                                        connect _bundle_literal_expr_72.imm_sign, _match_arm_value_21.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_29: Ty61
-                                        connect _cast_bundle_to_bits_expr_29.imm_low, _bundle_literal_expr_72.imm_low
-                                        connect _cast_bundle_to_bits_expr_29.reversed_src, _bundle_literal_expr_72.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_29.imm_sign, asUInt(_bundle_literal_expr_72.imm_sign)
+                                        connect _array_literal_expr_25[0], _match_arm_value_35.common.src[2]
+                                        connect _bundle_literal_expr_74.reversed_src, _array_literal_expr_25
+                                        connect _bundle_literal_expr_74.imm_sign, _match_arm_value_35.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_29: Ty51
+                                        connect _cast_bundle_to_bits_expr_29.imm_low, _bundle_literal_expr_74.imm_low
+                                        connect _cast_bundle_to_bits_expr_29.reversed_src, _bundle_literal_expr_74.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_29.imm_sign, asUInt(_bundle_literal_expr_74.imm_sign)
                                         wire _cast_to_bits_expr_29: UInt<34>
                                         connect _cast_to_bits_expr_29, cat(_cast_bundle_to_bits_expr_29.imm_sign, cat(_cast_bundle_to_bits_expr_29.reversed_src, _cast_bundle_to_bits_expr_29.imm_low))
-                                        wire _cast_bits_to_bundle_expr_3: Ty60
-                                        wire _cast_bits_to_bundle_expr_flattened_3: Ty61
+                                        wire _cast_bits_to_bundle_expr_3: Ty50
+                                        wire _cast_bits_to_bundle_expr_flattened_3: Ty51
                                         connect _cast_bits_to_bundle_expr_flattened_3.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_29)), 24, 0)
                                         connect _cast_bits_to_bundle_expr_3.imm_low, _cast_bits_to_bundle_expr_flattened_3.imm_low
                                         connect _cast_bits_to_bundle_expr_flattened_3.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_29)), 32, 25)
@@ -1245,63 +1107,63 @@ circuit reg_alloc:
                                         connect _cast_bits_to_bundle_expr_flattened_3.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_29)), 33, 33)
                                         connect _cast_bits_to_bundle_expr_3.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_3.imm_sign)
                                         connect _array_literal_expr_23[2], tail(_cast_bits_to_bundle_expr_3.reversed_src[0], 2)
-                                        connect _bundle_literal_expr_71.src, _array_literal_expr_23
-                                        wire _bundle_literal_expr_73: Ty60
-                                        connect _bundle_literal_expr_73.imm_low, _match_arm_value_21.common.imm_low
+                                        connect _bundle_literal_expr_73.src, _array_literal_expr_23
+                                        wire _bundle_literal_expr_75: Ty50
+                                        connect _bundle_literal_expr_75.imm_low, _match_arm_value_35.common.imm_low
                                         wire _array_literal_expr_26: UInt<8>[1]
-                                        connect _array_literal_expr_26[0], _match_arm_value_21.common.src[2]
-                                        connect _bundle_literal_expr_73.reversed_src, _array_literal_expr_26
-                                        connect _bundle_literal_expr_73.imm_sign, _match_arm_value_21.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_30: Ty61
-                                        connect _cast_bundle_to_bits_expr_30.imm_low, _bundle_literal_expr_73.imm_low
-                                        connect _cast_bundle_to_bits_expr_30.reversed_src, _bundle_literal_expr_73.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_30.imm_sign, asUInt(_bundle_literal_expr_73.imm_sign)
+                                        connect _array_literal_expr_26[0], _match_arm_value_35.common.src[2]
+                                        connect _bundle_literal_expr_75.reversed_src, _array_literal_expr_26
+                                        connect _bundle_literal_expr_75.imm_sign, _match_arm_value_35.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_30: Ty51
+                                        connect _cast_bundle_to_bits_expr_30.imm_low, _bundle_literal_expr_75.imm_low
+                                        connect _cast_bundle_to_bits_expr_30.reversed_src, _bundle_literal_expr_75.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_30.imm_sign, asUInt(_bundle_literal_expr_75.imm_sign)
                                         wire _cast_to_bits_expr_30: UInt<34>
                                         connect _cast_to_bits_expr_30, cat(_cast_bundle_to_bits_expr_30.imm_sign, cat(_cast_bundle_to_bits_expr_30.reversed_src, _cast_bundle_to_bits_expr_30.imm_low))
-                                        connect _bundle_literal_expr_71.imm_low, bits(asSInt(_cast_to_bits_expr_30), 24, 0)
-                                        wire _bundle_literal_expr_74: Ty60
-                                        connect _bundle_literal_expr_74.imm_low, _match_arm_value_21.common.imm_low
+                                        connect _bundle_literal_expr_73.imm_low, bits(asSInt(_cast_to_bits_expr_30), 24, 0)
+                                        wire _bundle_literal_expr_76: Ty50
+                                        connect _bundle_literal_expr_76.imm_low, _match_arm_value_35.common.imm_low
                                         wire _array_literal_expr_27: UInt<8>[1]
-                                        connect _array_literal_expr_27[0], _match_arm_value_21.common.src[2]
-                                        connect _bundle_literal_expr_74.reversed_src, _array_literal_expr_27
-                                        connect _bundle_literal_expr_74.imm_sign, _match_arm_value_21.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_31: Ty61
-                                        connect _cast_bundle_to_bits_expr_31.imm_low, _bundle_literal_expr_74.imm_low
-                                        connect _cast_bundle_to_bits_expr_31.reversed_src, _bundle_literal_expr_74.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_31.imm_sign, asUInt(_bundle_literal_expr_74.imm_sign)
+                                        connect _array_literal_expr_27[0], _match_arm_value_35.common.src[2]
+                                        connect _bundle_literal_expr_76.reversed_src, _array_literal_expr_27
+                                        connect _bundle_literal_expr_76.imm_sign, _match_arm_value_35.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_31: Ty51
+                                        connect _cast_bundle_to_bits_expr_31.imm_low, _bundle_literal_expr_76.imm_low
+                                        connect _cast_bundle_to_bits_expr_31.reversed_src, _bundle_literal_expr_76.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_31.imm_sign, asUInt(_bundle_literal_expr_76.imm_sign)
                                         wire _cast_to_bits_expr_31: UInt<34>
                                         connect _cast_to_bits_expr_31, cat(_cast_bundle_to_bits_expr_31.imm_sign, cat(_cast_bundle_to_bits_expr_31.reversed_src, _cast_bundle_to_bits_expr_31.imm_low))
-                                        connect _bundle_literal_expr_71.imm_sign, shr(asSInt(_cast_to_bits_expr_31), 33)
-                                        wire _bundle_literal_expr_75: Ty2
-                                        invalidate _bundle_literal_expr_75
-                                        connect _bundle_literal_expr_71._phantom, _bundle_literal_expr_75
-                                        connect _bundle_literal_expr_70.common, _bundle_literal_expr_71
-                                        connect mapped_regs_2, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(WriteL2Reg, _bundle_literal_expr_70) @[instruction.rs 504:1]
-                                connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(L2RegisterFile, mapped_regs_2) @[unit.rs 127:1]
-                            LoadStore(_match_arm_value_22):
-                                wire mapped_regs_3: Ty50 @[instruction.rs 539:1]
-                                match _match_arm_value_22: @[instruction.rs 539:1]
-                                    Load(_match_arm_value_23):
-                                        wire _bundle_literal_expr_76: Ty47
-                                        connect _bundle_literal_expr_76.prefix_pad, _match_arm_value_23.prefix_pad
-                                        connect _bundle_literal_expr_76.dest, _match_arm_value_4.unit_out_reg
+                                        connect _bundle_literal_expr_73.imm_sign, shr(asSInt(_cast_to_bits_expr_31), 33)
+                                        wire _bundle_literal_expr_77: Ty2
+                                        invalidate _bundle_literal_expr_77
+                                        connect _bundle_literal_expr_73._phantom, _bundle_literal_expr_77
+                                        connect _bundle_literal_expr_72.common, _bundle_literal_expr_73
+                                        connect mapped_regs_2, {|ReadL2Reg: Ty39, WriteL2Reg: Ty39|}(WriteL2Reg, _bundle_literal_expr_72) @[instruction.rs 504:1]
+                                connect mapped_regs, {|AluBranch: Ty37, L2RegisterFile: Ty40, LoadStore: Ty41|}(L2RegisterFile, mapped_regs_2) @[unit.rs 127:1]
+                            LoadStore(_match_arm_value_38):
+                                wire mapped_regs_3: Ty41 @[instruction.rs 539:1]
+                                match _match_arm_value_38: @[instruction.rs 539:1]
+                                    Load(_match_arm_value_39):
+                                        wire _bundle_literal_expr_78: Ty38
+                                        connect _bundle_literal_expr_78.prefix_pad, _match_arm_value_39.prefix_pad
+                                        connect _bundle_literal_expr_78.dest, _match_arm_value_4.unit_out_reg
                                         wire _array_literal_expr_28: UInt<6>[3]
                                         connect _array_literal_expr_28[0], pad(UInt<0>(0h0), 6)
                                         connect _array_literal_expr_28[1], pad(UInt<0>(0h0), 6)
-                                        wire _bundle_literal_expr_77: Ty60
-                                        connect _bundle_literal_expr_77.imm_low, _match_arm_value_23.imm_low
+                                        wire _bundle_literal_expr_79: Ty50
+                                        connect _bundle_literal_expr_79.imm_low, _match_arm_value_39.imm_low
                                         wire _array_literal_expr_29: UInt<8>[1]
-                                        connect _array_literal_expr_29[0], _match_arm_value_23.src[2]
-                                        connect _bundle_literal_expr_77.reversed_src, _array_literal_expr_29
-                                        connect _bundle_literal_expr_77.imm_sign, _match_arm_value_23.imm_sign
-                                        wire _cast_bundle_to_bits_expr_32: Ty61
-                                        connect _cast_bundle_to_bits_expr_32.imm_low, _bundle_literal_expr_77.imm_low
-                                        connect _cast_bundle_to_bits_expr_32.reversed_src, _bundle_literal_expr_77.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_32.imm_sign, asUInt(_bundle_literal_expr_77.imm_sign)
+                                        connect _array_literal_expr_29[0], _match_arm_value_39.src[2]
+                                        connect _bundle_literal_expr_79.reversed_src, _array_literal_expr_29
+                                        connect _bundle_literal_expr_79.imm_sign, _match_arm_value_39.imm_sign
+                                        wire _cast_bundle_to_bits_expr_32: Ty51
+                                        connect _cast_bundle_to_bits_expr_32.imm_low, _bundle_literal_expr_79.imm_low
+                                        connect _cast_bundle_to_bits_expr_32.reversed_src, _bundle_literal_expr_79.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_32.imm_sign, asUInt(_bundle_literal_expr_79.imm_sign)
                                         wire _cast_to_bits_expr_32: UInt<34>
                                         connect _cast_to_bits_expr_32, cat(_cast_bundle_to_bits_expr_32.imm_sign, cat(_cast_bundle_to_bits_expr_32.reversed_src, _cast_bundle_to_bits_expr_32.imm_low))
-                                        wire _cast_bits_to_bundle_expr_4: Ty60
-                                        wire _cast_bits_to_bundle_expr_flattened_4: Ty61
+                                        wire _cast_bits_to_bundle_expr_4: Ty50
+                                        wire _cast_bits_to_bundle_expr_flattened_4: Ty51
                                         connect _cast_bits_to_bundle_expr_flattened_4.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_32)), 24, 0)
                                         connect _cast_bits_to_bundle_expr_4.imm_low, _cast_bits_to_bundle_expr_flattened_4.imm_low
                                         connect _cast_bits_to_bundle_expr_flattened_4.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_32)), 32, 25)
@@ -1313,68 +1175,88 @@ circuit reg_alloc:
                                         connect _cast_bits_to_bundle_expr_flattened_4.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_32)), 33, 33)
                                         connect _cast_bits_to_bundle_expr_4.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_4.imm_sign)
                                         connect _array_literal_expr_28[2], tail(_cast_bits_to_bundle_expr_4.reversed_src[0], 2)
-                                        connect _bundle_literal_expr_76.src, _array_literal_expr_28
-                                        wire _bundle_literal_expr_78: Ty60
-                                        connect _bundle_literal_expr_78.imm_low, _match_arm_value_23.imm_low
+                                        connect _bundle_literal_expr_78.src, _array_literal_expr_28
+                                        wire _bundle_literal_expr_80: Ty50
+                                        connect _bundle_literal_expr_80.imm_low, _match_arm_value_39.imm_low
                                         wire _array_literal_expr_30: UInt<8>[1]
-                                        connect _array_literal_expr_30[0], _match_arm_value_23.src[2]
-                                        connect _bundle_literal_expr_78.reversed_src, _array_literal_expr_30
-                                        connect _bundle_literal_expr_78.imm_sign, _match_arm_value_23.imm_sign
-                                        wire _cast_bundle_to_bits_expr_33: Ty61
-                                        connect _cast_bundle_to_bits_expr_33.imm_low, _bundle_literal_expr_78.imm_low
-                                        connect _cast_bundle_to_bits_expr_33.reversed_src, _bundle_literal_expr_78.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_33.imm_sign, asUInt(_bundle_literal_expr_78.imm_sign)
+                                        connect _array_literal_expr_30[0], _match_arm_value_39.src[2]
+                                        connect _bundle_literal_expr_80.reversed_src, _array_literal_expr_30
+                                        connect _bundle_literal_expr_80.imm_sign, _match_arm_value_39.imm_sign
+                                        wire _cast_bundle_to_bits_expr_33: Ty51
+                                        connect _cast_bundle_to_bits_expr_33.imm_low, _bundle_literal_expr_80.imm_low
+                                        connect _cast_bundle_to_bits_expr_33.reversed_src, _bundle_literal_expr_80.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_33.imm_sign, asUInt(_bundle_literal_expr_80.imm_sign)
                                         wire _cast_to_bits_expr_33: UInt<34>
                                         connect _cast_to_bits_expr_33, cat(_cast_bundle_to_bits_expr_33.imm_sign, cat(_cast_bundle_to_bits_expr_33.reversed_src, _cast_bundle_to_bits_expr_33.imm_low))
-                                        connect _bundle_literal_expr_76.imm_low, bits(asSInt(_cast_to_bits_expr_33), 24, 0)
-                                        wire _bundle_literal_expr_79: Ty60
-                                        connect _bundle_literal_expr_79.imm_low, _match_arm_value_23.imm_low
+                                        connect _bundle_literal_expr_78.imm_low, bits(asSInt(_cast_to_bits_expr_33), 24, 0)
+                                        wire _bundle_literal_expr_81: Ty50
+                                        connect _bundle_literal_expr_81.imm_low, _match_arm_value_39.imm_low
                                         wire _array_literal_expr_31: UInt<8>[1]
-                                        connect _array_literal_expr_31[0], _match_arm_value_23.src[2]
-                                        connect _bundle_literal_expr_79.reversed_src, _array_literal_expr_31
-                                        connect _bundle_literal_expr_79.imm_sign, _match_arm_value_23.imm_sign
-                                        wire _cast_bundle_to_bits_expr_34: Ty61
-                                        connect _cast_bundle_to_bits_expr_34.imm_low, _bundle_literal_expr_79.imm_low
-                                        connect _cast_bundle_to_bits_expr_34.reversed_src, _bundle_literal_expr_79.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_34.imm_sign, asUInt(_bundle_literal_expr_79.imm_sign)
+                                        connect _array_literal_expr_31[0], _match_arm_value_39.src[2]
+                                        connect _bundle_literal_expr_81.reversed_src, _array_literal_expr_31
+                                        connect _bundle_literal_expr_81.imm_sign, _match_arm_value_39.imm_sign
+                                        wire _cast_bundle_to_bits_expr_34: Ty51
+                                        connect _cast_bundle_to_bits_expr_34.imm_low, _bundle_literal_expr_81.imm_low
+                                        connect _cast_bundle_to_bits_expr_34.reversed_src, _bundle_literal_expr_81.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_34.imm_sign, asUInt(_bundle_literal_expr_81.imm_sign)
                                         wire _cast_to_bits_expr_34: UInt<34>
                                         connect _cast_to_bits_expr_34, cat(_cast_bundle_to_bits_expr_34.imm_sign, cat(_cast_bundle_to_bits_expr_34.reversed_src, _cast_bundle_to_bits_expr_34.imm_low))
-                                        connect _bundle_literal_expr_76.imm_sign, shr(asSInt(_cast_to_bits_expr_34), 33)
-                                        wire _bundle_literal_expr_80: Ty2
-                                        invalidate _bundle_literal_expr_80
-                                        connect _bundle_literal_expr_76._phantom, _bundle_literal_expr_80
-                                        connect mapped_regs_3, {|Load: Ty47, Store: Ty47|}(Load, _bundle_literal_expr_76) @[instruction.rs 539:1]
-                                    Store(_match_arm_value_24):
-                                        wire _bundle_literal_expr_81: Ty1
-                                        connect _bundle_literal_expr_81.value, _match_arm_value_24.src[0]
-                                        connect rename_0_src_0.addr, _bundle_literal_expr_81 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_82: Ty47
-                                        connect _bundle_literal_expr_82.prefix_pad, _match_arm_value_24.prefix_pad
-                                        connect _bundle_literal_expr_82.dest, _match_arm_value_4.unit_out_reg
+                                        connect _bundle_literal_expr_78.imm_sign, shr(asSInt(_cast_to_bits_expr_34), 33)
+                                        wire _bundle_literal_expr_82: Ty2
+                                        invalidate _bundle_literal_expr_82
+                                        connect _bundle_literal_expr_78._phantom, _bundle_literal_expr_82
+                                        connect mapped_regs_3, {|Load: Ty38, Store: Ty38|}(Load, _bundle_literal_expr_78) @[instruction.rs 539:1]
+                                    Store(_match_arm_value_40):
+                                        wire renamed_src_reg_0_0_4: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_83: Ty1
+                                        connect _bundle_literal_expr_83.value, _match_arm_value_40.src[0]
+                                        connect rename_table_normal_0_src_0.addr, _bundle_literal_expr_83 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_84: Ty1
+                                        connect _bundle_literal_expr_84.value, _match_arm_value_40.src[0]
+                                        connect rename_table_special_0_src_0.addr, _bundle_literal_expr_84 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_0_src_0.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_0_src_0.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_85: Ty25
+                                                        wire _bundle_literal_expr_86: Ty23
+                                                        connect _bundle_literal_expr_86.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_85.unit_num, _bundle_literal_expr_86
+                                                        wire _bundle_literal_expr_87: Ty24
+                                                        connect _bundle_literal_expr_87.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_85.unit_out_reg, _bundle_literal_expr_87
+                                                        connect renamed_src_reg_0_0_4, _bundle_literal_expr_85 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_41):
+                                                        connect renamed_src_reg_0_0_4, _match_arm_value_41 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_42):
+                                                connect renamed_src_reg_0_0_4, _match_arm_value_42 @[reg_alloc.rs 185:33]
+                                        wire _bundle_literal_expr_88: Ty38
+                                        connect _bundle_literal_expr_88.prefix_pad, _match_arm_value_40.prefix_pad
+                                        connect _bundle_literal_expr_88.dest, _match_arm_value_4.unit_out_reg
                                         wire _array_literal_expr_32: UInt<6>[3]
                                         wire _array_literal_expr_33: UInt<6>[1]
-                                        wire _cast_bundle_to_bits_expr_35: Ty57
-                                        connect _cast_bundle_to_bits_expr_35.unit_num, rename_0_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_35.unit_out_reg, rename_0_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_35: Ty47
+                                        connect _cast_bundle_to_bits_expr_35.unit_num, renamed_src_reg_0_0_4.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_35.unit_out_reg, renamed_src_reg_0_0_4.unit_out_reg.value
                                         wire _cast_to_bits_expr_35: UInt<6>
                                         connect _cast_to_bits_expr_35, cat(_cast_bundle_to_bits_expr_35.unit_out_reg, _cast_bundle_to_bits_expr_35.unit_num)
                                         connect _array_literal_expr_33[0], _cast_to_bits_expr_35
                                         connect _array_literal_expr_32[0], _array_literal_expr_33[0]
                                         connect _array_literal_expr_32[1], pad(UInt<0>(0h0), 6)
-                                        wire _bundle_literal_expr_83: Ty60
-                                        connect _bundle_literal_expr_83.imm_low, _match_arm_value_24.imm_low
+                                        wire _bundle_literal_expr_89: Ty50
+                                        connect _bundle_literal_expr_89.imm_low, _match_arm_value_40.imm_low
                                         wire _array_literal_expr_34: UInt<8>[1]
-                                        connect _array_literal_expr_34[0], _match_arm_value_24.src[2]
-                                        connect _bundle_literal_expr_83.reversed_src, _array_literal_expr_34
-                                        connect _bundle_literal_expr_83.imm_sign, _match_arm_value_24.imm_sign
-                                        wire _cast_bundle_to_bits_expr_36: Ty61
-                                        connect _cast_bundle_to_bits_expr_36.imm_low, _bundle_literal_expr_83.imm_low
-                                        connect _cast_bundle_to_bits_expr_36.reversed_src, _bundle_literal_expr_83.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_36.imm_sign, asUInt(_bundle_literal_expr_83.imm_sign)
+                                        connect _array_literal_expr_34[0], _match_arm_value_40.src[2]
+                                        connect _bundle_literal_expr_89.reversed_src, _array_literal_expr_34
+                                        connect _bundle_literal_expr_89.imm_sign, _match_arm_value_40.imm_sign
+                                        wire _cast_bundle_to_bits_expr_36: Ty51
+                                        connect _cast_bundle_to_bits_expr_36.imm_low, _bundle_literal_expr_89.imm_low
+                                        connect _cast_bundle_to_bits_expr_36.reversed_src, _bundle_literal_expr_89.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_36.imm_sign, asUInt(_bundle_literal_expr_89.imm_sign)
                                         wire _cast_to_bits_expr_36: UInt<34>
                                         connect _cast_to_bits_expr_36, cat(_cast_bundle_to_bits_expr_36.imm_sign, cat(_cast_bundle_to_bits_expr_36.reversed_src, _cast_bundle_to_bits_expr_36.imm_low))
-                                        wire _cast_bits_to_bundle_expr_5: Ty60
-                                        wire _cast_bits_to_bundle_expr_flattened_5: Ty61
+                                        wire _cast_bits_to_bundle_expr_5: Ty50
+                                        wire _cast_bits_to_bundle_expr_flattened_5: Ty51
                                         connect _cast_bits_to_bundle_expr_flattened_5.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_36)), 24, 0)
                                         connect _cast_bits_to_bundle_expr_5.imm_low, _cast_bits_to_bundle_expr_flattened_5.imm_low
                                         connect _cast_bits_to_bundle_expr_flattened_5.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_36)), 32, 25)
@@ -1386,761 +1268,577 @@ circuit reg_alloc:
                                         connect _cast_bits_to_bundle_expr_flattened_5.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_36)), 33, 33)
                                         connect _cast_bits_to_bundle_expr_5.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_5.imm_sign)
                                         connect _array_literal_expr_32[2], tail(_cast_bits_to_bundle_expr_5.reversed_src[0], 2)
-                                        connect _bundle_literal_expr_82.src, _array_literal_expr_32
-                                        wire _bundle_literal_expr_84: Ty60
-                                        connect _bundle_literal_expr_84.imm_low, _match_arm_value_24.imm_low
+                                        connect _bundle_literal_expr_88.src, _array_literal_expr_32
+                                        wire _bundle_literal_expr_90: Ty50
+                                        connect _bundle_literal_expr_90.imm_low, _match_arm_value_40.imm_low
                                         wire _array_literal_expr_35: UInt<8>[1]
-                                        connect _array_literal_expr_35[0], _match_arm_value_24.src[2]
-                                        connect _bundle_literal_expr_84.reversed_src, _array_literal_expr_35
-                                        connect _bundle_literal_expr_84.imm_sign, _match_arm_value_24.imm_sign
-                                        wire _cast_bundle_to_bits_expr_37: Ty61
-                                        connect _cast_bundle_to_bits_expr_37.imm_low, _bundle_literal_expr_84.imm_low
-                                        connect _cast_bundle_to_bits_expr_37.reversed_src, _bundle_literal_expr_84.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_37.imm_sign, asUInt(_bundle_literal_expr_84.imm_sign)
+                                        connect _array_literal_expr_35[0], _match_arm_value_40.src[2]
+                                        connect _bundle_literal_expr_90.reversed_src, _array_literal_expr_35
+                                        connect _bundle_literal_expr_90.imm_sign, _match_arm_value_40.imm_sign
+                                        wire _cast_bundle_to_bits_expr_37: Ty51
+                                        connect _cast_bundle_to_bits_expr_37.imm_low, _bundle_literal_expr_90.imm_low
+                                        connect _cast_bundle_to_bits_expr_37.reversed_src, _bundle_literal_expr_90.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_37.imm_sign, asUInt(_bundle_literal_expr_90.imm_sign)
                                         wire _cast_to_bits_expr_37: UInt<34>
                                         connect _cast_to_bits_expr_37, cat(_cast_bundle_to_bits_expr_37.imm_sign, cat(_cast_bundle_to_bits_expr_37.reversed_src, _cast_bundle_to_bits_expr_37.imm_low))
-                                        connect _bundle_literal_expr_82.imm_low, bits(asSInt(_cast_to_bits_expr_37), 24, 0)
-                                        wire _bundle_literal_expr_85: Ty60
-                                        connect _bundle_literal_expr_85.imm_low, _match_arm_value_24.imm_low
+                                        connect _bundle_literal_expr_88.imm_low, bits(asSInt(_cast_to_bits_expr_37), 24, 0)
+                                        wire _bundle_literal_expr_91: Ty50
+                                        connect _bundle_literal_expr_91.imm_low, _match_arm_value_40.imm_low
                                         wire _array_literal_expr_36: UInt<8>[1]
-                                        connect _array_literal_expr_36[0], _match_arm_value_24.src[2]
-                                        connect _bundle_literal_expr_85.reversed_src, _array_literal_expr_36
-                                        connect _bundle_literal_expr_85.imm_sign, _match_arm_value_24.imm_sign
-                                        wire _cast_bundle_to_bits_expr_38: Ty61
-                                        connect _cast_bundle_to_bits_expr_38.imm_low, _bundle_literal_expr_85.imm_low
-                                        connect _cast_bundle_to_bits_expr_38.reversed_src, _bundle_literal_expr_85.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_38.imm_sign, asUInt(_bundle_literal_expr_85.imm_sign)
+                                        connect _array_literal_expr_36[0], _match_arm_value_40.src[2]
+                                        connect _bundle_literal_expr_91.reversed_src, _array_literal_expr_36
+                                        connect _bundle_literal_expr_91.imm_sign, _match_arm_value_40.imm_sign
+                                        wire _cast_bundle_to_bits_expr_38: Ty51
+                                        connect _cast_bundle_to_bits_expr_38.imm_low, _bundle_literal_expr_91.imm_low
+                                        connect _cast_bundle_to_bits_expr_38.reversed_src, _bundle_literal_expr_91.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_38.imm_sign, asUInt(_bundle_literal_expr_91.imm_sign)
                                         wire _cast_to_bits_expr_38: UInt<34>
                                         connect _cast_to_bits_expr_38, cat(_cast_bundle_to_bits_expr_38.imm_sign, cat(_cast_bundle_to_bits_expr_38.reversed_src, _cast_bundle_to_bits_expr_38.imm_low))
-                                        connect _bundle_literal_expr_82.imm_sign, shr(asSInt(_cast_to_bits_expr_38), 33)
-                                        wire _bundle_literal_expr_86: Ty2
-                                        invalidate _bundle_literal_expr_86
-                                        connect _bundle_literal_expr_82._phantom, _bundle_literal_expr_86
-                                        connect mapped_regs_3, {|Load: Ty47, Store: Ty47|}(Store, _bundle_literal_expr_82) @[instruction.rs 539:1]
-                                connect mapped_regs, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(LoadStore, mapped_regs_3) @[unit.rs 127:1]
-                        connect renamed_mops[0], {|HdlNone, HdlSome: Ty51|}(HdlSome, mapped_regs) @[reg_alloc.rs 198:17]
-                        wire flag_reg: Ty1 @[instruction.rs 806:32]
-                        wire _bundle_literal_expr_87: Ty1
-                        connect _bundle_literal_expr_87.value, tail(UInt<32>(0h0), 24)
-                        connect flag_reg, _bundle_literal_expr_87 @[instruction.rs 807:17]
-                        match dest_reg.flag_regs[0]: @[instruction.rs 809:17]
-                            HdlNone:
-                                skip
-                            HdlSome(_match_arm_value_25):
-                                wire _bundle_literal_expr_88: Ty1
-                                connect _bundle_literal_expr_88.value, tail(UInt<32>(0hFE), 24)
-                                connect flag_reg, _bundle_literal_expr_88 @[instruction.rs 811:21]
-                        wire flag_reg_1: Ty1 @[instruction.rs 806:32]
-                        wire _bundle_literal_expr_89: Ty1
-                        connect _bundle_literal_expr_89.value, tail(UInt<32>(0h0), 24)
-                        connect flag_reg_1, _bundle_literal_expr_89 @[instruction.rs 807:17]
-                        match dest_reg.flag_regs[1]: @[instruction.rs 809:17]
-                            HdlNone:
-                                skip
-                            HdlSome(_match_arm_value_26):
-                                wire _bundle_literal_expr_90: Ty1
-                                connect _bundle_literal_expr_90.value, tail(UInt<32>(0hFF), 24)
-                                connect flag_reg_1, _bundle_literal_expr_90 @[instruction.rs 811:21]
-                        when and(geq(dest_reg.normal_regs[0].value, UInt<32>(0h1)), lt(dest_reg.normal_regs[0].value, UInt<32>(0hFE))): @[reg_alloc.rs 229:25]
-                            connect rename_table_normal_0_dest0.data, _match_arm_value_4 @[reg_alloc.rs 230:29]
-                            ; connect different types:
-                            ; lhs: UInt<8>
-                            ; rhs: UInt<33>
-                            connect rename_table_normal_0_dest0.addr, sub(dest_reg.normal_regs[0].value, UInt<32>(0h1)) @[reg_alloc.rs 234:33]
-                            connect rename_table_normal_0_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 236:29]
-                        when and(geq(dest_reg.normal_regs[0].value, UInt<32>(0hFE)), lt(dest_reg.normal_regs[0].value, UInt<32>(0h100))): @[reg_alloc.rs 229:25]
-                            connect rename_table_special_0_dest0.data, _match_arm_value_4 @[reg_alloc.rs 230:29]
-                            ; connect different types:
-                            ; lhs: UInt<1>
-                            ; rhs: UInt<33>
-                            connect rename_table_special_0_dest0.addr, sub(dest_reg.normal_regs[0].value, UInt<32>(0hFE)) @[reg_alloc.rs 234:33]
-                            connect rename_table_special_0_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 236:29]
-                        when and(geq(dest_reg.normal_regs[1].value, UInt<32>(0h1)), lt(dest_reg.normal_regs[1].value, UInt<32>(0hFE))): @[reg_alloc.rs 229:25]
-                            connect rename_table_normal_0_dest1.data, _match_arm_value_4 @[reg_alloc.rs 230:29]
-                            ; connect different types:
-                            ; lhs: UInt<8>
-                            ; rhs: UInt<33>
-                            connect rename_table_normal_0_dest1.addr, sub(dest_reg.normal_regs[1].value, UInt<32>(0h1)) @[reg_alloc.rs 234:33]
-                            connect rename_table_normal_0_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 236:29]
-                        when and(geq(dest_reg.normal_regs[1].value, UInt<32>(0hFE)), lt(dest_reg.normal_regs[1].value, UInt<32>(0h100))): @[reg_alloc.rs 229:25]
-                            connect rename_table_special_0_dest1.data, _match_arm_value_4 @[reg_alloc.rs 230:29]
-                            ; connect different types:
-                            ; lhs: UInt<1>
-                            ; rhs: UInt<33>
-                            connect rename_table_special_0_dest1.addr, sub(dest_reg.normal_regs[1].value, UInt<32>(0hFE)) @[reg_alloc.rs 234:33]
-                            connect rename_table_special_0_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 236:29]
-                        when and(geq(flag_reg.value, UInt<32>(0hFE)), lt(flag_reg.value, UInt<32>(0h100))): @[reg_alloc.rs 229:25]
-                            connect rename_table_special_0_flag0_rFE.data, _match_arm_value_4 @[reg_alloc.rs 230:29]
-                            ; connect different types:
-                            ; lhs: UInt<1>
-                            ; rhs: UInt<32>
-                            connect rename_table_special_0_flag0_rFE.addr, UInt<32>(0h0) @[reg_alloc.rs 232:33]
-                            connect rename_table_special_0_flag0_rFE.en, UInt<1>(0h1) @[reg_alloc.rs 236:29]
-                        when and(geq(flag_reg_1.value, UInt<32>(0hFE)), lt(flag_reg_1.value, UInt<32>(0h100))): @[reg_alloc.rs 229:25]
-                            connect rename_table_special_0_flag1_rFF.data, _match_arm_value_4 @[reg_alloc.rs 230:29]
-                            ; connect different types:
-                            ; lhs: UInt<1>
-                            ; rhs: UInt<32>
-                            connect rename_table_special_0_flag1_rFF.addr, UInt<32>(0h1) @[reg_alloc.rs 232:33]
-                            connect rename_table_special_0_flag1_rFF.en, UInt<1>(0h1) @[reg_alloc.rs 236:29]
-        wire selected_unit_index_leaf_0_0: Ty41 @[reg_alloc.rs 250:25]
-        connect selected_unit_index_leaf_0_0, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 253:21]
-        wire unit_index_0_0: UInt<2> @[reg_alloc.rs 259:25]
+                                        connect _bundle_literal_expr_88.imm_sign, shr(asSInt(_cast_to_bits_expr_38), 33)
+                                        wire _bundle_literal_expr_92: Ty2
+                                        invalidate _bundle_literal_expr_92
+                                        connect _bundle_literal_expr_88._phantom, _bundle_literal_expr_92
+                                        connect mapped_regs_3, {|Load: Ty38, Store: Ty38|}(Store, _bundle_literal_expr_88) @[instruction.rs 539:1]
+                                connect mapped_regs, {|AluBranch: Ty37, L2RegisterFile: Ty40, LoadStore: Ty41|}(LoadStore, mapped_regs_3) @[unit.rs 127:1]
+                        connect renamed_mops[0], {|HdlNone, HdlSome: Ty42|}(HdlSome, mapped_regs) @[reg_alloc.rs 167:17]
+        wire selected_unit_index_leaf_0_0: Ty32 @[reg_alloc.rs 209:25]
+        connect selected_unit_index_leaf_0_0, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 212:21]
+        wire unit_index_0_0: UInt<2> @[reg_alloc.rs 218:25]
         ; connect different types:
         ; lhs: UInt<2>
         ; rhs: UInt<64>
-        connect unit_index_0_0, UInt<64>(0h0) @[reg_alloc.rs 262:21]
-        when available_units[0][0]: @[reg_alloc.rs 264:21]
-            connect selected_unit_index_leaf_0_0, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_0_0) @[reg_alloc.rs 265:25]
-        wire selected_unit_index_leaf_0_1: Ty41 @[reg_alloc.rs 250:25]
-        connect selected_unit_index_leaf_0_1, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 253:21]
-        wire unit_index_0_1: UInt<2> @[reg_alloc.rs 259:25]
+        connect unit_index_0_0, UInt<64>(0h0) @[reg_alloc.rs 221:21]
+        when available_units[0][0]: @[reg_alloc.rs 223:21]
+            connect selected_unit_index_leaf_0_0, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_0_0) @[reg_alloc.rs 224:25]
+        wire selected_unit_index_leaf_0_1: Ty32 @[reg_alloc.rs 209:25]
+        connect selected_unit_index_leaf_0_1, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 212:21]
+        wire unit_index_0_1: UInt<2> @[reg_alloc.rs 218:25]
         ; connect different types:
         ; lhs: UInt<2>
         ; rhs: UInt<64>
-        connect unit_index_0_1, UInt<64>(0h1) @[reg_alloc.rs 262:21]
-        when available_units[0][1]: @[reg_alloc.rs 264:21]
-            connect selected_unit_index_leaf_0_1, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_0_1) @[reg_alloc.rs 265:25]
-        wire selected_unit_index_node_0_0: Ty41 @[reg_alloc.rs 272:25]
-        connect selected_unit_index_node_0_0, selected_unit_index_leaf_0_0 @[reg_alloc.rs 276:21]
-        match selected_unit_index_leaf_0_0: @[reg_alloc.rs 278:21]
+        connect unit_index_0_1, UInt<64>(0h1) @[reg_alloc.rs 221:21]
+        when available_units[0][1]: @[reg_alloc.rs 223:21]
+            connect selected_unit_index_leaf_0_1, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_0_1) @[reg_alloc.rs 224:25]
+        wire selected_unit_index_node_0_0: Ty32 @[reg_alloc.rs 231:25]
+        connect selected_unit_index_node_0_0, selected_unit_index_leaf_0_0 @[reg_alloc.rs 235:21]
+        match selected_unit_index_leaf_0_0: @[reg_alloc.rs 237:21]
             HdlNone:
-                connect selected_unit_index_node_0_0, selected_unit_index_leaf_0_1 @[reg_alloc.rs 279:25]
-            HdlSome(_match_arm_value_27):
+                connect selected_unit_index_node_0_0, selected_unit_index_leaf_0_1 @[reg_alloc.rs 238:25]
+            HdlSome(_match_arm_value_43):
                 skip
-        connect selected_unit_indexes[0], selected_unit_index_node_0_0 @[reg_alloc.rs 242:9]
-        connect fetch_decode_interface.decoded_insns[1].ready, UInt<1>(0h1) @[reg_alloc.rs 92:9]
+        connect selected_unit_indexes[0], selected_unit_index_node_0_0 @[reg_alloc.rs 201:9]
+        connect fetch_decode_interface.decoded_insns[1].ready, UInt<1>(0h1) @[reg_alloc.rs 79:9]
         wire _array_literal_expr_37: UInt<1>[2]
         connect _array_literal_expr_37[0], UInt<1>(0h0)
         connect _array_literal_expr_37[1], UInt<1>(0h0)
-        connect available_units[1], _array_literal_expr_37 @[reg_alloc.rs 96:9]
-        connect renamed_mops[1], {|HdlNone, HdlSome: Ty51|}(HdlNone) @[reg_alloc.rs 100:9]
-        wire rename_1_src_0: Ty54 @[reg_alloc.rs 113:17]
-        wire _bundle_literal_expr_91: Ty1
-        connect _bundle_literal_expr_91.value, tail(UInt<32>(0h0), 24)
-        connect rename_1_src_0.addr, _bundle_literal_expr_91 @[reg_alloc.rs 116:13]
-        wire _bundle_literal_expr_92: Ty25
-        wire _bundle_literal_expr_93: Ty23
-        connect _bundle_literal_expr_93.adj_value, tail(UInt<64>(0h0), 62)
-        connect _bundle_literal_expr_92.unit_num, _bundle_literal_expr_93
-        wire _bundle_literal_expr_94: Ty24
-        connect _bundle_literal_expr_94.value, tail(UInt<8>(0h0), 4)
-        connect _bundle_literal_expr_92.unit_out_reg, _bundle_literal_expr_94
-        connect rename_1_src_0.data, _bundle_literal_expr_92 @[reg_alloc.rs 117:13]
-        connect rename_table_normal_mem_r5.clk, cd.clk @[reg_alloc.rs 121:17]
-        connect rename_table_normal_mem_r5.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17]
-        connect rename_table_normal_mem_r5.en, UInt<1>(0h0) @[reg_alloc.rs 123:17]
-        when and(geq(rename_1_src_0.addr.value, UInt<32>(0h1)), lt(rename_1_src_0.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 126:17]
+        connect available_units[1], _array_literal_expr_37 @[reg_alloc.rs 83:9]
+        connect renamed_mops[1], {|HdlNone, HdlSome: Ty42|}(HdlNone) @[reg_alloc.rs 87:9]
+        connect rename_table_normal_mem_r3.clk, cd.clk @[reg_alloc.rs 103:17]
+        connect rename_table_normal_mem_r3.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17]
+        connect rename_table_normal_mem_r3.en, UInt<1>(0h0) @[reg_alloc.rs 105:17]
+        wire rename_table_normal_1_src_0: Ty45 @[reg_alloc.rs 108:21]
+        wire _bundle_literal_expr_93: Ty1
+        connect _bundle_literal_expr_93.value, tail(UInt<32>(0h0), 24)
+        connect rename_table_normal_1_src_0.addr, _bundle_literal_expr_93 @[reg_alloc.rs 111:17]
+        connect rename_table_normal_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17]
+        when and(geq(rename_table_normal_1_src_0.addr.value, UInt<32>(0h1)), lt(rename_table_normal_1_src_0.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 114:17]
             ; connect different types:
             ; lhs: UInt<8>
             ; rhs: UInt<33>
-            connect rename_table_normal_mem_r5.addr, sub(rename_1_src_0.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 127:21]
-            connect rename_table_normal_mem_r5.en, UInt<1>(0h1) @[reg_alloc.rs 128:21]
-            connect rename_1_src_0.data, rename_table_normal_mem_r5.data @[reg_alloc.rs 129:21]
-            match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 132:25]
+            connect rename_table_normal_mem_r3.addr, sub(rename_table_normal_1_src_0.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 115:21]
+            connect rename_table_normal_mem_r3.en, UInt<1>(0h1) @[reg_alloc.rs 116:21]
+            connect rename_table_normal_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_normal_mem_r3.data) @[reg_alloc.rs 117:21]
+            match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 120:25]
                 HdlNone:
                     skip
-                HdlSome(_match_arm_value_28):
-                    match renamed_mops_out_reg[0]: @[reg_alloc.rs 136:29]
+                HdlSome(_match_arm_value_44):
+                    match renamed_mops_out_reg[0]: @[reg_alloc.rs 124:29]
                         HdlNone:
                             skip
-                        HdlSome(_match_arm_value_29):
+                        HdlSome(_match_arm_value_45):
                             wire dest_reg_4: Ty4 @[unit.rs 127:1]
-                            match _match_arm_value_28.mop: @[unit.rs 127:1]
-                                AluBranch(_match_arm_value_30):
+                            match _match_arm_value_44.mop: @[unit.rs 127:1]
+                                AluBranch(_match_arm_value_46):
                                     wire dest_reg_5: Ty4 @[instruction.rs 477:1]
-                                    match _match_arm_value_30: @[instruction.rs 477:1]
-                                        AddSub(_match_arm_value_31):
-                                            connect dest_reg_5, _match_arm_value_31.alu_common.common.dest @[instruction.rs 477:1]
-                                        AddSubI(_match_arm_value_32):
-                                            connect dest_reg_5, _match_arm_value_32.alu_common.common.dest @[instruction.rs 477:1]
-                                        Logical(_match_arm_value_33):
-                                            connect dest_reg_5, _match_arm_value_33.alu_common.common.dest @[instruction.rs 477:1]
+                                    match _match_arm_value_46: @[instruction.rs 477:1]
+                                        AddSub(_match_arm_value_47):
+                                            connect dest_reg_5, _match_arm_value_47.alu_common.common.dest @[instruction.rs 477:1]
+                                        AddSubI(_match_arm_value_48):
+                                            connect dest_reg_5, _match_arm_value_48.alu_common.common.dest @[instruction.rs 477:1]
+                                        Logical(_match_arm_value_49):
+                                            connect dest_reg_5, _match_arm_value_49.alu_common.common.dest @[instruction.rs 477:1]
                                     connect dest_reg_4, dest_reg_5 @[unit.rs 127:1]
-                                L2RegisterFile(_match_arm_value_34):
+                                L2RegisterFile(_match_arm_value_50):
                                     wire dest_reg_6: Ty4 @[instruction.rs 504:1]
-                                    match _match_arm_value_34: @[instruction.rs 504:1]
-                                        ReadL2Reg(_match_arm_value_35):
-                                            connect dest_reg_6, _match_arm_value_35.common.dest @[instruction.rs 504:1]
-                                        WriteL2Reg(_match_arm_value_36):
-                                            connect dest_reg_6, _match_arm_value_36.common.dest @[instruction.rs 504:1]
+                                    match _match_arm_value_50: @[instruction.rs 504:1]
+                                        ReadL2Reg(_match_arm_value_51):
+                                            connect dest_reg_6, _match_arm_value_51.common.dest @[instruction.rs 504:1]
+                                        WriteL2Reg(_match_arm_value_52):
+                                            connect dest_reg_6, _match_arm_value_52.common.dest @[instruction.rs 504:1]
                                     connect dest_reg_4, dest_reg_6 @[unit.rs 127:1]
-                                LoadStore(_match_arm_value_37):
+                                LoadStore(_match_arm_value_53):
                                     wire dest_reg_7: Ty4 @[instruction.rs 539:1]
-                                    match _match_arm_value_37: @[instruction.rs 539:1]
-                                        Load(_match_arm_value_38):
-                                            connect dest_reg_7, _match_arm_value_38.dest @[instruction.rs 539:1]
-                                        Store(_match_arm_value_39):
-                                            connect dest_reg_7, _match_arm_value_39.dest @[instruction.rs 539:1]
+                                    match _match_arm_value_53: @[instruction.rs 539:1]
+                                        Load(_match_arm_value_54):
+                                            connect dest_reg_7, _match_arm_value_54.dest @[instruction.rs 539:1]
+                                        Store(_match_arm_value_55):
+                                            connect dest_reg_7, _match_arm_value_55.dest @[instruction.rs 539:1]
                                     connect dest_reg_4, dest_reg_7 @[unit.rs 127:1]
-                            wire flag_reg_2: Ty1 @[instruction.rs 806:32]
-                            wire _bundle_literal_expr_95: Ty1
-                            connect _bundle_literal_expr_95.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_2, _bundle_literal_expr_95 @[instruction.rs 807:17]
-                            match dest_reg_4.flag_regs[0]: @[instruction.rs 809:17]
+                            wire flag_reg: Ty1 @[instruction.rs 720:32]
+                            wire _bundle_literal_expr_94: Ty1
+                            connect _bundle_literal_expr_94.value, tail(UInt<32>(0h0), 24)
+                            connect flag_reg, _bundle_literal_expr_94 @[instruction.rs 721:17]
+                            match dest_reg_4.flag_regs[0]: @[instruction.rs 723:17]
                                 HdlNone:
                                     skip
-                                HdlSome(_match_arm_value_40):
-                                    wire _bundle_literal_expr_96: Ty1
-                                    connect _bundle_literal_expr_96.value, tail(UInt<32>(0hFE), 24)
-                                    connect flag_reg_2, _bundle_literal_expr_96 @[instruction.rs 811:21]
-                            wire flag_reg_3: Ty1 @[instruction.rs 806:32]
-                            wire _bundle_literal_expr_97: Ty1
-                            connect _bundle_literal_expr_97.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_3, _bundle_literal_expr_97 @[instruction.rs 807:17]
-                            match dest_reg_4.flag_regs[1]: @[instruction.rs 809:17]
+                                HdlSome(_match_arm_value_56):
+                                    wire _bundle_literal_expr_95: Ty1
+                                    connect _bundle_literal_expr_95.value, tail(UInt<32>(0hFE), 24)
+                                    connect flag_reg, _bundle_literal_expr_95 @[instruction.rs 725:21]
+                            wire flag_reg_1: Ty1 @[instruction.rs 720:32]
+                            wire _bundle_literal_expr_96: Ty1
+                            connect _bundle_literal_expr_96.value, tail(UInt<32>(0h0), 24)
+                            connect flag_reg_1, _bundle_literal_expr_96 @[instruction.rs 721:17]
+                            match dest_reg_4.flag_regs[1]: @[instruction.rs 723:17]
                                 HdlNone:
                                     skip
-                                HdlSome(_match_arm_value_41):
-                                    wire _bundle_literal_expr_98: Ty1
-                                    connect _bundle_literal_expr_98.value, tail(UInt<32>(0hFF), 24)
-                                    connect flag_reg_3, _bundle_literal_expr_98 @[instruction.rs 811:21]
-                            when eq(dest_reg_4.normal_regs[0].value, rename_1_src_0.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_0.data, _match_arm_value_29 @[reg_alloc.rs 147:45]
-                            when eq(dest_reg_4.normal_regs[1].value, rename_1_src_0.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_0.data, _match_arm_value_29 @[reg_alloc.rs 147:45]
-        connect rename_table_special_mem_r7.clk, cd.clk @[reg_alloc.rs 121:17]
-        ; connect different types:
-        ; lhs: UInt<1>
-        ; rhs: UInt<8>
-        connect rename_table_special_mem_r7.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17]
-        connect rename_table_special_mem_r7.en, UInt<1>(0h0) @[reg_alloc.rs 123:17]
-        when and(geq(rename_1_src_0.addr.value, UInt<32>(0hFE)), lt(rename_1_src_0.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 126:17]
+                                HdlSome(_match_arm_value_57):
+                                    wire _bundle_literal_expr_97: Ty1
+                                    connect _bundle_literal_expr_97.value, tail(UInt<32>(0hFF), 24)
+                                    connect flag_reg_1, _bundle_literal_expr_97 @[instruction.rs 725:21]
+                            when eq(dest_reg_4.normal_regs[0].value, rename_table_normal_1_src_0.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_normal_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_45) @[reg_alloc.rs 131:41]
+                            when eq(dest_reg_4.normal_regs[1].value, rename_table_normal_1_src_0.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_normal_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_45) @[reg_alloc.rs 131:41]
+                            when eq(flag_reg.value, rename_table_normal_1_src_0.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_normal_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_45) @[reg_alloc.rs 131:41]
+                            when eq(flag_reg_1.value, rename_table_normal_1_src_0.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_normal_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_45) @[reg_alloc.rs 131:41]
+        connect rename_table_normal_mem_r4.clk, cd.clk @[reg_alloc.rs 103:17]
+        connect rename_table_normal_mem_r4.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17]
+        connect rename_table_normal_mem_r4.en, UInt<1>(0h0) @[reg_alloc.rs 105:17]
+        wire rename_table_normal_1_src_1: Ty45 @[reg_alloc.rs 108:21]
+        wire _bundle_literal_expr_98: Ty1
+        connect _bundle_literal_expr_98.value, tail(UInt<32>(0h0), 24)
+        connect rename_table_normal_1_src_1.addr, _bundle_literal_expr_98 @[reg_alloc.rs 111:17]
+        connect rename_table_normal_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17]
+        when and(geq(rename_table_normal_1_src_1.addr.value, UInt<32>(0h1)), lt(rename_table_normal_1_src_1.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 114:17]
             ; connect different types:
-            ; lhs: UInt<1>
+            ; lhs: UInt<8>
             ; rhs: UInt<33>
-            connect rename_table_special_mem_r7.addr, sub(rename_1_src_0.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 127:21]
-            connect rename_table_special_mem_r7.en, UInt<1>(0h1) @[reg_alloc.rs 128:21]
-            connect rename_1_src_0.data, rename_table_special_mem_r7.data @[reg_alloc.rs 129:21]
-            match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 132:25]
+            connect rename_table_normal_mem_r4.addr, sub(rename_table_normal_1_src_1.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 115:21]
+            connect rename_table_normal_mem_r4.en, UInt<1>(0h1) @[reg_alloc.rs 116:21]
+            connect rename_table_normal_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_normal_mem_r4.data) @[reg_alloc.rs 117:21]
+            match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 120:25]
                 HdlNone:
                     skip
-                HdlSome(_match_arm_value_42):
-                    match renamed_mops_out_reg[0]: @[reg_alloc.rs 136:29]
+                HdlSome(_match_arm_value_58):
+                    match renamed_mops_out_reg[0]: @[reg_alloc.rs 124:29]
                         HdlNone:
                             skip
-                        HdlSome(_match_arm_value_43):
+                        HdlSome(_match_arm_value_59):
                             wire dest_reg_8: Ty4 @[unit.rs 127:1]
-                            match _match_arm_value_42.mop: @[unit.rs 127:1]
-                                AluBranch(_match_arm_value_44):
+                            match _match_arm_value_58.mop: @[unit.rs 127:1]
+                                AluBranch(_match_arm_value_60):
                                     wire dest_reg_9: Ty4 @[instruction.rs 477:1]
-                                    match _match_arm_value_44: @[instruction.rs 477:1]
-                                        AddSub(_match_arm_value_45):
-                                            connect dest_reg_9, _match_arm_value_45.alu_common.common.dest @[instruction.rs 477:1]
-                                        AddSubI(_match_arm_value_46):
-                                            connect dest_reg_9, _match_arm_value_46.alu_common.common.dest @[instruction.rs 477:1]
-                                        Logical(_match_arm_value_47):
-                                            connect dest_reg_9, _match_arm_value_47.alu_common.common.dest @[instruction.rs 477:1]
+                                    match _match_arm_value_60: @[instruction.rs 477:1]
+                                        AddSub(_match_arm_value_61):
+                                            connect dest_reg_9, _match_arm_value_61.alu_common.common.dest @[instruction.rs 477:1]
+                                        AddSubI(_match_arm_value_62):
+                                            connect dest_reg_9, _match_arm_value_62.alu_common.common.dest @[instruction.rs 477:1]
+                                        Logical(_match_arm_value_63):
+                                            connect dest_reg_9, _match_arm_value_63.alu_common.common.dest @[instruction.rs 477:1]
                                     connect dest_reg_8, dest_reg_9 @[unit.rs 127:1]
-                                L2RegisterFile(_match_arm_value_48):
+                                L2RegisterFile(_match_arm_value_64):
                                     wire dest_reg_10: Ty4 @[instruction.rs 504:1]
-                                    match _match_arm_value_48: @[instruction.rs 504:1]
-                                        ReadL2Reg(_match_arm_value_49):
-                                            connect dest_reg_10, _match_arm_value_49.common.dest @[instruction.rs 504:1]
-                                        WriteL2Reg(_match_arm_value_50):
-                                            connect dest_reg_10, _match_arm_value_50.common.dest @[instruction.rs 504:1]
+                                    match _match_arm_value_64: @[instruction.rs 504:1]
+                                        ReadL2Reg(_match_arm_value_65):
+                                            connect dest_reg_10, _match_arm_value_65.common.dest @[instruction.rs 504:1]
+                                        WriteL2Reg(_match_arm_value_66):
+                                            connect dest_reg_10, _match_arm_value_66.common.dest @[instruction.rs 504:1]
                                     connect dest_reg_8, dest_reg_10 @[unit.rs 127:1]
-                                LoadStore(_match_arm_value_51):
+                                LoadStore(_match_arm_value_67):
                                     wire dest_reg_11: Ty4 @[instruction.rs 539:1]
-                                    match _match_arm_value_51: @[instruction.rs 539:1]
-                                        Load(_match_arm_value_52):
-                                            connect dest_reg_11, _match_arm_value_52.dest @[instruction.rs 539:1]
-                                        Store(_match_arm_value_53):
-                                            connect dest_reg_11, _match_arm_value_53.dest @[instruction.rs 539:1]
+                                    match _match_arm_value_67: @[instruction.rs 539:1]
+                                        Load(_match_arm_value_68):
+                                            connect dest_reg_11, _match_arm_value_68.dest @[instruction.rs 539:1]
+                                        Store(_match_arm_value_69):
+                                            connect dest_reg_11, _match_arm_value_69.dest @[instruction.rs 539:1]
                                     connect dest_reg_8, dest_reg_11 @[unit.rs 127:1]
-                            wire flag_reg_4: Ty1 @[instruction.rs 806:32]
+                            wire flag_reg_2: Ty1 @[instruction.rs 720:32]
                             wire _bundle_literal_expr_99: Ty1
                             connect _bundle_literal_expr_99.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_4, _bundle_literal_expr_99 @[instruction.rs 807:17]
-                            match dest_reg_8.flag_regs[0]: @[instruction.rs 809:17]
+                            connect flag_reg_2, _bundle_literal_expr_99 @[instruction.rs 721:17]
+                            match dest_reg_8.flag_regs[0]: @[instruction.rs 723:17]
                                 HdlNone:
                                     skip
-                                HdlSome(_match_arm_value_54):
+                                HdlSome(_match_arm_value_70):
                                     wire _bundle_literal_expr_100: Ty1
                                     connect _bundle_literal_expr_100.value, tail(UInt<32>(0hFE), 24)
-                                    connect flag_reg_4, _bundle_literal_expr_100 @[instruction.rs 811:21]
-                            wire flag_reg_5: Ty1 @[instruction.rs 806:32]
+                                    connect flag_reg_2, _bundle_literal_expr_100 @[instruction.rs 725:21]
+                            wire flag_reg_3: Ty1 @[instruction.rs 720:32]
                             wire _bundle_literal_expr_101: Ty1
                             connect _bundle_literal_expr_101.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_5, _bundle_literal_expr_101 @[instruction.rs 807:17]
-                            match dest_reg_8.flag_regs[1]: @[instruction.rs 809:17]
+                            connect flag_reg_3, _bundle_literal_expr_101 @[instruction.rs 721:17]
+                            match dest_reg_8.flag_regs[1]: @[instruction.rs 723:17]
                                 HdlNone:
                                     skip
-                                HdlSome(_match_arm_value_55):
+                                HdlSome(_match_arm_value_71):
                                     wire _bundle_literal_expr_102: Ty1
                                     connect _bundle_literal_expr_102.value, tail(UInt<32>(0hFF), 24)
-                                    connect flag_reg_5, _bundle_literal_expr_102 @[instruction.rs 811:21]
-                            when eq(dest_reg_8.normal_regs[0].value, rename_1_src_0.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 147:45]
-                            when eq(dest_reg_8.normal_regs[1].value, rename_1_src_0.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 147:45]
-                            when eq(flag_reg_4.value, rename_1_src_0.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 147:45]
-                            when eq(flag_reg_5.value, rename_1_src_0.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_0.data, _match_arm_value_43 @[reg_alloc.rs 147:45]
-        wire rename_1_src_1: Ty54 @[reg_alloc.rs 113:17]
+                                    connect flag_reg_3, _bundle_literal_expr_102 @[instruction.rs 725:21]
+                            when eq(dest_reg_8.normal_regs[0].value, rename_table_normal_1_src_1.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_normal_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_59) @[reg_alloc.rs 131:41]
+                            when eq(dest_reg_8.normal_regs[1].value, rename_table_normal_1_src_1.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_normal_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_59) @[reg_alloc.rs 131:41]
+                            when eq(flag_reg_2.value, rename_table_normal_1_src_1.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_normal_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_59) @[reg_alloc.rs 131:41]
+                            when eq(flag_reg_3.value, rename_table_normal_1_src_1.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_normal_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_59) @[reg_alloc.rs 131:41]
+        connect rename_table_normal_mem_r5.clk, cd.clk @[reg_alloc.rs 103:17]
+        connect rename_table_normal_mem_r5.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17]
+        connect rename_table_normal_mem_r5.en, UInt<1>(0h0) @[reg_alloc.rs 105:17]
+        wire rename_table_normal_1_src_2: Ty45 @[reg_alloc.rs 108:21]
         wire _bundle_literal_expr_103: Ty1
         connect _bundle_literal_expr_103.value, tail(UInt<32>(0h0), 24)
-        connect rename_1_src_1.addr, _bundle_literal_expr_103 @[reg_alloc.rs 116:13]
-        wire _bundle_literal_expr_104: Ty25
-        wire _bundle_literal_expr_105: Ty23
-        connect _bundle_literal_expr_105.adj_value, tail(UInt<64>(0h0), 62)
-        connect _bundle_literal_expr_104.unit_num, _bundle_literal_expr_105
-        wire _bundle_literal_expr_106: Ty24
-        connect _bundle_literal_expr_106.value, tail(UInt<8>(0h0), 4)
-        connect _bundle_literal_expr_104.unit_out_reg, _bundle_literal_expr_106
-        connect rename_1_src_1.data, _bundle_literal_expr_104 @[reg_alloc.rs 117:13]
-        connect rename_table_normal_mem_r6.clk, cd.clk @[reg_alloc.rs 121:17]
-        connect rename_table_normal_mem_r6.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17]
-        connect rename_table_normal_mem_r6.en, UInt<1>(0h0) @[reg_alloc.rs 123:17]
-        when and(geq(rename_1_src_1.addr.value, UInt<32>(0h1)), lt(rename_1_src_1.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 126:17]
+        connect rename_table_normal_1_src_2.addr, _bundle_literal_expr_103 @[reg_alloc.rs 111:17]
+        connect rename_table_normal_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17]
+        when and(geq(rename_table_normal_1_src_2.addr.value, UInt<32>(0h1)), lt(rename_table_normal_1_src_2.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 114:17]
             ; connect different types:
             ; lhs: UInt<8>
             ; rhs: UInt<33>
-            connect rename_table_normal_mem_r6.addr, sub(rename_1_src_1.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 127:21]
-            connect rename_table_normal_mem_r6.en, UInt<1>(0h1) @[reg_alloc.rs 128:21]
-            connect rename_1_src_1.data, rename_table_normal_mem_r6.data @[reg_alloc.rs 129:21]
-            match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 132:25]
+            connect rename_table_normal_mem_r5.addr, sub(rename_table_normal_1_src_2.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 115:21]
+            connect rename_table_normal_mem_r5.en, UInt<1>(0h1) @[reg_alloc.rs 116:21]
+            connect rename_table_normal_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_normal_mem_r5.data) @[reg_alloc.rs 117:21]
+            match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 120:25]
                 HdlNone:
                     skip
-                HdlSome(_match_arm_value_56):
-                    match renamed_mops_out_reg[0]: @[reg_alloc.rs 136:29]
+                HdlSome(_match_arm_value_72):
+                    match renamed_mops_out_reg[0]: @[reg_alloc.rs 124:29]
                         HdlNone:
                             skip
-                        HdlSome(_match_arm_value_57):
+                        HdlSome(_match_arm_value_73):
                             wire dest_reg_12: Ty4 @[unit.rs 127:1]
-                            match _match_arm_value_56.mop: @[unit.rs 127:1]
-                                AluBranch(_match_arm_value_58):
+                            match _match_arm_value_72.mop: @[unit.rs 127:1]
+                                AluBranch(_match_arm_value_74):
                                     wire dest_reg_13: Ty4 @[instruction.rs 477:1]
-                                    match _match_arm_value_58: @[instruction.rs 477:1]
-                                        AddSub(_match_arm_value_59):
-                                            connect dest_reg_13, _match_arm_value_59.alu_common.common.dest @[instruction.rs 477:1]
-                                        AddSubI(_match_arm_value_60):
-                                            connect dest_reg_13, _match_arm_value_60.alu_common.common.dest @[instruction.rs 477:1]
-                                        Logical(_match_arm_value_61):
-                                            connect dest_reg_13, _match_arm_value_61.alu_common.common.dest @[instruction.rs 477:1]
+                                    match _match_arm_value_74: @[instruction.rs 477:1]
+                                        AddSub(_match_arm_value_75):
+                                            connect dest_reg_13, _match_arm_value_75.alu_common.common.dest @[instruction.rs 477:1]
+                                        AddSubI(_match_arm_value_76):
+                                            connect dest_reg_13, _match_arm_value_76.alu_common.common.dest @[instruction.rs 477:1]
+                                        Logical(_match_arm_value_77):
+                                            connect dest_reg_13, _match_arm_value_77.alu_common.common.dest @[instruction.rs 477:1]
                                     connect dest_reg_12, dest_reg_13 @[unit.rs 127:1]
-                                L2RegisterFile(_match_arm_value_62):
+                                L2RegisterFile(_match_arm_value_78):
                                     wire dest_reg_14: Ty4 @[instruction.rs 504:1]
-                                    match _match_arm_value_62: @[instruction.rs 504:1]
-                                        ReadL2Reg(_match_arm_value_63):
-                                            connect dest_reg_14, _match_arm_value_63.common.dest @[instruction.rs 504:1]
-                                        WriteL2Reg(_match_arm_value_64):
-                                            connect dest_reg_14, _match_arm_value_64.common.dest @[instruction.rs 504:1]
+                                    match _match_arm_value_78: @[instruction.rs 504:1]
+                                        ReadL2Reg(_match_arm_value_79):
+                                            connect dest_reg_14, _match_arm_value_79.common.dest @[instruction.rs 504:1]
+                                        WriteL2Reg(_match_arm_value_80):
+                                            connect dest_reg_14, _match_arm_value_80.common.dest @[instruction.rs 504:1]
                                     connect dest_reg_12, dest_reg_14 @[unit.rs 127:1]
-                                LoadStore(_match_arm_value_65):
+                                LoadStore(_match_arm_value_81):
                                     wire dest_reg_15: Ty4 @[instruction.rs 539:1]
-                                    match _match_arm_value_65: @[instruction.rs 539:1]
-                                        Load(_match_arm_value_66):
-                                            connect dest_reg_15, _match_arm_value_66.dest @[instruction.rs 539:1]
-                                        Store(_match_arm_value_67):
-                                            connect dest_reg_15, _match_arm_value_67.dest @[instruction.rs 539:1]
+                                    match _match_arm_value_81: @[instruction.rs 539:1]
+                                        Load(_match_arm_value_82):
+                                            connect dest_reg_15, _match_arm_value_82.dest @[instruction.rs 539:1]
+                                        Store(_match_arm_value_83):
+                                            connect dest_reg_15, _match_arm_value_83.dest @[instruction.rs 539:1]
                                     connect dest_reg_12, dest_reg_15 @[unit.rs 127:1]
-                            wire flag_reg_6: Ty1 @[instruction.rs 806:32]
-                            wire _bundle_literal_expr_107: Ty1
-                            connect _bundle_literal_expr_107.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_6, _bundle_literal_expr_107 @[instruction.rs 807:17]
-                            match dest_reg_12.flag_regs[0]: @[instruction.rs 809:17]
+                            wire flag_reg_4: Ty1 @[instruction.rs 720:32]
+                            wire _bundle_literal_expr_104: Ty1
+                            connect _bundle_literal_expr_104.value, tail(UInt<32>(0h0), 24)
+                            connect flag_reg_4, _bundle_literal_expr_104 @[instruction.rs 721:17]
+                            match dest_reg_12.flag_regs[0]: @[instruction.rs 723:17]
                                 HdlNone:
                                     skip
-                                HdlSome(_match_arm_value_68):
-                                    wire _bundle_literal_expr_108: Ty1
-                                    connect _bundle_literal_expr_108.value, tail(UInt<32>(0hFE), 24)
-                                    connect flag_reg_6, _bundle_literal_expr_108 @[instruction.rs 811:21]
-                            wire flag_reg_7: Ty1 @[instruction.rs 806:32]
+                                HdlSome(_match_arm_value_84):
+                                    wire _bundle_literal_expr_105: Ty1
+                                    connect _bundle_literal_expr_105.value, tail(UInt<32>(0hFE), 24)
+                                    connect flag_reg_4, _bundle_literal_expr_105 @[instruction.rs 725:21]
+                            wire flag_reg_5: Ty1 @[instruction.rs 720:32]
+                            wire _bundle_literal_expr_106: Ty1
+                            connect _bundle_literal_expr_106.value, tail(UInt<32>(0h0), 24)
+                            connect flag_reg_5, _bundle_literal_expr_106 @[instruction.rs 721:17]
+                            match dest_reg_12.flag_regs[1]: @[instruction.rs 723:17]
+                                HdlNone:
+                                    skip
+                                HdlSome(_match_arm_value_85):
+                                    wire _bundle_literal_expr_107: Ty1
+                                    connect _bundle_literal_expr_107.value, tail(UInt<32>(0hFF), 24)
+                                    connect flag_reg_5, _bundle_literal_expr_107 @[instruction.rs 725:21]
+                            when eq(dest_reg_12.normal_regs[0].value, rename_table_normal_1_src_2.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_normal_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_73) @[reg_alloc.rs 131:41]
+                            when eq(dest_reg_12.normal_regs[1].value, rename_table_normal_1_src_2.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_normal_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_73) @[reg_alloc.rs 131:41]
+                            when eq(flag_reg_4.value, rename_table_normal_1_src_2.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_normal_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_73) @[reg_alloc.rs 131:41]
+                            when eq(flag_reg_5.value, rename_table_normal_1_src_2.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_normal_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_73) @[reg_alloc.rs 131:41]
+        connect rename_table_special_mem_r3.clk, cd.clk @[reg_alloc.rs 103:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<8>
+        connect rename_table_special_mem_r3.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17]
+        connect rename_table_special_mem_r3.en, UInt<1>(0h0) @[reg_alloc.rs 105:17]
+        wire rename_table_special_1_src_0: Ty45 @[reg_alloc.rs 108:21]
+        wire _bundle_literal_expr_108: Ty1
+        connect _bundle_literal_expr_108.value, tail(UInt<32>(0h0), 24)
+        connect rename_table_special_1_src_0.addr, _bundle_literal_expr_108 @[reg_alloc.rs 111:17]
+        connect rename_table_special_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17]
+        when and(geq(rename_table_special_1_src_0.addr.value, UInt<32>(0hFE)), lt(rename_table_special_1_src_0.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 114:17]
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<33>
+            connect rename_table_special_mem_r3.addr, sub(rename_table_special_1_src_0.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 115:21]
+            connect rename_table_special_mem_r3.en, UInt<1>(0h1) @[reg_alloc.rs 116:21]
+            connect rename_table_special_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_special_mem_r3.data) @[reg_alloc.rs 117:21]
+            match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 120:25]
+                HdlNone:
+                    skip
+                HdlSome(_match_arm_value_86):
+                    match renamed_mops_out_reg[0]: @[reg_alloc.rs 124:29]
+                        HdlNone:
+                            skip
+                        HdlSome(_match_arm_value_87):
+                            wire dest_reg_16: Ty4 @[unit.rs 127:1]
+                            match _match_arm_value_86.mop: @[unit.rs 127:1]
+                                AluBranch(_match_arm_value_88):
+                                    wire dest_reg_17: Ty4 @[instruction.rs 477:1]
+                                    match _match_arm_value_88: @[instruction.rs 477:1]
+                                        AddSub(_match_arm_value_89):
+                                            connect dest_reg_17, _match_arm_value_89.alu_common.common.dest @[instruction.rs 477:1]
+                                        AddSubI(_match_arm_value_90):
+                                            connect dest_reg_17, _match_arm_value_90.alu_common.common.dest @[instruction.rs 477:1]
+                                        Logical(_match_arm_value_91):
+                                            connect dest_reg_17, _match_arm_value_91.alu_common.common.dest @[instruction.rs 477:1]
+                                    connect dest_reg_16, dest_reg_17 @[unit.rs 127:1]
+                                L2RegisterFile(_match_arm_value_92):
+                                    wire dest_reg_18: Ty4 @[instruction.rs 504:1]
+                                    match _match_arm_value_92: @[instruction.rs 504:1]
+                                        ReadL2Reg(_match_arm_value_93):
+                                            connect dest_reg_18, _match_arm_value_93.common.dest @[instruction.rs 504:1]
+                                        WriteL2Reg(_match_arm_value_94):
+                                            connect dest_reg_18, _match_arm_value_94.common.dest @[instruction.rs 504:1]
+                                    connect dest_reg_16, dest_reg_18 @[unit.rs 127:1]
+                                LoadStore(_match_arm_value_95):
+                                    wire dest_reg_19: Ty4 @[instruction.rs 539:1]
+                                    match _match_arm_value_95: @[instruction.rs 539:1]
+                                        Load(_match_arm_value_96):
+                                            connect dest_reg_19, _match_arm_value_96.dest @[instruction.rs 539:1]
+                                        Store(_match_arm_value_97):
+                                            connect dest_reg_19, _match_arm_value_97.dest @[instruction.rs 539:1]
+                                    connect dest_reg_16, dest_reg_19 @[unit.rs 127:1]
+                            wire flag_reg_6: Ty1 @[instruction.rs 720:32]
                             wire _bundle_literal_expr_109: Ty1
                             connect _bundle_literal_expr_109.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_7, _bundle_literal_expr_109 @[instruction.rs 807:17]
-                            match dest_reg_12.flag_regs[1]: @[instruction.rs 809:17]
+                            connect flag_reg_6, _bundle_literal_expr_109 @[instruction.rs 721:17]
+                            match dest_reg_16.flag_regs[0]: @[instruction.rs 723:17]
                                 HdlNone:
                                     skip
-                                HdlSome(_match_arm_value_69):
+                                HdlSome(_match_arm_value_98):
                                     wire _bundle_literal_expr_110: Ty1
-                                    connect _bundle_literal_expr_110.value, tail(UInt<32>(0hFF), 24)
-                                    connect flag_reg_7, _bundle_literal_expr_110 @[instruction.rs 811:21]
-                            when eq(dest_reg_12.normal_regs[0].value, rename_1_src_1.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_1.data, _match_arm_value_57 @[reg_alloc.rs 147:45]
-                            when eq(dest_reg_12.normal_regs[1].value, rename_1_src_1.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_1.data, _match_arm_value_57 @[reg_alloc.rs 147:45]
-        connect rename_table_special_mem_r8.clk, cd.clk @[reg_alloc.rs 121:17]
-        ; connect different types:
-        ; lhs: UInt<1>
-        ; rhs: UInt<8>
-        connect rename_table_special_mem_r8.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17]
-        connect rename_table_special_mem_r8.en, UInt<1>(0h0) @[reg_alloc.rs 123:17]
-        when and(geq(rename_1_src_1.addr.value, UInt<32>(0hFE)), lt(rename_1_src_1.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 126:17]
-            ; connect different types:
-            ; lhs: UInt<1>
-            ; rhs: UInt<33>
-            connect rename_table_special_mem_r8.addr, sub(rename_1_src_1.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 127:21]
-            connect rename_table_special_mem_r8.en, UInt<1>(0h1) @[reg_alloc.rs 128:21]
-            connect rename_1_src_1.data, rename_table_special_mem_r8.data @[reg_alloc.rs 129:21]
-            match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 132:25]
-                HdlNone:
-                    skip
-                HdlSome(_match_arm_value_70):
-                    match renamed_mops_out_reg[0]: @[reg_alloc.rs 136:29]
-                        HdlNone:
-                            skip
-                        HdlSome(_match_arm_value_71):
-                            wire dest_reg_16: Ty4 @[unit.rs 127:1]
-                            match _match_arm_value_70.mop: @[unit.rs 127:1]
-                                AluBranch(_match_arm_value_72):
-                                    wire dest_reg_17: Ty4 @[instruction.rs 477:1]
-                                    match _match_arm_value_72: @[instruction.rs 477:1]
-                                        AddSub(_match_arm_value_73):
-                                            connect dest_reg_17, _match_arm_value_73.alu_common.common.dest @[instruction.rs 477:1]
-                                        AddSubI(_match_arm_value_74):
-                                            connect dest_reg_17, _match_arm_value_74.alu_common.common.dest @[instruction.rs 477:1]
-                                        Logical(_match_arm_value_75):
-                                            connect dest_reg_17, _match_arm_value_75.alu_common.common.dest @[instruction.rs 477:1]
-                                    connect dest_reg_16, dest_reg_17 @[unit.rs 127:1]
-                                L2RegisterFile(_match_arm_value_76):
-                                    wire dest_reg_18: Ty4 @[instruction.rs 504:1]
-                                    match _match_arm_value_76: @[instruction.rs 504:1]
-                                        ReadL2Reg(_match_arm_value_77):
-                                            connect dest_reg_18, _match_arm_value_77.common.dest @[instruction.rs 504:1]
-                                        WriteL2Reg(_match_arm_value_78):
-                                            connect dest_reg_18, _match_arm_value_78.common.dest @[instruction.rs 504:1]
-                                    connect dest_reg_16, dest_reg_18 @[unit.rs 127:1]
-                                LoadStore(_match_arm_value_79):
-                                    wire dest_reg_19: Ty4 @[instruction.rs 539:1]
-                                    match _match_arm_value_79: @[instruction.rs 539:1]
-                                        Load(_match_arm_value_80):
-                                            connect dest_reg_19, _match_arm_value_80.dest @[instruction.rs 539:1]
-                                        Store(_match_arm_value_81):
-                                            connect dest_reg_19, _match_arm_value_81.dest @[instruction.rs 539:1]
-                                    connect dest_reg_16, dest_reg_19 @[unit.rs 127:1]
-                            wire flag_reg_8: Ty1 @[instruction.rs 806:32]
+                                    connect _bundle_literal_expr_110.value, tail(UInt<32>(0hFE), 24)
+                                    connect flag_reg_6, _bundle_literal_expr_110 @[instruction.rs 725:21]
+                            wire flag_reg_7: Ty1 @[instruction.rs 720:32]
                             wire _bundle_literal_expr_111: Ty1
                             connect _bundle_literal_expr_111.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_8, _bundle_literal_expr_111 @[instruction.rs 807:17]
-                            match dest_reg_16.flag_regs[0]: @[instruction.rs 809:17]
+                            connect flag_reg_7, _bundle_literal_expr_111 @[instruction.rs 721:17]
+                            match dest_reg_16.flag_regs[1]: @[instruction.rs 723:17]
                                 HdlNone:
                                     skip
-                                HdlSome(_match_arm_value_82):
+                                HdlSome(_match_arm_value_99):
                                     wire _bundle_literal_expr_112: Ty1
-                                    connect _bundle_literal_expr_112.value, tail(UInt<32>(0hFE), 24)
-                                    connect flag_reg_8, _bundle_literal_expr_112 @[instruction.rs 811:21]
-                            wire flag_reg_9: Ty1 @[instruction.rs 806:32]
-                            wire _bundle_literal_expr_113: Ty1
-                            connect _bundle_literal_expr_113.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_9, _bundle_literal_expr_113 @[instruction.rs 807:17]
-                            match dest_reg_16.flag_regs[1]: @[instruction.rs 809:17]
-                                HdlNone:
-                                    skip
-                                HdlSome(_match_arm_value_83):
-                                    wire _bundle_literal_expr_114: Ty1
-                                    connect _bundle_literal_expr_114.value, tail(UInt<32>(0hFF), 24)
-                                    connect flag_reg_9, _bundle_literal_expr_114 @[instruction.rs 811:21]
-                            when eq(dest_reg_16.normal_regs[0].value, rename_1_src_1.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 147:45]
-                            when eq(dest_reg_16.normal_regs[1].value, rename_1_src_1.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 147:45]
-                            when eq(flag_reg_8.value, rename_1_src_1.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 147:45]
-                            when eq(flag_reg_9.value, rename_1_src_1.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_1.data, _match_arm_value_71 @[reg_alloc.rs 147:45]
-        wire rename_1_src_2: Ty54 @[reg_alloc.rs 113:17]
-        wire _bundle_literal_expr_115: Ty1
-        connect _bundle_literal_expr_115.value, tail(UInt<32>(0h0), 24)
-        connect rename_1_src_2.addr, _bundle_literal_expr_115 @[reg_alloc.rs 116:13]
-        wire _bundle_literal_expr_116: Ty25
-        wire _bundle_literal_expr_117: Ty23
-        connect _bundle_literal_expr_117.adj_value, tail(UInt<64>(0h0), 62)
-        connect _bundle_literal_expr_116.unit_num, _bundle_literal_expr_117
-        wire _bundle_literal_expr_118: Ty24
-        connect _bundle_literal_expr_118.value, tail(UInt<8>(0h0), 4)
-        connect _bundle_literal_expr_116.unit_out_reg, _bundle_literal_expr_118
-        connect rename_1_src_2.data, _bundle_literal_expr_116 @[reg_alloc.rs 117:13]
-        connect rename_table_normal_mem_r7.clk, cd.clk @[reg_alloc.rs 121:17]
-        connect rename_table_normal_mem_r7.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17]
-        connect rename_table_normal_mem_r7.en, UInt<1>(0h0) @[reg_alloc.rs 123:17]
-        when and(geq(rename_1_src_2.addr.value, UInt<32>(0h1)), lt(rename_1_src_2.addr.value, UInt<32>(0hFE))): @[reg_alloc.rs 126:17]
-            ; connect different types:
-            ; lhs: UInt<8>
-            ; rhs: UInt<33>
-            connect rename_table_normal_mem_r7.addr, sub(rename_1_src_2.addr.value, UInt<32>(0h1)) @[reg_alloc.rs 127:21]
-            connect rename_table_normal_mem_r7.en, UInt<1>(0h1) @[reg_alloc.rs 128:21]
-            connect rename_1_src_2.data, rename_table_normal_mem_r7.data @[reg_alloc.rs 129:21]
-            match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 132:25]
-                HdlNone:
-                    skip
-                HdlSome(_match_arm_value_84):
-                    match renamed_mops_out_reg[0]: @[reg_alloc.rs 136:29]
-                        HdlNone:
-                            skip
-                        HdlSome(_match_arm_value_85):
-                            wire dest_reg_20: Ty4 @[unit.rs 127:1]
-                            match _match_arm_value_84.mop: @[unit.rs 127:1]
-                                AluBranch(_match_arm_value_86):
-                                    wire dest_reg_21: Ty4 @[instruction.rs 477:1]
-                                    match _match_arm_value_86: @[instruction.rs 477:1]
-                                        AddSub(_match_arm_value_87):
-                                            connect dest_reg_21, _match_arm_value_87.alu_common.common.dest @[instruction.rs 477:1]
-                                        AddSubI(_match_arm_value_88):
-                                            connect dest_reg_21, _match_arm_value_88.alu_common.common.dest @[instruction.rs 477:1]
-                                        Logical(_match_arm_value_89):
-                                            connect dest_reg_21, _match_arm_value_89.alu_common.common.dest @[instruction.rs 477:1]
-                                    connect dest_reg_20, dest_reg_21 @[unit.rs 127:1]
-                                L2RegisterFile(_match_arm_value_90):
-                                    wire dest_reg_22: Ty4 @[instruction.rs 504:1]
-                                    match _match_arm_value_90: @[instruction.rs 504:1]
-                                        ReadL2Reg(_match_arm_value_91):
-                                            connect dest_reg_22, _match_arm_value_91.common.dest @[instruction.rs 504:1]
-                                        WriteL2Reg(_match_arm_value_92):
-                                            connect dest_reg_22, _match_arm_value_92.common.dest @[instruction.rs 504:1]
-                                    connect dest_reg_20, dest_reg_22 @[unit.rs 127:1]
-                                LoadStore(_match_arm_value_93):
-                                    wire dest_reg_23: Ty4 @[instruction.rs 539:1]
-                                    match _match_arm_value_93: @[instruction.rs 539:1]
-                                        Load(_match_arm_value_94):
-                                            connect dest_reg_23, _match_arm_value_94.dest @[instruction.rs 539:1]
-                                        Store(_match_arm_value_95):
-                                            connect dest_reg_23, _match_arm_value_95.dest @[instruction.rs 539:1]
-                                    connect dest_reg_20, dest_reg_23 @[unit.rs 127:1]
-                            wire flag_reg_10: Ty1 @[instruction.rs 806:32]
-                            wire _bundle_literal_expr_119: Ty1
-                            connect _bundle_literal_expr_119.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_10, _bundle_literal_expr_119 @[instruction.rs 807:17]
-                            match dest_reg_20.flag_regs[0]: @[instruction.rs 809:17]
-                                HdlNone:
-                                    skip
-                                HdlSome(_match_arm_value_96):
-                                    wire _bundle_literal_expr_120: Ty1
-                                    connect _bundle_literal_expr_120.value, tail(UInt<32>(0hFE), 24)
-                                    connect flag_reg_10, _bundle_literal_expr_120 @[instruction.rs 811:21]
-                            wire flag_reg_11: Ty1 @[instruction.rs 806:32]
-                            wire _bundle_literal_expr_121: Ty1
-                            connect _bundle_literal_expr_121.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_11, _bundle_literal_expr_121 @[instruction.rs 807:17]
-                            match dest_reg_20.flag_regs[1]: @[instruction.rs 809:17]
-                                HdlNone:
-                                    skip
-                                HdlSome(_match_arm_value_97):
-                                    wire _bundle_literal_expr_122: Ty1
-                                    connect _bundle_literal_expr_122.value, tail(UInt<32>(0hFF), 24)
-                                    connect flag_reg_11, _bundle_literal_expr_122 @[instruction.rs 811:21]
-                            when eq(dest_reg_20.normal_regs[0].value, rename_1_src_2.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_2.data, _match_arm_value_85 @[reg_alloc.rs 147:45]
-                            when eq(dest_reg_20.normal_regs[1].value, rename_1_src_2.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_2.data, _match_arm_value_85 @[reg_alloc.rs 147:45]
-        connect rename_table_special_mem_r9.clk, cd.clk @[reg_alloc.rs 121:17]
+                                    connect _bundle_literal_expr_112.value, tail(UInt<32>(0hFF), 24)
+                                    connect flag_reg_7, _bundle_literal_expr_112 @[instruction.rs 725:21]
+                            when eq(dest_reg_16.normal_regs[0].value, rename_table_special_1_src_0.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_special_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_87) @[reg_alloc.rs 131:41]
+                            when eq(dest_reg_16.normal_regs[1].value, rename_table_special_1_src_0.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_special_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_87) @[reg_alloc.rs 131:41]
+                            when eq(flag_reg_6.value, rename_table_special_1_src_0.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_special_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_87) @[reg_alloc.rs 131:41]
+                            when eq(flag_reg_7.value, rename_table_special_1_src_0.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_special_1_src_0.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_87) @[reg_alloc.rs 131:41]
+        connect rename_table_special_mem_r4.clk, cd.clk @[reg_alloc.rs 103:17]
         ; connect different types:
         ; lhs: UInt<1>
         ; rhs: UInt<8>
-        connect rename_table_special_mem_r9.addr, UInt<8>(0h0) @[reg_alloc.rs 122:17]
-        connect rename_table_special_mem_r9.en, UInt<1>(0h0) @[reg_alloc.rs 123:17]
-        when and(geq(rename_1_src_2.addr.value, UInt<32>(0hFE)), lt(rename_1_src_2.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 126:17]
+        connect rename_table_special_mem_r4.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17]
+        connect rename_table_special_mem_r4.en, UInt<1>(0h0) @[reg_alloc.rs 105:17]
+        wire rename_table_special_1_src_1: Ty45 @[reg_alloc.rs 108:21]
+        wire _bundle_literal_expr_113: Ty1
+        connect _bundle_literal_expr_113.value, tail(UInt<32>(0h0), 24)
+        connect rename_table_special_1_src_1.addr, _bundle_literal_expr_113 @[reg_alloc.rs 111:17]
+        connect rename_table_special_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17]
+        when and(geq(rename_table_special_1_src_1.addr.value, UInt<32>(0hFE)), lt(rename_table_special_1_src_1.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 114:17]
             ; connect different types:
             ; lhs: UInt<1>
             ; rhs: UInt<33>
-            connect rename_table_special_mem_r9.addr, sub(rename_1_src_2.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 127:21]
-            connect rename_table_special_mem_r9.en, UInt<1>(0h1) @[reg_alloc.rs 128:21]
-            connect rename_1_src_2.data, rename_table_special_mem_r9.data @[reg_alloc.rs 129:21]
-            match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 132:25]
+            connect rename_table_special_mem_r4.addr, sub(rename_table_special_1_src_1.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 115:21]
+            connect rename_table_special_mem_r4.en, UInt<1>(0h1) @[reg_alloc.rs 116:21]
+            connect rename_table_special_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_special_mem_r4.data) @[reg_alloc.rs 117:21]
+            match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 120:25]
                 HdlNone:
                     skip
-                HdlSome(_match_arm_value_98):
-                    match renamed_mops_out_reg[0]: @[reg_alloc.rs 136:29]
+                HdlSome(_match_arm_value_100):
+                    match renamed_mops_out_reg[0]: @[reg_alloc.rs 124:29]
                         HdlNone:
                             skip
-                        HdlSome(_match_arm_value_99):
+                        HdlSome(_match_arm_value_101):
+                            wire dest_reg_20: Ty4 @[unit.rs 127:1]
+                            match _match_arm_value_100.mop: @[unit.rs 127:1]
+                                AluBranch(_match_arm_value_102):
+                                    wire dest_reg_21: Ty4 @[instruction.rs 477:1]
+                                    match _match_arm_value_102: @[instruction.rs 477:1]
+                                        AddSub(_match_arm_value_103):
+                                            connect dest_reg_21, _match_arm_value_103.alu_common.common.dest @[instruction.rs 477:1]
+                                        AddSubI(_match_arm_value_104):
+                                            connect dest_reg_21, _match_arm_value_104.alu_common.common.dest @[instruction.rs 477:1]
+                                        Logical(_match_arm_value_105):
+                                            connect dest_reg_21, _match_arm_value_105.alu_common.common.dest @[instruction.rs 477:1]
+                                    connect dest_reg_20, dest_reg_21 @[unit.rs 127:1]
+                                L2RegisterFile(_match_arm_value_106):
+                                    wire dest_reg_22: Ty4 @[instruction.rs 504:1]
+                                    match _match_arm_value_106: @[instruction.rs 504:1]
+                                        ReadL2Reg(_match_arm_value_107):
+                                            connect dest_reg_22, _match_arm_value_107.common.dest @[instruction.rs 504:1]
+                                        WriteL2Reg(_match_arm_value_108):
+                                            connect dest_reg_22, _match_arm_value_108.common.dest @[instruction.rs 504:1]
+                                    connect dest_reg_20, dest_reg_22 @[unit.rs 127:1]
+                                LoadStore(_match_arm_value_109):
+                                    wire dest_reg_23: Ty4 @[instruction.rs 539:1]
+                                    match _match_arm_value_109: @[instruction.rs 539:1]
+                                        Load(_match_arm_value_110):
+                                            connect dest_reg_23, _match_arm_value_110.dest @[instruction.rs 539:1]
+                                        Store(_match_arm_value_111):
+                                            connect dest_reg_23, _match_arm_value_111.dest @[instruction.rs 539:1]
+                                    connect dest_reg_20, dest_reg_23 @[unit.rs 127:1]
+                            wire flag_reg_8: Ty1 @[instruction.rs 720:32]
+                            wire _bundle_literal_expr_114: Ty1
+                            connect _bundle_literal_expr_114.value, tail(UInt<32>(0h0), 24)
+                            connect flag_reg_8, _bundle_literal_expr_114 @[instruction.rs 721:17]
+                            match dest_reg_20.flag_regs[0]: @[instruction.rs 723:17]
+                                HdlNone:
+                                    skip
+                                HdlSome(_match_arm_value_112):
+                                    wire _bundle_literal_expr_115: Ty1
+                                    connect _bundle_literal_expr_115.value, tail(UInt<32>(0hFE), 24)
+                                    connect flag_reg_8, _bundle_literal_expr_115 @[instruction.rs 725:21]
+                            wire flag_reg_9: Ty1 @[instruction.rs 720:32]
+                            wire _bundle_literal_expr_116: Ty1
+                            connect _bundle_literal_expr_116.value, tail(UInt<32>(0h0), 24)
+                            connect flag_reg_9, _bundle_literal_expr_116 @[instruction.rs 721:17]
+                            match dest_reg_20.flag_regs[1]: @[instruction.rs 723:17]
+                                HdlNone:
+                                    skip
+                                HdlSome(_match_arm_value_113):
+                                    wire _bundle_literal_expr_117: Ty1
+                                    connect _bundle_literal_expr_117.value, tail(UInt<32>(0hFF), 24)
+                                    connect flag_reg_9, _bundle_literal_expr_117 @[instruction.rs 725:21]
+                            when eq(dest_reg_20.normal_regs[0].value, rename_table_special_1_src_1.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_special_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_101) @[reg_alloc.rs 131:41]
+                            when eq(dest_reg_20.normal_regs[1].value, rename_table_special_1_src_1.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_special_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_101) @[reg_alloc.rs 131:41]
+                            when eq(flag_reg_8.value, rename_table_special_1_src_1.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_special_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_101) @[reg_alloc.rs 131:41]
+                            when eq(flag_reg_9.value, rename_table_special_1_src_1.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_special_1_src_1.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_101) @[reg_alloc.rs 131:41]
+        connect rename_table_special_mem_r5.clk, cd.clk @[reg_alloc.rs 103:17]
+        ; connect different types:
+        ; lhs: UInt<1>
+        ; rhs: UInt<8>
+        connect rename_table_special_mem_r5.addr, UInt<8>(0h0) @[reg_alloc.rs 104:17]
+        connect rename_table_special_mem_r5.en, UInt<1>(0h0) @[reg_alloc.rs 105:17]
+        wire rename_table_special_1_src_2: Ty45 @[reg_alloc.rs 108:21]
+        wire _bundle_literal_expr_118: Ty1
+        connect _bundle_literal_expr_118.value, tail(UInt<32>(0h0), 24)
+        connect rename_table_special_1_src_2.addr, _bundle_literal_expr_118 @[reg_alloc.rs 111:17]
+        connect rename_table_special_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlNone) @[reg_alloc.rs 112:17]
+        when and(geq(rename_table_special_1_src_2.addr.value, UInt<32>(0hFE)), lt(rename_table_special_1_src_2.addr.value, UInt<32>(0h100))): @[reg_alloc.rs 114:17]
+            ; connect different types:
+            ; lhs: UInt<1>
+            ; rhs: UInt<33>
+            connect rename_table_special_mem_r5.addr, sub(rename_table_special_1_src_2.addr.value, UInt<32>(0hFE)) @[reg_alloc.rs 115:21]
+            connect rename_table_special_mem_r5.en, UInt<1>(0h1) @[reg_alloc.rs 116:21]
+            connect rename_table_special_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, rename_table_special_mem_r5.data) @[reg_alloc.rs 117:21]
+            match fetch_decode_interface.decoded_insns[0].data: @[reg_alloc.rs 120:25]
+                HdlNone:
+                    skip
+                HdlSome(_match_arm_value_114):
+                    match renamed_mops_out_reg[0]: @[reg_alloc.rs 124:29]
+                        HdlNone:
+                            skip
+                        HdlSome(_match_arm_value_115):
                             wire dest_reg_24: Ty4 @[unit.rs 127:1]
-                            match _match_arm_value_98.mop: @[unit.rs 127:1]
-                                AluBranch(_match_arm_value_100):
+                            match _match_arm_value_114.mop: @[unit.rs 127:1]
+                                AluBranch(_match_arm_value_116):
                                     wire dest_reg_25: Ty4 @[instruction.rs 477:1]
-                                    match _match_arm_value_100: @[instruction.rs 477:1]
-                                        AddSub(_match_arm_value_101):
-                                            connect dest_reg_25, _match_arm_value_101.alu_common.common.dest @[instruction.rs 477:1]
-                                        AddSubI(_match_arm_value_102):
-                                            connect dest_reg_25, _match_arm_value_102.alu_common.common.dest @[instruction.rs 477:1]
-                                        Logical(_match_arm_value_103):
-                                            connect dest_reg_25, _match_arm_value_103.alu_common.common.dest @[instruction.rs 477:1]
+                                    match _match_arm_value_116: @[instruction.rs 477:1]
+                                        AddSub(_match_arm_value_117):
+                                            connect dest_reg_25, _match_arm_value_117.alu_common.common.dest @[instruction.rs 477:1]
+                                        AddSubI(_match_arm_value_118):
+                                            connect dest_reg_25, _match_arm_value_118.alu_common.common.dest @[instruction.rs 477:1]
+                                        Logical(_match_arm_value_119):
+                                            connect dest_reg_25, _match_arm_value_119.alu_common.common.dest @[instruction.rs 477:1]
                                     connect dest_reg_24, dest_reg_25 @[unit.rs 127:1]
-                                L2RegisterFile(_match_arm_value_104):
+                                L2RegisterFile(_match_arm_value_120):
                                     wire dest_reg_26: Ty4 @[instruction.rs 504:1]
-                                    match _match_arm_value_104: @[instruction.rs 504:1]
-                                        ReadL2Reg(_match_arm_value_105):
-                                            connect dest_reg_26, _match_arm_value_105.common.dest @[instruction.rs 504:1]
-                                        WriteL2Reg(_match_arm_value_106):
-                                            connect dest_reg_26, _match_arm_value_106.common.dest @[instruction.rs 504:1]
+                                    match _match_arm_value_120: @[instruction.rs 504:1]
+                                        ReadL2Reg(_match_arm_value_121):
+                                            connect dest_reg_26, _match_arm_value_121.common.dest @[instruction.rs 504:1]
+                                        WriteL2Reg(_match_arm_value_122):
+                                            connect dest_reg_26, _match_arm_value_122.common.dest @[instruction.rs 504:1]
                                     connect dest_reg_24, dest_reg_26 @[unit.rs 127:1]
-                                LoadStore(_match_arm_value_107):
+                                LoadStore(_match_arm_value_123):
                                     wire dest_reg_27: Ty4 @[instruction.rs 539:1]
-                                    match _match_arm_value_107: @[instruction.rs 539:1]
-                                        Load(_match_arm_value_108):
-                                            connect dest_reg_27, _match_arm_value_108.dest @[instruction.rs 539:1]
-                                        Store(_match_arm_value_109):
-                                            connect dest_reg_27, _match_arm_value_109.dest @[instruction.rs 539:1]
+                                    match _match_arm_value_123: @[instruction.rs 539:1]
+                                        Load(_match_arm_value_124):
+                                            connect dest_reg_27, _match_arm_value_124.dest @[instruction.rs 539:1]
+                                        Store(_match_arm_value_125):
+                                            connect dest_reg_27, _match_arm_value_125.dest @[instruction.rs 539:1]
                                     connect dest_reg_24, dest_reg_27 @[unit.rs 127:1]
-                            wire flag_reg_12: Ty1 @[instruction.rs 806:32]
-                            wire _bundle_literal_expr_123: Ty1
-                            connect _bundle_literal_expr_123.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_12, _bundle_literal_expr_123 @[instruction.rs 807:17]
-                            match dest_reg_24.flag_regs[0]: @[instruction.rs 809:17]
+                            wire flag_reg_10: Ty1 @[instruction.rs 720:32]
+                            wire _bundle_literal_expr_119: Ty1
+                            connect _bundle_literal_expr_119.value, tail(UInt<32>(0h0), 24)
+                            connect flag_reg_10, _bundle_literal_expr_119 @[instruction.rs 721:17]
+                            match dest_reg_24.flag_regs[0]: @[instruction.rs 723:17]
                                 HdlNone:
                                     skip
-                                HdlSome(_match_arm_value_110):
-                                    wire _bundle_literal_expr_124: Ty1
-                                    connect _bundle_literal_expr_124.value, tail(UInt<32>(0hFE), 24)
-                                    connect flag_reg_12, _bundle_literal_expr_124 @[instruction.rs 811:21]
-                            wire flag_reg_13: Ty1 @[instruction.rs 806:32]
-                            wire _bundle_literal_expr_125: Ty1
-                            connect _bundle_literal_expr_125.value, tail(UInt<32>(0h0), 24)
-                            connect flag_reg_13, _bundle_literal_expr_125 @[instruction.rs 807:17]
-                            match dest_reg_24.flag_regs[1]: @[instruction.rs 809:17]
+                                HdlSome(_match_arm_value_126):
+                                    wire _bundle_literal_expr_120: Ty1
+                                    connect _bundle_literal_expr_120.value, tail(UInt<32>(0hFE), 24)
+                                    connect flag_reg_10, _bundle_literal_expr_120 @[instruction.rs 725:21]
+                            wire flag_reg_11: Ty1 @[instruction.rs 720:32]
+                            wire _bundle_literal_expr_121: Ty1
+                            connect _bundle_literal_expr_121.value, tail(UInt<32>(0h0), 24)
+                            connect flag_reg_11, _bundle_literal_expr_121 @[instruction.rs 721:17]
+                            match dest_reg_24.flag_regs[1]: @[instruction.rs 723:17]
                                 HdlNone:
                                     skip
-                                HdlSome(_match_arm_value_111):
-                                    wire _bundle_literal_expr_126: Ty1
-                                    connect _bundle_literal_expr_126.value, tail(UInt<32>(0hFF), 24)
-                                    connect flag_reg_13, _bundle_literal_expr_126 @[instruction.rs 811:21]
-                            when eq(dest_reg_24.normal_regs[0].value, rename_1_src_2.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 147:45]
-                            when eq(dest_reg_24.normal_regs[1].value, rename_1_src_2.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 147:45]
-                            when eq(flag_reg_12.value, rename_1_src_2.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 147:45]
-                            when eq(flag_reg_13.value, rename_1_src_2.addr.value): @[reg_alloc.rs 146:41]
-                                connect rename_1_src_2.data, _match_arm_value_99 @[reg_alloc.rs 147:45]
-        wire rename_table_normal_1_dest0: Ty30 @[reg_alloc.rs 171:21]
-        connect rename_table_normal_mem_w8, rename_table_normal_1_dest0 @[reg_alloc.rs 174:17]
-        wire _bundle_literal_expr_127: Ty55
-        connect _bundle_literal_expr_127.addr, UInt<0>(0h0)
-        connect _bundle_literal_expr_127.en, UInt<1>(0h0)
-        connect _bundle_literal_expr_127.clk, cd.clk
-        wire _uninit_expr_6: Ty25
-        invalidate _uninit_expr_6
-        connect _bundle_literal_expr_127.data, _uninit_expr_6
-        wire _bundle_literal_expr_128: Ty29
-        wire _bundle_literal_expr_129: Ty27
-        connect _bundle_literal_expr_129.adj_value, UInt<1>(0h1)
-        connect _bundle_literal_expr_128.unit_num, _bundle_literal_expr_129
-        wire _bundle_literal_expr_130: Ty28
-        connect _bundle_literal_expr_130.value, UInt<1>(0h1)
-        connect _bundle_literal_expr_128.unit_out_reg, _bundle_literal_expr_130
-        connect _bundle_literal_expr_127.mask, _bundle_literal_expr_128
-        ; connect different types:
-        ; lhs: Bundle {addr: UInt<8>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        connect rename_table_normal_1_dest0, _bundle_literal_expr_127 @[reg_alloc.rs 176:17]
-        wire rename_table_special_1_dest0: Ty36 @[reg_alloc.rs 171:21]
-        connect rename_table_special_mem_w10, rename_table_special_1_dest0 @[reg_alloc.rs 174:17]
-        wire _bundle_literal_expr_131: Ty55
-        connect _bundle_literal_expr_131.addr, UInt<0>(0h0)
-        connect _bundle_literal_expr_131.en, UInt<1>(0h0)
-        connect _bundle_literal_expr_131.clk, cd.clk
-        wire _uninit_expr_7: Ty25
-        invalidate _uninit_expr_7
-        connect _bundle_literal_expr_131.data, _uninit_expr_7
-        wire _bundle_literal_expr_132: Ty29
-        wire _bundle_literal_expr_133: Ty27
-        connect _bundle_literal_expr_133.adj_value, UInt<1>(0h1)
-        connect _bundle_literal_expr_132.unit_num, _bundle_literal_expr_133
-        wire _bundle_literal_expr_134: Ty28
-        connect _bundle_literal_expr_134.value, UInt<1>(0h1)
-        connect _bundle_literal_expr_132.unit_out_reg, _bundle_literal_expr_134
-        connect _bundle_literal_expr_131.mask, _bundle_literal_expr_132
-        ; connect different types:
-        ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        connect rename_table_special_1_dest0, _bundle_literal_expr_131 @[reg_alloc.rs 176:17]
-        wire rename_table_normal_1_dest1: Ty30 @[reg_alloc.rs 171:21]
-        connect rename_table_normal_mem_w9, rename_table_normal_1_dest1 @[reg_alloc.rs 174:17]
-        wire _bundle_literal_expr_135: Ty55
-        connect _bundle_literal_expr_135.addr, UInt<0>(0h0)
-        connect _bundle_literal_expr_135.en, UInt<1>(0h0)
-        connect _bundle_literal_expr_135.clk, cd.clk
-        wire _uninit_expr_8: Ty25
-        invalidate _uninit_expr_8
-        connect _bundle_literal_expr_135.data, _uninit_expr_8
-        wire _bundle_literal_expr_136: Ty29
-        wire _bundle_literal_expr_137: Ty27
-        connect _bundle_literal_expr_137.adj_value, UInt<1>(0h1)
-        connect _bundle_literal_expr_136.unit_num, _bundle_literal_expr_137
-        wire _bundle_literal_expr_138: Ty28
-        connect _bundle_literal_expr_138.value, UInt<1>(0h1)
-        connect _bundle_literal_expr_136.unit_out_reg, _bundle_literal_expr_138
-        connect _bundle_literal_expr_135.mask, _bundle_literal_expr_136
-        ; connect different types:
-        ; lhs: Bundle {addr: UInt<8>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        connect rename_table_normal_1_dest1, _bundle_literal_expr_135 @[reg_alloc.rs 176:17]
-        wire rename_table_special_1_dest1: Ty36 @[reg_alloc.rs 171:21]
-        connect rename_table_special_mem_w11, rename_table_special_1_dest1 @[reg_alloc.rs 174:17]
-        wire _bundle_literal_expr_139: Ty55
-        connect _bundle_literal_expr_139.addr, UInt<0>(0h0)
-        connect _bundle_literal_expr_139.en, UInt<1>(0h0)
-        connect _bundle_literal_expr_139.clk, cd.clk
-        wire _uninit_expr_9: Ty25
-        invalidate _uninit_expr_9
-        connect _bundle_literal_expr_139.data, _uninit_expr_9
-        wire _bundle_literal_expr_140: Ty29
-        wire _bundle_literal_expr_141: Ty27
-        connect _bundle_literal_expr_141.adj_value, UInt<1>(0h1)
-        connect _bundle_literal_expr_140.unit_num, _bundle_literal_expr_141
-        wire _bundle_literal_expr_142: Ty28
-        connect _bundle_literal_expr_142.value, UInt<1>(0h1)
-        connect _bundle_literal_expr_140.unit_out_reg, _bundle_literal_expr_142
-        connect _bundle_literal_expr_139.mask, _bundle_literal_expr_140
-        ; connect different types:
-        ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        connect rename_table_special_1_dest1, _bundle_literal_expr_139 @[reg_alloc.rs 176:17]
-        wire rename_table_special_1_flag0_rFE: Ty36 @[reg_alloc.rs 171:21]
-        connect rename_table_special_mem_w12, rename_table_special_1_flag0_rFE @[reg_alloc.rs 174:17]
-        wire _bundle_literal_expr_143: Ty55
-        connect _bundle_literal_expr_143.addr, UInt<0>(0h0)
-        connect _bundle_literal_expr_143.en, UInt<1>(0h0)
-        connect _bundle_literal_expr_143.clk, cd.clk
-        wire _uninit_expr_10: Ty25
-        invalidate _uninit_expr_10
-        connect _bundle_literal_expr_143.data, _uninit_expr_10
-        wire _bundle_literal_expr_144: Ty29
-        wire _bundle_literal_expr_145: Ty27
-        connect _bundle_literal_expr_145.adj_value, UInt<1>(0h1)
-        connect _bundle_literal_expr_144.unit_num, _bundle_literal_expr_145
-        wire _bundle_literal_expr_146: Ty28
-        connect _bundle_literal_expr_146.value, UInt<1>(0h1)
-        connect _bundle_literal_expr_144.unit_out_reg, _bundle_literal_expr_146
-        connect _bundle_literal_expr_143.mask, _bundle_literal_expr_144
-        ; connect different types:
-        ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        connect rename_table_special_1_flag0_rFE, _bundle_literal_expr_143 @[reg_alloc.rs 176:17]
-        wire rename_table_special_1_flag1_rFF: Ty36 @[reg_alloc.rs 171:21]
-        connect rename_table_special_mem_w13, rename_table_special_1_flag1_rFF @[reg_alloc.rs 174:17]
-        wire _bundle_literal_expr_147: Ty55
-        connect _bundle_literal_expr_147.addr, UInt<0>(0h0)
-        connect _bundle_literal_expr_147.en, UInt<1>(0h0)
-        connect _bundle_literal_expr_147.clk, cd.clk
-        wire _uninit_expr_11: Ty25
-        invalidate _uninit_expr_11
-        connect _bundle_literal_expr_147.data, _uninit_expr_11
-        wire _bundle_literal_expr_148: Ty29
-        wire _bundle_literal_expr_149: Ty27
-        connect _bundle_literal_expr_149.adj_value, UInt<1>(0h1)
-        connect _bundle_literal_expr_148.unit_num, _bundle_literal_expr_149
-        wire _bundle_literal_expr_150: Ty28
-        connect _bundle_literal_expr_150.value, UInt<1>(0h1)
-        connect _bundle_literal_expr_148.unit_out_reg, _bundle_literal_expr_150
-        connect _bundle_literal_expr_147.mask, _bundle_literal_expr_148
-        ; connect different types:
-        ; lhs: Bundle {addr: UInt<1>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        ; rhs: Bundle {addr: UInt<0>, en: Bool, clk: Clock, data: Bundle {unit_num: Bundle {adj_value: UInt<2>}, unit_out_reg: Bundle {value: UInt<4>}}, mask: Bundle {unit_num: Bundle {adj_value: Bool}, unit_out_reg: Bundle {value: Bool}}}
-        connect rename_table_special_1_flag1_rFF, _bundle_literal_expr_147 @[reg_alloc.rs 176:17]
-        match fetch_decode_interface.decoded_insns[1].data: @[reg_alloc.rs 190:9]
+                                HdlSome(_match_arm_value_127):
+                                    wire _bundle_literal_expr_122: Ty1
+                                    connect _bundle_literal_expr_122.value, tail(UInt<32>(0hFF), 24)
+                                    connect flag_reg_11, _bundle_literal_expr_122 @[instruction.rs 725:21]
+                            when eq(dest_reg_24.normal_regs[0].value, rename_table_special_1_src_2.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_special_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_115) @[reg_alloc.rs 131:41]
+                            when eq(dest_reg_24.normal_regs[1].value, rename_table_special_1_src_2.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_special_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_115) @[reg_alloc.rs 131:41]
+                            when eq(flag_reg_10.value, rename_table_special_1_src_2.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_special_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_115) @[reg_alloc.rs 131:41]
+                            when eq(flag_reg_11.value, rename_table_special_1_src_2.addr.value): @[reg_alloc.rs 130:37]
+                                connect rename_table_special_1_src_2.data, {|HdlNone, HdlSome: Ty25|}(HdlSome, _match_arm_value_115) @[reg_alloc.rs 131:41]
+        match fetch_decode_interface.decoded_insns[1].data: @[reg_alloc.rs 159:9]
             HdlNone:
                 skip
-            HdlSome(_match_arm_value_112):
-                wire unit_kind_1: Ty56 @[unit.rs 127:1]
-                match _match_arm_value_112.mop: @[unit.rs 127:1]
-                    AluBranch(_match_arm_value_113):
+            HdlSome(_match_arm_value_128):
+                wire unit_kind_1: Ty46 @[unit.rs 127:1]
+                match _match_arm_value_128.mop: @[unit.rs 127:1]
+                    AluBranch(_match_arm_value_129):
                         connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(AluBranch) @[unit.rs 127:1]
-                    L2RegisterFile(_match_arm_value_114):
+                    L2RegisterFile(_match_arm_value_130):
                         connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(L2RegisterFile) @[unit.rs 127:1]
-                    LoadStore(_match_arm_value_115):
+                    LoadStore(_match_arm_value_131):
                         connect unit_kind_1, {|AluBranch, L2RegisterFile, LoadStore|}(LoadStore) @[unit.rs 127:1]
                 wire available_units_for_kind_1: UInt<1>[2] @[unit.rs 127:1]
                 match unit_kind_1: @[unit.rs 127:1]
@@ -2153,213 +1851,313 @@ circuit reg_alloc:
                     LoadStore:
                         connect available_units_for_kind_1[0], UInt<1>(0h0) @[unit.rs 127:1]
                         connect available_units_for_kind_1[1], UInt<1>(0h0) @[unit.rs 127:1]
-                connect available_units[1], available_units_for_kind_1 @[reg_alloc.rs 191:13]
-                match renamed_mops_out_reg[1]: @[reg_alloc.rs 196:13]
+                connect available_units[1], available_units_for_kind_1 @[reg_alloc.rs 160:13]
+                match renamed_mops_out_reg[1]: @[reg_alloc.rs 165:13]
                     HdlNone:
                         skip
-                    HdlSome(_match_arm_value_116):
+                    HdlSome(_match_arm_value_132):
                         wire dest_reg_28: Ty4 @[unit.rs 127:1]
-                        match _match_arm_value_112.mop: @[unit.rs 127:1]
-                            AluBranch(_match_arm_value_117):
+                        match _match_arm_value_128.mop: @[unit.rs 127:1]
+                            AluBranch(_match_arm_value_133):
                                 wire dest_reg_29: Ty4 @[instruction.rs 477:1]
-                                match _match_arm_value_117: @[instruction.rs 477:1]
-                                    AddSub(_match_arm_value_118):
-                                        connect dest_reg_29, _match_arm_value_118.alu_common.common.dest @[instruction.rs 477:1]
-                                    AddSubI(_match_arm_value_119):
-                                        connect dest_reg_29, _match_arm_value_119.alu_common.common.dest @[instruction.rs 477:1]
-                                    Logical(_match_arm_value_120):
-                                        connect dest_reg_29, _match_arm_value_120.alu_common.common.dest @[instruction.rs 477:1]
+                                match _match_arm_value_133: @[instruction.rs 477:1]
+                                    AddSub(_match_arm_value_134):
+                                        connect dest_reg_29, _match_arm_value_134.alu_common.common.dest @[instruction.rs 477:1]
+                                    AddSubI(_match_arm_value_135):
+                                        connect dest_reg_29, _match_arm_value_135.alu_common.common.dest @[instruction.rs 477:1]
+                                    Logical(_match_arm_value_136):
+                                        connect dest_reg_29, _match_arm_value_136.alu_common.common.dest @[instruction.rs 477:1]
                                 connect dest_reg_28, dest_reg_29 @[unit.rs 127:1]
-                            L2RegisterFile(_match_arm_value_121):
+                            L2RegisterFile(_match_arm_value_137):
                                 wire dest_reg_30: Ty4 @[instruction.rs 504:1]
-                                match _match_arm_value_121: @[instruction.rs 504:1]
-                                    ReadL2Reg(_match_arm_value_122):
-                                        connect dest_reg_30, _match_arm_value_122.common.dest @[instruction.rs 504:1]
-                                    WriteL2Reg(_match_arm_value_123):
-                                        connect dest_reg_30, _match_arm_value_123.common.dest @[instruction.rs 504:1]
+                                match _match_arm_value_137: @[instruction.rs 504:1]
+                                    ReadL2Reg(_match_arm_value_138):
+                                        connect dest_reg_30, _match_arm_value_138.common.dest @[instruction.rs 504:1]
+                                    WriteL2Reg(_match_arm_value_139):
+                                        connect dest_reg_30, _match_arm_value_139.common.dest @[instruction.rs 504:1]
                                 connect dest_reg_28, dest_reg_30 @[unit.rs 127:1]
-                            LoadStore(_match_arm_value_124):
+                            LoadStore(_match_arm_value_140):
                                 wire dest_reg_31: Ty4 @[instruction.rs 539:1]
-                                match _match_arm_value_124: @[instruction.rs 539:1]
-                                    Load(_match_arm_value_125):
-                                        connect dest_reg_31, _match_arm_value_125.dest @[instruction.rs 539:1]
-                                    Store(_match_arm_value_126):
-                                        connect dest_reg_31, _match_arm_value_126.dest @[instruction.rs 539:1]
+                                match _match_arm_value_140: @[instruction.rs 539:1]
+                                    Load(_match_arm_value_141):
+                                        connect dest_reg_31, _match_arm_value_141.dest @[instruction.rs 539:1]
+                                    Store(_match_arm_value_142):
+                                        connect dest_reg_31, _match_arm_value_142.dest @[instruction.rs 539:1]
                                 connect dest_reg_28, dest_reg_31 @[unit.rs 127:1]
-                        wire mapped_regs_4: Ty51 @[unit.rs 127:1]
-                        match _match_arm_value_112.mop: @[unit.rs 127:1]
-                            AluBranch(_match_arm_value_127):
-                                wire mapped_regs_5: Ty46 @[instruction.rs 477:1]
-                                match _match_arm_value_127: @[instruction.rs 477:1]
-                                    AddSub(_match_arm_value_128):
-                                        wire _bundle_literal_expr_151: Ty1
-                                        connect _bundle_literal_expr_151.value, _match_arm_value_128.alu_common.common.src[0]
-                                        connect rename_1_src_0.addr, _bundle_literal_expr_151 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_152: Ty1
-                                        connect _bundle_literal_expr_152.value, _match_arm_value_128.alu_common.common.src[1]
-                                        connect rename_1_src_1.addr, _bundle_literal_expr_152 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_153: Ty1
-                                        connect _bundle_literal_expr_153.value, _match_arm_value_128.alu_common.common.src[2]
-                                        connect rename_1_src_2.addr, _bundle_literal_expr_153 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_154: Ty44
-                                        wire _bundle_literal_expr_155: Ty43
-                                        wire _bundle_literal_expr_156: Ty42
-                                        connect _bundle_literal_expr_156.prefix_pad, _match_arm_value_128.alu_common.common.prefix_pad
-                                        connect _bundle_literal_expr_156.dest, _match_arm_value_116.unit_out_reg
+                        wire mapped_regs_4: Ty42 @[unit.rs 127:1]
+                        match _match_arm_value_128.mop: @[unit.rs 127:1]
+                            AluBranch(_match_arm_value_143):
+                                wire mapped_regs_5: Ty37 @[instruction.rs 477:1]
+                                match _match_arm_value_143: @[instruction.rs 477:1]
+                                    AddSub(_match_arm_value_144):
+                                        wire renamed_src_reg_1_0: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_123: Ty1
+                                        connect _bundle_literal_expr_123.value, _match_arm_value_144.alu_common.common.src[0]
+                                        connect rename_table_normal_1_src_0.addr, _bundle_literal_expr_123 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_124: Ty1
+                                        connect _bundle_literal_expr_124.value, _match_arm_value_144.alu_common.common.src[0]
+                                        connect rename_table_special_1_src_0.addr, _bundle_literal_expr_124 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_1_src_0.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_1_src_0.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_125: Ty25
+                                                        wire _bundle_literal_expr_126: Ty23
+                                                        connect _bundle_literal_expr_126.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_125.unit_num, _bundle_literal_expr_126
+                                                        wire _bundle_literal_expr_127: Ty24
+                                                        connect _bundle_literal_expr_127.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_125.unit_out_reg, _bundle_literal_expr_127
+                                                        connect renamed_src_reg_1_0, _bundle_literal_expr_125 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_145):
+                                                        connect renamed_src_reg_1_0, _match_arm_value_145 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_146):
+                                                connect renamed_src_reg_1_0, _match_arm_value_146 @[reg_alloc.rs 185:33]
+                                        wire renamed_src_reg_1_1: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_128: Ty1
+                                        connect _bundle_literal_expr_128.value, _match_arm_value_144.alu_common.common.src[1]
+                                        connect rename_table_normal_1_src_1.addr, _bundle_literal_expr_128 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_129: Ty1
+                                        connect _bundle_literal_expr_129.value, _match_arm_value_144.alu_common.common.src[1]
+                                        connect rename_table_special_1_src_1.addr, _bundle_literal_expr_129 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_1_src_1.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_1_src_1.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_130: Ty25
+                                                        wire _bundle_literal_expr_131: Ty23
+                                                        connect _bundle_literal_expr_131.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_130.unit_num, _bundle_literal_expr_131
+                                                        wire _bundle_literal_expr_132: Ty24
+                                                        connect _bundle_literal_expr_132.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_130.unit_out_reg, _bundle_literal_expr_132
+                                                        connect renamed_src_reg_1_1, _bundle_literal_expr_130 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_147):
+                                                        connect renamed_src_reg_1_1, _match_arm_value_147 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_148):
+                                                connect renamed_src_reg_1_1, _match_arm_value_148 @[reg_alloc.rs 185:33]
+                                        wire renamed_src_reg_1_2: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_133: Ty1
+                                        connect _bundle_literal_expr_133.value, _match_arm_value_144.alu_common.common.src[2]
+                                        connect rename_table_normal_1_src_2.addr, _bundle_literal_expr_133 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_134: Ty1
+                                        connect _bundle_literal_expr_134.value, _match_arm_value_144.alu_common.common.src[2]
+                                        connect rename_table_special_1_src_2.addr, _bundle_literal_expr_134 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_1_src_2.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_1_src_2.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_135: Ty25
+                                                        wire _bundle_literal_expr_136: Ty23
+                                                        connect _bundle_literal_expr_136.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_135.unit_num, _bundle_literal_expr_136
+                                                        wire _bundle_literal_expr_137: Ty24
+                                                        connect _bundle_literal_expr_137.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_135.unit_out_reg, _bundle_literal_expr_137
+                                                        connect renamed_src_reg_1_2, _bundle_literal_expr_135 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_149):
+                                                        connect renamed_src_reg_1_2, _match_arm_value_149 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_150):
+                                                connect renamed_src_reg_1_2, _match_arm_value_150 @[reg_alloc.rs 185:33]
+                                        wire _bundle_literal_expr_138: Ty35
+                                        wire _bundle_literal_expr_139: Ty34
+                                        wire _bundle_literal_expr_140: Ty33
+                                        connect _bundle_literal_expr_140.prefix_pad, _match_arm_value_144.alu_common.common.prefix_pad
+                                        connect _bundle_literal_expr_140.dest, _match_arm_value_132.unit_out_reg
                                         wire _array_literal_expr_38: UInt<6>[3]
                                         wire _array_literal_expr_39: UInt<6>[3]
-                                        wire _cast_bundle_to_bits_expr_39: Ty57
-                                        connect _cast_bundle_to_bits_expr_39.unit_num, rename_1_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_39.unit_out_reg, rename_1_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_39: Ty47
+                                        connect _cast_bundle_to_bits_expr_39.unit_num, renamed_src_reg_1_0.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_39.unit_out_reg, renamed_src_reg_1_0.unit_out_reg.value
                                         wire _cast_to_bits_expr_39: UInt<6>
                                         connect _cast_to_bits_expr_39, cat(_cast_bundle_to_bits_expr_39.unit_out_reg, _cast_bundle_to_bits_expr_39.unit_num)
                                         connect _array_literal_expr_39[0], _cast_to_bits_expr_39
-                                        wire _cast_bundle_to_bits_expr_40: Ty57
-                                        connect _cast_bundle_to_bits_expr_40.unit_num, rename_1_src_1.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_40.unit_out_reg, rename_1_src_1.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_40: Ty47
+                                        connect _cast_bundle_to_bits_expr_40.unit_num, renamed_src_reg_1_1.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_40.unit_out_reg, renamed_src_reg_1_1.unit_out_reg.value
                                         wire _cast_to_bits_expr_40: UInt<6>
                                         connect _cast_to_bits_expr_40, cat(_cast_bundle_to_bits_expr_40.unit_out_reg, _cast_bundle_to_bits_expr_40.unit_num)
                                         connect _array_literal_expr_39[1], _cast_to_bits_expr_40
-                                        wire _cast_bundle_to_bits_expr_41: Ty57
-                                        connect _cast_bundle_to_bits_expr_41.unit_num, rename_1_src_2.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_41.unit_out_reg, rename_1_src_2.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_41: Ty47
+                                        connect _cast_bundle_to_bits_expr_41.unit_num, renamed_src_reg_1_2.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_41.unit_out_reg, renamed_src_reg_1_2.unit_out_reg.value
                                         wire _cast_to_bits_expr_41: UInt<6>
                                         connect _cast_to_bits_expr_41, cat(_cast_bundle_to_bits_expr_41.unit_out_reg, _cast_bundle_to_bits_expr_41.unit_num)
                                         connect _array_literal_expr_39[2], _cast_to_bits_expr_41
                                         connect _array_literal_expr_38[0], _array_literal_expr_39[0]
                                         wire _array_literal_expr_40: UInt<6>[3]
-                                        wire _cast_bundle_to_bits_expr_42: Ty57
-                                        connect _cast_bundle_to_bits_expr_42.unit_num, rename_1_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_42.unit_out_reg, rename_1_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_42: Ty47
+                                        connect _cast_bundle_to_bits_expr_42.unit_num, renamed_src_reg_1_0.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_42.unit_out_reg, renamed_src_reg_1_0.unit_out_reg.value
                                         wire _cast_to_bits_expr_42: UInt<6>
                                         connect _cast_to_bits_expr_42, cat(_cast_bundle_to_bits_expr_42.unit_out_reg, _cast_bundle_to_bits_expr_42.unit_num)
                                         connect _array_literal_expr_40[0], _cast_to_bits_expr_42
-                                        wire _cast_bundle_to_bits_expr_43: Ty57
-                                        connect _cast_bundle_to_bits_expr_43.unit_num, rename_1_src_1.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_43.unit_out_reg, rename_1_src_1.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_43: Ty47
+                                        connect _cast_bundle_to_bits_expr_43.unit_num, renamed_src_reg_1_1.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_43.unit_out_reg, renamed_src_reg_1_1.unit_out_reg.value
                                         wire _cast_to_bits_expr_43: UInt<6>
                                         connect _cast_to_bits_expr_43, cat(_cast_bundle_to_bits_expr_43.unit_out_reg, _cast_bundle_to_bits_expr_43.unit_num)
                                         connect _array_literal_expr_40[1], _cast_to_bits_expr_43
-                                        wire _cast_bundle_to_bits_expr_44: Ty57
-                                        connect _cast_bundle_to_bits_expr_44.unit_num, rename_1_src_2.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_44.unit_out_reg, rename_1_src_2.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_44: Ty47
+                                        connect _cast_bundle_to_bits_expr_44.unit_num, renamed_src_reg_1_2.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_44.unit_out_reg, renamed_src_reg_1_2.unit_out_reg.value
                                         wire _cast_to_bits_expr_44: UInt<6>
                                         connect _cast_to_bits_expr_44, cat(_cast_bundle_to_bits_expr_44.unit_out_reg, _cast_bundle_to_bits_expr_44.unit_num)
                                         connect _array_literal_expr_40[2], _cast_to_bits_expr_44
                                         connect _array_literal_expr_38[1], _array_literal_expr_40[1]
                                         wire _array_literal_expr_41: UInt<6>[3]
-                                        wire _cast_bundle_to_bits_expr_45: Ty57
-                                        connect _cast_bundle_to_bits_expr_45.unit_num, rename_1_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_45.unit_out_reg, rename_1_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_45: Ty47
+                                        connect _cast_bundle_to_bits_expr_45.unit_num, renamed_src_reg_1_0.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_45.unit_out_reg, renamed_src_reg_1_0.unit_out_reg.value
                                         wire _cast_to_bits_expr_45: UInt<6>
                                         connect _cast_to_bits_expr_45, cat(_cast_bundle_to_bits_expr_45.unit_out_reg, _cast_bundle_to_bits_expr_45.unit_num)
                                         connect _array_literal_expr_41[0], _cast_to_bits_expr_45
-                                        wire _cast_bundle_to_bits_expr_46: Ty57
-                                        connect _cast_bundle_to_bits_expr_46.unit_num, rename_1_src_1.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_46.unit_out_reg, rename_1_src_1.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_46: Ty47
+                                        connect _cast_bundle_to_bits_expr_46.unit_num, renamed_src_reg_1_1.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_46.unit_out_reg, renamed_src_reg_1_1.unit_out_reg.value
                                         wire _cast_to_bits_expr_46: UInt<6>
                                         connect _cast_to_bits_expr_46, cat(_cast_bundle_to_bits_expr_46.unit_out_reg, _cast_bundle_to_bits_expr_46.unit_num)
                                         connect _array_literal_expr_41[1], _cast_to_bits_expr_46
-                                        wire _cast_bundle_to_bits_expr_47: Ty57
-                                        connect _cast_bundle_to_bits_expr_47.unit_num, rename_1_src_2.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_47.unit_out_reg, rename_1_src_2.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_47: Ty47
+                                        connect _cast_bundle_to_bits_expr_47.unit_num, renamed_src_reg_1_2.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_47.unit_out_reg, renamed_src_reg_1_2.unit_out_reg.value
                                         wire _cast_to_bits_expr_47: UInt<6>
                                         connect _cast_to_bits_expr_47, cat(_cast_bundle_to_bits_expr_47.unit_out_reg, _cast_bundle_to_bits_expr_47.unit_num)
                                         connect _array_literal_expr_41[2], _cast_to_bits_expr_47
                                         connect _array_literal_expr_38[2], _array_literal_expr_41[2]
-                                        connect _bundle_literal_expr_156.src, _array_literal_expr_38
-                                        wire _bundle_literal_expr_157: Ty58
-                                        connect _bundle_literal_expr_157.imm_low, _match_arm_value_128.alu_common.common.imm_low
+                                        connect _bundle_literal_expr_140.src, _array_literal_expr_38
+                                        wire _bundle_literal_expr_141: Ty48
+                                        connect _bundle_literal_expr_141.imm_low, _match_arm_value_144.alu_common.common.imm_low
                                         wire _array_literal_expr_42: UInt<8>[0]
                                         invalidate _array_literal_expr_42
-                                        connect _bundle_literal_expr_157.reversed_src, _array_literal_expr_42
-                                        connect _bundle_literal_expr_157.imm_sign, _match_arm_value_128.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_48: Ty59
-                                        connect _cast_bundle_to_bits_expr_48.imm_low, _bundle_literal_expr_157.imm_low
+                                        connect _bundle_literal_expr_141.reversed_src, _array_literal_expr_42
+                                        connect _bundle_literal_expr_141.imm_sign, _match_arm_value_144.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_48: Ty49
+                                        connect _cast_bundle_to_bits_expr_48.imm_low, _bundle_literal_expr_141.imm_low
                                         connect _cast_bundle_to_bits_expr_48.reversed_src, UInt<0>(0)
-                                        connect _cast_bundle_to_bits_expr_48.imm_sign, asUInt(_bundle_literal_expr_157.imm_sign)
+                                        connect _cast_bundle_to_bits_expr_48.imm_sign, asUInt(_bundle_literal_expr_141.imm_sign)
                                         wire _cast_to_bits_expr_48: UInt<26>
                                         connect _cast_to_bits_expr_48, cat(_cast_bundle_to_bits_expr_48.imm_sign, cat(_cast_bundle_to_bits_expr_48.reversed_src, _cast_bundle_to_bits_expr_48.imm_low))
-                                        connect _bundle_literal_expr_156.imm_low, bits(asSInt(_cast_to_bits_expr_48), 24, 0)
-                                        wire _bundle_literal_expr_158: Ty58
-                                        connect _bundle_literal_expr_158.imm_low, _match_arm_value_128.alu_common.common.imm_low
+                                        connect _bundle_literal_expr_140.imm_low, bits(asSInt(_cast_to_bits_expr_48), 24, 0)
+                                        wire _bundle_literal_expr_142: Ty48
+                                        connect _bundle_literal_expr_142.imm_low, _match_arm_value_144.alu_common.common.imm_low
                                         wire _array_literal_expr_43: UInt<8>[0]
                                         invalidate _array_literal_expr_43
-                                        connect _bundle_literal_expr_158.reversed_src, _array_literal_expr_43
-                                        connect _bundle_literal_expr_158.imm_sign, _match_arm_value_128.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_49: Ty59
-                                        connect _cast_bundle_to_bits_expr_49.imm_low, _bundle_literal_expr_158.imm_low
+                                        connect _bundle_literal_expr_142.reversed_src, _array_literal_expr_43
+                                        connect _bundle_literal_expr_142.imm_sign, _match_arm_value_144.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_49: Ty49
+                                        connect _cast_bundle_to_bits_expr_49.imm_low, _bundle_literal_expr_142.imm_low
                                         connect _cast_bundle_to_bits_expr_49.reversed_src, UInt<0>(0)
-                                        connect _cast_bundle_to_bits_expr_49.imm_sign, asUInt(_bundle_literal_expr_158.imm_sign)
+                                        connect _cast_bundle_to_bits_expr_49.imm_sign, asUInt(_bundle_literal_expr_142.imm_sign)
                                         wire _cast_to_bits_expr_49: UInt<26>
                                         connect _cast_to_bits_expr_49, cat(_cast_bundle_to_bits_expr_49.imm_sign, cat(_cast_bundle_to_bits_expr_49.reversed_src, _cast_bundle_to_bits_expr_49.imm_low))
-                                        connect _bundle_literal_expr_156.imm_sign, shr(asSInt(_cast_to_bits_expr_49), 25)
-                                        wire _bundle_literal_expr_159: Ty2
-                                        invalidate _bundle_literal_expr_159
-                                        connect _bundle_literal_expr_156._phantom, _bundle_literal_expr_159
-                                        connect _bundle_literal_expr_155.common, _bundle_literal_expr_156
-                                        connect _bundle_literal_expr_155.output_integer_mode, _match_arm_value_128.alu_common.output_integer_mode
-                                        connect _bundle_literal_expr_154.alu_common, _bundle_literal_expr_155
-                                        connect _bundle_literal_expr_154.invert_src0, _match_arm_value_128.invert_src0
-                                        connect _bundle_literal_expr_154.invert_carry_in, _match_arm_value_128.invert_carry_in
-                                        connect _bundle_literal_expr_154.invert_carry_out, _match_arm_value_128.invert_carry_out
-                                        connect _bundle_literal_expr_154.add_pc, _match_arm_value_128.add_pc
-                                        connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSub, _bundle_literal_expr_154) @[instruction.rs 477:1]
-                                    AddSubI(_match_arm_value_129):
-                                        wire _bundle_literal_expr_160: Ty1
-                                        connect _bundle_literal_expr_160.value, _match_arm_value_129.alu_common.common.src[0]
-                                        connect rename_1_src_0.addr, _bundle_literal_expr_160 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_161: Ty1
-                                        connect _bundle_literal_expr_161.value, _match_arm_value_129.alu_common.common.src[1]
-                                        connect rename_1_src_1.addr, _bundle_literal_expr_161 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_162: Ty44
-                                        wire _bundle_literal_expr_163: Ty43
-                                        wire _bundle_literal_expr_164: Ty42
-                                        connect _bundle_literal_expr_164.prefix_pad, _match_arm_value_129.alu_common.common.prefix_pad
-                                        connect _bundle_literal_expr_164.dest, _match_arm_value_116.unit_out_reg
+                                        connect _bundle_literal_expr_140.imm_sign, shr(asSInt(_cast_to_bits_expr_49), 25)
+                                        wire _bundle_literal_expr_143: Ty2
+                                        invalidate _bundle_literal_expr_143
+                                        connect _bundle_literal_expr_140._phantom, _bundle_literal_expr_143
+                                        connect _bundle_literal_expr_139.common, _bundle_literal_expr_140
+                                        connect _bundle_literal_expr_139.output_integer_mode, _match_arm_value_144.alu_common.output_integer_mode
+                                        connect _bundle_literal_expr_138.alu_common, _bundle_literal_expr_139
+                                        connect _bundle_literal_expr_138.invert_src0, _match_arm_value_144.invert_src0
+                                        connect _bundle_literal_expr_138.invert_carry_in, _match_arm_value_144.invert_carry_in
+                                        connect _bundle_literal_expr_138.invert_carry_out, _match_arm_value_144.invert_carry_out
+                                        connect _bundle_literal_expr_138.add_pc, _match_arm_value_144.add_pc
+                                        connect mapped_regs_5, {|AddSub: Ty35, AddSubI: Ty35, Logical: Ty36|}(AddSub, _bundle_literal_expr_138) @[instruction.rs 477:1]
+                                    AddSubI(_match_arm_value_151):
+                                        wire renamed_src_reg_1_0_1: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_144: Ty1
+                                        connect _bundle_literal_expr_144.value, _match_arm_value_151.alu_common.common.src[0]
+                                        connect rename_table_normal_1_src_0.addr, _bundle_literal_expr_144 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_145: Ty1
+                                        connect _bundle_literal_expr_145.value, _match_arm_value_151.alu_common.common.src[0]
+                                        connect rename_table_special_1_src_0.addr, _bundle_literal_expr_145 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_1_src_0.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_1_src_0.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_146: Ty25
+                                                        wire _bundle_literal_expr_147: Ty23
+                                                        connect _bundle_literal_expr_147.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_146.unit_num, _bundle_literal_expr_147
+                                                        wire _bundle_literal_expr_148: Ty24
+                                                        connect _bundle_literal_expr_148.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_146.unit_out_reg, _bundle_literal_expr_148
+                                                        connect renamed_src_reg_1_0_1, _bundle_literal_expr_146 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_152):
+                                                        connect renamed_src_reg_1_0_1, _match_arm_value_152 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_153):
+                                                connect renamed_src_reg_1_0_1, _match_arm_value_153 @[reg_alloc.rs 185:33]
+                                        wire renamed_src_reg_1_1_1: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_149: Ty1
+                                        connect _bundle_literal_expr_149.value, _match_arm_value_151.alu_common.common.src[1]
+                                        connect rename_table_normal_1_src_1.addr, _bundle_literal_expr_149 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_150: Ty1
+                                        connect _bundle_literal_expr_150.value, _match_arm_value_151.alu_common.common.src[1]
+                                        connect rename_table_special_1_src_1.addr, _bundle_literal_expr_150 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_1_src_1.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_1_src_1.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_151: Ty25
+                                                        wire _bundle_literal_expr_152: Ty23
+                                                        connect _bundle_literal_expr_152.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_151.unit_num, _bundle_literal_expr_152
+                                                        wire _bundle_literal_expr_153: Ty24
+                                                        connect _bundle_literal_expr_153.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_151.unit_out_reg, _bundle_literal_expr_153
+                                                        connect renamed_src_reg_1_1_1, _bundle_literal_expr_151 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_154):
+                                                        connect renamed_src_reg_1_1_1, _match_arm_value_154 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_155):
+                                                connect renamed_src_reg_1_1_1, _match_arm_value_155 @[reg_alloc.rs 185:33]
+                                        wire _bundle_literal_expr_154: Ty35
+                                        wire _bundle_literal_expr_155: Ty34
+                                        wire _bundle_literal_expr_156: Ty33
+                                        connect _bundle_literal_expr_156.prefix_pad, _match_arm_value_151.alu_common.common.prefix_pad
+                                        connect _bundle_literal_expr_156.dest, _match_arm_value_132.unit_out_reg
                                         wire _array_literal_expr_44: UInt<6>[3]
                                         wire _array_literal_expr_45: UInt<6>[2]
-                                        wire _cast_bundle_to_bits_expr_50: Ty57
-                                        connect _cast_bundle_to_bits_expr_50.unit_num, rename_1_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_50.unit_out_reg, rename_1_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_50: Ty47
+                                        connect _cast_bundle_to_bits_expr_50.unit_num, renamed_src_reg_1_0_1.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_50.unit_out_reg, renamed_src_reg_1_0_1.unit_out_reg.value
                                         wire _cast_to_bits_expr_50: UInt<6>
                                         connect _cast_to_bits_expr_50, cat(_cast_bundle_to_bits_expr_50.unit_out_reg, _cast_bundle_to_bits_expr_50.unit_num)
                                         connect _array_literal_expr_45[0], _cast_to_bits_expr_50
-                                        wire _cast_bundle_to_bits_expr_51: Ty57
-                                        connect _cast_bundle_to_bits_expr_51.unit_num, rename_1_src_1.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_51.unit_out_reg, rename_1_src_1.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_51: Ty47
+                                        connect _cast_bundle_to_bits_expr_51.unit_num, renamed_src_reg_1_1_1.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_51.unit_out_reg, renamed_src_reg_1_1_1.unit_out_reg.value
                                         wire _cast_to_bits_expr_51: UInt<6>
                                         connect _cast_to_bits_expr_51, cat(_cast_bundle_to_bits_expr_51.unit_out_reg, _cast_bundle_to_bits_expr_51.unit_num)
                                         connect _array_literal_expr_45[1], _cast_to_bits_expr_51
                                         connect _array_literal_expr_44[0], _array_literal_expr_45[0]
                                         wire _array_literal_expr_46: UInt<6>[2]
-                                        wire _cast_bundle_to_bits_expr_52: Ty57
-                                        connect _cast_bundle_to_bits_expr_52.unit_num, rename_1_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_52.unit_out_reg, rename_1_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_52: Ty47
+                                        connect _cast_bundle_to_bits_expr_52.unit_num, renamed_src_reg_1_0_1.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_52.unit_out_reg, renamed_src_reg_1_0_1.unit_out_reg.value
                                         wire _cast_to_bits_expr_52: UInt<6>
                                         connect _cast_to_bits_expr_52, cat(_cast_bundle_to_bits_expr_52.unit_out_reg, _cast_bundle_to_bits_expr_52.unit_num)
                                         connect _array_literal_expr_46[0], _cast_to_bits_expr_52
-                                        wire _cast_bundle_to_bits_expr_53: Ty57
-                                        connect _cast_bundle_to_bits_expr_53.unit_num, rename_1_src_1.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_53.unit_out_reg, rename_1_src_1.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_53: Ty47
+                                        connect _cast_bundle_to_bits_expr_53.unit_num, renamed_src_reg_1_1_1.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_53.unit_out_reg, renamed_src_reg_1_1_1.unit_out_reg.value
                                         wire _cast_to_bits_expr_53: UInt<6>
                                         connect _cast_to_bits_expr_53, cat(_cast_bundle_to_bits_expr_53.unit_out_reg, _cast_bundle_to_bits_expr_53.unit_num)
                                         connect _array_literal_expr_46[1], _cast_to_bits_expr_53
                                         connect _array_literal_expr_44[1], _array_literal_expr_46[1]
-                                        wire _bundle_literal_expr_165: Ty60
-                                        connect _bundle_literal_expr_165.imm_low, _match_arm_value_129.alu_common.common.imm_low
+                                        wire _bundle_literal_expr_157: Ty50
+                                        connect _bundle_literal_expr_157.imm_low, _match_arm_value_151.alu_common.common.imm_low
                                         wire _array_literal_expr_47: UInt<8>[1]
-                                        connect _array_literal_expr_47[0], _match_arm_value_129.alu_common.common.src[2]
-                                        connect _bundle_literal_expr_165.reversed_src, _array_literal_expr_47
-                                        connect _bundle_literal_expr_165.imm_sign, _match_arm_value_129.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_54: Ty61
-                                        connect _cast_bundle_to_bits_expr_54.imm_low, _bundle_literal_expr_165.imm_low
-                                        connect _cast_bundle_to_bits_expr_54.reversed_src, _bundle_literal_expr_165.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_54.imm_sign, asUInt(_bundle_literal_expr_165.imm_sign)
+                                        connect _array_literal_expr_47[0], _match_arm_value_151.alu_common.common.src[2]
+                                        connect _bundle_literal_expr_157.reversed_src, _array_literal_expr_47
+                                        connect _bundle_literal_expr_157.imm_sign, _match_arm_value_151.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_54: Ty51
+                                        connect _cast_bundle_to_bits_expr_54.imm_low, _bundle_literal_expr_157.imm_low
+                                        connect _cast_bundle_to_bits_expr_54.reversed_src, _bundle_literal_expr_157.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_54.imm_sign, asUInt(_bundle_literal_expr_157.imm_sign)
                                         wire _cast_to_bits_expr_54: UInt<34>
                                         connect _cast_to_bits_expr_54, cat(_cast_bundle_to_bits_expr_54.imm_sign, cat(_cast_bundle_to_bits_expr_54.reversed_src, _cast_bundle_to_bits_expr_54.imm_low))
-                                        wire _cast_bits_to_bundle_expr_6: Ty60
-                                        wire _cast_bits_to_bundle_expr_flattened_6: Ty61
+                                        wire _cast_bits_to_bundle_expr_6: Ty50
+                                        wire _cast_bits_to_bundle_expr_flattened_6: Ty51
                                         connect _cast_bits_to_bundle_expr_flattened_6.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_54)), 24, 0)
                                         connect _cast_bits_to_bundle_expr_6.imm_low, _cast_bits_to_bundle_expr_flattened_6.imm_low
                                         connect _cast_bits_to_bundle_expr_flattened_6.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_54)), 32, 25)
@@ -2371,99 +2169,139 @@ circuit reg_alloc:
                                         connect _cast_bits_to_bundle_expr_flattened_6.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_54)), 33, 33)
                                         connect _cast_bits_to_bundle_expr_6.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_6.imm_sign)
                                         connect _array_literal_expr_44[2], tail(_cast_bits_to_bundle_expr_6.reversed_src[0], 2)
-                                        connect _bundle_literal_expr_164.src, _array_literal_expr_44
-                                        wire _bundle_literal_expr_166: Ty60
-                                        connect _bundle_literal_expr_166.imm_low, _match_arm_value_129.alu_common.common.imm_low
+                                        connect _bundle_literal_expr_156.src, _array_literal_expr_44
+                                        wire _bundle_literal_expr_158: Ty50
+                                        connect _bundle_literal_expr_158.imm_low, _match_arm_value_151.alu_common.common.imm_low
                                         wire _array_literal_expr_48: UInt<8>[1]
-                                        connect _array_literal_expr_48[0], _match_arm_value_129.alu_common.common.src[2]
-                                        connect _bundle_literal_expr_166.reversed_src, _array_literal_expr_48
-                                        connect _bundle_literal_expr_166.imm_sign, _match_arm_value_129.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_55: Ty61
-                                        connect _cast_bundle_to_bits_expr_55.imm_low, _bundle_literal_expr_166.imm_low
-                                        connect _cast_bundle_to_bits_expr_55.reversed_src, _bundle_literal_expr_166.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_55.imm_sign, asUInt(_bundle_literal_expr_166.imm_sign)
+                                        connect _array_literal_expr_48[0], _match_arm_value_151.alu_common.common.src[2]
+                                        connect _bundle_literal_expr_158.reversed_src, _array_literal_expr_48
+                                        connect _bundle_literal_expr_158.imm_sign, _match_arm_value_151.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_55: Ty51
+                                        connect _cast_bundle_to_bits_expr_55.imm_low, _bundle_literal_expr_158.imm_low
+                                        connect _cast_bundle_to_bits_expr_55.reversed_src, _bundle_literal_expr_158.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_55.imm_sign, asUInt(_bundle_literal_expr_158.imm_sign)
                                         wire _cast_to_bits_expr_55: UInt<34>
                                         connect _cast_to_bits_expr_55, cat(_cast_bundle_to_bits_expr_55.imm_sign, cat(_cast_bundle_to_bits_expr_55.reversed_src, _cast_bundle_to_bits_expr_55.imm_low))
-                                        connect _bundle_literal_expr_164.imm_low, bits(asSInt(_cast_to_bits_expr_55), 24, 0)
-                                        wire _bundle_literal_expr_167: Ty60
-                                        connect _bundle_literal_expr_167.imm_low, _match_arm_value_129.alu_common.common.imm_low
+                                        connect _bundle_literal_expr_156.imm_low, bits(asSInt(_cast_to_bits_expr_55), 24, 0)
+                                        wire _bundle_literal_expr_159: Ty50
+                                        connect _bundle_literal_expr_159.imm_low, _match_arm_value_151.alu_common.common.imm_low
                                         wire _array_literal_expr_49: UInt<8>[1]
-                                        connect _array_literal_expr_49[0], _match_arm_value_129.alu_common.common.src[2]
-                                        connect _bundle_literal_expr_167.reversed_src, _array_literal_expr_49
-                                        connect _bundle_literal_expr_167.imm_sign, _match_arm_value_129.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_56: Ty61
-                                        connect _cast_bundle_to_bits_expr_56.imm_low, _bundle_literal_expr_167.imm_low
-                                        connect _cast_bundle_to_bits_expr_56.reversed_src, _bundle_literal_expr_167.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_56.imm_sign, asUInt(_bundle_literal_expr_167.imm_sign)
+                                        connect _array_literal_expr_49[0], _match_arm_value_151.alu_common.common.src[2]
+                                        connect _bundle_literal_expr_159.reversed_src, _array_literal_expr_49
+                                        connect _bundle_literal_expr_159.imm_sign, _match_arm_value_151.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_56: Ty51
+                                        connect _cast_bundle_to_bits_expr_56.imm_low, _bundle_literal_expr_159.imm_low
+                                        connect _cast_bundle_to_bits_expr_56.reversed_src, _bundle_literal_expr_159.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_56.imm_sign, asUInt(_bundle_literal_expr_159.imm_sign)
                                         wire _cast_to_bits_expr_56: UInt<34>
                                         connect _cast_to_bits_expr_56, cat(_cast_bundle_to_bits_expr_56.imm_sign, cat(_cast_bundle_to_bits_expr_56.reversed_src, _cast_bundle_to_bits_expr_56.imm_low))
-                                        connect _bundle_literal_expr_164.imm_sign, shr(asSInt(_cast_to_bits_expr_56), 33)
-                                        wire _bundle_literal_expr_168: Ty2
-                                        invalidate _bundle_literal_expr_168
-                                        connect _bundle_literal_expr_164._phantom, _bundle_literal_expr_168
-                                        connect _bundle_literal_expr_163.common, _bundle_literal_expr_164
-                                        connect _bundle_literal_expr_163.output_integer_mode, _match_arm_value_129.alu_common.output_integer_mode
-                                        connect _bundle_literal_expr_162.alu_common, _bundle_literal_expr_163
-                                        connect _bundle_literal_expr_162.invert_src0, _match_arm_value_129.invert_src0
-                                        connect _bundle_literal_expr_162.invert_carry_in, _match_arm_value_129.invert_carry_in
-                                        connect _bundle_literal_expr_162.invert_carry_out, _match_arm_value_129.invert_carry_out
-                                        connect _bundle_literal_expr_162.add_pc, _match_arm_value_129.add_pc
-                                        connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(AddSubI, _bundle_literal_expr_162) @[instruction.rs 477:1]
-                                    Logical(_match_arm_value_130):
-                                        wire _bundle_literal_expr_169: Ty1
-                                        connect _bundle_literal_expr_169.value, _match_arm_value_130.alu_common.common.src[0]
-                                        connect rename_1_src_0.addr, _bundle_literal_expr_169 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_170: Ty1
-                                        connect _bundle_literal_expr_170.value, _match_arm_value_130.alu_common.common.src[1]
-                                        connect rename_1_src_1.addr, _bundle_literal_expr_170 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_171: Ty45
-                                        wire _bundle_literal_expr_172: Ty43
-                                        wire _bundle_literal_expr_173: Ty42
-                                        connect _bundle_literal_expr_173.prefix_pad, _match_arm_value_130.alu_common.common.prefix_pad
-                                        connect _bundle_literal_expr_173.dest, _match_arm_value_116.unit_out_reg
+                                        connect _bundle_literal_expr_156.imm_sign, shr(asSInt(_cast_to_bits_expr_56), 33)
+                                        wire _bundle_literal_expr_160: Ty2
+                                        invalidate _bundle_literal_expr_160
+                                        connect _bundle_literal_expr_156._phantom, _bundle_literal_expr_160
+                                        connect _bundle_literal_expr_155.common, _bundle_literal_expr_156
+                                        connect _bundle_literal_expr_155.output_integer_mode, _match_arm_value_151.alu_common.output_integer_mode
+                                        connect _bundle_literal_expr_154.alu_common, _bundle_literal_expr_155
+                                        connect _bundle_literal_expr_154.invert_src0, _match_arm_value_151.invert_src0
+                                        connect _bundle_literal_expr_154.invert_carry_in, _match_arm_value_151.invert_carry_in
+                                        connect _bundle_literal_expr_154.invert_carry_out, _match_arm_value_151.invert_carry_out
+                                        connect _bundle_literal_expr_154.add_pc, _match_arm_value_151.add_pc
+                                        connect mapped_regs_5, {|AddSub: Ty35, AddSubI: Ty35, Logical: Ty36|}(AddSubI, _bundle_literal_expr_154) @[instruction.rs 477:1]
+                                    Logical(_match_arm_value_156):
+                                        wire renamed_src_reg_1_0_2: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_161: Ty1
+                                        connect _bundle_literal_expr_161.value, _match_arm_value_156.alu_common.common.src[0]
+                                        connect rename_table_normal_1_src_0.addr, _bundle_literal_expr_161 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_162: Ty1
+                                        connect _bundle_literal_expr_162.value, _match_arm_value_156.alu_common.common.src[0]
+                                        connect rename_table_special_1_src_0.addr, _bundle_literal_expr_162 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_1_src_0.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_1_src_0.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_163: Ty25
+                                                        wire _bundle_literal_expr_164: Ty23
+                                                        connect _bundle_literal_expr_164.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_163.unit_num, _bundle_literal_expr_164
+                                                        wire _bundle_literal_expr_165: Ty24
+                                                        connect _bundle_literal_expr_165.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_163.unit_out_reg, _bundle_literal_expr_165
+                                                        connect renamed_src_reg_1_0_2, _bundle_literal_expr_163 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_157):
+                                                        connect renamed_src_reg_1_0_2, _match_arm_value_157 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_158):
+                                                connect renamed_src_reg_1_0_2, _match_arm_value_158 @[reg_alloc.rs 185:33]
+                                        wire renamed_src_reg_1_1_2: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_166: Ty1
+                                        connect _bundle_literal_expr_166.value, _match_arm_value_156.alu_common.common.src[1]
+                                        connect rename_table_normal_1_src_1.addr, _bundle_literal_expr_166 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_167: Ty1
+                                        connect _bundle_literal_expr_167.value, _match_arm_value_156.alu_common.common.src[1]
+                                        connect rename_table_special_1_src_1.addr, _bundle_literal_expr_167 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_1_src_1.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_1_src_1.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_168: Ty25
+                                                        wire _bundle_literal_expr_169: Ty23
+                                                        connect _bundle_literal_expr_169.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_168.unit_num, _bundle_literal_expr_169
+                                                        wire _bundle_literal_expr_170: Ty24
+                                                        connect _bundle_literal_expr_170.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_168.unit_out_reg, _bundle_literal_expr_170
+                                                        connect renamed_src_reg_1_1_2, _bundle_literal_expr_168 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_159):
+                                                        connect renamed_src_reg_1_1_2, _match_arm_value_159 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_160):
+                                                connect renamed_src_reg_1_1_2, _match_arm_value_160 @[reg_alloc.rs 185:33]
+                                        wire _bundle_literal_expr_171: Ty36
+                                        wire _bundle_literal_expr_172: Ty34
+                                        wire _bundle_literal_expr_173: Ty33
+                                        connect _bundle_literal_expr_173.prefix_pad, _match_arm_value_156.alu_common.common.prefix_pad
+                                        connect _bundle_literal_expr_173.dest, _match_arm_value_132.unit_out_reg
                                         wire _array_literal_expr_50: UInt<6>[3]
                                         wire _array_literal_expr_51: UInt<6>[2]
-                                        wire _cast_bundle_to_bits_expr_57: Ty57
-                                        connect _cast_bundle_to_bits_expr_57.unit_num, rename_1_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_57.unit_out_reg, rename_1_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_57: Ty47
+                                        connect _cast_bundle_to_bits_expr_57.unit_num, renamed_src_reg_1_0_2.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_57.unit_out_reg, renamed_src_reg_1_0_2.unit_out_reg.value
                                         wire _cast_to_bits_expr_57: UInt<6>
                                         connect _cast_to_bits_expr_57, cat(_cast_bundle_to_bits_expr_57.unit_out_reg, _cast_bundle_to_bits_expr_57.unit_num)
                                         connect _array_literal_expr_51[0], _cast_to_bits_expr_57
-                                        wire _cast_bundle_to_bits_expr_58: Ty57
-                                        connect _cast_bundle_to_bits_expr_58.unit_num, rename_1_src_1.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_58.unit_out_reg, rename_1_src_1.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_58: Ty47
+                                        connect _cast_bundle_to_bits_expr_58.unit_num, renamed_src_reg_1_1_2.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_58.unit_out_reg, renamed_src_reg_1_1_2.unit_out_reg.value
                                         wire _cast_to_bits_expr_58: UInt<6>
                                         connect _cast_to_bits_expr_58, cat(_cast_bundle_to_bits_expr_58.unit_out_reg, _cast_bundle_to_bits_expr_58.unit_num)
                                         connect _array_literal_expr_51[1], _cast_to_bits_expr_58
                                         connect _array_literal_expr_50[0], _array_literal_expr_51[0]
                                         wire _array_literal_expr_52: UInt<6>[2]
-                                        wire _cast_bundle_to_bits_expr_59: Ty57
-                                        connect _cast_bundle_to_bits_expr_59.unit_num, rename_1_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_59.unit_out_reg, rename_1_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_59: Ty47
+                                        connect _cast_bundle_to_bits_expr_59.unit_num, renamed_src_reg_1_0_2.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_59.unit_out_reg, renamed_src_reg_1_0_2.unit_out_reg.value
                                         wire _cast_to_bits_expr_59: UInt<6>
                                         connect _cast_to_bits_expr_59, cat(_cast_bundle_to_bits_expr_59.unit_out_reg, _cast_bundle_to_bits_expr_59.unit_num)
                                         connect _array_literal_expr_52[0], _cast_to_bits_expr_59
-                                        wire _cast_bundle_to_bits_expr_60: Ty57
-                                        connect _cast_bundle_to_bits_expr_60.unit_num, rename_1_src_1.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_60.unit_out_reg, rename_1_src_1.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_60: Ty47
+                                        connect _cast_bundle_to_bits_expr_60.unit_num, renamed_src_reg_1_1_2.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_60.unit_out_reg, renamed_src_reg_1_1_2.unit_out_reg.value
                                         wire _cast_to_bits_expr_60: UInt<6>
                                         connect _cast_to_bits_expr_60, cat(_cast_bundle_to_bits_expr_60.unit_out_reg, _cast_bundle_to_bits_expr_60.unit_num)
                                         connect _array_literal_expr_52[1], _cast_to_bits_expr_60
                                         connect _array_literal_expr_50[1], _array_literal_expr_52[1]
-                                        wire _bundle_literal_expr_174: Ty60
-                                        connect _bundle_literal_expr_174.imm_low, _match_arm_value_130.alu_common.common.imm_low
+                                        wire _bundle_literal_expr_174: Ty50
+                                        connect _bundle_literal_expr_174.imm_low, _match_arm_value_156.alu_common.common.imm_low
                                         wire _array_literal_expr_53: UInt<8>[1]
-                                        connect _array_literal_expr_53[0], _match_arm_value_130.alu_common.common.src[2]
+                                        connect _array_literal_expr_53[0], _match_arm_value_156.alu_common.common.src[2]
                                         connect _bundle_literal_expr_174.reversed_src, _array_literal_expr_53
-                                        connect _bundle_literal_expr_174.imm_sign, _match_arm_value_130.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_61: Ty61
+                                        connect _bundle_literal_expr_174.imm_sign, _match_arm_value_156.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_61: Ty51
                                         connect _cast_bundle_to_bits_expr_61.imm_low, _bundle_literal_expr_174.imm_low
                                         connect _cast_bundle_to_bits_expr_61.reversed_src, _bundle_literal_expr_174.reversed_src[0]
                                         connect _cast_bundle_to_bits_expr_61.imm_sign, asUInt(_bundle_literal_expr_174.imm_sign)
                                         wire _cast_to_bits_expr_61: UInt<34>
                                         connect _cast_to_bits_expr_61, cat(_cast_bundle_to_bits_expr_61.imm_sign, cat(_cast_bundle_to_bits_expr_61.reversed_src, _cast_bundle_to_bits_expr_61.imm_low))
-                                        wire _cast_bits_to_bundle_expr_7: Ty60
-                                        wire _cast_bits_to_bundle_expr_flattened_7: Ty61
+                                        wire _cast_bits_to_bundle_expr_7: Ty50
+                                        wire _cast_bits_to_bundle_expr_flattened_7: Ty51
                                         connect _cast_bits_to_bundle_expr_flattened_7.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_61)), 24, 0)
                                         connect _cast_bits_to_bundle_expr_7.imm_low, _cast_bits_to_bundle_expr_flattened_7.imm_low
                                         connect _cast_bits_to_bundle_expr_flattened_7.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_61)), 32, 25)
@@ -2476,26 +2314,26 @@ circuit reg_alloc:
                                         connect _cast_bits_to_bundle_expr_7.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_7.imm_sign)
                                         connect _array_literal_expr_50[2], tail(_cast_bits_to_bundle_expr_7.reversed_src[0], 2)
                                         connect _bundle_literal_expr_173.src, _array_literal_expr_50
-                                        wire _bundle_literal_expr_175: Ty60
-                                        connect _bundle_literal_expr_175.imm_low, _match_arm_value_130.alu_common.common.imm_low
+                                        wire _bundle_literal_expr_175: Ty50
+                                        connect _bundle_literal_expr_175.imm_low, _match_arm_value_156.alu_common.common.imm_low
                                         wire _array_literal_expr_54: UInt<8>[1]
-                                        connect _array_literal_expr_54[0], _match_arm_value_130.alu_common.common.src[2]
+                                        connect _array_literal_expr_54[0], _match_arm_value_156.alu_common.common.src[2]
                                         connect _bundle_literal_expr_175.reversed_src, _array_literal_expr_54
-                                        connect _bundle_literal_expr_175.imm_sign, _match_arm_value_130.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_62: Ty61
+                                        connect _bundle_literal_expr_175.imm_sign, _match_arm_value_156.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_62: Ty51
                                         connect _cast_bundle_to_bits_expr_62.imm_low, _bundle_literal_expr_175.imm_low
                                         connect _cast_bundle_to_bits_expr_62.reversed_src, _bundle_literal_expr_175.reversed_src[0]
                                         connect _cast_bundle_to_bits_expr_62.imm_sign, asUInt(_bundle_literal_expr_175.imm_sign)
                                         wire _cast_to_bits_expr_62: UInt<34>
                                         connect _cast_to_bits_expr_62, cat(_cast_bundle_to_bits_expr_62.imm_sign, cat(_cast_bundle_to_bits_expr_62.reversed_src, _cast_bundle_to_bits_expr_62.imm_low))
                                         connect _bundle_literal_expr_173.imm_low, bits(asSInt(_cast_to_bits_expr_62), 24, 0)
-                                        wire _bundle_literal_expr_176: Ty60
-                                        connect _bundle_literal_expr_176.imm_low, _match_arm_value_130.alu_common.common.imm_low
+                                        wire _bundle_literal_expr_176: Ty50
+                                        connect _bundle_literal_expr_176.imm_low, _match_arm_value_156.alu_common.common.imm_low
                                         wire _array_literal_expr_55: UInt<8>[1]
-                                        connect _array_literal_expr_55[0], _match_arm_value_130.alu_common.common.src[2]
+                                        connect _array_literal_expr_55[0], _match_arm_value_156.alu_common.common.src[2]
                                         connect _bundle_literal_expr_176.reversed_src, _array_literal_expr_55
-                                        connect _bundle_literal_expr_176.imm_sign, _match_arm_value_130.alu_common.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_63: Ty61
+                                        connect _bundle_literal_expr_176.imm_sign, _match_arm_value_156.alu_common.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_63: Ty51
                                         connect _cast_bundle_to_bits_expr_63.imm_low, _bundle_literal_expr_176.imm_low
                                         connect _cast_bundle_to_bits_expr_63.reversed_src, _bundle_literal_expr_176.reversed_src[0]
                                         connect _cast_bundle_to_bits_expr_63.imm_sign, asUInt(_bundle_literal_expr_176.imm_sign)
@@ -2506,36 +2344,36 @@ circuit reg_alloc:
                                         invalidate _bundle_literal_expr_177
                                         connect _bundle_literal_expr_173._phantom, _bundle_literal_expr_177
                                         connect _bundle_literal_expr_172.common, _bundle_literal_expr_173
-                                        connect _bundle_literal_expr_172.output_integer_mode, _match_arm_value_130.alu_common.output_integer_mode
+                                        connect _bundle_literal_expr_172.output_integer_mode, _match_arm_value_156.alu_common.output_integer_mode
                                         connect _bundle_literal_expr_171.alu_common, _bundle_literal_expr_172
-                                        connect _bundle_literal_expr_171.lut, _match_arm_value_130.lut
-                                        connect mapped_regs_5, {|AddSub: Ty44, AddSubI: Ty44, Logical: Ty45|}(Logical, _bundle_literal_expr_171) @[instruction.rs 477:1]
-                                connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(AluBranch, mapped_regs_5) @[unit.rs 127:1]
-                            L2RegisterFile(_match_arm_value_131):
-                                wire mapped_regs_6: Ty49 @[instruction.rs 504:1]
-                                match _match_arm_value_131: @[instruction.rs 504:1]
-                                    ReadL2Reg(_match_arm_value_132):
-                                        wire _bundle_literal_expr_178: Ty48
-                                        wire _bundle_literal_expr_179: Ty47
-                                        connect _bundle_literal_expr_179.prefix_pad, _match_arm_value_132.common.prefix_pad
-                                        connect _bundle_literal_expr_179.dest, _match_arm_value_116.unit_out_reg
+                                        connect _bundle_literal_expr_171.lut, _match_arm_value_156.lut
+                                        connect mapped_regs_5, {|AddSub: Ty35, AddSubI: Ty35, Logical: Ty36|}(Logical, _bundle_literal_expr_171) @[instruction.rs 477:1]
+                                connect mapped_regs_4, {|AluBranch: Ty37, L2RegisterFile: Ty40, LoadStore: Ty41|}(AluBranch, mapped_regs_5) @[unit.rs 127:1]
+                            L2RegisterFile(_match_arm_value_161):
+                                wire mapped_regs_6: Ty40 @[instruction.rs 504:1]
+                                match _match_arm_value_161: @[instruction.rs 504:1]
+                                    ReadL2Reg(_match_arm_value_162):
+                                        wire _bundle_literal_expr_178: Ty39
+                                        wire _bundle_literal_expr_179: Ty38
+                                        connect _bundle_literal_expr_179.prefix_pad, _match_arm_value_162.common.prefix_pad
+                                        connect _bundle_literal_expr_179.dest, _match_arm_value_132.unit_out_reg
                                         wire _array_literal_expr_56: UInt<6>[3]
                                         connect _array_literal_expr_56[0], pad(UInt<0>(0h0), 6)
                                         connect _array_literal_expr_56[1], pad(UInt<0>(0h0), 6)
-                                        wire _bundle_literal_expr_180: Ty60
-                                        connect _bundle_literal_expr_180.imm_low, _match_arm_value_132.common.imm_low
+                                        wire _bundle_literal_expr_180: Ty50
+                                        connect _bundle_literal_expr_180.imm_low, _match_arm_value_162.common.imm_low
                                         wire _array_literal_expr_57: UInt<8>[1]
-                                        connect _array_literal_expr_57[0], _match_arm_value_132.common.src[2]
+                                        connect _array_literal_expr_57[0], _match_arm_value_162.common.src[2]
                                         connect _bundle_literal_expr_180.reversed_src, _array_literal_expr_57
-                                        connect _bundle_literal_expr_180.imm_sign, _match_arm_value_132.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_64: Ty61
+                                        connect _bundle_literal_expr_180.imm_sign, _match_arm_value_162.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_64: Ty51
                                         connect _cast_bundle_to_bits_expr_64.imm_low, _bundle_literal_expr_180.imm_low
                                         connect _cast_bundle_to_bits_expr_64.reversed_src, _bundle_literal_expr_180.reversed_src[0]
                                         connect _cast_bundle_to_bits_expr_64.imm_sign, asUInt(_bundle_literal_expr_180.imm_sign)
                                         wire _cast_to_bits_expr_64: UInt<34>
                                         connect _cast_to_bits_expr_64, cat(_cast_bundle_to_bits_expr_64.imm_sign, cat(_cast_bundle_to_bits_expr_64.reversed_src, _cast_bundle_to_bits_expr_64.imm_low))
-                                        wire _cast_bits_to_bundle_expr_8: Ty60
-                                        wire _cast_bits_to_bundle_expr_flattened_8: Ty61
+                                        wire _cast_bits_to_bundle_expr_8: Ty50
+                                        wire _cast_bits_to_bundle_expr_flattened_8: Ty51
                                         connect _cast_bits_to_bundle_expr_flattened_8.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_64)), 24, 0)
                                         connect _cast_bits_to_bundle_expr_8.imm_low, _cast_bits_to_bundle_expr_flattened_8.imm_low
                                         connect _cast_bits_to_bundle_expr_flattened_8.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_64)), 32, 25)
@@ -2548,26 +2386,26 @@ circuit reg_alloc:
                                         connect _cast_bits_to_bundle_expr_8.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_8.imm_sign)
                                         connect _array_literal_expr_56[2], tail(_cast_bits_to_bundle_expr_8.reversed_src[0], 2)
                                         connect _bundle_literal_expr_179.src, _array_literal_expr_56
-                                        wire _bundle_literal_expr_181: Ty60
-                                        connect _bundle_literal_expr_181.imm_low, _match_arm_value_132.common.imm_low
+                                        wire _bundle_literal_expr_181: Ty50
+                                        connect _bundle_literal_expr_181.imm_low, _match_arm_value_162.common.imm_low
                                         wire _array_literal_expr_58: UInt<8>[1]
-                                        connect _array_literal_expr_58[0], _match_arm_value_132.common.src[2]
+                                        connect _array_literal_expr_58[0], _match_arm_value_162.common.src[2]
                                         connect _bundle_literal_expr_181.reversed_src, _array_literal_expr_58
-                                        connect _bundle_literal_expr_181.imm_sign, _match_arm_value_132.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_65: Ty61
+                                        connect _bundle_literal_expr_181.imm_sign, _match_arm_value_162.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_65: Ty51
                                         connect _cast_bundle_to_bits_expr_65.imm_low, _bundle_literal_expr_181.imm_low
                                         connect _cast_bundle_to_bits_expr_65.reversed_src, _bundle_literal_expr_181.reversed_src[0]
                                         connect _cast_bundle_to_bits_expr_65.imm_sign, asUInt(_bundle_literal_expr_181.imm_sign)
                                         wire _cast_to_bits_expr_65: UInt<34>
                                         connect _cast_to_bits_expr_65, cat(_cast_bundle_to_bits_expr_65.imm_sign, cat(_cast_bundle_to_bits_expr_65.reversed_src, _cast_bundle_to_bits_expr_65.imm_low))
                                         connect _bundle_literal_expr_179.imm_low, bits(asSInt(_cast_to_bits_expr_65), 24, 0)
-                                        wire _bundle_literal_expr_182: Ty60
-                                        connect _bundle_literal_expr_182.imm_low, _match_arm_value_132.common.imm_low
+                                        wire _bundle_literal_expr_182: Ty50
+                                        connect _bundle_literal_expr_182.imm_low, _match_arm_value_162.common.imm_low
                                         wire _array_literal_expr_59: UInt<8>[1]
-                                        connect _array_literal_expr_59[0], _match_arm_value_132.common.src[2]
+                                        connect _array_literal_expr_59[0], _match_arm_value_162.common.src[2]
                                         connect _bundle_literal_expr_182.reversed_src, _array_literal_expr_59
-                                        connect _bundle_literal_expr_182.imm_sign, _match_arm_value_132.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_66: Ty61
+                                        connect _bundle_literal_expr_182.imm_sign, _match_arm_value_162.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_66: Ty51
                                         connect _cast_bundle_to_bits_expr_66.imm_low, _bundle_literal_expr_182.imm_low
                                         connect _cast_bundle_to_bits_expr_66.reversed_src, _bundle_literal_expr_182.reversed_src[0]
                                         connect _cast_bundle_to_bits_expr_66.imm_sign, asUInt(_bundle_literal_expr_182.imm_sign)
@@ -2578,39 +2416,59 @@ circuit reg_alloc:
                                         invalidate _bundle_literal_expr_183
                                         connect _bundle_literal_expr_179._phantom, _bundle_literal_expr_183
                                         connect _bundle_literal_expr_178.common, _bundle_literal_expr_179
-                                        connect mapped_regs_6, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(ReadL2Reg, _bundle_literal_expr_178) @[instruction.rs 504:1]
-                                    WriteL2Reg(_match_arm_value_133):
+                                        connect mapped_regs_6, {|ReadL2Reg: Ty39, WriteL2Reg: Ty39|}(ReadL2Reg, _bundle_literal_expr_178) @[instruction.rs 504:1]
+                                    WriteL2Reg(_match_arm_value_163):
+                                        wire renamed_src_reg_1_0_3: Ty25 @[reg_alloc.rs 178:33]
                                         wire _bundle_literal_expr_184: Ty1
-                                        connect _bundle_literal_expr_184.value, _match_arm_value_133.common.src[0]
-                                        connect rename_1_src_0.addr, _bundle_literal_expr_184 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_185: Ty48
-                                        wire _bundle_literal_expr_186: Ty47
-                                        connect _bundle_literal_expr_186.prefix_pad, _match_arm_value_133.common.prefix_pad
-                                        connect _bundle_literal_expr_186.dest, _match_arm_value_116.unit_out_reg
+                                        connect _bundle_literal_expr_184.value, _match_arm_value_163.common.src[0]
+                                        connect rename_table_normal_1_src_0.addr, _bundle_literal_expr_184 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_185: Ty1
+                                        connect _bundle_literal_expr_185.value, _match_arm_value_163.common.src[0]
+                                        connect rename_table_special_1_src_0.addr, _bundle_literal_expr_185 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_1_src_0.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_1_src_0.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_186: Ty25
+                                                        wire _bundle_literal_expr_187: Ty23
+                                                        connect _bundle_literal_expr_187.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_186.unit_num, _bundle_literal_expr_187
+                                                        wire _bundle_literal_expr_188: Ty24
+                                                        connect _bundle_literal_expr_188.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_186.unit_out_reg, _bundle_literal_expr_188
+                                                        connect renamed_src_reg_1_0_3, _bundle_literal_expr_186 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_164):
+                                                        connect renamed_src_reg_1_0_3, _match_arm_value_164 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_165):
+                                                connect renamed_src_reg_1_0_3, _match_arm_value_165 @[reg_alloc.rs 185:33]
+                                        wire _bundle_literal_expr_189: Ty39
+                                        wire _bundle_literal_expr_190: Ty38
+                                        connect _bundle_literal_expr_190.prefix_pad, _match_arm_value_163.common.prefix_pad
+                                        connect _bundle_literal_expr_190.dest, _match_arm_value_132.unit_out_reg
                                         wire _array_literal_expr_60: UInt<6>[3]
                                         wire _array_literal_expr_61: UInt<6>[1]
-                                        wire _cast_bundle_to_bits_expr_67: Ty57
-                                        connect _cast_bundle_to_bits_expr_67.unit_num, rename_1_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_67.unit_out_reg, rename_1_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_67: Ty47
+                                        connect _cast_bundle_to_bits_expr_67.unit_num, renamed_src_reg_1_0_3.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_67.unit_out_reg, renamed_src_reg_1_0_3.unit_out_reg.value
                                         wire _cast_to_bits_expr_67: UInt<6>
                                         connect _cast_to_bits_expr_67, cat(_cast_bundle_to_bits_expr_67.unit_out_reg, _cast_bundle_to_bits_expr_67.unit_num)
                                         connect _array_literal_expr_61[0], _cast_to_bits_expr_67
                                         connect _array_literal_expr_60[0], _array_literal_expr_61[0]
                                         connect _array_literal_expr_60[1], pad(UInt<0>(0h0), 6)
-                                        wire _bundle_literal_expr_187: Ty60
-                                        connect _bundle_literal_expr_187.imm_low, _match_arm_value_133.common.imm_low
+                                        wire _bundle_literal_expr_191: Ty50
+                                        connect _bundle_literal_expr_191.imm_low, _match_arm_value_163.common.imm_low
                                         wire _array_literal_expr_62: UInt<8>[1]
-                                        connect _array_literal_expr_62[0], _match_arm_value_133.common.src[2]
-                                        connect _bundle_literal_expr_187.reversed_src, _array_literal_expr_62
-                                        connect _bundle_literal_expr_187.imm_sign, _match_arm_value_133.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_68: Ty61
-                                        connect _cast_bundle_to_bits_expr_68.imm_low, _bundle_literal_expr_187.imm_low
-                                        connect _cast_bundle_to_bits_expr_68.reversed_src, _bundle_literal_expr_187.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_68.imm_sign, asUInt(_bundle_literal_expr_187.imm_sign)
+                                        connect _array_literal_expr_62[0], _match_arm_value_163.common.src[2]
+                                        connect _bundle_literal_expr_191.reversed_src, _array_literal_expr_62
+                                        connect _bundle_literal_expr_191.imm_sign, _match_arm_value_163.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_68: Ty51
+                                        connect _cast_bundle_to_bits_expr_68.imm_low, _bundle_literal_expr_191.imm_low
+                                        connect _cast_bundle_to_bits_expr_68.reversed_src, _bundle_literal_expr_191.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_68.imm_sign, asUInt(_bundle_literal_expr_191.imm_sign)
                                         wire _cast_to_bits_expr_68: UInt<34>
                                         connect _cast_to_bits_expr_68, cat(_cast_bundle_to_bits_expr_68.imm_sign, cat(_cast_bundle_to_bits_expr_68.reversed_src, _cast_bundle_to_bits_expr_68.imm_low))
-                                        wire _cast_bits_to_bundle_expr_9: Ty60
-                                        wire _cast_bits_to_bundle_expr_flattened_9: Ty61
+                                        wire _cast_bits_to_bundle_expr_9: Ty50
+                                        wire _cast_bits_to_bundle_expr_flattened_9: Ty51
                                         connect _cast_bits_to_bundle_expr_flattened_9.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_68)), 24, 0)
                                         connect _cast_bits_to_bundle_expr_9.imm_low, _cast_bits_to_bundle_expr_flattened_9.imm_low
                                         connect _cast_bits_to_bundle_expr_flattened_9.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_68)), 32, 25)
@@ -2622,63 +2480,63 @@ circuit reg_alloc:
                                         connect _cast_bits_to_bundle_expr_flattened_9.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_68)), 33, 33)
                                         connect _cast_bits_to_bundle_expr_9.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_9.imm_sign)
                                         connect _array_literal_expr_60[2], tail(_cast_bits_to_bundle_expr_9.reversed_src[0], 2)
-                                        connect _bundle_literal_expr_186.src, _array_literal_expr_60
-                                        wire _bundle_literal_expr_188: Ty60
-                                        connect _bundle_literal_expr_188.imm_low, _match_arm_value_133.common.imm_low
+                                        connect _bundle_literal_expr_190.src, _array_literal_expr_60
+                                        wire _bundle_literal_expr_192: Ty50
+                                        connect _bundle_literal_expr_192.imm_low, _match_arm_value_163.common.imm_low
                                         wire _array_literal_expr_63: UInt<8>[1]
-                                        connect _array_literal_expr_63[0], _match_arm_value_133.common.src[2]
-                                        connect _bundle_literal_expr_188.reversed_src, _array_literal_expr_63
-                                        connect _bundle_literal_expr_188.imm_sign, _match_arm_value_133.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_69: Ty61
-                                        connect _cast_bundle_to_bits_expr_69.imm_low, _bundle_literal_expr_188.imm_low
-                                        connect _cast_bundle_to_bits_expr_69.reversed_src, _bundle_literal_expr_188.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_69.imm_sign, asUInt(_bundle_literal_expr_188.imm_sign)
+                                        connect _array_literal_expr_63[0], _match_arm_value_163.common.src[2]
+                                        connect _bundle_literal_expr_192.reversed_src, _array_literal_expr_63
+                                        connect _bundle_literal_expr_192.imm_sign, _match_arm_value_163.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_69: Ty51
+                                        connect _cast_bundle_to_bits_expr_69.imm_low, _bundle_literal_expr_192.imm_low
+                                        connect _cast_bundle_to_bits_expr_69.reversed_src, _bundle_literal_expr_192.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_69.imm_sign, asUInt(_bundle_literal_expr_192.imm_sign)
                                         wire _cast_to_bits_expr_69: UInt<34>
                                         connect _cast_to_bits_expr_69, cat(_cast_bundle_to_bits_expr_69.imm_sign, cat(_cast_bundle_to_bits_expr_69.reversed_src, _cast_bundle_to_bits_expr_69.imm_low))
-                                        connect _bundle_literal_expr_186.imm_low, bits(asSInt(_cast_to_bits_expr_69), 24, 0)
-                                        wire _bundle_literal_expr_189: Ty60
-                                        connect _bundle_literal_expr_189.imm_low, _match_arm_value_133.common.imm_low
+                                        connect _bundle_literal_expr_190.imm_low, bits(asSInt(_cast_to_bits_expr_69), 24, 0)
+                                        wire _bundle_literal_expr_193: Ty50
+                                        connect _bundle_literal_expr_193.imm_low, _match_arm_value_163.common.imm_low
                                         wire _array_literal_expr_64: UInt<8>[1]
-                                        connect _array_literal_expr_64[0], _match_arm_value_133.common.src[2]
-                                        connect _bundle_literal_expr_189.reversed_src, _array_literal_expr_64
-                                        connect _bundle_literal_expr_189.imm_sign, _match_arm_value_133.common.imm_sign
-                                        wire _cast_bundle_to_bits_expr_70: Ty61
-                                        connect _cast_bundle_to_bits_expr_70.imm_low, _bundle_literal_expr_189.imm_low
-                                        connect _cast_bundle_to_bits_expr_70.reversed_src, _bundle_literal_expr_189.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_70.imm_sign, asUInt(_bundle_literal_expr_189.imm_sign)
+                                        connect _array_literal_expr_64[0], _match_arm_value_163.common.src[2]
+                                        connect _bundle_literal_expr_193.reversed_src, _array_literal_expr_64
+                                        connect _bundle_literal_expr_193.imm_sign, _match_arm_value_163.common.imm_sign
+                                        wire _cast_bundle_to_bits_expr_70: Ty51
+                                        connect _cast_bundle_to_bits_expr_70.imm_low, _bundle_literal_expr_193.imm_low
+                                        connect _cast_bundle_to_bits_expr_70.reversed_src, _bundle_literal_expr_193.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_70.imm_sign, asUInt(_bundle_literal_expr_193.imm_sign)
                                         wire _cast_to_bits_expr_70: UInt<34>
                                         connect _cast_to_bits_expr_70, cat(_cast_bundle_to_bits_expr_70.imm_sign, cat(_cast_bundle_to_bits_expr_70.reversed_src, _cast_bundle_to_bits_expr_70.imm_low))
-                                        connect _bundle_literal_expr_186.imm_sign, shr(asSInt(_cast_to_bits_expr_70), 33)
-                                        wire _bundle_literal_expr_190: Ty2
-                                        invalidate _bundle_literal_expr_190
-                                        connect _bundle_literal_expr_186._phantom, _bundle_literal_expr_190
-                                        connect _bundle_literal_expr_185.common, _bundle_literal_expr_186
-                                        connect mapped_regs_6, {|ReadL2Reg: Ty48, WriteL2Reg: Ty48|}(WriteL2Reg, _bundle_literal_expr_185) @[instruction.rs 504:1]
-                                connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(L2RegisterFile, mapped_regs_6) @[unit.rs 127:1]
-                            LoadStore(_match_arm_value_134):
-                                wire mapped_regs_7: Ty50 @[instruction.rs 539:1]
-                                match _match_arm_value_134: @[instruction.rs 539:1]
-                                    Load(_match_arm_value_135):
-                                        wire _bundle_literal_expr_191: Ty47
-                                        connect _bundle_literal_expr_191.prefix_pad, _match_arm_value_135.prefix_pad
-                                        connect _bundle_literal_expr_191.dest, _match_arm_value_116.unit_out_reg
+                                        connect _bundle_literal_expr_190.imm_sign, shr(asSInt(_cast_to_bits_expr_70), 33)
+                                        wire _bundle_literal_expr_194: Ty2
+                                        invalidate _bundle_literal_expr_194
+                                        connect _bundle_literal_expr_190._phantom, _bundle_literal_expr_194
+                                        connect _bundle_literal_expr_189.common, _bundle_literal_expr_190
+                                        connect mapped_regs_6, {|ReadL2Reg: Ty39, WriteL2Reg: Ty39|}(WriteL2Reg, _bundle_literal_expr_189) @[instruction.rs 504:1]
+                                connect mapped_regs_4, {|AluBranch: Ty37, L2RegisterFile: Ty40, LoadStore: Ty41|}(L2RegisterFile, mapped_regs_6) @[unit.rs 127:1]
+                            LoadStore(_match_arm_value_166):
+                                wire mapped_regs_7: Ty41 @[instruction.rs 539:1]
+                                match _match_arm_value_166: @[instruction.rs 539:1]
+                                    Load(_match_arm_value_167):
+                                        wire _bundle_literal_expr_195: Ty38
+                                        connect _bundle_literal_expr_195.prefix_pad, _match_arm_value_167.prefix_pad
+                                        connect _bundle_literal_expr_195.dest, _match_arm_value_132.unit_out_reg
                                         wire _array_literal_expr_65: UInt<6>[3]
                                         connect _array_literal_expr_65[0], pad(UInt<0>(0h0), 6)
                                         connect _array_literal_expr_65[1], pad(UInt<0>(0h0), 6)
-                                        wire _bundle_literal_expr_192: Ty60
-                                        connect _bundle_literal_expr_192.imm_low, _match_arm_value_135.imm_low
+                                        wire _bundle_literal_expr_196: Ty50
+                                        connect _bundle_literal_expr_196.imm_low, _match_arm_value_167.imm_low
                                         wire _array_literal_expr_66: UInt<8>[1]
-                                        connect _array_literal_expr_66[0], _match_arm_value_135.src[2]
-                                        connect _bundle_literal_expr_192.reversed_src, _array_literal_expr_66
-                                        connect _bundle_literal_expr_192.imm_sign, _match_arm_value_135.imm_sign
-                                        wire _cast_bundle_to_bits_expr_71: Ty61
-                                        connect _cast_bundle_to_bits_expr_71.imm_low, _bundle_literal_expr_192.imm_low
-                                        connect _cast_bundle_to_bits_expr_71.reversed_src, _bundle_literal_expr_192.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_71.imm_sign, asUInt(_bundle_literal_expr_192.imm_sign)
+                                        connect _array_literal_expr_66[0], _match_arm_value_167.src[2]
+                                        connect _bundle_literal_expr_196.reversed_src, _array_literal_expr_66
+                                        connect _bundle_literal_expr_196.imm_sign, _match_arm_value_167.imm_sign
+                                        wire _cast_bundle_to_bits_expr_71: Ty51
+                                        connect _cast_bundle_to_bits_expr_71.imm_low, _bundle_literal_expr_196.imm_low
+                                        connect _cast_bundle_to_bits_expr_71.reversed_src, _bundle_literal_expr_196.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_71.imm_sign, asUInt(_bundle_literal_expr_196.imm_sign)
                                         wire _cast_to_bits_expr_71: UInt<34>
                                         connect _cast_to_bits_expr_71, cat(_cast_bundle_to_bits_expr_71.imm_sign, cat(_cast_bundle_to_bits_expr_71.reversed_src, _cast_bundle_to_bits_expr_71.imm_low))
-                                        wire _cast_bits_to_bundle_expr_10: Ty60
-                                        wire _cast_bits_to_bundle_expr_flattened_10: Ty61
+                                        wire _cast_bits_to_bundle_expr_10: Ty50
+                                        wire _cast_bits_to_bundle_expr_flattened_10: Ty51
                                         connect _cast_bits_to_bundle_expr_flattened_10.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_71)), 24, 0)
                                         connect _cast_bits_to_bundle_expr_10.imm_low, _cast_bits_to_bundle_expr_flattened_10.imm_low
                                         connect _cast_bits_to_bundle_expr_flattened_10.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_71)), 32, 25)
@@ -2690,68 +2548,88 @@ circuit reg_alloc:
                                         connect _cast_bits_to_bundle_expr_flattened_10.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_71)), 33, 33)
                                         connect _cast_bits_to_bundle_expr_10.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_10.imm_sign)
                                         connect _array_literal_expr_65[2], tail(_cast_bits_to_bundle_expr_10.reversed_src[0], 2)
-                                        connect _bundle_literal_expr_191.src, _array_literal_expr_65
-                                        wire _bundle_literal_expr_193: Ty60
-                                        connect _bundle_literal_expr_193.imm_low, _match_arm_value_135.imm_low
+                                        connect _bundle_literal_expr_195.src, _array_literal_expr_65
+                                        wire _bundle_literal_expr_197: Ty50
+                                        connect _bundle_literal_expr_197.imm_low, _match_arm_value_167.imm_low
                                         wire _array_literal_expr_67: UInt<8>[1]
-                                        connect _array_literal_expr_67[0], _match_arm_value_135.src[2]
-                                        connect _bundle_literal_expr_193.reversed_src, _array_literal_expr_67
-                                        connect _bundle_literal_expr_193.imm_sign, _match_arm_value_135.imm_sign
-                                        wire _cast_bundle_to_bits_expr_72: Ty61
-                                        connect _cast_bundle_to_bits_expr_72.imm_low, _bundle_literal_expr_193.imm_low
-                                        connect _cast_bundle_to_bits_expr_72.reversed_src, _bundle_literal_expr_193.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_72.imm_sign, asUInt(_bundle_literal_expr_193.imm_sign)
+                                        connect _array_literal_expr_67[0], _match_arm_value_167.src[2]
+                                        connect _bundle_literal_expr_197.reversed_src, _array_literal_expr_67
+                                        connect _bundle_literal_expr_197.imm_sign, _match_arm_value_167.imm_sign
+                                        wire _cast_bundle_to_bits_expr_72: Ty51
+                                        connect _cast_bundle_to_bits_expr_72.imm_low, _bundle_literal_expr_197.imm_low
+                                        connect _cast_bundle_to_bits_expr_72.reversed_src, _bundle_literal_expr_197.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_72.imm_sign, asUInt(_bundle_literal_expr_197.imm_sign)
                                         wire _cast_to_bits_expr_72: UInt<34>
                                         connect _cast_to_bits_expr_72, cat(_cast_bundle_to_bits_expr_72.imm_sign, cat(_cast_bundle_to_bits_expr_72.reversed_src, _cast_bundle_to_bits_expr_72.imm_low))
-                                        connect _bundle_literal_expr_191.imm_low, bits(asSInt(_cast_to_bits_expr_72), 24, 0)
-                                        wire _bundle_literal_expr_194: Ty60
-                                        connect _bundle_literal_expr_194.imm_low, _match_arm_value_135.imm_low
+                                        connect _bundle_literal_expr_195.imm_low, bits(asSInt(_cast_to_bits_expr_72), 24, 0)
+                                        wire _bundle_literal_expr_198: Ty50
+                                        connect _bundle_literal_expr_198.imm_low, _match_arm_value_167.imm_low
                                         wire _array_literal_expr_68: UInt<8>[1]
-                                        connect _array_literal_expr_68[0], _match_arm_value_135.src[2]
-                                        connect _bundle_literal_expr_194.reversed_src, _array_literal_expr_68
-                                        connect _bundle_literal_expr_194.imm_sign, _match_arm_value_135.imm_sign
-                                        wire _cast_bundle_to_bits_expr_73: Ty61
-                                        connect _cast_bundle_to_bits_expr_73.imm_low, _bundle_literal_expr_194.imm_low
-                                        connect _cast_bundle_to_bits_expr_73.reversed_src, _bundle_literal_expr_194.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_73.imm_sign, asUInt(_bundle_literal_expr_194.imm_sign)
+                                        connect _array_literal_expr_68[0], _match_arm_value_167.src[2]
+                                        connect _bundle_literal_expr_198.reversed_src, _array_literal_expr_68
+                                        connect _bundle_literal_expr_198.imm_sign, _match_arm_value_167.imm_sign
+                                        wire _cast_bundle_to_bits_expr_73: Ty51
+                                        connect _cast_bundle_to_bits_expr_73.imm_low, _bundle_literal_expr_198.imm_low
+                                        connect _cast_bundle_to_bits_expr_73.reversed_src, _bundle_literal_expr_198.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_73.imm_sign, asUInt(_bundle_literal_expr_198.imm_sign)
                                         wire _cast_to_bits_expr_73: UInt<34>
                                         connect _cast_to_bits_expr_73, cat(_cast_bundle_to_bits_expr_73.imm_sign, cat(_cast_bundle_to_bits_expr_73.reversed_src, _cast_bundle_to_bits_expr_73.imm_low))
-                                        connect _bundle_literal_expr_191.imm_sign, shr(asSInt(_cast_to_bits_expr_73), 33)
-                                        wire _bundle_literal_expr_195: Ty2
-                                        invalidate _bundle_literal_expr_195
-                                        connect _bundle_literal_expr_191._phantom, _bundle_literal_expr_195
-                                        connect mapped_regs_7, {|Load: Ty47, Store: Ty47|}(Load, _bundle_literal_expr_191) @[instruction.rs 539:1]
-                                    Store(_match_arm_value_136):
-                                        wire _bundle_literal_expr_196: Ty1
-                                        connect _bundle_literal_expr_196.value, _match_arm_value_136.src[0]
-                                        connect rename_1_src_0.addr, _bundle_literal_expr_196 @[reg_alloc.rs 205:29]
-                                        wire _bundle_literal_expr_197: Ty47
-                                        connect _bundle_literal_expr_197.prefix_pad, _match_arm_value_136.prefix_pad
-                                        connect _bundle_literal_expr_197.dest, _match_arm_value_116.unit_out_reg
+                                        connect _bundle_literal_expr_195.imm_sign, shr(asSInt(_cast_to_bits_expr_73), 33)
+                                        wire _bundle_literal_expr_199: Ty2
+                                        invalidate _bundle_literal_expr_199
+                                        connect _bundle_literal_expr_195._phantom, _bundle_literal_expr_199
+                                        connect mapped_regs_7, {|Load: Ty38, Store: Ty38|}(Load, _bundle_literal_expr_195) @[instruction.rs 539:1]
+                                    Store(_match_arm_value_168):
+                                        wire renamed_src_reg_1_0_4: Ty25 @[reg_alloc.rs 178:33]
+                                        wire _bundle_literal_expr_200: Ty1
+                                        connect _bundle_literal_expr_200.value, _match_arm_value_168.src[0]
+                                        connect rename_table_normal_1_src_0.addr, _bundle_literal_expr_200 @[reg_alloc.rs 181:29]
+                                        wire _bundle_literal_expr_201: Ty1
+                                        connect _bundle_literal_expr_201.value, _match_arm_value_168.src[0]
+                                        connect rename_table_special_1_src_0.addr, _bundle_literal_expr_201 @[reg_alloc.rs 182:29]
+                                        match rename_table_normal_1_src_0.data: @[reg_alloc.rs 184:29]
+                                            HdlNone:
+                                                match rename_table_special_1_src_0.data: @[reg_alloc.rs 186:36]
+                                                    HdlNone:
+                                                        wire _bundle_literal_expr_202: Ty25
+                                                        wire _bundle_literal_expr_203: Ty23
+                                                        connect _bundle_literal_expr_203.adj_value, tail(UInt<64>(0h0), 62)
+                                                        connect _bundle_literal_expr_202.unit_num, _bundle_literal_expr_203
+                                                        wire _bundle_literal_expr_204: Ty24
+                                                        connect _bundle_literal_expr_204.value, tail(UInt<8>(0h0), 4)
+                                                        connect _bundle_literal_expr_202.unit_out_reg, _bundle_literal_expr_204
+                                                        connect renamed_src_reg_1_0_4, _bundle_literal_expr_202 @[reg_alloc.rs 191:33]
+                                                    HdlSome(_match_arm_value_169):
+                                                        connect renamed_src_reg_1_0_4, _match_arm_value_169 @[reg_alloc.rs 189:33]
+                                            HdlSome(_match_arm_value_170):
+                                                connect renamed_src_reg_1_0_4, _match_arm_value_170 @[reg_alloc.rs 185:33]
+                                        wire _bundle_literal_expr_205: Ty38
+                                        connect _bundle_literal_expr_205.prefix_pad, _match_arm_value_168.prefix_pad
+                                        connect _bundle_literal_expr_205.dest, _match_arm_value_132.unit_out_reg
                                         wire _array_literal_expr_69: UInt<6>[3]
                                         wire _array_literal_expr_70: UInt<6>[1]
-                                        wire _cast_bundle_to_bits_expr_74: Ty57
-                                        connect _cast_bundle_to_bits_expr_74.unit_num, rename_1_src_0.data.unit_num.adj_value
-                                        connect _cast_bundle_to_bits_expr_74.unit_out_reg, rename_1_src_0.data.unit_out_reg.value
+                                        wire _cast_bundle_to_bits_expr_74: Ty47
+                                        connect _cast_bundle_to_bits_expr_74.unit_num, renamed_src_reg_1_0_4.unit_num.adj_value
+                                        connect _cast_bundle_to_bits_expr_74.unit_out_reg, renamed_src_reg_1_0_4.unit_out_reg.value
                                         wire _cast_to_bits_expr_74: UInt<6>
                                         connect _cast_to_bits_expr_74, cat(_cast_bundle_to_bits_expr_74.unit_out_reg, _cast_bundle_to_bits_expr_74.unit_num)
                                         connect _array_literal_expr_70[0], _cast_to_bits_expr_74
                                         connect _array_literal_expr_69[0], _array_literal_expr_70[0]
                                         connect _array_literal_expr_69[1], pad(UInt<0>(0h0), 6)
-                                        wire _bundle_literal_expr_198: Ty60
-                                        connect _bundle_literal_expr_198.imm_low, _match_arm_value_136.imm_low
+                                        wire _bundle_literal_expr_206: Ty50
+                                        connect _bundle_literal_expr_206.imm_low, _match_arm_value_168.imm_low
                                         wire _array_literal_expr_71: UInt<8>[1]
-                                        connect _array_literal_expr_71[0], _match_arm_value_136.src[2]
-                                        connect _bundle_literal_expr_198.reversed_src, _array_literal_expr_71
-                                        connect _bundle_literal_expr_198.imm_sign, _match_arm_value_136.imm_sign
-                                        wire _cast_bundle_to_bits_expr_75: Ty61
-                                        connect _cast_bundle_to_bits_expr_75.imm_low, _bundle_literal_expr_198.imm_low
-                                        connect _cast_bundle_to_bits_expr_75.reversed_src, _bundle_literal_expr_198.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_75.imm_sign, asUInt(_bundle_literal_expr_198.imm_sign)
+                                        connect _array_literal_expr_71[0], _match_arm_value_168.src[2]
+                                        connect _bundle_literal_expr_206.reversed_src, _array_literal_expr_71
+                                        connect _bundle_literal_expr_206.imm_sign, _match_arm_value_168.imm_sign
+                                        wire _cast_bundle_to_bits_expr_75: Ty51
+                                        connect _cast_bundle_to_bits_expr_75.imm_low, _bundle_literal_expr_206.imm_low
+                                        connect _cast_bundle_to_bits_expr_75.reversed_src, _bundle_literal_expr_206.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_75.imm_sign, asUInt(_bundle_literal_expr_206.imm_sign)
                                         wire _cast_to_bits_expr_75: UInt<34>
                                         connect _cast_to_bits_expr_75, cat(_cast_bundle_to_bits_expr_75.imm_sign, cat(_cast_bundle_to_bits_expr_75.reversed_src, _cast_bundle_to_bits_expr_75.imm_low))
-                                        wire _cast_bits_to_bundle_expr_11: Ty60
-                                        wire _cast_bits_to_bundle_expr_flattened_11: Ty61
+                                        wire _cast_bits_to_bundle_expr_11: Ty50
+                                        wire _cast_bits_to_bundle_expr_flattened_11: Ty51
                                         connect _cast_bits_to_bundle_expr_flattened_11.imm_low, bits(asUInt(asSInt(_cast_to_bits_expr_75)), 24, 0)
                                         connect _cast_bits_to_bundle_expr_11.imm_low, _cast_bits_to_bundle_expr_flattened_11.imm_low
                                         connect _cast_bits_to_bundle_expr_flattened_11.reversed_src, bits(asUInt(asSInt(_cast_to_bits_expr_75)), 32, 25)
@@ -2763,352 +2641,288 @@ circuit reg_alloc:
                                         connect _cast_bits_to_bundle_expr_flattened_11.imm_sign, bits(asUInt(asSInt(_cast_to_bits_expr_75)), 33, 33)
                                         connect _cast_bits_to_bundle_expr_11.imm_sign, asSInt(_cast_bits_to_bundle_expr_flattened_11.imm_sign)
                                         connect _array_literal_expr_69[2], tail(_cast_bits_to_bundle_expr_11.reversed_src[0], 2)
-                                        connect _bundle_literal_expr_197.src, _array_literal_expr_69
-                                        wire _bundle_literal_expr_199: Ty60
-                                        connect _bundle_literal_expr_199.imm_low, _match_arm_value_136.imm_low
+                                        connect _bundle_literal_expr_205.src, _array_literal_expr_69
+                                        wire _bundle_literal_expr_207: Ty50
+                                        connect _bundle_literal_expr_207.imm_low, _match_arm_value_168.imm_low
                                         wire _array_literal_expr_72: UInt<8>[1]
-                                        connect _array_literal_expr_72[0], _match_arm_value_136.src[2]
-                                        connect _bundle_literal_expr_199.reversed_src, _array_literal_expr_72
-                                        connect _bundle_literal_expr_199.imm_sign, _match_arm_value_136.imm_sign
-                                        wire _cast_bundle_to_bits_expr_76: Ty61
-                                        connect _cast_bundle_to_bits_expr_76.imm_low, _bundle_literal_expr_199.imm_low
-                                        connect _cast_bundle_to_bits_expr_76.reversed_src, _bundle_literal_expr_199.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_76.imm_sign, asUInt(_bundle_literal_expr_199.imm_sign)
+                                        connect _array_literal_expr_72[0], _match_arm_value_168.src[2]
+                                        connect _bundle_literal_expr_207.reversed_src, _array_literal_expr_72
+                                        connect _bundle_literal_expr_207.imm_sign, _match_arm_value_168.imm_sign
+                                        wire _cast_bundle_to_bits_expr_76: Ty51
+                                        connect _cast_bundle_to_bits_expr_76.imm_low, _bundle_literal_expr_207.imm_low
+                                        connect _cast_bundle_to_bits_expr_76.reversed_src, _bundle_literal_expr_207.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_76.imm_sign, asUInt(_bundle_literal_expr_207.imm_sign)
                                         wire _cast_to_bits_expr_76: UInt<34>
                                         connect _cast_to_bits_expr_76, cat(_cast_bundle_to_bits_expr_76.imm_sign, cat(_cast_bundle_to_bits_expr_76.reversed_src, _cast_bundle_to_bits_expr_76.imm_low))
-                                        connect _bundle_literal_expr_197.imm_low, bits(asSInt(_cast_to_bits_expr_76), 24, 0)
-                                        wire _bundle_literal_expr_200: Ty60
-                                        connect _bundle_literal_expr_200.imm_low, _match_arm_value_136.imm_low
+                                        connect _bundle_literal_expr_205.imm_low, bits(asSInt(_cast_to_bits_expr_76), 24, 0)
+                                        wire _bundle_literal_expr_208: Ty50
+                                        connect _bundle_literal_expr_208.imm_low, _match_arm_value_168.imm_low
                                         wire _array_literal_expr_73: UInt<8>[1]
-                                        connect _array_literal_expr_73[0], _match_arm_value_136.src[2]
-                                        connect _bundle_literal_expr_200.reversed_src, _array_literal_expr_73
-                                        connect _bundle_literal_expr_200.imm_sign, _match_arm_value_136.imm_sign
-                                        wire _cast_bundle_to_bits_expr_77: Ty61
-                                        connect _cast_bundle_to_bits_expr_77.imm_low, _bundle_literal_expr_200.imm_low
-                                        connect _cast_bundle_to_bits_expr_77.reversed_src, _bundle_literal_expr_200.reversed_src[0]
-                                        connect _cast_bundle_to_bits_expr_77.imm_sign, asUInt(_bundle_literal_expr_200.imm_sign)
+                                        connect _array_literal_expr_73[0], _match_arm_value_168.src[2]
+                                        connect _bundle_literal_expr_208.reversed_src, _array_literal_expr_73
+                                        connect _bundle_literal_expr_208.imm_sign, _match_arm_value_168.imm_sign
+                                        wire _cast_bundle_to_bits_expr_77: Ty51
+                                        connect _cast_bundle_to_bits_expr_77.imm_low, _bundle_literal_expr_208.imm_low
+                                        connect _cast_bundle_to_bits_expr_77.reversed_src, _bundle_literal_expr_208.reversed_src[0]
+                                        connect _cast_bundle_to_bits_expr_77.imm_sign, asUInt(_bundle_literal_expr_208.imm_sign)
                                         wire _cast_to_bits_expr_77: UInt<34>
                                         connect _cast_to_bits_expr_77, cat(_cast_bundle_to_bits_expr_77.imm_sign, cat(_cast_bundle_to_bits_expr_77.reversed_src, _cast_bundle_to_bits_expr_77.imm_low))
-                                        connect _bundle_literal_expr_197.imm_sign, shr(asSInt(_cast_to_bits_expr_77), 33)
-                                        wire _bundle_literal_expr_201: Ty2
-                                        invalidate _bundle_literal_expr_201
-                                        connect _bundle_literal_expr_197._phantom, _bundle_literal_expr_201
-                                        connect mapped_regs_7, {|Load: Ty47, Store: Ty47|}(Store, _bundle_literal_expr_197) @[instruction.rs 539:1]
-                                connect mapped_regs_4, {|AluBranch: Ty46, L2RegisterFile: Ty49, LoadStore: Ty50|}(LoadStore, mapped_regs_7) @[unit.rs 127:1]
-                        connect renamed_mops[1], {|HdlNone, HdlSome: Ty51|}(HdlSome, mapped_regs_4) @[reg_alloc.rs 198:17]
-                        wire flag_reg_14: Ty1 @[instruction.rs 806:32]
-                        wire _bundle_literal_expr_202: Ty1
-                        connect _bundle_literal_expr_202.value, tail(UInt<32>(0h0), 24)
-                        connect flag_reg_14, _bundle_literal_expr_202 @[instruction.rs 807:17]
-                        match dest_reg_28.flag_regs[0]: @[instruction.rs 809:17]
-                            HdlNone:
-                                skip
-                            HdlSome(_match_arm_value_137):
-                                wire _bundle_literal_expr_203: Ty1
-                                connect _bundle_literal_expr_203.value, tail(UInt<32>(0hFE), 24)
-                                connect flag_reg_14, _bundle_literal_expr_203 @[instruction.rs 811:21]
-                        wire flag_reg_15: Ty1 @[instruction.rs 806:32]
-                        wire _bundle_literal_expr_204: Ty1
-                        connect _bundle_literal_expr_204.value, tail(UInt<32>(0h0), 24)
-                        connect flag_reg_15, _bundle_literal_expr_204 @[instruction.rs 807:17]
-                        match dest_reg_28.flag_regs[1]: @[instruction.rs 809:17]
-                            HdlNone:
-                                skip
-                            HdlSome(_match_arm_value_138):
-                                wire _bundle_literal_expr_205: Ty1
-                                connect _bundle_literal_expr_205.value, tail(UInt<32>(0hFF), 24)
-                                connect flag_reg_15, _bundle_literal_expr_205 @[instruction.rs 811:21]
-                        when and(geq(dest_reg_28.normal_regs[0].value, UInt<32>(0h1)), lt(dest_reg_28.normal_regs[0].value, UInt<32>(0hFE))): @[reg_alloc.rs 229:25]
-                            connect rename_table_normal_1_dest0.data, _match_arm_value_116 @[reg_alloc.rs 230:29]
-                            ; connect different types:
-                            ; lhs: UInt<8>
-                            ; rhs: UInt<33>
-                            connect rename_table_normal_1_dest0.addr, sub(dest_reg_28.normal_regs[0].value, UInt<32>(0h1)) @[reg_alloc.rs 234:33]
-                            connect rename_table_normal_1_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 236:29]
-                        when and(geq(dest_reg_28.normal_regs[0].value, UInt<32>(0hFE)), lt(dest_reg_28.normal_regs[0].value, UInt<32>(0h100))): @[reg_alloc.rs 229:25]
-                            connect rename_table_special_1_dest0.data, _match_arm_value_116 @[reg_alloc.rs 230:29]
-                            ; connect different types:
-                            ; lhs: UInt<1>
-                            ; rhs: UInt<33>
-                            connect rename_table_special_1_dest0.addr, sub(dest_reg_28.normal_regs[0].value, UInt<32>(0hFE)) @[reg_alloc.rs 234:33]
-                            connect rename_table_special_1_dest0.en, UInt<1>(0h1) @[reg_alloc.rs 236:29]
-                        when and(geq(dest_reg_28.normal_regs[1].value, UInt<32>(0h1)), lt(dest_reg_28.normal_regs[1].value, UInt<32>(0hFE))): @[reg_alloc.rs 229:25]
-                            connect rename_table_normal_1_dest1.data, _match_arm_value_116 @[reg_alloc.rs 230:29]
-                            ; connect different types:
-                            ; lhs: UInt<8>
-                            ; rhs: UInt<33>
-                            connect rename_table_normal_1_dest1.addr, sub(dest_reg_28.normal_regs[1].value, UInt<32>(0h1)) @[reg_alloc.rs 234:33]
-                            connect rename_table_normal_1_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 236:29]
-                        when and(geq(dest_reg_28.normal_regs[1].value, UInt<32>(0hFE)), lt(dest_reg_28.normal_regs[1].value, UInt<32>(0h100))): @[reg_alloc.rs 229:25]
-                            connect rename_table_special_1_dest1.data, _match_arm_value_116 @[reg_alloc.rs 230:29]
-                            ; connect different types:
-                            ; lhs: UInt<1>
-                            ; rhs: UInt<33>
-                            connect rename_table_special_1_dest1.addr, sub(dest_reg_28.normal_regs[1].value, UInt<32>(0hFE)) @[reg_alloc.rs 234:33]
-                            connect rename_table_special_1_dest1.en, UInt<1>(0h1) @[reg_alloc.rs 236:29]
-                        when and(geq(flag_reg_14.value, UInt<32>(0hFE)), lt(flag_reg_14.value, UInt<32>(0h100))): @[reg_alloc.rs 229:25]
-                            connect rename_table_special_1_flag0_rFE.data, _match_arm_value_116 @[reg_alloc.rs 230:29]
-                            ; connect different types:
-                            ; lhs: UInt<1>
-                            ; rhs: UInt<32>
-                            connect rename_table_special_1_flag0_rFE.addr, UInt<32>(0h0) @[reg_alloc.rs 232:33]
-                            connect rename_table_special_1_flag0_rFE.en, UInt<1>(0h1) @[reg_alloc.rs 236:29]
-                        when and(geq(flag_reg_15.value, UInt<32>(0hFE)), lt(flag_reg_15.value, UInt<32>(0h100))): @[reg_alloc.rs 229:25]
-                            connect rename_table_special_1_flag1_rFF.data, _match_arm_value_116 @[reg_alloc.rs 230:29]
-                            ; connect different types:
-                            ; lhs: UInt<1>
-                            ; rhs: UInt<32>
-                            connect rename_table_special_1_flag1_rFF.addr, UInt<32>(0h1) @[reg_alloc.rs 232:33]
-                            connect rename_table_special_1_flag1_rFF.en, UInt<1>(0h1) @[reg_alloc.rs 236:29]
-        wire selected_unit_index_leaf_1_0: Ty41 @[reg_alloc.rs 250:25]
-        connect selected_unit_index_leaf_1_0, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 253:21]
-        wire unit_index_1_0: UInt<2> @[reg_alloc.rs 259:25]
+                                        connect _bundle_literal_expr_205.imm_sign, shr(asSInt(_cast_to_bits_expr_77), 33)
+                                        wire _bundle_literal_expr_209: Ty2
+                                        invalidate _bundle_literal_expr_209
+                                        connect _bundle_literal_expr_205._phantom, _bundle_literal_expr_209
+                                        connect mapped_regs_7, {|Load: Ty38, Store: Ty38|}(Store, _bundle_literal_expr_205) @[instruction.rs 539:1]
+                                connect mapped_regs_4, {|AluBranch: Ty37, L2RegisterFile: Ty40, LoadStore: Ty41|}(LoadStore, mapped_regs_7) @[unit.rs 127:1]
+                        connect renamed_mops[1], {|HdlNone, HdlSome: Ty42|}(HdlSome, mapped_regs_4) @[reg_alloc.rs 167:17]
+        wire selected_unit_index_leaf_1_0: Ty32 @[reg_alloc.rs 209:25]
+        connect selected_unit_index_leaf_1_0, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 212:21]
+        wire unit_index_1_0: UInt<2> @[reg_alloc.rs 218:25]
         ; connect different types:
         ; lhs: UInt<2>
         ; rhs: UInt<64>
-        connect unit_index_1_0, UInt<64>(0h0) @[reg_alloc.rs 262:21]
-        when available_units[1][0]: @[reg_alloc.rs 264:21]
-            connect selected_unit_index_leaf_1_0, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_1_0) @[reg_alloc.rs 265:25]
-        wire selected_unit_index_leaf_1_1: Ty41 @[reg_alloc.rs 250:25]
-        connect selected_unit_index_leaf_1_1, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 253:21]
-        wire unit_index_1_1: UInt<2> @[reg_alloc.rs 259:25]
+        connect unit_index_1_0, UInt<64>(0h0) @[reg_alloc.rs 221:21]
+        when available_units[1][0]: @[reg_alloc.rs 223:21]
+            connect selected_unit_index_leaf_1_0, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_1_0) @[reg_alloc.rs 224:25]
+        wire selected_unit_index_leaf_1_1: Ty32 @[reg_alloc.rs 209:25]
+        connect selected_unit_index_leaf_1_1, {|HdlNone, HdlSome: UInt<2>|}(HdlNone) @[reg_alloc.rs 212:21]
+        wire unit_index_1_1: UInt<2> @[reg_alloc.rs 218:25]
         ; connect different types:
         ; lhs: UInt<2>
         ; rhs: UInt<64>
-        connect unit_index_1_1, UInt<64>(0h1) @[reg_alloc.rs 262:21]
-        when available_units[1][1]: @[reg_alloc.rs 264:21]
-            connect selected_unit_index_leaf_1_1, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_1_1) @[reg_alloc.rs 265:25]
-        wire selected_unit_index_node_1_0: Ty41 @[reg_alloc.rs 272:25]
-        connect selected_unit_index_node_1_0, selected_unit_index_leaf_1_0 @[reg_alloc.rs 276:21]
-        match selected_unit_index_leaf_1_0: @[reg_alloc.rs 278:21]
+        connect unit_index_1_1, UInt<64>(0h1) @[reg_alloc.rs 221:21]
+        when available_units[1][1]: @[reg_alloc.rs 223:21]
+            connect selected_unit_index_leaf_1_1, {|HdlNone, HdlSome: UInt<2>|}(HdlSome, unit_index_1_1) @[reg_alloc.rs 224:25]
+        wire selected_unit_index_node_1_0: Ty32 @[reg_alloc.rs 231:25]
+        connect selected_unit_index_node_1_0, selected_unit_index_leaf_1_0 @[reg_alloc.rs 235:21]
+        match selected_unit_index_leaf_1_0: @[reg_alloc.rs 237:21]
             HdlNone:
-                connect selected_unit_index_node_1_0, selected_unit_index_leaf_1_1 @[reg_alloc.rs 279:25]
-            HdlSome(_match_arm_value_139):
+                connect selected_unit_index_node_1_0, selected_unit_index_leaf_1_1 @[reg_alloc.rs 238:25]
+            HdlSome(_match_arm_value_171):
                 skip
-        connect selected_unit_indexes[1], selected_unit_index_node_1_0 @[reg_alloc.rs 242:9]
-        match selected_unit_indexes[0]: @[reg_alloc.rs 292:13]
+        connect selected_unit_indexes[1], selected_unit_index_node_1_0 @[reg_alloc.rs 201:9]
+        match selected_unit_indexes[0]: @[reg_alloc.rs 251:13]
             HdlNone:
                 skip
-            HdlSome(_match_arm_value_140):
-                connect available_units[1][_match_arm_value_140], UInt<1>(0h0) @[reg_alloc.rs 293:17]
-        wire _array_literal_expr_74: Ty53[2]
+            HdlSome(_match_arm_value_172):
+                connect available_units[1][_match_arm_value_172], UInt<1>(0h0) @[reg_alloc.rs 252:17]
+        wire _array_literal_expr_74: Ty44[2]
         connect _array_literal_expr_74[0], {|HdlNone, HdlSome: Ty25|}(HdlNone)
         connect _array_literal_expr_74[1], {|HdlNone, HdlSome: Ty25|}(HdlNone)
-        connect renamed_mops_out_reg, _array_literal_expr_74 @[reg_alloc.rs 300:5]
-        inst unit_0 of alu_branch @[reg_alloc.rs 312:13]
-        connect unit_0.cd, cd @[reg_alloc.rs 314:9]
-        inst unit_0_free_regs_tracker of unit_free_regs_tracker @[reg_alloc.rs 327:13]
-        connect unit_0_free_regs_tracker.cd, cd @[reg_alloc.rs 329:9]
-        wire _uninit_expr_12: Ty65
-        invalidate _uninit_expr_12
-        connect unit_0_free_regs_tracker.free_in[0].data, _uninit_expr_12 @[reg_alloc.rs 331:9]
-        connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 335:9]
-        connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 336:9]
-        match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 339:13]
+        connect renamed_mops_out_reg, _array_literal_expr_74 @[reg_alloc.rs 259:5]
+        inst unit_0 of alu_branch @[reg_alloc.rs 271:13]
+        connect unit_0.cd, cd @[reg_alloc.rs 273:9]
+        inst unit_0_free_regs_tracker of unit_free_regs_tracker @[reg_alloc.rs 286:13]
+        connect unit_0_free_regs_tracker.cd, cd @[reg_alloc.rs 288:9]
+        wire _uninit_expr: Ty55
+        invalidate _uninit_expr
+        connect unit_0_free_regs_tracker.free_in[0].data, _uninit_expr @[reg_alloc.rs 290:9]
+        connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 294:9]
+        connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[reg_alloc.rs 295:9]
+        match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 298:13]
             HdlNone:
-                connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 341:17]
-            HdlSome(_match_arm_value_141):
+                connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 300:17]
+            HdlSome(_match_arm_value_173):
                 skip
-        when not(unit_0.`input`.ready): @[reg_alloc.rs 344:13]
-            connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 346:17]
-        match selected_unit_indexes[0]: @[reg_alloc.rs 349:13]
+        when not(unit_0.`input`.ready): @[reg_alloc.rs 303:13]
+            connect available_units[0][0], UInt<1>(0h0) @[reg_alloc.rs 305:17]
+        match selected_unit_indexes[0]: @[reg_alloc.rs 308:13]
             HdlNone:
                 skip
-            HdlSome(_match_arm_value_142):
-                when eq(_match_arm_value_142, UInt<64>(0h0)): @[reg_alloc.rs 351:17]
-                    wire and_then_out: Ty62 @[reg_alloc.rs 355:25]
-                    connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 352:21]
-                    match renamed_mops[0]: @[reg_alloc.rs 355:25]
+            HdlSome(_match_arm_value_174):
+                when eq(_match_arm_value_174, UInt<64>(0h0)): @[reg_alloc.rs 310:17]
+                    wire and_then_out: Ty52 @[reg_alloc.rs 314:25]
+                    connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 311:21]
+                    match renamed_mops[0]: @[reg_alloc.rs 314:25]
                         HdlNone:
-                            connect and_then_out, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 355:25]
-                        HdlSome(_match_arm_value_143):
-                            wire alu_branch_mop: Ty62 @[unit.rs 127:1]
-                            connect alu_branch_mop, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 127:1]
-                            match _match_arm_value_143: @[unit.rs 127:1]
-                                AluBranch(_match_arm_value_144):
-                                    connect alu_branch_mop, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_144) @[unit.rs 127:1]
-                                L2RegisterFile(_match_arm_value_145):
+                            connect and_then_out, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[reg_alloc.rs 314:25]
+                        HdlSome(_match_arm_value_175):
+                            wire alu_branch_mop: Ty52 @[unit.rs 127:1]
+                            connect alu_branch_mop, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[unit.rs 127:1]
+                            match _match_arm_value_175: @[unit.rs 127:1]
+                                AluBranch(_match_arm_value_176):
+                                    connect alu_branch_mop, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_176) @[unit.rs 127:1]
+                                L2RegisterFile(_match_arm_value_177):
                                     skip
-                                LoadStore(_match_arm_value_146):
+                                LoadStore(_match_arm_value_178):
                                     skip
-                            connect and_then_out, alu_branch_mop @[reg_alloc.rs 355:25]
-                    match and_then_out: @[reg_alloc.rs 354:21]
+                            connect and_then_out, alu_branch_mop @[reg_alloc.rs 314:25]
+                    match and_then_out: @[reg_alloc.rs 313:21]
                         HdlNone:
-                            wire _uninit_expr_13: Ty46
-                            invalidate _uninit_expr_13
-                            connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_13) @[reg_alloc.rs 359:25]
-                        HdlSome(_match_arm_value_147):
-                            connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_147) @[reg_alloc.rs 357:25]
-                    match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 366:21]
+                            wire _uninit_expr_1: Ty37
+                            invalidate _uninit_expr_1
+                            connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _uninit_expr_1) @[reg_alloc.rs 318:25]
+                        HdlSome(_match_arm_value_179):
+                            connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_179) @[reg_alloc.rs 316:25]
+                    match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 325:21]
                         HdlNone:
                             skip
-                        HdlSome(_match_arm_value_148):
-                            wire _bundle_literal_expr_206: Ty25
-                            wire _bundle_literal_expr_207: Ty23
-                            connect _bundle_literal_expr_207.adj_value, tail(UInt<64>(0h1), 62)
-                            connect _bundle_literal_expr_206.unit_num, _bundle_literal_expr_207
-                            wire _bundle_literal_expr_208: Ty24
-                            connect _bundle_literal_expr_208.value, _match_arm_value_148
-                            connect _bundle_literal_expr_206.unit_out_reg, _bundle_literal_expr_208
-                            connect renamed_mops_out_reg[0], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_206) @[reg_alloc.rs 372:25]
-        match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 339:13]
+                        HdlSome(_match_arm_value_180):
+                            wire _bundle_literal_expr_210: Ty25
+                            wire _bundle_literal_expr_211: Ty23
+                            connect _bundle_literal_expr_211.adj_value, tail(UInt<64>(0h1), 62)
+                            connect _bundle_literal_expr_210.unit_num, _bundle_literal_expr_211
+                            wire _bundle_literal_expr_212: Ty24
+                            connect _bundle_literal_expr_212.value, _match_arm_value_180
+                            connect _bundle_literal_expr_210.unit_out_reg, _bundle_literal_expr_212
+                            connect renamed_mops_out_reg[0], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_210) @[reg_alloc.rs 331:25]
+        match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 298:13]
             HdlNone:
-                connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 341:17]
-            HdlSome(_match_arm_value_149):
+                connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 300:17]
+            HdlSome(_match_arm_value_181):
                 skip
-        when not(unit_0.`input`.ready): @[reg_alloc.rs 344:13]
-            connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 346:17]
-        match selected_unit_indexes[1]: @[reg_alloc.rs 349:13]
+        when not(unit_0.`input`.ready): @[reg_alloc.rs 303:13]
+            connect available_units[1][0], UInt<1>(0h0) @[reg_alloc.rs 305:17]
+        match selected_unit_indexes[1]: @[reg_alloc.rs 308:13]
             HdlNone:
                 skip
-            HdlSome(_match_arm_value_150):
-                when eq(_match_arm_value_150, UInt<64>(0h0)): @[reg_alloc.rs 351:17]
-                    wire and_then_out_1: Ty62 @[reg_alloc.rs 355:25]
-                    connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 352:21]
-                    match renamed_mops[1]: @[reg_alloc.rs 355:25]
+            HdlSome(_match_arm_value_182):
+                when eq(_match_arm_value_182, UInt<64>(0h0)): @[reg_alloc.rs 310:17]
+                    wire and_then_out_1: Ty52 @[reg_alloc.rs 314:25]
+                    connect unit_0_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 311:21]
+                    match renamed_mops[1]: @[reg_alloc.rs 314:25]
                         HdlNone:
-                            connect and_then_out_1, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 355:25]
-                        HdlSome(_match_arm_value_151):
-                            wire alu_branch_mop_1: Ty62 @[unit.rs 127:1]
-                            connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 127:1]
-                            match _match_arm_value_151: @[unit.rs 127:1]
-                                AluBranch(_match_arm_value_152):
-                                    connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_152) @[unit.rs 127:1]
-                                L2RegisterFile(_match_arm_value_153):
+                            connect and_then_out_1, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[reg_alloc.rs 314:25]
+                        HdlSome(_match_arm_value_183):
+                            wire alu_branch_mop_1: Ty52 @[unit.rs 127:1]
+                            connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[unit.rs 127:1]
+                            match _match_arm_value_183: @[unit.rs 127:1]
+                                AluBranch(_match_arm_value_184):
+                                    connect alu_branch_mop_1, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_184) @[unit.rs 127:1]
+                                L2RegisterFile(_match_arm_value_185):
                                     skip
-                                LoadStore(_match_arm_value_154):
+                                LoadStore(_match_arm_value_186):
                                     skip
-                            connect and_then_out_1, alu_branch_mop_1 @[reg_alloc.rs 355:25]
-                    match and_then_out_1: @[reg_alloc.rs 354:21]
+                            connect and_then_out_1, alu_branch_mop_1 @[reg_alloc.rs 314:25]
+                    match and_then_out_1: @[reg_alloc.rs 313:21]
                         HdlNone:
-                            wire _uninit_expr_14: Ty46
-                            invalidate _uninit_expr_14
-                            connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_14) @[reg_alloc.rs 359:25]
-                        HdlSome(_match_arm_value_155):
-                            connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_155) @[reg_alloc.rs 357:25]
-                    match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 366:21]
+                            wire _uninit_expr_2: Ty37
+                            invalidate _uninit_expr_2
+                            connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _uninit_expr_2) @[reg_alloc.rs 318:25]
+                        HdlSome(_match_arm_value_187):
+                            connect unit_0.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_187) @[reg_alloc.rs 316:25]
+                    match unit_0_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 325:21]
                         HdlNone:
                             skip
-                        HdlSome(_match_arm_value_156):
-                            wire _bundle_literal_expr_209: Ty25
-                            wire _bundle_literal_expr_210: Ty23
-                            connect _bundle_literal_expr_210.adj_value, tail(UInt<64>(0h1), 62)
-                            connect _bundle_literal_expr_209.unit_num, _bundle_literal_expr_210
-                            wire _bundle_literal_expr_211: Ty24
-                            connect _bundle_literal_expr_211.value, _match_arm_value_156
-                            connect _bundle_literal_expr_209.unit_out_reg, _bundle_literal_expr_211
-                            connect renamed_mops_out_reg[1], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_209) @[reg_alloc.rs 372:25]
-        inst unit_1 of alu_branch_1 @[reg_alloc.rs 312:13]
-        connect unit_1.cd, cd @[reg_alloc.rs 314:9]
-        inst unit_1_free_regs_tracker of unit_free_regs_tracker_1 @[reg_alloc.rs 327:13]
-        connect unit_1_free_regs_tracker.cd, cd @[reg_alloc.rs 329:9]
-        wire _uninit_expr_15: Ty65
-        invalidate _uninit_expr_15
-        connect unit_1_free_regs_tracker.free_in[0].data, _uninit_expr_15 @[reg_alloc.rs 331:9]
-        connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 335:9]
-        connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 336:9]
-        match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 339:13]
+                        HdlSome(_match_arm_value_188):
+                            wire _bundle_literal_expr_213: Ty25
+                            wire _bundle_literal_expr_214: Ty23
+                            connect _bundle_literal_expr_214.adj_value, tail(UInt<64>(0h1), 62)
+                            connect _bundle_literal_expr_213.unit_num, _bundle_literal_expr_214
+                            wire _bundle_literal_expr_215: Ty24
+                            connect _bundle_literal_expr_215.value, _match_arm_value_188
+                            connect _bundle_literal_expr_213.unit_out_reg, _bundle_literal_expr_215
+                            connect renamed_mops_out_reg[1], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_213) @[reg_alloc.rs 331:25]
+        inst unit_1 of alu_branch_1 @[reg_alloc.rs 271:13]
+        connect unit_1.cd, cd @[reg_alloc.rs 273:9]
+        inst unit_1_free_regs_tracker of unit_free_regs_tracker_1 @[reg_alloc.rs 286:13]
+        connect unit_1_free_regs_tracker.cd, cd @[reg_alloc.rs 288:9]
+        wire _uninit_expr_3: Ty55
+        invalidate _uninit_expr_3
+        connect unit_1_free_regs_tracker.free_in[0].data, _uninit_expr_3 @[reg_alloc.rs 290:9]
+        connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h0) @[reg_alloc.rs 294:9]
+        connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[reg_alloc.rs 295:9]
+        match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 298:13]
             HdlNone:
-                connect available_units[0][1], UInt<1>(0h0) @[reg_alloc.rs 341:17]
-            HdlSome(_match_arm_value_157):
+                connect available_units[0][1], UInt<1>(0h0) @[reg_alloc.rs 300:17]
+            HdlSome(_match_arm_value_189):
                 skip
-        when not(unit_1.`input`.ready): @[reg_alloc.rs 344:13]
-            connect available_units[0][1], UInt<1>(0h0) @[reg_alloc.rs 346:17]
-        match selected_unit_indexes[0]: @[reg_alloc.rs 349:13]
+        when not(unit_1.`input`.ready): @[reg_alloc.rs 303:13]
+            connect available_units[0][1], UInt<1>(0h0) @[reg_alloc.rs 305:17]
+        match selected_unit_indexes[0]: @[reg_alloc.rs 308:13]
             HdlNone:
                 skip
-            HdlSome(_match_arm_value_158):
-                when eq(_match_arm_value_158, UInt<64>(0h1)): @[reg_alloc.rs 351:17]
-                    wire and_then_out_2: Ty62 @[reg_alloc.rs 355:25]
-                    connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 352:21]
-                    match renamed_mops[0]: @[reg_alloc.rs 355:25]
+            HdlSome(_match_arm_value_190):
+                when eq(_match_arm_value_190, UInt<64>(0h1)): @[reg_alloc.rs 310:17]
+                    wire and_then_out_2: Ty52 @[reg_alloc.rs 314:25]
+                    connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 311:21]
+                    match renamed_mops[0]: @[reg_alloc.rs 314:25]
                         HdlNone:
-                            connect and_then_out_2, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 355:25]
-                        HdlSome(_match_arm_value_159):
-                            wire alu_branch_mop_2: Ty62 @[unit.rs 127:1]
-                            connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 127:1]
-                            match _match_arm_value_159: @[unit.rs 127:1]
-                                AluBranch(_match_arm_value_160):
-                                    connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_160) @[unit.rs 127:1]
-                                L2RegisterFile(_match_arm_value_161):
+                            connect and_then_out_2, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[reg_alloc.rs 314:25]
+                        HdlSome(_match_arm_value_191):
+                            wire alu_branch_mop_2: Ty52 @[unit.rs 127:1]
+                            connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[unit.rs 127:1]
+                            match _match_arm_value_191: @[unit.rs 127:1]
+                                AluBranch(_match_arm_value_192):
+                                    connect alu_branch_mop_2, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_192) @[unit.rs 127:1]
+                                L2RegisterFile(_match_arm_value_193):
                                     skip
-                                LoadStore(_match_arm_value_162):
+                                LoadStore(_match_arm_value_194):
                                     skip
-                            connect and_then_out_2, alu_branch_mop_2 @[reg_alloc.rs 355:25]
-                    match and_then_out_2: @[reg_alloc.rs 354:21]
+                            connect and_then_out_2, alu_branch_mop_2 @[reg_alloc.rs 314:25]
+                    match and_then_out_2: @[reg_alloc.rs 313:21]
                         HdlNone:
-                            wire _uninit_expr_16: Ty46
-                            invalidate _uninit_expr_16
-                            connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_16) @[reg_alloc.rs 359:25]
-                        HdlSome(_match_arm_value_163):
-                            connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_163) @[reg_alloc.rs 357:25]
-                    match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 366:21]
+                            wire _uninit_expr_4: Ty37
+                            invalidate _uninit_expr_4
+                            connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _uninit_expr_4) @[reg_alloc.rs 318:25]
+                        HdlSome(_match_arm_value_195):
+                            connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_195) @[reg_alloc.rs 316:25]
+                    match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 325:21]
                         HdlNone:
                             skip
-                        HdlSome(_match_arm_value_164):
-                            wire _bundle_literal_expr_212: Ty25
-                            wire _bundle_literal_expr_213: Ty23
-                            connect _bundle_literal_expr_213.adj_value, tail(UInt<64>(0h2), 62)
-                            connect _bundle_literal_expr_212.unit_num, _bundle_literal_expr_213
-                            wire _bundle_literal_expr_214: Ty24
-                            connect _bundle_literal_expr_214.value, _match_arm_value_164
-                            connect _bundle_literal_expr_212.unit_out_reg, _bundle_literal_expr_214
-                            connect renamed_mops_out_reg[0], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_212) @[reg_alloc.rs 372:25]
-        match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 339:13]
+                        HdlSome(_match_arm_value_196):
+                            wire _bundle_literal_expr_216: Ty25
+                            wire _bundle_literal_expr_217: Ty23
+                            connect _bundle_literal_expr_217.adj_value, tail(UInt<64>(0h2), 62)
+                            connect _bundle_literal_expr_216.unit_num, _bundle_literal_expr_217
+                            wire _bundle_literal_expr_218: Ty24
+                            connect _bundle_literal_expr_218.value, _match_arm_value_196
+                            connect _bundle_literal_expr_216.unit_out_reg, _bundle_literal_expr_218
+                            connect renamed_mops_out_reg[0], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_216) @[reg_alloc.rs 331:25]
+        match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 298:13]
             HdlNone:
-                connect available_units[1][1], UInt<1>(0h0) @[reg_alloc.rs 341:17]
-            HdlSome(_match_arm_value_165):
+                connect available_units[1][1], UInt<1>(0h0) @[reg_alloc.rs 300:17]
+            HdlSome(_match_arm_value_197):
                 skip
-        when not(unit_1.`input`.ready): @[reg_alloc.rs 344:13]
-            connect available_units[1][1], UInt<1>(0h0) @[reg_alloc.rs 346:17]
-        match selected_unit_indexes[1]: @[reg_alloc.rs 349:13]
+        when not(unit_1.`input`.ready): @[reg_alloc.rs 303:13]
+            connect available_units[1][1], UInt<1>(0h0) @[reg_alloc.rs 305:17]
+        match selected_unit_indexes[1]: @[reg_alloc.rs 308:13]
             HdlNone:
                 skip
-            HdlSome(_match_arm_value_166):
-                when eq(_match_arm_value_166, UInt<64>(0h1)): @[reg_alloc.rs 351:17]
-                    wire and_then_out_3: Ty62 @[reg_alloc.rs 355:25]
-                    connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 352:21]
-                    match renamed_mops[1]: @[reg_alloc.rs 355:25]
+            HdlSome(_match_arm_value_198):
+                when eq(_match_arm_value_198, UInt<64>(0h1)): @[reg_alloc.rs 310:17]
+                    wire and_then_out_3: Ty52 @[reg_alloc.rs 314:25]
+                    connect unit_1_free_regs_tracker.alloc_out[0].ready, UInt<1>(0h1) @[reg_alloc.rs 311:21]
+                    match renamed_mops[1]: @[reg_alloc.rs 314:25]
                         HdlNone:
-                            connect and_then_out_3, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[reg_alloc.rs 355:25]
-                        HdlSome(_match_arm_value_167):
-                            wire alu_branch_mop_3: Ty62 @[unit.rs 127:1]
-                            connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty46|}(HdlNone) @[unit.rs 127:1]
-                            match _match_arm_value_167: @[unit.rs 127:1]
-                                AluBranch(_match_arm_value_168):
-                                    connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_168) @[unit.rs 127:1]
-                                L2RegisterFile(_match_arm_value_169):
+                            connect and_then_out_3, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[reg_alloc.rs 314:25]
+                        HdlSome(_match_arm_value_199):
+                            wire alu_branch_mop_3: Ty52 @[unit.rs 127:1]
+                            connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty37|}(HdlNone) @[unit.rs 127:1]
+                            match _match_arm_value_199: @[unit.rs 127:1]
+                                AluBranch(_match_arm_value_200):
+                                    connect alu_branch_mop_3, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_200) @[unit.rs 127:1]
+                                L2RegisterFile(_match_arm_value_201):
                                     skip
-                                LoadStore(_match_arm_value_170):
+                                LoadStore(_match_arm_value_202):
                                     skip
-                            connect and_then_out_3, alu_branch_mop_3 @[reg_alloc.rs 355:25]
-                    match and_then_out_3: @[reg_alloc.rs 354:21]
+                            connect and_then_out_3, alu_branch_mop_3 @[reg_alloc.rs 314:25]
+                    match and_then_out_3: @[reg_alloc.rs 313:21]
                         HdlNone:
-                            wire _uninit_expr_17: Ty46
-                            invalidate _uninit_expr_17
-                            connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _uninit_expr_17) @[reg_alloc.rs 359:25]
-                        HdlSome(_match_arm_value_171):
-                            connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty46|}(HdlSome, _match_arm_value_171) @[reg_alloc.rs 357:25]
-                    match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 366:21]
+                            wire _uninit_expr_5: Ty37
+                            invalidate _uninit_expr_5
+                            connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _uninit_expr_5) @[reg_alloc.rs 318:25]
+                        HdlSome(_match_arm_value_203):
+                            connect unit_1.`input`.data, {|HdlNone, HdlSome: Ty37|}(HdlSome, _match_arm_value_203) @[reg_alloc.rs 316:25]
+                    match unit_1_free_regs_tracker.alloc_out[0].data: @[reg_alloc.rs 325:21]
                         HdlNone:
                             skip
-                        HdlSome(_match_arm_value_172):
-                            wire _bundle_literal_expr_215: Ty25
-                            wire _bundle_literal_expr_216: Ty23
-                            connect _bundle_literal_expr_216.adj_value, tail(UInt<64>(0h2), 62)
-                            connect _bundle_literal_expr_215.unit_num, _bundle_literal_expr_216
-                            wire _bundle_literal_expr_217: Ty24
-                            connect _bundle_literal_expr_217.value, _match_arm_value_172
-                            connect _bundle_literal_expr_215.unit_out_reg, _bundle_literal_expr_217
-                            connect renamed_mops_out_reg[1], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_215) @[reg_alloc.rs 372:25]
+                        HdlSome(_match_arm_value_204):
+                            wire _bundle_literal_expr_219: Ty25
+                            wire _bundle_literal_expr_220: Ty23
+                            connect _bundle_literal_expr_220.adj_value, tail(UInt<64>(0h2), 62)
+                            connect _bundle_literal_expr_219.unit_num, _bundle_literal_expr_220
+                            wire _bundle_literal_expr_221: Ty24
+                            connect _bundle_literal_expr_221.value, _match_arm_value_204
+                            connect _bundle_literal_expr_219.unit_out_reg, _bundle_literal_expr_221
+                            connect renamed_mops_out_reg[1], {|HdlNone, HdlSome: Ty25|}(HdlSome, _bundle_literal_expr_219) @[reg_alloc.rs 331:25]
     module alu_branch: @[alu_branch.rs 15:1]
         input cd: Ty0 @[alu_branch.rs 18:29]
-        input `input`: Ty63 @[alu_branch.rs 21:11]
+        input `input`: Ty53 @[alu_branch.rs 21:11]
         connect `input`.ready, UInt<1>(0h1) @[alu_branch.rs 23:5]
     module unit_free_regs_tracker: @[unit_free_regs_tracker.rs 7:1]
         input cd: Ty0 @[unit_free_regs_tracker.rs 14:29]
-        input free_in: Ty66[1] @[unit_free_regs_tracker.rs 17:11]
-        output alloc_out: Ty66[1] @[unit_free_regs_tracker.rs 20:11]
+        input free_in: Ty56[1] @[unit_free_regs_tracker.rs 17:11]
+        output alloc_out: Ty56[1] @[unit_free_regs_tracker.rs 20:11]
         wire _array_literal_expr: UInt<1>[16]
         connect _array_literal_expr[0], UInt<1>(0h0)
         connect _array_literal_expr[1], UInt<1>(0h0)
@@ -3128,7 +2942,7 @@ circuit reg_alloc:
         connect _array_literal_expr[15], UInt<1>(0h0)
         regreset allocated_reg: UInt<1>[16], cd.clk, cd.rst, _array_literal_expr @[unit_free_regs_tracker.rs 27:25]
         connect free_in[0].ready, UInt<1>(0h1) @[unit_free_regs_tracker.rs 29:9]
-        wire firing_data: Ty65 @[ready_valid.rs 30:27]
+        wire firing_data: Ty55 @[ready_valid.rs 30:27]
         connect firing_data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9]
         when free_in[0].ready: @[ready_valid.rs 33:9]
             connect firing_data, free_in[0].data @[ready_valid.rs 34:13]
@@ -3439,7 +3253,7 @@ circuit reg_alloc:
             ; lhs: UInt<4>
             ; rhs: UInt<65>
             connect reduced_alloc_nums_0_16[0], add(reduced_alloc_nums_8_16[sub(UInt<64>(0h0), reduced_count_0_8)], UInt<64>(0h8)) @[unit_free_regs_tracker.rs 83:21]
-        wire firing_data_1: Ty65 @[ready_valid.rs 30:27]
+        wire firing_data_1: Ty55 @[ready_valid.rs 30:27]
         connect firing_data_1, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9]
         when alloc_out[0].ready: @[ready_valid.rs 33:9]
             connect firing_data_1, alloc_out[0].data @[ready_valid.rs 34:13]
@@ -3454,12 +3268,12 @@ circuit reg_alloc:
             connect alloc_out[0].data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[unit_free_regs_tracker.rs 112:13]
     module alu_branch_1: @[alu_branch.rs 15:1]
         input cd: Ty0 @[alu_branch.rs 18:29]
-        input `input`: Ty63 @[alu_branch.rs 21:11]
+        input `input`: Ty53 @[alu_branch.rs 21:11]
         connect `input`.ready, UInt<1>(0h1) @[alu_branch.rs 23:5]
     module unit_free_regs_tracker_1: @[unit_free_regs_tracker.rs 7:1]
         input cd: Ty0 @[unit_free_regs_tracker.rs 14:29]
-        input free_in: Ty66[1] @[unit_free_regs_tracker.rs 17:11]
-        output alloc_out: Ty66[1] @[unit_free_regs_tracker.rs 20:11]
+        input free_in: Ty56[1] @[unit_free_regs_tracker.rs 17:11]
+        output alloc_out: Ty56[1] @[unit_free_regs_tracker.rs 20:11]
         wire _array_literal_expr: UInt<1>[16]
         connect _array_literal_expr[0], UInt<1>(0h0)
         connect _array_literal_expr[1], UInt<1>(0h0)
@@ -3479,7 +3293,7 @@ circuit reg_alloc:
         connect _array_literal_expr[15], UInt<1>(0h0)
         regreset allocated_reg: UInt<1>[16], cd.clk, cd.rst, _array_literal_expr @[unit_free_regs_tracker.rs 27:25]
         connect free_in[0].ready, UInt<1>(0h1) @[unit_free_regs_tracker.rs 29:9]
-        wire firing_data: Ty65 @[ready_valid.rs 30:27]
+        wire firing_data: Ty55 @[ready_valid.rs 30:27]
         connect firing_data, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9]
         when free_in[0].ready: @[ready_valid.rs 33:9]
             connect firing_data, free_in[0].data @[ready_valid.rs 34:13]
@@ -3790,7 +3604,7 @@ circuit reg_alloc:
             ; lhs: UInt<4>
             ; rhs: UInt<65>
             connect reduced_alloc_nums_0_16[0], add(reduced_alloc_nums_8_16[sub(UInt<64>(0h0), reduced_count_0_8)], UInt<64>(0h8)) @[unit_free_regs_tracker.rs 83:21]
-        wire firing_data_1: Ty65 @[ready_valid.rs 30:27]
+        wire firing_data_1: Ty55 @[ready_valid.rs 30:27]
         connect firing_data_1, {|HdlNone, HdlSome: UInt<4>|}(HdlNone) @[ready_valid.rs 31:9]
         when alloc_out[0].ready: @[ready_valid.rs 33:9]
             connect firing_data_1, alloc_out[0].data @[ready_valid.rs 34:13]