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00ddd602c5
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format code
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2025-08-24 19:08:58 -07:00 |
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518284685f
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UnitMOp now has L2RegisterFileMOp after renaming and instead has MoveRegMOp before renaming
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2025-02-28 17:45:46 -08:00 |
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4ff75313e7
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add helper functions for creating instructions
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2025-02-23 20:51:44 -08:00 |
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3bd5c77a3f
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unit_base is basically finished, implemented AddSub[I], didn't check any tests yet
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2025-02-20 20:24:14 -08:00 |
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3f6e5cc600
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WIP implementing unit_base
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2025-02-19 23:54:41 -08:00 |
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2b7e7e4946
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WIP adding unit input/output values and insn tracking
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2025-02-13 20:55:43 -08:00 |
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1084278f34
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reg_alloc: add writes to rename table
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2025-02-11 19:19:06 -08:00 |
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7efcd872b5
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working on reg_alloc
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2025-02-06 21:28:30 -08:00 |
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12481cfab3
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start debugging reg_alloc with simulator
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2024-12-20 00:28:22 -08:00 |
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b51109f4f6
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WIP implementing reg_alloc
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2024-11-05 17:34:31 -08:00 |
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cb5855589f
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WIP adding register allocator
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2024-10-14 21:20:42 -07:00 |
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d7f62737f2
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add license headers
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2024-10-14 16:29:20 -07:00 |
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f65fc1d616
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add more register stuff
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2024-10-13 01:41:45 -07:00 |
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4c3dd128a3
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WIP: adding micro ops
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2024-10-10 22:57:11 -07:00 |
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0f4f067996
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start adding cpu data types
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2024-10-08 20:22:15 -07:00 |
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