diff --git a/crates/cpu/src/config.rs b/crates/cpu/src/config.rs index cf2fd08..9826955 100644 --- a/crates/cpu/src/config.rs +++ b/crates/cpu/src/config.rs @@ -37,6 +37,9 @@ pub struct CpuConfig { pub max_branches_per_fetch: NonZeroUsize, pub max_fetches_in_flight: NonZeroUsize, pub log2_fetch_width_in_bytes: u8, + pub log2_cache_line_size_in_bytes: u8, + pub log2_l1_i_cache_line_count: u8, + pub l1_i_cache_max_misses_in_flight: NonZeroUsize, /// default value for [`UnitConfig::max_in_flight`] pub default_unit_max_in_flight: NonZeroUsize, pub rob_size: NonZeroUsize, @@ -63,6 +66,14 @@ impl CpuConfig { v }; pub const DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES: u8 = 3; + pub const DEFAULT_LOG2_CACHE_LINE_SIZE_IN_BYTES: u8 = 6; + pub const DEFAULT_LOG2_L1_I_CACHE_LINE_COUNT: u8 = 8; + pub const DEFAULT_L1_I_CACHE_MAX_MISSES_IN_FLIGHT: NonZeroUsize = { + let Some(v) = NonZeroUsize::new(2) else { + unreachable!(); + }; + v + }; pub const DEFAULT_UNIT_MAX_IN_FLIGHT: NonZeroUsize = { let Some(v) = NonZeroUsize::new(8) else { unreachable!(); @@ -77,6 +88,9 @@ impl CpuConfig { max_branches_per_fetch: Self::DEFAULT_MAX_BRANCHES_PER_FETCH, max_fetches_in_flight: Self::DEFAULT_MAX_FETCHES_IN_FLIGHT, log2_fetch_width_in_bytes: Self::DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES, + log2_cache_line_size_in_bytes: Self::DEFAULT_LOG2_CACHE_LINE_SIZE_IN_BYTES, + log2_l1_i_cache_line_count: Self::DEFAULT_LOG2_L1_I_CACHE_LINE_COUNT, + l1_i_cache_max_misses_in_flight: Self::DEFAULT_L1_I_CACHE_MAX_MISSES_IN_FLIGHT, default_unit_max_in_flight: Self::DEFAULT_UNIT_MAX_IN_FLIGHT, rob_size, } @@ -141,6 +155,37 @@ impl CpuConfig { .checked_shl(self.log2_fetch_width_in_bytes.into()) .expect("log2_fetch_width_in_bytes is too big") } + pub fn cache_line_size_in_bytes(&self) -> usize { + 1usize + .checked_shl(self.log2_cache_line_size_in_bytes.into()) + .expect("log2_cache_line_size_in_bytes is too big") + } + pub fn log2_fetches_per_cache_line(&self) -> usize { + self.log2_cache_line_size_in_bytes + .checked_sub(self.log2_fetch_width_in_bytes) + .expect("cache line size in bytes must not be smaller than fetch width in bytes") + .into() + } + pub fn fetches_per_cache_line(&self) -> usize { + self.log2_fetches_per_cache_line() + .try_into() + .ok() + .and_then(|v| 1usize.checked_shl(v)) + .expect("log2_fetches_per_cache_line is too big") + } + pub fn l1_i_cache_line_count(&self) -> usize { + 1usize + .checked_shl(self.log2_l1_i_cache_line_count.into()) + .expect("log2_l1_i_cache_line_count is too big") + } + pub fn log2_l1_i_cache_size_in_bytes(&self) -> usize { + self.log2_l1_i_cache_line_count as usize + self.log2_cache_line_size_in_bytes as usize + } + pub fn l1_i_cache_size_in_bytes(&self) -> usize { + 1usize + .checked_shl(self.log2_l1_i_cache_size_in_bytes() as _) + .expect("L1 I-Cache is too big") + } } #[hdl(get(|c| c.fetch_width.get()))] @@ -161,6 +206,33 @@ pub type CpuConfigLog2FetchWidthInBytes> = DynSize #[hdl(get(|c| c.fetch_width_in_bytes()))] pub type CpuConfigFetchWidthInBytes> = DynSize; +#[hdl(get(|c| c.log2_fetches_per_cache_line()))] +pub type CpuConfigLog2FetchesPerCacheLine> = DynSize; + +#[hdl(get(|c| c.fetches_per_cache_line()))] +pub type CpuConfigFetchesPerCacheLine> = DynSize; + +#[hdl(get(|c| c.log2_cache_line_size_in_bytes.into()))] +pub type CpuConfigLog2CacheLineSizeInBytes> = DynSize; + +#[hdl(get(|c| c.cache_line_size_in_bytes()))] +pub type CpuConfigCacheLineSizeInBytes> = DynSize; + +#[hdl(get(|c| c.log2_l1_i_cache_line_count.into()))] +pub type CpuConfigLog2L1ICacheLineCount> = DynSize; + +#[hdl(get(|c| c.l1_i_cache_line_count()))] +pub type CpuConfigL1ICacheLineCount> = DynSize; + +#[hdl(get(|c| c.log2_l1_i_cache_size_in_bytes()))] +pub type CpuConfigLog2L1ICacheSizeInBytes> = DynSize; + +#[hdl(get(|c| c.l1_i_cache_size_in_bytes()))] +pub type CpuConfigL1ICacheSizeInBytes> = DynSize; + +#[hdl(get(|c| c.l1_i_cache_max_misses_in_flight.get()))] +pub type CpuConfigL1ICacheMaxMissesInFlight> = DynSize; + #[hdl(get(|c| c.rob_size.get()))] pub type CpuConfigRobSize> = DynSize; diff --git a/crates/cpu/src/fetch.rs b/crates/cpu/src/fetch.rs new file mode 100644 index 0000000..20035eb --- /dev/null +++ b/crates/cpu/src/fetch.rs @@ -0,0 +1,1581 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information + +use crate::{ + config::{ + CpuConfig, CpuConfigFetchWidthInBytes, CpuConfigFetchesPerCacheLine, + CpuConfigL1ICacheLineCount, CpuConfigL1ICacheMaxMissesInFlight, + CpuConfigLog2FetchWidthInBytes, CpuConfigLog2L1ICacheLineCount, + CpuConfigMaxFetchesInFlight, PhantomConstCpuConfig, + }, + next_pc::{ + FETCH_BLOCK_ID_WIDTH, NextPcToFetchInterface, NextPcToFetchInterfaceInner, ResetStatus, + ResetSteps, SimValueDefault, + }, + util::array_vec::ArrayVec, +}; +use fayalite::{ + int::{UIntInRangeInclusiveType, UIntInRangeType}, + memory::{ReadWriteStruct, memory_addr_width, splat_mask}, + prelude::*, + util::{DebugAsDisplay, ready_valid::ReadyValid}, +}; +use std::{collections::VecDeque, fmt}; + +#[hdl] +pub enum MemoryOperationKind { + Read, + Write, +} + +#[hdl(no_static)] +pub struct MemoryOperationStart + PhantomConstCpuConfig> { + pub kind: MemoryOperationKind, + pub addr: UInt<64>, + pub write_data: ArrayType, CpuConfigFetchWidthInBytes>, + pub fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, // for debugging + pub config: C, +} + +#[hdl] +pub enum MemoryOperationErrorKind { + Generic, +} + +#[hdl] +pub enum MemoryOperationFinishKind { + Success(MemoryOperationKind), + Error(MemoryOperationErrorKind), +} + +#[hdl(no_static)] +pub struct MemoryOperationFinish + PhantomConstCpuConfig> { + pub kind: MemoryOperationFinishKind, + pub read_data: ArrayType, CpuConfigFetchWidthInBytes>, + pub config: C, +} + +#[hdl(no_static)] +pub struct MemoryInterface + PhantomConstCpuConfig> { + pub start: ReadyValid>, + #[hdl(flip)] + pub finish: ReadyValid>, + /// for debugging + #[hdl(flip)] + pub next_fetch_block_ids: + HdlOption, CpuConfigMaxFetchesInFlight>>, + pub config: C, +} + +#[hdl(no_static)] +pub struct FetchToDecodeInterfaceInner + PhantomConstCpuConfig> { + pub start_pc: UInt<64>, + pub fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, + pub fetch_block_data: ArrayType, CpuConfigFetchWidthInBytes>, + pub error: HdlOption, + pub config: C, +} + +#[hdl(no_static)] +pub struct FetchToDecodeInterface + PhantomConstCpuConfig> { + pub fetched: ReadyValid>, + /// when both fetch and cancel are triggered in the same clock cycle, that means to cancel and then start a new fetch + pub cancel: HdlOption, CpuConfigMaxFetchesInFlight>>, + /// for debugging + #[hdl(flip)] + pub next_fetch_block_ids: + HdlOption, CpuConfigMaxFetchesInFlight>>, +} + +#[hdl(no_static)] +struct CacheLine + PhantomConstCpuConfig> { + data: ArrayType< + ArrayType, CpuConfigFetchWidthInBytes>, + CpuConfigFetchesPerCacheLine, + >, + addr: HdlOption>>, + config: C, +} + +impl SimValueDefault for CacheLine { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { data, addr, config } = self; + #[hdl(sim)] + Self { + data: data.sim_value_default(), + addr: addr.sim_value_default(), + config, + } + } +} + +#[hdl(get(|c| 64usize.saturating_sub(c.log2_l1_i_cache_size_in_bytes())))] +type CacheLineTagAddrWidth> = DynSize; + +#[hdl] +enum CacheLookupState { + Start, + ReadingCache, + CacheMiss, + AfterCacheMiss, + ReadingCacheAfterCacheMiss, + Returning, +} + +#[hdl(no_static)] +struct FetchQueueEntry + PhantomConstCpuConfig> { + start_pc: UInt<64>, + fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, + state: CacheLookupState, + error: HdlOption, + fetch_block_data: ArrayType, CpuConfigFetchWidthInBytes>, + config: C, +} + +impl SimValueDefault for FetchQueueEntry { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + start_pc: _, + fetch_block_id, + state: _, + error: _, + fetch_block_data, + config, + } = self; + #[hdl(sim)] + Self { + start_pc: 0u64, + fetch_block_id: fetch_block_id.zero(), + state: #[hdl(sim)] + CacheLookupState.Start(), + error: #[hdl(sim)] + HdlNone(), + fetch_block_data: fetch_block_data.sim_value_default(), + config, + } + } +} + +#[hdl(no_static)] +struct CacheMiss + PhantomConstCpuConfig> { + addr: UInt<64>, + fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, + next_start_fetch_block: HdlOption>, + next_finish_fetch_block: HdlOption>, + error: HdlOption, + config: C, +} + +impl CacheMiss { + #[hdl] + fn next_fetch_block( + next_opt: &mut SimValue>>, + limit: Option, + ) -> Option>> { + let next: &mut SimValue> = #[hdl(sim)] + match &mut *next_opt { + HdlSome(next) => next, + HdlNone => return None, + }; + let limit = limit.unwrap_or(next.ty().end()); + if **next >= limit { + return None; + } + let retval = next.clone(); + if **next + 1 >= limit { + *next_opt = #[hdl(sim)] + (next_opt.ty()).HdlNone(); + } else { + **next += 1; + } + Some(retval) + } + #[hdl] + fn next_start_fetch_block( + this: &mut SimValue, + ) -> Option>> { + #[hdl(sim)] + if let HdlSome(_) = &this.error { + return None; + } + Self::next_fetch_block(&mut this.next_start_fetch_block, None) + } + #[hdl] + fn next_finish_fetch_block( + this: &mut SimValue, + ) -> Option>> { + let mut limit = None; + #[hdl(sim)] + if let HdlSome(_) = &this.error { + #[hdl(sim)] + if let HdlSome(v) = &this.next_start_fetch_block { + limit = Some(**v); + } + } + Self::next_fetch_block(&mut this.next_finish_fetch_block, limit) + } +} + +impl SimValueDefault for CacheMiss { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + addr: _, + fetch_block_id, + next_start_fetch_block, + next_finish_fetch_block, + error: _, + config, + } = self; + #[hdl(sim)] + Self { + addr: 0u64, + fetch_block_id: fetch_block_id.zero(), + next_start_fetch_block: #[hdl(sim)] + next_start_fetch_block.HdlNone(), + next_finish_fetch_block: #[hdl(sim)] + next_finish_fetch_block.HdlNone(), + error: #[hdl(sim)] + HdlNone(), + config, + } + } +} + +#[hdl(no_static)] +struct L1ICacheState + PhantomConstCpuConfig> { + queue: ArrayVec, CpuConfigMaxFetchesInFlight>, + cache_misses: ArrayVec, CpuConfigL1ICacheMaxMissesInFlight>, + config: C, +} + +#[derive(Clone)] +struct L1ICacheStateSim { + queue: VecDeque>>, + cache_misses: VecDeque>>, + state_expr: Expr>, +} + +impl fmt::Debug for L1ICacheStateSim { + #[hdl] + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + queue, + cache_misses, + state_expr: _, + } = self; + f.debug_struct("L1ICacheStateSim") + .field( + "queue", + &fmt::from_fn(|f| { + let mut debug_list = f.debug_list(); + for entry in queue { + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc, + fetch_block_id, + state, + error, + fetch_block_data, + config: _, + } = entry; + let entry = fmt::from_fn(|f| { + f.debug_struct("FetchQueueEntry") + .field("start_pc", start_pc) + .field("fetch_block_id", fetch_block_id) + .field( + "state", + #[hdl(sim)] + match state { + CacheLookupState::Start => &DebugAsDisplay("Start"), + CacheLookupState::ReadingCache => { + &DebugAsDisplay("ReadingCache") + } + CacheLookupState::CacheMiss => &DebugAsDisplay("CacheMiss"), + CacheLookupState::AfterCacheMiss => { + &DebugAsDisplay("AfterCacheMiss") + } + CacheLookupState::ReadingCacheAfterCacheMiss => { + &DebugAsDisplay("ReadingCacheAfterCacheMiss") + } + CacheLookupState::Returning => &DebugAsDisplay("Returning"), + CacheLookupState::Unknown => state, + }, + ) + .field( + "error", + &fmt::from_fn(|f| { + #[hdl(sim)] + match error { + HdlSome(v) => { + write!(f, "HdlSome({v:?})") + } + HdlNone => write!(f, "HdlNone"), + } + }), + ) + .field("fetch_block_data", fetch_block_data) + .finish() + }); + debug_list.entry(&format_args!("{entry}")); + } + debug_list.finish() + }), + ) + .field( + "cache_misses", + &fmt::from_fn(|f| { + let mut debug_list = f.debug_list(); + for cache_miss in cache_misses { + #[hdl(sim)] + let CacheMiss::<_> { + addr, + fetch_block_id, + next_start_fetch_block, + next_finish_fetch_block, + error, + config: _, + } = cache_miss; + let entry = fmt::from_fn(|f| { + f.debug_struct("CacheMiss") + .field("addr", addr) + .field("fetch_block_id", fetch_block_id) + .field( + "next_start_fetch_block", + &fmt::from_fn(|f| { + #[hdl(sim)] + match next_start_fetch_block { + HdlSome(v) => { + write!(f, "HdlSome({})", **v) + } + HdlNone => write!(f, "HdlNone"), + } + }), + ) + .field( + "next_finish_fetch_block", + &fmt::from_fn(|f| { + #[hdl(sim)] + match next_finish_fetch_block { + HdlSome(v) => { + write!(f, "HdlSome({})", **v) + } + HdlNone => write!(f, "HdlNone"), + } + }), + ) + .field( + "error", + &fmt::from_fn(|f| { + #[hdl(sim)] + match error { + HdlSome(v) => { + write!(f, "HdlSome({v:?})") + } + HdlNone => write!(f, "HdlNone"), + } + }), + ) + .finish() + }); + debug_list.entry(&format_args!("{entry}")); + } + debug_list.finish() + }), + ) + .finish_non_exhaustive() + } +} + +#[hdl(no_static)] +struct WriteBackStep + PhantomConstCpuConfig> { + cache_line_index: UIntType>, + data: CacheLine, + mask: AsMask>, +} + +#[hdl(no_static)] +struct CacheRead + PhantomConstCpuConfig> { + cache_line_index: UIntType>, + config: C, +} + +#[hdl(no_static)] +struct CacheReadData + PhantomConstCpuConfig> { + cache_line_index: UIntType>, + cache_line: CacheLine, +} + +#[hdl] +type FetchBlockInCacheLine + PhantomConstCpuConfig> = + UIntInRangeType, CpuConfigFetchesPerCacheLine>; + +#[hdl(no_static)] +struct SplitAddr + PhantomConstCpuConfig> { + // fields must be in LSB to MSB order + byte_in_fetch_block: UIntType>, + fetch_block_in_cache_line: FetchBlockInCacheLine, + cache_line_index: UIntType>, + tag: UIntType>, +} + +impl SplitAddr { + #[hdl] + fn split_addr_sim(self, addr: impl ToSimValueWithType>) -> SimValue { + let addr = addr.into_sim_value_with_type(UInt::<64>::new_static()); + assert_eq!( + self.fetch_block_in_cache_line.bit_width(), + self.fetch_block_in_cache_line.end().ilog2() as usize + ); + addr.cast_bits_to(self) + } + #[hdl] + fn addr_sim(this: impl ToSimValue) -> SimValue> { + SimValue::from_dyn_int(this.into_sim_value().cast_to_bits()) + } +} + +struct ReadyForMemoryOperationFinish { + cache_miss_index: usize, +} + +struct ReadyForFetch {} + +impl L1ICacheStateSim { + fn new(state_expr: Expr>) -> Self { + let config = state_expr.ty().config; + Self { + queue: VecDeque::with_capacity(CpuConfigMaxFetchesInFlight[config]), + cache_misses: VecDeque::with_capacity(CpuConfigL1ICacheMaxMissesInFlight[config]), + state_expr, + } + } + fn config(&self) -> C { + self.state_expr.ty().config + } + #[hdl] + fn try_start_memory_operation(&mut self) -> Option>> { + let config = self.config(); + for cache_miss in &mut self.cache_misses { + let Some(next_start_fetch_block) = CacheMiss::next_start_fetch_block(cache_miss) else { + continue; + }; + #[hdl(sim)] + let CacheMiss::<_> { + addr, + fetch_block_id, + next_start_fetch_block: _, + next_finish_fetch_block: _, + error: _, // handled by CacheMiss::next_start_fetch_block() + config: _, + } = cache_miss; + let mem_op_ty = MemoryOperationStart[config]; + let mut addr = SplitAddr[config].split_addr_sim(addr); + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block, + fetch_block_in_cache_line, + cache_line_index: _, + tag: _, + } = &mut addr; + assert!(*byte_in_fetch_block.cmp_eq(0u8), "{addr:?}"); + assert!(*fetch_block_in_cache_line.cmp_eq(0u8), "{addr:?}"); + *fetch_block_in_cache_line = next_start_fetch_block; + return Some( + #[hdl(sim)] + MemoryOperationStart::<_> { + kind: #[hdl(sim)] + MemoryOperationKind.Read(), + addr: SplitAddr::addr_sim(addr), + write_data: repeat( + mem_op_ty.write_data.element().zero(), + mem_op_ty.write_data.len(), + ), + fetch_block_id, + config, + }, + ); + } + None + } + #[hdl] + fn queue_front_state_is_after_cache_miss(&self) -> bool { + self.queue.front().is_some_and(|entry| { + #[hdl(sim)] + match &entry.state { + CacheLookupState::Start + | CacheLookupState::ReadingCache + | CacheLookupState::CacheMiss + | CacheLookupState::Returning => false, + CacheLookupState::AfterCacheMiss | CacheLookupState::ReadingCacheAfterCacheMiss => { + true + } + CacheLookupState::Unknown => unreachable!(), + } + }) + } + #[hdl] + fn ready_for_memory_operation_finish(&self) -> Option { + if self.queue_front_state_is_after_cache_miss() { + println!("ready_for_memory_operation_finish: queue_front_state_is_after_cache_miss"); + return None; + } + for (cache_miss_index, cache_miss) in self.cache_misses.iter().enumerate() { + let Some(_next_finish_cache_block) = + CacheMiss::next_finish_fetch_block(&mut cache_miss.clone()) + else { + continue; + }; + return Some(ReadyForMemoryOperationFinish { cache_miss_index }); + } + None + } + #[must_use] + #[hdl] + fn do_memory_operation_finish<'a>( + &mut self, + ready_for_memory_operation_finish: ReadyForMemoryOperationFinish, + memory_operation_finish: impl ToSimValue>, + ) -> Option>> { + let config = self.config(); + let cache_miss = &mut self.cache_misses[ready_for_memory_operation_finish.cache_miss_index]; + let Some(fetch_block) = CacheMiss::next_finish_fetch_block(cache_miss) else { + unreachable!(); + }; + #[hdl(sim)] + let CacheMiss::<_> { + addr, + fetch_block_id: _, + next_start_fetch_block: _, + next_finish_fetch_block, + error, + config: _, + } = cache_miss; + #[hdl(sim)] + let MemoryOperationFinish::<_> { + kind, + read_data, + config: _, + } = memory_operation_finish; + #[hdl(sim)] + match kind { + MemoryOperationFinishKind::Success(success) => + { + #[hdl(sim)] + match success { + MemoryOperationKind::Read => {} + MemoryOperationKind::Write => unreachable!(), + } + } + MemoryOperationFinishKind::Error(e) => + { + #[hdl(sim)] + if let HdlNone = &error { + *error = #[hdl(sim)] + HdlSome(e); + } + } + } + #[hdl(sim)] + if let HdlSome(_) = error { + return None; + } + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block, + fetch_block_in_cache_line, + cache_line_index, + tag, + } = SplitAddr[config].split_addr_sim(&addr); + assert!(*byte_in_fetch_block.cmp_eq(0u8), "{addr:?}"); + assert!(*fetch_block_in_cache_line.cmp_eq(0u8), "{addr:?}"); + let write_back_step_ty = WriteBackStep[config]; + let mut data = write_back_step_ty.data.sim_value_default(); + let mut mask = splat_mask(write_back_step_ty.data, false.to_expr()).into_sim_value(); + #[hdl(sim)] + let AsMask::> { + data: mask_data, + addr: mask_addr, + config: _, + } = &mut mask; + #[hdl(sim)] + let CacheLine::<_> { + data: data_data, + addr: data_addr, + config: _, + } = &mut data; + // set cache line tag, making sure to mark partially-filled cache lines as invalid + **mask_addr = true; + let data_addr_ty = data_addr.ty(); + *data_addr = #[hdl(sim)] + if let HdlNone = next_finish_fetch_block { + #[hdl(sim)] + data_addr_ty.HdlSome(tag) + } else { + #[hdl(sim)] + data_addr_ty.HdlNone() + }; + data_data[*fetch_block] = read_data.clone(); + for mask_data_byte in &mut mask_data[*fetch_block] { + **mask_data_byte = true; + } + Some( + #[hdl(sim)] + WriteBackStep::<_> { + cache_line_index, + data, + mask, + }, + ) + } + #[hdl] + async fn write_debug_state(&self, sim: &mut ExternModuleSimulationState) { + dbg!(self); + let L1ICacheState { + queue, + cache_misses, + config, + } = self.state_expr.ty(); + let queue = queue + .from_iter_sim(queue.element().sim_value_default(), &self.queue) + .expect("known to fit"); + let cache_misses = cache_misses + .from_iter_sim( + cache_misses.element().sim_value_default(), + &self.cache_misses, + ) + .expect("known to fit"); + sim.write( + self.state_expr, + #[hdl(sim)] + L1ICacheState::<_> { + queue, + cache_misses, + config, + }, + ) + .await; + } + #[hdl] + fn check_memory_next_fetch_block_ids( + &self, + memory_next_fetch_block_ids: SimValue< + ArrayVec, CpuConfigMaxFetchesInFlight>, + >, + ) { + let memory_next_fetch_block_ids = ArrayVec::elements_sim_ref(&memory_next_fetch_block_ids); + let mut expected_memory_next_fetch_block_ids = Vec::new(); + for cache_miss in &self.cache_misses { + let range_start = #[hdl(sim)] + match &cache_miss.next_finish_fetch_block { + HdlSome(v) => **v, + HdlNone => continue, // fully finished + }; + let range_end = #[hdl(sim)] + match &cache_miss.next_start_fetch_block { + HdlSome(v) => **v, + HdlNone => cache_miss.next_start_fetch_block.ty().HdlSome.end(), + }; + for _ in range_start..range_end { + expected_memory_next_fetch_block_ids.push(cache_miss.fetch_block_id.clone()); + } + } + assert_eq!( + memory_next_fetch_block_ids, + expected_memory_next_fetch_block_ids + ); + } + #[hdl] + fn from_next_pc_next_fetch_block_ids( + &self, + to_decode_next_fetch_block_ids: SimValue< + HdlOption, CpuConfigMaxFetchesInFlight>>, + >, + ) -> SimValue, CpuConfigMaxFetchesInFlight>>> + { + let config = self.config(); + let array_vec_ty = ArrayVec[UInt::new_static()][CpuConfigMaxFetchesInFlight[config]]; + let retval_ty = HdlOption[array_vec_ty]; + #[hdl(sim)] + if let HdlSome(to_decode_next_fetch_block_ids) = to_decode_next_fetch_block_ids { + #[hdl(sim)] + retval_ty.HdlSome( + array_vec_ty + .from_iter_sim( + 0u8, + self.queue + .iter() + .map(|entry| &entry.fetch_block_id) + .chain(ArrayVec::elements_sim_ref(&to_decode_next_fetch_block_ids)), + ) + .expect("should fit"), + ) + } else { + #[hdl(sim)] + retval_ty.HdlNone() + } + } + #[hdl] + async fn wait_for_clock_edge_while_updating( + &self, + sim: &mut ExternModuleSimulationState, + clk: Expr, + from_next_pc_next_fetch_block_ids: Expr< + HdlOption< + ArrayVec< + UInt<{ FETCH_BLOCK_ID_WIDTH }>, + CpuConfigMaxFetchesInFlight>, + >, + >, + >, + to_decode_next_fetch_block_ids: Expr< + HdlOption< + ArrayVec< + UInt<{ FETCH_BLOCK_ID_WIDTH }>, + CpuConfigMaxFetchesInFlight>, + >, + >, + >, + ) { + let do_update = async |sim: &mut ExternModuleSimulationState| { + let next_fetch_block_ids = sim.read(to_decode_next_fetch_block_ids).await; + let next_fetch_block_ids = self.from_next_pc_next_fetch_block_ids(next_fetch_block_ids); + sim.write(from_next_pc_next_fetch_block_ids, next_fetch_block_ids) + .await; + }; + let sensitivity_list = [ + Expr::canonical(clk), + Expr::canonical(to_decode_next_fetch_block_ids), + ]; + while sim.read_clock(clk).await { + do_update(sim).await; + sim.wait_for_changes(sensitivity_list, None).await; + } + while !sim.read_clock(clk).await { + do_update(sim).await; + sim.wait_for_changes(sensitivity_list, None).await; + } + } + #[hdl] + fn ready_for_fetch(&self) -> Option { + if self.queue_front_state_is_after_cache_miss() { + println!("ready_for_fetch: queue_front_state_is_after_cache_miss"); + return None; + } + let config = self.config(); + let max_fetches_in_flight = CpuConfigMaxFetchesInFlight[config]; + assert!(self.queue.len() <= max_fetches_in_flight); + (self.queue.len() < max_fetches_in_flight).then_some(ReadyForFetch {}) + } + #[hdl] + fn do_fetch<'a>( + &mut self, + ready_for_fetch: ReadyForFetch, + fetch: impl ToSimValue, + ) { + let ReadyForFetch {} = ready_for_fetch; + let config = self.config(); + let max_fetches_in_flight = CpuConfigMaxFetchesInFlight[config]; + assert!(self.queue.len() < max_fetches_in_flight); + #[hdl(sim)] + let NextPcToFetchInterfaceInner { + start_pc, + fetch_block_id, + } = fetch; + let entry_ty = FetchQueueEntry[config]; + self.queue.push_back( + #[hdl(sim)] + FetchQueueEntry::<_> { + start_pc, + fetch_block_id, + state: #[hdl(sim)] + CacheLookupState.Start(), + error: #[hdl(sim)] + HdlNone(), + fetch_block_data: entry_ty.fetch_block_data.sim_value_default(), + config, + }, + ); + } + #[hdl] + fn cancel_fetches(&mut self, in_progress_fetches_to_cancel: usize) { + // cancel in-progress fetches from newest to oldest + self.queue.truncate( + self.queue + .len() + .saturating_sub(in_progress_fetches_to_cancel), + ); + } + #[hdl] + fn finish_cache_misses(&mut self) { + let split_addr_ty = SplitAddr[self.config()]; + let cache_miss = self.cache_misses.pop_front_if(|cache_miss| { + let mut cache_miss = cache_miss.clone(); + CacheMiss::next_start_fetch_block(&mut cache_miss).is_none() + && CacheMiss::next_finish_fetch_block(&mut cache_miss).is_none() + }); + let Some(cache_miss) = cache_miss else { + return; + }; + #[hdl(sim)] + let CacheMiss::<_> { + addr, + fetch_block_id: _, + next_start_fetch_block: _, + next_finish_fetch_block: _, + error, + config: _, + } = cache_miss; + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block, + fetch_block_in_cache_line, + cache_line_index, + tag, + } = split_addr_ty.split_addr_sim(&addr); + assert!(*byte_in_fetch_block.cmp_eq(0u8), "{addr:?}"); + assert!(*fetch_block_in_cache_line.cmp_eq(0u8), "{addr:?}"); + for entry in &mut self.queue { + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc, + fetch_block_id: _, + state, + error: entry_error, + fetch_block_data: _, + config: _, + } = entry; + #[hdl(sim)] + match &state { + CacheLookupState::Start + | CacheLookupState::ReadingCache + | CacheLookupState::AfterCacheMiss + | CacheLookupState::ReadingCacheAfterCacheMiss + | CacheLookupState::Returning => continue, + CacheLookupState::CacheMiss => {} + CacheLookupState::Unknown => unreachable!(), + } + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block: _, + fetch_block_in_cache_line: _, + cache_line_index: entry_cache_line_index, + tag: entry_tag, + } = split_addr_ty.split_addr_sim(start_pc); + if *cache_line_index.cmp_eq(entry_cache_line_index) && *tag.cmp_eq(entry_tag) { + *entry_error = error.clone(); + *state = #[hdl(sim)] + if let HdlSome(_) = &error { + #[hdl(sim)] + CacheLookupState.Returning() + } else { + #[hdl(sim)] + CacheLookupState.AfterCacheMiss() + }; + } + } + } + #[must_use] + #[hdl] + fn next_cache_read(&mut self) -> Option>> { + let config = self.config(); + for entry in &mut self.queue { + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc, + fetch_block_id: _, + state, + error: _, + fetch_block_data: _, + config: _, + } = entry; + *state = #[hdl(sim)] + match &state { + CacheLookupState::Start => + { + #[hdl(sim)] + CacheLookupState.ReadingCache() + } + CacheLookupState::AfterCacheMiss => + { + #[hdl(sim)] + CacheLookupState.ReadingCacheAfterCacheMiss() + } + CacheLookupState::ReadingCache + | CacheLookupState::CacheMiss + | CacheLookupState::ReadingCacheAfterCacheMiss + | CacheLookupState::Returning => continue, + CacheLookupState::Unknown => unreachable!(), + }; + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block: _, + fetch_block_in_cache_line: _, + cache_line_index, + tag: _, + } = SplitAddr[config].split_addr_sim(start_pc); + return Some( + #[hdl(sim)] + CacheRead::<_> { + cache_line_index, + config, + }, + ); + } + None + } + #[hdl] + fn cache_read_data(&mut self, cache_read_data: impl ToSimValue>) { + #[hdl(sim)] + let CacheReadData::<_> { + cache_line_index: read_cache_line_index, + cache_line, + } = cache_read_data; + let config = self.config(); + for entry in &mut self.queue { + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc, + fetch_block_id, + state, + error: _, + fetch_block_data, + config: _, + } = entry; + #[hdl(sim)] + match &state { + CacheLookupState::Start + | CacheLookupState::CacheMiss + | CacheLookupState::AfterCacheMiss + | CacheLookupState::Returning => continue, + CacheLookupState::ReadingCache | CacheLookupState::ReadingCacheAfterCacheMiss => {} + CacheLookupState::Unknown => unreachable!(), + } + let split_addr_ty = SplitAddr[config]; + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block: _, + fetch_block_in_cache_line, + cache_line_index, + tag, + } = split_addr_ty.split_addr_sim(start_pc); + if *cache_line_index.cmp_ne(&read_cache_line_index) { + break; + } + let addr_ty = cache_line.addr.ty(); + let opt_tag = #[hdl(sim)] + addr_ty.HdlSome(&tag); + if *opt_tag.cmp_eq(&cache_line.addr) { + // cache hit + *fetch_block_data = cache_line.data[*fetch_block_in_cache_line].clone(); + *state = #[hdl(sim)] + CacheLookupState.Returning(); + } else { + // cache miss + let is_matching_cache_miss = |cache_miss: &SimValue>| { + let addr = &cache_miss.addr; + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block: cache_miss_byte_in_fetch_block, + fetch_block_in_cache_line: cache_miss_fetch_block_in_cache_line, + cache_line_index: cache_miss_cache_line_index, + tag: cache_miss_tag, + } = split_addr_ty.split_addr_sim(addr); + assert!(*cache_miss_byte_in_fetch_block.cmp_eq(0u8), "{addr:?}"); + assert!( + *cache_miss_fetch_block_in_cache_line.cmp_eq(0u8), + "{addr:?}" + ); + *cache_line_index.cmp_eq(cache_miss_cache_line_index) + && *tag.cmp_eq(cache_miss_tag) + }; + if self.cache_misses.iter().any(is_matching_cache_miss) { + *state = #[hdl(sim)] + CacheLookupState.CacheMiss(); + } else if self.cache_misses.len() < CpuConfigL1ICacheMaxMissesInFlight[config] { + let CacheMiss { + addr: _, + fetch_block_id: _, + next_start_fetch_block, + next_finish_fetch_block, + error, + config: _, + } = CacheMiss[config]; + self.cache_misses.push_back( + #[hdl(sim)] + CacheMiss::<_> { + addr: SplitAddr::::addr_sim( + #[hdl(sim)] + SplitAddr::<_> { + byte_in_fetch_block: split_addr_ty.byte_in_fetch_block.zero(), + fetch_block_in_cache_line: 0usize.to_sim_value_with_type( + split_addr_ty.fetch_block_in_cache_line, + ), + cache_line_index, + tag, + }, + ), + fetch_block_id, + next_start_fetch_block: #[hdl(sim)] + next_start_fetch_block.HdlSome(0usize), + next_finish_fetch_block: #[hdl(sim)] + next_finish_fetch_block.HdlSome(0usize), + error: #[hdl(sim)] + error.HdlNone(), + config, + }, + ); + *state = #[hdl(sim)] + CacheLookupState.CacheMiss(); + } else { + // no space for a cache miss, wait until there's space + *state = #[hdl(sim)] + CacheLookupState.Start(); + } + } + break; + } + } + #[hdl] + fn to_decode_fetched(&mut self) -> Option>> { + let entry = self.queue.front_mut()?; + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc, + fetch_block_id, + state, + error, + fetch_block_data, + config, + } = &mut *entry; + #[hdl(sim)] + match &state { + CacheLookupState::Start + | CacheLookupState::ReadingCache + | CacheLookupState::CacheMiss + | CacheLookupState::AfterCacheMiss + | CacheLookupState::ReadingCacheAfterCacheMiss => return None, + CacheLookupState::Returning => {} + CacheLookupState::Unknown => unreachable!(), + } + let retval = #[hdl(sim)] + FetchToDecodeInterfaceInner::<_> { + start_pc, + fetch_block_id, + fetch_block_data, + error, + config, + }; + self.queue.pop_front(); + Some(retval) + } +} + +impl SimValueDefault for L1ICacheState { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + queue, + cache_misses, + config, + } = self; + #[hdl(sim)] + Self { + queue: queue.sim_value_default(), + cache_misses: cache_misses.sim_value_default(), + config, + } + } +} + +impl ResetSteps for L1ICacheState { + #[hdl] + fn reset_step(this: &mut SimValue, step: usize) -> ResetStatus { + #[hdl(sim)] + let Self { + // overwritten every cycle, no reset needed + queue: _, + // overwritten every cycle, no reset needed + cache_misses: _, + config: _, + } = this; + let _ = step; + ResetStatus::Done + } +} + +#[hdl_module(extern)] +fn l1_i_cache_impl(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let memory_interface: MemoryInterface> = + m.output(MemoryInterface[config]); + #[hdl] + let from_next_pc: NextPcToFetchInterface> = + m.input(NextPcToFetchInterface[config]); + #[hdl] + let to_decode_fetched: ReadyValid>> = + m.output(ReadyValid[FetchToDecodeInterfaceInner[config]]); + #[hdl] + let to_decode_next_fetch_block_ids: HdlOption< + ArrayVec< + UInt<{ FETCH_BLOCK_ID_WIDTH }>, + CpuConfigMaxFetchesInFlight>, + >, + > = m.input(HdlOption[ArrayVec[UInt::new_static()][CpuConfigMaxFetchesInFlight[config]]]); + #[hdl] + let max_cancel_in_fetch: UIntInRangeInclusiveType< + ConstUsize<0>, + CpuConfigMaxFetchesInFlight>, + > = m.output(UIntInRangeInclusiveType[ConstUsize::<0>][CpuConfigMaxFetchesInFlight[config]]); + // i_cache_port.clk is externally overridden with cd.clk + #[hdl] + let i_cache_port: ReadWriteStruct>, DynSize> = m.output( + ReadWriteStruct[CacheLine[config]][memory_addr_width(CpuConfigL1ICacheLineCount[config])], + ); + #[hdl] + let state_for_debug: L1ICacheState> = m.output(L1ICacheState[config]); + m.register_clock_for_past(cd.clk); + #[hdl] + async fn run( + mut sim: ExternModuleSimulationState, + cd: Expr, + memory_interface: Expr>>, + from_next_pc: Expr>>, + to_decode_fetched: Expr>>>, + to_decode_next_fetch_block_ids: Expr< + HdlOption< + ArrayVec< + UInt<{ FETCH_BLOCK_ID_WIDTH }>, + CpuConfigMaxFetchesInFlight>, + >, + >, + >, + max_cancel_in_fetch: Expr< + UIntInRangeInclusiveType< + ConstUsize<0>, + CpuConfigMaxFetchesInFlight>, + >, + >, + i_cache_port: Expr>, DynSize>>, + state_expr: Expr>>, + ) { + let config = state_expr.ty().config; + let l1_i_cache_line_count = CpuConfigL1ICacheLineCount[config]; + let cache_line_ty = CacheLine[config]; + for step in 0usize..l1_i_cache_line_count { + sim.write(i_cache_port.en, false).await; + #[hdl] + let ReadWriteStruct::<_, _> { + addr, + en, + clk: _, // externally overridden with cd.clk + rdata: _, + wmode, + wdata, + wmask, + } = i_cache_port; + sim.write(addr, step.cast_to(addr.ty())).await; + sim.write(en, true).await; + sim.write(wmode, true).await; + sim.write(wdata, CacheLine::sim_value_default(wdata.ty())) + .await; + sim.write(wmask, splat_mask(cache_line_ty, true.to_expr())) + .await; + sim.wait_for_clock_edge(cd.clk).await; + } + sim.write(from_next_pc.cancel.ready, true).await; + let memory_interface_start_data_ty = memory_interface.start.data.ty(); + let to_decode_fetched_data_ty = to_decode_fetched.data.ty(); + let cache_read_data_ty = CacheReadData[config]; + let mut state = L1ICacheStateSim::new(state_expr); + loop { + state.finish_cache_misses(); + let ready_for_fetch = state.ready_for_fetch(); + sim.write(from_next_pc.fetch.ready, ready_for_fetch.is_some()) + .await; + let ready_for_memory_operation_finish = state.ready_for_memory_operation_finish(); + sim.write( + memory_interface.finish.ready, + ready_for_memory_operation_finish.is_some(), + ) + .await; + sim.write( + memory_interface.start.data, + if let Some(v) = state.clone().try_start_memory_operation() { + #[hdl(sim)] + memory_interface_start_data_ty.HdlSome(v) + } else { + #[hdl(sim)] + memory_interface_start_data_ty.HdlNone() + }, + ) + .await; + sim.write( + to_decode_fetched.data, + if let Some(v) = state.clone().to_decode_fetched() { + #[hdl(sim)] + to_decode_fetched_data_ty.HdlSome(v) + } else { + #[hdl(sim)] + to_decode_fetched_data_ty.HdlNone() + }, + ) + .await; + state.write_debug_state(&mut sim).await; + sim.write(max_cancel_in_fetch, state.queue.len()).await; + state + .wait_for_clock_edge_while_updating( + &mut sim, + cd.clk, + from_next_pc.next_fetch_block_ids, + to_decode_next_fetch_block_ids, + ) + .await; + #[hdl(sim)] + if let HdlSome(next_fetch_block_ids) = sim + .read_past(memory_interface.next_fetch_block_ids, cd.clk) + .await + { + state.check_memory_next_fetch_block_ids(next_fetch_block_ids); + } + if sim + .read_past_bool(memory_interface.start.ready, cd.clk) + .await + { + state.try_start_memory_operation(); + } + if sim.read_past_bool(to_decode_fetched.ready, cd.clk).await { + state.to_decode_fetched(); + } + if sim.read_past_bool(i_cache_port.en, cd.clk).await + && !sim.read_past_bool(i_cache_port.wmode, cd.clk).await + { + let addr = sim.read_past(i_cache_port.addr, cd.clk).await; + let cache_line = sim.read_past(i_cache_port.rdata, cd.clk).await; + state.cache_read_data( + #[hdl(sim)] + CacheReadData::<_> { + cache_line_index: addr.cast_to(cache_read_data_ty.cache_line_index), + cache_line, + }, + ); + } + let mut write_back_step = None; + if sim + .read_past_bool(memory_interface.finish.ready, cd.clk) + .await + { + let Some(ready_for_memory_operation_finish) = ready_for_memory_operation_finish + else { + unreachable!(); + }; + #[hdl(sim)] + if let HdlSome(memory_operation_finish) = + sim.read_past(memory_interface.finish.data, cd.clk).await + { + write_back_step = state.do_memory_operation_finish( + ready_for_memory_operation_finish, + memory_operation_finish, + ); + } + } else { + assert!(ready_for_memory_operation_finish.is_none()); + } + // handle cancels before pushing new fetch op + if sim.read_past_bool(from_next_pc.cancel.ready, cd.clk).await { + #[hdl(sim)] + if let HdlSome(in_progress_fetches_to_cancel) = + sim.read_past(from_next_pc.cancel.data, cd.clk).await + { + state.cancel_fetches(*in_progress_fetches_to_cancel); + } + } + if let Some(ready_for_fetch) = ready_for_fetch { + assert_eq!( + sim.read_past_bool(from_next_pc.fetch.ready, cd.clk).await, + true, + ); + // handle pushing new fetch op after handling cancels + #[hdl(sim)] + if let HdlSome(fetch) = sim.read_past(from_next_pc.fetch.data, cd.clk).await { + state.do_fetch(ready_for_fetch, fetch); + } + } else { + println!("l1_i_cache_impl: not ready to start fetch"); + assert_eq!( + sim.read_past_bool(from_next_pc.fetch.ready, cd.clk).await, + false, + ); + } + if let Some(write_back_step) = write_back_step { + #[hdl(sim)] + let WriteBackStep::<_> { + cache_line_index, + data, + mask, + } = write_back_step; + #[hdl] + let ReadWriteStruct::<_, _> { + addr, + en, + clk: _, // externally overridden with cd.clk + rdata: _, + wmode, + wdata, + wmask, + } = i_cache_port; + sim.write(addr, cache_line_index.cast_to(addr.ty())).await; + sim.write(en, true).await; + sim.write(wmode, true).await; + sim.write(wdata, data).await; + sim.write(wmask, mask).await; + } else if let Some(cache_read) = state.next_cache_read() { + #[hdl] + let CacheRead::<_> { + cache_line_index, + config: _, + } = cache_read; + #[hdl] + let ReadWriteStruct::<_, _> { + addr, + en, + clk: _, // externally overridden with cd.clk + rdata: _, + wmode, + wdata, + wmask, + } = i_cache_port; + sim.write(addr, cache_line_index.cast_to(addr.ty())).await; + sim.write(en, true).await; + sim.write(wmode, false).await; + sim.write(wdata, CacheLine::sim_value_default(wdata.ty())) + .await; + sim.write(wmask, splat_mask(cache_line_ty, false.to_expr())) + .await; + } else { + #[hdl] + let ReadWriteStruct::<_, _> { + addr, + en, + clk: _, // externally overridden with cd.clk + rdata: _, + wmode, + wdata, + wmask, + } = i_cache_port; + sim.write(addr, 0u8.cast_to(addr.ty())).await; + sim.write(en, false).await; + sim.write(wmode, false).await; + sim.write(wdata, CacheLine::sim_value_default(wdata.ty())) + .await; + sim.write(wmask, splat_mask(cache_line_ty, false.to_expr())) + .await; + } + } + } + m.extern_module_simulation_fn( + ( + cd, + memory_interface, + from_next_pc, + to_decode_fetched, + to_decode_next_fetch_block_ids, + max_cancel_in_fetch, + i_cache_port, + state_for_debug, + ), + |( + cd, + memory_interface, + from_next_pc, + to_decode_fetched, + to_decode_next_fetch_block_ids, + max_cancel_in_fetch, + i_cache_port, + state_for_debug, + ), + mut sim| async move { + let config = memory_interface.ty().config; + let cache_line_ty = CacheLine[config]; + sim.write(i_cache_port.clk, false).await; // externally overridden with cd.clk, so just write a constant here + sim.resettable( + cd, + |mut sim: ExternModuleSimulationState| async move { + sim.write( + memory_interface.start.data, + memory_interface.ty().start.data.HdlNone(), + ) + .await; + sim.write(memory_interface.finish.ready, false).await; + sim.write( + from_next_pc.next_fetch_block_ids, + from_next_pc.ty().next_fetch_block_ids.HdlNone(), + ) + .await; + sim.write(from_next_pc.fetch.ready, false).await; + sim.write(from_next_pc.cancel.ready, false).await; + sim.write( + to_decode_fetched.data, + to_decode_fetched.ty().data.HdlNone(), + ) + .await; + sim.write(max_cancel_in_fetch, 0usize).await; + sim.write(i_cache_port.addr, 0u8.cast_to(i_cache_port.addr.ty())) + .await; + sim.write(i_cache_port.en, false).await; + sim.write(i_cache_port.wmode, false).await; + sim.write( + i_cache_port.wdata, + CacheLine::sim_value_default(cache_line_ty), + ) + .await; + sim.write( + i_cache_port.wmask, + splat_mask(cache_line_ty, false.to_expr()), + ) + .await; + sim.write(state_for_debug, state_for_debug.ty().sim_value_default()) + .await; + }, + |sim, ()| { + run( + sim, + cd, + memory_interface, + from_next_pc, + to_decode_fetched, + to_decode_next_fetch_block_ids, + max_cancel_in_fetch, + i_cache_port, + state_for_debug, + ) + }, + ) + .await; + }, + ); +} + +/// implements a direct-mapped L1 I-Cache +#[hdl_module] +pub fn l1_i_cache(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let memory_interface: MemoryInterface> = + m.output(MemoryInterface[config]); + #[hdl] + let from_next_pc: NextPcToFetchInterface> = + m.input(NextPcToFetchInterface[config]); + #[hdl] + let to_decode: FetchToDecodeInterface> = + m.output(FetchToDecodeInterface[config]); + let cache_line_ty = CacheLine[config]; + let cache_line_count = CpuConfigL1ICacheLineCount[config]; + // TODO: convert to memory with single read/write port once semantics + // for read/write latencies are properly implemented in the simulator: + // https://git.libre-chip.org/libre-chip/fayalite/src/commit/c632e5d570d4763e8e18d764e95b7a9e515ebf99/crates/fayalite/src/sim/compiler.rs#L4774 + // which depends on: + // https://github.com/chipsalliance/firrtl-spec/issues/263 + #[hdl] + let i_cache = reg_builder() + .clock_domain(cd) + .no_reset(ArrayType[cache_line_ty][cache_line_count]); + #[hdl] + let l1_i_cache_impl = instance(l1_i_cache_impl(config)); + connect(l1_i_cache_impl.cd, cd); + connect(memory_interface, l1_i_cache_impl.memory_interface); + connect(l1_i_cache_impl.from_next_pc, from_next_pc); + connect(to_decode.fetched, l1_i_cache_impl.to_decode_fetched); + connect( + l1_i_cache_impl.to_decode_next_fetch_block_ids, + to_decode.next_fetch_block_ids, + ); + let to_decode_cancel_ty = to_decode.cancel.ty(); + connect(to_decode.cancel, to_decode_cancel_ty.HdlNone()); + #[hdl] + if from_next_pc.cancel.ready { + #[hdl] + if let HdlSome(cancel) = from_next_pc.cancel.data { + let cancel = cancel.cast_to(UInt[cancel.ty().bit_width()]); + #[hdl] + if cancel.cmp_gt(l1_i_cache_impl.max_cancel_in_fetch) { + connect( + to_decode.cancel, + to_decode_cancel_ty.HdlSome( + (cancel - l1_i_cache_impl.max_cancel_in_fetch.cast_to(cancel.ty())) + .cast_to(to_decode_cancel_ty.HdlSome), + ), + ); + } + } + } + #[hdl] + let ReadWriteStruct::<_, _> { + addr, + en, + clk: _, + rdata, + wmode, + wdata, + wmask, + } = l1_i_cache_impl.i_cache_port; + connect(rdata, rdata.ty().uninit()); + #[hdl] + if en { + let i_cache_line = i_cache[addr]; + #[hdl] + if wmode { + #[hdl] + let CacheLine::<_> { + data: wdata_data, + addr: wdata_addr, + config: _, + } = wdata; + for ((dest, src), mask) in i_cache_line + .data + .into_iter() + .zip(wdata_data) + .zip(wmask.data) + { + for ((dest, src), mask) in dest.into_iter().zip(src).zip(mask) { + #[hdl] + if mask { + connect(dest, src); + } + } + } + #[hdl] + if wmask.addr { + connect(i_cache_line.addr, wdata_addr); + } + } else { + connect(rdata, i_cache_line); + } + } +} + +#[hdl_module] +pub fn fetch(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let memory_interface: MemoryInterface> = + m.output(MemoryInterface[config]); + #[hdl] + let from_next_pc: NextPcToFetchInterface> = + m.input(NextPcToFetchInterface[config]); + #[hdl] + let to_decode: FetchToDecodeInterface> = + m.output(FetchToDecodeInterface[config]); + #[hdl] + let l1_i_cache = instance(l1_i_cache(config)); + connect(l1_i_cache.cd, cd); + connect(memory_interface, l1_i_cache.memory_interface); + connect(l1_i_cache.from_next_pc, from_next_pc); + connect(to_decode, l1_i_cache.to_decode); +} diff --git a/crates/cpu/src/lib.rs b/crates/cpu/src/lib.rs index 7992ec5..62936de 100644 --- a/crates/cpu/src/lib.rs +++ b/crates/cpu/src/lib.rs @@ -2,6 +2,7 @@ // See Notices.txt for copyright information pub mod config; pub mod decoder; +pub mod fetch; pub mod instruction; pub mod next_pc; pub mod powerisa_instructions_xml; diff --git a/crates/cpu/src/next_pc.rs b/crates/cpu/src/next_pc.rs index db22f7e..fcc5286 100644 --- a/crates/cpu/src/next_pc.rs +++ b/crates/cpu/src/next_pc.rs @@ -46,6 +46,7 @@ pub struct NextPcToFetchInterface> { pub fetch: ReadyValid, /// when both fetch and cancel are triggered in the same clock cycle, that means to cancel and then start a new fetch pub cancel: ReadyValid, CpuConfigMaxFetchesInFlight>>, + /// for debugging #[hdl(flip)] pub next_fetch_block_ids: HdlOption, CpuConfigMaxFetchesInFlight>>, @@ -2719,13 +2720,13 @@ impl SimValueDefault for BranchPredictionState { #[derive(Copy, Clone, Debug)] #[must_use] -enum ResetStatus { +pub(crate) enum ResetStatus { Done, Working, } impl ResetStatus { - fn and(self, other: Self) -> Self { + pub(crate) fn and(self, other: Self) -> Self { match (self, other) { (ResetStatus::Done, ResetStatus::Done) => ResetStatus::Done, (ResetStatus::Done | ResetStatus::Working, ResetStatus::Working) @@ -2734,7 +2735,7 @@ impl ResetStatus { } } -trait SimValueDefault: Type { +pub(crate) trait SimValueDefault: Type { fn sim_value_default(self) -> SimValue; } @@ -2828,7 +2829,7 @@ impl SimValueDefault for WipDecodedInsn { } } -trait ResetSteps: Type { +pub(crate) trait ResetSteps: Type { fn reset_step(this: &mut SimValue, step: usize) -> ResetStatus; } diff --git a/crates/cpu/src/util/array_vec.rs b/crates/cpu/src/util/array_vec.rs index 71275b1..b4ac8f0 100644 --- a/crates/cpu/src/util/array_vec.rs +++ b/crates/cpu/src/util/array_vec.rs @@ -2,6 +2,24 @@ // See Notices.txt for copyright information use fayalite::{expr::ops::ExprIndex, int::UIntInRangeInclusiveType, prelude::*}; +use std::fmt; + +#[derive(Clone, Debug)] +pub struct ArrayVecFullError { + pub value: V, + pub rest: std::iter::Chain, I>, +} + +impl fmt::Display for ArrayVecFullError { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!(f, "ArrayVec is full") + } +} + +impl + fmt::Debug> std::error::Error + for ArrayVecFullError +{ +} #[hdl] pub type Length = UIntInRangeInclusiveType, Max>; @@ -46,6 +64,30 @@ impl ArrayVec { len: self.elements.len().to_sim_value_with_type(self.len), } } + pub fn from_iter_sim>>( + self, + uninit_element: impl ToSimValueWithType, + iter: I, + ) -> Result, ArrayVecFullError, I::IntoIter>> { + let mut value = Self::new_sim(self, uninit_element); + let element = self.element(); + let mut iter = iter.into_iter(); + for i in 0..self.capacity() { + let Some(v) = iter.next() else { + break; + }; + value.elements[i] = v.into_sim_value_with_type(element); + *value.len = i + 1; + } + if let Some(extra) = iter.next() { + Err(ArrayVecFullError { + value, + rest: std::iter::once(extra).chain(iter), + }) + } else { + Ok(value) + } + } pub fn element(self) -> T { self.elements.element() } diff --git a/crates/cpu/tests/expected/fetch.vcd b/crates/cpu/tests/expected/fetch.vcd new file mode 100644 index 0000000..7348f46 --- /dev/null +++ b/crates/cpu/tests/expected/fetch.vcd @@ -0,0 +1,22960 @@ +$timescale 1 ps $end +$scope module dut $end +$scope struct cd $end +$var wire 1 ! clk $end +$var wire 1 " rst $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 # \$tag $end +$scope struct HdlSome $end +$var wire 64 $ start_pc $end +$var wire 8 % fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 & ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 ' \$tag $end +$scope struct HdlSome $end +$var wire 5 ( value $end +$var string 1 ) range $end +$upscope $end +$upscope $end +$var wire 1 * ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 + \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 , \[0] $end +$var wire 8 - \[1] $end +$var wire 8 . \[2] $end +$var wire 8 / \[3] $end +$var wire 8 0 \[4] $end +$var wire 8 1 \[5] $end +$var wire 8 2 \[6] $end +$var wire 8 3 \[7] $end +$var wire 8 4 \[8] $end +$var wire 8 5 \[9] $end +$var wire 8 6 \[10] $end +$var wire 8 7 \[11] $end +$var wire 8 8 \[12] $end +$var wire 8 9 \[13] $end +$var wire 8 : \[14] $end +$var wire 8 ; \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 < value $end +$var string 1 = range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 > config $end +$upscope $end +$scope struct to_decode $end +$scope struct fetched $end +$scope struct data $end +$var string 1 ? \$tag $end +$scope struct HdlSome $end +$var wire 64 @ start_pc $end +$var wire 8 A fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 B \[0] $end +$var wire 8 C \[1] $end +$var wire 8 D \[2] $end +$var wire 8 E \[3] $end +$var wire 8 F \[4] $end +$var wire 8 G \[5] $end +$var wire 8 H \[6] $end +$var wire 8 I \[7] $end +$upscope $end +$scope struct error $end +$var string 1 J \$tag $end +$var string 1 K HdlSome $end +$upscope $end +$var string 1 L config $end +$upscope $end +$upscope $end +$var wire 1 M ready $end +$upscope $end +$scope struct cancel $end +$var string 1 N \$tag $end +$scope struct HdlSome $end +$var wire 5 O value $end +$var string 1 P range $end +$upscope $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 Q \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 R \[0] $end +$var wire 8 S \[1] $end +$var wire 8 T \[2] $end +$var wire 8 U \[3] $end +$var wire 8 V \[4] $end +$var wire 8 W \[5] $end +$var wire 8 X \[6] $end +$var wire 8 Y \[7] $end +$var wire 8 Z \[8] $end +$var wire 8 [ \[9] $end +$var wire 8 \ \[10] $end +$var wire 8 ] \[11] $end +$var wire 8 ^ \[12] $end +$var wire 8 _ \[13] $end +$var wire 8 ` \[14] $end +$var wire 8 a \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 b value $end +$var string 1 c range $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct fetch $end +$scope struct cd $end +$var wire 1 E5 clk $end +$var wire 1 F5 rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 G5 \$tag $end +$scope struct HdlSome $end +$var string 1 H5 kind $end +$var wire 64 I5 addr $end +$scope struct write_data $end +$var wire 8 J5 \[0] $end +$var wire 8 K5 \[1] $end +$var wire 8 L5 \[2] $end +$var wire 8 M5 \[3] $end +$var wire 8 N5 \[4] $end +$var wire 8 O5 \[5] $end +$var wire 8 P5 \[6] $end +$var wire 8 Q5 \[7] $end +$upscope $end +$var wire 8 R5 fetch_block_id $end +$var string 1 S5 config $end +$upscope $end +$upscope $end +$var wire 1 T5 ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 U5 \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 V5 \$tag $end +$var string 1 W5 Success $end +$var string 1 X5 Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 Y5 \[0] $end +$var wire 8 Z5 \[1] $end +$var wire 8 [5 \[2] $end +$var wire 8 \5 \[3] $end +$var wire 8 ]5 \[4] $end +$var wire 8 ^5 \[5] $end +$var wire 8 _5 \[6] $end +$var wire 8 `5 \[7] $end +$upscope $end +$var string 1 a5 config $end +$upscope $end +$upscope $end +$var wire 1 b5 ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 c5 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 d5 \[0] $end +$var wire 8 e5 \[1] $end +$var wire 8 f5 \[2] $end +$var wire 8 g5 \[3] $end +$var wire 8 h5 \[4] $end +$var wire 8 i5 \[5] $end +$var wire 8 j5 \[6] $end +$var wire 8 k5 \[7] $end +$var wire 8 l5 \[8] $end +$var wire 8 m5 \[9] $end +$var wire 8 n5 \[10] $end +$var wire 8 o5 \[11] $end +$var wire 8 p5 \[12] $end +$var wire 8 q5 \[13] $end +$var wire 8 r5 \[14] $end +$var wire 8 s5 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 t5 value $end +$var string 1 u5 range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 v5 config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 w5 \$tag $end +$scope struct HdlSome $end +$var wire 64 x5 start_pc $end +$var wire 8 y5 fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 z5 ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 {5 \$tag $end +$scope struct HdlSome $end +$var wire 5 |5 value $end +$var string 1 }5 range $end +$upscope $end +$upscope $end +$var wire 1 ~5 ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 !6 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 "6 \[0] $end +$var wire 8 #6 \[1] $end +$var wire 8 $6 \[2] $end +$var wire 8 %6 \[3] $end +$var wire 8 &6 \[4] $end +$var wire 8 '6 \[5] $end +$var wire 8 (6 \[6] $end +$var wire 8 )6 \[7] $end +$var wire 8 *6 \[8] $end +$var wire 8 +6 \[9] $end +$var wire 8 ,6 \[10] $end +$var wire 8 -6 \[11] $end +$var wire 8 .6 \[12] $end +$var wire 8 /6 \[13] $end +$var wire 8 06 \[14] $end +$var wire 8 16 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 26 value $end +$var string 1 36 range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 46 config $end +$upscope $end +$scope struct to_decode $end +$scope struct fetched $end +$scope struct data $end +$var string 1 56 \$tag $end +$scope struct HdlSome $end +$var wire 64 66 start_pc $end +$var wire 8 76 fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 86 \[0] $end +$var wire 8 96 \[1] $end +$var wire 8 :6 \[2] $end +$var wire 8 ;6 \[3] $end +$var wire 8 <6 \[4] $end +$var wire 8 =6 \[5] $end +$var wire 8 >6 \[6] $end +$var wire 8 ?6 \[7] $end +$upscope $end +$scope struct error $end +$var string 1 @6 \$tag $end +$var string 1 A6 HdlSome $end +$upscope $end +$var string 1 B6 config $end +$upscope $end +$upscope $end +$var wire 1 C6 ready $end +$upscope $end +$scope struct cancel $end +$var string 1 D6 \$tag $end +$scope struct HdlSome $end +$var wire 5 E6 value $end +$var string 1 F6 range $end +$upscope $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 G6 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 H6 \[0] $end +$var wire 8 I6 \[1] $end +$var wire 8 J6 \[2] $end +$var wire 8 K6 \[3] $end +$var wire 8 L6 \[4] $end +$var wire 8 M6 \[5] $end +$var wire 8 N6 \[6] $end +$var wire 8 O6 \[7] $end +$var wire 8 P6 \[8] $end +$var wire 8 Q6 \[9] $end +$var wire 8 R6 \[10] $end +$var wire 8 S6 \[11] $end +$var wire 8 T6 \[12] $end +$var wire 8 U6 \[13] $end +$var wire 8 V6 \[14] $end +$var wire 8 W6 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 X6 value $end +$var string 1 Y6 range $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module fetch_2 $end +$scope struct cd $end +$var wire 1 d clk $end +$var wire 1 e rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 f \$tag $end +$scope struct HdlSome $end +$var string 1 g kind $end +$var wire 64 h addr $end +$scope struct write_data $end +$var wire 8 i \[0] $end +$var wire 8 j \[1] $end +$var wire 8 k \[2] $end +$var wire 8 l \[3] $end +$var wire 8 m \[4] $end +$var wire 8 n \[5] $end +$var wire 8 o \[6] $end +$var wire 8 p \[7] $end +$upscope $end +$var wire 8 q fetch_block_id $end +$var string 1 r config $end +$upscope $end +$upscope $end +$var wire 1 s ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 t \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 u \$tag $end +$var string 1 v Success $end +$var string 1 w Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 x \[0] $end +$var wire 8 y \[1] $end +$var wire 8 z \[2] $end +$var wire 8 { \[3] $end +$var wire 8 | \[4] $end +$var wire 8 } \[5] $end +$var wire 8 ~ \[6] $end +$var wire 8 !" \[7] $end +$upscope $end +$var string 1 "" config $end +$upscope $end +$upscope $end +$var wire 1 #" ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 $" \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 %" \[0] $end +$var wire 8 &" \[1] $end +$var wire 8 '" \[2] $end +$var wire 8 (" \[3] $end +$var wire 8 )" \[4] $end +$var wire 8 *" \[5] $end +$var wire 8 +" \[6] $end +$var wire 8 ," \[7] $end +$var wire 8 -" \[8] $end +$var wire 8 ." \[9] $end +$var wire 8 /" \[10] $end +$var wire 8 0" \[11] $end +$var wire 8 1" \[12] $end +$var wire 8 2" \[13] $end +$var wire 8 3" \[14] $end +$var wire 8 4" \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 5" value $end +$var string 1 6" range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 7" config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 8" \$tag $end +$scope struct HdlSome $end +$var wire 64 9" start_pc $end +$var wire 8 :" fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 ;" ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 <" \$tag $end +$scope struct HdlSome $end +$var wire 5 =" value $end +$var string 1 >" range $end +$upscope $end +$upscope $end +$var wire 1 ?" ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 @" \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 A" \[0] $end +$var wire 8 B" \[1] $end +$var wire 8 C" \[2] $end +$var wire 8 D" \[3] $end +$var wire 8 E" \[4] $end +$var wire 8 F" \[5] $end +$var wire 8 G" \[6] $end +$var wire 8 H" \[7] $end +$var wire 8 I" \[8] $end +$var wire 8 J" \[9] $end +$var wire 8 K" \[10] $end +$var wire 8 L" \[11] $end +$var wire 8 M" \[12] $end +$var wire 8 N" \[13] $end +$var wire 8 O" \[14] $end +$var wire 8 P" \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 Q" value $end +$var string 1 R" range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 S" config $end +$upscope $end +$scope struct to_decode $end +$scope struct fetched $end +$scope struct data $end +$var string 1 T" \$tag $end +$scope struct HdlSome $end +$var wire 64 U" start_pc $end +$var wire 8 V" fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 W" \[0] $end +$var wire 8 X" \[1] $end +$var wire 8 Y" \[2] $end +$var wire 8 Z" \[3] $end +$var wire 8 [" \[4] $end +$var wire 8 \" \[5] $end +$var wire 8 ]" \[6] $end +$var wire 8 ^" \[7] $end +$upscope $end +$scope struct error $end +$var string 1 _" \$tag $end +$var string 1 `" HdlSome $end +$upscope $end +$var string 1 a" config $end +$upscope $end +$upscope $end +$var wire 1 b" ready $end +$upscope $end +$scope struct cancel $end +$var string 1 c" \$tag $end +$scope struct HdlSome $end +$var wire 5 d" value $end +$var string 1 e" range $end +$upscope $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 f" \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 g" \[0] $end +$var wire 8 h" \[1] $end +$var wire 8 i" \[2] $end +$var wire 8 j" \[3] $end +$var wire 8 k" \[4] $end +$var wire 8 l" \[5] $end +$var wire 8 m" \[6] $end +$var wire 8 n" \[7] $end +$var wire 8 o" \[8] $end +$var wire 8 p" \[9] $end +$var wire 8 q" \[10] $end +$var wire 8 r" \[11] $end +$var wire 8 s" \[12] $end +$var wire 8 t" \[13] $end +$var wire 8 u" \[14] $end +$var wire 8 v" \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 w" value $end +$var string 1 x" range $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct l1_i_cache $end +$scope struct cd $end +$var wire 1 04 clk $end +$var wire 1 14 rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 24 \$tag $end +$scope struct HdlSome $end +$var string 1 34 kind $end +$var wire 64 44 addr $end +$scope struct write_data $end +$var wire 8 54 \[0] $end +$var wire 8 64 \[1] $end +$var wire 8 74 \[2] $end +$var wire 8 84 \[3] $end +$var wire 8 94 \[4] $end +$var wire 8 :4 \[5] $end +$var wire 8 ;4 \[6] $end +$var wire 8 <4 \[7] $end +$upscope $end +$var wire 8 =4 fetch_block_id $end +$var string 1 >4 config $end +$upscope $end +$upscope $end +$var wire 1 ?4 ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 @4 \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 A4 \$tag $end +$var string 1 B4 Success $end +$var string 1 C4 Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 D4 \[0] $end +$var wire 8 E4 \[1] $end +$var wire 8 F4 \[2] $end +$var wire 8 G4 \[3] $end +$var wire 8 H4 \[4] $end +$var wire 8 I4 \[5] $end +$var wire 8 J4 \[6] $end +$var wire 8 K4 \[7] $end +$upscope $end +$var string 1 L4 config $end +$upscope $end +$upscope $end +$var wire 1 M4 ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 N4 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 O4 \[0] $end +$var wire 8 P4 \[1] $end +$var wire 8 Q4 \[2] $end +$var wire 8 R4 \[3] $end +$var wire 8 S4 \[4] $end +$var wire 8 T4 \[5] $end +$var wire 8 U4 \[6] $end +$var wire 8 V4 \[7] $end +$var wire 8 W4 \[8] $end +$var wire 8 X4 \[9] $end +$var wire 8 Y4 \[10] $end +$var wire 8 Z4 \[11] $end +$var wire 8 [4 \[12] $end +$var wire 8 \4 \[13] $end +$var wire 8 ]4 \[14] $end +$var wire 8 ^4 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 _4 value $end +$var string 1 `4 range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 a4 config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 b4 \$tag $end +$scope struct HdlSome $end +$var wire 64 c4 start_pc $end +$var wire 8 d4 fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 e4 ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 f4 \$tag $end +$scope struct HdlSome $end +$var wire 5 g4 value $end +$var string 1 h4 range $end +$upscope $end +$upscope $end +$var wire 1 i4 ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 j4 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 k4 \[0] $end +$var wire 8 l4 \[1] $end +$var wire 8 m4 \[2] $end +$var wire 8 n4 \[3] $end +$var wire 8 o4 \[4] $end +$var wire 8 p4 \[5] $end +$var wire 8 q4 \[6] $end +$var wire 8 r4 \[7] $end +$var wire 8 s4 \[8] $end +$var wire 8 t4 \[9] $end +$var wire 8 u4 \[10] $end +$var wire 8 v4 \[11] $end +$var wire 8 w4 \[12] $end +$var wire 8 x4 \[13] $end +$var wire 8 y4 \[14] $end +$var wire 8 z4 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 {4 value $end +$var string 1 |4 range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 }4 config $end +$upscope $end +$scope struct to_decode $end +$scope struct fetched $end +$scope struct data $end +$var string 1 ~4 \$tag $end +$scope struct HdlSome $end +$var wire 64 !5 start_pc $end +$var wire 8 "5 fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 #5 \[0] $end +$var wire 8 $5 \[1] $end +$var wire 8 %5 \[2] $end +$var wire 8 &5 \[3] $end +$var wire 8 '5 \[4] $end +$var wire 8 (5 \[5] $end +$var wire 8 )5 \[6] $end +$var wire 8 *5 \[7] $end +$upscope $end +$scope struct error $end +$var string 1 +5 \$tag $end +$var string 1 ,5 HdlSome $end +$upscope $end +$var string 1 -5 config $end +$upscope $end +$upscope $end +$var wire 1 .5 ready $end +$upscope $end +$scope struct cancel $end +$var string 1 /5 \$tag $end +$scope struct HdlSome $end +$var wire 5 05 value $end +$var string 1 15 range $end +$upscope $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 25 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 35 \[0] $end +$var wire 8 45 \[1] $end +$var wire 8 55 \[2] $end +$var wire 8 65 \[3] $end +$var wire 8 75 \[4] $end +$var wire 8 85 \[5] $end +$var wire 8 95 \[6] $end +$var wire 8 :5 \[7] $end +$var wire 8 ;5 \[8] $end +$var wire 8 <5 \[9] $end +$var wire 8 =5 \[10] $end +$var wire 8 >5 \[11] $end +$var wire 8 ?5 \[12] $end +$var wire 8 @5 \[13] $end +$var wire 8 A5 \[14] $end +$var wire 8 B5 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 C5 value $end +$var string 1 D5 range $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module l1_i_cache_2 $end +$scope struct cd $end +$var wire 1 y" clk $end +$var wire 1 z" rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 {" \$tag $end +$scope struct HdlSome $end +$var string 1 |" kind $end +$var wire 64 }" addr $end +$scope struct write_data $end +$var wire 8 ~" \[0] $end +$var wire 8 !# \[1] $end +$var wire 8 "# \[2] $end +$var wire 8 ## \[3] $end +$var wire 8 $# \[4] $end +$var wire 8 %# \[5] $end +$var wire 8 &# \[6] $end +$var wire 8 '# \[7] $end +$upscope $end +$var wire 8 (# fetch_block_id $end +$var string 1 )# config $end +$upscope $end +$upscope $end +$var wire 1 *# ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 +# \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 ,# \$tag $end +$var string 1 -# Success $end +$var string 1 .# Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 /# \[0] $end +$var wire 8 0# \[1] $end +$var wire 8 1# \[2] $end +$var wire 8 2# \[3] $end +$var wire 8 3# \[4] $end +$var wire 8 4# \[5] $end +$var wire 8 5# \[6] $end +$var wire 8 6# \[7] $end +$upscope $end +$var string 1 7# config $end +$upscope $end +$upscope $end +$var wire 1 8# ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 9# \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 :# \[0] $end +$var wire 8 ;# \[1] $end +$var wire 8 <# \[2] $end +$var wire 8 =# \[3] $end +$var wire 8 ># \[4] $end +$var wire 8 ?# \[5] $end +$var wire 8 @# \[6] $end +$var wire 8 A# \[7] $end +$var wire 8 B# \[8] $end +$var wire 8 C# \[9] $end +$var wire 8 D# \[10] $end +$var wire 8 E# \[11] $end +$var wire 8 F# \[12] $end +$var wire 8 G# \[13] $end +$var wire 8 H# \[14] $end +$var wire 8 I# \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 J# value $end +$var string 1 K# range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 L# config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 M# \$tag $end +$scope struct HdlSome $end +$var wire 64 N# start_pc $end +$var wire 8 O# fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 P# ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 Q# \$tag $end +$scope struct HdlSome $end +$var wire 5 R# value $end +$var string 1 S# range $end +$upscope $end +$upscope $end +$var wire 1 T# ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 U# \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 V# \[0] $end +$var wire 8 W# \[1] $end +$var wire 8 X# \[2] $end +$var wire 8 Y# \[3] $end +$var wire 8 Z# \[4] $end +$var wire 8 [# \[5] $end +$var wire 8 \# \[6] $end +$var wire 8 ]# \[7] $end +$var wire 8 ^# \[8] $end +$var wire 8 _# \[9] $end +$var wire 8 `# \[10] $end +$var wire 8 a# \[11] $end +$var wire 8 b# \[12] $end +$var wire 8 c# \[13] $end +$var wire 8 d# \[14] $end +$var wire 8 e# \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 f# value $end +$var string 1 g# range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 h# config $end +$upscope $end +$scope struct to_decode $end +$scope struct fetched $end +$scope struct data $end +$var string 1 i# \$tag $end +$scope struct HdlSome $end +$var wire 64 j# start_pc $end +$var wire 8 k# fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 l# \[0] $end +$var wire 8 m# \[1] $end +$var wire 8 n# \[2] $end +$var wire 8 o# \[3] $end +$var wire 8 p# \[4] $end +$var wire 8 q# \[5] $end +$var wire 8 r# \[6] $end +$var wire 8 s# \[7] $end +$upscope $end +$scope struct error $end +$var string 1 t# \$tag $end +$var string 1 u# HdlSome $end +$upscope $end +$var string 1 v# config $end +$upscope $end +$upscope $end +$var wire 1 w# ready $end +$upscope $end +$scope struct cancel $end +$var string 1 x# \$tag $end +$scope struct HdlSome $end +$var wire 5 y# value $end +$var string 1 z# range $end +$upscope $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 {# \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 |# \[0] $end +$var wire 8 }# \[1] $end +$var wire 8 ~# \[2] $end +$var wire 8 !$ \[3] $end +$var wire 8 "$ \[4] $end +$var wire 8 #$ \[5] $end +$var wire 8 $$ \[6] $end +$var wire 8 %$ \[7] $end +$var wire 8 &$ \[8] $end +$var wire 8 '$ \[9] $end +$var wire 8 ($ \[10] $end +$var wire 8 )$ \[11] $end +$var wire 8 *$ \[12] $end +$var wire 8 +$ \[13] $end +$var wire 8 ,$ \[14] $end +$var wire 8 -$ \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 .$ value $end +$var string 1 /$ range $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct i_cache $end +$scope struct \[0] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 0$ \[0] $end +$var reg 8 1$ \[1] $end +$var reg 8 2$ \[2] $end +$var reg 8 3$ \[3] $end +$var reg 8 4$ \[4] $end +$var reg 8 5$ \[5] $end +$var reg 8 6$ \[6] $end +$var reg 8 7$ \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 8$ \[0] $end +$var reg 8 9$ \[1] $end +$var reg 8 :$ \[2] $end +$var reg 8 ;$ \[3] $end +$var reg 8 <$ \[4] $end +$var reg 8 =$ \[5] $end +$var reg 8 >$ \[6] $end +$var reg 8 ?$ \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 @$ \[0] $end +$var reg 8 A$ \[1] $end +$var reg 8 B$ \[2] $end +$var reg 8 C$ \[3] $end +$var reg 8 D$ \[4] $end +$var reg 8 E$ \[5] $end +$var reg 8 F$ \[6] $end +$var reg 8 G$ \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 H$ \[0] $end +$var reg 8 I$ \[1] $end +$var reg 8 J$ \[2] $end +$var reg 8 K$ \[3] $end +$var reg 8 L$ \[4] $end +$var reg 8 M$ \[5] $end +$var reg 8 N$ \[6] $end +$var reg 8 O$ \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 P$ \$tag $end +$var reg 55 Q$ HdlSome $end +$upscope $end +$var string 1 R$ config $end +$upscope $end +$scope struct \[1] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 S$ \[0] $end +$var reg 8 T$ \[1] $end +$var reg 8 U$ \[2] $end +$var reg 8 V$ \[3] $end +$var reg 8 W$ \[4] $end +$var reg 8 X$ \[5] $end +$var reg 8 Y$ \[6] $end +$var reg 8 Z$ \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 [$ \[0] $end +$var reg 8 \$ \[1] $end +$var reg 8 ]$ \[2] $end +$var reg 8 ^$ \[3] $end +$var reg 8 _$ \[4] $end +$var reg 8 `$ \[5] $end +$var reg 8 a$ \[6] $end +$var reg 8 b$ \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 c$ \[0] $end +$var reg 8 d$ \[1] $end +$var reg 8 e$ \[2] $end +$var reg 8 f$ \[3] $end +$var reg 8 g$ \[4] $end +$var reg 8 h$ \[5] $end +$var reg 8 i$ \[6] $end +$var reg 8 j$ \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 k$ \[0] $end +$var reg 8 l$ \[1] $end +$var reg 8 m$ \[2] $end +$var reg 8 n$ \[3] $end +$var reg 8 o$ \[4] $end +$var reg 8 p$ \[5] $end +$var reg 8 q$ \[6] $end +$var reg 8 r$ \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 s$ \$tag $end +$var reg 55 t$ HdlSome $end +$upscope $end +$var string 1 u$ config $end +$upscope $end +$scope struct \[2] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 v$ \[0] $end +$var reg 8 w$ \[1] $end +$var reg 8 x$ \[2] $end +$var reg 8 y$ \[3] $end +$var reg 8 z$ \[4] $end +$var reg 8 {$ \[5] $end +$var reg 8 |$ \[6] $end +$var reg 8 }$ \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 ~$ \[0] $end +$var reg 8 !% \[1] $end +$var reg 8 "% \[2] $end +$var reg 8 #% \[3] $end +$var reg 8 $% \[4] $end +$var reg 8 %% \[5] $end +$var reg 8 &% \[6] $end +$var reg 8 '% \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 (% \[0] $end +$var reg 8 )% \[1] $end +$var reg 8 *% \[2] $end +$var reg 8 +% \[3] $end +$var reg 8 ,% \[4] $end +$var reg 8 -% \[5] $end +$var reg 8 .% \[6] $end +$var reg 8 /% \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 0% \[0] $end +$var reg 8 1% \[1] $end +$var reg 8 2% \[2] $end +$var reg 8 3% \[3] $end +$var reg 8 4% \[4] $end +$var reg 8 5% \[5] $end +$var reg 8 6% \[6] $end +$var reg 8 7% \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 8% \$tag $end +$var reg 55 9% HdlSome $end +$upscope $end +$var string 1 :% config $end +$upscope $end +$scope struct \[3] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 ;% \[0] $end +$var reg 8 <% \[1] $end +$var reg 8 =% \[2] $end +$var reg 8 >% \[3] $end +$var reg 8 ?% \[4] $end +$var reg 8 @% \[5] $end +$var reg 8 A% \[6] $end +$var reg 8 B% \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 C% \[0] $end +$var reg 8 D% \[1] $end +$var reg 8 E% \[2] $end +$var reg 8 F% \[3] $end +$var reg 8 G% \[4] $end +$var reg 8 H% \[5] $end +$var reg 8 I% \[6] $end +$var reg 8 J% \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 K% \[0] $end +$var reg 8 L% \[1] $end +$var reg 8 M% \[2] $end +$var reg 8 N% \[3] $end +$var reg 8 O% \[4] $end +$var reg 8 P% \[5] $end +$var reg 8 Q% \[6] $end +$var reg 8 R% \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 S% \[0] $end +$var reg 8 T% \[1] $end +$var reg 8 U% \[2] $end +$var reg 8 V% \[3] $end +$var reg 8 W% \[4] $end +$var reg 8 X% \[5] $end +$var reg 8 Y% \[6] $end +$var reg 8 Z% \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 [% \$tag $end +$var reg 55 \% HdlSome $end +$upscope $end +$var string 1 ]% config $end +$upscope $end +$scope struct \[4] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 ^% \[0] $end +$var reg 8 _% \[1] $end +$var reg 8 `% \[2] $end +$var reg 8 a% \[3] $end +$var reg 8 b% \[4] $end +$var reg 8 c% \[5] $end +$var reg 8 d% \[6] $end +$var reg 8 e% \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 f% \[0] $end +$var reg 8 g% \[1] $end +$var reg 8 h% \[2] $end +$var reg 8 i% \[3] $end +$var reg 8 j% \[4] $end +$var reg 8 k% \[5] $end +$var reg 8 l% \[6] $end +$var reg 8 m% \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 n% \[0] $end +$var reg 8 o% \[1] $end +$var reg 8 p% \[2] $end +$var reg 8 q% \[3] $end +$var reg 8 r% \[4] $end +$var reg 8 s% \[5] $end +$var reg 8 t% \[6] $end +$var reg 8 u% \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 v% \[0] $end +$var reg 8 w% \[1] $end +$var reg 8 x% \[2] $end +$var reg 8 y% \[3] $end +$var reg 8 z% \[4] $end +$var reg 8 {% \[5] $end +$var reg 8 |% \[6] $end +$var reg 8 }% \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 ~% \$tag $end +$var reg 55 !& HdlSome $end +$upscope $end +$var string 1 "& config $end +$upscope $end +$scope struct \[5] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 #& \[0] $end +$var reg 8 $& \[1] $end +$var reg 8 %& \[2] $end +$var reg 8 && \[3] $end +$var reg 8 '& \[4] $end +$var reg 8 (& \[5] $end +$var reg 8 )& \[6] $end +$var reg 8 *& \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 +& \[0] $end +$var reg 8 ,& \[1] $end +$var reg 8 -& \[2] $end +$var reg 8 .& \[3] $end +$var reg 8 /& \[4] $end +$var reg 8 0& \[5] $end +$var reg 8 1& \[6] $end +$var reg 8 2& \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 3& \[0] $end +$var reg 8 4& \[1] $end +$var reg 8 5& \[2] $end +$var reg 8 6& \[3] $end +$var reg 8 7& \[4] $end +$var reg 8 8& \[5] $end +$var reg 8 9& \[6] $end +$var reg 8 :& \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 ;& \[0] $end +$var reg 8 <& \[1] $end +$var reg 8 =& \[2] $end +$var reg 8 >& \[3] $end +$var reg 8 ?& \[4] $end +$var reg 8 @& \[5] $end +$var reg 8 A& \[6] $end +$var reg 8 B& \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 C& \$tag $end +$var reg 55 D& HdlSome $end +$upscope $end +$var string 1 E& config $end +$upscope $end +$scope struct \[6] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 F& \[0] $end +$var reg 8 G& \[1] $end +$var reg 8 H& \[2] $end +$var reg 8 I& \[3] $end +$var reg 8 J& \[4] $end +$var reg 8 K& \[5] $end +$var reg 8 L& \[6] $end +$var reg 8 M& \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 N& \[0] $end +$var reg 8 O& \[1] $end +$var reg 8 P& \[2] $end +$var reg 8 Q& \[3] $end +$var reg 8 R& \[4] $end +$var reg 8 S& \[5] $end +$var reg 8 T& \[6] $end +$var reg 8 U& \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 V& \[0] $end +$var reg 8 W& \[1] $end +$var reg 8 X& \[2] $end +$var reg 8 Y& \[3] $end +$var reg 8 Z& \[4] $end +$var reg 8 [& \[5] $end +$var reg 8 \& \[6] $end +$var reg 8 ]& \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 ^& \[0] $end +$var reg 8 _& \[1] $end +$var reg 8 `& \[2] $end +$var reg 8 a& \[3] $end +$var reg 8 b& \[4] $end +$var reg 8 c& \[5] $end +$var reg 8 d& \[6] $end +$var reg 8 e& \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 f& \$tag $end +$var reg 55 g& HdlSome $end +$upscope $end +$var string 1 h& config $end +$upscope $end +$scope struct \[7] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 i& \[0] $end +$var reg 8 j& \[1] $end +$var reg 8 k& \[2] $end +$var reg 8 l& \[3] $end +$var reg 8 m& \[4] $end +$var reg 8 n& \[5] $end +$var reg 8 o& \[6] $end +$var reg 8 p& \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 q& \[0] $end +$var reg 8 r& \[1] $end +$var reg 8 s& \[2] $end +$var reg 8 t& \[3] $end +$var reg 8 u& \[4] $end +$var reg 8 v& \[5] $end +$var reg 8 w& \[6] $end +$var reg 8 x& \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 y& \[0] $end +$var reg 8 z& \[1] $end +$var reg 8 {& \[2] $end +$var reg 8 |& \[3] $end +$var reg 8 }& \[4] $end +$var reg 8 ~& \[5] $end +$var reg 8 !' \[6] $end +$var reg 8 "' \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 #' \[0] $end +$var reg 8 $' \[1] $end +$var reg 8 %' \[2] $end +$var reg 8 &' \[3] $end +$var reg 8 '' \[4] $end +$var reg 8 (' \[5] $end +$var reg 8 )' \[6] $end +$var reg 8 *' \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 +' \$tag $end +$var reg 55 ,' HdlSome $end +$upscope $end +$var string 1 -' config $end +$upscope $end +$scope struct \[8] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 .' \[0] $end +$var reg 8 /' \[1] $end +$var reg 8 0' \[2] $end +$var reg 8 1' \[3] $end +$var reg 8 2' \[4] $end +$var reg 8 3' \[5] $end +$var reg 8 4' \[6] $end +$var reg 8 5' \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 6' \[0] $end +$var reg 8 7' \[1] $end +$var reg 8 8' \[2] $end +$var reg 8 9' \[3] $end +$var reg 8 :' \[4] $end +$var reg 8 ;' \[5] $end +$var reg 8 <' \[6] $end +$var reg 8 =' \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 >' \[0] $end +$var reg 8 ?' \[1] $end +$var reg 8 @' \[2] $end +$var reg 8 A' \[3] $end +$var reg 8 B' \[4] $end +$var reg 8 C' \[5] $end +$var reg 8 D' \[6] $end +$var reg 8 E' \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 F' \[0] $end +$var reg 8 G' \[1] $end +$var reg 8 H' \[2] $end +$var reg 8 I' \[3] $end +$var reg 8 J' \[4] $end +$var reg 8 K' \[5] $end +$var reg 8 L' \[6] $end +$var reg 8 M' \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 N' \$tag $end +$var reg 55 O' HdlSome $end +$upscope $end +$var string 1 P' config $end +$upscope $end +$scope struct \[9] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 Q' \[0] $end +$var reg 8 R' \[1] $end +$var reg 8 S' \[2] $end +$var reg 8 T' \[3] $end +$var reg 8 U' \[4] $end +$var reg 8 V' \[5] $end +$var reg 8 W' \[6] $end +$var reg 8 X' \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 Y' \[0] $end +$var reg 8 Z' \[1] $end +$var reg 8 [' \[2] $end +$var reg 8 \' \[3] $end +$var reg 8 ]' \[4] $end +$var reg 8 ^' \[5] $end +$var reg 8 _' \[6] $end +$var reg 8 `' \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 a' \[0] $end +$var reg 8 b' \[1] $end +$var reg 8 c' \[2] $end +$var reg 8 d' \[3] $end +$var reg 8 e' \[4] $end +$var reg 8 f' \[5] $end +$var reg 8 g' \[6] $end +$var reg 8 h' \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 i' \[0] $end +$var reg 8 j' \[1] $end +$var reg 8 k' \[2] $end +$var reg 8 l' \[3] $end +$var reg 8 m' \[4] $end +$var reg 8 n' \[5] $end +$var reg 8 o' \[6] $end +$var reg 8 p' \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 q' \$tag $end +$var reg 55 r' HdlSome $end +$upscope $end +$var string 1 s' config $end +$upscope $end +$scope struct \[10] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 t' \[0] $end +$var reg 8 u' \[1] $end +$var reg 8 v' \[2] $end +$var reg 8 w' \[3] $end +$var reg 8 x' \[4] $end +$var reg 8 y' \[5] $end +$var reg 8 z' \[6] $end +$var reg 8 {' \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 |' \[0] $end +$var reg 8 }' \[1] $end +$var reg 8 ~' \[2] $end +$var reg 8 !( \[3] $end +$var reg 8 "( \[4] $end +$var reg 8 #( \[5] $end +$var reg 8 $( \[6] $end +$var reg 8 %( \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 &( \[0] $end +$var reg 8 '( \[1] $end +$var reg 8 (( \[2] $end +$var reg 8 )( \[3] $end +$var reg 8 *( \[4] $end +$var reg 8 +( \[5] $end +$var reg 8 ,( \[6] $end +$var reg 8 -( \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 .( \[0] $end +$var reg 8 /( \[1] $end +$var reg 8 0( \[2] $end +$var reg 8 1( \[3] $end +$var reg 8 2( \[4] $end +$var reg 8 3( \[5] $end +$var reg 8 4( \[6] $end +$var reg 8 5( \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 6( \$tag $end +$var reg 55 7( HdlSome $end +$upscope $end +$var string 1 8( config $end +$upscope $end +$scope struct \[11] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 9( \[0] $end +$var reg 8 :( \[1] $end +$var reg 8 ;( \[2] $end +$var reg 8 <( \[3] $end +$var reg 8 =( \[4] $end +$var reg 8 >( \[5] $end +$var reg 8 ?( \[6] $end +$var reg 8 @( \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 A( \[0] $end +$var reg 8 B( \[1] $end +$var reg 8 C( \[2] $end +$var reg 8 D( \[3] $end +$var reg 8 E( \[4] $end +$var reg 8 F( \[5] $end +$var reg 8 G( \[6] $end +$var reg 8 H( \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 I( \[0] $end +$var reg 8 J( \[1] $end +$var reg 8 K( \[2] $end +$var reg 8 L( \[3] $end +$var reg 8 M( \[4] $end +$var reg 8 N( \[5] $end +$var reg 8 O( \[6] $end +$var reg 8 P( \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 Q( \[0] $end +$var reg 8 R( \[1] $end +$var reg 8 S( \[2] $end +$var reg 8 T( \[3] $end +$var reg 8 U( \[4] $end +$var reg 8 V( \[5] $end +$var reg 8 W( \[6] $end +$var reg 8 X( \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 Y( \$tag $end +$var reg 55 Z( HdlSome $end +$upscope $end +$var string 1 [( config $end +$upscope $end +$scope struct \[12] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 \( \[0] $end +$var reg 8 ]( \[1] $end +$var reg 8 ^( \[2] $end +$var reg 8 _( \[3] $end +$var reg 8 `( \[4] $end +$var reg 8 a( \[5] $end +$var reg 8 b( \[6] $end +$var reg 8 c( \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 d( \[0] $end +$var reg 8 e( \[1] $end +$var reg 8 f( \[2] $end +$var reg 8 g( \[3] $end +$var reg 8 h( \[4] $end +$var reg 8 i( \[5] $end +$var reg 8 j( \[6] $end +$var reg 8 k( \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 l( \[0] $end +$var reg 8 m( \[1] $end +$var reg 8 n( \[2] $end +$var reg 8 o( \[3] $end +$var reg 8 p( \[4] $end +$var reg 8 q( \[5] $end +$var reg 8 r( \[6] $end +$var reg 8 s( \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 t( \[0] $end +$var reg 8 u( \[1] $end +$var reg 8 v( \[2] $end +$var reg 8 w( \[3] $end +$var reg 8 x( \[4] $end +$var reg 8 y( \[5] $end +$var reg 8 z( \[6] $end +$var reg 8 {( \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 |( \$tag $end +$var reg 55 }( HdlSome $end +$upscope $end +$var string 1 ~( config $end +$upscope $end +$scope struct \[13] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 !) \[0] $end +$var reg 8 ") \[1] $end +$var reg 8 #) \[2] $end +$var reg 8 $) \[3] $end +$var reg 8 %) \[4] $end +$var reg 8 &) \[5] $end +$var reg 8 ') \[6] $end +$var reg 8 () \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 )) \[0] $end +$var reg 8 *) \[1] $end +$var reg 8 +) \[2] $end +$var reg 8 ,) \[3] $end +$var reg 8 -) \[4] $end +$var reg 8 .) \[5] $end +$var reg 8 /) \[6] $end +$var reg 8 0) \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 1) \[0] $end +$var reg 8 2) \[1] $end +$var reg 8 3) \[2] $end +$var reg 8 4) \[3] $end +$var reg 8 5) \[4] $end +$var reg 8 6) \[5] $end +$var reg 8 7) \[6] $end +$var reg 8 8) \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 9) \[0] $end +$var reg 8 :) \[1] $end +$var reg 8 ;) \[2] $end +$var reg 8 <) \[3] $end +$var reg 8 =) \[4] $end +$var reg 8 >) \[5] $end +$var reg 8 ?) \[6] $end +$var reg 8 @) \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 A) \$tag $end +$var reg 55 B) HdlSome $end +$upscope $end +$var string 1 C) config $end +$upscope $end +$scope struct \[14] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 D) \[0] $end +$var reg 8 E) \[1] $end +$var reg 8 F) \[2] $end +$var reg 8 G) \[3] $end +$var reg 8 H) \[4] $end +$var reg 8 I) \[5] $end +$var reg 8 J) \[6] $end +$var reg 8 K) \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 L) \[0] $end +$var reg 8 M) \[1] $end +$var reg 8 N) \[2] $end +$var reg 8 O) \[3] $end +$var reg 8 P) \[4] $end +$var reg 8 Q) \[5] $end +$var reg 8 R) \[6] $end +$var reg 8 S) \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 T) \[0] $end +$var reg 8 U) \[1] $end +$var reg 8 V) \[2] $end +$var reg 8 W) \[3] $end +$var reg 8 X) \[4] $end +$var reg 8 Y) \[5] $end +$var reg 8 Z) \[6] $end +$var reg 8 [) \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 \) \[0] $end +$var reg 8 ]) \[1] $end +$var reg 8 ^) \[2] $end +$var reg 8 _) \[3] $end +$var reg 8 `) \[4] $end +$var reg 8 a) \[5] $end +$var reg 8 b) \[6] $end +$var reg 8 c) \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 d) \$tag $end +$var reg 55 e) HdlSome $end +$upscope $end +$var string 1 f) config $end +$upscope $end +$scope struct \[15] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 g) \[0] $end +$var reg 8 h) \[1] $end +$var reg 8 i) \[2] $end +$var reg 8 j) \[3] $end +$var reg 8 k) \[4] $end +$var reg 8 l) \[5] $end +$var reg 8 m) \[6] $end +$var reg 8 n) \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 o) \[0] $end +$var reg 8 p) \[1] $end +$var reg 8 q) \[2] $end +$var reg 8 r) \[3] $end +$var reg 8 s) \[4] $end +$var reg 8 t) \[5] $end +$var reg 8 u) \[6] $end +$var reg 8 v) \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 w) \[0] $end +$var reg 8 x) \[1] $end +$var reg 8 y) \[2] $end +$var reg 8 z) \[3] $end +$var reg 8 {) \[4] $end +$var reg 8 |) \[5] $end +$var reg 8 }) \[6] $end +$var reg 8 ~) \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 !* \[0] $end +$var reg 8 "* \[1] $end +$var reg 8 #* \[2] $end +$var reg 8 $* \[3] $end +$var reg 8 %* \[4] $end +$var reg 8 &* \[5] $end +$var reg 8 '* \[6] $end +$var reg 8 (* \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 )* \$tag $end +$var reg 55 ** HdlSome $end +$upscope $end +$var string 1 +* config $end +$upscope $end +$upscope $end +$scope struct l1_i_cache_impl $end +$scope struct cd $end +$var wire 1 ./ clk $end +$var wire 1 // rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 0/ \$tag $end +$scope struct HdlSome $end +$var string 1 1/ kind $end +$var wire 64 2/ addr $end +$scope struct write_data $end +$var wire 8 3/ \[0] $end +$var wire 8 4/ \[1] $end +$var wire 8 5/ \[2] $end +$var wire 8 6/ \[3] $end +$var wire 8 7/ \[4] $end +$var wire 8 8/ \[5] $end +$var wire 8 9/ \[6] $end +$var wire 8 :/ \[7] $end +$upscope $end +$var wire 8 ;/ fetch_block_id $end +$var string 1 / \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 ?/ \$tag $end +$var string 1 @/ Success $end +$var string 1 A/ Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 B/ \[0] $end +$var wire 8 C/ \[1] $end +$var wire 8 D/ \[2] $end +$var wire 8 E/ \[3] $end +$var wire 8 F/ \[4] $end +$var wire 8 G/ \[5] $end +$var wire 8 H/ \[6] $end +$var wire 8 I/ \[7] $end +$upscope $end +$var string 1 J/ config $end +$upscope $end +$upscope $end +$var wire 1 K/ ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 L/ \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 M/ \[0] $end +$var wire 8 N/ \[1] $end +$var wire 8 O/ \[2] $end +$var wire 8 P/ \[3] $end +$var wire 8 Q/ \[4] $end +$var wire 8 R/ \[5] $end +$var wire 8 S/ \[6] $end +$var wire 8 T/ \[7] $end +$var wire 8 U/ \[8] $end +$var wire 8 V/ \[9] $end +$var wire 8 W/ \[10] $end +$var wire 8 X/ \[11] $end +$var wire 8 Y/ \[12] $end +$var wire 8 Z/ \[13] $end +$var wire 8 [/ \[14] $end +$var wire 8 \/ \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 ]/ value $end +$var string 1 ^/ range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 _/ config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 `/ \$tag $end +$scope struct HdlSome $end +$var wire 64 a/ start_pc $end +$var wire 8 b/ fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 c/ ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 d/ \$tag $end +$scope struct HdlSome $end +$var wire 5 e/ value $end +$var string 1 f/ range $end +$upscope $end +$upscope $end +$var wire 1 g/ ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 h/ \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 i/ \[0] $end +$var wire 8 j/ \[1] $end +$var wire 8 k/ \[2] $end +$var wire 8 l/ \[3] $end +$var wire 8 m/ \[4] $end +$var wire 8 n/ \[5] $end +$var wire 8 o/ \[6] $end +$var wire 8 p/ \[7] $end +$var wire 8 q/ \[8] $end +$var wire 8 r/ \[9] $end +$var wire 8 s/ \[10] $end +$var wire 8 t/ \[11] $end +$var wire 8 u/ \[12] $end +$var wire 8 v/ \[13] $end +$var wire 8 w/ \[14] $end +$var wire 8 x/ \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 y/ value $end +$var string 1 z/ range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 {/ config $end +$upscope $end +$scope struct to_decode_fetched $end +$scope struct data $end +$var string 1 |/ \$tag $end +$scope struct HdlSome $end +$var wire 64 }/ start_pc $end +$var wire 8 ~/ fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 !0 \[0] $end +$var wire 8 "0 \[1] $end +$var wire 8 #0 \[2] $end +$var wire 8 $0 \[3] $end +$var wire 8 %0 \[4] $end +$var wire 8 &0 \[5] $end +$var wire 8 '0 \[6] $end +$var wire 8 (0 \[7] $end +$upscope $end +$scope struct error $end +$var string 1 )0 \$tag $end +$var string 1 *0 HdlSome $end +$upscope $end +$var string 1 +0 config $end +$upscope $end +$upscope $end +$var wire 1 ,0 ready $end +$upscope $end +$scope struct to_decode_next_fetch_block_ids $end +$var string 1 -0 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 .0 \[0] $end +$var wire 8 /0 \[1] $end +$var wire 8 00 \[2] $end +$var wire 8 10 \[3] $end +$var wire 8 20 \[4] $end +$var wire 8 30 \[5] $end +$var wire 8 40 \[6] $end +$var wire 8 50 \[7] $end +$var wire 8 60 \[8] $end +$var wire 8 70 \[9] $end +$var wire 8 80 \[10] $end +$var wire 8 90 \[11] $end +$var wire 8 :0 \[12] $end +$var wire 8 ;0 \[13] $end +$var wire 8 <0 \[14] $end +$var wire 8 =0 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 >0 value $end +$var string 1 ?0 range $end +$upscope $end +$upscope $end +$upscope $end +$scope struct max_cancel_in_fetch $end +$var wire 5 @0 value $end +$var string 1 A0 range $end +$upscope $end +$scope struct i_cache_port $end +$var wire 4 B0 addr $end +$var wire 1 C0 en $end +$var wire 1 D0 clk $end +$scope struct rdata $end +$scope struct data $end +$scope struct \[0] $end +$var wire 8 E0 \[0] $end +$var wire 8 F0 \[1] $end +$var wire 8 G0 \[2] $end +$var wire 8 H0 \[3] $end +$var wire 8 I0 \[4] $end +$var wire 8 J0 \[5] $end +$var wire 8 K0 \[6] $end +$var wire 8 L0 \[7] $end +$upscope $end +$scope struct \[1] $end +$var wire 8 M0 \[0] $end +$var wire 8 N0 \[1] $end +$var wire 8 O0 \[2] $end +$var wire 8 P0 \[3] $end +$var wire 8 Q0 \[4] $end +$var wire 8 R0 \[5] $end +$var wire 8 S0 \[6] $end +$var wire 8 T0 \[7] $end +$upscope $end +$scope struct \[2] $end +$var wire 8 U0 \[0] $end +$var wire 8 V0 \[1] $end +$var wire 8 W0 \[2] $end +$var wire 8 X0 \[3] $end +$var wire 8 Y0 \[4] $end +$var wire 8 Z0 \[5] $end +$var wire 8 [0 \[6] $end +$var wire 8 \0 \[7] $end +$upscope $end +$scope struct \[3] $end +$var wire 8 ]0 \[0] $end +$var wire 8 ^0 \[1] $end +$var wire 8 _0 \[2] $end +$var wire 8 `0 \[3] $end +$var wire 8 a0 \[4] $end +$var wire 8 b0 \[5] $end +$var wire 8 c0 \[6] $end +$var wire 8 d0 \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 e0 \$tag $end +$var wire 55 f0 HdlSome $end +$upscope $end +$var string 1 g0 config $end +$upscope $end +$var wire 1 h0 wmode $end +$scope struct wdata $end +$scope struct data $end +$scope struct \[0] $end +$var wire 8 i0 \[0] $end +$var wire 8 j0 \[1] $end +$var wire 8 k0 \[2] $end +$var wire 8 l0 \[3] $end +$var wire 8 m0 \[4] $end +$var wire 8 n0 \[5] $end +$var wire 8 o0 \[6] $end +$var wire 8 p0 \[7] $end +$upscope $end +$scope struct \[1] $end +$var wire 8 q0 \[0] $end +$var wire 8 r0 \[1] $end +$var wire 8 s0 \[2] $end +$var wire 8 t0 \[3] $end +$var wire 8 u0 \[4] $end +$var wire 8 v0 \[5] $end +$var wire 8 w0 \[6] $end +$var wire 8 x0 \[7] $end +$upscope $end +$scope struct \[2] $end +$var wire 8 y0 \[0] $end +$var wire 8 z0 \[1] $end +$var wire 8 {0 \[2] $end +$var wire 8 |0 \[3] $end +$var wire 8 }0 \[4] $end +$var wire 8 ~0 \[5] $end +$var wire 8 !1 \[6] $end +$var wire 8 "1 \[7] $end +$upscope $end +$scope struct \[3] $end +$var wire 8 #1 \[0] $end +$var wire 8 $1 \[1] $end +$var wire 8 %1 \[2] $end +$var wire 8 &1 \[3] $end +$var wire 8 '1 \[4] $end +$var wire 8 (1 \[5] $end +$var wire 8 )1 \[6] $end +$var wire 8 *1 \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 +1 \$tag $end +$var wire 55 ,1 HdlSome $end +$upscope $end +$var string 1 -1 config $end +$upscope $end +$scope struct wmask $end +$scope struct data $end +$scope struct \[0] $end +$var wire 1 .1 \[0] $end +$var wire 1 /1 \[1] $end +$var wire 1 01 \[2] $end +$var wire 1 11 \[3] $end +$var wire 1 21 \[4] $end +$var wire 1 31 \[5] $end +$var wire 1 41 \[6] $end +$var wire 1 51 \[7] $end +$upscope $end +$scope struct \[1] $end +$var wire 1 61 \[0] $end +$var wire 1 71 \[1] $end +$var wire 1 81 \[2] $end +$var wire 1 91 \[3] $end +$var wire 1 :1 \[4] $end +$var wire 1 ;1 \[5] $end +$var wire 1 <1 \[6] $end +$var wire 1 =1 \[7] $end +$upscope $end +$scope struct \[2] $end +$var wire 1 >1 \[0] $end +$var wire 1 ?1 \[1] $end +$var wire 1 @1 \[2] $end +$var wire 1 A1 \[3] $end +$var wire 1 B1 \[4] $end +$var wire 1 C1 \[5] $end +$var wire 1 D1 \[6] $end +$var wire 1 E1 \[7] $end +$upscope $end +$scope struct \[3] $end +$var wire 1 F1 \[0] $end +$var wire 1 G1 \[1] $end +$var wire 1 H1 \[2] $end +$var wire 1 I1 \[3] $end +$var wire 1 J1 \[4] $end +$var wire 1 K1 \[5] $end +$var wire 1 L1 \[6] $end +$var wire 1 M1 \[7] $end +$upscope $end +$upscope $end +$var wire 1 N1 addr $end +$scope struct config $end +$upscope $end +$upscope $end +$upscope $end +$scope struct state_for_debug $end +$scope struct queue $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 O1 start_pc $end +$var wire 8 P1 fetch_block_id $end +$var string 1 Q1 state $end +$scope struct error $end +$var string 1 R1 \$tag $end +$var string 1 S1 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 T1 \[0] $end +$var wire 8 U1 \[1] $end +$var wire 8 V1 \[2] $end +$var wire 8 W1 \[3] $end +$var wire 8 X1 \[4] $end +$var wire 8 Y1 \[5] $end +$var wire 8 Z1 \[6] $end +$var wire 8 [1 \[7] $end +$upscope $end +$var string 1 \1 config $end +$upscope $end +$scope struct \[1] $end +$var wire 64 ]1 start_pc $end +$var wire 8 ^1 fetch_block_id $end +$var string 1 _1 state $end +$scope struct error $end +$var string 1 `1 \$tag $end +$var string 1 a1 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 b1 \[0] $end +$var wire 8 c1 \[1] $end +$var wire 8 d1 \[2] $end +$var wire 8 e1 \[3] $end +$var wire 8 f1 \[4] $end +$var wire 8 g1 \[5] $end +$var wire 8 h1 \[6] $end +$var wire 8 i1 \[7] $end +$upscope $end +$var string 1 j1 config $end +$upscope $end +$scope struct \[2] $end +$var wire 64 k1 start_pc $end +$var wire 8 l1 fetch_block_id $end +$var string 1 m1 state $end +$scope struct error $end +$var string 1 n1 \$tag $end +$var string 1 o1 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 p1 \[0] $end +$var wire 8 q1 \[1] $end +$var wire 8 r1 \[2] $end +$var wire 8 s1 \[3] $end +$var wire 8 t1 \[4] $end +$var wire 8 u1 \[5] $end +$var wire 8 v1 \[6] $end +$var wire 8 w1 \[7] $end +$upscope $end +$var string 1 x1 config $end +$upscope $end +$scope struct \[3] $end +$var wire 64 y1 start_pc $end +$var wire 8 z1 fetch_block_id $end +$var string 1 {1 state $end +$scope struct error $end +$var string 1 |1 \$tag $end +$var string 1 }1 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 ~1 \[0] $end +$var wire 8 !2 \[1] $end +$var wire 8 "2 \[2] $end +$var wire 8 #2 \[3] $end +$var wire 8 $2 \[4] $end +$var wire 8 %2 \[5] $end +$var wire 8 &2 \[6] $end +$var wire 8 '2 \[7] $end +$upscope $end +$var string 1 (2 config $end +$upscope $end +$scope struct \[4] $end +$var wire 64 )2 start_pc $end +$var wire 8 *2 fetch_block_id $end +$var string 1 +2 state $end +$scope struct error $end +$var string 1 ,2 \$tag $end +$var string 1 -2 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 .2 \[0] $end +$var wire 8 /2 \[1] $end +$var wire 8 02 \[2] $end +$var wire 8 12 \[3] $end +$var wire 8 22 \[4] $end +$var wire 8 32 \[5] $end +$var wire 8 42 \[6] $end +$var wire 8 52 \[7] $end +$upscope $end +$var string 1 62 config $end +$upscope $end +$scope struct \[5] $end +$var wire 64 72 start_pc $end +$var wire 8 82 fetch_block_id $end +$var string 1 92 state $end +$scope struct error $end +$var string 1 :2 \$tag $end +$var string 1 ;2 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 <2 \[0] $end +$var wire 8 =2 \[1] $end +$var wire 8 >2 \[2] $end +$var wire 8 ?2 \[3] $end +$var wire 8 @2 \[4] $end +$var wire 8 A2 \[5] $end +$var wire 8 B2 \[6] $end +$var wire 8 C2 \[7] $end +$upscope $end +$var string 1 D2 config $end +$upscope $end +$scope struct \[6] $end +$var wire 64 E2 start_pc $end +$var wire 8 F2 fetch_block_id $end +$var string 1 G2 state $end +$scope struct error $end +$var string 1 H2 \$tag $end +$var string 1 I2 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 J2 \[0] $end +$var wire 8 K2 \[1] $end +$var wire 8 L2 \[2] $end +$var wire 8 M2 \[3] $end +$var wire 8 N2 \[4] $end +$var wire 8 O2 \[5] $end +$var wire 8 P2 \[6] $end +$var wire 8 Q2 \[7] $end +$upscope $end +$var string 1 R2 config $end +$upscope $end +$scope struct \[7] $end +$var wire 64 S2 start_pc $end +$var wire 8 T2 fetch_block_id $end +$var string 1 U2 state $end +$scope struct error $end +$var string 1 V2 \$tag $end +$var string 1 W2 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 X2 \[0] $end +$var wire 8 Y2 \[1] $end +$var wire 8 Z2 \[2] $end +$var wire 8 [2 \[3] $end +$var wire 8 \2 \[4] $end +$var wire 8 ]2 \[5] $end +$var wire 8 ^2 \[6] $end +$var wire 8 _2 \[7] $end +$upscope $end +$var string 1 `2 config $end +$upscope $end +$scope struct \[8] $end +$var wire 64 a2 start_pc $end +$var wire 8 b2 fetch_block_id $end +$var string 1 c2 state $end +$scope struct error $end +$var string 1 d2 \$tag $end +$var string 1 e2 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 f2 \[0] $end +$var wire 8 g2 \[1] $end +$var wire 8 h2 \[2] $end +$var wire 8 i2 \[3] $end +$var wire 8 j2 \[4] $end +$var wire 8 k2 \[5] $end +$var wire 8 l2 \[6] $end +$var wire 8 m2 \[7] $end +$upscope $end +$var string 1 n2 config $end +$upscope $end +$scope struct \[9] $end +$var wire 64 o2 start_pc $end +$var wire 8 p2 fetch_block_id $end +$var string 1 q2 state $end +$scope struct error $end +$var string 1 r2 \$tag $end +$var string 1 s2 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 t2 \[0] $end +$var wire 8 u2 \[1] $end +$var wire 8 v2 \[2] $end +$var wire 8 w2 \[3] $end +$var wire 8 x2 \[4] $end +$var wire 8 y2 \[5] $end +$var wire 8 z2 \[6] $end +$var wire 8 {2 \[7] $end +$upscope $end +$var string 1 |2 config $end +$upscope $end +$scope struct \[10] $end +$var wire 64 }2 start_pc $end +$var wire 8 ~2 fetch_block_id $end +$var string 1 !3 state $end +$scope struct error $end +$var string 1 "3 \$tag $end +$var string 1 #3 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 $3 \[0] $end +$var wire 8 %3 \[1] $end +$var wire 8 &3 \[2] $end +$var wire 8 '3 \[3] $end +$var wire 8 (3 \[4] $end +$var wire 8 )3 \[5] $end +$var wire 8 *3 \[6] $end +$var wire 8 +3 \[7] $end +$upscope $end +$var string 1 ,3 config $end +$upscope $end +$scope struct \[11] $end +$var wire 64 -3 start_pc $end +$var wire 8 .3 fetch_block_id $end +$var string 1 /3 state $end +$scope struct error $end +$var string 1 03 \$tag $end +$var string 1 13 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 23 \[0] $end +$var wire 8 33 \[1] $end +$var wire 8 43 \[2] $end +$var wire 8 53 \[3] $end +$var wire 8 63 \[4] $end +$var wire 8 73 \[5] $end +$var wire 8 83 \[6] $end +$var wire 8 93 \[7] $end +$upscope $end +$var string 1 :3 config $end +$upscope $end +$scope struct \[12] $end +$var wire 64 ;3 start_pc $end +$var wire 8 <3 fetch_block_id $end +$var string 1 =3 state $end +$scope struct error $end +$var string 1 >3 \$tag $end +$var string 1 ?3 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 @3 \[0] $end +$var wire 8 A3 \[1] $end +$var wire 8 B3 \[2] $end +$var wire 8 C3 \[3] $end +$var wire 8 D3 \[4] $end +$var wire 8 E3 \[5] $end +$var wire 8 F3 \[6] $end +$var wire 8 G3 \[7] $end +$upscope $end +$var string 1 H3 config $end +$upscope $end +$scope struct \[13] $end +$var wire 64 I3 start_pc $end +$var wire 8 J3 fetch_block_id $end +$var string 1 K3 state $end +$scope struct error $end +$var string 1 L3 \$tag $end +$var string 1 M3 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 N3 \[0] $end +$var wire 8 O3 \[1] $end +$var wire 8 P3 \[2] $end +$var wire 8 Q3 \[3] $end +$var wire 8 R3 \[4] $end +$var wire 8 S3 \[5] $end +$var wire 8 T3 \[6] $end +$var wire 8 U3 \[7] $end +$upscope $end +$var string 1 V3 config $end +$upscope $end +$scope struct \[14] $end +$var wire 64 W3 start_pc $end +$var wire 8 X3 fetch_block_id $end +$var string 1 Y3 state $end +$scope struct error $end +$var string 1 Z3 \$tag $end +$var string 1 [3 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 \3 \[0] $end +$var wire 8 ]3 \[1] $end +$var wire 8 ^3 \[2] $end +$var wire 8 _3 \[3] $end +$var wire 8 `3 \[4] $end +$var wire 8 a3 \[5] $end +$var wire 8 b3 \[6] $end +$var wire 8 c3 \[7] $end +$upscope $end +$var string 1 d3 config $end +$upscope $end +$scope struct \[15] $end +$var wire 64 e3 start_pc $end +$var wire 8 f3 fetch_block_id $end +$var string 1 g3 state $end +$scope struct error $end +$var string 1 h3 \$tag $end +$var string 1 i3 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 j3 \[0] $end +$var wire 8 k3 \[1] $end +$var wire 8 l3 \[2] $end +$var wire 8 m3 \[3] $end +$var wire 8 n3 \[4] $end +$var wire 8 o3 \[5] $end +$var wire 8 p3 \[6] $end +$var wire 8 q3 \[7] $end +$upscope $end +$var string 1 r3 config $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 5 s3 value $end +$var string 1 t3 range $end +$upscope $end +$upscope $end +$scope struct cache_misses $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 u3 addr $end +$var wire 8 v3 fetch_block_id $end +$scope struct next_start_fetch_block $end +$var string 1 w3 \$tag $end +$scope struct HdlSome $end +$var wire 2 x3 value $end +$var string 1 y3 range $end +$upscope $end +$upscope $end +$scope struct next_finish_fetch_block $end +$var string 1 z3 \$tag $end +$scope struct HdlSome $end +$var wire 2 {3 value $end +$var string 1 |3 range $end +$upscope $end +$upscope $end +$scope struct error $end +$var string 1 }3 \$tag $end +$var string 1 ~3 HdlSome $end +$upscope $end +$var string 1 !4 config $end +$upscope $end +$scope struct \[1] $end +$var wire 64 "4 addr $end +$var wire 8 #4 fetch_block_id $end +$scope struct next_start_fetch_block $end +$var string 1 $4 \$tag $end +$scope struct HdlSome $end +$var wire 2 %4 value $end +$var string 1 &4 range $end +$upscope $end +$upscope $end +$scope struct next_finish_fetch_block $end +$var string 1 '4 \$tag $end +$scope struct HdlSome $end +$var wire 2 (4 value $end +$var string 1 )4 range $end +$upscope $end +$upscope $end +$scope struct error $end +$var string 1 *4 \$tag $end +$var string 1 +4 HdlSome $end +$upscope $end +$var string 1 ,4 config $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 2 -4 value $end +$var string 1 .4 range $end +$upscope $end +$upscope $end +$var string 1 /4 config $end +$upscope $end +$upscope $end +$scope module l1_i_cache_impl_2 $end +$scope struct cd $end +$var wire 1 ,* clk $end +$var wire 1 -* rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 .* \$tag $end +$scope struct HdlSome $end +$var string 1 /* kind $end +$var wire 64 0* addr $end +$scope struct write_data $end +$var wire 8 1* \[0] $end +$var wire 8 2* \[1] $end +$var wire 8 3* \[2] $end +$var wire 8 4* \[3] $end +$var wire 8 5* \[4] $end +$var wire 8 6* \[5] $end +$var wire 8 7* \[6] $end +$var wire 8 8* \[7] $end +$upscope $end +$var wire 8 9* fetch_block_id $end +$var string 1 :* config $end +$upscope $end +$upscope $end +$var wire 1 ;* ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 <* \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 =* \$tag $end +$var string 1 >* Success $end +$var string 1 ?* Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 @* \[0] $end +$var wire 8 A* \[1] $end +$var wire 8 B* \[2] $end +$var wire 8 C* \[3] $end +$var wire 8 D* \[4] $end +$var wire 8 E* \[5] $end +$var wire 8 F* \[6] $end +$var wire 8 G* \[7] $end +$upscope $end +$var string 1 H* config $end +$upscope $end +$upscope $end +$var wire 1 I* ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 J* \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 K* \[0] $end +$var wire 8 L* \[1] $end +$var wire 8 M* \[2] $end +$var wire 8 N* \[3] $end +$var wire 8 O* \[4] $end +$var wire 8 P* \[5] $end +$var wire 8 Q* \[6] $end +$var wire 8 R* \[7] $end +$var wire 8 S* \[8] $end +$var wire 8 T* \[9] $end +$var wire 8 U* \[10] $end +$var wire 8 V* \[11] $end +$var wire 8 W* \[12] $end +$var wire 8 X* \[13] $end +$var wire 8 Y* \[14] $end +$var wire 8 Z* \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 [* value $end +$var string 1 \* range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 ]* config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 ^* \$tag $end +$scope struct HdlSome $end +$var wire 64 _* start_pc $end +$var wire 8 `* fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 a* ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 b* \$tag $end +$scope struct HdlSome $end +$var wire 5 c* value $end +$var string 1 d* range $end +$upscope $end +$upscope $end +$var wire 1 e* ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 f* \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 g* \[0] $end +$var wire 8 h* \[1] $end +$var wire 8 i* \[2] $end +$var wire 8 j* \[3] $end +$var wire 8 k* \[4] $end +$var wire 8 l* \[5] $end +$var wire 8 m* \[6] $end +$var wire 8 n* \[7] $end +$var wire 8 o* \[8] $end +$var wire 8 p* \[9] $end +$var wire 8 q* \[10] $end +$var wire 8 r* \[11] $end +$var wire 8 s* \[12] $end +$var wire 8 t* \[13] $end +$var wire 8 u* \[14] $end +$var wire 8 v* \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 w* value $end +$var string 1 x* range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 y* config $end +$upscope $end +$scope struct to_decode_fetched $end +$scope struct data $end +$var string 1 z* \$tag $end +$scope struct HdlSome $end +$var wire 64 {* start_pc $end +$var wire 8 |* fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 }* \[0] $end +$var wire 8 ~* \[1] $end +$var wire 8 !+ \[2] $end +$var wire 8 "+ \[3] $end +$var wire 8 #+ \[4] $end +$var wire 8 $+ \[5] $end +$var wire 8 %+ \[6] $end +$var wire 8 &+ \[7] $end +$upscope $end +$scope struct error $end +$var string 1 '+ \$tag $end +$var string 1 (+ HdlSome $end +$upscope $end +$var string 1 )+ config $end +$upscope $end +$upscope $end +$var wire 1 *+ ready $end +$upscope $end +$scope struct to_decode_next_fetch_block_ids $end +$var string 1 ++ \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 ,+ \[0] $end +$var wire 8 -+ \[1] $end +$var wire 8 .+ \[2] $end +$var wire 8 /+ \[3] $end +$var wire 8 0+ \[4] $end +$var wire 8 1+ \[5] $end +$var wire 8 2+ \[6] $end +$var wire 8 3+ \[7] $end +$var wire 8 4+ \[8] $end +$var wire 8 5+ \[9] $end +$var wire 8 6+ \[10] $end +$var wire 8 7+ \[11] $end +$var wire 8 8+ \[12] $end +$var wire 8 9+ \[13] $end +$var wire 8 :+ \[14] $end +$var wire 8 ;+ \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 <+ value $end +$var string 1 =+ range $end +$upscope $end +$upscope $end +$upscope $end +$scope struct max_cancel_in_fetch $end +$var wire 5 >+ value $end +$var string 1 ?+ range $end +$upscope $end +$scope struct i_cache_port $end +$var wire 4 @+ addr $end +$var wire 1 A+ en $end +$var wire 1 B+ clk $end +$scope struct rdata $end +$scope struct data $end +$scope struct \[0] $end +$var wire 8 C+ \[0] $end +$var wire 8 D+ \[1] $end +$var wire 8 E+ \[2] $end +$var wire 8 F+ \[3] $end +$var wire 8 G+ \[4] $end +$var wire 8 H+ \[5] $end +$var wire 8 I+ \[6] $end +$var wire 8 J+ \[7] $end +$upscope $end +$scope struct \[1] $end +$var wire 8 K+ \[0] $end +$var wire 8 L+ \[1] $end +$var wire 8 M+ \[2] $end +$var wire 8 N+ \[3] $end +$var wire 8 O+ \[4] $end +$var wire 8 P+ \[5] $end +$var wire 8 Q+ \[6] $end +$var wire 8 R+ \[7] $end +$upscope $end +$scope struct \[2] $end +$var wire 8 S+ \[0] $end +$var wire 8 T+ \[1] $end +$var wire 8 U+ \[2] $end +$var wire 8 V+ \[3] $end +$var wire 8 W+ \[4] $end +$var wire 8 X+ \[5] $end +$var wire 8 Y+ \[6] $end +$var wire 8 Z+ \[7] $end +$upscope $end +$scope struct \[3] $end +$var wire 8 [+ \[0] $end +$var wire 8 \+ \[1] $end +$var wire 8 ]+ \[2] $end +$var wire 8 ^+ \[3] $end +$var wire 8 _+ \[4] $end +$var wire 8 `+ \[5] $end +$var wire 8 a+ \[6] $end +$var wire 8 b+ \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 c+ \$tag $end +$var wire 55 d+ HdlSome $end +$upscope $end +$var string 1 e+ config $end +$upscope $end +$var wire 1 f+ wmode $end +$scope struct wdata $end +$scope struct data $end +$scope struct \[0] $end +$var wire 8 g+ \[0] $end +$var wire 8 h+ \[1] $end +$var wire 8 i+ \[2] $end +$var wire 8 j+ \[3] $end +$var wire 8 k+ \[4] $end +$var wire 8 l+ \[5] $end +$var wire 8 m+ \[6] $end +$var wire 8 n+ \[7] $end +$upscope $end +$scope struct \[1] $end +$var wire 8 o+ \[0] $end +$var wire 8 p+ \[1] $end +$var wire 8 q+ \[2] $end +$var wire 8 r+ \[3] $end +$var wire 8 s+ \[4] $end +$var wire 8 t+ \[5] $end +$var wire 8 u+ \[6] $end +$var wire 8 v+ \[7] $end +$upscope $end +$scope struct \[2] $end +$var wire 8 w+ \[0] $end +$var wire 8 x+ \[1] $end +$var wire 8 y+ \[2] $end +$var wire 8 z+ \[3] $end +$var wire 8 {+ \[4] $end +$var wire 8 |+ \[5] $end +$var wire 8 }+ \[6] $end +$var wire 8 ~+ \[7] $end +$upscope $end +$scope struct \[3] $end +$var wire 8 !, \[0] $end +$var wire 8 ", \[1] $end +$var wire 8 #, \[2] $end +$var wire 8 $, \[3] $end +$var wire 8 %, \[4] $end +$var wire 8 &, \[5] $end +$var wire 8 ', \[6] $end +$var wire 8 (, \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 ), \$tag $end +$var wire 55 *, HdlSome $end +$upscope $end +$var string 1 +, config $end +$upscope $end +$scope struct wmask $end +$scope struct data $end +$scope struct \[0] $end +$var wire 1 ,, \[0] $end +$var wire 1 -, \[1] $end +$var wire 1 ., \[2] $end +$var wire 1 /, \[3] $end +$var wire 1 0, \[4] $end +$var wire 1 1, \[5] $end +$var wire 1 2, \[6] $end +$var wire 1 3, \[7] $end +$upscope $end +$scope struct \[1] $end +$var wire 1 4, \[0] $end +$var wire 1 5, \[1] $end +$var wire 1 6, \[2] $end +$var wire 1 7, \[3] $end +$var wire 1 8, \[4] $end +$var wire 1 9, \[5] $end +$var wire 1 :, \[6] $end +$var wire 1 ;, \[7] $end +$upscope $end +$scope struct \[2] $end +$var wire 1 <, \[0] $end +$var wire 1 =, \[1] $end +$var wire 1 >, \[2] $end +$var wire 1 ?, \[3] $end +$var wire 1 @, \[4] $end +$var wire 1 A, \[5] $end +$var wire 1 B, \[6] $end +$var wire 1 C, \[7] $end +$upscope $end +$scope struct \[3] $end +$var wire 1 D, \[0] $end +$var wire 1 E, \[1] $end +$var wire 1 F, \[2] $end +$var wire 1 G, \[3] $end +$var wire 1 H, \[4] $end +$var wire 1 I, \[5] $end +$var wire 1 J, \[6] $end +$var wire 1 K, \[7] $end +$upscope $end +$upscope $end +$var wire 1 L, addr $end +$scope struct config $end +$upscope $end +$upscope $end +$upscope $end +$scope struct state_for_debug $end +$scope struct queue $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 M, start_pc $end +$var wire 8 N, fetch_block_id $end +$var string 1 O, state $end +$scope struct error $end +$var string 1 P, \$tag $end +$var string 1 Q, HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 R, \[0] $end +$var wire 8 S, \[1] $end +$var wire 8 T, \[2] $end +$var wire 8 U, \[3] $end +$var wire 8 V, \[4] $end +$var wire 8 W, \[5] $end +$var wire 8 X, \[6] $end +$var wire 8 Y, \[7] $end +$upscope $end +$var string 1 Z, config $end +$upscope $end +$scope struct \[1] $end +$var wire 64 [, start_pc $end +$var wire 8 \, fetch_block_id $end +$var string 1 ], state $end +$scope struct error $end +$var string 1 ^, \$tag $end +$var string 1 _, HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 `, \[0] $end +$var wire 8 a, \[1] $end +$var wire 8 b, \[2] $end +$var wire 8 c, \[3] $end +$var wire 8 d, \[4] $end +$var wire 8 e, \[5] $end +$var wire 8 f, \[6] $end +$var wire 8 g, \[7] $end +$upscope $end +$var string 1 h, config $end +$upscope $end +$scope struct \[2] $end +$var wire 64 i, start_pc $end +$var wire 8 j, fetch_block_id $end +$var string 1 k, state $end +$scope struct error $end +$var string 1 l, \$tag $end +$var string 1 m, HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 n, \[0] $end +$var wire 8 o, \[1] $end +$var wire 8 p, \[2] $end +$var wire 8 q, \[3] $end +$var wire 8 r, \[4] $end +$var wire 8 s, \[5] $end +$var wire 8 t, \[6] $end +$var wire 8 u, \[7] $end +$upscope $end +$var string 1 v, config $end +$upscope $end +$scope struct \[3] $end +$var wire 64 w, start_pc $end +$var wire 8 x, fetch_block_id $end +$var string 1 y, state $end +$scope struct error $end +$var string 1 z, \$tag $end +$var string 1 {, HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 |, \[0] $end +$var wire 8 }, \[1] $end +$var wire 8 ~, \[2] $end +$var wire 8 !- \[3] $end +$var wire 8 "- \[4] $end +$var wire 8 #- \[5] $end +$var wire 8 $- \[6] $end +$var wire 8 %- \[7] $end +$upscope $end +$var string 1 &- config $end +$upscope $end +$scope struct \[4] $end +$var wire 64 '- start_pc $end +$var wire 8 (- fetch_block_id $end +$var string 1 )- state $end +$scope struct error $end +$var string 1 *- \$tag $end +$var string 1 +- HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 ,- \[0] $end +$var wire 8 -- \[1] $end +$var wire 8 .- \[2] $end +$var wire 8 /- \[3] $end +$var wire 8 0- \[4] $end +$var wire 8 1- \[5] $end +$var wire 8 2- \[6] $end +$var wire 8 3- \[7] $end +$upscope $end +$var string 1 4- config $end +$upscope $end +$scope struct \[5] $end +$var wire 64 5- start_pc $end +$var wire 8 6- fetch_block_id $end +$var string 1 7- state $end +$scope struct error $end +$var string 1 8- \$tag $end +$var string 1 9- HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 :- \[0] $end +$var wire 8 ;- \[1] $end +$var wire 8 <- \[2] $end +$var wire 8 =- \[3] $end +$var wire 8 >- \[4] $end +$var wire 8 ?- \[5] $end +$var wire 8 @- \[6] $end +$var wire 8 A- \[7] $end +$upscope $end +$var string 1 B- config $end +$upscope $end +$scope struct \[6] $end +$var wire 64 C- start_pc $end +$var wire 8 D- fetch_block_id $end +$var string 1 E- state $end +$scope struct error $end +$var string 1 F- \$tag $end +$var string 1 G- HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 H- \[0] $end +$var wire 8 I- \[1] $end +$var wire 8 J- \[2] $end +$var wire 8 K- \[3] $end +$var wire 8 L- \[4] $end +$var wire 8 M- \[5] $end +$var wire 8 N- \[6] $end +$var wire 8 O- \[7] $end +$upscope $end +$var string 1 P- config $end +$upscope $end +$scope struct \[7] $end +$var wire 64 Q- start_pc $end +$var wire 8 R- fetch_block_id $end +$var string 1 S- state $end +$scope struct error $end +$var string 1 T- \$tag $end +$var string 1 U- HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 V- \[0] $end +$var wire 8 W- \[1] $end +$var wire 8 X- \[2] $end +$var wire 8 Y- \[3] $end +$var wire 8 Z- \[4] $end +$var wire 8 [- \[5] $end +$var wire 8 \- \[6] $end +$var wire 8 ]- \[7] $end +$upscope $end +$var string 1 ^- config $end +$upscope $end +$scope struct \[8] $end +$var wire 64 _- start_pc $end +$var wire 8 `- fetch_block_id $end +$var string 1 a- state $end +$scope struct error $end +$var string 1 b- \$tag $end +$var string 1 c- HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 d- \[0] $end +$var wire 8 e- \[1] $end +$var wire 8 f- \[2] $end +$var wire 8 g- \[3] $end +$var wire 8 h- \[4] $end +$var wire 8 i- \[5] $end +$var wire 8 j- \[6] $end +$var wire 8 k- \[7] $end +$upscope $end +$var string 1 l- config $end +$upscope $end +$scope struct \[9] $end +$var wire 64 m- start_pc $end +$var wire 8 n- fetch_block_id $end +$var string 1 o- state $end +$scope struct error $end +$var string 1 p- \$tag $end +$var string 1 q- HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 r- \[0] $end +$var wire 8 s- \[1] $end +$var wire 8 t- \[2] $end +$var wire 8 u- \[3] $end +$var wire 8 v- \[4] $end +$var wire 8 w- \[5] $end +$var wire 8 x- \[6] $end +$var wire 8 y- \[7] $end +$upscope $end +$var string 1 z- config $end +$upscope $end +$scope struct \[10] $end +$var wire 64 {- start_pc $end +$var wire 8 |- fetch_block_id $end +$var string 1 }- state $end +$scope struct error $end +$var string 1 ~- \$tag $end +$var string 1 !. HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 ". \[0] $end +$var wire 8 #. \[1] $end +$var wire 8 $. \[2] $end +$var wire 8 %. \[3] $end +$var wire 8 &. \[4] $end +$var wire 8 '. \[5] $end +$var wire 8 (. \[6] $end +$var wire 8 ). \[7] $end +$upscope $end +$var string 1 *. config $end +$upscope $end +$scope struct \[11] $end +$var wire 64 +. start_pc $end +$var wire 8 ,. fetch_block_id $end +$var string 1 -. state $end +$scope struct error $end +$var string 1 .. \$tag $end +$var string 1 /. HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 0. \[0] $end +$var wire 8 1. \[1] $end +$var wire 8 2. \[2] $end +$var wire 8 3. \[3] $end +$var wire 8 4. \[4] $end +$var wire 8 5. \[5] $end +$var wire 8 6. \[6] $end +$var wire 8 7. \[7] $end +$upscope $end +$var string 1 8. config $end +$upscope $end +$scope struct \[12] $end +$var wire 64 9. start_pc $end +$var wire 8 :. fetch_block_id $end +$var string 1 ;. state $end +$scope struct error $end +$var string 1 <. \$tag $end +$var string 1 =. HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 >. \[0] $end +$var wire 8 ?. \[1] $end +$var wire 8 @. \[2] $end +$var wire 8 A. \[3] $end +$var wire 8 B. \[4] $end +$var wire 8 C. \[5] $end +$var wire 8 D. \[6] $end +$var wire 8 E. \[7] $end +$upscope $end +$var string 1 F. config $end +$upscope $end +$scope struct \[13] $end +$var wire 64 G. start_pc $end +$var wire 8 H. fetch_block_id $end +$var string 1 I. state $end +$scope struct error $end +$var string 1 J. \$tag $end +$var string 1 K. HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 L. \[0] $end +$var wire 8 M. \[1] $end +$var wire 8 N. \[2] $end +$var wire 8 O. \[3] $end +$var wire 8 P. \[4] $end +$var wire 8 Q. \[5] $end +$var wire 8 R. \[6] $end +$var wire 8 S. \[7] $end +$upscope $end +$var string 1 T. config $end +$upscope $end +$scope struct \[14] $end +$var wire 64 U. start_pc $end +$var wire 8 V. fetch_block_id $end +$var string 1 W. state $end +$scope struct error $end +$var string 1 X. \$tag $end +$var string 1 Y. HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 Z. \[0] $end +$var wire 8 [. \[1] $end +$var wire 8 \. \[2] $end +$var wire 8 ]. \[3] $end +$var wire 8 ^. \[4] $end +$var wire 8 _. \[5] $end +$var wire 8 `. \[6] $end +$var wire 8 a. \[7] $end +$upscope $end +$var string 1 b. config $end +$upscope $end +$scope struct \[15] $end +$var wire 64 c. start_pc $end +$var wire 8 d. fetch_block_id $end +$var string 1 e. state $end +$scope struct error $end +$var string 1 f. \$tag $end +$var string 1 g. HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 h. \[0] $end +$var wire 8 i. \[1] $end +$var wire 8 j. \[2] $end +$var wire 8 k. \[3] $end +$var wire 8 l. \[4] $end +$var wire 8 m. \[5] $end +$var wire 8 n. \[6] $end +$var wire 8 o. \[7] $end +$upscope $end +$var string 1 p. config $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 5 q. value $end +$var string 1 r. range $end +$upscope $end +$upscope $end +$scope struct cache_misses $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 s. addr $end +$var wire 8 t. fetch_block_id $end +$scope struct next_start_fetch_block $end +$var string 1 u. \$tag $end +$scope struct HdlSome $end +$var wire 2 v. value $end +$var string 1 w. range $end +$upscope $end +$upscope $end +$scope struct next_finish_fetch_block $end +$var string 1 x. \$tag $end +$scope struct HdlSome $end +$var wire 2 y. value $end +$var string 1 z. range $end +$upscope $end +$upscope $end +$scope struct error $end +$var string 1 {. \$tag $end +$var string 1 |. HdlSome $end +$upscope $end +$var string 1 }. config $end +$upscope $end +$scope struct \[1] $end +$var wire 64 ~. addr $end +$var wire 8 !/ fetch_block_id $end +$scope struct next_start_fetch_block $end +$var string 1 "/ \$tag $end +$scope struct HdlSome $end +$var wire 2 #/ value $end +$var string 1 $/ range $end +$upscope $end +$upscope $end +$scope struct next_finish_fetch_block $end +$var string 1 %/ \$tag $end +$scope struct HdlSome $end +$var wire 2 &/ value $end +$var string 1 '/ range $end +$upscope $end +$upscope $end +$scope struct error $end +$var string 1 (/ \$tag $end +$var string 1 )/ HdlSome $end +$upscope $end +$var string 1 */ config $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 2 +/ value $end +$var string 1 ,/ range $end +$upscope $end +$upscope $end +$var string 1 -/ config $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct mock_memory $end +$scope struct cd $end +$var wire 1 `7 clk $end +$var wire 1 a7 rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 b7 \$tag $end +$scope struct HdlSome $end +$var string 1 c7 kind $end +$var wire 64 d7 addr $end +$scope struct write_data $end +$var wire 8 e7 \[0] $end +$var wire 8 f7 \[1] $end +$var wire 8 g7 \[2] $end +$var wire 8 h7 \[3] $end +$var wire 8 i7 \[4] $end +$var wire 8 j7 \[5] $end +$var wire 8 k7 \[6] $end +$var wire 8 l7 \[7] $end +$upscope $end +$var wire 8 m7 fetch_block_id $end +$var string 1 n7 config $end +$upscope $end +$upscope $end +$var wire 1 o7 ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 p7 \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 q7 \$tag $end +$var string 1 r7 Success $end +$var string 1 s7 Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 t7 \[0] $end +$var wire 8 u7 \[1] $end +$var wire 8 v7 \[2] $end +$var wire 8 w7 \[3] $end +$var wire 8 x7 \[4] $end +$var wire 8 y7 \[5] $end +$var wire 8 z7 \[6] $end +$var wire 8 {7 \[7] $end +$upscope $end +$var string 1 |7 config $end +$upscope $end +$upscope $end +$var wire 1 }7 ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 ~7 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 !8 \[0] $end +$var wire 8 "8 \[1] $end +$var wire 8 #8 \[2] $end +$var wire 8 $8 \[3] $end +$var wire 8 %8 \[4] $end +$var wire 8 &8 \[5] $end +$var wire 8 '8 \[6] $end +$var wire 8 (8 \[7] $end +$var wire 8 )8 \[8] $end +$var wire 8 *8 \[9] $end +$var wire 8 +8 \[10] $end +$var wire 8 ,8 \[11] $end +$var wire 8 -8 \[12] $end +$var wire 8 .8 \[13] $end +$var wire 8 /8 \[14] $end +$var wire 8 08 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 18 value $end +$var string 1 28 range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 38 config $end +$upscope $end +$scope struct queue_debug $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 48 addr $end +$var wire 8 58 fetch_block_id $end +$var wire 8 68 cycles_left $end +$upscope $end +$scope struct \[1] $end +$var wire 64 78 addr $end +$var wire 8 88 fetch_block_id $end +$var wire 8 98 cycles_left $end +$upscope $end +$scope struct \[2] $end +$var wire 64 :8 addr $end +$var wire 8 ;8 fetch_block_id $end +$var wire 8 <8 cycles_left $end +$upscope $end +$scope struct \[3] $end +$var wire 64 =8 addr $end +$var wire 8 >8 fetch_block_id $end +$var wire 8 ?8 cycles_left $end +$upscope $end +$scope struct \[4] $end +$var wire 64 @8 addr $end +$var wire 8 A8 fetch_block_id $end +$var wire 8 B8 cycles_left $end +$upscope $end +$scope struct \[5] $end +$var wire 64 C8 addr $end +$var wire 8 D8 fetch_block_id $end +$var wire 8 E8 cycles_left $end +$upscope $end +$scope struct \[6] $end +$var wire 64 F8 addr $end +$var wire 8 G8 fetch_block_id $end +$var wire 8 H8 cycles_left $end +$upscope $end +$scope struct \[7] $end +$var wire 64 I8 addr $end +$var wire 8 J8 fetch_block_id $end +$var wire 8 K8 cycles_left $end +$upscope $end +$scope struct \[8] $end +$var wire 64 L8 addr $end +$var wire 8 M8 fetch_block_id $end +$var wire 8 N8 cycles_left $end +$upscope $end +$scope struct \[9] $end +$var wire 64 O8 addr $end +$var wire 8 P8 fetch_block_id $end +$var wire 8 Q8 cycles_left $end +$upscope $end +$scope struct \[10] $end +$var wire 64 R8 addr $end +$var wire 8 S8 fetch_block_id $end +$var wire 8 T8 cycles_left $end +$upscope $end +$scope struct \[11] $end +$var wire 64 U8 addr $end +$var wire 8 V8 fetch_block_id $end +$var wire 8 W8 cycles_left $end +$upscope $end +$scope struct \[12] $end +$var wire 64 X8 addr $end +$var wire 8 Y8 fetch_block_id $end +$var wire 8 Z8 cycles_left $end +$upscope $end +$scope struct \[13] $end +$var wire 64 [8 addr $end +$var wire 8 \8 fetch_block_id $end +$var wire 8 ]8 cycles_left $end +$upscope $end +$scope struct \[14] $end +$var wire 64 ^8 addr $end +$var wire 8 _8 fetch_block_id $end +$var wire 8 `8 cycles_left $end +$upscope $end +$scope struct \[15] $end +$var wire 64 a8 addr $end +$var wire 8 b8 fetch_block_id $end +$var wire 8 c8 cycles_left $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 5 d8 value $end +$var string 1 e8 range $end +$upscope $end +$upscope $end +$upscope $end +$scope module mock_memory_2 $end +$scope struct cd $end +$var wire 1 Z6 clk $end +$var wire 1 [6 rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 \6 \$tag $end +$scope struct HdlSome $end +$var string 1 ]6 kind $end +$var wire 64 ^6 addr $end +$scope struct write_data $end +$var wire 8 _6 \[0] $end +$var wire 8 `6 \[1] $end +$var wire 8 a6 \[2] $end +$var wire 8 b6 \[3] $end +$var wire 8 c6 \[4] $end +$var wire 8 d6 \[5] $end +$var wire 8 e6 \[6] $end +$var wire 8 f6 \[7] $end +$upscope $end +$var wire 8 g6 fetch_block_id $end +$var string 1 h6 config $end +$upscope $end +$upscope $end +$var wire 1 i6 ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 j6 \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 k6 \$tag $end +$var string 1 l6 Success $end +$var string 1 m6 Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 n6 \[0] $end +$var wire 8 o6 \[1] $end +$var wire 8 p6 \[2] $end +$var wire 8 q6 \[3] $end +$var wire 8 r6 \[4] $end +$var wire 8 s6 \[5] $end +$var wire 8 t6 \[6] $end +$var wire 8 u6 \[7] $end +$upscope $end +$var string 1 v6 config $end +$upscope $end +$upscope $end +$var wire 1 w6 ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 x6 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 y6 \[0] $end +$var wire 8 z6 \[1] $end +$var wire 8 {6 \[2] $end +$var wire 8 |6 \[3] $end +$var wire 8 }6 \[4] $end +$var wire 8 ~6 \[5] $end +$var wire 8 !7 \[6] $end +$var wire 8 "7 \[7] $end +$var wire 8 #7 \[8] $end +$var wire 8 $7 \[9] $end +$var wire 8 %7 \[10] $end +$var wire 8 &7 \[11] $end +$var wire 8 '7 \[12] $end +$var wire 8 (7 \[13] $end +$var wire 8 )7 \[14] $end +$var wire 8 *7 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 +7 value $end +$var string 1 ,7 range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 -7 config $end +$upscope $end +$scope struct queue_debug $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 .7 addr $end +$var wire 8 /7 fetch_block_id $end +$var wire 8 07 cycles_left $end +$upscope $end +$scope struct \[1] $end +$var wire 64 17 addr $end +$var wire 8 27 fetch_block_id $end +$var wire 8 37 cycles_left $end +$upscope $end +$scope struct \[2] $end +$var wire 64 47 addr $end +$var wire 8 57 fetch_block_id $end +$var wire 8 67 cycles_left $end +$upscope $end +$scope struct \[3] $end +$var wire 64 77 addr $end +$var wire 8 87 fetch_block_id $end +$var wire 8 97 cycles_left $end +$upscope $end +$scope struct \[4] $end +$var wire 64 :7 addr $end +$var wire 8 ;7 fetch_block_id $end +$var wire 8 <7 cycles_left $end +$upscope $end +$scope struct \[5] $end +$var wire 64 =7 addr $end +$var wire 8 >7 fetch_block_id $end +$var wire 8 ?7 cycles_left $end +$upscope $end +$scope struct \[6] $end +$var wire 64 @7 addr $end +$var wire 8 A7 fetch_block_id $end +$var wire 8 B7 cycles_left $end +$upscope $end +$scope struct \[7] $end +$var wire 64 C7 addr $end +$var wire 8 D7 fetch_block_id $end +$var wire 8 E7 cycles_left $end +$upscope $end +$scope struct \[8] $end +$var wire 64 F7 addr $end +$var wire 8 G7 fetch_block_id $end +$var wire 8 H7 cycles_left $end +$upscope $end +$scope struct \[9] $end +$var wire 64 I7 addr $end +$var wire 8 J7 fetch_block_id $end +$var wire 8 K7 cycles_left $end +$upscope $end +$scope struct \[10] $end +$var wire 64 L7 addr $end +$var wire 8 M7 fetch_block_id $end +$var wire 8 N7 cycles_left $end +$upscope $end +$scope struct \[11] $end +$var wire 64 O7 addr $end +$var wire 8 P7 fetch_block_id $end +$var wire 8 Q7 cycles_left $end +$upscope $end +$scope struct \[12] $end +$var wire 64 R7 addr $end +$var wire 8 S7 fetch_block_id $end +$var wire 8 T7 cycles_left $end +$upscope $end +$scope struct \[13] $end +$var wire 64 U7 addr $end +$var wire 8 V7 fetch_block_id $end +$var wire 8 W7 cycles_left $end +$upscope $end +$scope struct \[14] $end +$var wire 64 X7 addr $end +$var wire 8 Y7 fetch_block_id $end +$var wire 8 Z7 cycles_left $end +$upscope $end +$scope struct \[15] $end +$var wire 64 [7 addr $end +$var wire 8 \7 fetch_block_id $end +$var wire 8 ]7 cycles_left $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 5 ^7 value $end +$var string 1 _7 range $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +0! +1" +sHdlSome\x20(1) # +b1000000000000 $ +b0 % +0& +sHdlNone\x20(0) ' +b0 ( +sPhantomConst(\"1..=16\") ) +0* +sHdlNone\x20(0) + +b0 , +b0 - +b0 . +b0 / +b0 0 +b0 1 +b0 2 +b0 3 +b0 4 +b0 5 +b0 6 +b0 7 +b0 8 +b0 9 +b0 : +b0 ; +b0 < +sPhantomConst(\"0..=16\") = +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) > +sHdlNone\x20(0) ? +b0 @ +b0 A +b0 B +b0 C +b0 D +b0 E +b0 F +b0 G +b0 H +b0 I +sHdlNone\x20(0) J +sGeneric\x20(0) K +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) L +1M +sHdlNone\x20(0) N +b0 O +sPhantomConst(\"1..=16\") P +sHdlSome\x20(1) Q +b0 R +b0 S +b0 T +b0 U +b0 V +b0 W +b0 X +b0 Y +b0 Z +b0 [ +b0 \ +b0 ] +b0 ^ +b0 _ +b0 ` +b0 a +b0 b +sPhantomConst(\"0..=16\") c +0d +1e +sHdlNone\x20(0) f +sRead\x20(0) g +b0 h +b0 i +b0 j +b0 k +b0 l +b0 m +b0 n +b0 o +b0 p +b0 q +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) r +0s +sHdlNone\x20(0) t +sSuccess\x20(0) u +sRead\x20(0) v +sGeneric\x20(0) w +b0 x +b0 y +b0 z +b0 { +b0 | +b0 } +b0 ~ +b0 !" +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "" +0#" +sHdlNone\x20(0) $" +b0 %" +b0 &" +b0 '" +b0 (" +b0 )" +b0 *" +b0 +" +b0 ," +b0 -" +b0 ." +b0 /" +b0 0" +b0 1" +b0 2" +b0 3" +b0 4" +b0 5" +sPhantomConst(\"0..=16\") 6" +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 7" +sHdlSome\x20(1) 8" +b1000000000000 9" +b0 :" +0;" +sHdlNone\x20(0) <" +b0 =" +sPhantomConst(\"1..=16\") >" +0?" +sHdlNone\x20(0) @" +b0 A" +b0 B" +b0 C" +b0 D" +b0 E" +b0 F" +b0 G" +b0 H" +b0 I" +b0 J" +b0 K" +b0 L" +b0 M" +b0 N" +b0 O" +b0 P" +b0 Q" +sPhantomConst(\"0..=16\") R" +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) S" +sHdlNone\x20(0) T" +b0 U" +b0 V" +b0 W" +b0 X" +b0 Y" +b0 Z" +b0 [" +b0 \" +b0 ]" +b0 ^" +sHdlNone\x20(0) _" +sGeneric\x20(0) `" +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) a" +1b" +sHdlNone\x20(0) c" +b0 d" +sPhantomConst(\"1..=16\") e" +sHdlSome\x20(1) f" +b0 g" +b0 h" +b0 i" +b0 j" +b0 k" +b0 l" +b0 m" +b0 n" +b0 o" +b0 p" +b0 q" +b0 r" +b0 s" +b0 t" +b0 u" +b0 v" +b0 w" +sPhantomConst(\"0..=16\") x" +0y" +1z" +sHdlNone\x20(0) {" +sRead\x20(0) |" +b0 }" +b0 ~" +b0 !# +b0 "# +b0 ## +b0 $# +b0 %# +b0 &# +b0 '# +b0 (# +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) )# +0*# +sHdlNone\x20(0) +# +sSuccess\x20(0) ,# +sRead\x20(0) -# +sGeneric\x20(0) .# +b0 /# +b0 0# +b0 1# +b0 2# +b0 3# +b0 4# +b0 5# +b0 6# +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 7# +08# +sHdlNone\x20(0) 9# +b0 :# +b0 ;# +b0 <# +b0 =# +b0 ># +b0 ?# +b0 @# +b0 A# +b0 B# +b0 C# +b0 D# +b0 E# +b0 F# +b0 G# +b0 H# +b0 I# +b0 J# +sPhantomConst(\"0..=16\") K# +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) L# +sHdlSome\x20(1) M# +b1000000000000 N# +b0 O# +0P# +sHdlNone\x20(0) Q# +b0 R# +sPhantomConst(\"1..=16\") S# +0T# +sHdlNone\x20(0) U# +b0 V# +b0 W# +b0 X# +b0 Y# +b0 Z# +b0 [# +b0 \# +b0 ]# +b0 ^# +b0 _# +b0 `# +b0 a# +b0 b# +b0 c# +b0 d# +b0 e# +b0 f# +sPhantomConst(\"0..=16\") g# +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) h# +sHdlNone\x20(0) i# +b0 j# +b0 k# +b0 l# +b0 m# +b0 n# +b0 o# +b0 p# +b0 q# +b0 r# +b0 s# +sHdlNone\x20(0) t# +sGeneric\x20(0) u# +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) v# +1w# +sHdlNone\x20(0) x# +b0 y# +sPhantomConst(\"1..=16\") z# +sHdlSome\x20(1) {# +b0 |# +b0 }# +b0 ~# +b0 !$ +b0 "$ +b0 #$ +b0 $$ +b0 %$ +b0 &$ +b0 '$ +b0 ($ +b0 )$ +b0 *$ +b0 +$ +b0 ,$ +b0 -$ +b0 .$ +sPhantomConst(\"0..=16\") /$ +b0 0$ +b0 1$ +b0 2$ +b0 3$ +b0 4$ +b0 5$ +b0 6$ +b0 7$ +b0 8$ +b0 9$ +b0 :$ +b0 ;$ +b0 <$ +b0 =$ +b0 >$ +b0 ?$ +b0 @$ +b0 A$ +b0 B$ +b0 C$ +b0 D$ +b0 E$ +b0 F$ +b0 G$ +b0 H$ +b0 I$ +b0 J$ +b0 K$ +b0 L$ +b0 M$ +b0 N$ +b0 O$ +sHdlNone\x20(0) P$ +b0 Q$ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) R$ +b0 S$ +b0 T$ +b0 U$ +b0 V$ +b0 W$ +b0 X$ +b0 Y$ +b0 Z$ +b0 [$ +b0 \$ +b0 ]$ +b0 ^$ +b0 _$ +b0 `$ +b0 a$ +b0 b$ +b0 c$ +b0 d$ +b0 e$ +b0 f$ +b0 g$ +b0 h$ +b0 i$ +b0 j$ +b0 k$ +b0 l$ +b0 m$ +b0 n$ +b0 o$ +b0 p$ +b0 q$ +b0 r$ +sHdlNone\x20(0) s$ +b0 t$ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) u$ +b0 v$ +b0 w$ +b0 x$ +b0 y$ +b0 z$ +b0 {$ +b0 |$ +b0 }$ +b0 ~$ +b0 !% +b0 "% +b0 #% +b0 $% +b0 %% +b0 &% +b0 '% +b0 (% +b0 )% +b0 *% +b0 +% +b0 ,% +b0 -% +b0 .% +b0 /% +b0 0% +b0 1% +b0 2% +b0 3% +b0 4% +b0 5% +b0 6% +b0 7% +sHdlNone\x20(0) 8% +b0 9% +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :% +b0 ;% +b0 <% +b0 =% +b0 >% +b0 ?% +b0 @% +b0 A% +b0 B% +b0 C% +b0 D% +b0 E% +b0 F% +b0 G% +b0 H% +b0 I% +b0 J% +b0 K% +b0 L% +b0 M% +b0 N% +b0 O% +b0 P% +b0 Q% +b0 R% +b0 S% +b0 T% +b0 U% +b0 V% +b0 W% +b0 X% +b0 Y% +b0 Z% +sHdlNone\x20(0) [% +b0 \% +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ]% +b0 ^% +b0 _% +b0 `% +b0 a% +b0 b% +b0 c% +b0 d% +b0 e% +b0 f% +b0 g% +b0 h% +b0 i% +b0 j% +b0 k% +b0 l% +b0 m% +b0 n% +b0 o% +b0 p% +b0 q% +b0 r% +b0 s% +b0 t% +b0 u% +b0 v% +b0 w% +b0 x% +b0 y% +b0 z% +b0 {% +b0 |% +b0 }% +sHdlNone\x20(0) ~% +b0 !& +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "& +b0 #& +b0 $& +b0 %& +b0 && +b0 '& +b0 (& +b0 )& +b0 *& +b0 +& +b0 ,& +b0 -& +b0 .& +b0 /& +b0 0& +b0 1& +b0 2& +b0 3& +b0 4& +b0 5& +b0 6& +b0 7& +b0 8& +b0 9& +b0 :& +b0 ;& +b0 <& +b0 =& +b0 >& +b0 ?& +b0 @& +b0 A& +b0 B& +sHdlNone\x20(0) C& +b0 D& +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) E& +b0 F& +b0 G& +b0 H& +b0 I& +b0 J& +b0 K& +b0 L& +b0 M& +b0 N& +b0 O& +b0 P& +b0 Q& +b0 R& +b0 S& +b0 T& +b0 U& +b0 V& +b0 W& +b0 X& +b0 Y& +b0 Z& +b0 [& +b0 \& +b0 ]& +b0 ^& +b0 _& +b0 `& +b0 a& +b0 b& +b0 c& +b0 d& +b0 e& +sHdlNone\x20(0) f& +b0 g& +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) h& +b0 i& +b0 j& +b0 k& +b0 l& +b0 m& +b0 n& +b0 o& +b0 p& +b0 q& +b0 r& +b0 s& +b0 t& +b0 u& +b0 v& +b0 w& +b0 x& +b0 y& +b0 z& +b0 {& +b0 |& +b0 }& +b0 ~& +b0 !' +b0 "' +b0 #' +b0 $' +b0 %' +b0 &' +b0 '' +b0 (' +b0 )' +b0 *' +sHdlNone\x20(0) +' +b0 ,' +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) -' +b0 .' +b0 /' +b0 0' +b0 1' +b0 2' +b0 3' +b0 4' +b0 5' +b0 6' +b0 7' +b0 8' +b0 9' +b0 :' +b0 ;' +b0 <' +b0 =' +b0 >' +b0 ?' +b0 @' +b0 A' +b0 B' +b0 C' +b0 D' +b0 E' +b0 F' +b0 G' +b0 H' +b0 I' +b0 J' +b0 K' +b0 L' +b0 M' +sHdlNone\x20(0) N' +b0 O' +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) P' +b0 Q' +b0 R' +b0 S' +b0 T' +b0 U' +b0 V' +b0 W' +b0 X' +b0 Y' +b0 Z' +b0 [' +b0 \' +b0 ]' +b0 ^' +b0 _' +b0 `' +b0 a' +b0 b' +b0 c' +b0 d' +b0 e' +b0 f' +b0 g' +b0 h' +b0 i' +b0 j' +b0 k' +b0 l' +b0 m' +b0 n' +b0 o' +b0 p' +sHdlNone\x20(0) q' +b0 r' +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) s' +b0 t' +b0 u' +b0 v' +b0 w' +b0 x' +b0 y' +b0 z' +b0 {' +b0 |' +b0 }' +b0 ~' +b0 !( +b0 "( +b0 #( +b0 $( +b0 %( +b0 &( +b0 '( +b0 (( +b0 )( +b0 *( +b0 +( +b0 ,( +b0 -( +b0 .( +b0 /( +b0 0( +b0 1( +b0 2( +b0 3( +b0 4( +b0 5( +sHdlNone\x20(0) 6( +b0 7( +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 8( +b0 9( +b0 :( +b0 ;( +b0 <( +b0 =( +b0 >( +b0 ?( +b0 @( +b0 A( +b0 B( +b0 C( +b0 D( +b0 E( +b0 F( +b0 G( +b0 H( +b0 I( +b0 J( +b0 K( +b0 L( +b0 M( +b0 N( +b0 O( +b0 P( +b0 Q( +b0 R( +b0 S( +b0 T( +b0 U( +b0 V( +b0 W( +b0 X( +sHdlNone\x20(0) Y( +b0 Z( +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) [( +b0 \( +b0 ]( +b0 ^( +b0 _( +b0 `( +b0 a( +b0 b( +b0 c( +b0 d( +b0 e( +b0 f( +b0 g( +b0 h( +b0 i( +b0 j( +b0 k( +b0 l( +b0 m( +b0 n( +b0 o( +b0 p( +b0 q( +b0 r( +b0 s( +b0 t( +b0 u( +b0 v( +b0 w( +b0 x( +b0 y( +b0 z( +b0 {( +sHdlNone\x20(0) |( +b0 }( +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ~( +b0 !) +b0 ") +b0 #) +b0 $) +b0 %) +b0 &) +b0 ') +b0 () +b0 )) +b0 *) +b0 +) +b0 ,) +b0 -) +b0 .) +b0 /) +b0 0) +b0 1) +b0 2) +b0 3) +b0 4) +b0 5) +b0 6) +b0 7) +b0 8) +b0 9) +b0 :) +b0 ;) +b0 <) +b0 =) +b0 >) +b0 ?) +b0 @) +sHdlNone\x20(0) A) +b0 B) +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) C) +b0 D) +b0 E) +b0 F) +b0 G) +b0 H) +b0 I) +b0 J) +b0 K) +b0 L) +b0 M) +b0 N) +b0 O) +b0 P) +b0 Q) +b0 R) +b0 S) +b0 T) +b0 U) +b0 V) +b0 W) +b0 X) +b0 Y) +b0 Z) +b0 [) +b0 \) +b0 ]) +b0 ^) +b0 _) +b0 `) +b0 a) +b0 b) +b0 c) +sHdlNone\x20(0) d) +b0 e) +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) f) +b0 g) +b0 h) +b0 i) +b0 j) +b0 k) +b0 l) +b0 m) +b0 n) +b0 o) +b0 p) +b0 q) +b0 r) +b0 s) +b0 t) +b0 u) +b0 v) +b0 w) +b0 x) +b0 y) +b0 z) +b0 {) +b0 |) +b0 }) +b0 ~) +b0 !* +b0 "* +b0 #* +b0 $* +b0 %* +b0 &* +b0 '* +b0 (* +sHdlNone\x20(0) )* +b0 ** +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +* +0,* +1-* +sHdlNone\x20(0) .* +sRead\x20(0) /* +b0 0* +b0 1* +b0 2* +b0 3* +b0 4* +b0 5* +b0 6* +b0 7* +b0 8* +b0 9* +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :* +0;* +sHdlNone\x20(0) <* +sSuccess\x20(0) =* +sRead\x20(0) >* +sGeneric\x20(0) ?* +b0 @* +b0 A* +b0 B* +b0 C* +b0 D* +b0 E* +b0 F* +b0 G* +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) H* +0I* +sHdlNone\x20(0) J* +b0 K* +b0 L* +b0 M* +b0 N* +b0 O* +b0 P* +b0 Q* +b0 R* +b0 S* +b0 T* +b0 U* +b0 V* +b0 W* +b0 X* +b0 Y* +b0 Z* +b0 [* +sPhantomConst(\"0..=16\") \* +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ]* +sHdlSome\x20(1) ^* +b1000000000000 _* +b0 `* +0a* +sHdlNone\x20(0) b* +b0 c* +sPhantomConst(\"1..=16\") d* +0e* +sHdlNone\x20(0) f* +b0 g* +b0 h* +b0 i* +b0 j* +b0 k* +b0 l* +b0 m* +b0 n* +b0 o* +b0 p* +b0 q* +b0 r* +b0 s* +b0 t* +b0 u* +b0 v* +b0 w* +sPhantomConst(\"0..=16\") x* +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) y* +sHdlNone\x20(0) z* +b0 {* +b0 |* +b0 }* +b0 ~* +b0 !+ +b0 "+ +b0 #+ +b0 $+ +b0 %+ +b0 &+ +sHdlNone\x20(0) '+ +sGeneric\x20(0) (+ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) )+ +1*+ +sHdlSome\x20(1) ++ +b0 ,+ +b0 -+ +b0 .+ +b0 /+ +b0 0+ +b0 1+ +b0 2+ +b0 3+ +b0 4+ +b0 5+ +b0 6+ +b0 7+ +b0 8+ +b0 9+ +b0 :+ +b0 ;+ +b0 <+ +sPhantomConst(\"0..=16\") =+ +b0 >+ +sPhantomConst(\"0..=16\") ?+ +b0 @+ +0A+ +0B+ +b0 C+ +b0 D+ +b0 E+ +b0 F+ +b0 G+ +b0 H+ +b0 I+ +b0 J+ +b0 K+ +b0 L+ +b0 M+ +b0 N+ +b0 O+ +b0 P+ +b0 Q+ +b0 R+ +b0 S+ +b0 T+ +b0 U+ +b0 V+ +b0 W+ +b0 X+ +b0 Y+ +b0 Z+ +b0 [+ +b0 \+ +b0 ]+ +b0 ^+ +b0 _+ +b0 `+ +b0 a+ +b0 b+ +sHdlNone\x20(0) c+ +b0 d+ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) e+ +0f+ +b0 g+ +b0 h+ +b0 i+ +b0 j+ +b0 k+ +b0 l+ +b0 m+ +b0 n+ +b0 o+ +b0 p+ +b0 q+ +b0 r+ +b0 s+ +b0 t+ +b0 u+ +b0 v+ +b0 w+ +b0 x+ +b0 y+ +b0 z+ +b0 {+ +b0 |+ +b0 }+ +b0 ~+ +b0 !, +b0 ", +b0 #, +b0 $, +b0 %, +b0 &, +b0 ', +b0 (, +sHdlNone\x20(0) ), +b0 *, +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +, +0,, +0-, +0., +0/, +00, +01, +02, +03, +04, +05, +06, +07, +08, +09, +0:, +0;, +0<, +0=, +0>, +0?, +0@, +0A, +0B, +0C, +0D, +0E, +0F, +0G, +0H, +0I, +0J, +0K, +0L, +b0 M, +b0 N, +sStart\x20(0) O, +sHdlNone\x20(0) P, +sGeneric\x20(0) Q, +b0 R, +b0 S, +b0 T, +b0 U, +b0 V, +b0 W, +b0 X, +b0 Y, +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Z, +b0 [, +b0 \, +sStart\x20(0) ], +sHdlNone\x20(0) ^, +sGeneric\x20(0) _, +b0 `, +b0 a, +b0 b, +b0 c, +b0 d, +b0 e, +b0 f, +b0 g, +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) h, +b0 i, +b0 j, +sStart\x20(0) k, +sHdlNone\x20(0) l, +sGeneric\x20(0) m, +b0 n, +b0 o, +b0 p, +b0 q, +b0 r, +b0 s, +b0 t, +b0 u, +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) v, +b0 w, +b0 x, +sStart\x20(0) y, +sHdlNone\x20(0) z, +sGeneric\x20(0) {, +b0 |, +b0 }, +b0 ~, +b0 !- +b0 "- +b0 #- +b0 $- +b0 %- +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) &- +b0 '- +b0 (- +sStart\x20(0) )- +sHdlNone\x20(0) *- +sGeneric\x20(0) +- +b0 ,- +b0 -- +b0 .- +b0 /- +b0 0- +b0 1- +b0 2- +b0 3- +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 4- +b0 5- +b0 6- +sStart\x20(0) 7- +sHdlNone\x20(0) 8- +sGeneric\x20(0) 9- +b0 :- +b0 ;- +b0 <- +b0 =- +b0 >- +b0 ?- +b0 @- +b0 A- +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) B- +b0 C- +b0 D- +sStart\x20(0) E- +sHdlNone\x20(0) F- +sGeneric\x20(0) G- +b0 H- +b0 I- +b0 J- +b0 K- +b0 L- +b0 M- +b0 N- +b0 O- +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) P- +b0 Q- +b0 R- +sStart\x20(0) S- +sHdlNone\x20(0) T- +sGeneric\x20(0) U- +b0 V- +b0 W- +b0 X- +b0 Y- +b0 Z- +b0 [- +b0 \- +b0 ]- +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ^- +b0 _- +b0 `- +sStart\x20(0) a- +sHdlNone\x20(0) b- +sGeneric\x20(0) c- +b0 d- +b0 e- +b0 f- +b0 g- +b0 h- +b0 i- +b0 j- +b0 k- +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) l- +b0 m- +b0 n- +sStart\x20(0) o- +sHdlNone\x20(0) p- +sGeneric\x20(0) q- +b0 r- +b0 s- +b0 t- +b0 u- +b0 v- +b0 w- +b0 x- +b0 y- +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z- +b0 {- +b0 |- +sStart\x20(0) }- +sHdlNone\x20(0) ~- +sGeneric\x20(0) !. +b0 ". +b0 #. +b0 $. +b0 %. +b0 &. +b0 '. +b0 (. +b0 ). +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) *. +b0 +. +b0 ,. +sStart\x20(0) -. +sHdlNone\x20(0) .. +sGeneric\x20(0) /. +b0 0. +b0 1. +b0 2. +b0 3. +b0 4. +b0 5. +b0 6. +b0 7. +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 8. +b0 9. +b0 :. +sStart\x20(0) ;. +sHdlNone\x20(0) <. +sGeneric\x20(0) =. +b0 >. +b0 ?. +b0 @. +b0 A. +b0 B. +b0 C. +b0 D. +b0 E. +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) F. +b0 G. +b0 H. +sStart\x20(0) I. +sHdlNone\x20(0) J. +sGeneric\x20(0) K. +b0 L. +b0 M. +b0 N. +b0 O. +b0 P. +b0 Q. +b0 R. +b0 S. +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) T. +b0 U. +b0 V. +sStart\x20(0) W. +sHdlNone\x20(0) X. +sGeneric\x20(0) Y. +b0 Z. +b0 [. +b0 \. +b0 ]. +b0 ^. +b0 _. +b0 `. +b0 a. +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) b. +b0 c. +b0 d. +sStart\x20(0) e. +sHdlNone\x20(0) f. +sGeneric\x20(0) g. +b0 h. +b0 i. +b0 j. +b0 k. +b0 l. +b0 m. +b0 n. +b0 o. +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) p. +b0 q. +sPhantomConst(\"0..=16\") r. +b0 s. +b0 t. +sHdlNone\x20(0) u. +b0 v. +sPhantomConst(\"0..4\") w. +sHdlNone\x20(0) x. +b0 y. +sPhantomConst(\"0..4\") z. +sHdlNone\x20(0) {. +sGeneric\x20(0) |. +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }. +b0 ~. +b0 !/ +sHdlNone\x20(0) "/ +b0 #/ +sPhantomConst(\"0..4\") $/ +sHdlNone\x20(0) %/ +b0 &/ +sPhantomConst(\"0..4\") '/ +sHdlNone\x20(0) (/ +sGeneric\x20(0) )/ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) */ +b0 +/ +sPhantomConst(\"0..=2\") ,/ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) -/ +0./ +1// +sHdlNone\x20(0) 0/ +sRead\x20(0) 1/ +b0 2/ +b0 3/ +b0 4/ +b0 5/ +b0 6/ +b0 7/ +b0 8/ +b0 9/ +b0 :/ +b0 ;/ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) / +sSuccess\x20(0) ?/ +sRead\x20(0) @/ +sGeneric\x20(0) A/ +b0 B/ +b0 C/ +b0 D/ +b0 E/ +b0 F/ +b0 G/ +b0 H/ +b0 I/ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) J/ +0K/ +sHdlNone\x20(0) L/ +b0 M/ +b0 N/ +b0 O/ +b0 P/ +b0 Q/ +b0 R/ +b0 S/ +b0 T/ +b0 U/ +b0 V/ +b0 W/ +b0 X/ +b0 Y/ +b0 Z/ +b0 [/ +b0 \/ +b0 ]/ +sPhantomConst(\"0..=16\") ^/ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) _/ +sHdlSome\x20(1) `/ +b1000000000000 a/ +b0 b/ +0c/ +sHdlNone\x20(0) d/ +b0 e/ +sPhantomConst(\"1..=16\") f/ +0g/ +sHdlNone\x20(0) h/ +b0 i/ +b0 j/ +b0 k/ +b0 l/ +b0 m/ +b0 n/ +b0 o/ +b0 p/ +b0 q/ +b0 r/ +b0 s/ +b0 t/ +b0 u/ +b0 v/ +b0 w/ +b0 x/ +b0 y/ +sPhantomConst(\"0..=16\") z/ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) {/ +sHdlNone\x20(0) |/ +b0 }/ +b0 ~/ +b0 !0 +b0 "0 +b0 #0 +b0 $0 +b0 %0 +b0 &0 +b0 '0 +b0 (0 +sHdlNone\x20(0) )0 +sGeneric\x20(0) *0 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +0 +1,0 +sHdlSome\x20(1) -0 +b0 .0 +b0 /0 +b0 00 +b0 10 +b0 20 +b0 30 +b0 40 +b0 50 +b0 60 +b0 70 +b0 80 +b0 90 +b0 :0 +b0 ;0 +b0 <0 +b0 =0 +b0 >0 +sPhantomConst(\"0..=16\") ?0 +b0 @0 +sPhantomConst(\"0..=16\") A0 +b0 B0 +0C0 +0D0 +b0 E0 +b0 F0 +b0 G0 +b0 H0 +b0 I0 +b0 J0 +b0 K0 +b0 L0 +b0 M0 +b0 N0 +b0 O0 +b0 P0 +b0 Q0 +b0 R0 +b0 S0 +b0 T0 +b0 U0 +b0 V0 +b0 W0 +b0 X0 +b0 Y0 +b0 Z0 +b0 [0 +b0 \0 +b0 ]0 +b0 ^0 +b0 _0 +b0 `0 +b0 a0 +b0 b0 +b0 c0 +b0 d0 +sHdlNone\x20(0) e0 +b0 f0 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) g0 +0h0 +b0 i0 +b0 j0 +b0 k0 +b0 l0 +b0 m0 +b0 n0 +b0 o0 +b0 p0 +b0 q0 +b0 r0 +b0 s0 +b0 t0 +b0 u0 +b0 v0 +b0 w0 +b0 x0 +b0 y0 +b0 z0 +b0 {0 +b0 |0 +b0 }0 +b0 ~0 +b0 !1 +b0 "1 +b0 #1 +b0 $1 +b0 %1 +b0 &1 +b0 '1 +b0 (1 +b0 )1 +b0 *1 +sHdlNone\x20(0) +1 +b0 ,1 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) -1 +0.1 +0/1 +001 +011 +021 +031 +041 +051 +061 +071 +081 +091 +0:1 +0;1 +0<1 +0=1 +0>1 +0?1 +0@1 +0A1 +0B1 +0C1 +0D1 +0E1 +0F1 +0G1 +0H1 +0I1 +0J1 +0K1 +0L1 +0M1 +0N1 +b0 O1 +b0 P1 +sStart\x20(0) Q1 +sHdlNone\x20(0) R1 +sGeneric\x20(0) S1 +b0 T1 +b0 U1 +b0 V1 +b0 W1 +b0 X1 +b0 Y1 +b0 Z1 +b0 [1 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \1 +b0 ]1 +b0 ^1 +sStart\x20(0) _1 +sHdlNone\x20(0) `1 +sGeneric\x20(0) a1 +b0 b1 +b0 c1 +b0 d1 +b0 e1 +b0 f1 +b0 g1 +b0 h1 +b0 i1 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) j1 +b0 k1 +b0 l1 +sStart\x20(0) m1 +sHdlNone\x20(0) n1 +sGeneric\x20(0) o1 +b0 p1 +b0 q1 +b0 r1 +b0 s1 +b0 t1 +b0 u1 +b0 v1 +b0 w1 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) x1 +b0 y1 +b0 z1 +sStart\x20(0) {1 +sHdlNone\x20(0) |1 +sGeneric\x20(0) }1 +b0 ~1 +b0 !2 +b0 "2 +b0 #2 +b0 $2 +b0 %2 +b0 &2 +b0 '2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) (2 +b0 )2 +b0 *2 +sStart\x20(0) +2 +sHdlNone\x20(0) ,2 +sGeneric\x20(0) -2 +b0 .2 +b0 /2 +b0 02 +b0 12 +b0 22 +b0 32 +b0 42 +b0 52 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 62 +b0 72 +b0 82 +sStart\x20(0) 92 +sHdlNone\x20(0) :2 +sGeneric\x20(0) ;2 +b0 <2 +b0 =2 +b0 >2 +b0 ?2 +b0 @2 +b0 A2 +b0 B2 +b0 C2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) D2 +b0 E2 +b0 F2 +sStart\x20(0) G2 +sHdlNone\x20(0) H2 +sGeneric\x20(0) I2 +b0 J2 +b0 K2 +b0 L2 +b0 M2 +b0 N2 +b0 O2 +b0 P2 +b0 Q2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) R2 +b0 S2 +b0 T2 +sStart\x20(0) U2 +sHdlNone\x20(0) V2 +sGeneric\x20(0) W2 +b0 X2 +b0 Y2 +b0 Z2 +b0 [2 +b0 \2 +b0 ]2 +b0 ^2 +b0 _2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) `2 +b0 a2 +b0 b2 +sStart\x20(0) c2 +sHdlNone\x20(0) d2 +sGeneric\x20(0) e2 +b0 f2 +b0 g2 +b0 h2 +b0 i2 +b0 j2 +b0 k2 +b0 l2 +b0 m2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) n2 +b0 o2 +b0 p2 +sStart\x20(0) q2 +sHdlNone\x20(0) r2 +sGeneric\x20(0) s2 +b0 t2 +b0 u2 +b0 v2 +b0 w2 +b0 x2 +b0 y2 +b0 z2 +b0 {2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) |2 +b0 }2 +b0 ~2 +sStart\x20(0) !3 +sHdlNone\x20(0) "3 +sGeneric\x20(0) #3 +b0 $3 +b0 %3 +b0 &3 +b0 '3 +b0 (3 +b0 )3 +b0 *3 +b0 +3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,3 +b0 -3 +b0 .3 +sStart\x20(0) /3 +sHdlNone\x20(0) 03 +sGeneric\x20(0) 13 +b0 23 +b0 33 +b0 43 +b0 53 +b0 63 +b0 73 +b0 83 +b0 93 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :3 +b0 ;3 +b0 <3 +sStart\x20(0) =3 +sHdlNone\x20(0) >3 +sGeneric\x20(0) ?3 +b0 @3 +b0 A3 +b0 B3 +b0 C3 +b0 D3 +b0 E3 +b0 F3 +b0 G3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) H3 +b0 I3 +b0 J3 +sStart\x20(0) K3 +sHdlNone\x20(0) L3 +sGeneric\x20(0) M3 +b0 N3 +b0 O3 +b0 P3 +b0 Q3 +b0 R3 +b0 S3 +b0 T3 +b0 U3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) V3 +b0 W3 +b0 X3 +sStart\x20(0) Y3 +sHdlNone\x20(0) Z3 +sGeneric\x20(0) [3 +b0 \3 +b0 ]3 +b0 ^3 +b0 _3 +b0 `3 +b0 a3 +b0 b3 +b0 c3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) d3 +b0 e3 +b0 f3 +sStart\x20(0) g3 +sHdlNone\x20(0) h3 +sGeneric\x20(0) i3 +b0 j3 +b0 k3 +b0 l3 +b0 m3 +b0 n3 +b0 o3 +b0 p3 +b0 q3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) r3 +b0 s3 +sPhantomConst(\"0..=16\") t3 +b0 u3 +b0 v3 +sHdlNone\x20(0) w3 +b0 x3 +sPhantomConst(\"0..4\") y3 +sHdlNone\x20(0) z3 +b0 {3 +sPhantomConst(\"0..4\") |3 +sHdlNone\x20(0) }3 +sGeneric\x20(0) ~3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) !4 +b0 "4 +b0 #4 +sHdlNone\x20(0) $4 +b0 %4 +sPhantomConst(\"0..4\") &4 +sHdlNone\x20(0) '4 +b0 (4 +sPhantomConst(\"0..4\") )4 +sHdlNone\x20(0) *4 +sGeneric\x20(0) +4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,4 +b0 -4 +sPhantomConst(\"0..=2\") .4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) /4 +004 +114 +sHdlNone\x20(0) 24 +sRead\x20(0) 34 +b0 44 +b0 54 +b0 64 +b0 74 +b0 84 +b0 94 +b0 :4 +b0 ;4 +b0 <4 +b0 =4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) >4 +0?4 +sHdlNone\x20(0) @4 +sSuccess\x20(0) A4 +sRead\x20(0) B4 +sGeneric\x20(0) C4 +b0 D4 +b0 E4 +b0 F4 +b0 G4 +b0 H4 +b0 I4 +b0 J4 +b0 K4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) L4 +0M4 +sHdlNone\x20(0) N4 +b0 O4 +b0 P4 +b0 Q4 +b0 R4 +b0 S4 +b0 T4 +b0 U4 +b0 V4 +b0 W4 +b0 X4 +b0 Y4 +b0 Z4 +b0 [4 +b0 \4 +b0 ]4 +b0 ^4 +b0 _4 +sPhantomConst(\"0..=16\") `4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) a4 +sHdlSome\x20(1) b4 +b1000000000000 c4 +b0 d4 +0e4 +sHdlNone\x20(0) f4 +b0 g4 +sPhantomConst(\"1..=16\") h4 +0i4 +sHdlNone\x20(0) j4 +b0 k4 +b0 l4 +b0 m4 +b0 n4 +b0 o4 +b0 p4 +b0 q4 +b0 r4 +b0 s4 +b0 t4 +b0 u4 +b0 v4 +b0 w4 +b0 x4 +b0 y4 +b0 z4 +b0 {4 +sPhantomConst(\"0..=16\") |4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) }4 +sHdlNone\x20(0) ~4 +b0 !5 +b0 "5 +b0 #5 +b0 $5 +b0 %5 +b0 &5 +b0 '5 +b0 (5 +b0 )5 +b0 *5 +sHdlNone\x20(0) +5 +sGeneric\x20(0) ,5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) -5 +1.5 +sHdlNone\x20(0) /5 +b0 05 +sPhantomConst(\"1..=16\") 15 +sHdlSome\x20(1) 25 +b0 35 +b0 45 +b0 55 +b0 65 +b0 75 +b0 85 +b0 95 +b0 :5 +b0 ;5 +b0 <5 +b0 =5 +b0 >5 +b0 ?5 +b0 @5 +b0 A5 +b0 B5 +b0 C5 +sPhantomConst(\"0..=16\") D5 +0E5 +1F5 +sHdlNone\x20(0) G5 +sRead\x20(0) H5 +b0 I5 +b0 J5 +b0 K5 +b0 L5 +b0 M5 +b0 N5 +b0 O5 +b0 P5 +b0 Q5 +b0 R5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) S5 +0T5 +sHdlNone\x20(0) U5 +sSuccess\x20(0) V5 +sRead\x20(0) W5 +sGeneric\x20(0) X5 +b0 Y5 +b0 Z5 +b0 [5 +b0 \5 +b0 ]5 +b0 ^5 +b0 _5 +b0 `5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) a5 +0b5 +sHdlNone\x20(0) c5 +b0 d5 +b0 e5 +b0 f5 +b0 g5 +b0 h5 +b0 i5 +b0 j5 +b0 k5 +b0 l5 +b0 m5 +b0 n5 +b0 o5 +b0 p5 +b0 q5 +b0 r5 +b0 s5 +b0 t5 +sPhantomConst(\"0..=16\") u5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) v5 +sHdlSome\x20(1) w5 +b1000000000000 x5 +b0 y5 +0z5 +sHdlNone\x20(0) {5 +b0 |5 +sPhantomConst(\"1..=16\") }5 +0~5 +sHdlNone\x20(0) !6 +b0 "6 +b0 #6 +b0 $6 +b0 %6 +b0 &6 +b0 '6 +b0 (6 +b0 )6 +b0 *6 +b0 +6 +b0 ,6 +b0 -6 +b0 .6 +b0 /6 +b0 06 +b0 16 +b0 26 +sPhantomConst(\"0..=16\") 36 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 46 +sHdlNone\x20(0) 56 +b0 66 +b0 76 +b0 86 +b0 96 +b0 :6 +b0 ;6 +b0 <6 +b0 =6 +b0 >6 +b0 ?6 +sHdlNone\x20(0) @6 +sGeneric\x20(0) A6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) B6 +1C6 +sHdlNone\x20(0) D6 +b0 E6 +sPhantomConst(\"1..=16\") F6 +sHdlSome\x20(1) G6 +b0 H6 +b0 I6 +b0 J6 +b0 K6 +b0 L6 +b0 M6 +b0 N6 +b0 O6 +b0 P6 +b0 Q6 +b0 R6 +b0 S6 +b0 T6 +b0 U6 +b0 V6 +b0 W6 +b0 X6 +sPhantomConst(\"0..=16\") Y6 +0Z6 +1[6 +sHdlNone\x20(0) \6 +sRead\x20(0) ]6 +b0 ^6 +b0 _6 +b0 `6 +b0 a6 +b0 b6 +b0 c6 +b0 d6 +b0 e6 +b0 f6 +b0 g6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) h6 +0i6 +sHdlNone\x20(0) j6 +sSuccess\x20(0) k6 +sRead\x20(0) l6 +sGeneric\x20(0) m6 +b0 n6 +b0 o6 +b0 p6 +b0 q6 +b0 r6 +b0 s6 +b0 t6 +b0 u6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) v6 +0w6 +sHdlNone\x20(0) x6 +b0 y6 +b0 z6 +b0 {6 +b0 |6 +b0 }6 +b0 ~6 +b0 !7 +b0 "7 +b0 #7 +b0 $7 +b0 %7 +b0 &7 +b0 '7 +b0 (7 +b0 )7 +b0 *7 +b0 +7 +sPhantomConst(\"0..=16\") ,7 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+b10001111100000000 i, +b101 j, +b10010111100000000 w, +b110 x, +b10011111100000000 '- +b111 (- +b1000000000000 5- +b1000 6- +b1000000010000 C- +b1001 D- +b1000000100000 Q- +b1010 R- +b1000000000000 _- +b1011 `- +b1000000010000 m- +b1100 n- +b1000000100000 {- +b1101 |- +b10000000000000 +. +b1110 ,. +b1111 :. +b10000 H. +b10001 V. +b0 c. +b0 d. +b1111 q. +b1 y. +sHdlSome\x20(1) {. +b10000111100000000 ~. +b100 !/ +sHdlSome\x20(1) "/ +sHdlSome\x20(1) %/ +b10 +/ +sHdlSome\x20(1) 0/ +b10000111100000000 2/ +b100 ;/ +1c/ +sHdlNone\x20(0) |/ +b0 }/ +b0 ~/ +b0 !0 +b0 "0 +b0 #0 +b0 $0 +b0 %0 +b0 &0 +b0 '0 +b0 (0 +b1111 @0 +b100000000 O1 +b11 P1 +sCacheMiss\x20(2) Q1 +b0 T1 +b0 U1 +b0 V1 +b0 W1 +b0 X1 +b0 Y1 +b0 Z1 +b0 [1 +b10000111100000000 ]1 +b100 ^1 +b10001111100000000 k1 +b101 l1 +b10010111100000000 y1 +b110 z1 +b10011111100000000 )2 +b111 *2 +b1000000000000 72 +b1000 82 +b1000000010000 E2 +b1001 F2 +b1000000100000 S2 +b1010 T2 +b1000000000000 a2 +b1011 b2 +b1000000010000 o2 +b1100 p2 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y. +sHdlNone\x20(0) {. +b0 ~. +b0 !/ +sHdlNone\x20(0) "/ +b0 #/ +sHdlNone\x20(0) %/ +b1 +/ +b10000111100010000 2/ +sHdlSome\x20(1) |/ +b100000000 }/ +b11 ~/ +sHdlSome\x20(1) )0 +sReturning\x20(5) Q1 +sHdlSome\x20(1) R1 +b10000111100000000 u3 +b100 v3 +sHdlSome\x20(1) w3 +b10 x3 +b0 {3 +sHdlNone\x20(0) }3 +b0 "4 +b0 #4 +sHdlNone\x20(0) $4 +b0 %4 +sHdlNone\x20(0) '4 +b1 -4 +b10000111100010000 44 +sHdlSome\x20(1) ~4 +b100000000 !5 +b11 "5 +sHdlSome\x20(1) +5 +b10000111100010000 I5 +sHdlSome\x20(1) 56 +b100000000 66 +b11 76 +sHdlSome\x20(1) @6 +b10000111100010000 ^6 +b10000111100010000 d7 +sHdlNone\x20(0) t +sSuccess\x20(0) u +b100 %" +sHdlNone\x20(0) +# +sSuccess\x20(0) ,# +b100 :# +sHdlNone\x20(0) <* +sSuccess\x20(0) =* +b100 K* +sHdlNone\x20(0) >/ +sSuccess\x20(0) ?/ +b100 M/ +sHdlNone\x20(0) @4 +sSuccess\x20(0) A4 +b100 O4 +sHdlNone\x20(0) U5 +sSuccess\x20(0) V5 +b100 d5 +sHdlNone\x20(0) j6 +sSuccess\x20(0) k6 +b100 y6 +b10000111100000000 .7 +b100 /7 +b10 07 +b10000111100001000 17 +b100 37 +sHdlNone\x20(0) p7 +sSuccess\x20(0) q7 +b100 !8 +b10000111100000000 48 +b100 58 +b10 68 +b10000111100001000 78 +b100 98 +#63000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#63500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +1& +sHdlNone\x20(0) ? +b0 @ +b0 A +sHdlNone\x20(0) J +b10000111100011000 h +1;" +sHdlNone\x20(0) T" +b0 U" +b0 V" +sHdlNone\x20(0) _" +b10000111100011000 }" +1P# +sHdlNone\x20(0) i# +b0 j# +b0 k# +sHdlNone\x20(0) t# +b10000111100011000 0* +1a* +sHdlNone\x20(0) z* +b0 {* +b0 |* +sHdlNone\x20(0) '+ +b1111 >+ +b10000111100000000 M, +b100 N, +sCacheMiss\x20(2) O, +sHdlNone\x20(0) P, +b10001111100000000 [, +b101 \, +b10010111100000000 i, +b110 j, +b10011111100000000 w, +b111 x, +b1000000000000 '- +b1000 (- +b1000000010000 5- +b1001 6- +b1000000100000 C- +b1010 D- +b1000000000000 Q- +b1011 R- +b1000000010000 _- +b1100 `- +b1000000100000 m- +b1101 n- +b10000000000000 {- +b1110 |- +b1111 ,. +b10000 :. +b10001 H. +b10010 V. +b0 c. +b0 d. +b1111 q. +b11 v. +b10001111100000000 ~. +b101 !/ +sHdlSome\x20(1) "/ +sHdlSome\x20(1) %/ +b10 +/ +b10000111100011000 2/ +1c/ +sHdlNone\x20(0) |/ +b0 }/ +b0 ~/ +sHdlNone\x20(0) )0 +b1111 @0 +b10000111100000000 O1 +b100 P1 +sCacheMiss\x20(2) Q1 +sHdlNone\x20(0) R1 +b10001111100000000 ]1 +b101 ^1 +b10010111100000000 k1 +b110 l1 +b10011111100000000 y1 +b111 z1 +b1000000000000 )2 +b1000 *2 +b1000000010000 72 +b1001 82 +b1000000100000 E2 +b1010 F2 +b1000000000000 S2 +b1011 T2 +b1000000010000 a2 +b1100 b2 +b1000000100000 o2 +b1101 p2 +b10000000000000 }2 +b1110 ~2 +b1111 .3 +b10000 <3 +b10001 J3 +b10010 X3 +b0 e3 +b0 f3 +b1111 s3 +b11 x3 +b10001111100000000 "4 +b101 #4 +sHdlSome\x20(1) $4 +sHdlSome\x20(1) '4 +b10 -4 +b10000111100011000 44 +1e4 +sHdlNone\x20(0) ~4 +b0 !5 +b0 "5 +sHdlNone\x20(0) +5 +b10000111100011000 I5 +1z5 +sHdlNone\x20(0) 56 +b0 66 +b0 76 +sHdlNone\x20(0) @6 +b10000111100011000 ^6 +b10000111100011000 d7 +b100 , +b101 - +b110 . +b111 / +b1000 0 +b1001 1 +b1010 2 +b1011 3 +b1100 4 +b1101 5 +b1110 6 +b1111 7 +b10000 8 +b10001 9 +b10010 : +b0 ; +b1111 < +b100 A" +b101 B" +b110 C" +b111 D" +b1000 E" +b1001 F" +b1010 G" +b1011 H" +b1100 I" +b1101 J" +b1110 K" +b1111 L" +b10000 M" +b10001 N" +b10010 O" +b0 P" +b1111 Q" +b100 V# +b101 W# +b110 X# +b111 Y# +b1000 Z# +b1001 [# +b1010 \# +b1011 ]# +b1100 ^# +b1101 _# +b1110 `# +b1111 a# +b10000 b# +b10001 c# +b10010 d# +b0 e# +b1111 f# +b100 g* +b101 h* +b110 i* +b111 j* +b1000 k* +b1001 l* +b1010 m* +b1011 n* +b1100 o* +b1101 p* +b1110 q* +b1111 r* +b10000 s* +b10001 t* +b10010 u* +b0 v* +b1111 w* +b100 i/ +b101 j/ +b110 k/ +b111 l/ +b1000 m/ +b1001 n/ +b1010 o/ +b1011 p/ +b1100 q/ +b1101 r/ +b1110 s/ +b1111 t/ +b10000 u/ +b10001 v/ +b10010 w/ +b0 x/ +b1111 y/ +b100 k4 +b101 l4 +b110 m4 +b111 n4 +b1000 o4 +b1001 p4 +b1010 q4 +b1011 r4 +b1100 s4 +b1101 t4 +b1110 u4 +b1111 v4 +b10000 w4 +b10001 x4 +b10010 y4 +b0 z4 +b1111 {4 +b100 "6 +b101 #6 +b110 $6 +b111 %6 +b1000 &6 +b1001 '6 +b1010 (6 +b1011 )6 +b1100 *6 +b1101 +6 +b1110 ,6 +b1111 -6 +b10000 .6 +b10001 /6 +b10010 06 +b0 16 +b1111 26 +b100 '" +b11 5" +b100 <# +b11 J# +b100 M* +b11 [* +b100 O/ +b11 ]/ +b100 Q4 +b11 _4 +b100 f5 +b11 t5 +b100 {6 +b11 +7 +b1 07 +b11 37 +b10000111100010000 47 +b100 57 +b100 67 +b11 ^7 +b100 #8 +b11 18 +b1 68 +b11 98 +b10000111100010000 :8 +b100 ;8 +b100 <8 +b11 d8 +#64000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#64500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +0& +b10001111100000000 h +b101 q +0;" +b10001111100000000 }" +b101 (# +0P# +b10001111100000000 0* +b101 9* +0a* +b10000 >+ +b10000000000000 c. +b10011 d. +b10000 q. +sHdlNone\x20(0) u. +b0 v. +b10001111100000000 2/ +b101 ;/ +0c/ +b10000 @0 +b10000000000000 e3 +b10011 f3 +b10000 s3 +sHdlNone\x20(0) w3 +b0 x3 +b10001111100000000 44 +b101 =4 +0e4 +b10001111100000000 I5 +b101 R5 +0z5 +b10001111100000000 ^6 +b101 g6 +b10001111100000000 d7 +b101 m7 +b10011 ; +b10000 < +b10011 P" +b10000 Q" +b10011 e# +b10000 f# +b10011 v* +b10000 w* +b10011 x/ +b10000 y/ +b10011 z4 +b10000 {4 +b10011 16 +b10000 26 +sHdlSome\x20(1) t +sError\x20(1) u +b100 (" +b100 5" +sHdlSome\x20(1) +# +sError\x20(1) ,# +b100 =# +b100 J# +sHdlSome\x20(1) <* +sError\x20(1) =* +b100 N* +b100 [* +sHdlSome\x20(1) >/ +sError\x20(1) ?/ +b100 P/ +b100 ]/ +sHdlSome\x20(1) @4 +sError\x20(1) A4 +b100 R4 +b100 _4 +sHdlSome\x20(1) U5 +sError\x20(1) V5 +b100 g5 +b100 t5 +sHdlSome\x20(1) j6 +sError\x20(1) k6 +b100 |6 +b100 +7 +b0 07 +b10 37 +b11 67 +b10000111100011000 77 +b100 87 +b100 97 +b100 ^7 +sHdlSome\x20(1) p7 +sError\x20(1) q7 +b100 $8 +b100 18 +b0 68 +b10 98 +b11 <8 +b10000111100011000 =8 +b100 >8 +b100 ?8 +b100 d8 +#65000000 +0! +b10100 % +0d +b10100 :" +0y" +b10100 O# +0,* +b10100 `* +0./ +b10100 b/ +004 +b10100 d4 +0E5 +b10100 y5 +0Z6 +0`7 +#65500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +b10001111100001000 h +b10001111100001000 }" +b10001111100001000 0* +b1 y. +sHdlSome\x20(1) {. +b1 #/ +b10001111100001000 2/ +b1 {3 +sHdlSome\x20(1) }3 +b1 %4 +b10001111100001000 44 +b10001111100001000 I5 +b10001111100001000 ^6 +b10001111100001000 d7 +sHdlNone\x20(0) t +sSuccess\x20(0) u +b101 (" +sHdlNone\x20(0) +# +sSuccess\x20(0) ,# +b101 =# +sHdlNone\x20(0) <* +sSuccess\x20(0) =* +b101 N* +sHdlNone\x20(0) >/ +sSuccess\x20(0) ?/ +b101 P/ +sHdlNone\x20(0) @4 +sSuccess\x20(0) A4 +b101 R4 +sHdlNone\x20(0) U5 +sSuccess\x20(0) V5 +b101 g5 +sHdlNone\x20(0) j6 +sSuccess\x20(0) k6 +b101 |6 +b10000111100001000 .7 +b1 07 +b10000111100010000 17 +b10000111100011000 47 +b10001111100000000 77 +b101 87 +sHdlNone\x20(0) p7 +sSuccess\x20(0) q7 +b101 $8 +b10000111100001000 48 +b1 68 +b10000111100010000 78 +b10000111100011000 :8 +b10001111100000000 =8 +b101 >8 +#66000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#66500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +b10001111100010000 h +b10001111100010000 }" +b10001111100010000 0* +b10 #/ +b10001111100010000 2/ +b10 %4 +b10001111100010000 44 +b10001111100010000 I5 +b10001111100010000 ^6 +b10001111100010000 d7 +sHdlSome\x20(1) t +sError\x20(1) u +b101 )" +b101 5" +sHdlSome\x20(1) +# +sError\x20(1) ,# +b101 ># +b101 J# +sHdlSome\x20(1) <* +sError\x20(1) =* +b101 O* +b101 [* +sHdlSome\x20(1) >/ +sError\x20(1) ?/ +b101 Q/ +b101 ]/ +sHdlSome\x20(1) @4 +sError\x20(1) A4 +b101 S4 +b101 _4 +sHdlSome\x20(1) U5 +sError\x20(1) V5 +b101 h5 +b101 t5 +sHdlSome\x20(1) j6 +sError\x20(1) k6 +b101 }6 +b101 +7 +b0 07 +b1 37 +b10 67 +b11 97 +b10001111100001000 :7 +b101 ;7 +b100 <7 +b101 ^7 +sHdlSome\x20(1) p7 +sError\x20(1) q7 +b101 %8 +b101 18 +b0 68 +b1 98 +b10 <8 +b11 ?8 +b10001111100001000 @8 +b101 A8 +b100 B8 +b101 d8 +#67000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#67500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +b10001111100011000 h +b10001111100011000 }" +b10001111100011000 0* +b10 y. +b11 #/ +b10001111100011000 2/ +b10 {3 +b11 %4 +b10001111100011000 44 +b10001111100011000 I5 +b10001111100011000 ^6 +b10001111100011000 d7 +b101 '" +b101 <# +b101 M* +b101 O/ +b101 Q4 +b101 f5 +b101 {6 +b10000111100010000 .7 +b10000111100011000 17 +b10001111100000000 47 +b101 57 +b10001111100001000 77 +b10001111100010000 :7 +b101 #8 +b10000111100010000 48 +b10000111100011000 78 +b10001111100000000 :8 +b101 ;8 +b10001111100001000 =8 +b10001111100010000 @8 +#68000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#68500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +sHdlNone\x20(0) f +b0 h +b0 q +sHdlNone\x20(0) {" +b0 }" +b0 (# +sHdlNone\x20(0) .* +b0 0* +b0 9* +b11 y. +sHdlNone\x20(0) "/ +b0 #/ +sHdlNone\x20(0) 0/ +b0 2/ +b0 ;/ +b11 {3 +sHdlNone\x20(0) $4 +b0 %4 +sHdlNone\x20(0) 24 +b0 44 +b0 =4 +sHdlNone\x20(0) G5 +b0 I5 +b0 R5 +sHdlNone\x20(0) \6 +b0 ^6 +b0 g6 +sHdlNone\x20(0) b7 +b0 d7 +b0 m7 +b101 &" +b101 ;# +b101 L* +b101 N/ +b101 P4 +b101 e5 +b101 z6 +b10000111100011000 .7 +b10001111100000000 17 +b101 27 +b10001111100001000 47 +b10001111100010000 77 +b10001111100011000 :7 +b101 "8 +b10000111100011000 48 +b10001111100000000 78 +b101 88 +b10001111100001000 :8 +b10001111100010000 =8 +b10001111100011000 @8 +#69000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#69500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +sHdlSome\x20(1) ? +b10000111100000000 @ +b100 A +sHdlSome\x20(1) J +sHdlSome\x20(1) T" +b10000111100000000 U" +b100 V" +sHdlSome\x20(1) _" +sHdlSome\x20(1) i# +b10000111100000000 j# +b100 k# +sHdlSome\x20(1) t# +sHdlSome\x20(1) z* +b10000111100000000 {* +b100 |* +sHdlSome\x20(1) '+ +sReturning\x20(5) O, +sHdlSome\x20(1) P, +b10001111100000000 s. +b101 t. +b0 y. +sHdlNone\x20(0) {. +b0 ~. +b0 !/ +sHdlNone\x20(0) %/ +b1 +/ +sHdlSome\x20(1) |/ +b10000111100000000 }/ +b100 ~/ +sHdlSome\x20(1) )0 +sReturning\x20(5) Q1 +sHdlSome\x20(1) R1 +b10001111100000000 u3 +b101 v3 +b0 {3 +sHdlNone\x20(0) }3 +b0 "4 +b0 #4 +sHdlNone\x20(0) '4 +b1 -4 +sHdlSome\x20(1) ~4 +b10000111100000000 !5 +b100 "5 +sHdlSome\x20(1) +5 +sHdlSome\x20(1) 56 +b10000111100000000 66 +b100 76 +sHdlSome\x20(1) @6 +sSuccess\x20(0) u +b11111111 x +b11111111 y +b11111111 z +b11111111 { +b11111111 | +b11111111 } +b11111111 ~ +b11111111 !" +b101 %" +b0 )" +b100 5" +sSuccess\x20(0) ,# +b11111111 /# +b11111111 0# +b11111111 1# +b11111111 2# +b11111111 3# +b11111111 4# +b11111111 5# +b11111111 6# +b101 :# +b0 ># +b100 J# +sSuccess\x20(0) =* +b11111111 @* +b11111111 A* +b11111111 B* +b11111111 C* +b11111111 D* +b11111111 E* +b11111111 F* +b11111111 G* +b101 K* +b0 O* +b100 [* +sSuccess\x20(0) ?/ +b11111111 B/ +b11111111 C/ +b11111111 D/ +b11111111 E/ +b11111111 F/ +b11111111 G/ +b11111111 H/ +b11111111 I/ +b101 M/ +b0 Q/ +b100 ]/ +sSuccess\x20(0) A4 +b11111111 D4 +b11111111 E4 +b11111111 F4 +b11111111 G4 +b11111111 H4 +b11111111 I4 +b11111111 J4 +b11111111 K4 +b101 O4 +b0 S4 +b100 _4 +sSuccess\x20(0) V5 +b11111111 Y5 +b11111111 Z5 +b11111111 [5 +b11111111 \5 +b11111111 ]5 +b11111111 ^5 +b11111111 _5 +b11111111 `5 +b101 d5 +b0 h5 +b100 t5 +sSuccess\x20(0) k6 +b11111111 n6 +b11111111 o6 +b11111111 p6 +b11111111 q6 +b11111111 r6 +b11111111 s6 +b11111111 t6 +b11111111 u6 +b101 y6 +b0 }6 +b100 +7 +b10001111100000000 .7 +b101 /7 +b10001111100001000 17 +b10001111100010000 47 +b10001111100011000 77 +b0 :7 +b0 ;7 +b0 <7 +b100 ^7 +sSuccess\x20(0) q7 +b11111111 t7 +b11111111 u7 +b11111111 v7 +b11111111 w7 +b11111111 x7 +b11111111 y7 +b11111111 z7 +b11111111 {7 +b101 !8 +b0 %8 +b100 18 +b10001111100000000 48 +b101 58 +b10001111100001000 78 +b10001111100010000 :8 +b10001111100011000 =8 +b0 @8 +b0 A8 +b0 B8 +b100 d8 +#70000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#70500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +1& +sHdlNone\x20(0) ? +b0 @ +b0 A +sHdlNone\x20(0) J +sHdlSome\x20(1) f +b10010111100000000 h +b110 q +1;" +sHdlNone\x20(0) T" +b0 U" +b0 V" +sHdlNone\x20(0) _" +sHdlSome\x20(1) {" +b10010111100000000 }" +b110 (# +1P# +sHdlNone\x20(0) i# +b0 j# +b0 k# +sHdlNone\x20(0) t# +sHdlSome\x20(1) .* +b10010111100000000 0* +b110 9* +1a* +sHdlNone\x20(0) z* +b0 {* +b0 |* +sHdlNone\x20(0) '+ +b1111 >+ +1f+ +b11111111 g+ +b11111111 h+ +b11111111 i+ +b11111111 j+ +b11111111 k+ +b11111111 l+ +b11111111 m+ +b11111111 n+ +1,, +1-, +1., +1/, +10, +11, +12, +13, +1L, +b10001111100000000 M, +b101 N, +sCacheMiss\x20(2) O, +sHdlNone\x20(0) P, +b10010111100000000 [, +b110 \, +b10011111100000000 i, +b111 j, +sStart\x20(0) k, +b1000000000000 w, +b1000 x, +b1000000010000 '- +b1001 (- +b1000000100000 5- +b1010 6- +b1000000000000 C- +b1011 D- +b1000000010000 Q- +b1100 R- +b1000000100000 _- +b1101 `- +b10000000000000 m- +b1110 n- +b1111 |- +b10000 ,. +b10001 :. +b10010 H. +b10011 V. +b0 c. +b0 d. +b1111 q. +b1 y. +b10010111100000000 ~. +b110 !/ +sHdlSome\x20(1) "/ +sHdlSome\x20(1) %/ +b10 +/ +sHdlSome\x20(1) 0/ +b10010111100000000 2/ +b110 ;/ +1c/ +sHdlNone\x20(0) |/ +b0 }/ +b0 ~/ +sHdlNone\x20(0) )0 +b1111 @0 +1h0 +b11111111 i0 +b11111111 j0 +b11111111 k0 +b11111111 l0 +b11111111 m0 +b11111111 n0 +b11111111 o0 +b11111111 p0 +1.1 +1/1 +101 +111 +121 +131 +141 +151 +1N1 +b10001111100000000 O1 +b101 P1 +sCacheMiss\x20(2) Q1 +sHdlNone\x20(0) R1 +b10010111100000000 ]1 +b110 ^1 +b10011111100000000 k1 +b111 l1 +sStart\x20(0) m1 +b1000000000000 y1 +b1000 z1 +b1000000010000 )2 +b1001 *2 +b1000000100000 72 +b1010 82 +b1000000000000 E2 +b1011 F2 +b1000000010000 S2 +b1100 T2 +b1000000100000 a2 +b1101 b2 +b10000000000000 o2 +b1110 p2 +b1111 ~2 +b10000 .3 +b10001 <3 +b10010 J3 +b10011 X3 +b0 e3 +b0 f3 +b1111 s3 +b1 {3 +b10010111100000000 "4 +b110 #4 +sHdlSome\x20(1) $4 +sHdlSome\x20(1) '4 +b10 -4 +sHdlSome\x20(1) 24 +b10010111100000000 44 +b110 =4 +1e4 +sHdlNone\x20(0) ~4 +b0 !5 +b0 "5 +sHdlNone\x20(0) +5 +sHdlSome\x20(1) G5 +b10010111100000000 I5 +b110 R5 +1z5 +sHdlNone\x20(0) 56 +b0 66 +b0 76 +sHdlNone\x20(0) @6 +sHdlSome\x20(1) \6 +b10010111100000000 ^6 +b110 g6 +sHdlSome\x20(1) b7 +b10010111100000000 d7 +b110 m7 +b101 , +b110 - +b111 . +b1000 / +b1001 0 +b1010 1 +b1011 2 +b1100 3 +b1101 4 +b1110 5 +b1111 6 +b10000 7 +b10001 8 +b10010 9 +b10011 : +b0 ; +b1111 < +b101 A" +b110 B" +b111 C" +b1000 D" +b1001 E" +b1010 F" +b1011 G" +b1100 H" +b1101 I" +b1110 J" +b1111 K" +b10000 L" +b10001 M" +b10010 N" +b10011 O" +b0 P" +b1111 Q" +b101 V# +b110 W# +b111 X# +b1000 Y# +b1001 Z# +b1010 [# +b1011 \# +b1100 ]# +b1101 ^# +b1110 _# +b1111 `# +b10000 a# +b10001 b# +b10010 c# +b10011 d# +b0 e# +b1111 f# +b101 g* +b110 h* +b111 i* +b1000 j* +b1001 k* +b1010 l* +b1011 m* +b1100 n* +b1101 o* +b1110 p* +b1111 q* +b10000 r* +b10001 s* +b10010 t* +b10011 u* +b0 v* +b1111 w* +b101 i/ +b110 j/ +b111 k/ +b1000 l/ +b1001 m/ +b1010 n/ +b1011 o/ +b1100 p/ +b1101 q/ +b1110 r/ +b1111 s/ +b10000 t/ +b10001 u/ +b10010 v/ +b10011 w/ +b0 x/ +b1111 y/ +b101 k4 +b110 l4 +b111 m4 +b1000 n4 +b1001 o4 +b1010 p4 +b1011 q4 +b1100 r4 +b1101 s4 +b1110 t4 +b1111 u4 +b10000 v4 +b10001 w4 +b10010 x4 +b10011 y4 +b0 z4 +b1111 {4 +b101 "6 +b110 #6 +b111 $6 +b1000 %6 +b1001 &6 +b1010 '6 +b1011 (6 +b1100 )6 +b1101 *6 +b1110 +6 +b1111 ,6 +b10000 -6 +b10001 .6 +b10010 /6 +b10011 06 +b0 16 +b1111 26 +sError\x20(1) u +b0 x +b0 y +b0 z +b0 { +b0 | +b0 } +b0 ~ +b0 !" +b0 (" +b11 5" +sError\x20(1) ,# +b0 /# +b0 0# +b0 1# +b0 2# +b0 3# +b0 4# +b0 5# +b0 6# +b0 =# +b11 J# +sError\x20(1) =* +b0 @* +b0 A* +b0 B* +b0 C* +b0 D* +b0 E* +b0 F* +b0 G* +b0 N* +b11 [* +sError\x20(1) ?/ +b0 B/ +b0 C/ +b0 D/ +b0 E/ +b0 F/ +b0 G/ +b0 H/ +b0 I/ +b0 P/ +b11 ]/ +sError\x20(1) A4 +b0 D4 +b0 E4 +b0 F4 +b0 G4 +b0 H4 +b0 I4 +b0 J4 +b0 K4 +b0 R4 +b11 _4 +sError\x20(1) V5 +b0 Y5 +b0 Z5 +b0 [5 +b0 \5 +b0 ]5 +b0 ^5 +b0 _5 +b0 `5 +b0 g5 +b11 t5 +sError\x20(1) k6 +b0 n6 +b0 o6 +b0 p6 +b0 q6 +b0 r6 +b0 s6 +b0 t6 +b0 u6 +b0 |6 +b11 +7 +b10001111100001000 .7 +b10001111100010000 17 +b10001111100011000 47 +b0 77 +b0 87 +b0 97 +b11 ^7 +sError\x20(1) q7 +b0 t7 +b0 u7 +b0 v7 +b0 w7 +b0 x7 +b0 y7 +b0 z7 +b0 {7 +b0 $8 +b11 18 +b10001111100001000 48 +b10001111100010000 78 +b10001111100011000 :8 +b0 =8 +b0 >8 +b0 ?8 +b11 d8 +#71000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#71500000 +1! +1d +1y" +b11111111 .' +b11111111 /' +b11111111 0' +b11111111 1' +b11111111 2' +b11111111 3' +b11111111 4' +b11111111 5' +1,* +1./ +104 +1E5 +1Z6 +1`7 +0& +b10010111100001000 h +0;" +b10010111100001000 }" +0P# +b10010111100001000 0* +0a* +b10000 >+ +b11111111 C+ +b11111111 D+ +b11111111 E+ +b11111111 F+ +b11111111 G+ +b11111111 H+ +b11111111 I+ +b11111111 J+ +0f+ +b0 g+ +b0 h+ +b0 i+ +b0 j+ +b0 k+ +b0 l+ +b0 m+ +b0 n+ +0,, +0-, +0., +0/, +00, +01, +02, +03, +0L, +sReadingCache\x20(1) k, +b10000000000000 c. +b10100 d. +b10000 q. +b10 y. +sHdlSome\x20(1) {. +b1 #/ +b10010111100001000 2/ +0c/ +b10000 @0 +b11111111 E0 +b11111111 F0 +b11111111 G0 +b11111111 H0 +b11111111 I0 +b11111111 J0 +b11111111 K0 +b11111111 L0 +0h0 +b0 i0 +b0 j0 +b0 k0 +b0 l0 +b0 m0 +b0 n0 +b0 o0 +b0 p0 +0.1 +0/1 +001 +011 +021 +031 +041 +051 +0N1 +sReadingCache\x20(1) m1 +b10000000000000 e3 +b10100 f3 +b10000 s3 +b10 {3 +sHdlSome\x20(1) }3 +b1 %4 +b10010111100001000 44 +0e4 +b10010111100001000 I5 +0z5 +b10010111100001000 ^6 +b10010111100001000 d7 +b10100 ; +b10000 < +b10100 P" +b10000 Q" +b10100 e# +b10000 f# +b10100 v* +b10000 w* +b10100 x/ +b10000 y/ +b10100 z4 +b10000 {4 +b10100 16 +b10000 26 +b110 '" +b110 <# +b110 M* +b110 O/ +b110 Q4 +b110 f5 +b110 {6 +b10001111100010000 .7 +b10001111100011000 17 +b10010111100000000 47 +b110 57 +b100 67 +b110 #8 +b10001111100010000 48 +b10001111100011000 78 +b10010111100000000 :8 +b110 ;8 +b100 <8 +#72000000 +0! +b1000000000000 $ +b10101 % +0d +b1000000000000 9" +b10101 :" +0y" +b1000000000000 N# +b10101 O# +0,* +b1000000000000 _* +b10101 `* +0./ +b1000000000000 a/ +b10101 b/ +004 +b1000000000000 c4 +b10101 d4 +0E5 +b1000000000000 x5 +b10101 y5 +0Z6 +0`7 +#72500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +b10010111100010000 h +b10010111100010000 }" +b10010111100010000 0* +b11 y. +b10 #/ +b10010111100010000 2/ +b11 {3 +b10 %4 +b10010111100010000 44 +b10010111100010000 I5 +b10010111100010000 ^6 +b10010111100010000 d7 +b110 &" +b110 ;# +b110 L* +b110 N/ +b110 P4 +b110 e5 +b110 z6 +b10001111100011000 .7 +b10010111100000000 17 +b110 27 +b11 37 +b10010111100001000 47 +b110 "8 +b10001111100011000 48 +b10010111100000000 78 +b110 88 +b11 98 +b10010111100001000 :8 +#73000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#73500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +sHdlSome\x20(1) ? +b10001111100000000 @ +b101 A +sHdlSome\x20(1) J +b10010111100011000 h +sHdlSome\x20(1) T" +b10001111100000000 U" +b101 V" +sHdlSome\x20(1) _" +b10010111100011000 }" +sHdlSome\x20(1) i# +b10001111100000000 j# +b101 k# +sHdlSome\x20(1) t# +b10010111100011000 0* +sHdlSome\x20(1) z* +b10001111100000000 {* +b101 |* +sHdlSome\x20(1) '+ +sReturning\x20(5) O, +sHdlSome\x20(1) P, +b10010111100000000 s. +b110 t. +sHdlSome\x20(1) u. +b11 v. +b0 y. +sHdlNone\x20(0) {. +b0 ~. +b0 !/ +sHdlNone\x20(0) "/ +b0 #/ +sHdlNone\x20(0) %/ +b1 +/ +b10010111100011000 2/ +sHdlSome\x20(1) |/ +b10001111100000000 }/ +b101 ~/ +sHdlSome\x20(1) )0 +sReturning\x20(5) Q1 +sHdlSome\x20(1) R1 +b10010111100000000 u3 +b110 v3 +sHdlSome\x20(1) w3 +b11 x3 +b0 {3 +sHdlNone\x20(0) }3 +b0 "4 +b0 #4 +sHdlNone\x20(0) $4 +b0 %4 +sHdlNone\x20(0) '4 +b1 -4 +b10010111100011000 44 +sHdlSome\x20(1) ~4 +b10001111100000000 !5 +b101 "5 +sHdlSome\x20(1) +5 +b10010111100011000 I5 +sHdlSome\x20(1) 56 +b10001111100000000 66 +b101 76 +sHdlSome\x20(1) @6 +b10010111100011000 ^6 +b10010111100011000 d7 +sHdlNone\x20(0) t +sSuccess\x20(0) u +b110 %" +sHdlNone\x20(0) +# +sSuccess\x20(0) ,# +b110 :# +sHdlNone\x20(0) <* +sSuccess\x20(0) =* +b110 K* +sHdlNone\x20(0) >/ +sSuccess\x20(0) ?/ +b110 M/ +sHdlNone\x20(0) @4 +sSuccess\x20(0) A4 +b110 O4 +sHdlNone\x20(0) U5 +sSuccess\x20(0) V5 +b110 d5 +sHdlNone\x20(0) j6 +sSuccess\x20(0) k6 +b110 y6 +b10010111100000000 .7 +b110 /7 +b10 07 +b10010111100001000 17 +b10010111100010000 47 +sHdlNone\x20(0) p7 +sSuccess\x20(0) q7 +b110 !8 +b10010111100000000 48 +b110 58 +b10 68 +b10010111100001000 78 +b10010111100010000 :8 +#74000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#74500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +1& +sHdlNone\x20(0) ? +b0 @ +b0 A +sHdlNone\x20(0) J +b10011111100000000 h +b111 q +1;" +sHdlNone\x20(0) T" +b0 U" +b0 V" +sHdlNone\x20(0) _" +b10011111100000000 }" +b111 (# +1P# +sHdlNone\x20(0) i# +b0 j# +b0 k# +sHdlNone\x20(0) t# +b10011111100000000 0* +b111 9* +1a* +sHdlNone\x20(0) z* +b0 {* +b0 |* +sHdlNone\x20(0) '+ +b1111 >+ +b0 @+ +b1010100 C+ +b1100101 D+ +b1110011 E+ +b1110100 F+ +b100000 G+ +b1100100 H+ +b1100001 I+ +b1110100 J+ +b1100001 K+ +b101100 L+ +b100000 M+ +b1110100 N+ +b1100101 O+ +b1110011 P+ +b1110100 Q+ +b1101001 R+ +b1101110 S+ +b1100111 T+ +b101110 U+ +b101110 V+ +b101110 W+ +b1010 X+ +b1010100 Y+ +b1100101 Z+ +b1110011 [+ +b1110100 \+ +b100000 ]+ +b1010100 ^+ +b1100101 _+ +b1110011 `+ +b1110100 a+ +b100001 b+ +sHdlSome\x20(1) c+ +b1000 d+ +b10010111100000000 M, +b110 N, +sCacheMiss\x20(2) O, +sHdlNone\x20(0) P, +b10011111100000000 [, +b111 \, +b1000000000000 i, +b1000 j, +b1000000010000 w, +b1001 x, +b1000000100000 '- +b1010 (- +b1000000000000 5- +b1011 6- +b1000000010000 C- +b1100 D- +b1000000100000 Q- +b1101 R- +b10000000000000 _- +b1110 `- +b1111 n- +b10000 |- +b10001 ,. +b10010 :. +b10011 H. +b10100 V. +b0 c. +b0 d. +b1111 q. +sHdlNone\x20(0) u. +b0 v. +b10011111100000000 ~. +b111 !/ +sHdlSome\x20(1) "/ +sHdlSome\x20(1) %/ +b10 +/ +b10011111100000000 2/ +b111 ;/ +1c/ +sHdlNone\x20(0) |/ +b0 }/ +b0 ~/ +sHdlNone\x20(0) )0 +b1111 @0 +b0 B0 +b1010100 E0 +b1100101 F0 +b1110011 G0 +b1110100 H0 +b100000 I0 +b1100100 J0 +b1100001 K0 +b1110100 L0 +b1100001 M0 +b101100 N0 +b100000 O0 +b1110100 P0 +b1100101 Q0 +b1110011 R0 +b1110100 S0 +b1101001 T0 +b1101110 U0 +b1100111 V0 +b101110 W0 +b101110 X0 +b101110 Y0 +b1010 Z0 +b1010100 [0 +b1100101 \0 +b1110011 ]0 +b1110100 ^0 +b100000 _0 +b1010100 `0 +b1100101 a0 +b1110011 b0 +b1110100 c0 +b100001 d0 +sHdlSome\x20(1) e0 +b1000 f0 +b10010111100000000 O1 +b110 P1 +sCacheMiss\x20(2) Q1 +sHdlNone\x20(0) R1 +b10011111100000000 ]1 +b111 ^1 +b1000000000000 k1 +b1000 l1 +b1000000010000 y1 +b1001 z1 +b1000000100000 )2 +b1010 *2 +b1000000000000 72 +b1011 82 +b1000000010000 E2 +b1100 F2 +b1000000100000 S2 +b1101 T2 +b10000000000000 a2 +b1110 b2 +b1111 p2 +b10000 ~2 +b10001 .3 +b10010 <3 +b10011 J3 +b10100 X3 +b0 e3 +b0 f3 +b1111 s3 +sHdlNone\x20(0) w3 +b0 x3 +b10011111100000000 "4 +b111 #4 +sHdlSome\x20(1) $4 +sHdlSome\x20(1) '4 +b10 -4 +b10011111100000000 44 +b111 =4 +1e4 +sHdlNone\x20(0) ~4 +b0 !5 +b0 "5 +sHdlNone\x20(0) +5 +b10011111100000000 I5 +b111 R5 +1z5 +sHdlNone\x20(0) 56 +b0 66 +b0 76 +sHdlNone\x20(0) @6 +b10011111100000000 ^6 +b111 g6 +b10011111100000000 d7 +b111 m7 +b110 , +b111 - +b1000 . +b1001 / +b1010 0 +b1011 1 +b1100 2 +b1101 3 +b1110 4 +b1111 5 +b10000 6 +b10001 7 +b10010 8 +b10011 9 +b10100 : +b0 ; +b1111 < +b110 A" +b111 B" +b1000 C" +b1001 D" +b1010 E" +b1011 F" +b1100 G" +b1101 H" +b1110 I" +b1111 J" +b10000 K" +b10001 L" +b10010 M" +b10011 N" +b10100 O" +b0 P" +b1111 Q" +b110 V# +b111 W# +b1000 X# +b1001 Y# +b1010 Z# +b1011 [# +b1100 \# +b1101 ]# +b1110 ^# +b1111 _# +b10000 `# +b10001 a# +b10010 b# +b10011 c# +b10100 d# +b0 e# +b1111 f# +b110 g* +b111 h* +b1000 i* +b1001 j* +b1010 k* +b1011 l* +b1100 m* +b1101 n* +b1110 o* +b1111 p* +b10000 q* +b10001 r* +b10010 s* +b10011 t* +b10100 u* +b0 v* +b1111 w* +b110 i/ +b111 j/ +b1000 k/ +b1001 l/ +b1010 m/ +b1011 n/ +b1100 o/ +b1101 p/ +b1110 q/ +b1111 r/ +b10000 s/ +b10001 t/ +b10010 u/ +b10011 v/ +b10100 w/ +b0 x/ +b1111 y/ +b110 k4 +b111 l4 +b1000 m4 +b1001 n4 +b1010 o4 +b1011 p4 +b1100 q4 +b1101 r4 +b1110 s4 +b1111 t4 +b10000 u4 +b10001 v4 +b10010 w4 +b10011 x4 +b10100 y4 +b0 z4 +b1111 {4 +b110 "6 +b111 #6 +b1000 $6 +b1001 %6 +b1010 &6 +b1011 '6 +b1100 (6 +b1101 )6 +b1110 *6 +b1111 +6 +b10000 ,6 +b10001 -6 +b10010 .6 +b10011 /6 +b10100 06 +b0 16 +b1111 26 +b110 (" +b100 5" +b110 =# +b100 J# +b110 N* +b100 [* +b110 P/ +b100 ]/ +b110 R4 +b100 _4 +b110 g5 +b100 t5 +b110 |6 +b100 +7 +b1 07 +b10 37 +b11 67 +b10010111100011000 77 +b110 87 +b100 97 +b100 ^7 +b110 $8 +b100 18 +b1 68 +b10 98 +b11 <8 +b10010111100011000 =8 +b110 >8 +b100 ?8 +b100 d8 +#75000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#75500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +0& +b10011111100001000 h +0;" +b10011111100001000 }" +0P# +b10011111100001000 0* +0a* +b10000 >+ +sReturning\x20(5) k, +b1010100 n, +b1100101 o, +b1110011 p, +b1110100 q, +b100000 r, +b1100100 s, +b1100001 t, +b1110100 u, +sReadingCache\x20(1) y, +b1000000000000 c. +b10101 d. +b10000 q. +b1 #/ +b10011111100001000 2/ +0c/ +b10000 @0 +sReturning\x20(5) m1 +b1010100 p1 +b1100101 q1 +b1110011 r1 +b1110100 s1 +b100000 t1 +b1100100 u1 +b1100001 v1 +b1110100 w1 +sReadingCache\x20(1) {1 +b1000000000000 e3 +b10101 f3 +b10000 s3 +b1 %4 +b10011111100001000 44 +0e4 +b10011111100001000 I5 +0z5 +b10011111100001000 ^6 +b10011111100001000 d7 +b10101 ; +b10000 < +b10101 P" +b10000 Q" +b10101 e# +b10000 f# +b10101 v* +b10000 w* +b10101 x/ +b10000 y/ +b10101 z4 +b10000 {4 +b10101 16 +b10000 26 +sHdlSome\x20(1) t +b11111111 x +b11111111 y +b11111111 z +b11111111 { +b11111111 | +b11111111 } +b11111111 ~ +b11111111 !" +b111 )" +b101 5" +sHdlSome\x20(1) +# +b11111111 /# +b11111111 0# +b11111111 1# +b11111111 2# +b11111111 3# +b11111111 4# +b11111111 5# +b11111111 6# +b111 ># +b101 J# +sHdlSome\x20(1) <* +b11111111 @* +b11111111 A* +b11111111 B* +b11111111 C* +b11111111 D* +b11111111 E* +b11111111 F* +b11111111 G* +b111 O* +b101 [* +sHdlSome\x20(1) >/ +b11111111 B/ +b11111111 C/ +b11111111 D/ +b11111111 E/ +b11111111 F/ +b11111111 G/ +b11111111 H/ +b11111111 I/ +b111 Q/ +b101 ]/ +sHdlSome\x20(1) @4 +b11111111 D4 +b11111111 E4 +b11111111 F4 +b11111111 G4 +b11111111 H4 +b11111111 I4 +b11111111 J4 +b11111111 K4 +b111 S4 +b101 _4 +sHdlSome\x20(1) U5 +b11111111 Y5 +b11111111 Z5 +b11111111 [5 +b11111111 \5 +b11111111 ]5 +b11111111 ^5 +b11111111 _5 +b11111111 `5 +b111 h5 +b101 t5 +sHdlSome\x20(1) j6 +b11111111 n6 +b11111111 o6 +b11111111 p6 +b11111111 q6 +b11111111 r6 +b11111111 s6 +b11111111 t6 +b11111111 u6 +b111 }6 +b101 +7 +b0 07 +b1 37 +b10 67 +b11 97 +b10011111100000000 :7 +b111 ;7 +b100 <7 +b101 ^7 +sHdlSome\x20(1) p7 +b11111111 t7 +b11111111 u7 +b11111111 v7 +b11111111 w7 +b11111111 x7 +b11111111 y7 +b11111111 z7 +b11111111 {7 +b111 %8 +b101 18 +b0 68 +b1 98 +b10 <8 +b11 ?8 +b10011111100000000 @8 +b111 A8 +b100 B8 +b101 d8 +#76000000 +0! +b10110 % +0d +b10110 :" +0y" +b10110 O# +0,* +b10110 `* +0./ +b10110 b/ +004 +b10110 d4 +0E5 +b10110 y5 +0Z6 +0`7 +#76500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +b10011111100010000 h +b10011111100010000 }" +b10011111100010000 0* +b1000 @+ +b0 C+ +b0 D+ +b0 E+ +b0 F+ +b0 G+ +b0 H+ +b0 I+ +b0 J+ +b0 K+ +b0 L+ +b0 M+ +b0 N+ +b0 O+ +b0 P+ +b0 Q+ +b0 R+ +b0 S+ +b0 T+ +b0 U+ +b0 V+ +b0 W+ +b0 X+ +b0 Y+ +b0 Z+ +b0 [+ +b0 \+ +b0 ]+ +b0 ^+ +b0 _+ +b0 `+ +b0 a+ +b0 b+ +sHdlNone\x20(0) c+ +b0 d+ +1f+ +b11111111 g+ +b11111111 h+ +b11111111 i+ +b11111111 j+ +b11111111 k+ +b11111111 l+ +b11111111 m+ +b11111111 n+ +1,, +1-, +1., +1/, +10, +11, +12, +13, +1L, +sReturning\x20(5) y, +b1101110 |, +b1100111 }, +b101110 ~, +b101110 !- +b101110 "- +b1010 #- +b1010100 $- +b1100101 %- +b1 y. +b10 #/ +b10011111100010000 2/ +b1000 B0 +b0 E0 +b0 F0 +b0 G0 +b0 H0 +b0 I0 +b0 J0 +b0 K0 +b0 L0 +b0 M0 +b0 N0 +b0 O0 +b0 P0 +b0 Q0 +b0 R0 +b0 S0 +b0 T0 +b0 U0 +b0 V0 +b0 W0 +b0 X0 +b0 Y0 +b0 Z0 +b0 [0 +b0 \0 +b0 ]0 +b0 ^0 +b0 _0 +b0 `0 +b0 a0 +b0 b0 +b0 c0 +b0 d0 +sHdlNone\x20(0) e0 +b0 f0 +1h0 +b11111111 i0 +b11111111 j0 +b11111111 k0 +b11111111 l0 +b11111111 m0 +b11111111 n0 +b11111111 o0 +b11111111 p0 +1.1 +1/1 +101 +111 +121 +131 +141 +151 +1N1 +sReturning\x20(5) {1 +b1101110 ~1 +b1100111 !2 +b101110 "2 +b101110 #2 +b101110 $2 +b1010 %2 +b1010100 &2 +b1100101 '2 +b1 {3 +b10 %4 +b10011111100010000 44 +b10011111100010000 I5 +b10011111100010000 ^6 +b10011111100010000 d7 +sError\x20(1) u +b0 x +b0 y +b0 z +b0 { +b0 | +b0 } +b0 ~ +b0 !" +b111 (" +sError\x20(1) ,# +b0 /# +b0 0# +b0 1# +b0 2# +b0 3# +b0 4# +b0 5# +b0 6# +b111 =# +sError\x20(1) =* +b0 @* +b0 A* +b0 B* +b0 C* +b0 D* +b0 E* +b0 F* +b0 G* +b111 N* +sError\x20(1) ?/ +b0 B/ +b0 C/ +b0 D/ +b0 E/ +b0 F/ +b0 G/ +b0 H/ +b0 I/ +b111 P/ +sError\x20(1) A4 +b0 D4 +b0 E4 +b0 F4 +b0 G4 +b0 H4 +b0 I4 +b0 J4 +b0 K4 +b111 R4 +sError\x20(1) V5 +b0 Y5 +b0 Z5 +b0 [5 +b0 \5 +b0 ]5 +b0 ^5 +b0 _5 +b0 `5 +b111 g5 +sError\x20(1) k6 +b0 n6 +b0 o6 +b0 p6 +b0 q6 +b0 r6 +b0 s6 +b0 t6 +b0 u6 +b111 |6 +b10010111100001000 .7 +b10010111100010000 17 +b10010111100011000 47 +b10011111100000000 77 +b111 87 +b10011111100001000 :7 +sError\x20(1) q7 +b0 t7 +b0 u7 +b0 v7 +b0 w7 +b0 x7 +b0 y7 +b0 z7 +b0 {7 +b111 $8 +b10010111100001000 48 +b10010111100010000 78 +b10010111100011000 :8 +b10011111100000000 =8 +b111 >8 +b10011111100001000 @8 +#77000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#77500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +b10011111100011000 h +b10011111100011000 }" +b10011111100011000 0* +b1 @+ +b1010 C+ +b1010011 D+ +b1100101 E+ +b1100011 F+ +b1101111 G+ +b1101110 H+ +b1100100 I+ +b100000 J+ +b1000011 K+ +b1100001 L+ +b1100011 M+ +b1101000 N+ +b1100101 O+ +b100000 P+ +b1001100 Q+ +b1101001 R+ +b1101110 S+ +b1100101 T+ +b1010 U+ +b1010100 V+ +b1100101 W+ +b1110011 X+ +b1110100 Y+ +b1101001 Z+ +b1101110 [+ +b1100111 \+ +b101110 ]+ +b101110 ^+ +b101110 _+ +b101110 `+ +b101110 a+ +b1010 b+ +sHdlSome\x20(1) c+ +b1000 d+ +0f+ +b0 g+ +b0 h+ +b0 i+ +b0 j+ +b0 k+ +b0 l+ +b0 m+ +b0 n+ +0,, +0-, +0., +0/, +00, +01, +02, +03, +0L, +sReadingCache\x20(1) )- +b10 y. +sHdlSome\x20(1) {. +b11 #/ +b10011111100011000 2/ +b1 B0 +b1010 E0 +b1010011 F0 +b1100101 G0 +b1100011 H0 +b1101111 I0 +b1101110 J0 +b1100100 K0 +b100000 L0 +b1000011 M0 +b1100001 N0 +b1100011 O0 +b1101000 P0 +b1100101 Q0 +b100000 R0 +b1001100 S0 +b1101001 T0 +b1101110 U0 +b1100101 V0 +b1010 W0 +b1010100 X0 +b1100101 Y0 +b1110011 Z0 +b1110100 [0 +b1101001 \0 +b1101110 ]0 +b1100111 ^0 +b101110 _0 +b101110 `0 +b101110 a0 +b101110 b0 +b101110 c0 +b1010 d0 +sHdlSome\x20(1) e0 +b1000 f0 +0h0 +b0 i0 +b0 j0 +b0 k0 +b0 l0 +b0 m0 +b0 n0 +b0 o0 +b0 p0 +0.1 +0/1 +001 +011 +021 +031 +041 +051 +0N1 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^+ +b1100101 _+ +b1110011 `+ +b1110100 a+ +b100001 b+ +sReturning\x20(5) )- +b1010 ,- +b1010011 -- +b1100101 .- +b1100011 /- +b1101111 0- +b1101110 1- +b1100100 2- +b100000 3- +sReadingCache\x20(1) 7- +b11 y. +sHdlNone\x20(0) "/ +b0 #/ +sHdlNone\x20(0) 0/ +b0 2/ +b0 ;/ +b0 B0 +b1010100 E0 +b1100101 F0 +b1110011 G0 +b1110100 H0 +b100000 I0 +b1100100 J0 +b1100001 K0 +b1110100 L0 +b1100001 M0 +b101100 N0 +b100000 O0 +b1110100 P0 +b1110011 R0 +b1110100 S0 +b1100111 V0 +b101110 W0 +b101110 X0 +b101110 Y0 +b1010 Z0 +b1010100 [0 +b1100101 \0 +b1110011 ]0 +b1110100 ^0 +b100000 _0 +b1010100 `0 +b1100101 a0 +b1110011 b0 +b1110100 c0 +b100001 d0 +sReturning\x20(5) +2 +b1010 .2 +b1010011 /2 +b1100101 02 +b1100011 12 +b1101111 22 +b1101110 32 +b1100100 42 +b100000 52 +sReadingCache\x20(1) 92 +b11 {3 +sHdlNone\x20(0) $4 +b0 %4 +sHdlNone\x20(0) 24 +b0 44 +b0 =4 +sHdlNone\x20(0) G5 +b0 I5 +b0 R5 +sHdlNone\x20(0) \6 +b0 ^6 +b0 g6 +sHdlNone\x20(0) b7 +b0 d7 +b0 m7 +b111 &" +b111 ;# +b111 L* +b111 N/ +b111 P4 +b111 e5 +b111 z6 +b10010111100011000 .7 +b10011111100000000 17 +b111 27 +b10011111100001000 47 +b10011111100010000 77 +b10011111100011000 :7 +b11101 <7 +b111 "8 +b10010111100011000 48 +b10011111100000000 78 +b111 88 +b10011111100001000 :8 +b10011111100010000 =8 +b10011111100011000 @8 +b11101 B8 +#79000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#79500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +sHdlSome\x20(1) ? +b10010111100000000 @ +b110 A +sHdlSome\x20(1) J +sHdlSome\x20(1) T" +b10010111100000000 U" +b110 V" +sHdlSome\x20(1) _" +sHdlSome\x20(1) i# +b10010111100000000 j# +b110 k# +sHdlSome\x20(1) t# +sHdlSome\x20(1) z* +b10010111100000000 {* +b110 |* +sHdlSome\x20(1) '+ +sReturning\x20(5) O, +sHdlSome\x20(1) P, +sReturning\x20(5) 7- +b1010100 :- +b1100101 ;- +b1110011 <- +b1110100 =- +b100000 >- +b1100100 ?- +b1100001 @- +b1110100 A- +sReadingCache\x20(1) E- +b10011111100000000 s. +b111 t. +b0 y. +sHdlNone\x20(0) {. +b0 ~. +b0 !/ +sHdlNone\x20(0) %/ +b1 +/ +sHdlSome\x20(1) |/ +b10010111100000000 }/ +b110 ~/ +sHdlSome\x20(1) )0 +sReturning\x20(5) Q1 +sHdlSome\x20(1) R1 +sReturning\x20(5) 92 +b1010100 <2 +b1100101 =2 +b1110011 >2 +b1110100 ?2 +b100000 @2 +b1100100 A2 +b1100001 B2 +b1110100 C2 +sReadingCache\x20(1) G2 +b10011111100000000 u3 +b111 v3 +b0 {3 +sHdlNone\x20(0) }3 +b0 "4 +b0 #4 +sHdlNone\x20(0) '4 +b1 -4 +sHdlSome\x20(1) ~4 +b10010111100000000 !5 +b110 "5 +sHdlSome\x20(1) +5 +sHdlSome\x20(1) 56 +b10010111100000000 66 +b110 76 +sHdlSome\x20(1) @6 +sSuccess\x20(0) u +b11111111 x +b11111111 y +b11111111 z +b11111111 { +b11111111 | +b11111111 } +b11111111 ~ +b11111111 !" +b111 %" +b0 )" +b100 5" +sSuccess\x20(0) ,# +b11111111 /# +b11111111 0# +b11111111 1# +b11111111 2# +b11111111 3# +b11111111 4# +b11111111 5# +b11111111 6# +b111 :# +b0 ># +b100 J# +sSuccess\x20(0) =* +b11111111 @* +b11111111 A* +b11111111 B* +b11111111 C* +b11111111 D* +b11111111 E* +b11111111 F* +b11111111 G* +b111 K* +b0 O* +b100 [* +sSuccess\x20(0) ?/ +b11111111 B/ +b11111111 C/ +b11111111 D/ +b11111111 E/ +b11111111 F/ +b11111111 G/ +b11111111 H/ +b11111111 I/ +b111 M/ +b0 Q/ +b100 ]/ +sSuccess\x20(0) A4 +b11111111 D4 +b11111111 E4 +b11111111 F4 +b11111111 G4 +b11111111 H4 +b11111111 I4 +b11111111 J4 +b11111111 K4 +b111 O4 +b0 S4 +b100 _4 +sSuccess\x20(0) V5 +b11111111 Y5 +b11111111 Z5 +b11111111 [5 +b11111111 \5 +b11111111 ]5 +b11111111 ^5 +b11111111 _5 +b11111111 `5 +b111 d5 +b0 h5 +b100 t5 +sSuccess\x20(0) k6 +b11111111 n6 +b11111111 o6 +b11111111 p6 +b11111111 q6 +b11111111 r6 +b11111111 s6 +b11111111 t6 +b11111111 u6 +b111 y6 +b0 }6 +b100 +7 +b10011111100000000 .7 +b111 /7 +b10011111100001000 17 +b10011111100010000 47 +b10011111100011000 77 +b11100 97 +b0 :7 +b0 ;7 +b0 <7 +b100 ^7 +sSuccess\x20(0) q7 +b11111111 t7 +b11111111 u7 +b11111111 v7 +b11111111 w7 +b11111111 x7 +b11111111 y7 +b11111111 z7 +b11111111 {7 +b111 !8 +b0 %8 +b100 18 +b10011111100000000 48 +b111 58 +b10011111100001000 78 +b10011111100010000 :8 +b10011111100011000 =8 +b11100 ?8 +b0 @8 +b0 A8 +b0 B8 +b100 d8 +#80000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#80500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +1& +sHdlNone\x20(0) ? +b0 @ +b0 A +sHdlNone\x20(0) J +1;" +sHdlNone\x20(0) T" +b0 U" +b0 V" +sHdlNone\x20(0) _" +1P# +sHdlNone\x20(0) i# +b0 j# +b0 k# +sHdlNone\x20(0) t# +1a* +sHdlNone\x20(0) z* +b0 {* +b0 |* +sHdlNone\x20(0) '+ +b1111 >+ +b1000 @+ +b0 C+ +b0 D+ +b0 E+ +b0 F+ +b0 G+ +b0 H+ +b0 I+ +b0 J+ +b0 K+ +b0 L+ +b0 M+ +b0 N+ +b0 O+ +b0 P+ +b0 Q+ +b0 R+ +b0 S+ +b0 T+ +b0 U+ +b0 V+ +b0 W+ +b0 X+ +b0 Y+ +b0 Z+ +b0 [+ +b0 \+ +b0 ]+ +b0 ^+ +b0 _+ +b0 `+ +b0 a+ +b0 b+ +sHdlNone\x20(0) c+ +b0 d+ +1f+ +b11111111 g+ +b11111111 h+ +b11111111 i+ +b11111111 j+ +b11111111 k+ +b11111111 l+ +b11111111 m+ +b11111111 n+ +1,, +1-, +1., +1/, +10, +11, +12, +13, +1L, +b10011111100000000 M, +b111 N, +sCacheMiss\x20(2) O, +sHdlNone\x20(0) P, +b1000000000000 [, +b1000 \, +sReturning\x20(5) ], +b1010100 `, +b1100101 a, +b1110011 b, +b1110100 c, +b100000 d, +b1100100 e, +b1100001 f, +b1110100 g, +b1000000010000 i, +b1001 j, +b1101110 n, +b1100111 o, +b101110 p, +b101110 q, +b101110 r, +b1010 s, +b1010100 t, +b1100101 u, +b1000000100000 w, +b1010 x, +b1010 |, +b1010011 }, +b1100101 ~, +b1100011 !- +b1101111 "- +b1101110 #- +b1100100 $- +b100000 %- +b1000000000000 '- +b1011 (- +b1010100 ,- +b1100101 -- +b1110011 .- +b1110100 /- +b100000 0- +b1100100 1- +b1100001 2- +b1110100 3- +b1000000010000 5- +b1100 6- +b1101110 :- +b1100111 ;- +b101110 <- +b101110 =- +b101110 >- +b1010 ?- +b1010100 @- +b1100101 A- +b1000000100000 C- +b1101 D- +sStart\x20(0) E- +b10000000000000 Q- +b1110 R- +b1111 `- +b10000 n- +b10001 |- +b10010 ,. +b10011 :. +b10100 H. +b1000000000000 U. +b10101 V. +b0 c. +b0 d. +b1111 q. +b1 y. +1c/ +sHdlNone\x20(0) |/ +b0 }/ +b0 ~/ +sHdlNone\x20(0) )0 +b1111 @0 +b1000 B0 +b0 E0 +b0 F0 +b0 G0 +b0 H0 +b0 I0 +b0 J0 +b0 K0 +b0 L0 +b0 M0 +b0 N0 +b0 O0 +b0 P0 +b0 Q0 +b0 R0 +b0 S0 +b0 T0 +b0 U0 +b0 V0 +b0 W0 +b0 X0 +b0 Y0 +b0 Z0 +b0 [0 +b0 \0 +b0 ]0 +b0 ^0 +b0 _0 +b0 `0 +b0 a0 +b0 b0 +b0 c0 +b0 d0 +sHdlNone\x20(0) e0 +b0 f0 +1h0 +b11111111 i0 +b11111111 j0 +b11111111 k0 +b11111111 l0 +b11111111 m0 +b11111111 n0 +b11111111 o0 +b11111111 p0 +1.1 +1/1 +101 +111 +121 +131 +141 +151 +1N1 +b10011111100000000 O1 +b111 P1 +sCacheMiss\x20(2) Q1 +sHdlNone\x20(0) R1 +b1000000000000 ]1 +b1000 ^1 +sReturning\x20(5) _1 +b1010100 b1 +b1100101 c1 +b1110011 d1 +b1110100 e1 +b100000 f1 +b1100100 g1 +b1100001 h1 +b1110100 i1 +b1000000010000 k1 +b1001 l1 +b1101110 p1 +b1100111 q1 +b101110 r1 +b101110 s1 +b101110 t1 +b1010 u1 +b1010100 v1 +b1100101 w1 +b1000000100000 y1 +b1010 z1 +b1010 ~1 +b1010011 !2 +b1100101 "2 +b1100011 #2 +b1101111 $2 +b1101110 %2 +b1100100 &2 +b100000 '2 +b1000000000000 )2 +b1011 *2 +b1010100 .2 +b1100101 /2 +b1110011 02 +b1110100 12 +b100000 22 +b1100100 32 +b1100001 42 +b1110100 52 +b1000000010000 72 +b1100 82 +b1101110 <2 +b1100111 =2 +b101110 >2 +b101110 ?2 +b101110 @2 +b1010 A2 +b1010100 B2 +b1100101 C2 +b1000000100000 E2 +b1101 F2 +sStart\x20(0) G2 +b10000000000000 S2 +b1110 T2 +b1111 b2 +b10000 p2 +b10001 ~2 +b10010 .3 +b10011 <3 +b10100 J3 +b1000000000000 W3 +b10101 X3 +b0 e3 +b0 f3 +b1111 s3 +b1 {3 +1e4 +sHdlNone\x20(0) ~4 +b0 !5 +b0 "5 +sHdlNone\x20(0) +5 +1z5 +sHdlNone\x20(0) 56 +b0 66 +b0 76 +sHdlNone\x20(0) @6 +b111 , +b1000 - +b1001 . +b1010 / +b1011 0 +b1100 1 +b1101 2 +b1110 3 +b1111 4 +b10000 5 +b10001 6 +b10010 7 +b10011 8 +b10100 9 +b10101 : +b0 ; +b1111 < +b111 A" +b1000 B" +b1001 C" +b1010 D" +b1011 E" +b1100 F" +b1101 G" +b1110 H" +b1111 I" +b10000 J" +b10001 K" +b10010 L" +b10011 M" +b10100 N" +b10101 O" +b0 P" +b1111 Q" +b111 V# +b1000 W# +b1001 X# +b1010 Y# +b1011 Z# +b1100 [# +b1101 \# +b1110 ]# +b1111 ^# +b10000 _# +b10001 `# +b10010 a# +b10011 b# +b10100 c# +b10101 d# +b0 e# +b1111 f# +b111 g* +b1000 h* +b1001 i* +b1010 j* +b1011 k* +b1100 l* +b1101 m* +b1110 n* +b1111 o* +b10000 p* +b10001 q* +b10010 r* +b10011 s* +b10100 t* +b10101 u* +b0 v* +b1111 w* +b111 i/ +b1000 j/ +b1001 k/ +b1010 l/ +b1011 m/ +b1100 n/ +b1101 o/ +b1110 p/ +b1111 q/ +b10000 r/ +b10001 s/ +b10010 t/ +b10011 u/ +b10100 v/ +b10101 w/ +b0 x/ +b1111 y/ +b111 k4 +b1000 l4 +b1001 m4 +b1010 n4 +b1011 o4 +b1100 p4 +b1101 q4 +b1110 r4 +b1111 s4 +b10000 t4 +b10001 u4 +b10010 v4 +b10011 w4 +b10100 x4 +b10101 y4 +b0 z4 +b1111 {4 +b111 "6 +b1000 #6 +b1001 $6 +b1010 %6 +b1011 &6 +b1100 '6 +b1101 (6 +b1110 )6 +b1111 *6 +b10000 +6 +b10001 ,6 +b10010 -6 +b10011 .6 +b10100 /6 +b10101 06 +b0 16 +b1111 26 +sError\x20(1) u +b0 x +b0 y +b0 z +b0 { +b0 | +b0 } +b0 ~ +b0 !" +b0 (" +b11 5" +sError\x20(1) ,# +b0 /# +b0 0# +b0 1# +b0 2# +b0 3# +b0 4# +b0 5# +b0 6# +b0 =# +b11 J# +sError\x20(1) =* +b0 @* +b0 A* +b0 B* +b0 C* +b0 D* +b0 E* +b0 F* +b0 G* +b0 N* +b11 [* +sError\x20(1) ?/ +b0 B/ +b0 C/ +b0 D/ +b0 E/ +b0 F/ +b0 G/ +b0 H/ +b0 I/ +b0 P/ +b11 ]/ +sError\x20(1) A4 +b0 D4 +b0 E4 +b0 F4 +b0 G4 +b0 H4 +b0 I4 +b0 J4 +b0 K4 +b0 R4 +b11 _4 +sError\x20(1) V5 +b0 Y5 +b0 Z5 +b0 [5 +b0 \5 +b0 ]5 +b0 ^5 +b0 _5 +b0 `5 +b0 g5 +b11 t5 +sError\x20(1) k6 +b0 n6 +b0 o6 +b0 p6 +b0 q6 +b0 r6 +b0 s6 +b0 t6 +b0 u6 +b0 |6 +b11 +7 +b10011111100001000 .7 +b10011111100010000 17 +b10011111100011000 47 +b11011 67 +b0 77 +b0 87 +b0 97 +b11 ^7 +sError\x20(1) q7 +b0 t7 +b0 u7 +b0 v7 +b0 w7 +b0 x7 +b0 y7 +b0 z7 +b0 {7 +b0 $8 +b11 18 +b10011111100001000 48 +b10011111100010000 78 +b10011111100011000 :8 +b11011 <8 +b0 =8 +b0 >8 +b0 ?8 +b11 d8 +#81000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#81500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +0& +0;" +0P# +0a* +b10000 >+ +b1 @+ +b1010 C+ +b1010011 D+ +b1100101 E+ +b1100011 F+ +b1101111 G+ +b1101110 H+ +b1100100 I+ +b100000 J+ +b1000011 K+ +b1100001 L+ +b1100011 M+ +b1101000 N+ +b1100101 O+ +b100000 P+ +b1001100 Q+ +b1101001 R+ +b1101110 S+ +b1100101 T+ +b1010 U+ +b1010100 V+ +b1100101 W+ +b1110011 X+ +b1110100 Y+ +b1101001 Z+ +b1101110 [+ +b1100111 \+ +b101110 ]+ +b101110 ^+ +b101110 _+ +b101110 `+ +b101110 a+ +b1010 b+ +sHdlSome\x20(1) c+ +b1000 d+ +0f+ +b0 g+ +b0 h+ +b0 i+ +b0 j+ +b0 k+ +b0 l+ +b0 m+ +b0 n+ +0,, +0-, +0., +0/, +00, +01, +02, +03, +0L, +sReadingCache\x20(1) E- +b1000000000000 c. +b10110 d. +b10000 q. +b10 y. +sHdlSome\x20(1) {. +0c/ +b10000 @0 +b1 B0 +b1010 E0 +b1010011 F0 +b1100101 G0 +b1100011 H0 +b1101111 I0 +b1101110 J0 +b1100100 K0 +b100000 L0 +b1000011 M0 +b1100001 N0 +b1100011 O0 +b1101000 P0 +b1100101 Q0 +b100000 R0 +b1001100 S0 +b1101001 T0 +b1101110 U0 +b1100101 V0 +b1010 W0 +b1010100 X0 +b1100101 Y0 +b1110011 Z0 +b1110100 [0 +b1101001 \0 +b1101110 ]0 +b1100111 ^0 +b101110 _0 +b101110 `0 +b101110 a0 +b101110 b0 +b101110 c0 +b1010 d0 +sHdlSome\x20(1) e0 +b1000 f0 +0h0 +b0 i0 +b0 j0 +b0 k0 +b0 l0 +b0 m0 +b0 n0 +b0 o0 +b0 p0 +0.1 +0/1 +001 +011 +021 +031 +041 +051 +0N1 +sReadingCache\x20(1) G2 +b1000000000000 e3 +b10110 f3 +b10000 s3 +b10 {3 +sHdlSome\x20(1) }3 +0e4 +0z5 +b10110 ; +b10000 < +b10110 P" +b10000 Q" +b10110 e# +b10000 f# +b10110 v* +b10000 w* +b10110 x/ +b10000 y/ +b10110 z4 +b10000 {4 +b10110 16 +b10000 26 +b0 '" +b10 5" +b0 <# +b10 J# +b0 M* +b10 [* +b0 O/ +b10 ]/ +b0 Q4 +b10 _4 +b0 f5 +b10 t5 +b0 {6 +b10 +7 +b10011111100010000 .7 +b10011111100011000 17 +b11010 37 +b0 47 +b0 57 +b0 67 +b10 ^7 +b0 #8 +b10 18 +b10011111100010000 48 +b10011111100011000 78 +b11010 98 +b0 :8 +b0 ;8 +b0 <8 +b10 d8 +#82000000 +0! +b10111 % +0d +b10111 :" +0y" +b10111 O# +0,* +b10111 `* +0./ +b10111 b/ +004 +b10111 d4 +0E5 +b10111 y5 +0Z6 +0`7 +#82500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +b0 @+ +b1010100 C+ +b1100101 D+ +b1110011 E+ +b1110100 F+ +b100000 G+ +b1100100 H+ +b1100001 I+ +b1110100 J+ +b1100001 K+ +b101100 L+ +b100000 M+ +b1110100 N+ +b1110011 P+ +b1110100 Q+ +b1100111 T+ +b101110 U+ +b101110 V+ +b101110 W+ +b1010 X+ +b1010100 Y+ +b1100101 Z+ +b1110011 [+ +b1110100 \+ +b100000 ]+ +b1010100 ^+ +b1100101 _+ +b1110011 `+ +b1110100 a+ +b100001 b+ +sReturning\x20(5) E- +b1010 H- +b1010011 I- +b1100101 J- +b1100011 K- +b1101111 L- +b1101110 M- +b1100100 N- +b100000 O- +sReadingCache\x20(1) S- +b11 y. +b0 B0 +b1010100 E0 +b1100101 F0 +b1110011 G0 +b1110100 H0 +b100000 I0 +b1100100 J0 +b1100001 K0 +b1110100 L0 +b1100001 M0 +b101100 N0 +b100000 O0 +b1110100 P0 +b1110011 R0 +b1110100 S0 +b1100111 V0 +b101110 W0 +b101110 X0 +b101110 Y0 +b1010 Z0 +b1010100 [0 +b1100101 \0 +b1110011 ]0 +b1110100 ^0 +b100000 _0 +b1010100 `0 +b1100101 a0 +b1110011 b0 +b1110100 c0 +b100001 d0 +sReturning\x20(5) G2 +b1010 J2 +b1010011 K2 +b1100101 L2 +b1100011 M2 +b1101111 N2 +b1101110 O2 +b1100100 P2 +b100000 Q2 +sReadingCache\x20(1) U2 +b11 {3 +sHdlNone\x20(0) t +sSuccess\x20(0) u +b0 &" +b1 5" +sHdlNone\x20(0) +# +sSuccess\x20(0) ,# +b0 ;# +b1 J# +sHdlNone\x20(0) <* +sSuccess\x20(0) =* +b0 L* +b1 [* +sHdlNone\x20(0) >/ +sSuccess\x20(0) ?/ +b0 N/ +b1 ]/ +sHdlNone\x20(0) @4 +sSuccess\x20(0) A4 +b0 P4 +b1 _4 +sHdlNone\x20(0) U5 +sSuccess\x20(0) V5 +b0 e5 +b1 t5 +sHdlNone\x20(0) j6 +sSuccess\x20(0) k6 +b0 z6 +b1 +7 +b10011111100011000 .7 +b11001 07 +b0 17 +b0 27 +b0 37 +b1 ^7 +sHdlNone\x20(0) p7 +sSuccess\x20(0) q7 +b0 "8 +b1 18 +b10011111100011000 48 +b11001 68 +b0 78 +b0 88 +b0 98 +b1 d8 +#83000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#83500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +sHdlSome\x20(1) f +b10000000000000 h +b1110 q +sHdlSome\x20(1) {" +b10000000000000 }" +b1110 (# +sHdlSome\x20(1) .* +b10000000000000 0* +b1110 9* +sCacheMiss\x20(2) S- +sReadingCache\x20(1) a- +b10000000000000 ~. +b1110 !/ +sHdlSome\x20(1) "/ +sHdlSome\x20(1) %/ +b10 +/ +sHdlSome\x20(1) 0/ +b10000000000000 2/ +b1110 ;/ +sCacheMiss\x20(2) U2 +sReadingCache\x20(1) c2 +b10000000000000 "4 +b1110 #4 +sHdlSome\x20(1) $4 +sHdlSome\x20(1) '4 +b10 -4 +sHdlSome\x20(1) 24 +b10000000000000 44 +b1110 =4 +sHdlSome\x20(1) G5 +b10000000000000 I5 +b1110 R5 +sHdlSome\x20(1) \6 +b10000000000000 ^6 +b1110 g6 +sHdlSome\x20(1) b7 +b10000000000000 d7 +b1110 m7 +b11000 07 +b11000 68 +#84000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#84500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +b10000000001000 h +b10000000001000 }" +b10000000001000 0* +sCacheMiss\x20(2) a- +sReadingCache\x20(1) o- +b1 #/ +b10000000001000 2/ +sCacheMiss\x20(2) c2 +sReadingCache\x20(1) q2 +b1 %4 +b10000000001000 44 +b10000000001000 I5 +b10000000001000 ^6 +b10000000001000 d7 +b1110 &" +b10 5" +b1110 ;# +b10 J# +b1110 L* +b10 [* +b1110 N/ +b10 ]/ +b1110 P4 +b10 _4 +b1110 e5 +b10 t5 +b1110 z6 +b10 +7 +b10111 07 +b10000000000000 17 +b1110 27 +b100 37 +b10 ^7 +b1110 "8 +b10 18 +b10111 68 +b10000000000000 78 +b1110 88 +b100 98 +b10 d8 +#85000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#85500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +b10000000010000 h +b10000000010000 }" +b10000000010000 0* +sCacheMiss\x20(2) o- +sReadingCache\x20(1) }- +b10 #/ +b10000000010000 2/ +sCacheMiss\x20(2) q2 +sReadingCache\x20(1) !3 +b10 %4 +b10000000010000 44 +b10000000010000 I5 +b10000000010000 ^6 +b10000000010000 d7 +b1110 '" +b11 5" +b1110 <# +b11 J# +b1110 M* +b11 [* +b1110 O/ +b11 ]/ +b1110 Q4 +b11 _4 +b1110 f5 +b11 t5 +b1110 {6 +b11 +7 +b10110 07 +b11 37 +b10000000001000 47 +b1110 57 +b100 67 +b11 ^7 +b1110 #8 +b11 18 +b10110 68 +b11 98 +b10000000001000 :8 +b1110 ;8 +b100 <8 +b11 d8 +#86000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#86500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +b10000000011000 h +b10000000011000 }" +b10000000011000 0* +sCacheMiss\x20(2) }- +sReadingCache\x20(1) -. +b11 #/ +b10000000011000 2/ +sCacheMiss\x20(2) !3 +sReadingCache\x20(1) /3 +b11 %4 +b10000000011000 44 +b10000000011000 I5 +b10000000011000 ^6 +b10000000011000 d7 +b1110 (" +b100 5" +b1110 =# +b100 J# +b1110 N* +b100 [* +b1110 P/ +b100 ]/ +b1110 R4 +b100 _4 +b1110 g5 +b100 t5 +b1110 |6 +b100 +7 +b10101 07 +b10 37 +b11 67 +b10000000010000 77 +b1110 87 +b100 97 +b100 ^7 +b1110 $8 +b100 18 +b10101 68 +b10 98 +b11 <8 +b10000000010000 =8 +b1110 >8 +b100 ?8 +b100 d8 +#87000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#87500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +sHdlNone\x20(0) f +b0 h +b0 q +sHdlNone\x20(0) {" +b0 }" +b0 (# +sHdlNone\x20(0) .* +b0 0* +b0 9* +sCacheMiss\x20(2) -. +sReadingCache\x20(1) ;. +sHdlNone\x20(0) "/ +b0 #/ +sHdlNone\x20(0) 0/ +b0 2/ +b0 ;/ +sCacheMiss\x20(2) /3 +sReadingCache\x20(1) =3 +sHdlNone\x20(0) $4 +b0 %4 +sHdlNone\x20(0) 24 +b0 44 +b0 =4 +sHdlNone\x20(0) G5 +b0 I5 +b0 R5 +sHdlNone\x20(0) \6 +b0 ^6 +b0 g6 +sHdlNone\x20(0) b7 +b0 d7 +b0 m7 +b1110 )" +b101 5" +b1110 ># +b101 J# +b1110 O* +b101 [* +b1110 Q/ +b101 ]/ +b1110 S4 +b101 _4 +b1110 h5 +b101 t5 +b1110 }6 +b101 +7 +b10100 07 +b1 37 +b10 67 +b11 97 +b10000000011000 :7 +b1110 ;7 +b100 <7 +b101 ^7 +b1110 %8 +b101 18 +b10100 68 +b1 98 +b10 <8 +b11 ?8 +b10000000011000 @8 +b1110 A8 +b100 B8 +b101 d8 +#88000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#88500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +sCacheMiss\x20(2) ;. +sReadingCache\x20(1) I. +sCacheMiss\x20(2) =3 +sReadingCache\x20(1) K3 +b10011 07 +b0 37 +b1 67 +b10 97 +b11 <7 +b10011 68 +b0 98 +b1 <8 +b10 ?8 +b11 B8 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+b11110010 y +b11110010 z +b11110010 { +b11110010 | +b11110010 } +b11110010 ~ +b11110010 !" +b1110 %" +b0 )" +b100 5" +sSuccess\x20(0) ,# +b11110010 /# +b11110010 0# +b11110010 1# +b11110010 2# +b11110010 3# +b11110010 4# +b11110010 5# +b11110010 6# +b1110 :# +b0 ># +b100 J# +sSuccess\x20(0) =* +b11110010 @* +b11110010 A* +b11110010 B* +b11110010 C* +b11110010 D* +b11110010 E* +b11110010 F* +b11110010 G* +b1110 K* +b0 O* +b100 [* +sSuccess\x20(0) ?/ +b11110010 B/ +b11110010 C/ +b11110010 D/ +b11110010 E/ +b11110010 F/ +b11110010 G/ +b11110010 H/ +b11110010 I/ +b1110 M/ +b0 Q/ +b100 ]/ +sSuccess\x20(0) A4 +b11110010 D4 +b11110010 E4 +b11110010 F4 +b11110010 G4 +b11110010 H4 +b11110010 I4 +b11110010 J4 +b11110010 K4 +b1110 O4 +b0 S4 +b100 _4 +sSuccess\x20(0) V5 +b11110010 Y5 +b11110010 Z5 +b11110010 [5 +b11110010 \5 +b11110010 ]5 +b11110010 ^5 +b11110010 _5 +b11110010 `5 +b1110 d5 +b0 h5 +b100 t5 +sSuccess\x20(0) k6 +b11110010 n6 +b11110010 o6 +b11110010 p6 +b11110010 q6 +b11110010 r6 +b11110010 s6 +b11110010 t6 +b11110010 u6 +b1110 y6 +b0 }6 +b100 +7 +b10000000000000 .7 +b1110 /7 +b10000000001000 17 +b10000000010000 47 +b10000000011000 77 +b0 :7 +b0 ;7 +b100 ^7 +sSuccess\x20(0) q7 +b11110010 t7 +b11110010 u7 +b11110010 v7 +b11110010 w7 +b11110010 x7 +b11110010 y7 +b11110010 z7 +b11110010 {7 +b1110 !8 +b0 %8 +b100 18 +b10000000000000 48 +b1110 58 +b10000000001000 78 +b10000000010000 :8 +b10000000011000 =8 +b0 @8 +b0 A8 +b100 d8 +#109000000 +0! +0d +0y" +0,* +0./ +004 +0E5 +0Z6 +0`7 +#109500000 +1! +1d +1y" +1,* +1./ +104 +1E5 +1Z6 +1`7 +1& +b1000000000000 @ +b1000 A +b1010100 B +b1100101 C +b1110011 D +b1110100 E +b100000 F +b1100100 G +b1100001 H +b1110100 I +sHdlNone\x20(0) J +1;" +b1000000000000 U" +b1000 V" +b1010100 W" +b1100101 X" +b1110011 Y" +b1110100 Z" +b100000 [" +b1100100 \" +b1100001 ]" +b1110100 ^" +sHdlNone\x20(0) _" +1P# +b1000000000000 j# +b1000 k# +b1010100 l# +b1100101 m# +b1110011 n# +b1110100 o# +b100000 p# +b1100100 q# +b1100001 r# +b1110100 s# +sHdlNone\x20(0) t# +1a* +b1000000000000 {* +b1000 |* +b1010100 }* +b1100101 ~* +b1110011 !+ +b1110100 "+ +b100000 #+ +b1100100 $+ +b1100001 %+ +b1110100 &+ +sHdlNone\x20(0) '+ +b1111 >+ +1A+ +1f+ +b11110010 g+ +b11110010 h+ +b11110010 i+ +b11110010 j+ +b11110010 k+ +b11110010 l+ +b11110010 m+ +b11110010 n+ +1,, +1-, +1., +1/, +10, +11, +12, +13, +1L, +b1000000000000 M, +b1000 N, +sHdlNone\x20(0) P, +b1010100 R, +b1100101 S, +b1110011 T, +b1110100 U, +b100000 V, +b1100100 W, +b1100001 X, +b1110100 Y, +b1000000010000 [, +b1001 \, +b1101110 `, +b1100111 a, +b101110 b, +b101110 c, +b101110 d, +b1010 e, +b1010100 f, +b1100101 g, +b1000000100000 i, +b1010 j, +b1010 n, +b1010011 o, +b1100101 p, +b1100011 q, +b1101111 r, +b1101110 s, +b1100100 t, +b100000 u, +b1000000000000 w, +b1011 x, +b1010100 |, +b1100101 }, +b1110011 ~, +b1110100 !- +b100000 "- +b1100100 #- +b1100001 $- +b1110100 %- +b1000000010000 '- +b1100 (- +b1101110 ,- +b1100111 -- +b101110 .- +b101110 /- +b101110 0- +b1010 1- +b1010100 2- +b1100101 3- +b1000000100000 5- +b1101 6- +b1010 :- +b1010011 ;- +b1100101 <- +b1100011 =- +b1101111 >- +b1101110 ?- +b1100100 @- +b100000 A- +b10000000000000 C- +b1110 D- +sCacheMiss\x20(2) E- +b0 H- +b0 I- +b0 J- +b0 K- +b0 L- +b0 M- +b0 N- +b0 O- +b1111 R- +b10000 `- +b10001 n- +b10010 |- +b10011 ,. +b10100 :. +b1000000000000 G. +b10101 H. +sReturning\x20(5) I. +b1010100 L. +b1100101 M. +b1110011 N. +b1110100 O. +b100000 P. +b1100100 Q. +b1100001 R. +b1110100 S. +b10110 V. +b0 c. +b0 d. +sStart\x20(0) e. +b0 h. +b0 i. +b0 j. +b0 k. +b0 l. +b0 m. +b0 n. +b0 o. +b1111 q. +b1 y. +1c/ +b1000000000000 }/ +b1000 ~/ +b1010100 !0 +b1100101 "0 +b1110011 #0 +b1110100 $0 +b100000 %0 +b1100100 &0 +b1100001 '0 +b1110100 (0 +sHdlNone\x20(0) )0 +b1111 @0 +1C0 +1h0 +b11110010 i0 +b11110010 j0 +b11110010 k0 +b11110010 l0 +b11110010 m0 +b11110010 n0 +b11110010 o0 +b11110010 p0 +1.1 +1/1 +101 +111 +121 +131 +141 +151 +1N1 +b1000000000000 O1 +b1000 P1 +sHdlNone\x20(0) R1 +b1010100 T1 +b1100101 U1 +b1110011 V1 +b1110100 W1 +b100000 X1 +b1100100 Y1 +b1100001 Z1 +b1110100 [1 +b1000000010000 ]1 +b1001 ^1 +b1101110 b1 +b1100111 c1 +b101110 d1 +b101110 e1 +b101110 f1 +b1010 g1 +b1010100 h1 +b1100101 i1 +b1000000100000 k1 +b1010 l1 +b1010 p1 +b1010011 q1 +b1100101 r1 +b1100011 s1 +b1101111 t1 +b1101110 u1 +b1100100 v1 +b100000 w1 +b1000000000000 y1 +b1011 z1 +b1010100 ~1 +b1100101 !2 +b1110011 "2 +b1110100 #2 +b100000 $2 +b1100100 %2 +b1100001 &2 +b1110100 '2 +b1000000010000 )2 +b1100 *2 +b1101110 .2 +b1100111 /2 +b101110 02 +b101110 12 +b101110 22 +b1010 32 +b1010100 42 +b1100101 52 +b1000000100000 72 +b1101 82 +b1010 <2 +b1010011 =2 +b1100101 >2 +b1100011 ?2 +b1101111 @2 +b1101110 A2 +b1100100 B2 +b100000 C2 +b10000000000000 E2 +b1110 F2 +sCacheMiss\x20(2) G2 +b0 J2 +b0 K2 +b0 L2 +b0 M2 +b0 N2 +b0 O2 +b0 P2 +b0 Q2 +b1111 T2 +b10000 b2 +b10001 p2 +b10010 ~2 +b10011 .3 +b10100 <3 +b1000000000000 I3 +b10101 J3 +sReturning\x20(5) K3 +b1010100 N3 +b1100101 O3 +b1110011 P3 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+b10110 :. +b10111 H. +sStart\x20(0) I. +b0 L. +b0 M. +b0 N. +b0 O. +b0 P. +b0 Q. +b0 R. +b0 S. +b11000 V. +b11 y. +b1000000100000 }/ +b1010 ~/ +b1010 !0 +b1010011 "0 +b1100101 #0 +b1100011 $0 +b1101111 %0 +b1101110 &0 +b1100100 '0 +b100000 (0 +b0 q0 +b0 r0 +b0 s0 +b0 t0 +b0 u0 +b0 v0 +b0 w0 +b0 x0 +b11110010 y0 +b11110010 z0 +b11110010 {0 +b11110010 |0 +b11110010 }0 +b11110010 ~0 +b11110010 !1 +b11110010 "1 +061 +071 +081 +091 +0:1 +0;1 +0<1 +0=1 +1>1 +1?1 +1@1 +1A1 +1B1 +1C1 +1D1 +1E1 +b1000000100000 O1 +b1010 P1 +b1010 T1 +b1010011 U1 +b1100101 V1 +b1100011 W1 +b1101111 X1 +b1101110 Y1 +b1100100 Z1 +b100000 [1 +b1000000000000 ]1 +b1011 ^1 +b1010100 b1 +b1100101 c1 +b1110011 d1 +b1110100 e1 +b100000 f1 +b1100100 g1 +b1100001 h1 +b1110100 i1 +b1000000010000 k1 +b1100 l1 +b1101110 p1 +b1100111 q1 +b101110 r1 +b101110 s1 +b101110 t1 +b1010 u1 +b1010100 v1 +b1100101 w1 +b1000000100000 y1 +b1101 z1 +b1010 ~1 +b1010011 !2 +b1100101 "2 +b1100011 #2 +b1101111 $2 +b1101110 %2 +b1100100 &2 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+b1110100 ). +b10110 ,. +b10111 :. +sStart\x20(0) ;. +b0 >. +b0 ?. +b0 @. +b0 A. +b0 B. +b0 C. +b0 D. +b0 E. +b11000 H. +b11001 V. +b0 s. +b0 t. +sHdlNone\x20(0) x. +b0 y. +b0 +/ +0K/ +b1000000000000 }/ +b1011 ~/ +b1010100 !0 +b1100101 "0 +b1110011 #0 +b1110100 $0 +b100000 %0 +b1100100 &0 +b1100001 '0 +b1110100 (0 +b0 y0 +b0 z0 +b0 {0 +b0 |0 +b0 }0 +b0 ~0 +b0 !1 +b0 "1 +b11110010 #1 +b11110010 $1 +b11110010 %1 +b11110010 &1 +b11110010 '1 +b11110010 (1 +b11110010 )1 +b11110010 *1 +sHdlSome\x20(1) +1 +b10000 ,1 +0>1 +0?1 +0@1 +0A1 +0B1 +0C1 +0D1 +0E1 +1F1 +1G1 +1H1 +1I1 +1J1 +1K1 +1L1 +1M1 +b1000000000000 O1 +b1011 P1 +b1010100 T1 +b1100101 U1 +b1110011 V1 +b1110100 W1 +b100000 X1 +b1100100 Y1 +b1100001 Z1 +b1110100 [1 +b1000000010000 ]1 +b1100 ^1 +b1101110 b1 +b1100111 c1 +b101110 d1 +b101110 e1 +b101110 f1 +b1010 g1 +b1010100 h1 +b1100101 i1 +b1000000100000 k1 +b1101 l1 +b1010 p1 +b1010011 q1 +b1100101 r1 +b1100011 s1 +b1101111 t1 +b1101110 u1 +b1100100 v1 +b100000 w1 +b10000000000000 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+b10000 x, +b10001 (- +b10010 6- +b10011 D- +b10100 R- +b1000000000000 _- +b10101 `- +sReturning\x20(5) a- +b1010100 d- +b1100101 e- +b1110011 f- +b1110100 g- +b100000 h- +b1100100 i- +b1100001 j- +b1110100 k- +b10110 n- +b10111 |- +sStart\x20(0) }- +b0 ". +b0 #. +b0 $. +b0 %. +b0 &. +b0 '. +b0 (. +b0 ). +b11000 ,. +b11001 :. +b11010 H. +b0 U. +b0 V. +b1110 q. +b1000000100000 }/ +b1101 ~/ +b1010 !0 +b1010011 "0 +b1100101 #0 +b1100011 $0 +b1101111 %0 +b1101110 &0 +b1100100 '0 +b100000 (0 +b1110 @0 +b1000000100000 O1 +b1101 P1 +b1010 T1 +b1010011 U1 +b1100101 V1 +b1100011 W1 +b1101111 X1 +b1101110 Y1 +b1100100 Z1 +b100000 [1 +b10000000000000 ]1 +b1110 ^1 +b11110010 b1 +b11110010 c1 +b11110010 d1 +b11110010 e1 +b11110010 f1 +b11110010 g1 +b11110010 h1 +b11110010 i1 +b1111 l1 +b10000 z1 +b10001 *2 +b10010 82 +b10011 F2 +b10100 T2 +b1000000000000 a2 +b10101 b2 +sReturning\x20(5) c2 +b1010100 f2 +b1100101 g2 +b1110011 h2 +b1110100 i2 +b100000 j2 +b1100100 k2 +b1100001 l2 +b1110100 m2 +b10110 p2 +b10111 ~2 +sStart\x20(0) !3 +b0 $3 +b0 %3 +b0 &3 +b0 '3 +b0 (3 +b0 )3 +b0 *3 +b0 +3 +b11000 .3 +b11001 <3 +b11010 J3 +b0 W3 +b0 X3 +b1110 s3 +b1000000100000 !5 +b1101 "5 +b1010 #5 +b1010011 $5 +b1100101 %5 +b1100011 &5 +b1101111 '5 +b1101110 (5 +b1100100 )5 +b100000 *5 +b1000000100000 66 +b1101 76 +b1010 86 +b1010011 96 +b1100101 :6 +b1100011 ;6 +b1101111 <6 +b1101110 =6 +b1100100 >6 +b100000 ?6 +b1101 , +b1110 - +b1111 . +b10000 / +b10001 0 +b10010 1 +b10011 2 +b10100 3 +b10101 4 +b10110 5 +b10111 6 +b11000 7 +b11001 8 +b11010 9 +b0 : +b1110 < +b1101 A" +b1110 B" +b1111 C" +b10000 D" +b10001 E" +b10010 F" +b10011 G" +b10100 H" +b10101 I" +b10110 J" +b10111 K" +b11000 L" +b11001 M" +b11010 N" +b0 O" +b1110 Q" +b1101 V# +b1110 W# +b1111 X# +b10000 Y# +b10001 Z# +b10010 [# +b10011 \# +b10100 ]# +b10101 ^# +b10110 _# +b10111 `# +b11000 a# +b11001 b# +b11010 c# +b0 d# +b1110 f# +b1101 g* +b1110 h* +b1111 i* +b10000 j* +b10001 k* +b10010 l* +b10011 m* +b10100 n* +b10101 o* +b10110 p* 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Notices.txt for copyright information + +use cpu::{ + config::{CpuConfig, UnitConfig}, + fetch::{ + FetchToDecodeInterface, FetchToDecodeInterfaceInner, MemoryInterface, + MemoryOperationErrorKind, MemoryOperationFinish, MemoryOperationFinishKind, + MemoryOperationKind, MemoryOperationStart, fetch, + }, + next_pc::{FETCH_BLOCK_ID_WIDTH, NextPcToFetchInterface, NextPcToFetchInterfaceInner}, + unit::UnitKind, + util::array_vec::ArrayVec, +}; +use fayalite::{ + prelude::*, + sim::vcd::VcdWriterDecls, + util::{DebugAsDisplay, RcWriter}, +}; +use std::{cell::RefCell, collections::VecDeque, fmt, num::NonZeroUsize}; + +struct Random { + index: u64, +} + +impl Random { + fn next(&mut self) -> u64 { + let index = self.index; + self.index = self.index.wrapping_add(1); + // make a pseudo-random number deterministically based on index + index + .wrapping_add(1) + .wrapping_mul(0x18C49126EABE7A0D) // random prime + .rotate_left(32) + .wrapping_mul(0x92B38C197608A6B) // random prime + .rotate_right(60) + } +} + +const MEMORY_QUEUE_SIZE: usize = 16; + +#[hdl] +struct MemoryQueueEntry { + addr: UInt<64>, + fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, + cycles_left: UInt<8>, +} + +impl MemoryQueueEntry { + #[hdl] + fn default_sim(self) -> SimValue { + #[hdl(sim)] + Self { + addr: 0u64, + fetch_block_id: self.fetch_block_id.zero(), + cycles_left: 0u8, + } + } + fn get_next_delay(random: &mut Random) -> u8 { + if random.next() % 32 == 0 { 30 } else { 5 } + } +} + +const MEMORY_DATA: &str = "Test data, testing...\nTest Test!\nSecond Cache Line\nTesting.....\n"; +const MEMORY_START: u64 = 0x1000; +const MEMORY_RANGE2: std::ops::Range = 0x2000..0x3000; +const MEMORY_ERROR_RANGE: std::ops::Range = 0x10F00..0x20F00; +const MEMORY_ERROR_STEP: u64 = 0x1000; + +fn read_memory(start: u64, len: usize) -> Option<&'static [u8]> { + if MEMORY_ERROR_RANGE.contains(&start) { + let start = start - MEMORY_ERROR_RANGE.start; + let fail_at = start / MEMORY_ERROR_STEP; + let offset = start % MEMORY_ERROR_STEP; + return if offset < fail_at { + [0xFFu8; MEMORY_DATA.len()].get(..len) + } else { + None + }; + } + if MEMORY_RANGE2.contains(&start) { + return [0xF2u8; MEMORY_DATA.len()].get(..len); + } + MEMORY_DATA + .as_bytes() + .get(start.checked_sub(MEMORY_START)?.try_into().ok()?..)? + .get(..len) +} + +#[hdl_module(extern)] +fn mock_memory(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let memory_interface: MemoryInterface> = + m.input(MemoryInterface[config]); + #[hdl] + let queue_debug: ArrayVec> = m.output(); + m.register_clock_for_past(cd.clk); + m.extern_module_simulation_fn( + (cd, memory_interface, queue_debug), + |(cd, memory_interface, queue_debug), mut sim| async move { + // intentionally have a different sequence each time we're reset + let random = RefCell::new(Random { index: 0 }); + sim.resettable( + cd, + async |mut sim| { + #[hdl] + let MemoryInterface::<_> { + start, + finish, + next_fetch_block_ids, + config: _, + } = memory_interface; + sim.write(start.ready, false).await; + sim.write(finish.data, finish.ty().data.HdlNone()).await; + sim.write(next_fetch_block_ids, next_fetch_block_ids.ty().HdlNone()) + .await; + sim.write( + queue_debug, + queue_debug.ty().new_sim(MemoryQueueEntry.default_sim()), + ) + .await; + }, + |sim, ()| run_fn(cd, memory_interface, queue_debug, &random, sim), + ) + .await; + }, + ); + #[hdl] + async fn run_fn( + cd: Expr, + memory_interface: Expr>>, + queue_debug: Expr>>, + random: &RefCell, + mut sim: ExternModuleSimulationState, + ) { + let mut random = random.borrow_mut(); + let config = memory_interface.config.ty(); + let finish_data_ty = memory_interface.finish.data.ty(); + let next_fetch_block_ids_ty = memory_interface.next_fetch_block_ids.ty(); + let mut queue: VecDeque> = VecDeque::new(); + loop { + for entry in &mut queue { + entry.cycles_left = entry.cycles_left.as_int().saturating_sub(1).to_sim_value(); + } + let sim_queue = queue_debug + .ty() + .from_iter_sim(MemoryQueueEntry.default_sim(), &queue) + .ok() + .expect("queue is known to be small enough"); + sim.write(queue_debug, sim_queue).await; + sim.write_bool( + memory_interface.start.ready, + queue.len() < MEMORY_QUEUE_SIZE && random.next() % 32 != 0, + ) + .await; + sim.write( + memory_interface.next_fetch_block_ids, + #[hdl(sim)] + next_fetch_block_ids_ty.HdlSome( + next_fetch_block_ids_ty + .HdlSome + .from_iter_sim(0u8, queue.iter().map(|entry| &entry.fetch_block_id)) + .ok() + .expect("queue is known to be small enough"), + ), + ) + .await; + let finish_data = if let Some(entry) = queue + .front() + .filter(|entry| entry.cycles_left.as_int() == 0) + { + #[hdl(sim)] + let MemoryQueueEntry { + addr, + fetch_block_id: _, + cycles_left: _, + } = entry; + let addr = addr.as_int(); + let mut read_data = + repeat(0u8, finish_data_ty.HdlSome.read_data.len()).to_sim_value(); + let kind = if let Some(data) = read_memory(addr, read_data.len()) { + for (l, r) in read_data.iter_mut().zip(data) { + *l = r.to_sim_value(); + } + #[hdl(sim)] + MemoryOperationFinishKind.Success( + #[hdl(sim)] + MemoryOperationKind.Read(), + ) + } else { + #[hdl(sim)] + MemoryOperationFinishKind.Error( + #[hdl(sim)] + MemoryOperationErrorKind.Generic(), + ) + }; + #[hdl(sim)] + finish_data_ty.HdlSome( + #[hdl(sim)] + MemoryOperationFinish::<_> { + kind, + read_data, + config, + }, + ) + } else { + #[hdl(sim)] + finish_data_ty.HdlNone() + }; + sim.write(memory_interface.finish.data, &finish_data).await; + sim.wait_for_clock_edge(cd.clk).await; + println!( + "Dump mock memory queue: {:#?}", + Vec::from_iter(queue.iter().map(|v| { + DebugAsDisplay(format!( + "fid={:#x} addr={:#x}", + v.fetch_block_id.as_int(), + v.addr.as_int(), + )) + })) + ); + if sim + .read_past_bool(memory_interface.start.ready, cd.clk) + .await + { + #[hdl(sim)] + if let HdlSome(memory_operation_start) = + sim.read_past(memory_interface.start.data, cd.clk).await + { + #[hdl(sim)] + let MemoryOperationStart::<_> { + kind, + addr, + write_data: _, + fetch_block_id, + config: _, + } = memory_operation_start; + #[hdl(sim)] + match kind { + MemoryOperationKind::Read => {} + MemoryOperationKind::Write => unreachable!(), + } + let entry = #[hdl(sim)] + MemoryQueueEntry { + addr, + fetch_block_id, + cycles_left: MemoryQueueEntry::get_next_delay(&mut random), + }; + println!("mock memory start: {entry:#?}"); + queue.push_back(entry); + } + } + if sim + .read_past_bool(memory_interface.finish.ready, cd.clk) + .await + { + #[hdl(sim)] + if let HdlSome(finish_data) = finish_data { + let Some(entry) = queue.pop_front() else { + unreachable!(); + }; + #[hdl(sim)] + let MemoryOperationFinish::<_> { + kind, + read_data, + config: _, + } = finish_data; + let kind = #[hdl(sim)] + match kind { + MemoryOperationFinishKind::Error(_) => Err(()), + MemoryOperationFinishKind::Success(_) => Ok(()), + }; + println!( + "mock memory finish: kind={kind:?} read_data={read_data:?} {entry:#?}" + ); + } + } + } + } +} + +#[hdl_module] +fn dut(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let from_next_pc: NextPcToFetchInterface> = + m.input(NextPcToFetchInterface[config]); + #[hdl] + let to_decode: FetchToDecodeInterface> = + m.output(FetchToDecodeInterface[config]); + #[hdl] + let fetch = instance(fetch(config)); + #[hdl] + let fetch { + cd: fetch_cd, + memory_interface: fetch_memory_interface, + from_next_pc: fetch_from_next_pc, + to_decode: fetch_to_decode, + } = fetch; + connect(fetch_cd, cd); + connect(fetch_from_next_pc, from_next_pc); + connect(to_decode, fetch_to_decode); + #[hdl] + let mock_memory = instance(mock_memory(config)); + #[hdl] + let mock_memory { + cd: mock_memory_cd, + memory_interface: mock_memory_interface, + queue_debug: _, + } = mock_memory; + connect(mock_memory_cd, cd); + connect(mock_memory_interface, fetch_memory_interface); +} + +#[derive(Clone)] +struct FetchTestOperation { + start_pc: u64, + fetch_block_id: u8, + fetch_block_data: [u8; FETCH_WIDTH_IN_BYTES], + error: Option>, +} + +impl PartialEq for FetchTestOperation { + #[hdl] + fn eq(&self, other: &Self) -> bool { + let Self { + start_pc, + fetch_block_id, + fetch_block_data, + ref error, + } = *self; + if let Some(error) = error { + #[hdl(sim)] + match error { + MemoryOperationErrorKind::Generic => {} + } + } + start_pc == other.start_pc + && fetch_block_id == other.fetch_block_id + && fetch_block_data == other.fetch_block_data + && error.is_some() == other.error.is_some() + } +} + +impl fmt::Debug for FetchTestOperation { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + start_pc, + fetch_block_id, + fetch_block_data, + error, + } = self; + let mut debug_struct = f.debug_struct("FetchTestOperation"); + debug_struct.field("start_pc", &format_args!("{start_pc:#x}")); + debug_struct.field("fetch_block_id", &format_args!("{fetch_block_id:#x}")); + if fetch_block_data.iter().all(|v| *v == fetch_block_data[0]) { + debug_struct.field( + "fetch_block_data", + &format_args!( + "[b'{}'; {FETCH_WIDTH_IN_BYTES}]", + fetch_block_data[0].escape_ascii(), + ), + ); + } else { + debug_struct.field( + "fetch_block_data", + &format_args!("b\"{}\"", fetch_block_data.escape_ascii()), + ); + } + debug_struct.field("error", error).finish() + } +} + +const LOG2_FETCH_WIDTH_IN_BYTES: u8 = 3; +const FETCH_WIDTH_IN_BYTES: usize = 1 << LOG2_FETCH_WIDTH_IN_BYTES; +const LOG2_CACHE_LINE_SIZE_IN_BYTES: u8 = 5; +const CACHE_LINE_SIZE_IN_BYTES: usize = 1 << LOG2_CACHE_LINE_SIZE_IN_BYTES; + +// needs to be a multiple of the cache line size +const _: [(); CACHE_LINE_SIZE_IN_BYTES * 2] = [(); MEMORY_DATA.len()]; + +fn fetch_test_operations() -> Vec { + #[track_caller] + fn mem_data(r: std::ops::RangeFrom) -> [u8; FETCH_WIDTH_IN_BYTES] { + *MEMORY_DATA[r] + .as_bytes() + .first_chunk() + .expect("start should be in-range") + } + #[hdl] + fn generic_error() -> SimValue { + #[hdl(sim)] + MemoryOperationErrorKind.Generic() + } + let mut last_fetch_block_id = 0u8.wrapping_sub(1); + macro_rules! op { + { + $($field:ident: $value:expr,)* + } => { + FetchTestOperation { + fetch_block_id: { + last_fetch_block_id = last_fetch_block_id.wrapping_add(1); + last_fetch_block_id + }, + $($field: $value,)* + } + }; + } + vec![ + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1010, + fetch_block_data: mem_data(0x10..), + error: None, + }, + op! { + start_pc: 0x1020, + fetch_block_data: mem_data(0x20..), + error: None, + }, + op! { + start_pc: 0x100, + fetch_block_data: [0; _], + error: Some(generic_error()), + }, + op! { + start_pc: MEMORY_ERROR_RANGE.start, + fetch_block_data: [0; _], + error: Some(generic_error()), + }, + op! { + start_pc: MEMORY_ERROR_RANGE.start + MEMORY_ERROR_STEP, + fetch_block_data: [0; _], + error: Some(generic_error()), + }, + op! { + start_pc: MEMORY_ERROR_RANGE.start + MEMORY_ERROR_STEP * 2, + fetch_block_data: [0; _], + error: Some(generic_error()), + }, + op! { + start_pc: MEMORY_ERROR_RANGE.start + MEMORY_ERROR_STEP * 3, + fetch_block_data: [0; _], + error: Some(generic_error()), + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1010, + fetch_block_data: mem_data(0x10..), + error: None, + }, + op! { + start_pc: 0x1020, + fetch_block_data: mem_data(0x20..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1010, + fetch_block_data: mem_data(0x10..), + error: None, + }, + op! { + start_pc: 0x1020, + fetch_block_data: mem_data(0x20..), + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + ] +} + +#[test] +#[hdl] +fn test_fetch() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut config = CpuConfig::new( + vec![ + UnitConfig::new(UnitKind::AluBranch), + UnitConfig::new(UnitKind::AluBranch), + ], + NonZeroUsize::new(20).unwrap(), + ); + config.fetch_width = NonZeroUsize::new(2).unwrap(); + config.log2_fetch_width_in_bytes = LOG2_FETCH_WIDTH_IN_BYTES; + config.log2_cache_line_size_in_bytes = LOG2_CACHE_LINE_SIZE_IN_BYTES; + config.log2_l1_i_cache_line_count = 4; + let m = dut(PhantomConst::new_sized(config)); + let mut sim = Simulation::new(m); + let writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + struct DumpVcdOnDrop { + writer: Option, + } + impl Drop for DumpVcdOnDrop { + fn drop(&mut self) { + if let Some(mut writer) = self.writer.take() { + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + } + } + } + let mut writer = DumpVcdOnDrop { + writer: Some(writer), + }; + let from_next_pc_ty = sim.io().from_next_pc.ty(); + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, true); + sim.write( + sim.io().from_next_pc.cancel.data, + from_next_pc_ty.cancel.data.HdlNone(), + ); + sim.write( + sim.io().from_next_pc.fetch.data, + from_next_pc_ty.fetch.data.HdlNone(), + ); + sim.write(sim.io().to_decode.fetched.ready, true); + sim.write( + sim.io().to_decode.next_fetch_block_ids, + HdlSome( + sim.io() + .ty() + .to_decode + .next_fetch_block_ids + .HdlSome + .new_sim(0u8), + ), + ); + let operations = fetch_test_operations(); + let mut started_operations = 0; + let mut finished_operations = 0; + for cycle in 0..150 { + sim.write( + sim.io().from_next_pc.fetch.data, + if let Some(op) = operations.get(started_operations) { + #[hdl(sim)] + HdlSome( + #[hdl(sim)] + NextPcToFetchInterfaceInner { + start_pc: op.start_pc, + fetch_block_id: op.fetch_block_id, + }, + ) + } else { + #[hdl(sim)] + HdlNone() + }, + ); + sim.advance_time(SimDuration::from_nanos(500)); + #[hdl(sim)] + if let HdlSome(next_fetch_block_ids) = sim.read(sim.io().from_next_pc.next_fetch_block_ids) + { + let next_fetch_block_ids = ArrayVec::elements_sim_ref(&next_fetch_block_ids); + let expected_next_fetch_block_ids = Vec::from_iter( + operations + .get(finished_operations..started_operations) + .unwrap_or(&[]) + .iter() + .map(|op| op.fetch_block_id.to_sim_value()), + ); + println!("expected_next_fetch_block_ids={expected_next_fetch_block_ids:?}"); + assert_eq!(next_fetch_block_ids, expected_next_fetch_block_ids); + } + if sim.read_bool(sim.io().from_next_pc.fetch.ready) { + #[hdl(sim)] + if let HdlSome(_) = sim.read(sim.io().from_next_pc.fetch.data) { + println!("started fetch: {:#?}", operations[started_operations]); + started_operations += 1; + } + } else { + println!("not ready to start fetch"); + } + if sim.read_bool(sim.io().to_decode.fetched.ready) { + #[hdl(sim)] + if let HdlSome(fetched) = sim.read(sim.io().to_decode.fetched.data) { + #[hdl(sim)] + let FetchToDecodeInterfaceInner::<_> { + start_pc, + fetch_block_id, + fetch_block_data, + error, + config: _, + } = &fetched; + let Some(expected_op) = operations.get(finished_operations) else { + panic!("too many finished operations: {fetched:#?}"); + }; + let op = FetchTestOperation { + start_pc: start_pc.as_int(), + fetch_block_id: fetch_block_id.as_int(), + error: #[hdl(sim)] + match error { + HdlSome(e) => Some(e.clone()), + HdlNone => None, + }, + fetch_block_data: std::array::from_fn(|i| fetch_block_data[i].as_int()), + }; + println!("finished fetch: op={op:#?}"); + assert_eq!( + op, *expected_op, + "cycle={cycle} finished_operations={finished_operations}", + ); + finished_operations += 1; + } else { + println!("not ready to finish fetch"); + } + } + println!("clock tick: {cycle}"); + sim.write_clock(sim.io().cd.clk, true); + sim.advance_time(SimDuration::from_nanos(500)); + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, false); + } + assert_eq!(finished_operations, operations.len()); + // FIXME: vcd is just whatever fetch does now, which isn't known to be correct + let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("expected/fetch.vcd") { + panic!(); + } +}