From d361a2b578e71574e8ce323828fd5415fb985896 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 23 Jan 2026 12:06:59 -0800
Subject: [PATCH] make LogicalFlagsMOp also copy the dest PRegValue.flags into
 PRegValue.int_fp

---
 crates/cpu/src/instruction.rs | 34 ++++++++++++++++++++++------------
 1 file changed, 22 insertions(+), 12 deletions(-)

diff --git a/crates/cpu/src/instruction.rs b/crates/cpu/src/instruction.rs
index 98d9393..3c7431f 100644
--- a/crates/cpu/src/instruction.rs
+++ b/crates/cpu/src/instruction.rs
@@ -1473,14 +1473,19 @@ impl<DestReg: Type, SrcRegWidth: Size> LogicalFlagsMOp<DestReg, SrcRegWidth> {
         src: impl ToExpr<Type = Array<PRegValue, 3>>,
     ) -> Expr<PRegValue> {
         let this = this.to_expr();
+        let flags = LogicalFlagsMOpImm::flags_operation(
+            Self::imm(this),
+            this.lut,
+            src.to_expr().map(|v| v.flags),
+        );
         #[hdl]
         PRegValue {
-            int_fp: 0u64,
-            flags: LogicalFlagsMOpImm::flags_operation(
-                Self::imm(this),
-                this.lut,
-                src.to_expr().map(|v| v.flags),
-            ),
+            int_fp: PRegFlags::fields(flags)
+                .iter()
+                .as_slice()
+                .cast_to_bits()
+                .cast_to_static::<UInt<64>>(),
+            flags,
         }
     }
     #[hdl]
@@ -1489,14 +1494,19 @@ impl<DestReg: Type, SrcRegWidth: Size> LogicalFlagsMOp<DestReg, SrcRegWidth> {
         src: impl ToSimValue<Type = Array<PRegValue, 3>>,
     ) -> SimValue<PRegValue> {
         let this = this.into_sim_value();
+        let flags = LogicalFlagsMOpImm::flags_operation_sim(
+            Self::imm(&this),
+            SimValue::into_value(this).lut,
+            SimValue::into_value(src.into_sim_value()).map(|v| SimValue::into_value(v).flags),
+        );
         #[hdl(sim)]
         PRegValue {
-            int_fp: 0u64,
-            flags: LogicalFlagsMOpImm::flags_operation_sim(
-                Self::imm(&this),
-                SimValue::into_value(this).lut,
-                SimValue::into_value(src.into_sim_value()).map(|v| SimValue::into_value(v).flags),
-            ),
+            int_fp: PRegFlags::fields_sim_ref(&flags)
+                .iter()
+                .as_slice()
+                .cast_to_bits()
+                .cast_to_static::<UInt<64>>(),
+            flags,
         }
     }
     #[hdl]