From c9a3de19b7ff58588fcd15f04e48cf618aae350c Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Sun, 18 Jan 2026 22:44:30 -0800 Subject: [PATCH] add test that UnitMOp has all the register fields aligned across the different variants --- crates/cpu/src/instruction.rs | 330 ++++++++++- crates/cpu/src/unit.rs | 16 +- crates/cpu/tests/expected/decode_one_insn.vcd | 524 ++++++++---------- 3 files changed, 569 insertions(+), 301 deletions(-) diff --git a/crates/cpu/src/instruction.rs b/crates/cpu/src/instruction.rs index 7f878c5..8cabaea 100644 --- a/crates/cpu/src/instruction.rs +++ b/crates/cpu/src/instruction.rs @@ -8,11 +8,18 @@ use fayalite::{ prelude::*, ty::StaticType, }; -use std::{borrow::Cow, fmt, marker::PhantomData, ops::Range}; +use std::{ + borrow::Cow, + fmt, + marker::PhantomData, + ops::{ControlFlow, Range}, +}; pub mod power_isa; -pub trait MOpInto: MOpTrait { +pub trait MOpInto: + MOpTrait +{ fn mop_into_ty(self) -> Target; fn mop_into(this: Expr) -> Expr; } @@ -26,6 +33,52 @@ impl MOpInto for T { } } +pub trait MOpVariantVisitOps { + type MOp: MOpTrait< + DestReg = ::DestReg, + SrcRegWidth = ::SrcRegWidth, + >; + type Target: MOpTrait; + fn mop_ty(&self) -> &Self::MOp; + fn target_ty(&self) -> &Self::Target; + fn path() -> Vec<&'static str>; + fn mop_into_target(&self, mop: Expr) -> Expr; +} + +impl MOpVariantVisitOps for T { + type MOp = T; + type Target = T; + fn mop_ty(&self) -> &Self::MOp { + self + } + fn target_ty(&self) -> &Self::Target { + self + } + fn path() -> Vec<&'static str> { + Vec::new() + } + fn mop_into_target(&self, mop: Expr) -> Expr { + assert_eq!(*self, mop.ty()); + mop + } +} + +pub trait MOpVariantVisitor { + type Break; + fn visit_variant>( + &mut self, + visit_ops: &VisitOps, + ) -> ControlFlow; +} + +pub trait MOpVisitVariants: MOpTrait { + fn visit_variants(visitor: &mut V, visit_ops: &VisitOps) -> ControlFlow + where + V: ?Sized + MOpVariantVisitor, + VisitOps: ?Sized + MOpVariantVisitOps, + VisitOps::Target: MOpTrait; +} + pub trait MOpTrait: Type { type Mapped: MOpTrait; type DestReg: Type; @@ -161,6 +214,17 @@ impl MOpTrait for T { } } +impl MOpVisitVariants for T { + fn visit_variants(visitor: &mut V, visit_ops: &VisitOps) -> ControlFlow + where + V: ?Sized + MOpVariantVisitor, + VisitOps: ?Sized + MOpVariantVisitOps, + VisitOps::Target: MOpTrait, + { + visitor.visit_variant(visit_ops) + } +} + #[hdl] pub enum OutputIntegerMode { Full64, @@ -456,6 +520,7 @@ macro_rules! mop_enum { $SrcRegWidth:ident: Size $(, #[MOp(get_ty = $mop_types_get_ty:expr)] $MOpTypes:ident: Type)* $(, #[Size(get_size = $sizes_get_size:expr)] $Sizes:ident: Size)* + $(, #[MOpVisitVariants] [$($visit_variants_bounds:tt)*])? > { $(#[$($first_variant_meta:tt)*])* $FirstVariant:ident($first_ty:ty), @@ -489,6 +554,30 @@ macro_rules! mop_enum { } } + mop_enum! { + @impl_visit_variants [ + enum $MOp< + $DestReg: Type, + $SrcRegWidth: Size + $(, #[MOp] $MOpTypes: Type)* + $(, #[Size(get_size = $sizes_get_size)] $Sizes: Size)* + $(, #[MOpVisitVariants] [$($visit_variants_bounds)*])? + > + ] + enum $MOp< + $DestReg: Type, + $SrcRegWidth: Size + $(, #[MOp] $MOpTypes: Type)* + $(, #[Size] $Sizes: Size)* + $(, #[MOpVisitVariants] [$($visit_variants_bounds)*])? + > { + $FirstVariant($first_ty), + $( + $Variant($ty), + )* + } + } + impl< $DestReg: Type, $SrcRegWidth: Size, @@ -568,6 +657,109 @@ macro_rules! mop_enum { } } }; + ( + @impl_visit_variants $visit_variant_args:tt + enum $MOp:ident< + $DestReg:ident: Type, + $SrcRegWidth:ident: Size + $(, #[MOp] $MOpTypes:ident: Type)* + $(, #[Size] $Sizes:ident: Size)* + $(, #[MOpVisitVariants] [$($visit_variants_bounds:tt)*])? + > { + $( + $Variant:ident($ty:ty), + )* + } + ) => { + const _: () = { + mod variant_visit_ops { + $( + #[derive(Copy, Clone)] + pub(super) struct $Variant(pub(super) VisitOps); + )* + } + + $(mop_enum! { + @impl_visit_variant $visit_variant_args + #[variant_ty = $ty] + struct variant_visit_ops::$Variant<_>(_); + })* + + impl< + $DestReg: Type, + $SrcRegWidth: Size, + $($MOpTypes: Type + MOpTrait,)* + $($Sizes: Size,)* + > MOpVisitVariants for $MOp< + $DestReg, + $SrcRegWidth, + $($MOpTypes,)* + $($Sizes,)* + > + where + $($($visit_variants_bounds)*)? + { + fn visit_variants(visitor: &mut V, visit_ops: &VisitOps) -> ControlFlow + where + V: ?Sized + MOpVariantVisitor, + VisitOps: ?Sized + MOpVariantVisitOps, + VisitOps::Target: MOpTrait, + { + $(MOpVisitVariants::visit_variants(visitor, &variant_visit_ops::$Variant(visit_ops))?;)* + std::ops::ControlFlow::Continue(()) + } + } + }; + }; + ( + @impl_visit_variant [ + enum $MOp:ident< + $DestReg:ident: Type, + $SrcRegWidth:ident: Size + $(, #[MOp] $MOpTypes:ident: Type)* + $(, #[Size(get_size = $sizes_get_size:expr)] $Sizes:ident: Size)* + $(, #[MOpVisitVariants] [$($visit_variants_bounds:tt)*])? + > + ] + #[variant_ty = $ty:ty] + struct $variant_visit_ops:ident::$Variant:ident<_>(_); + ) => { + impl< + $DestReg: Type, + $SrcRegWidth: Size, + $($MOpTypes: Type + MOpTrait,)* + $($Sizes: Size,)* + VisitOps, + > MOpVariantVisitOps for $variant_visit_ops::$Variant<&'_ VisitOps> + where + VisitOps: ?Sized + MOpVariantVisitOps>, + VisitOps::Target: MOpTrait, + { + type MOp = $ty; + type Target = VisitOps::Target; + fn mop_ty(&self) -> &Self::MOp { + &self.0.mop_ty().$Variant + } + fn target_ty(&self) -> &Self::Target { + self.0.target_ty() + } + fn path() -> Vec<&'static str> { + let mut retval = VisitOps::path(); + retval.push(stringify!($Variant)); + retval + } + fn mop_into_target(&self, mop: Expr) -> Expr { + let mop_ty = self.0.mop_ty(); + assert_eq!(mop_ty.$Variant, mop.ty()); + self.0.mop_into_target(mop_ty.$Variant(mop)) + } + } + }; ( @impl_variants #[impl_mop_into = true] @@ -595,9 +787,10 @@ macro_rules! mop_enum { $Variant:ident($ty:ty), } ) => { - impl<$DestReg: Type, $SrcRegWidth: Size, Target: MOpTrait, $($Sizes: Size,)*> MOpInto for $ty + impl<$DestReg: Type, $SrcRegWidth: Size, Target, $($Sizes: Size,)*> MOpInto for $ty where - $MOp<$DestReg, $SrcRegWidth, $($Sizes,)*>: MOpInto + $MOp<$DestReg, $SrcRegWidth, $($Sizes,)*>: MOpInto, + Target: MOpTrait, { fn mop_into_ty(self) -> Target { MOpInto::mop_into_ty($MOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)]$([$sizes_get_size(self)])*) @@ -989,8 +1182,8 @@ mop_enum! { #[impl_mop_into = true] #[hdl] pub enum LoadStoreMOp { - Load(CommonMOp, DestReg, SrcRegWidth, ConstUsize<0>>), - Store(CommonMOp, DestReg, SrcRegWidth, ConstUsize<1>>), + Load(CommonMOp, DestReg, SrcRegWidth, ConstUsize<0>>), + Store(CommonMOp, DestReg, SrcRegWidth, ConstUsize<1>>), } } @@ -999,14 +1192,14 @@ common_mop_struct! { #[hdl(cmp_eq)] pub struct MoveRegMOp { #[common] - pub common: CommonMOp, DestReg, SrcRegWidth, ConstUsize<1>>, + pub common: CommonMOp, DestReg, SrcRegWidth, ConstUsize<1>>, } } -impl MOpInto - for MoveRegMOp +impl MOpInto for MoveRegMOp where UnitMOp: MOpInto, + Target: MOpTrait, { fn mop_into_ty(self) -> Target { MOpInto::mop_into_ty( @@ -1034,7 +1227,12 @@ impl MoveRegMOp { MOpInto::mop_into( #[hdl] MoveRegMOp { - common: CommonMOp::new(0_hdl_u2, dest, src, Expr::as_dyn_int(imm.to_expr())), + common: CommonMOp::new( + 0.cast_to_static::>(), + dest, + src, + Expr::as_dyn_int(imm.to_expr()), + ), }, ) } @@ -1406,3 +1604,115 @@ pub type MOp = UnitMOp< #[hdl] pub type RenamedMOp = UnitMOp>; + +#[cfg(test)] +mod tests { + use super::*; + use std::{convert::Infallible, fmt::Write, usize}; + + #[test] + fn ensure_reg_fields_are_in_the_same_place() { + struct Visitor { + dest_reg_offset: Option<(usize, String)>, + max_dest_reg_offset: usize, + min_prefix_pad: usize, + errors: Option, + } + impl MOpVariantVisitor for Visitor { + type Break = Infallible; + fn visit_variant< + VisitOps: ?Sized + MOpVariantVisitOps, + >( + &mut self, + visit_ops: &VisitOps, + ) -> ControlFlow { + self.min_prefix_pad = self + .min_prefix_pad + .min(::PrefixPad::VALUE); + let variant = visit_ops.mop_ty(); + let zeroed_variant = UInt[variant.canonical().bit_width()] + .zero() + .cast_bits_to(*variant); + let mut common_mop = CommonMOpTrait::common_mop(&zeroed_variant).into_sim_value(); + SimValue::bits_mut(&mut common_mop.dest) + .bits_mut() + .fill(false); + let with_zeros = visit_ops + .mop_into_target(Expr::from_canonical(Expr::canonical( + CommonMOpTrait::with_common_mop(&zeroed_variant, &common_mop), + ))) + .into_sim_value(); + SimValue::bits_mut(&mut common_mop.dest) + .bits_mut() + .fill(true); + let with_ones = visit_ops + .mop_into_target(Expr::from_canonical(Expr::canonical( + CommonMOpTrait::with_common_mop(&zeroed_variant, &common_mop), + ))) + .into_sim_value(); + let mut dest_reg_offset = None; + for (i, (a, b)) in SimValue::bits(&with_zeros) + .bits() + .iter() + .by_vals() + .zip(SimValue::bits(&with_ones).bits().iter().by_vals()) + .enumerate() + { + if a != b { + dest_reg_offset = Some(i); + break; + } + } + let Some(dest_reg_offset) = dest_reg_offset else { + panic!("no dest reg offset: {variant:#?}"); + }; + self.max_dest_reg_offset = self.max_dest_reg_offset.max(dest_reg_offset); + if let Some((first_dest_reg_offset, _)) = self.dest_reg_offset { + if first_dest_reg_offset != dest_reg_offset { + writeln!( + self.errors.get_or_insert_default(), + "dest_reg_offset {dest_reg_offset} doesn't match first \ + variant's dest_reg_offset {first_dest_reg_offset}\n\ + variant's path: {:?}\n\ + variant: {variant:#?}\n", + VisitOps::path(), + ) + .unwrap(); + } + } else { + self.dest_reg_offset = Some(( + dest_reg_offset, + format!( + "first variant's path: {:?}\nfirst variant: {variant:#?}", + VisitOps::path() + ), + )); + } + ControlFlow::Continue(()) + } + } + let mut visitor = Visitor { + dest_reg_offset: None, + max_dest_reg_offset: 0, + min_prefix_pad: usize::MAX, + errors: None, + }; + let ControlFlow::Continue(()) = MOp::visit_variants(&mut visitor, &MOp); + let Visitor { + dest_reg_offset: Some((_, first_variant)), + max_dest_reg_offset, + min_prefix_pad, + errors, + } = visitor + else { + panic!("no variants"); + }; + println!("max_dest_reg_offset: {max_dest_reg_offset}"); + println!("min_prefix_pad: {min_prefix_pad}"); + println!("{first_variant}"); + if let Some(errors) = errors { + panic!("{errors}"); + } + assert_eq!(min_prefix_pad, 0); + } +} diff --git a/crates/cpu/src/unit.rs b/crates/cpu/src/unit.rs index 8db75c2..400358c 100644 --- a/crates/cpu/src/unit.rs +++ b/crates/cpu/src/unit.rs @@ -4,8 +4,9 @@ use crate::{ config::CpuConfig, instruction::{ - AluBranchMOp, LoadStoreMOp, MOp, MOpDestReg, MOpInto, MOpRegNum, MOpTrait, RenamedMOp, - UnitOutRegNum, mop_enum, + AluBranchMOp, LoadStoreMOp, MOp, MOpDestReg, MOpInto, MOpRegNum, MOpTrait, + MOpVariantVisitOps, MOpVariantVisitor, MOpVisitVariants, RenamedMOp, UnitOutRegNum, + mop_enum, }, register::{FlagsMode, PRegValue}, unit::unit_base::UnitToRegAlloc, @@ -16,6 +17,7 @@ use fayalite::{ prelude::*, }; use serde::{Deserialize, Serialize}; +use std::ops::ControlFlow; pub mod alu_branch; pub mod unit_base; @@ -83,7 +85,15 @@ macro_rules! all_units { #[impl_mop_into = false] #[hdl] $(#[$enum_meta])* - $vis enum $UnitMOpEnum<$DestReg: Type, $SrcRegWidth: Size, #[MOp(get_ty = $transformed_move_op_get_ty)] $TransformedMoveOp: Type> { + $vis enum $UnitMOpEnum< + $DestReg: Type, + $SrcRegWidth: Size, + #[MOp(get_ty = $transformed_move_op_get_ty)] $TransformedMoveOp: Type, + #[MOpVisitVariants] [ + $TransformedMoveOp: MOpVisitVariants, + $($Op: MOpVisitVariants,)* + ] + > { $( $(#[$variant_meta])* $Unit($Op), diff --git a/crates/cpu/tests/expected/decode_one_insn.vcd b/crates/cpu/tests/expected/decode_one_insn.vcd index 8778398..dfc609f 100644 --- a/crates/cpu/tests/expected/decode_one_insn.vcd +++ b/crates/cpu/tests/expected/decode_one_insn.vcd @@ -255,7 +255,7 @@ $upscope $end $upscope $end $scope struct TransformedMove $end $scope struct common $end -$var wire 2 q prefix_pad $end +$var wire 3 q prefix_pad $end $scope struct dest $end $scope struct normal_regs $end $scope struct \[0] $end @@ -292,7 +292,7 @@ $upscope $end $scope struct LoadStore $end $var string 1 { \$tag $end $scope struct Load $end -$var wire 1 | prefix_pad $end +$var wire 2 | prefix_pad $end $scope struct dest $end $scope struct normal_regs $end $scope struct \[0] $end @@ -326,7 +326,7 @@ $scope struct _phantom $end $upscope $end $upscope $end $scope struct Store $end -$var wire 1 (" prefix_pad $end +$var wire 2 (" prefix_pad $end $scope struct dest $end $scope struct normal_regs $end $scope struct \[0] $end @@ -614,7 +614,7 @@ $upscope $end $upscope $end $scope struct TransformedMove $end $scope struct common $end -$var wire 2 $# prefix_pad $end +$var wire 3 $# prefix_pad $end $scope struct dest $end $scope struct normal_regs $end $scope struct \[0] $end @@ -651,7 +651,7 @@ $upscope $end $scope struct LoadStore $end $var string 1 .# \$tag $end $scope struct Load $end -$var wire 1 /# prefix_pad $end +$var wire 2 /# prefix_pad $end $scope struct dest $end $scope struct normal_regs $end $scope struct \[0] $end @@ -685,7 +685,7 @@ $scope struct _phantom $end $upscope $end $upscope $end $scope struct Store $end -$var wire 1 9# prefix_pad $end +$var wire 2 9# prefix_pad $end $scope struct dest $end $scope struct normal_regs $end $scope struct \[0] $end @@ -1639,35 +1639,35 @@ b1001000110100 m sFull64\x20(0) o sU64\x20(0) p b1 q -b1000110 r +b100011 r b0 s sHdlNone\x20(0) t sHdlNone\x20(0) u -b1001000 v +b100100 v b0 w b0 x -b10010001101000 y +b1001000110100 y 0z sStore\x20(1) { -0| -b1000110 } +b0 | +b100011 } b0 ~ sHdlNone\x20(0) !" sHdlNone\x20(0) "" -b1001000 #" +b100100 #" b0 $" b0 %" -b10010001101000 &" +b1001000110100 &" 0'" -0(" -b1000110 )" +b0 (" +b100011 )" b0 *" sHdlNone\x20(0) +" sHdlNone\x20(0) ," -b1001000 -" +b100100 -" b0 ." b0 /" -b10010001101000 0" +b1001000110100 0" 01" sAluBranch\x20(0) 2" sAddSub\x20(0) 3" @@ -1760,7 +1760,7 @@ b0 +# b0 ,# 0-# sLoad\x20(0) .# -0/# +b0 /# b0 0# b0 1# sHdlNone\x20(0) 2# @@ -1770,7 +1770,7 @@ b0 5# b0 6# b0 7# 08# -09# +b0 9# b0 :# b0 ;# sHdlNone\x20(0) <# @@ -2153,15 +2153,12 @@ b10010001 ` b1010001010110011110001001 a b10010001 l b1010001010110011110001001 m -b100010 x -b100010101100111100010011 y -1z -b100010 %" -b100010101100111100010011 &" -1'" -b100010 /" -b100010101100111100010011 0" -11" +b10010001 x +b1010001010110011110001001 y +b10010001 %" +b1010001010110011110001001 &" +b10010001 /" +b1010001010110011110001001 0" b110000000010010001101000101 F# sHdlSome\x20(1) G# b111000011001000110011110001001 H# @@ -2530,18 +2527,15 @@ b100100 j b1001 l b1101000000000000000000 m sU64\x20(0) p -b1001000 v -b10010 x -b11010000000000000000000 y -0z -b1001000 #" -b10010 %" -b11010000000000000000000 &" -0'" -b1001000 -" -b10010 /" -b11010000000000000000000 0" -01" +b100100 v +b1001 x +b1101000000000000000000 y +b100100 #" +b1001 %" +b1101000000000000000000 &" +b100100 -" +b1001 /" +b1101000000000000000000 0" b111100011001000001001000110100 F# sHdlNone\x20(0) G# b0 H# @@ -2803,11 +2797,11 @@ b0 j b1101000000000000000100 m sCmpRBOne\x20(8) p b0 v -b11010000000000000001000 y +b1101000000000000000100 y b0 #" -b11010000000000000001000 &" +b1101000000000000000100 &" b0 -" -b11010000000000000001000 0" +b1101000000000000000100 0" b1001100011110100001001000000100 F# b1001000000100 J# b11010 K# @@ -2943,17 +2937,20 @@ b0 l b0 m sU64\x20(0) p b0 q -b1001001 v -b1001010 w +sHdlSome\x20(1) u +b100100 v +b100101 w b0 x b0 y sLoad\x20(0) { -b1001001 #" -b1001010 $" +sHdlSome\x20(1) "" +b100100 #" +b100101 $" b0 %" b0 &" -b1001001 -" -b1001010 ." +sHdlSome\x20(1) ," +b100100 -" +b100101 ." b0 /" b0 0" b1111100011001000010101000010101 F# @@ -3119,16 +3116,16 @@ b100 g b0 k b1001000110100 m b1 q -b1000 s +b100 s b0 w -b10010001101000 y +b1001000110100 y sStore\x20(1) { -b1000 ~ +b100 ~ b0 $" -b10010001101000 &" -b1000 *" +b1001000110100 &" +b100 *" b0 ." -b10010001101000 0" +b1001000110100 0" b110100011001000001001000110100 F# b1001000110100 J# b1001000110100 N# @@ -3220,14 +3217,14 @@ b0 m sS16\x20(5) p b0 q b0 s -b1001010 w +b100101 w b0 y sLoad\x20(0) { b0 ~ -b1001010 $" +b100101 $" b0 &" b0 *" -b1001010 ." +b100101 ." b0 0" b1111100011001000010100001010001 F# b10100001010001 J# @@ -3317,19 +3314,19 @@ sHdlNone\x20(0) i b0 k b1001000110100 m b1 q -b1000 s -b1001000 v +b100 s +sHdlNone\x20(0) u b0 w -b10010001101000 y +b1001000110100 y sStore\x20(1) { -b1000 ~ -b1001000 #" +b100 ~ +sHdlNone\x20(0) "" b0 $" -b10010001101000 &" -b1000 *" -b1001000 -" +b1001000110100 &" +b100 *" +sHdlNone\x20(0) ," b0 ." -b10010001101000 0" +b1001000110100 0" b100000011001000001001000110100 F# b1001000110100 J# b1001000110100 N# @@ -3420,15 +3417,15 @@ b100101 k b0 m sU64\x20(0) p b0 q -b1001001 v -b1001010 w +sHdlSome\x20(1) u +b100101 w b0 y sLoad\x20(0) { -b1001001 #" -b1001010 $" +sHdlSome\x20(1) "" +b100101 $" b0 &" -b1001001 -" -b1001010 ." +sHdlSome\x20(1) ," +b100101 ." b0 0" b1111100011001000010100000010101 F# b10100000010101 J# @@ -3538,12 +3535,12 @@ sU32\x20(2) d b100 k b100101 l sU32\x20(2) p -b1000 w -b1001010 x -b1000 $" -b1001010 %" -b1000 ." -b1001010 /" +b100 w +b100101 x +b100 $" +b100101 %" +b100 ." +b100101 /" b1111100011001000010100100010101 F# b10100100010101 J# b10100100010101 N# @@ -3608,13 +3605,13 @@ b1111111111111111111111111 m 1n sU32\x20(2) p b0 x -b1111111111111111111111110 y +b1111111111111111111111111 y 1z b0 %" -b1111111111111111111111110 &" +b1111111111111111111111111 &" 1'" b0 /" -b1111111111111111111111110 0" +b1111111111111111111111111 0" 11" b1111100011001000000000111010101 F# b111010101 J# @@ -3832,17 +3829,19 @@ b1011 f sHdlNone\x20(0) i b1001000110100 m sS32\x20(3) p -b1 q -b10111 r -b1001000 v -b10010001101000 y +b101 q +b1011 r +sHdlNone\x20(0) u +b1001000110100 y sStore\x20(1) { -b10111 } -b1001000 #" -b10010001101000 &" -b10111 )" -b1001000 -" -b10010001101000 0" +b10 | +b1011 } +sHdlNone\x20(0) "" +b1001000110100 &" +b10 (" +b1011 )" +sHdlNone\x20(0) ," +b1001000110100 0" b101101100001000001001000110100 F# b1001000110100 J# b1100 L# @@ -4023,14 +4022,14 @@ b11111111 l b1111111111000100110101011 m 1n sS64\x20(1) p -b11111110 x -b1111111110001001101010111 y +b11111111 x +b1111111111000100110101011 y 1z -b11111110 %" -b1111111110001001101010111 &" +b11111111 %" +b1111111111000100110101011 &" 1'" -b11111110 /" -b1111111110001001101010111 0" +b11111111 /" +b1111111111000100110101011 0" 11" b101101101001001000100110101011 F# b1000100110101011 J# @@ -4207,17 +4206,17 @@ b0 l b0 m 0n sS32\x20(3) p -b0 q -b1001010 w +b100 q +b100101 w b0 x b0 y 0z sLoad\x20(0) { -b1001010 $" +b100101 $" b0 %" b0 &" 0'" -b1001010 ." +b100101 ." b0 /" b0 0" 01" @@ -4476,14 +4475,14 @@ sU32\x20(2) d b0 k b1001000110100 m sU32\x20(2) p -b1 q +b101 q b0 w -b10010001101000 y +b1001000110100 y sStore\x20(1) { b0 $" -b10010001101000 &" +b1001000110100 &" b0 ." -b10010001101000 0" +b1001000110100 0" b101001100001000001001000110100 F# b1001000110100 J# b1100 L# @@ -4639,9 +4638,9 @@ b1000100110101011 a sU64\x20(0) d b1000100110101011 m sU64\x20(0) p -b10001001101010110 y -b10001001101010110 &" -b10001001101010110 0" +b1000100110101011 y +b1000100110101011 &" +b1000100110101011 0" b101001101001001000100110101011 F# b1000100110101011 J# b1101 L# @@ -4805,13 +4804,13 @@ sU32\x20(2) d b100101 k b0 m sU32\x20(2) p -b0 q -b1001010 w +b100 q +b100101 w b0 y sLoad\x20(0) { -b1001010 $" +b100101 $" b0 &" -b1001010 ." +b100101 ." b0 0" b1111101100001000010100001000000 F# b10100001000000 J# @@ -5381,21 +5380,21 @@ b0 k b1000100110101011 m sCmpRBOne\x20(8) p b11 q -b1000110 r -b1001001 v +b100011 r +sHdlSome\x20(1) u b0 w -b10001001101010110 y +b1000100110101011 y sStore\x20(1) { -1| -b1000110 } -b1001001 #" +b1 | +b100011 } +sHdlSome\x20(1) "" b0 $" -b10001001101010110 &" -1(" -b1000110 )" -b1001001 -" +b1000100110101011 &" +b1 (" +b100011 )" +sHdlSome\x20(1) ," b0 ." -b10001001101010110 0" +b1000100110101011 0" b1110000100000111000100110101011 F# b1000100110101011 J# b11 K# @@ -5634,15 +5633,12 @@ b1000100 ` b1101010110000000000000000 a b1000100 l b1101010110000000000000000 m -b10001000 x -b1010101100000000000000000 y -1z -b10001000 %" -b1010101100000000000000000 &" -1'" -b10001000 /" -b1010101100000000000000000 0" -11" +b1000100 x +b1101010110000000000000000 y +b1000100 %" +b1101010110000000000000000 &" +b1000100 /" +b1101010110000000000000000 0" b1110100100000111000100110101011 F# #31000000 sHdlNone\x20(0) ' @@ -5671,18 +5667,15 @@ sHdlNone\x20(0) i b0 l b1000100110101011 m s\x20(14) p -b1001000 v +sHdlNone\x20(0) u b0 x -b10001001101010110 y -0z -b1001000 #" +b1000100110101011 y +sHdlNone\x20(0) "" b0 %" -b10001001101010110 &" -0'" -b1001000 -" +b1000100110101011 &" +sHdlNone\x20(0) ," b0 /" -b10001001101010110 0" -01" +b1000100110101011 0" b1100000100000111000100110101011 F# #32000000 b100000 $ @@ -5703,14 +5696,14 @@ b0 a b100000 f b100000 j b0 m -b1000000 r -b1000000 v +b100000 r +b100000 v b0 y -b1000000 } -b1000000 #" +b100000 } +b100000 #" b0 &" -b1000000 )" -b1000000 -" +b100000 )" +b100000 -" b0 0" b0 C# b1100000000000000000000000000000 F# @@ -5963,21 +5956,18 @@ b100011 f b100100 j b1000100 l b1101010110000000000000000 m -b1000110 r -b1001000 v -b10001000 x -b1010101100000000000000000 y -1z -b1000110 } -b1001000 #" -b10001000 %" -b1010101100000000000000000 &" -1'" -b1000110 )" -b1001000 -" -b10001000 /" -b1010101100000000000000000 0" -11" +b100011 r +b100100 v +b1000100 x +b1101010110000000000000000 y +b100011 } +b100100 #" +b1000100 %" +b1101010110000000000000000 &" +b100011 )" +b100100 -" +b1000100 /" +b1101010110000000000000000 0" b1 C# b1100100100000111000100110101011 F# b1000100110101011 J# @@ -6224,14 +6214,11 @@ b0 l b1000100110101011 m sU8\x20(6) p b0 x -b10001001101010110 y -0z +b1000100110101011 y b0 %" -b10001001101010110 &" -0'" +b1000100110101011 &" b0 /" -b10001001101010110 0" -01" +b1000100110101011 0" b1101000100000111000100110101011 F# #35000000 b100000 $ @@ -6252,14 +6239,14 @@ b0 a b100000 f b100000 j b0 m -b1000000 r -b1000000 v +b100000 r +b100000 v b0 y -b1000000 } -b1000000 #" +b100000 } +b100000 #" b0 &" -b1000000 )" -b1000000 -" +b100000 )" +b100000 -" b0 0" b1101000000000000000000000000000 F# b0 J# @@ -6511,21 +6498,18 @@ b100011 f b100100 j b1000100 l b1101010110000000000000000 m -b1000110 r -b1001000 v -b10001000 x -b1010101100000000000000000 y -1z -b1000110 } -b1001000 #" -b10001000 %" -b1010101100000000000000000 &" -1'" -b1000110 )" -b1001000 -" -b10001000 /" -b1010101100000000000000000 0" -11" +b100011 r +b100100 v +b1000100 x +b1101010110000000000000000 y +b100011 } +b100100 #" +b1000100 %" +b1101010110000000000000000 &" +b100011 )" +b100100 -" +b1000100 /" +b1101010110000000000000000 0" b1101100100000111000100110101011 F# b1000100110101011 J# b11 K# @@ -6782,19 +6766,16 @@ b0 l b0 m sCmpRBOne\x20(8) p b10 q -b1001010 w +b100101 w b0 x b0 y -0z sLoad\x20(0) { -b1001010 $" +b100101 $" b0 %" b0 &" -0'" -b1001010 ." +b100101 ." b0 /" b0 0" -01" b1111100100000110010100000111000 F# b10100000111000 J# b110010100000111000 N# @@ -6863,9 +6844,9 @@ sHdlSome\x20(1) E sHdlSome\x20(1) Q sHdlSome\x20(1) ] sHdlSome\x20(1) i -b1001001 v -b1001001 #" -b1001001 -" +sHdlSome\x20(1) u +sHdlSome\x20(1) "" +sHdlSome\x20(1) ," b1111100100000110010100000111001 F# b10100000111001 J# b110010100000111001 N# @@ -6899,9 +6880,9 @@ sHdlNone\x20(0) ] sU8\x20(6) d sHdlNone\x20(0) i sU8\x20(6) p -b1001000 v -b1001000 #" -b1001000 -" +sHdlNone\x20(0) u +sHdlNone\x20(0) "" +sHdlNone\x20(0) ," b1111100100000110010101001111000 F# b10101001111000 J# b110010101001111000 N# @@ -6926,9 +6907,9 @@ sHdlSome\x20(1) E sHdlSome\x20(1) Q sHdlSome\x20(1) ] sHdlSome\x20(1) i -b1001001 v -b1001001 #" -b1001001 -" +sHdlSome\x20(1) u +sHdlSome\x20(1) "" +sHdlSome\x20(1) ," b1111100100000110010101001111001 F# b10101001111001 J# b110010101001111001 N# @@ -6958,9 +6939,9 @@ sHdlNone\x20(0) ] sS8\x20(7) d sHdlNone\x20(0) i sS8\x20(7) p -b1001000 v -b1001000 #" -b1001000 -" +sHdlNone\x20(0) u +sHdlNone\x20(0) "" +sHdlNone\x20(0) ," b1111100100000110010101110111000 F# b10101110111000 J# b110010101110111000 N# @@ -6985,9 +6966,9 @@ sHdlSome\x20(1) E sHdlSome\x20(1) Q sHdlSome\x20(1) ] sHdlSome\x20(1) i -b1001001 v -b1001001 #" -b1001001 -" +sHdlSome\x20(1) u +sHdlSome\x20(1) "" +sHdlSome\x20(1) ," b1111100100000110010101110111001 F# b10101110111001 J# b110010101110111001 N# @@ -7019,9 +7000,9 @@ sHdlNone\x20(0) ] s\x20(14) d sHdlNone\x20(0) i s\x20(14) p -b1001000 v -b1001000 #" -b1001000 -" +sHdlNone\x20(0) u +sHdlNone\x20(0) "" +sHdlNone\x20(0) ," b1111100100000110010101101111000 F# b10101101111000 J# b110010101101111000 N# @@ -7041,46 +7022,28 @@ b10101101111000 H& b10101101111000 L& #44000000 sTransformedMove\x20(1) ! -sCompare\x20(4) " -b10001 $ -b10010 ( +sAddSub\x20(0) " b0 ) 0/ 00 01 -b10001 3 -b10010 7 b0 8 0> 0? 0@ -b10001 B -b10010 F b0 G b0 L -b10001 N -b10010 R b0 S b0 X -b10001 Z -b10010 ^ b0 _ sU64\x20(0) d -b10001 f -b10010 j b0 k sU64\x20(0) p b0 q -b100011 r -b100100 v b0 w -0| -b100011 } -b100100 #" +b0 | b0 $" -0(" -b100011 )" -b100100 -" +b0 (" b0 ." b1111100100000110010001101111000 F# b10001101111000 J# @@ -7145,52 +7108,37 @@ b100 .' #45000000 sAluBranch\x20(0) ! sLogical\x20(2) " -b100011 $ sHdlSome\x20(1) ' -b100100 ( b100101 ) 1/ 10 11 -b100011 3 sHdlSome\x20(1) 6 -b100100 7 b100101 8 1> 1? 1@ -b100011 B sHdlSome\x20(1) E -b100100 F b100101 G b1110 L -b100011 N sHdlSome\x20(1) Q -b100100 R b100101 S b1110 X -b100011 Z sHdlSome\x20(1) ] -b100100 ^ b100101 _ s\x20(14) d -b100011 f sHdlSome\x20(1) i -b100100 j b100101 k s\x20(14) p b10 q -b1000110 r -b1001001 v -b1001010 w -1| -b1000110 } -b1001001 #" -b1001010 $" -1(" -b1000110 )" -b1001001 -" -b1001010 ." +sHdlSome\x20(1) u +b100101 w +b1 | +sHdlSome\x20(1) "" +b100101 $" +b1 (" +sHdlSome\x20(1) ," +b100101 ." b1111100100000110010101101111001 F# b10101101111001 J# b110010101101111001 N# @@ -7259,9 +7207,9 @@ b100100 G b100100 S b100100 _ b100100 k -b1001000 w -b1001000 $" -b1001000 ." +b100100 w +b100100 $" +b100100 ." b1111100100000110010001101111001 F# b10001101111001 J# b110010001101111001 N# @@ -7343,12 +7291,12 @@ s\x20(11) d sHdlNone\x20(0) i b100101 k s\x20(11) p -b1001000 v -b1001010 w -b1001000 #" -b1001010 $" -b1001000 -" -b1001010 ." +sHdlNone\x20(0) u +b100101 w +sHdlNone\x20(0) "" +b100101 $" +sHdlNone\x20(0) ," +b100101 ." b1111100100000110010101100111000 F# b10101100111000 J# b110010101100111000 N# @@ -7417,9 +7365,9 @@ sHdlSome\x20(1) E sHdlSome\x20(1) Q sHdlSome\x20(1) ] sHdlSome\x20(1) i -b1001001 v -b1001001 #" -b1001001 -" +sHdlSome\x20(1) u +sHdlSome\x20(1) "" +sHdlSome\x20(1) ," b1111100100000110010101100111001 F# b10101100111001 J# b110010101100111001 N# @@ -7451,9 +7399,9 @@ sHdlNone\x20(0) ] sS64\x20(1) d sHdlNone\x20(0) i sS64\x20(1) p -b1001000 v -b1001000 #" -b1001000 -" +sHdlNone\x20(0) u +sHdlNone\x20(0) "" +sHdlNone\x20(0) ," b1111100100000110010100011111000 F# b10100011111000 J# b110010100011111000 N# @@ -7478,9 +7426,9 @@ sHdlSome\x20(1) E sHdlSome\x20(1) Q sHdlSome\x20(1) ] sHdlSome\x20(1) i -b1001001 v -b1001001 #" -b1001001 -" +sHdlSome\x20(1) u +sHdlSome\x20(1) "" +sHdlSome\x20(1) ," b1111100100000110010100011111001 F# b10100011111001 J# b110010100011111001 N# @@ -7510,9 +7458,9 @@ sHdlNone\x20(0) ] sCmpRBTwo\x20(9) d sHdlNone\x20(0) i sCmpRBTwo\x20(9) p -b1001000 v -b1001000 #" -b1001000 -" +sHdlNone\x20(0) u +sHdlNone\x20(0) "" +sHdlNone\x20(0) ," b1111100100000110010101000111000 F# b10101000111000 J# b110010101000111000 N# @@ -7537,9 +7485,9 @@ sHdlSome\x20(1) E sHdlSome\x20(1) Q sHdlSome\x20(1) ] sHdlSome\x20(1) i -b1001001 v -b1001001 #" -b1001001 -" +sHdlSome\x20(1) u +sHdlSome\x20(1) "" +sHdlSome\x20(1) ," b1111100100000110010101000111001 F# b10101000111001 J# b110010101000111001 N# @@ -7573,9 +7521,9 @@ sHdlNone\x20(0) ] sU32\x20(2) d sHdlNone\x20(0) i sU32\x20(2) p -b1001000 v -b1001000 #" -b1001000 -" +sHdlNone\x20(0) u +sHdlNone\x20(0) "" +sHdlNone\x20(0) ," b1111100100000110010100001111000 F# b10100001111000 J# b110010100001111000 N# @@ -7600,9 +7548,9 @@ sHdlSome\x20(1) E sHdlSome\x20(1) Q sHdlSome\x20(1) ] sHdlSome\x20(1) i -b1001001 v -b1001001 #" -b1001001 -" +sHdlSome\x20(1) u +sHdlSome\x20(1) "" +sHdlSome\x20(1) ," b1111100100000110010100001111001 F# b10100001111001 J# b110010100001111001 N#