diff --git a/crates/cpu/src/fetch.rs b/crates/cpu/src/fetch.rs
index 52e3585..a87018d 100644
--- a/crates/cpu/src/fetch.rs
+++ b/crates/cpu/src/fetch.rs
@@ -523,7 +523,7 @@ impl<C: PhantomConstCpuConfig> L1ICacheStateSim<C> {
             kind,
             read_data,
             config: _,
-        } = memory_operation_finish;
+        } = memory_operation_finish.into_sim_value();
         #[hdl(sim)]
         match kind {
             MemoryOperationFinishKind::Success(success) =>
@@ -746,7 +746,7 @@ impl<C: PhantomConstCpuConfig> L1ICacheStateSim<C> {
         let NextPcToFetchInterfaceInner {
             start_pc,
             fetch_block_id,
-        } = fetch;
+        } = fetch.into_sim_value();
         let entry_ty = FetchQueueEntry[config];
         self.queue.push_back(
             #[hdl(sim)]
@@ -895,7 +895,7 @@ impl<C: PhantomConstCpuConfig> L1ICacheStateSim<C> {
         let CacheReadData::<_> {
             cache_line_index: read_cache_line_index,
             cache_line,
-        } = cache_read_data;
+        } = cache_read_data.into_sim_value();
         let config = self.config();
         for entry in &mut self.queue {
             #[hdl(sim)]
@@ -1151,8 +1151,6 @@ fn l1_i_cache_impl(config: PhantomConst<CpuConfig>) {
             sim.wait_for_clock_edge(cd.clk).await;
         }
         sim.write(from_next_pc.cancel.ready, true).await;
-        let memory_interface_start_data_ty = memory_interface.start.data.ty();
-        let to_decode_fetched_data_ty = to_decode_fetched.data.ty();
         let cache_read_data_ty = CacheReadData[config];
         let mut state = L1ICacheStateSim::new(state_expr);
         loop {
@@ -1168,26 +1166,11 @@ fn l1_i_cache_impl(config: PhantomConst<CpuConfig>) {
             .await;
             sim.write(
                 memory_interface.start.data,
-                if let Some(v) = state.clone().try_start_memory_operation() {
-                    #[hdl(sim)]
-                    memory_interface_start_data_ty.HdlSome(v)
-                } else {
-                    #[hdl(sim)]
-                    memory_interface_start_data_ty.HdlNone()
-                },
-            )
-            .await;
-            sim.write(
-                to_decode_fetched.data,
-                if let Some(v) = state.clone().to_decode_fetched() {
-                    #[hdl(sim)]
-                    to_decode_fetched_data_ty.HdlSome(v)
-                } else {
-                    #[hdl(sim)]
-                    to_decode_fetched_data_ty.HdlNone()
-                },
+                state.clone().try_start_memory_operation(),
             )
             .await;
+            sim.write(to_decode_fetched.data, state.clone().to_decode_fetched())
+                .await;
             state.write_debug_state(&mut sim).await;
             sim.write(max_cancel_in_fetch, state.queue.len()).await;
             state
diff --git a/crates/cpu/src/instruction.rs b/crates/cpu/src/instruction.rs
index e8f2af1..c6c0082 100644
--- a/crates/cpu/src/instruction.rs
+++ b/crates/cpu/src/instruction.rs
@@ -12,7 +12,7 @@ use fayalite::{
     intern::Interned,
     module::wire_with_loc,
     prelude::*,
-    ty::{StaticType, TypeProperties},
+    ty::{SimValueDebug, StaticType, TypeProperties},
     util::ConstBool,
 };
 use std::{
@@ -381,7 +381,7 @@ impl<T: CommonMOpTrait> MOpVisitVariants for T {
     }
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub enum OutputIntegerMode {
     Full64,
     DupLow32,
@@ -410,40 +410,6 @@ impl OutputIntegerMode {
     }
 }
 
-impl HdlPartialEqImpl<Self> for OutputIntegerMode {
-    #[track_caller]
-    fn cmp_value_eq(
-        lhs: Self,
-        lhs_value: Cow<'_, Self::SimValue>,
-        rhs: Self,
-        rhs_value: Cow<'_, Self::SimValue>,
-    ) -> bool {
-        SimValue::opaque(&SimValue::from_value(lhs, lhs_value.into_owned()))
-            == SimValue::opaque(&SimValue::from_value(rhs, rhs_value.into_owned()))
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_eq(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::opaque(&lhs) == SimValue::opaque(&rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_ne(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::opaque(&lhs) != SimValue::opaque(&rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
-    }
-}
-
 pub const MOP_IMM_WIDTH: usize = 34;
 pub const MOP_MIN_REG_WIDTH: usize = 8;
 pub const COMMON_MOP_SRC_LEN: usize = 3;
@@ -494,6 +460,15 @@ impl<SrcCount: KnownSize> fmt::Debug for CommonMOpDefaultImm<SrcCount> {
     }
 }
 
+impl<SrcCount: KnownSize> SimValueDebug for CommonMOpDefaultImm<SrcCount> {
+    fn sim_value_debug(
+        value: &<Self as Type>::SimValue,
+        f: &mut fmt::Formatter<'_>,
+    ) -> fmt::Result {
+        fmt::Debug::fmt(value, f)
+    }
+}
+
 impl<SrcCount: KnownSize> MOpImmDebug for CommonMOpDefaultImm<SrcCount> {
     fn mop_imm_debug(this: &SimValue<Self>, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         <SIntValue as fmt::Display>::fmt(this, f)
@@ -2254,7 +2229,7 @@ impl<DestReg: Type, SrcRegWidth: Size> LogicalMOp<DestReg, SrcRegWidth, ConstUsi
     }
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub enum ShiftRotateMode {
     /// like `llvm.fsh[lr].i8(src0, src1, shift_rotate_amount.unwrap_or(src2))`
     FunnelShift2x8Bit,
@@ -2274,40 +2249,6 @@ pub enum ShiftRotateMode {
     ShiftSigned64,
 }
 
-impl HdlPartialEqImpl<Self> for ShiftRotateMode {
-    #[track_caller]
-    fn cmp_value_eq(
-        lhs: Self,
-        lhs_value: Cow<'_, Self::SimValue>,
-        rhs: Self,
-        rhs_value: Cow<'_, Self::SimValue>,
-    ) -> bool {
-        SimValue::opaque(&SimValue::from_value(lhs, lhs_value.into_owned()))
-            == SimValue::opaque(&SimValue::from_value(rhs, rhs_value.into_owned()))
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_eq(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::opaque(&lhs) == SimValue::opaque(&rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_ne(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::opaque(&lhs) != SimValue::opaque(&rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
-    }
-}
-
 impl ShiftRotateMode {
     #[hdl]
     fn debug_str(this: &SimValue<Self>) -> &'static str {
@@ -2505,7 +2446,7 @@ impl<DestReg: Type, SrcRegWidth: Size> ShiftRotateMOp<DestReg, SrcRegWidth> {
     }
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub enum CompareMode {
     U64,
     S64,
@@ -2523,40 +2464,6 @@ pub enum CompareMode {
     CmpEqB,
 }
 
-impl HdlPartialEqImpl<Self> for CompareMode {
-    #[track_caller]
-    fn cmp_value_eq(
-        lhs: Self,
-        lhs_value: Cow<'_, Self::SimValue>,
-        rhs: Self,
-        rhs_value: Cow<'_, Self::SimValue>,
-    ) -> bool {
-        SimValue::opaque(&SimValue::from_value(lhs, lhs_value.into_owned()))
-            == SimValue::opaque(&SimValue::from_value(rhs, rhs_value.into_owned()))
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_eq(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::opaque(&lhs) == SimValue::opaque(&rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_ne(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::opaque(&lhs) != SimValue::opaque(&rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
-    }
-}
-
 impl CompareMode {
     #[hdl]
     fn debug_str(this: &SimValue<Self>) -> &'static str {
@@ -2652,7 +2559,7 @@ impl<DestReg: Type, SrcRegWidth: Size> CompareMOp<DestReg, SrcRegWidth, ConstUsi
     }
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub enum ConditionMode {
     Eq,
     ULt,
@@ -2664,40 +2571,6 @@ pub enum ConditionMode {
     Parity,
 }
 
-impl HdlPartialEqImpl<Self> for ConditionMode {
-    #[track_caller]
-    fn cmp_value_eq(
-        lhs: Self,
-        lhs_value: Cow<'_, Self::SimValue>,
-        rhs: Self,
-        rhs_value: Cow<'_, Self::SimValue>,
-    ) -> bool {
-        SimValue::opaque(&SimValue::from_value(lhs, lhs_value.into_owned()))
-            == SimValue::opaque(&SimValue::from_value(rhs, rhs_value.into_owned()))
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_eq(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::opaque(&lhs) == SimValue::opaque(&rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_ne(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::opaque(&lhs) != SimValue::opaque(&rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
-    }
-}
-
 impl ConditionMode {
     #[hdl]
     fn debug_str(this: &SimValue<Self>, inverted: bool) -> &'static str {
@@ -2892,46 +2765,12 @@ impl<DestReg: Type, SrcRegWidth: Size> BranchMOp<DestReg, SrcRegWidth, ConstUsiz
     }
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub enum ReadSpecialMOpImm {
     PowerIsaTimeBase,
     PowerIsaTimeBaseU,
 }
 
-impl HdlPartialEqImpl<Self> for ReadSpecialMOpImm {
-    #[track_caller]
-    fn cmp_value_eq(
-        lhs: Self,
-        lhs_value: Cow<'_, Self::SimValue>,
-        rhs: Self,
-        rhs_value: Cow<'_, Self::SimValue>,
-    ) -> bool {
-        SimValue::opaque(&SimValue::from_value(lhs, lhs_value.into_owned()))
-            == SimValue::opaque(&SimValue::from_value(rhs, rhs_value.into_owned()))
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_eq(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::opaque(&lhs) == SimValue::opaque(&rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_ne(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::opaque(&lhs) != SimValue::opaque(&rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
-    }
-}
-
 impl MOpImmDebug for ReadSpecialMOpImm {
     fn mop_imm_debug(this: &SimValue<Self>, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         f.write_str(Self::debug_str(this))
@@ -3151,7 +2990,7 @@ where
     }
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 pub enum LoadStoreWidth {
     Width8Bit,
     Width16Bit,
@@ -3159,81 +2998,13 @@ pub enum LoadStoreWidth {
     Width64Bit,
 }
 
-impl HdlPartialEqImpl<Self> for LoadStoreWidth {
-    #[track_caller]
-    fn cmp_value_eq(
-        lhs: Self,
-        lhs_value: Cow<'_, Self::SimValue>,
-        rhs: Self,
-        rhs_value: Cow<'_, Self::SimValue>,
-    ) -> bool {
-        SimValue::opaque(&SimValue::from_value(lhs, lhs_value.into_owned()))
-            == SimValue::opaque(&SimValue::from_value(rhs, rhs_value.into_owned()))
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_eq(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::opaque(&lhs) == SimValue::opaque(&rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_ne(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::opaque(&lhs) != SimValue::opaque(&rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
-    }
-}
-
-#[hdl]
+#[hdl(cmp_eq)]
 pub enum LoadStoreConversion {
     ZeroExt,
     SignExt,
     // TODO(FP): add Power ISA's f32 in f64 format and RISC-V's ones-extension of floating-point
 }
 
-impl HdlPartialEqImpl<Self> for LoadStoreConversion {
-    #[track_caller]
-    fn cmp_value_eq(
-        lhs: Self,
-        lhs_value: Cow<'_, Self::SimValue>,
-        rhs: Self,
-        rhs_value: Cow<'_, Self::SimValue>,
-    ) -> bool {
-        SimValue::opaque(&SimValue::from_value(lhs, lhs_value.into_owned()))
-            == SimValue::opaque(&SimValue::from_value(rhs, rhs_value.into_owned()))
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_eq(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::opaque(&lhs) == SimValue::opaque(&rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_ne(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::opaque(&lhs) != SimValue::opaque(&rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
-    }
-}
-
 common_mop_struct! {
     #[mapped(<NewDestReg, NewSrcRegWidth> LoadStoreCommonMOp<NewDestReg, NewSrcRegWidth, SrcCount>)]
     #[hdl(cmp_eq)]
diff --git a/crates/cpu/src/next_pc.rs b/crates/cpu/src/next_pc.rs
index fcc5286..7a0d063 100644
--- a/crates/cpu/src/next_pc.rs
+++ b/crates/cpu/src/next_pc.rs
@@ -23,14 +23,13 @@ use crate::{
     util::array_vec::ArrayVec,
 };
 use fayalite::{
-    expr::HdlPartialEqImpl,
     int::{UIntInRange, UIntInRangeInclusive, UIntInRangeInclusiveType, UIntInRangeType},
     prelude::*,
     sim::value::SimOnlyValueTrait,
     ty::StaticType,
     util::{DebugAsDisplay, ready_valid::ReadyValid},
 };
-use std::{borrow::Cow, fmt};
+use std::fmt;
 
 pub const FETCH_BLOCK_ID_WIDTH: usize = FetchBlockIdInt::BITS as usize;
 type FetchBlockIdInt = u8;
@@ -53,7 +52,7 @@ pub struct NextPcToFetchInterface<C: PhantomConstGet<CpuConfig>> {
     pub config: C,
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 /// WIP version of decoded instruction just good enough to represent stuff needed for [`next_pc()`]
 /// since the actual instruction definition isn't finalized yet.
 /// This will be replaced at a later point.
@@ -93,101 +92,6 @@ impl WipDecodedInsnKind {
     }
 }
 
-// TODO: replace with #[hdl(cmp_eq)] when that's implemented for enums
-impl HdlPartialEqImpl<Self> for WipDecodedInsnKind {
-    #[track_caller]
-    fn cmp_value_eq(
-        lhs: Self,
-        lhs_value: Cow<'_, Self::SimValue>,
-        rhs: Self,
-        rhs_value: Cow<'_, Self::SimValue>,
-    ) -> bool {
-        *Self::cmp_sim_value_eq(
-            Cow::Owned(SimValue::from_value(lhs, lhs_value.into_owned())),
-            Cow::Owned(SimValue::from_value(rhs, rhs_value.into_owned())),
-        )
-    }
-
-    #[hdl]
-    #[track_caller]
-    fn cmp_sim_value_eq(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        let clear_unused_bits = |v: Cow<'_, SimValue<Self>>| {
-            #[hdl(sim)]
-            match &*v {
-                Self::NonBranch =>
-                {
-                    #[hdl(sim)]
-                    Self::NonBranch()
-                }
-                Self::Branch(target) =>
-                {
-                    #[hdl(sim)]
-                    Self::Branch(target)
-                }
-                Self::BranchCond(target) =>
-                {
-                    #[hdl(sim)]
-                    Self::BranchCond(target)
-                }
-                Self::IndirectBranch =>
-                {
-                    #[hdl(sim)]
-                    Self::IndirectBranch()
-                }
-                Self::Call(target) =>
-                {
-                    #[hdl(sim)]
-                    Self::Call(target)
-                }
-                Self::CallCond(target) =>
-                {
-                    #[hdl(sim)]
-                    Self::CallCond(target)
-                }
-                Self::IndirectCall =>
-                {
-                    #[hdl(sim)]
-                    Self::IndirectCall()
-                }
-                Self::Ret =>
-                {
-                    #[hdl(sim)]
-                    Self::Ret()
-                }
-                Self::RetCond =>
-                {
-                    #[hdl(sim)]
-                    Self::RetCond()
-                }
-                Self::Interrupt(target) =>
-                {
-                    #[hdl(sim)]
-                    Self::Interrupt(target)
-                }
-                Self::Unknown => v.into_owned(),
-            }
-        };
-        (SimValue::bits(&clear_unused_bits(lhs)) == SimValue::bits(&clear_unused_bits(rhs)))
-            .to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_ne(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        !Self::cmp_sim_value_eq(lhs, rhs)
-    }
-
-    #[track_caller]
-    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        todo!()
-    }
-}
-
 #[hdl(cmp_eq)]
 /// WIP version of decoded instruction just good enough to represent stuff needed for [`next_pc()`]
 /// since the actual instruction definition isn't finalized yet.
@@ -2781,8 +2685,10 @@ impl<T: SimValueDefault, N: Size> SimValueDefault for ArrayType<T, N> {
 }
 
 impl<T: Type> SimValueDefault for HdlOption<T> {
+    #[hdl]
     fn sim_value_default(self) -> SimValue<Self> {
-        self.HdlNone().to_sim_value_with_type(self)
+        #[hdl(sim)]
+        self.HdlNone()
     }
 }
 
@@ -2911,50 +2817,13 @@ impl ResetSteps for CallStack {
     }
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 enum BTBEntryInsnKind {
     Branch,
     Call,
     Ret,
 }
 
-// TODO: replace with #[hdl(cmp_eq)] when that's implemented for enums
-impl HdlPartialEqImpl<Self> for BTBEntryInsnKind {
-    #[track_caller]
-    fn cmp_value_eq(
-        lhs: Self,
-        lhs_value: Cow<'_, Self::SimValue>,
-        rhs: Self,
-        rhs_value: Cow<'_, Self::SimValue>,
-    ) -> bool {
-        *Self::cmp_sim_value_eq(
-            Cow::Owned(SimValue::from_value(lhs, lhs_value.into_owned())),
-            Cow::Owned(SimValue::from_value(rhs, rhs_value.into_owned())),
-        )
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_eq(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::bits(&*lhs) == SimValue::bits(&*rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_ne(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::bits(&*lhs) != SimValue::bits(&*rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
-    }
-}
-
 impl BTBEntryInsnKind {
     #[hdl]
     fn try_from_decoded_insn_kind(kind: &SimValue<WipDecodedInsnKind>) -> Option<SimValue<Self>> {
@@ -2983,7 +2852,7 @@ impl BTBEntryInsnKind {
     }
 }
 
-#[hdl]
+#[hdl(cmp_eq)]
 enum BTBEntryAddrKind {
     Unconditional,
     Indirect,
@@ -2991,43 +2860,6 @@ enum BTBEntryAddrKind {
     CondNotTaken,
 }
 
-// TODO: replace with #[hdl(cmp_eq)] when that's implemented for enums
-impl HdlPartialEqImpl<Self> for BTBEntryAddrKind {
-    #[track_caller]
-    fn cmp_value_eq(
-        lhs: Self,
-        lhs_value: Cow<'_, Self::SimValue>,
-        rhs: Self,
-        rhs_value: Cow<'_, Self::SimValue>,
-    ) -> bool {
-        *Self::cmp_sim_value_eq(
-            Cow::Owned(SimValue::from_value(lhs, lhs_value.into_owned())),
-            Cow::Owned(SimValue::from_value(rhs, rhs_value.into_owned())),
-        )
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_eq(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::bits(&*lhs) == SimValue::bits(&*rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_sim_value_ne(
-        lhs: Cow<'_, SimValue<Self>>,
-        rhs: Cow<'_, SimValue<Self>>,
-    ) -> SimValue<Bool> {
-        (SimValue::bits(&*lhs) != SimValue::bits(&*rhs)).to_sim_value()
-    }
-
-    #[track_caller]
-    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
-        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
-    }
-}
-
 impl BTBEntryAddrKind {
     #[hdl]
     fn taken(this: &SimValue<Self>) -> bool {
diff --git a/crates/cpu/src/rename_execute_retire.rs b/crates/cpu/src/rename_execute_retire.rs
index 602d113..bc0aefd 100644
--- a/crates/cpu/src/rename_execute_retire.rs
+++ b/crates/cpu/src/rename_execute_retire.rs
@@ -635,20 +635,8 @@ impl<C: PhantomConstCpuConfig> RobEntry<C> {
             mop,
             mop_in_unit_state: SimOnlyValue::new(*mop_in_unit_state),
             is_speculative,
-            finished: if let Some(finished) = finished {
-                #[hdl(sim)]
-                (ret_ty.finished).HdlSome(finished)
-            } else {
-                #[hdl(sim)]
-                (ret_ty.finished).HdlNone()
-            },
-            caused_cancel: if let Some(caused_cancel) = caused_cancel {
-                #[hdl(sim)]
-                (ret_ty.caused_cancel).HdlSome(caused_cancel)
-            } else {
-                #[hdl(sim)]
-                (ret_ty.caused_cancel).HdlNone()
-            },
+            finished: finished.into_sim_value_with_type(ret_ty.finished),
+            caused_cancel: caused_cancel.into_sim_value_with_type(ret_ty.caused_cancel),
         }
     }
 }
@@ -813,13 +801,7 @@ impl<C: PhantomConstCpuConfig> ReorderBuffer<C> {
                     entries.iter().map(RobEntries::debug_state),
                 )
                 .expect("known to fit"),
-            incomplete_back_entry: if let Some(incomplete_back_entry) = incomplete_back_entry {
-                #[hdl(sim)]
-                HdlSome(incomplete_back_entry.debug_state())
-            } else {
-                #[hdl(sim)]
-                HdlNone()
-            },
+            incomplete_back_entry: incomplete_back_entry.as_ref().map(|v| v.debug_state()),
             renamed: ty
                 .renamed
                 .from_iter_sim(
@@ -1085,18 +1067,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
                 l1_reg_file: SimValue::from_array_elements(
                     state_for_debug.ty().l1_reg_file,
                     l1_reg_file.iter().map(|v| {
-                        SimValue::from_array_elements(
-                            state_for_debug.ty().l1_reg_file.element(),
-                            v.iter().map(|v| {
-                                if let Some(v) = v {
-                                    #[hdl(sim)]
-                                    HdlSome(v)
-                                } else {
-                                    #[hdl(sim)]
-                                    HdlNone()
-                                }
-                            }),
-                        )
+                        SimValue::from_array_elements(state_for_debug.ty().l1_reg_file.element(), v)
                     }),
                 ),
                 per_insn_timeline: self.per_insn_timeline(),
diff --git a/crates/cpu/src/rename_execute_retire/to_unit_interfaces.rs b/crates/cpu/src/rename_execute_retire/to_unit_interfaces.rs
index 2709083..d3ec39a 100644
--- a/crates/cpu/src/rename_execute_retire/to_unit_interfaces.rs
+++ b/crates/cpu/src/rename_execute_retire/to_unit_interfaces.rs
@@ -7,7 +7,10 @@ use fayalite::{
     expr::ops::FieldAccess,
     intern::{Intern, Interned, Memoize},
     prelude::*,
-    ty::{OpaqueSimValue, OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten},
+    ty::{
+        OpaqueSimValue, OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten,
+        SimValueDebug,
+    },
 };
 use std::{fmt, marker::PhantomData, ops::Index};
 
@@ -116,6 +119,15 @@ impl<C: Type + PhantomConstGet<CpuConfig>> Index<C> for ExecuteToUnitInterfacesW
     }
 }
 
+impl<C: Type + PhantomConstGet<CpuConfig>> SimValueDebug for ExecuteToUnitInterfaces<C> {
+    fn sim_value_debug(
+        value: &<Self as Type>::SimValue,
+        f: &mut fmt::Formatter<'_>,
+    ) -> fmt::Result {
+        fmt::Debug::fmt(value, f)
+    }
+}
+
 impl<C: Type + PhantomConstGet<CpuConfig>> Type for ExecuteToUnitInterfaces<C> {
     type BaseType = Bundle;
     type MaskType = Bundle;
diff --git a/crates/cpu/tests/next_pc.rs b/crates/cpu/tests/next_pc.rs
index e17a8bd..2046a26 100644
--- a/crates/cpu/tests/next_pc.rs
+++ b/crates/cpu/tests/next_pc.rs
@@ -1163,13 +1163,7 @@ impl MockExecuteState {
                 id: &insn.id,
                 next_pc,
                 call_stack_op: mock_insn.call_stack_op(pc),
-                cond_br_taken: if let Some(cond_br_taken) = cond_br_taken {
-                    #[hdl(sim)]
-                    HdlSome(cond_br_taken)
-                } else {
-                    #[hdl(sim)]
-                    HdlNone()
-                },
+                cond_br_taken,
                 config: self.config,
             },
         )
diff --git a/crates/cpu/tests/rename_execute_retire.rs b/crates/cpu/tests/rename_execute_retire.rs
index fb4b14b..ac21b10 100644
--- a/crates/cpu/tests/rename_execute_retire.rs
+++ b/crates/cpu/tests/rename_execute_retire.rs
@@ -1817,20 +1817,8 @@ impl<C: PhantomConstCpuConfig> MockUnitOp<C> {
             mop,
             src_values,
             sent_cant_cause_cancel,
-            output_ready: if let Some(output_ready) = output_ready {
-                #[hdl(sim)]
-                output_ready_ty.HdlSome(output_ready)
-            } else {
-                #[hdl(sim)]
-                output_ready_ty.HdlNone()
-            },
-            caused_cancel: if let Some(caused_cancel) = caused_cancel {
-                #[hdl(sim)]
-                caused_cancel_ty.HdlSome(caused_cancel)
-            } else {
-                #[hdl(sim)]
-                caused_cancel_ty.HdlNone()
-            },
+            output_ready: output_ready.into_sim_value_with_type(output_ready_ty),
+            caused_cancel: caused_cancel.into_sim_value_with_type(caused_cancel_ty),
             config,
         }
     }
@@ -1985,20 +1973,8 @@ impl<C: PhantomConstCpuConfig, E: MockExecutionStateTrait> MockUnitState<C, E> {
             if op.output_ready.is_none() && op.caused_cancel.is_none() {
                 continue;
             }
-            let output_ready = if let Some(output_ready) = &op.output_ready {
-                #[hdl(sim)]
-                output_ready_ty.HdlSome(output_ready)
-            } else {
-                #[hdl(sim)]
-                output_ready_ty.HdlNone()
-            };
-            let caused_cancel = if let Some(caused_cancel) = &op.caused_cancel {
-                #[hdl(sim)]
-                caused_cancel_ty.HdlSome(caused_cancel)
-            } else {
-                #[hdl(sim)]
-                caused_cancel_ty.HdlNone()
-            };
+            let output_ready = op.output_ready.to_sim_value_with_type(output_ready_ty);
+            let caused_cancel = op.caused_cancel.to_sim_value_with_type(caused_cancel_ty);
             // TODO: add delay
             return (
                 output_ready,
@@ -2301,20 +2277,8 @@ impl<C: PhantomConstCpuConfig> MockLoadStoreOp<C> {
         MockLoadStoreOpDebugState::<_> {
             mop,
             is_speculative,
-            src_values: if let Some(v) = src_values {
-                #[hdl(sim)]
-                HdlSome(v)
-            } else {
-                #[hdl(sim)]
-                HdlNone()
-            },
-            dest_value: if let Some(v) = dest_value {
-                #[hdl(sim)]
-                HdlSome(v)
-            } else {
-                #[hdl(sim)]
-                HdlNone()
-            },
+            src_values,
+            dest_value,
             ran_nonspeculatively,
             sent_cant_cause_cancel,
             sent_output_ready,
diff --git a/crates/cpu/tests/simple_power_isa_decoder/main.rs b/crates/cpu/tests/simple_power_isa_decoder/main.rs
index 9fa5d3c..a345f44 100644
--- a/crates/cpu/tests/simple_power_isa_decoder/main.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/main.rs
@@ -152,16 +152,7 @@ fn test_decode_insn() {
     } in test_cases::test_cases()
     {
         sim.write(sim.io().first_input, first_input);
-        sim.write(
-            sim.io().second_input,
-            if let Some(v) = second_input {
-                #[hdl(sim)]
-                HdlSome(v)
-            } else {
-                #[hdl(sim)]
-                HdlNone()
-            },
-        );
+        sim.write(sim.io().second_input, second_input);
         sim.advance_time(SimDuration::from_micros(1));
         let second_input_used = sim.read_bool(sim.io().second_input_used);
         let is_illegal = sim.read_bool(sim.io().is_illegal);
diff --git a/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_rotate_and_shift.rs b/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_rotate_and_shift.rs
index 29f84b4..6195154 100644
--- a/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_rotate_and_shift.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_rotate_and_shift.rs
@@ -30,13 +30,7 @@ fn rotate_imm(
 ) -> SimValue<ShiftRotateMOpImm> {
     #[hdl(sim)]
     ShiftRotateMOpImm {
-        shift_rotate_amount: if let Some(amount) = amount {
-            #[hdl(sim)]
-            HdlSome(amount.cast_to_static::<UInt<_>>())
-        } else {
-            #[hdl(sim)]
-            HdlNone()
-        },
+        shift_rotate_amount: amount.map(|amount| amount.cast_to_static::<UInt<_>>()),
         shift_rotate_right: false,
         dest_logic_op: if let Some((rotated_output_start, rotated_output_len)) =
             rotated_output_start_and_len