From a4b052f5f3dfe67c8dbf7c27d4510d7f651936a4 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Sun, 18 Jan 2026 15:02:15 -0800 Subject: [PATCH] decode all fixed-point add/sub instructions other than addex --- crates/cpu/src/decoder/simple_power_isa.rs | 254 ++- crates/cpu/tests/expected/decode_one_insn.vcd | 1849 ++++++++++++++--- crates/cpu/tests/simple_power_isa_decoder.rs | 290 ++- 3 files changed, 2112 insertions(+), 281 deletions(-) diff --git a/crates/cpu/src/decoder/simple_power_isa.rs b/crates/cpu/src/decoder/simple_power_isa.rs index c2e08f6..44622b2 100644 --- a/crates/cpu/src/decoder/simple_power_isa.rs +++ b/crates/cpu/src/decoder/simple_power_isa.rs @@ -185,6 +185,10 @@ impl_fields! { struct FieldRT(FieldGpr); #[name = "SI"] struct FieldSI(SInt<16>); + #[name = "si0"] + struct FieldSi0(SInt<18>); + #[name = "si1"] + struct FieldSi1(UInt<16>); #[name = "d0"] struct FieldAddPcISD0(SInt<10>); #[name = "d1"] @@ -193,6 +197,8 @@ impl_fields! { struct FieldAddPcISD2(UInt<1>); #[name = "OE"] struct FieldOE(Bool); + #[name = "R"] + struct FieldR(Bool); #[name = "Rc"] struct FieldRc(Bool); } @@ -388,17 +394,17 @@ impl DecodeState { } if let Some(prefix) = self.header.bit_fields().prefix() { #[hdl] - if let HdlSome(prefix_word) = self.second_input { + if let HdlSome(suffix_word) = self.second_input { self.decode_word( &mut matches, &mut fields, - prefix_word, + self.first_input, prefix.fields_inner(), ); self.decode_word( &mut matches, &mut fields, - self.first_input, + suffix_word, self.header.bit_fields().fields_inner(), ); run(self, matches, &mut fields, &mut f); @@ -442,7 +448,28 @@ impl DecodeState { }); } "paddi" => { - // TODO + self.decode_scope( + |this, (FieldRT(rt), FieldRA(ra), FieldSi0(si0), FieldSi1(si1), FieldR(r))| { + connect( + ArrayVec::len(this.output), + 1usize.cast_to_static::>(), + ); + connect( + this.output[0], + AddSubMOp::add_sub_i( + MOpDestReg::new([gpr(rt)], []), + #[hdl] + [gpr_or_zero(ra).value, MOpRegNum::const_zero().value], + ((si0 << 16) + si1.cast_to(SInt[34])).cast_to_static(), + OutputIntegerMode.Full64(), + false, + false, + false, + r, + ), + ); + }, + ); } _ => unreachable!("{:?}", self.mnemonic), } @@ -561,14 +588,74 @@ impl DecodeState { ); }); } - /// for `subf[o][.]` + /// for `subf[c][o][.]` #[hdl] - fn decode_subf(&mut self) { - // TODO + fn decode_subf_subfc(&mut self) { + self.decode_scope( + |this, (FieldRT(rt), FieldRA(ra), FieldRB(rb), FieldOE(oe), FieldRc(rc))| { + // TODO: handle SO propagation + connect( + ArrayVec::len(this.output), + 1usize.cast_to_static::>(), + ); + connect( + this.output[0], + AddSubMOp::add_sub( + MOpDestReg::new( + [ + gpr(rt), + if this.mnemonic.contains('c') { + MOpRegNum::power_isa_xer_ca_ca32_reg() + } else { + MOpRegNum::const_zero() + }, + ], + [ + (MOpRegNum::POWER_ISA_XER_SO_OV_OV32_REG_NUM, oe), + (MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc), + ], + ), + #[hdl] + [gpr(ra).value, gpr(rb).value, MOpRegNum::const_zero().value], + 0i8.cast_to_static::>(), + OutputIntegerMode.Full64(), + true, + false, + true, + false, + ), + ); + }, + ); } #[hdl] fn decode_subfic(&mut self) { - // TODO + self.decode_scope(|this, (FieldRT(rt), FieldRA(ra), FieldSI(si))| { + connect( + ArrayVec::len(this.output), + 1usize.cast_to_static::>(), + ); + connect( + this.output[0], + AddSubMOp::add_sub_i( + MOpDestReg::new( + [gpr(rt), MOpRegNum::power_isa_xer_ca_ca32_reg()], + [( + MOpRegNum::POWER_ISA_CR_0_REG_NUM, + self.mnemonic.ends_with('.').to_expr(), + )], + ), + #[hdl] + [gpr(ra).value, MOpRegNum::const_zero().value], + si.cast_to_static(), + OutputIntegerMode.Full64(), + true, + false, + true, + false, + ), + ); + }); } /// for `addc[o][.]` #[hdl] @@ -603,11 +690,6 @@ impl DecodeState { }, ); } - /// for `subfc[o][.]` - #[hdl] - fn decode_subfc(&mut self) { - // TODO - } /// for `adde[o][.]` #[hdl] fn decode_adde(&mut self) { @@ -645,6 +727,118 @@ impl DecodeState { }, ); } + /// for `subfe[o][.]` + #[hdl] + fn decode_subfe(&mut self) { + self.decode_scope( + |this, (FieldRT(rt), FieldRA(ra), FieldRB(rb), FieldOE(oe), FieldRc(rc))| { + // TODO: handle SO propagation + connect( + ArrayVec::len(this.output), + 1usize.cast_to_static::>(), + ); + connect( + this.output[0], + AddSubMOp::add_sub( + MOpDestReg::new( + [gpr(rt), MOpRegNum::power_isa_xer_ca_ca32_reg()], + [ + (MOpRegNum::POWER_ISA_XER_SO_OV_OV32_REG_NUM, oe), + (MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc), + ], + ), + #[hdl] + [ + gpr(ra).value, + MOpRegNum::power_isa_xer_ca_ca32_reg().value, + gpr(rb).value, + ], + 0i8.cast_to_static::>(), + OutputIntegerMode.Full64(), + true, + true, + false, + false, + ), + ); + }, + ); + } + /// for `addme[o][.]` and `subfme[o][.]` and `addze[o][.]` and `subfze[o][.]` + #[hdl] + fn decode_addme_subfme_addze_subfze(&mut self) { + self.decode_scope( + |this, (FieldRT(rt), FieldRA(ra), FieldOE(oe), FieldRc(rc))| { + // TODO: handle SO propagation + connect( + ArrayVec::len(this.output), + 1usize.cast_to_static::>(), + ); + connect( + this.output[0], + AddSubMOp::add_sub( + MOpDestReg::new( + [gpr(rt), MOpRegNum::power_isa_xer_ca_ca32_reg()], + [ + (MOpRegNum::POWER_ISA_XER_SO_OV_OV32_REG_NUM, oe), + (MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc), + ], + ), + #[hdl] + [ + gpr(ra).value, + MOpRegNum::power_isa_xer_ca_ca32_reg().value, + MOpRegNum::const_zero().value, + ], + if this.mnemonic.contains('m') { -1i8 } else { 0 } + .cast_to_static::>(), + OutputIntegerMode.Full64(), + this.mnemonic.contains("subf"), + true, + false, + false, + ), + ); + }, + ); + } + /// for `neg[o][.]` + #[hdl] + fn decode_neg(&mut self) { + self.decode_scope( + |this, (FieldRT(rt), FieldRA(ra), FieldOE(oe), FieldRc(rc))| { + // TODO: handle SO propagation + connect( + ArrayVec::len(this.output), + 1usize.cast_to_static::>(), + ); + connect( + this.output[0], + AddSubMOp::add_sub( + MOpDestReg::new( + [gpr(rt)], + [ + (MOpRegNum::POWER_ISA_XER_SO_OV_OV32_REG_NUM, oe), + (MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc), + ], + ), + #[hdl] + [ + gpr(ra).value, + MOpRegNum::const_zero().value, + MOpRegNum::const_zero().value, + ], + 0i8.cast_to_static::>(), + OutputIntegerMode.Full64(), + true, + false, + true, + false, + ), + ); + }, + ); + } } type DecodeFn = fn(&mut DecodeState); @@ -718,7 +912,7 @@ const DECODE_FNS: &[(&[&str], DecodeFn)] = &[ (&["addic", "addic."], DecodeState::decode_addic), ( &["subf", "subf.", "subfo", "subfo."], - DecodeState::decode_subf, + DecodeState::decode_subf_subfc, ), (&["subfic"], DecodeState::decode_subfic), ( @@ -727,33 +921,27 @@ const DECODE_FNS: &[(&[&str], DecodeFn)] = &[ ), ( &["subfc", "subfc.", "subfco", "subfco."], - DecodeState::decode_subfc, + DecodeState::decode_subf_subfc, ), ( &["adde", "adde.", "addeo", "addeo."], DecodeState::decode_adde, ), - (&["subfe", "subfe.", "subfeo", "subfeo."], |_state| { - // TODO - }), - (&["addme", "addme.", "addmeo", "addmeo."], |_state| { - // TODO - }), - (&["addze", "addze.", "addzeo", "addzeo."], |_state| { - // TODO - }), - (&["subfme", "subfme.", "subfmeo", "subfmeo."], |_state| { - // TODO - }), - (&["subfze", "subfze.", "subfzeo", "subfzeo."], |_state| { - // TODO - }), + ( + &["subfe", "subfe.", "subfeo", "subfeo."], + DecodeState::decode_subfe, + ), + ( + &[ + "addme", "addme.", "addmeo", "addmeo.", "addze", "addze.", "addzeo", "addzeo.", + "subfme", "subfme.", "subfmeo", "subfmeo.", "subfze", "subfze.", "subfzeo", "subfzeo.", + ], + DecodeState::decode_addme_subfme_addze_subfze, + ), (&["addex"], |_state| { // TODO }), - (&["neg", "neg.", "nego", "nego."], |_state| { - // TODO - }), + (&["neg", "neg.", "nego", "nego."], DecodeState::decode_neg), ( &[ "mulli", "mullw", "mullw.", "mullwo", "mullwo.", "mulhw", "mulhw.", "mulhwu", "mulhwu.", diff --git a/crates/cpu/tests/expected/decode_one_insn.vcd b/crates/cpu/tests/expected/decode_one_insn.vcd index fb5f75f..12ff601 100644 --- a/crates/cpu/tests/expected/decode_one_insn.vcd +++ b/crates/cpu/tests/expected/decode_one_insn.vcd @@ -499,188 +499,600 @@ $var wire 5 b" addi_RT $end $scope struct power_isa_gpr_or_zero_reg $end $var wire 8 c" value $end $upscope $end -$var wire 16 d" addis_SI $end -$var wire 5 e" addis_RA $end -$var wire 5 f" addis_RT $end +$var wire 18 d" paddi_si0 $end +$var wire 1 e" paddi_R $end +$var wire 16 f" paddi_si1 $end +$var wire 5 g" paddi_RA $end +$var wire 5 h" paddi_RT $end $scope struct power_isa_gpr_or_zero_reg_2 $end -$var wire 8 g" value $end +$var wire 8 i" value $end $upscope $end -$var wire 1 h" addpcis_d2 $end -$var wire 10 i" addpcis_d0 $end -$var wire 5 j" addpcis_d1 $end -$var wire 5 k" addpcis_RT $end -$var wire 5 l" add_RB $end -$var wire 5 m" add_RA $end -$var wire 5 n" add_RT $end +$var wire 16 j" addis_SI $end +$var wire 5 k" addis_RA $end +$var wire 5 l" addis_RT $end +$scope struct power_isa_gpr_or_zero_reg_3 $end +$var wire 8 m" value $end +$upscope $end +$var wire 1 n" addpcis_d2 $end +$var wire 10 o" addpcis_d0 $end +$var wire 5 p" addpcis_d1 $end +$var wire 5 q" addpcis_RT $end +$var wire 5 r" add_RB $end +$var wire 5 s" add_RA $end +$var wire 5 t" add_RT $end $scope struct flag_reg_0 $end -$var string 1 o" \$tag $end -$scope struct HdlSome $end -$upscope $end -$upscope $end -$scope struct flag_reg_1 $end -$var string 1 p" \$tag $end -$scope struct HdlSome $end -$upscope $end -$upscope $end -$var wire 5 q" add__RB $end -$var wire 5 r" add__RA $end -$var wire 5 s" add__RT $end -$scope struct flag_reg_0_2 $end -$var string 1 t" \$tag $end -$scope struct HdlSome $end -$upscope $end -$upscope $end -$scope struct flag_reg_1_2 $end $var string 1 u" \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$var wire 5 v" addo_RB $end -$var wire 5 w" addo_RA $end -$var wire 5 x" addo_RT $end -$scope struct flag_reg_0_3 $end -$var string 1 y" \$tag $end +$scope struct flag_reg_1 $end +$var string 1 v" \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$scope struct flag_reg_1_3 $end +$var wire 5 w" add__RB $end +$var wire 5 x" add__RA $end +$var wire 5 y" add__RT $end +$scope struct flag_reg_0_2 $end $var string 1 z" \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$var wire 5 {" addo__RB $end -$var wire 5 |" addo__RA $end -$var wire 5 }" addo__RT $end -$scope struct flag_reg_0_4 $end -$var string 1 ~" \$tag $end +$scope struct flag_reg_1_2 $end +$var string 1 {" \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$scope struct flag_reg_1_4 $end +$var wire 5 |" addo_RB $end +$var wire 5 }" addo_RA $end +$var wire 5 ~" addo_RT $end +$scope struct flag_reg_0_3 $end $var string 1 !# \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$var wire 16 "# addic_SI $end -$var wire 5 ## addic_RA $end -$var wire 5 $# addic_RT $end +$scope struct flag_reg_1_3 $end +$var string 1 "# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 ## addo__RB $end +$var wire 5 $# addo__RA $end +$var wire 5 %# addo__RT $end +$scope struct flag_reg_0_4 $end +$var string 1 &# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_4 $end +$var string 1 '# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 16 (# addic_SI $end +$var wire 5 )# addic_RA $end +$var wire 5 *# addic_RT $end $scope struct flag_reg_1_5 $end -$var string 1 %# \$tag $end +$var string 1 +# \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$var wire 16 &# addic__SI $end -$var wire 5 '# addic__RA $end -$var wire 5 (# addic__RT $end +$var wire 16 ,# addic__SI $end +$var wire 5 -# addic__RA $end +$var wire 5 .# addic__RT $end $scope struct flag_reg_1_6 $end -$var string 1 )# \$tag $end +$var string 1 /# \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$var wire 5 *# addc_RB $end -$var wire 5 +# addc_RA $end -$var wire 5 ,# addc_RT $end +$var wire 5 0# subf_RB $end +$var wire 5 1# subf_RA $end +$var wire 5 2# subf_RT $end $scope struct flag_reg_0_5 $end -$var string 1 -# \$tag $end -$scope struct HdlSome $end -$upscope $end -$upscope $end -$scope struct flag_reg_1_7 $end -$var string 1 .# \$tag $end -$scope struct HdlSome $end -$upscope $end -$upscope $end -$var wire 5 /# addc__RB $end -$var wire 5 0# addc__RA $end -$var wire 5 1# addc__RT $end -$scope struct flag_reg_0_6 $end -$var string 1 2# \$tag $end -$scope struct HdlSome $end -$upscope $end -$upscope $end -$scope struct flag_reg_1_8 $end $var string 1 3# \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$var wire 5 4# addco_RB $end -$var wire 5 5# addco_RA $end -$var wire 5 6# addco_RT $end -$scope struct flag_reg_0_7 $end -$var string 1 7# \$tag $end +$scope struct flag_reg_1_7 $end +$var string 1 4# \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$scope struct flag_reg_1_9 $end +$var wire 5 5# subf__RB $end +$var wire 5 6# subf__RA $end +$var wire 5 7# subf__RT $end +$scope struct flag_reg_0_6 $end $var string 1 8# \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$var wire 5 9# addco__RB $end -$var wire 5 :# addco__RA $end -$var wire 5 ;# addco__RT $end -$scope struct flag_reg_0_8 $end -$var string 1 <# \$tag $end +$scope struct flag_reg_1_8 $end +$var string 1 9# \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$scope struct flag_reg_1_10 $end +$var wire 5 :# subfo_RB $end +$var wire 5 ;# subfo_RA $end +$var wire 5 <# subfo_RT $end +$scope struct flag_reg_0_7 $end $var string 1 =# \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$var wire 5 ># adde_RB $end -$var wire 5 ?# adde_RA $end -$var wire 5 @# adde_RT $end -$scope struct flag_reg_0_9 $end -$var string 1 A# \$tag $end +$scope struct flag_reg_1_9 $end +$var string 1 ># \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$scope struct flag_reg_1_11 $end +$var wire 5 ?# subfo__RB $end +$var wire 5 @# subfo__RA $end +$var wire 5 A# subfo__RT $end +$scope struct flag_reg_0_8 $end $var string 1 B# \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$var wire 5 C# adde__RB $end -$var wire 5 D# adde__RA $end -$var wire 5 E# adde__RT $end -$scope struct flag_reg_0_10 $end -$var string 1 F# \$tag $end +$scope struct flag_reg_1_10 $end +$var string 1 C# \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$scope struct flag_reg_1_12 $end +$var wire 16 D# subfic_SI $end +$var wire 5 E# subfic_RA $end +$var wire 5 F# subfic_RT $end +$scope struct flag_reg_1_11 $end $var string 1 G# \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$var wire 5 H# addeo_RB $end -$var wire 5 I# addeo_RA $end -$var wire 5 J# addeo_RT $end -$scope struct flag_reg_0_11 $end +$var wire 5 H# addc_RB $end +$var wire 5 I# addc_RA $end +$var wire 5 J# addc_RT $end +$scope struct flag_reg_0_9 $end $var string 1 K# \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$scope struct flag_reg_1_13 $end +$scope struct flag_reg_1_12 $end $var string 1 L# \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$var wire 5 M# addeo__RB $end -$var wire 5 N# addeo__RA $end -$var wire 5 O# addeo__RT $end -$scope struct flag_reg_0_12 $end +$var wire 5 M# addc__RB $end +$var wire 5 N# addc__RA $end +$var wire 5 O# addc__RT $end +$scope struct flag_reg_0_10 $end $var string 1 P# \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end -$scope struct flag_reg_1_14 $end +$scope struct flag_reg_1_13 $end $var string 1 Q# \$tag $end $scope struct HdlSome $end $upscope $end $upscope $end +$var wire 5 R# addco_RB $end +$var wire 5 S# addco_RA $end +$var wire 5 T# addco_RT $end +$scope struct flag_reg_0_11 $end +$var string 1 U# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_14 $end +$var string 1 V# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 W# addco__RB $end +$var wire 5 X# addco__RA $end +$var wire 5 Y# addco__RT $end +$scope struct flag_reg_0_12 $end +$var string 1 Z# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_15 $end +$var string 1 [# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 \# subfc_RB $end +$var wire 5 ]# subfc_RA $end +$var wire 5 ^# subfc_RT $end +$scope struct flag_reg_0_13 $end +$var string 1 _# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_16 $end +$var string 1 `# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 a# subfc__RB $end +$var wire 5 b# subfc__RA $end +$var wire 5 c# subfc__RT $end +$scope struct flag_reg_0_14 $end +$var string 1 d# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_17 $end +$var string 1 e# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 f# subfco_RB $end +$var wire 5 g# subfco_RA $end +$var wire 5 h# subfco_RT $end +$scope struct flag_reg_0_15 $end +$var string 1 i# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_18 $end +$var string 1 j# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 k# subfco__RB $end +$var wire 5 l# subfco__RA $end +$var wire 5 m# subfco__RT $end +$scope struct flag_reg_0_16 $end +$var string 1 n# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_19 $end +$var string 1 o# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 p# adde_RB $end +$var wire 5 q# adde_RA $end +$var wire 5 r# adde_RT $end +$scope struct flag_reg_0_17 $end +$var string 1 s# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_20 $end +$var string 1 t# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 u# adde__RB $end +$var wire 5 v# adde__RA $end +$var wire 5 w# adde__RT $end +$scope struct flag_reg_0_18 $end +$var string 1 x# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_21 $end +$var string 1 y# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 z# addeo_RB $end +$var wire 5 {# addeo_RA $end +$var wire 5 |# addeo_RT $end +$scope struct flag_reg_0_19 $end +$var string 1 }# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_22 $end +$var string 1 ~# \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 !$ addeo__RB $end +$var wire 5 "$ addeo__RA $end +$var wire 5 #$ addeo__RT $end +$scope struct flag_reg_0_20 $end +$var string 1 $$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_23 $end +$var string 1 %$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 &$ subfe_RB $end +$var wire 5 '$ subfe_RA $end +$var wire 5 ($ subfe_RT $end +$scope struct flag_reg_0_21 $end +$var string 1 )$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_24 $end +$var string 1 *$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 +$ subfe__RB $end +$var wire 5 ,$ subfe__RA $end +$var wire 5 -$ subfe__RT $end +$scope struct flag_reg_0_22 $end +$var string 1 .$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_25 $end +$var string 1 /$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 0$ subfeo_RB $end +$var wire 5 1$ subfeo_RA $end +$var wire 5 2$ subfeo_RT $end +$scope struct flag_reg_0_23 $end +$var string 1 3$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_26 $end +$var string 1 4$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 5$ subfeo__RB $end +$var wire 5 6$ subfeo__RA $end +$var wire 5 7$ subfeo__RT $end +$scope struct flag_reg_0_24 $end +$var string 1 8$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_27 $end +$var string 1 9$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 :$ addme_RA $end +$var wire 5 ;$ addme_RT $end +$scope struct flag_reg_0_25 $end +$var string 1 <$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_28 $end +$var string 1 =$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 >$ addme__RA $end +$var wire 5 ?$ addme__RT $end +$scope struct flag_reg_0_26 $end +$var string 1 @$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_29 $end +$var string 1 A$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 B$ addmeo_RA $end +$var wire 5 C$ addmeo_RT $end +$scope struct flag_reg_0_27 $end +$var string 1 D$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_30 $end +$var string 1 E$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 F$ addmeo__RA $end +$var wire 5 G$ addmeo__RT $end +$scope struct flag_reg_0_28 $end +$var string 1 H$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_31 $end +$var string 1 I$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 J$ addze_RA $end +$var wire 5 K$ addze_RT $end +$scope struct flag_reg_0_29 $end +$var string 1 L$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_32 $end +$var string 1 M$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 N$ addze__RA $end +$var wire 5 O$ addze__RT $end +$scope struct flag_reg_0_30 $end +$var string 1 P$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_33 $end +$var string 1 Q$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 R$ addzeo_RA $end +$var wire 5 S$ addzeo_RT $end +$scope struct flag_reg_0_31 $end +$var string 1 T$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_34 $end +$var string 1 U$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 V$ addzeo__RA $end +$var wire 5 W$ addzeo__RT $end +$scope struct flag_reg_0_32 $end +$var string 1 X$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_35 $end +$var string 1 Y$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 Z$ subfme_RA $end +$var wire 5 [$ subfme_RT $end +$scope struct flag_reg_0_33 $end +$var string 1 \$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_36 $end +$var string 1 ]$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 ^$ subfme__RA $end +$var wire 5 _$ subfme__RT $end +$scope struct flag_reg_0_34 $end +$var string 1 `$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_37 $end +$var string 1 a$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 b$ subfmeo_RA $end +$var wire 5 c$ subfmeo_RT $end +$scope struct flag_reg_0_35 $end +$var string 1 d$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_38 $end +$var string 1 e$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 f$ subfmeo__RA $end +$var wire 5 g$ subfmeo__RT $end +$scope struct flag_reg_0_36 $end +$var string 1 h$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_39 $end +$var string 1 i$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 j$ subfze_RA $end +$var wire 5 k$ subfze_RT $end +$scope struct flag_reg_0_37 $end +$var string 1 l$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_40 $end +$var string 1 m$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 n$ subfze__RA $end +$var wire 5 o$ subfze__RT $end +$scope struct flag_reg_0_38 $end +$var string 1 p$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_41 $end +$var string 1 q$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 r$ subfzeo_RA $end +$var wire 5 s$ subfzeo_RT $end +$scope struct flag_reg_0_39 $end +$var string 1 t$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_42 $end +$var string 1 u$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 v$ subfzeo__RA $end +$var wire 5 w$ subfzeo__RT $end +$scope struct flag_reg_0_40 $end +$var string 1 x$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_43 $end +$var string 1 y$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 z$ neg_RA $end +$var wire 5 {$ neg_RT $end +$scope struct flag_reg_0_41 $end +$var string 1 |$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_44 $end +$var string 1 }$ \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 ~$ neg__RA $end +$var wire 5 !% neg__RT $end +$scope struct flag_reg_0_42 $end +$var string 1 "% \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_45 $end +$var string 1 #% \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 $% nego_RA $end +$var wire 5 %% nego_RT $end +$scope struct flag_reg_0_43 $end +$var string 1 &% \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_46 $end +$var string 1 '% \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$var wire 5 (% nego__RA $end +$var wire 5 )% nego__RT $end +$scope struct flag_reg_0_44 $end +$var string 1 *% \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end +$scope struct flag_reg_1_47 $end +$var string 1 +% \$tag $end +$scope struct HdlSome $end +$upscope $end +$upscope $end $upscope $end $enddefinitions $end $dumpvars @@ -846,97 +1258,618 @@ b100 a" b11 b" b100100 c" b1001000110100 d" -b100 e" -b11 f" -b100100 g" -0h" -b1001000 i" -b100 j" -b11 k" -b10 l" -b100 m" -b11 n" -sHdlNone\x20(0) o" -sHdlNone\x20(0) p" -b10 q" -b100 r" -b11 s" -sHdlNone\x20(0) t" -sHdlSome\x20(1) u" -b10 v" -b100 w" -b11 x" -sHdlSome\x20(1) y" +0e" +b0 f" +b0 g" +b0 h" +b0 i" +b1001000110100 j" +b100 k" +b11 l" +b100100 m" +0n" +b1001000 o" +b100 p" +b11 q" +b10 r" +b100 s" +b11 t" +sHdlNone\x20(0) u" +sHdlNone\x20(0) v" +b10 w" +b100 x" +b11 y" sHdlNone\x20(0) z" -b10 {" -b100 |" -b11 }" -sHdlSome\x20(1) ~" +sHdlSome\x20(1) {" +b10 |" +b100 }" +b11 ~" sHdlSome\x20(1) !# -b1001000110100 "# -b100 ## -b11 $# -sHdlNone\x20(0) %# -b1001000110100 &# -b100 '# -b11 (# -sHdlSome\x20(1) )# -b10 *# -b100 +# -b11 ,# -sHdlNone\x20(0) -# -sHdlNone\x20(0) .# -b10 /# -b100 0# -b11 1# -sHdlNone\x20(0) 2# -sHdlSome\x20(1) 3# -b10 4# -b100 5# -b11 6# -sHdlSome\x20(1) 7# +sHdlNone\x20(0) "# +b10 ## +b100 $# +b11 %# +sHdlSome\x20(1) &# +sHdlSome\x20(1) '# +b1001000110100 (# +b100 )# +b11 *# +sHdlNone\x20(0) +# +b1001000110100 ,# +b100 -# +b11 .# +sHdlSome\x20(1) /# +b10 0# +b100 1# +b11 2# +sHdlNone\x20(0) 3# +sHdlNone\x20(0) 4# +b10 5# +b100 6# +b11 7# sHdlNone\x20(0) 8# -b10 9# -b100 :# -b11 ;# -sHdlSome\x20(1) <# +sHdlSome\x20(1) 9# +b10 :# +b100 ;# +b11 <# sHdlSome\x20(1) =# -b10 ># -b100 ?# -b11 @# -sHdlNone\x20(0) A# -sHdlNone\x20(0) B# -b10 C# -b100 D# -b11 E# -sHdlNone\x20(0) F# -sHdlSome\x20(1) G# +sHdlNone\x20(0) ># +b10 ?# +b100 @# +b11 A# +sHdlSome\x20(1) B# +sHdlSome\x20(1) C# +b1001000110100 D# +b100 E# +b11 F# +sHdlNone\x20(0) G# b10 H# b100 I# b11 J# -sHdlSome\x20(1) K# +sHdlNone\x20(0) K# sHdlNone\x20(0) L# b10 M# b100 N# b11 O# -sHdlSome\x20(1) P# +sHdlNone\x20(0) P# sHdlSome\x20(1) Q# +b10 R# +b100 S# +b11 T# +sHdlSome\x20(1) U# +sHdlNone\x20(0) V# +b10 W# +b100 X# +b11 Y# +sHdlSome\x20(1) Z# +sHdlSome\x20(1) [# +b10 \# +b100 ]# +b11 ^# +sHdlNone\x20(0) _# +sHdlNone\x20(0) `# +b10 a# +b100 b# +b11 c# +sHdlNone\x20(0) d# +sHdlSome\x20(1) e# +b10 f# +b100 g# +b11 h# +sHdlSome\x20(1) i# +sHdlNone\x20(0) j# +b10 k# +b100 l# +b11 m# +sHdlSome\x20(1) n# +sHdlSome\x20(1) o# +b10 p# +b100 q# +b11 r# +sHdlNone\x20(0) s# +sHdlNone\x20(0) t# +b10 u# +b100 v# +b11 w# +sHdlNone\x20(0) x# +sHdlSome\x20(1) y# +b10 z# +b100 {# +b11 |# +sHdlSome\x20(1) }# +sHdlNone\x20(0) ~# +b10 !$ +b100 "$ +b11 #$ +sHdlSome\x20(1) $$ +sHdlSome\x20(1) %$ +b10 &$ +b100 '$ +b11 ($ +sHdlNone\x20(0) )$ +sHdlNone\x20(0) *$ +b10 +$ +b100 ,$ +b11 -$ +sHdlNone\x20(0) .$ +sHdlSome\x20(1) /$ +b10 0$ +b100 1$ +b11 2$ +sHdlSome\x20(1) 3$ +sHdlNone\x20(0) 4$ +b10 5$ +b100 6$ +b11 7$ +sHdlSome\x20(1) 8$ +sHdlSome\x20(1) 9$ +b100 :$ +b11 ;$ +sHdlNone\x20(0) <$ +sHdlNone\x20(0) =$ +b100 >$ +b11 ?$ +sHdlNone\x20(0) @$ +sHdlSome\x20(1) A$ +b100 B$ +b11 C$ +sHdlSome\x20(1) D$ +sHdlNone\x20(0) E$ +b100 F$ +b11 G$ +sHdlSome\x20(1) H$ +sHdlSome\x20(1) I$ +b100 J$ +b11 K$ +sHdlNone\x20(0) L$ +sHdlNone\x20(0) M$ +b100 N$ +b11 O$ +sHdlNone\x20(0) P$ +sHdlSome\x20(1) Q$ +b100 R$ +b11 S$ +sHdlSome\x20(1) T$ +sHdlNone\x20(0) U$ +b100 V$ +b11 W$ +sHdlSome\x20(1) X$ +sHdlSome\x20(1) Y$ +b100 Z$ +b11 [$ +sHdlNone\x20(0) \$ +sHdlNone\x20(0) ]$ +b100 ^$ +b11 _$ +sHdlNone\x20(0) `$ +sHdlSome\x20(1) a$ +b100 b$ +b11 c$ +sHdlSome\x20(1) d$ +sHdlNone\x20(0) e$ +b100 f$ +b11 g$ +sHdlSome\x20(1) h$ +sHdlSome\x20(1) i$ +b100 j$ +b11 k$ +sHdlNone\x20(0) l$ +sHdlNone\x20(0) m$ +b100 n$ +b11 o$ +sHdlNone\x20(0) p$ +sHdlSome\x20(1) q$ +b100 r$ +b11 s$ +sHdlSome\x20(1) t$ +sHdlNone\x20(0) u$ +b100 v$ +b11 w$ +sHdlSome\x20(1) x$ +sHdlSome\x20(1) y$ +b100 z$ +b11 {$ +sHdlNone\x20(0) |$ +sHdlNone\x20(0) }$ +b100 ~$ +b11 !% +sHdlNone\x20(0) "% +sHdlSome\x20(1) #% +b100 $% +b11 %% +sHdlSome\x20(1) &% +sHdlNone\x20(0) '% +b100 (% +b11 )% +sHdlSome\x20(1) *% +sHdlSome\x20(1) +% $end #1000000 +b10010001 * +b1010001010110011110001001 + +b10010001 9 +b1010001010110011110001001 : +b10010001 H +b1010001010110011110001001 I +b10010001 T +b1010001010110011110001001 U +b10010001 _ +b1010001010110011110001001 ` +b10010001 i +b1010001010110011110001001 j +b110000000010010001101000101 \" +sHdlSome\x20(1) ]" +b111000011001000110011110001001 ^" +1_" +b10001101000101 `" +b1 a" +b10000 b" +b100001 c" +b10010001101000101 d" +b110011110001001 f" +b100 g" +b11 h" +b100100 i" +b10001101000101 j" +b1 k" +b10000 l" +b100001 m" +1n" +b10001101 o" +b1 p" +b10000 q" +b100 r" +b1 s" +b10000 t" +b100 w" +b1 x" +b10000 y" +b100 |" +b1 }" +b10000 ~" +b100 ## +b1 $# +b10000 %# +b10001101000101 (# +b1 )# +b10000 *# +b10001101000101 ,# +b1 -# +b10000 .# +b100 0# +b1 1# +b10000 2# +b100 5# +b1 6# +b10000 7# +b100 :# +b1 ;# +b10000 <# +b100 ?# +b1 @# +b10000 A# +b10001101000101 D# +b1 E# +b10000 F# +b100 H# +b1 I# +b10000 J# +b100 M# +b1 N# +b10000 O# +b100 R# +b1 S# +b10000 T# +b100 W# +b1 X# +b10000 Y# +b100 \# +b1 ]# +b10000 ^# +b100 a# +b1 b# +b10000 c# +b100 f# +b1 g# +b10000 h# +b100 k# +b1 l# +b10000 m# +b100 p# +b1 q# +b10000 r# +b100 u# +b1 v# +b10000 w# +b100 z# +b1 {# +b10000 |# +b100 !$ +b1 "$ +b10000 #$ +b100 &$ +b1 '$ +b10000 ($ +b100 +$ +b1 ,$ +b10000 -$ +b100 0$ +b1 1$ +b10000 2$ +b100 5$ +b1 6$ +b10000 7$ +b1 :$ +b10000 ;$ +b1 >$ +b10000 ?$ +b1 B$ +b10000 C$ +b1 F$ +b10000 G$ +b1 J$ +b10000 K$ +b1 N$ +b10000 O$ +b1 R$ +b10000 S$ +b1 V$ +b10000 W$ +b1 Z$ +b10000 [$ +b1 ^$ +b10000 _$ +b1 b$ +b10000 c$ +b1 f$ +b10000 g$ +b1 j$ +b10000 k$ +b1 n$ +b10000 o$ +b1 r$ +b10000 s$ +b1 v$ +b10000 w$ +b1 z$ +b10000 {$ +b1 ~$ +b10000 !% +b1 $% +b10000 %% +b1 (% +b10000 )% +#2000000 +b0 ( +11 +b0 7 +1@ +b0 F +b1000 L +b0 R +b0 ] +b0 g +b110000100010010001101000101 \" +b111000011000000110011110001001 ^" +b10001 a" +b110001 c" +1e" +b0 g" +b0 i" +b10001 k" +b110001 m" +b10001 p" +b10001 s" +b10001 x" +b10001 }" +b10001 $# +b10001 )# +b10001 -# +b10001 1# +b10001 6# +b10001 ;# +b10001 @# +b10001 E# +b10001 I# +b10001 N# +b10001 S# +b10001 X# +b10001 ]# +b10001 b# +b10001 g# +b10001 l# +b10001 q# +b10001 v# +b10001 {# +b10001 "$ +b10001 '$ +b10001 ,$ +b10001 1$ +b10001 6$ +b10001 :$ +b10001 >$ +b10001 B$ +b10001 F$ +b10001 J$ +b10001 N$ +b10001 R$ +b10001 V$ +b10001 Z$ +b10001 ^$ +b10001 b$ +b10001 f$ +b10001 j$ +b10001 n$ +b10001 r$ +b10001 v$ +b10001 z$ +b10001 ~$ +b10001 $% +b10001 (% +#3000000 +b100100 ( b1001 * b1101000000000000000000 + +01 +b100100 7 b1001 9 b1101000000000000000000 : +0@ +b100100 F b1001 H b1101000000000000000000 I +b0 L +b100100 R b1001 T b1101000000000000000000 U +b100100 ] b1001 _ b1101000000000000000000 ` +b100100 g b1001 i b1101000000000000000000 j b111100011001000001001000110100 \" -#2000000 +sHdlNone\x20(0) ]" +b0 ^" +0_" +b1001000110100 `" +b100 a" +b11 b" +b100100 c" +b1001000110100 d" +0e" +b0 f" +b0 h" +b1001000110100 j" +b100 k" +b11 l" +b100100 m" +0n" +b1001000 o" +b100 p" +b11 q" +b10 r" +b100 s" +b11 t" +b10 w" +b100 x" +b11 y" +b10 |" +b100 }" +b11 ~" +b10 ## +b100 $# +b11 %# +b1001000110100 (# +b100 )# +b11 *# +b1001000110100 ,# +b100 -# +b11 .# +b10 0# +b100 1# +b11 2# +b10 5# +b100 6# +b11 7# +b10 :# +b100 ;# +b11 <# +b10 ?# +b100 @# +b11 A# +b1001000110100 D# +b100 E# +b11 F# +b10 H# +b100 I# +b11 J# +b10 M# +b100 N# +b11 O# +b10 R# +b100 S# +b11 T# +b10 W# +b100 X# +b11 Y# +b10 \# +b100 ]# +b11 ^# +b10 a# +b100 b# +b11 c# +b10 f# +b100 g# +b11 h# +b10 k# +b100 l# +b11 m# +b10 p# +b100 q# +b11 r# +b10 u# +b100 v# +b11 w# +b10 z# +b100 {# +b11 |# +b10 !$ +b100 "$ +b11 #$ +b10 &$ +b100 '$ +b11 ($ +b10 +$ +b100 ,$ +b11 -$ +b10 0$ +b100 1$ +b11 2$ +b10 5$ +b100 6$ +b11 7$ +b100 :$ +b11 ;$ +b100 >$ +b11 ?$ +b100 B$ +b11 C$ +b100 F$ +b11 G$ +b100 J$ +b11 K$ +b100 N$ +b11 O$ +b100 R$ +b11 S$ +b100 V$ +b11 W$ +b100 Z$ +b11 [$ +b100 ^$ +b11 _$ +b100 b$ +b11 c$ +b100 f$ +b11 g$ +b100 j$ +b11 k$ +b100 n$ +b11 o$ +b100 r$ +b11 s$ +b100 v$ +b11 w$ +b100 z$ +b11 {$ +b100 ~$ +b11 !% +b100 $% +b11 %% +b100 (% +b11 )% +#4000000 b0 ( b1101000000000000000100 + 11 @@ -956,27 +1889,63 @@ b1001100011110100001001000000100 \" b1001000000100 `" b11010 a" b111010 c" -b1001000000100 d" -b11010 e" -b111010 g" -b11010 j" -b11010 m" -b11010 r" -b11010 w" -b11010 |" -b1001000000100 "# -b11010 ## -b1001000000100 &# -b11010 '# -b11010 +# -b11010 0# -b11010 5# -b11010 :# -b11010 ?# -b11010 D# +b100001001000000100 d" +1e" +b1001000000100 j" +b11010 k" +b111010 m" +b11010 p" +b11010 s" +b11010 x" +b11010 }" +b11010 $# +b1001000000100 (# +b11010 )# +b1001000000100 ,# +b11010 -# +b11010 1# +b11010 6# +b11010 ;# +b11010 @# +b1001000000100 D# +b11010 E# b11010 I# b11010 N# -#3000000 +b11010 S# +b11010 X# +b11010 ]# +b11010 b# +b11010 g# +b11010 l# +b11010 q# +b11010 v# +b11010 {# +b11010 "$ +b11010 '$ +b11010 ,$ +b11010 1$ +b11010 6$ +b11010 :$ +b11010 >$ +b11010 B$ +b11010 F$ +b11010 J$ +b11010 N$ +b11010 R$ +b11010 V$ +b11010 Z$ +b11010 ^$ +b11010 b$ +b11010 f$ +b11010 j$ +b11010 n$ +b11010 r$ +b11010 v$ +b11010 z$ +b11010 ~$ +b11010 $% +b11010 (% +#5000000 sAddSub\x20(0) " sHdlSome\x20(1) ' b100100 ( @@ -1018,40 +1987,88 @@ b10101000010101 `" b100 a" b100100 c" b10101000010101 d" -b100 e" -b100100 g" -1h" -b10101000 i" -b100 j" -b101 l" -b100 m" -b101 q" -b100 r" -b101 v" -b100 w" -b101 {" -b100 |" -b10101000010101 "# -b100 ## -b10101000010101 &# -b100 '# -b101 *# -b100 +# -b101 /# -b100 0# -b101 4# -b100 5# -b101 9# -b100 :# -b101 ># -b100 ?# -b101 C# -b100 D# +0e" +b10101000010101 j" +b100 k" +b100100 m" +1n" +b10101000 o" +b100 p" +b101 r" +b100 s" +b101 w" +b100 x" +b101 |" +b100 }" +b101 ## +b100 $# +b10101000010101 (# +b100 )# +b10101000010101 ,# +b100 -# +b101 0# +b100 1# +b101 5# +b100 6# +b101 :# +b100 ;# +b101 ?# +b100 @# +b10101000010101 D# +b100 E# b101 H# b100 I# b101 M# b100 N# -#4000000 +b101 R# +b100 S# +b101 W# +b100 X# +b101 \# +b100 ]# +b101 a# +b100 b# +b101 f# +b100 g# +b101 k# +b100 l# +b101 p# +b100 q# +b101 u# +b100 v# +b101 z# +b100 {# +b101 !$ +b100 "$ +b101 &$ +b100 '$ +b101 +$ +b100 ,$ +b101 0$ +b100 1$ +b101 5$ +b100 6$ +b100 :$ +b100 >$ +b100 B$ +b100 F$ +b100 J$ +b100 N$ +b100 R$ +b100 V$ +b100 Z$ +b100 ^$ +b100 b$ +b100 f$ +b100 j$ +b100 n$ +b100 r$ +b100 v$ +b100 z$ +b100 ~$ +b100 $% +b100 (% +#6000000 sAddSubI\x20(1) " b100 % b0 ) @@ -1076,55 +2093,393 @@ b1001000110100 j b110100011001000001001000110100 \" b1001000110100 `" b1001000110100 d" -0h" -b1001000 i" -b10 l" -b10 q" -b10 v" -b10 {" -b1001000110100 "# -b1001000110100 &# -b10 *# -b10 /# -b10 4# -b10 9# -b10 ># -b10 C# +b1001000110100 j" +0n" +b1001000 o" +b10 r" +b10 w" +b10 |" +b10 ## +b1001000110100 (# +b1001000110100 ,# +b10 0# +b10 5# +b10 :# +b10 ?# +b1001000110100 D# b10 H# b10 M# -#5000000 +b10 R# +b10 W# +b10 \# +b10 a# +b10 f# +b10 k# +b10 p# +b10 u# +b10 z# +b10 !$ +b10 &$ +b10 +$ +b10 0$ +b10 5$ +#7000000 sAddSub\x20(0) " +b0 % b100101 ) b0 + +1. +10 +b0 4 b100101 8 b0 : +1= +1? +b0 C b100101 G b0 I +b101 L b0 M +b0 O b100101 S b0 U sLoad\x20(0) W +b0 Z b100101 ^ b0 ` +b0 d +b100101 h +b0 j +b1111100011001000010100001010001 \" +b10100001010001 `" +b10100001010001 d" +b10100001010001 j" +1n" +b10100001 o" +b101 r" +b101 w" +b101 |" +b101 ## +b10100001010001 (# +b10100001010001 ,# +b101 0# +b101 5# +b101 :# +b101 ?# +b10100001010001 D# +b101 H# +b101 M# +b101 R# +b101 W# +b101 \# +b101 a# +b101 f# +b101 k# +b101 p# +b101 u# +b101 z# +b101 !$ +b101 &$ +b101 +$ +b101 0$ +b101 5$ +#8000000 +sAddSubI\x20(1) " +b100 % +sHdlNone\x20(0) ' +b0 ) +b1001000110100 + +b100 4 +sHdlNone\x20(0) 6 +b0 8 +b1001000110100 : +b100 C +sHdlNone\x20(0) E +b0 G +b1001000110100 I +b1 M +b100 O +sHdlNone\x20(0) Q +b0 S +b1001000110100 U +sStore\x20(1) W +b100 Z +sHdlNone\x20(0) \ +b0 ^ +b1001000110100 ` +b100 d +sHdlNone\x20(0) f +b0 h +b1001000110100 j +b100000011001000001001000110100 \" +b1001000110100 `" +b1001000110100 d" +b1001000110100 j" +0n" +b1001000 o" +b10 r" +b10 w" +b10 |" +b10 ## +b1001000110100 (# +b1001000110100 ,# +b10 0# +b10 5# +b10 :# +b10 ?# +b1001000110100 D# +b10 H# +b10 M# +b10 R# +b10 W# +b10 \# +b10 a# +b10 f# +b10 k# +b10 p# +b10 u# +b10 z# +b10 !$ +b10 &$ +b10 +$ +b10 0$ +b10 5$ +#9000000 +sAddSub\x20(0) " +sHdlSome\x20(1) ' +b100101 ) +b0 + +0. +00 +sHdlSome\x20(1) 6 +b100101 8 +b0 : +0= +0? +sHdlSome\x20(1) E +b100101 G +b0 I +b0 L +b0 M +sHdlSome\x20(1) Q +b100101 S +b0 U +sLoad\x20(0) W +sHdlSome\x20(1) \ +b100101 ^ +b0 ` +sHdlSome\x20(1) f b100101 h b0 j b1111100011001000010100000010101 \" b10100000010101 `" b10100000010101 d" -1h" -b10100000 i" -b101 l" -b101 q" -b101 v" -b101 {" -b10100000010101 "# -b10100000010101 &# -b101 *# -b101 /# -b101 4# -b101 9# -b101 ># -b101 C# +b10100000010101 j" +1n" +b10100000 o" +b101 r" +b101 w" +b101 |" +b101 ## +b10100000010101 (# +b10100000010101 ,# +b101 0# +b101 5# +b101 :# +b101 ?# +b10100000010101 D# b101 H# b101 M# -#6000000 +b101 R# +b101 W# +b101 \# +b101 a# +b101 f# +b101 k# +b101 p# +b101 u# +b101 z# +b101 !$ +b101 &$ +b101 +$ +b101 0$ +b101 5$ +#10000000 +1. +10 +1= +1? +b101 L +b1111100011001000010100000010001 \" +b10100000010001 `" +b10100000010001 d" +b10100000010001 j" +b10100000010001 (# +b10100000010001 ,# +b10100000010001 D# +#11000000 +b100 ) +b100101 * +0. +1/ +00 +b100 8 +b100101 9 +0= +1> +0? +b100 G +b100101 H +b10 L +b100 S +b100101 T +b100 ^ +b100101 _ +b100 h +b100101 i +b1111100011001000010100100010101 \" +b10100100010101 `" +b10100100010101 d" +b10100100010101 j" +b10100100 o" +b10100100010101 (# +b10100100010101 ,# +b10100100010101 D# +#12000000 +1. +1= +b11 L +b1111100011001000010100100010001 \" +b10100100010001 `" +b10100100010001 d" +b10100100010001 j" +b10100100010001 (# +b10100100010001 ,# +b10100100010001 D# +#13000000 +b0 * +b1111111111111111111111111 + +1, +0. +b0 9 +b1111111111111111111111111 : +1; +0= +b0 H +b1111111111111111111111111 I +1J +b10 L +b0 T +b1111111111111111111111111 U +1V +b0 _ +b1111111111111111111111111 ` +1a +b0 i +b1111111111111111111111111 j +1k +b1111100011001000000000111010101 \" +b111010101 `" +b111010101 d" +b111010101 j" +b111 o" +b0 r" +b0 w" +b0 |" +b0 ## +b111010101 (# +b111010101 ,# +b0 0# +b0 5# +b0 :# +b0 ?# +b111010101 D# +b0 H# +b0 M# +b0 R# +b0 W# +b0 \# +b0 a# +b0 f# +b0 k# +b0 p# +b0 u# +b0 z# +b0 !$ +b0 &$ +b0 +$ +b0 0$ +b0 5$ +#14000000 +1. +1= +b11 L +b1111100011001000000000111010001 \" +b111010001 `" +b111010001 d" +b111010001 j" +b111010001 (# +b111010001 ,# +b111010001 D# +#15000000 +b0 + +0, +0. +b0 : +0; +0= +b0 I +0J +b10 L +b0 U +0V +b0 ` +0a +b0 j +0k +b1111100011001000000000110010101 \" +b110010101 `" +b110010101 d" +b110010101 j" +b110 o" +b110010101 (# +b110010101 ,# +b110010101 D# +#16000000 +1. +1= +b11 L +b1111100011001000000000110010001 \" +b110010001 `" +b110010001 d" +b110010001 j" +b110010001 (# +b110010001 ,# +b110010001 D# +#17000000 +b0 % +b0 ) +0/ +10 +b0 4 +b0 8 +0> +1? +b0 C +b0 G +b101 L +b0 O +b0 S +b0 Z +b0 ^ +b0 d +b0 h +b1111100011001000000000011010001 \" +b11010001 `" +b11010001 d" +b11010001 j" +b11 o" +b11010001 (# +b11010001 ,# +b11010001 D# +#18000000 diff --git a/crates/cpu/tests/simple_power_isa_decoder.rs b/crates/cpu/tests/simple_power_isa_decoder.rs index eaf82b3..1eee0fa 100644 --- a/crates/cpu/tests/simple_power_isa_decoder.rs +++ b/crates/cpu/tests/simple_power_isa_decoder.rs @@ -89,6 +89,41 @@ fn test_cases() -> Vec { false, ), )); + retval.push(insn_single( + "paddi 3, 4, 0x123456789, 0", + 0x06012345, + Some(0x38646789), + AddSubMOp::add_sub_i( + MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), + [ + MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, + MOpRegNum::const_zero().value, + ], + 0x123456789i64.cast_to_static::>(), + #[hdl(sim)] + OutputIntegerMode::Full64(), + false, + false, + false, + false, + ), + )); + retval.push(insn_single( + "paddi 3, 0, 0x123456789, 1", + 0x06112345, + Some(0x38606789), + AddSubMOp::add_sub_i( + MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), + [MOpRegNum::const_zero().value, MOpRegNum::const_zero().value], + 0x123456789i64.cast_to_static::>(), + #[hdl(sim)] + OutputIntegerMode::Full64(), + false, + false, + false, + true, + ), + )); retval.push(insn_single( "addis 3, 4, 0x1234", 0x3C641234, @@ -172,6 +207,54 @@ fn test_cases() -> Vec { false, ), )); + retval.push(insn_single( + "subf. 3, 4, 5", + 0x7c642851, + None, + AddSubMOp::add_sub( + MOpDestReg::new_sim( + &[MOpRegNum::power_isa_gpr_reg_num(3)], + &[MOpRegNum::POWER_ISA_CR_0_REG_NUM], + ), + [ + MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, + MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, + MOpRegNum::const_zero().value, + ], + 0.cast_to_static::>(), + #[hdl(sim)] + OutputIntegerMode::Full64(), + true, + false, + true, + false, + ), + )); + retval.push(insn_single( + "subfic 3, 4, 0x1234", + 0x20641234, + None, + AddSubMOp::add_sub_i( + MOpDestReg::new_sim( + &[ + MOpRegNum::power_isa_gpr_reg_num(3), + MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM, + ], + &[], + ), + [ + MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, + MOpRegNum::const_zero().value, + ], + 0x1234.cast_to_static::>(), + #[hdl(sim)] + OutputIntegerMode::Full64(), + true, + false, + true, + false, + ), + )); retval.push(insn_single( "addc. 3, 4, 5", 0x7c642815, @@ -198,6 +281,211 @@ fn test_cases() -> Vec { false, ), )); + retval.push(insn_single( + "subfc. 3, 4, 5", + 0x7c642811, + None, + AddSubMOp::add_sub( + MOpDestReg::new_sim( + &[ + MOpRegNum::power_isa_gpr_reg_num(3), + MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM, + ], + &[MOpRegNum::POWER_ISA_CR_0_REG_NUM], + ), + [ + MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, + MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, + MOpRegNum::const_zero().value, + ], + 0.cast_to_static::>(), + #[hdl(sim)] + OutputIntegerMode::Full64(), + true, + false, + true, + false, + ), + )); + retval.push(insn_single( + "adde. 3, 4, 5", + 0x7c642915, + None, + AddSubMOp::add_sub( + MOpDestReg::new_sim( + &[ + MOpRegNum::power_isa_gpr_reg_num(3), + MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM, + ], + &[MOpRegNum::POWER_ISA_CR_0_REG_NUM], + ), + [ + MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, + MOpRegNum::power_isa_xer_ca_ca32_reg().value, + MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, + ], + 0.cast_to_static::>(), + #[hdl(sim)] + OutputIntegerMode::Full64(), + false, + true, + false, + false, + ), + )); + retval.push(insn_single( + "subfe. 3, 4, 5", + 0x7c642911, + None, + AddSubMOp::add_sub( + MOpDestReg::new_sim( + &[ + MOpRegNum::power_isa_gpr_reg_num(3), + MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM, + ], + &[MOpRegNum::POWER_ISA_CR_0_REG_NUM], + ), + [ + MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, + MOpRegNum::power_isa_xer_ca_ca32_reg().value, + MOpRegNum::power_isa_gpr_reg(5_hdl_u5).value, + ], + 0.cast_to_static::>(), + #[hdl(sim)] + OutputIntegerMode::Full64(), + true, + true, + false, + false, + ), + )); + retval.push(insn_single( + "addme. 3, 4", + 0x7c6401d5, + None, + AddSubMOp::add_sub( + MOpDestReg::new_sim( + &[ + MOpRegNum::power_isa_gpr_reg_num(3), + MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM, + ], + &[MOpRegNum::POWER_ISA_CR_0_REG_NUM], + ), + [ + MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, + MOpRegNum::power_isa_xer_ca_ca32_reg().value, + MOpRegNum::const_zero().value, + ], + (-1i8).cast_to_static::>(), + #[hdl(sim)] + OutputIntegerMode::Full64(), + false, + true, + false, + false, + ), + )); + retval.push(insn_single( + "subfme. 3, 4", + 0x7c6401d1, + None, + AddSubMOp::add_sub( + MOpDestReg::new_sim( + &[ + MOpRegNum::power_isa_gpr_reg_num(3), + MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM, + ], + &[MOpRegNum::POWER_ISA_CR_0_REG_NUM], + ), + [ + MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, + MOpRegNum::power_isa_xer_ca_ca32_reg().value, + MOpRegNum::const_zero().value, + ], + (-1i8).cast_to_static::>(), + #[hdl(sim)] + OutputIntegerMode::Full64(), + true, + true, + false, + false, + ), + )); + retval.push(insn_single( + "addze. 3, 4", + 0x7c640195, + None, + AddSubMOp::add_sub( + MOpDestReg::new_sim( + &[ + MOpRegNum::power_isa_gpr_reg_num(3), + MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM, + ], + &[MOpRegNum::POWER_ISA_CR_0_REG_NUM], + ), + [ + MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, + MOpRegNum::power_isa_xer_ca_ca32_reg().value, + MOpRegNum::const_zero().value, + ], + 0.cast_to_static::>(), + #[hdl(sim)] + OutputIntegerMode::Full64(), + false, + true, + false, + false, + ), + )); + retval.push(insn_single( + "subfze. 3, 4", + 0x7c640191, + None, + AddSubMOp::add_sub( + MOpDestReg::new_sim( + &[ + MOpRegNum::power_isa_gpr_reg_num(3), + MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM, + ], + &[MOpRegNum::POWER_ISA_CR_0_REG_NUM], + ), + [ + MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, + MOpRegNum::power_isa_xer_ca_ca32_reg().value, + MOpRegNum::const_zero().value, + ], + 0.cast_to_static::>(), + #[hdl(sim)] + OutputIntegerMode::Full64(), + true, + true, + false, + false, + ), + )); + retval.push(insn_single( + "neg. 3, 4", + 0x7c6400d1, + None, + AddSubMOp::add_sub( + MOpDestReg::new_sim( + &[MOpRegNum::power_isa_gpr_reg_num(3)], + &[MOpRegNum::POWER_ISA_CR_0_REG_NUM], + ), + [ + MOpRegNum::power_isa_gpr_reg(4_hdl_u5).value, + MOpRegNum::const_zero().value, + MOpRegNum::const_zero().value, + ], + 0.cast_to_static::>(), + #[hdl(sim)] + OutputIntegerMode::Full64(), + true, + false, + true, + false, + ), + )); retval } @@ -349,7 +637,7 @@ fn test_decode_insn() { ); assert!( expected == output, - "test_case={test_case:#?}\noutput={output}" + "test_case={test_case:#?}\noutput={output}\nexpected={expected}" ); } let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();