From 7fc205e5833f92f0318923a16de0b73ad62540ba Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 29 May 2026 01:31:29 -0700
Subject: [PATCH] ArrayVec::map: actually connect to all output elements

---
 crates/cpu/src/util/array_vec.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/crates/cpu/src/util/array_vec.rs b/crates/cpu/src/util/array_vec.rs
index b4ac8f0..9fcb4fb 100644
--- a/crates/cpu/src/util/array_vec.rs
+++ b/crates/cpu/src/util/array_vec.rs
@@ -226,6 +226,10 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
         #[hdl]
         let mapped_array_vec = wire(this.ty().mapped_ty(new_element_ty));
         connect(mapped_array_vec.len, this.len);
+        connect(
+            mapped_array_vec.elements,
+            mapped_array_vec.ty().elements.uninit(),
+        );
         Self::for_each(this, |index, element| {
             connect(mapped_array_vec[index], f(index, element));
         });